drivers/gpu/drm/amd/amdgpu/nv.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include <drm/amdgpu_drm.h>
  29
  30 #include "amdgpu.h"
  31 #include "amdgpu_atombios.h"
  32 #include "amdgpu_ih.h"
  33 #include "amdgpu_uvd.h"
  34 #include "amdgpu_vce.h"
  35 #include "amdgpu_ucode.h"
  36 #include "amdgpu_psp.h"
  37 #include "atom.h"
  38 #include "amd_pcie.h"
  39
  40 #include "gc/gc_10_1_0_offset.h"
  41 #include "gc/gc_10_1_0_sh_mask.h"
  42 #include "mp/mp_11_0_offset.h"
  43
  44 #include "soc15.h"
  45 #include "soc15_common.h"
  46 #include "gmc_v10_0.h"
  47 #include "gfxhub_v2_0.h"
  48 #include "mmhub_v2_0.h"
  49 #include "nbio_v2_3.h"
  50 #include "nbio_v7_2.h"
  51 #include "hdp_v5_0.h"
  52 #include "nv.h"
  53 #include "navi10_ih.h"
  54 #include "gfx_v10_0.h"
  55 #include "sdma_v5_0.h"
  56 #include "sdma_v5_2.h"
  57 #include "vcn_v2_0.h"
  58 #include "jpeg_v2_0.h"
  59 #include "vcn_v3_0.h"
  60 #include "jpeg_v3_0.h"
  61 #include "amdgpu_vkms.h"
  62 #include "mes_v10_1.h"
  63 #include "mxgpu_nv.h"
  64 #include "smuio_v11_0.h"
  65 #include "smuio_v11_0_6.h"
  66
  67 static const struct amd_ip_funcs nv_common_ip_funcs;
  68
  69 /* Navi */
  70 static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] =
  71 {
  72         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
  73         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
  74 };
  75
  76 static const struct amdgpu_video_codecs nv_video_codecs_encode =
  77 {
  78         .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array),
  79         .codec_array = nv_video_codecs_encode_array,
  80 };
  81
  82 /* Navi1x */
  83 static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] =
  84 {
  85         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},
  86         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},
  87         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
  88         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},
  89         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
  90         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
  91         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
  92 };
  93
  94 static const struct amdgpu_video_codecs nv_video_codecs_decode =
  95 {
  96         .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array),
  97         .codec_array = nv_video_codecs_decode_array,
  98 };
  99
 100 /* Sienna Cichlid */
 101 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] =
 102 {
 103         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},
 104         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},
 105         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
 106         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},
 107         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 108         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
 109         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 110         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
 111 };
 112
 113 static const struct amdgpu_video_codecs sc_video_codecs_decode =
 114 {
 115         .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array),
 116         .codec_array = sc_video_codecs_decode_array,
 117 };
 118
 119 /* SRIOV Sienna Cichlid, not const since data is controlled by host */
 120 static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] =
 121 {
 122         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
 123         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
 124 };
 125
 126 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array[] =
 127 {
 128         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},
 129         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},
 130         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
 131         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},
 132         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 133         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
 134         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 135         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
 136 };
 137
 138 static struct amdgpu_video_codecs sriov_sc_video_codecs_encode =
 139 {
 140         .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
 141         .codec_array = sriov_sc_video_codecs_encode_array,
 142 };
 143
 144 static struct amdgpu_video_codecs sriov_sc_video_codecs_decode =
 145 {
 146         .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array),
 147         .codec_array = sriov_sc_video_codecs_decode_array,
 148 };
 149
 150 /* Beige Goby*/
 151 static const struct amdgpu_video_codec_info bg_video_codecs_decode_array[] = {
 152         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
 153         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 154         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 155 };
 156
 157 static const struct amdgpu_video_codecs bg_video_codecs_decode = {
 158         .codec_count = ARRAY_SIZE(bg_video_codecs_decode_array),
 159         .codec_array = bg_video_codecs_decode_array,
 160 };
 161
 162 static const struct amdgpu_video_codecs bg_video_codecs_encode = {
 163         .codec_count = 0,
 164         .codec_array = NULL,
 165 };
 166
 167 /* Yellow Carp*/
 168 static const struct amdgpu_video_codec_info yc_video_codecs_decode_array[] = {
 169         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
 170         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 171         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 172         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
 173 };
 174
 175 static const struct amdgpu_video_codecs yc_video_codecs_decode = {
 176         .codec_count = ARRAY_SIZE(yc_video_codecs_decode_array),
 177         .codec_array = yc_video_codecs_decode_array,
 178 };
 179
 180 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
 181                                  const struct amdgpu_video_codecs **codecs)
 182 {
 183         switch (adev->ip_versions[UVD_HWIP][0]) {
 184         case IP_VERSION(3, 0, 0):
 185                 if (amdgpu_sriov_vf(adev)) {
 186                         if (encode)
 187                                 *codecs = &sriov_sc_video_codecs_encode;
 188                         else
 189                                 *codecs = &sriov_sc_video_codecs_decode;
 190                 } else {
 191                         if (encode)
 192                                 *codecs = &nv_video_codecs_encode;
 193                         else
 194                                 *codecs = &sc_video_codecs_decode;
 195                 }
 196                 return 0;
 197         case IP_VERSION(3, 0, 16):
 198         case IP_VERSION(3, 0, 2):
 199                 if (encode)
 200                         *codecs = &nv_video_codecs_encode;
 201                 else
 202                         *codecs = &sc_video_codecs_decode;
 203                 return 0;
 204         case IP_VERSION(3, 1, 1):
 205                 if (encode)
 206                         *codecs = &nv_video_codecs_encode;
 207                 else
 208                         *codecs = &yc_video_codecs_decode;
 209                 return 0;
 210         case IP_VERSION(3, 0, 33):
 211                 if (encode)
 212                         *codecs = &bg_video_codecs_encode;
 213                 else
 214                         *codecs = &bg_video_codecs_decode;
 215                 return 0;
 216         case IP_VERSION(2, 0, 0):
 217         case IP_VERSION(2, 0, 2):
 218                 if (encode)
 219                         *codecs = &nv_video_codecs_encode;
 220                 else
 221                         *codecs = &nv_video_codecs_decode;
 222                 return 0;
 223         default:
 224                 return -EINVAL;
 225         }
 226 }
 227
 228 /*
 229  * Indirect registers accessor
 230  */
 231 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg)
 232 {
 233         unsigned long address, data;
 234         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 235         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 236
 237         return amdgpu_device_indirect_rreg(adev, address, data, reg);
 238 }
 239
 240 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 241 {
 242         unsigned long address, data;
 243
 244         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 245         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 246
 247         amdgpu_device_indirect_wreg(adev, address, data, reg, v);
 248 }
 249
 250 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
 251 {
 252         unsigned long address, data;
 253         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 254         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 255
 256         return amdgpu_device_indirect_rreg64(adev, address, data, reg);
 257 }
 258
 259 static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg)
 260 {
 261         unsigned long flags, address, data;
 262         u32 r;
 263         address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
 264         data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
 265
 266         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 267         WREG32(address, reg * 4);
 268         (void)RREG32(address);
 269         r = RREG32(data);
 270         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 271         return r;
 272 }
 273
 274 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
 275 {
 276         unsigned long address, data;
 277
 278         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 279         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 280
 281         amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
 282 }
 283
 284 static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 285 {
 286         unsigned long flags, address, data;
 287
 288         address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
 289         data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
 290
 291         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 292         WREG32(address, reg * 4);
 293         (void)RREG32(address);
 294         WREG32(data, v);
 295         (void)RREG32(data);
 296         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 297 }
 298
 299 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
 300 {
 301         unsigned long flags, address, data;
 302         u32 r;
 303
 304         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 305         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 306
 307         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 308         WREG32(address, (reg));
 309         r = RREG32(data);
 310         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 311         return r;
 312 }
 313
 314 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 315 {
 316         unsigned long flags, address, data;
 317
 318         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 319         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 320
 321         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 322         WREG32(address, (reg));
 323         WREG32(data, (v));
 324         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 325 }
 326
 327 static u32 nv_get_config_memsize(struct amdgpu_device *adev)
 328 {
 329         return adev->nbio.funcs->get_memsize(adev);
 330 }
 331
 332 static u32 nv_get_xclk(struct amdgpu_device *adev)
 333 {
 334         return adev->clock.spll.reference_freq;
 335 }
 336
 337
 338 void nv_grbm_select(struct amdgpu_device *adev,
 339                      u32 me, u32 pipe, u32 queue, u32 vmid)
 340 {
 341         u32 grbm_gfx_cntl = 0;
 342         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 343         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 344         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 345         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 346
 347         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
 348 }
 349
 350 static void nv_vga_set_state(struct amdgpu_device *adev, bool state)
 351 {
 352         /* todo */
 353 }
 354
 355 static bool nv_read_disabled_bios(struct amdgpu_device *adev)
 356 {
 357         /* todo */
 358         return false;
 359 }
 360
 361 static bool nv_read_bios_from_rom(struct amdgpu_device *adev,
 362                                   u8 *bios, u32 length_bytes)
 363 {
 364         u32 *dw_ptr;
 365         u32 i, length_dw;
 366         u32 rom_index_offset, rom_data_offset;
 367
 368         if (bios == NULL)
 369                 return false;
 370         if (length_bytes == 0)
 371                 return false;
 372         /* APU vbios image is part of sbios image */
 373         if (adev->flags & AMD_IS_APU)
 374                 return false;
 375
 376         dw_ptr = (u32 *)bios;
 377         length_dw = ALIGN(length_bytes, 4) / 4;
 378
 379         rom_index_offset =
 380                 adev->smuio.funcs->get_rom_index_offset(adev);
 381         rom_data_offset =
 382                 adev->smuio.funcs->get_rom_data_offset(adev);
 383
 384         /* set rom index to 0 */
 385         WREG32(rom_index_offset, 0);
 386         /* read out the rom data */
 387         for (i = 0; i < length_dw; i++)
 388                 dw_ptr[i] = RREG32(rom_data_offset);
 389
 390         return true;
 391 }
 392
 393 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {
 394         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
 395         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
 396         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
 397         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
 398         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
 399         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
 400         { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
 401         { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
 402         { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
 403         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
 404         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
 405         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
 406         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
 407         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
 408         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
 409         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
 410         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 411         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 412         { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
 413 };
 414
 415 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 416                                          u32 sh_num, u32 reg_offset)
 417 {
 418         uint32_t val;
 419
 420         mutex_lock(&adev->grbm_idx_mutex);
 421         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 422                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 423
 424         val = RREG32(reg_offset);
 425
 426         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 427                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 428         mutex_unlock(&adev->grbm_idx_mutex);
 429         return val;
 430 }
 431
 432 static uint32_t nv_get_register_value(struct amdgpu_device *adev,
 433                                       bool indexed, u32 se_num,
 434                                       u32 sh_num, u32 reg_offset)
 435 {
 436         if (indexed) {
 437                 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
 438         } else {
 439                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
 440                         return adev->gfx.config.gb_addr_config;
 441                 return RREG32(reg_offset);
 442         }
 443 }
 444
 445 static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
 446                             u32 sh_num, u32 reg_offset, u32 *value)
 447 {
 448         uint32_t i;
 449         struct soc15_allowed_register_entry  *en;
 450
 451         *value = 0;
 452         for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) {
 453                 en = &nv_allowed_read_registers[i];
 454                 if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */
 455                     reg_offset !=
 456                     (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
 457                         continue;
 458
 459                 *value = nv_get_register_value(adev,
 460                                                nv_allowed_read_registers[i].grbm_indexed,
 461                                                se_num, sh_num, reg_offset);
 462                 return 0;
 463         }
 464         return -EINVAL;
 465 }
 466
 467 static int nv_asic_mode2_reset(struct amdgpu_device *adev)
 468 {
 469         u32 i;
 470         int ret = 0;
 471
 472         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 473
 474         /* disable BM */
 475         pci_clear_master(adev->pdev);
 476
 477         amdgpu_device_cache_pci_state(adev->pdev);
 478
 479         ret = amdgpu_dpm_mode2_reset(adev);
 480         if (ret)
 481                 dev_err(adev->dev, "GPU mode2 reset failed\n");
 482
 483         amdgpu_device_load_pci_state(adev->pdev);
 484
 485         /* wait for asic to come out of reset */
 486         for (i = 0; i < adev->usec_timeout; i++) {
 487                 u32 memsize = adev->nbio.funcs->get_memsize(adev);
 488
 489                 if (memsize != 0xffffffff)
 490                         break;
 491                 udelay(1);
 492         }
 493
 494         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 495
 496         return ret;
 497 }
 498
 499 static enum amd_reset_method
 500 nv_asic_reset_method(struct amdgpu_device *adev)
 501 {
 502         if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
 503             amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
 504             amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
 505             amdgpu_reset_method == AMD_RESET_METHOD_PCI)
 506                 return amdgpu_reset_method;
 507
 508         if (amdgpu_reset_method != -1)
 509                 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
 510                                   amdgpu_reset_method);
 511
 512         switch (adev->ip_versions[MP1_HWIP][0]) {
 513         case IP_VERSION(11, 5, 0):
 514         case IP_VERSION(13, 0, 1):
 515         case IP_VERSION(13, 0, 3):
 516                 return AMD_RESET_METHOD_MODE2;
 517         case IP_VERSION(11, 0, 7):
 518         case IP_VERSION(11, 0, 11):
 519         case IP_VERSION(11, 0, 12):
 520         case IP_VERSION(11, 0, 13):
 521                 return AMD_RESET_METHOD_MODE1;
 522         default:
 523                 if (amdgpu_dpm_is_baco_supported(adev))
 524                         return AMD_RESET_METHOD_BACO;
 525                 else
 526                         return AMD_RESET_METHOD_MODE1;
 527         }
 528 }
 529
 530 static int nv_asic_reset(struct amdgpu_device *adev)
 531 {
 532         int ret = 0;
 533
 534         switch (nv_asic_reset_method(adev)) {
 535         case AMD_RESET_METHOD_PCI:
 536                 dev_info(adev->dev, "PCI reset\n");
 537                 ret = amdgpu_device_pci_reset(adev);
 538                 break;
 539         case AMD_RESET_METHOD_BACO:
 540                 dev_info(adev->dev, "BACO reset\n");
 541                 ret = amdgpu_dpm_baco_reset(adev);
 542                 break;
 543         case AMD_RESET_METHOD_MODE2:
 544                 dev_info(adev->dev, "MODE2 reset\n");
 545                 ret = nv_asic_mode2_reset(adev);
 546                 break;
 547         default:
 548                 dev_info(adev->dev, "MODE1 reset\n");
 549                 ret = amdgpu_device_mode1_reset(adev);
 550                 break;
 551         }
 552
 553         return ret;
 554 }
 555
 556 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 557 {
 558         /* todo */
 559         return 0;
 560 }
 561
 562 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 563 {
 564         /* todo */
 565         return 0;
 566 }
 567
 568 static void nv_pcie_gen3_enable(struct amdgpu_device *adev)
 569 {
 570         if (pci_is_root_bus(adev->pdev->bus))
 571                 return;
 572
 573         if (amdgpu_pcie_gen2 == 0)
 574                 return;
 575
 576         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 577                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 578                 return;
 579
 580         /* todo */
 581 }
 582
 583 static void nv_program_aspm(struct amdgpu_device *adev)
 584 {
 585         if (!amdgpu_aspm)
 586                 return;
 587
 588         if (!(adev->flags & AMD_IS_APU) &&
 589             (adev->nbio.funcs->program_aspm))
 590                 adev->nbio.funcs->program_aspm(adev);
 591
 592 }
 593
 594 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev,
 595                                         bool enable)
 596 {
 597         adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
 598         adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
 599 }
 600
 601 const struct amdgpu_ip_block_version nv_common_ip_block =
 602 {
 603         .type = AMD_IP_BLOCK_TYPE_COMMON,
 604         .major = 1,
 605         .minor = 0,
 606         .rev = 0,
 607         .funcs = &nv_common_ip_funcs,
 608 };
 609
 610 void nv_set_virt_ops(struct amdgpu_device *adev)
 611 {
 612         adev->virt.ops = &xgpu_nv_virt_ops;
 613 }
 614
 615 static uint32_t nv_get_rev_id(struct amdgpu_device *adev)
 616 {
 617         return adev->nbio.funcs->get_rev_id(adev);
 618 }
 619
 620 static bool nv_need_full_reset(struct amdgpu_device *adev)
 621 {
 622         return true;
 623 }
 624
 625 static bool nv_need_reset_on_init(struct amdgpu_device *adev)
 626 {
 627         u32 sol_reg;
 628
 629         if (adev->flags & AMD_IS_APU)
 630                 return false;
 631
 632         /* Check sOS sign of life register to confirm sys driver and sOS
 633          * are already been loaded.
 634          */
 635         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 636         if (sol_reg)
 637                 return true;
 638
 639         return false;
 640 }
 641
 642 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev)
 643 {
 644
 645         /* TODO
 646          * dummy implement for pcie_replay_count sysfs interface
 647          * */
 648
 649         return 0;
 650 }
 651
 652 static void nv_init_doorbell_index(struct amdgpu_device *adev)
 653 {
 654         adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
 655         adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
 656         adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
 657         adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
 658         adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
 659         adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
 660         adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
 661         adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
 662         adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
 663         adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
 664         adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
 665         adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
 666         adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
 667         adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING;
 668         adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
 669         adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
 670         adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2;
 671         adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3;
 672         adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
 673         adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
 674         adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
 675         adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
 676         adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
 677         adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
 678         adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
 679
 680         adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
 681         adev->doorbell_index.sdma_doorbell_range = 20;
 682 }
 683
 684 static void nv_pre_asic_init(struct amdgpu_device *adev)
 685 {
 686 }
 687
 688 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev,
 689                                        bool enter)
 690 {
 691         if (enter)
 692                 amdgpu_gfx_rlc_enter_safe_mode(adev);
 693         else
 694                 amdgpu_gfx_rlc_exit_safe_mode(adev);
 695
 696         if (adev->gfx.funcs->update_perfmon_mgcg)
 697                 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
 698
 699         if (!(adev->flags & AMD_IS_APU) &&
 700             (adev->nbio.funcs->enable_aspm))
 701                 adev->nbio.funcs->enable_aspm(adev, !enter);
 702
 703         return 0;
 704 }
 705
 706 static const struct amdgpu_asic_funcs nv_asic_funcs =
 707 {
 708         .read_disabled_bios = &nv_read_disabled_bios,
 709         .read_bios_from_rom = &nv_read_bios_from_rom,
 710         .read_register = &nv_read_register,
 711         .reset = &nv_asic_reset,
 712         .reset_method = &nv_asic_reset_method,
 713         .set_vga_state = &nv_vga_set_state,
 714         .get_xclk = &nv_get_xclk,
 715         .set_uvd_clocks = &nv_set_uvd_clocks,
 716         .set_vce_clocks = &nv_set_vce_clocks,
 717         .get_config_memsize = &nv_get_config_memsize,
 718         .init_doorbell_index = &nv_init_doorbell_index,
 719         .need_full_reset = &nv_need_full_reset,
 720         .need_reset_on_init = &nv_need_reset_on_init,
 721         .get_pcie_replay_count = &nv_get_pcie_replay_count,
 722         .supports_baco = &amdgpu_dpm_is_baco_supported,
 723         .pre_asic_init = &nv_pre_asic_init,
 724         .update_umd_stable_pstate = &nv_update_umd_stable_pstate,
 725         .query_video_codecs = &nv_query_video_codecs,
 726 };
 727
 728 static int nv_common_early_init(void *handle)
 729 {
 730 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
 731         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 732
 733         adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
 734         adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
 735         adev->smc_rreg = NULL;
 736         adev->smc_wreg = NULL;
 737         adev->pcie_rreg = &nv_pcie_rreg;
 738         adev->pcie_wreg = &nv_pcie_wreg;
 739         adev->pcie_rreg64 = &nv_pcie_rreg64;
 740         adev->pcie_wreg64 = &nv_pcie_wreg64;
 741         adev->pciep_rreg = &nv_pcie_port_rreg;
 742         adev->pciep_wreg = &nv_pcie_port_wreg;
 743
 744         /* TODO: will add them during VCN v2 implementation */
 745         adev->uvd_ctx_rreg = NULL;
 746         adev->uvd_ctx_wreg = NULL;
 747
 748         adev->didt_rreg = &nv_didt_rreg;
 749         adev->didt_wreg = &nv_didt_wreg;
 750
 751         adev->asic_funcs = &nv_asic_funcs;
 752
 753         adev->rev_id = nv_get_rev_id(adev);
 754         adev->external_rev_id = 0xff;
 755         /* TODO: split the GC and PG flags based on the relevant IP version for which
 756          * they are relevant.
 757          */
 758         switch (adev->ip_versions[GC_HWIP][0]) {
 759         case IP_VERSION(10, 1, 10):
 760                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 761                         AMD_CG_SUPPORT_GFX_CGCG |
 762                         AMD_CG_SUPPORT_IH_CG |
 763                         AMD_CG_SUPPORT_HDP_MGCG |
 764                         AMD_CG_SUPPORT_HDP_LS |
 765                         AMD_CG_SUPPORT_SDMA_MGCG |
 766                         AMD_CG_SUPPORT_SDMA_LS |
 767                         AMD_CG_SUPPORT_MC_MGCG |
 768                         AMD_CG_SUPPORT_MC_LS |
 769                         AMD_CG_SUPPORT_ATHUB_MGCG |
 770                         AMD_CG_SUPPORT_ATHUB_LS |
 771                         AMD_CG_SUPPORT_VCN_MGCG |
 772                         AMD_CG_SUPPORT_JPEG_MGCG |
 773                         AMD_CG_SUPPORT_BIF_MGCG |
 774                         AMD_CG_SUPPORT_BIF_LS;
 775                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 776                         AMD_PG_SUPPORT_VCN_DPG |
 777                         AMD_PG_SUPPORT_JPEG |
 778                         AMD_PG_SUPPORT_ATHUB;
 779                 adev->external_rev_id = adev->rev_id + 0x1;
 780                 break;
 781         case IP_VERSION(10, 1, 1):
 782                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 783                         AMD_CG_SUPPORT_GFX_CGCG |
 784                         AMD_CG_SUPPORT_IH_CG |
 785                         AMD_CG_SUPPORT_HDP_MGCG |
 786                         AMD_CG_SUPPORT_HDP_LS |
 787                         AMD_CG_SUPPORT_SDMA_MGCG |
 788                         AMD_CG_SUPPORT_SDMA_LS |
 789                         AMD_CG_SUPPORT_MC_MGCG |
 790                         AMD_CG_SUPPORT_MC_LS |
 791                         AMD_CG_SUPPORT_ATHUB_MGCG |
 792                         AMD_CG_SUPPORT_ATHUB_LS |
 793                         AMD_CG_SUPPORT_VCN_MGCG |
 794                         AMD_CG_SUPPORT_JPEG_MGCG |
 795                         AMD_CG_SUPPORT_BIF_MGCG |
 796                         AMD_CG_SUPPORT_BIF_LS;
 797                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 798                         AMD_PG_SUPPORT_JPEG |
 799                         AMD_PG_SUPPORT_VCN_DPG;
 800                 adev->external_rev_id = adev->rev_id + 20;
 801                 break;
 802         case IP_VERSION(10, 1, 2):
 803                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 804                         AMD_CG_SUPPORT_GFX_MGLS |
 805                         AMD_CG_SUPPORT_GFX_CGCG |
 806                         AMD_CG_SUPPORT_GFX_CP_LS |
 807                         AMD_CG_SUPPORT_GFX_RLC_LS |
 808                         AMD_CG_SUPPORT_IH_CG |
 809                         AMD_CG_SUPPORT_HDP_MGCG |
 810                         AMD_CG_SUPPORT_HDP_LS |
 811                         AMD_CG_SUPPORT_SDMA_MGCG |
 812                         AMD_CG_SUPPORT_SDMA_LS |
 813                         AMD_CG_SUPPORT_MC_MGCG |
 814                         AMD_CG_SUPPORT_MC_LS |
 815                         AMD_CG_SUPPORT_ATHUB_MGCG |
 816                         AMD_CG_SUPPORT_ATHUB_LS |
 817                         AMD_CG_SUPPORT_VCN_MGCG |
 818                         AMD_CG_SUPPORT_JPEG_MGCG;
 819                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 820                         AMD_PG_SUPPORT_VCN_DPG |
 821                         AMD_PG_SUPPORT_JPEG |
 822                         AMD_PG_SUPPORT_ATHUB;
 823                 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0,
 824                  * as a consequence, the rev_id and external_rev_id are wrong.
 825                  * workaround it by hardcoding rev_id to 0 (default value).
 826                  */
 827                 if (amdgpu_sriov_vf(adev))
 828                         adev->rev_id = 0;
 829                 adev->external_rev_id = adev->rev_id + 0xa;
 830                 break;
 831         case IP_VERSION(10, 3, 0):
 832                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 833                         AMD_CG_SUPPORT_GFX_CGCG |
 834                         AMD_CG_SUPPORT_GFX_CGLS |
 835                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 836                         AMD_CG_SUPPORT_MC_MGCG |
 837                         AMD_CG_SUPPORT_VCN_MGCG |
 838                         AMD_CG_SUPPORT_JPEG_MGCG |
 839                         AMD_CG_SUPPORT_HDP_MGCG |
 840                         AMD_CG_SUPPORT_HDP_LS |
 841                         AMD_CG_SUPPORT_IH_CG |
 842                         AMD_CG_SUPPORT_MC_LS;
 843                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 844                         AMD_PG_SUPPORT_VCN_DPG |
 845                         AMD_PG_SUPPORT_JPEG |
 846                         AMD_PG_SUPPORT_ATHUB |
 847                         AMD_PG_SUPPORT_MMHUB;
 848                 if (amdgpu_sriov_vf(adev)) {
 849                         /* hypervisor control CG and PG enablement */
 850                         adev->cg_flags = 0;
 851                         adev->pg_flags = 0;
 852                 }
 853                 adev->external_rev_id = adev->rev_id + 0x28;
 854                 break;
 855         case IP_VERSION(10, 3, 2):
 856                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 857                         AMD_CG_SUPPORT_GFX_CGCG |
 858                         AMD_CG_SUPPORT_GFX_CGLS |
 859                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 860                         AMD_CG_SUPPORT_VCN_MGCG |
 861                         AMD_CG_SUPPORT_JPEG_MGCG |
 862                         AMD_CG_SUPPORT_MC_MGCG |
 863                         AMD_CG_SUPPORT_MC_LS |
 864                         AMD_CG_SUPPORT_HDP_MGCG |
 865                         AMD_CG_SUPPORT_HDP_LS |
 866                         AMD_CG_SUPPORT_IH_CG;
 867                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 868                         AMD_PG_SUPPORT_VCN_DPG |
 869                         AMD_PG_SUPPORT_JPEG |
 870                         AMD_PG_SUPPORT_ATHUB |
 871                         AMD_PG_SUPPORT_MMHUB;
 872                 adev->external_rev_id = adev->rev_id + 0x32;
 873                 break;
 874         case IP_VERSION(10, 3, 1):
 875                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 876                         AMD_CG_SUPPORT_GFX_MGLS |
 877                         AMD_CG_SUPPORT_GFX_CP_LS |
 878                         AMD_CG_SUPPORT_GFX_RLC_LS |
 879                         AMD_CG_SUPPORT_GFX_CGCG |
 880                         AMD_CG_SUPPORT_GFX_CGLS |
 881                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 882                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 883                         AMD_CG_SUPPORT_MC_MGCG |
 884                         AMD_CG_SUPPORT_MC_LS |
 885                         AMD_CG_SUPPORT_GFX_FGCG |
 886                         AMD_CG_SUPPORT_VCN_MGCG |
 887                         AMD_CG_SUPPORT_SDMA_MGCG |
 888                         AMD_CG_SUPPORT_SDMA_LS |
 889                         AMD_CG_SUPPORT_JPEG_MGCG;
 890                 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
 891                         AMD_PG_SUPPORT_VCN |
 892                         AMD_PG_SUPPORT_VCN_DPG |
 893                         AMD_PG_SUPPORT_JPEG;
 894                 if (adev->apu_flags & AMD_APU_IS_VANGOGH)
 895                         adev->external_rev_id = adev->rev_id + 0x01;
 896                 break;
 897         case IP_VERSION(10, 3, 4):
 898                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 899                         AMD_CG_SUPPORT_GFX_CGCG |
 900                         AMD_CG_SUPPORT_GFX_CGLS |
 901                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 902                         AMD_CG_SUPPORT_VCN_MGCG |
 903                         AMD_CG_SUPPORT_JPEG_MGCG |
 904                         AMD_CG_SUPPORT_MC_MGCG |
 905                         AMD_CG_SUPPORT_MC_LS |
 906                         AMD_CG_SUPPORT_HDP_MGCG |
 907                         AMD_CG_SUPPORT_HDP_LS |
 908                         AMD_CG_SUPPORT_IH_CG;
 909                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 910                         AMD_PG_SUPPORT_VCN_DPG |
 911                         AMD_PG_SUPPORT_JPEG |
 912                         AMD_PG_SUPPORT_ATHUB |
 913                         AMD_PG_SUPPORT_MMHUB;
 914                 adev->external_rev_id = adev->rev_id + 0x3c;
 915                 break;
 916         case IP_VERSION(10, 3, 5):
 917                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 918                         AMD_CG_SUPPORT_GFX_CGCG |
 919                         AMD_CG_SUPPORT_GFX_CGLS |
 920                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 921                         AMD_CG_SUPPORT_MC_MGCG |
 922                         AMD_CG_SUPPORT_MC_LS |
 923                         AMD_CG_SUPPORT_HDP_MGCG |
 924                         AMD_CG_SUPPORT_HDP_LS |
 925                         AMD_CG_SUPPORT_IH_CG |
 926                         AMD_CG_SUPPORT_VCN_MGCG;
 927                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 928                         AMD_PG_SUPPORT_VCN_DPG |
 929                         AMD_PG_SUPPORT_ATHUB |
 930                         AMD_PG_SUPPORT_MMHUB;
 931                 adev->external_rev_id = adev->rev_id + 0x46;
 932                 break;
 933         case IP_VERSION(10, 3, 3):
 934                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 935                         AMD_CG_SUPPORT_GFX_MGLS |
 936                         AMD_CG_SUPPORT_GFX_CGCG |
 937                         AMD_CG_SUPPORT_GFX_CGLS |
 938                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 939                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 940                         AMD_CG_SUPPORT_GFX_RLC_LS |
 941                         AMD_CG_SUPPORT_GFX_CP_LS |
 942                         AMD_CG_SUPPORT_GFX_FGCG |
 943                         AMD_CG_SUPPORT_MC_MGCG |
 944                         AMD_CG_SUPPORT_MC_LS |
 945                         AMD_CG_SUPPORT_SDMA_LS |
 946                         AMD_CG_SUPPORT_HDP_MGCG |
 947                         AMD_CG_SUPPORT_HDP_LS |
 948                         AMD_CG_SUPPORT_ATHUB_MGCG |
 949                         AMD_CG_SUPPORT_ATHUB_LS |
 950                         AMD_CG_SUPPORT_IH_CG |
 951                         AMD_CG_SUPPORT_VCN_MGCG |
 952                         AMD_CG_SUPPORT_JPEG_MGCG;
 953                 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
 954                         AMD_PG_SUPPORT_VCN |
 955                         AMD_PG_SUPPORT_VCN_DPG |
 956                         AMD_PG_SUPPORT_JPEG;
 957                 if (adev->pdev->device == 0x1681)
 958                         adev->external_rev_id = 0x20;
 959                 else
 960                         adev->external_rev_id = adev->rev_id + 0x01;
 961                 break;
 962         case IP_VERSION(10, 1, 3):
 963                 adev->cg_flags = 0;
 964                 adev->pg_flags = 0;
 965                 adev->external_rev_id = adev->rev_id + 0x82;
 966                 break;
 967         default:
 968                 /* FIXME: not supported yet */
 969                 return -EINVAL;
 970         }
 971
 972         if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
 973                 adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN |
 974                                     AMD_PG_SUPPORT_VCN_DPG |
 975                                     AMD_PG_SUPPORT_JPEG);
 976
 977         if (amdgpu_sriov_vf(adev)) {
 978                 amdgpu_virt_init_setting(adev);
 979                 xgpu_nv_mailbox_set_irq_funcs(adev);
 980         }
 981
 982         return 0;
 983 }
 984
 985 static int nv_common_late_init(void *handle)
 986 {
 987         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 988
 989         if (amdgpu_sriov_vf(adev)) {
 990                 xgpu_nv_mailbox_get_irq(adev);
 991                 amdgpu_virt_update_sriov_video_codec(adev,
 992                                 sriov_sc_video_codecs_encode_array, ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
 993                                 sriov_sc_video_codecs_decode_array, ARRAY_SIZE(sriov_sc_video_codecs_decode_array));
 994         }
 995
 996         return 0;
 997 }
 998
 999 static int nv_common_sw_init(void *handle)
1000 {
1001         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1002
1003         if (amdgpu_sriov_vf(adev))
1004                 xgpu_nv_mailbox_add_irq_id(adev);
1005
1006         return 0;
1007 }
1008
1009 static int nv_common_sw_fini(void *handle)
1010 {
1011         return 0;
1012 }
1013
1014 static int nv_common_hw_init(void *handle)
1015 {
1016         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1017
1018         if (adev->nbio.funcs->apply_lc_spc_mode_wa)
1019                 adev->nbio.funcs->apply_lc_spc_mode_wa(adev);
1020
1021         if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa)
1022                 adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev);
1023
1024         /* enable pcie gen2/3 link */
1025         nv_pcie_gen3_enable(adev);
1026         /* enable aspm */
1027         nv_program_aspm(adev);
1028         /* setup nbio registers */
1029         adev->nbio.funcs->init_registers(adev);
1030         /* remap HDP registers to a hole in mmio space,
1031          * for the purpose of expose those registers
1032          * to process space
1033          */
1034         if (adev->nbio.funcs->remap_hdp_registers)
1035                 adev->nbio.funcs->remap_hdp_registers(adev);
1036         /* enable the doorbell aperture */
1037         nv_enable_doorbell_aperture(adev, true);
1038
1039         return 0;
1040 }
1041
1042 static int nv_common_hw_fini(void *handle)
1043 {
1044         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1045
1046         /* disable the doorbell aperture */
1047         nv_enable_doorbell_aperture(adev, false);
1048
1049         return 0;
1050 }
1051
1052 static int nv_common_suspend(void *handle)
1053 {
1054         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1055
1056         return nv_common_hw_fini(adev);
1057 }
1058
1059 static int nv_common_resume(void *handle)
1060 {
1061         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1062
1063         return nv_common_hw_init(adev);
1064 }
1065
1066 static bool nv_common_is_idle(void *handle)
1067 {
1068         return true;
1069 }
1070
1071 static int nv_common_wait_for_idle(void *handle)
1072 {
1073         return 0;
1074 }
1075
1076 static int nv_common_soft_reset(void *handle)
1077 {
1078         return 0;
1079 }
1080
1081 static int nv_common_set_clockgating_state(void *handle,
1082                                            enum amd_clockgating_state state)
1083 {
1084         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1085
1086         if (amdgpu_sriov_vf(adev))
1087                 return 0;
1088
1089         switch (adev->ip_versions[NBIO_HWIP][0]) {
1090         case IP_VERSION(2, 3, 0):
1091         case IP_VERSION(2, 3, 1):
1092         case IP_VERSION(2, 3, 2):
1093         case IP_VERSION(3, 3, 0):
1094         case IP_VERSION(3, 3, 1):
1095         case IP_VERSION(3, 3, 2):
1096         case IP_VERSION(3, 3, 3):
1097                 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1098                                 state == AMD_CG_STATE_GATE);
1099                 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1100                                 state == AMD_CG_STATE_GATE);
1101                 adev->hdp.funcs->update_clock_gating(adev,
1102                                 state == AMD_CG_STATE_GATE);
1103                 adev->smuio.funcs->update_rom_clock_gating(adev,
1104                                 state == AMD_CG_STATE_GATE);
1105                 break;
1106         default:
1107                 break;
1108         }
1109         return 0;
1110 }
1111
1112 static int nv_common_set_powergating_state(void *handle,
1113                                            enum amd_powergating_state state)
1114 {
1115         /* TODO */
1116         return 0;
1117 }
1118
1119 static void nv_common_get_clockgating_state(void *handle, u32 *flags)
1120 {
1121         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1122
1123         if (amdgpu_sriov_vf(adev))
1124                 *flags = 0;
1125
1126         adev->nbio.funcs->get_clockgating_state(adev, flags);
1127
1128         adev->hdp.funcs->get_clock_gating_state(adev, flags);
1129
1130         adev->smuio.funcs->get_clock_gating_state(adev, flags);
1131
1132         return;
1133 }
1134
1135 static const struct amd_ip_funcs nv_common_ip_funcs = {
1136         .name = "nv_common",
1137         .early_init = nv_common_early_init,
1138         .late_init = nv_common_late_init,
1139         .sw_init = nv_common_sw_init,
1140         .sw_fini = nv_common_sw_fini,
1141         .hw_init = nv_common_hw_init,
1142         .hw_fini = nv_common_hw_fini,
1143         .suspend = nv_common_suspend,
1144         .resume = nv_common_resume,
1145         .is_idle = nv_common_is_idle,
1146         .wait_for_idle = nv_common_wait_for_idle,
1147         .soft_reset = nv_common_soft_reset,
1148         .set_clockgating_state = nv_common_set_clockgating_state,
1149         .set_powergating_state = nv_common_set_powergating_state,
1150         .get_clockgating_state = nv_common_get_clockgating_state,
1151 };