drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_discovery.h"
  28 #include "soc15_hw_ip.h"
  29 #include "discovery.h"
  30
  31 #include "soc15.h"
  32 #include "gfx_v9_0.h"
  33 #include "gmc_v9_0.h"
  34 #include "df_v1_7.h"
  35 #include "df_v3_6.h"
  36 #include "nbio_v6_1.h"
  37 #include "nbio_v7_0.h"
  38 #include "nbio_v7_4.h"
  39 #include "hdp_v4_0.h"
  40 #include "vega10_ih.h"
  41 #include "vega20_ih.h"
  42 #include "sdma_v4_0.h"
  43 #include "uvd_v7_0.h"
  44 #include "vce_v4_0.h"
  45 #include "vcn_v1_0.h"
  46 #include "vcn_v2_5.h"
  47 #include "jpeg_v2_5.h"
  48 #include "smuio_v9_0.h"
  49 #include "gmc_v10_0.h"
  50 #include "gfxhub_v2_0.h"
  51 #include "mmhub_v2_0.h"
  52 #include "nbio_v2_3.h"
  53 #include "nbio_v7_2.h"
  54 #include "hdp_v5_0.h"
  55 #include "nv.h"
  56 #include "navi10_ih.h"
  57 #include "gfx_v10_0.h"
  58 #include "sdma_v5_0.h"
  59 #include "sdma_v5_2.h"
  60 #include "vcn_v2_0.h"
  61 #include "jpeg_v2_0.h"
  62 #include "vcn_v3_0.h"
  63 #include "jpeg_v3_0.h"
  64 #include "amdgpu_vkms.h"
  65 #include "mes_v10_1.h"
  66 #include "smuio_v11_0.h"
  67 #include "smuio_v11_0_6.h"
  68 #include "smuio_v13_0.h"
  69
  70 MODULE_FIRMWARE("amdgpu/ip_discovery.bin");
  71
  72 #define mmRCC_CONFIG_MEMSIZE    0xde3
  73 #define mmMM_INDEX              0x0
  74 #define mmMM_INDEX_HI           0x6
  75 #define mmMM_DATA               0x1
  76
  77 static const char *hw_id_names[HW_ID_MAX] = {
  78         [MP1_HWID]              = "MP1",
  79         [MP2_HWID]              = "MP2",
  80         [THM_HWID]              = "THM",
  81         [SMUIO_HWID]            = "SMUIO",
  82         [FUSE_HWID]             = "FUSE",
  83         [CLKA_HWID]             = "CLKA",
  84         [PWR_HWID]              = "PWR",
  85         [GC_HWID]               = "GC",
  86         [UVD_HWID]              = "UVD",
  87         [AUDIO_AZ_HWID]         = "AUDIO_AZ",
  88         [ACP_HWID]              = "ACP",
  89         [DCI_HWID]              = "DCI",
  90         [DMU_HWID]              = "DMU",
  91         [DCO_HWID]              = "DCO",
  92         [DIO_HWID]              = "DIO",
  93         [XDMA_HWID]             = "XDMA",
  94         [DCEAZ_HWID]            = "DCEAZ",
  95         [DAZ_HWID]              = "DAZ",
  96         [SDPMUX_HWID]           = "SDPMUX",
  97         [NTB_HWID]              = "NTB",
  98         [IOHC_HWID]             = "IOHC",
  99         [L2IMU_HWID]            = "L2IMU",
 100         [VCE_HWID]              = "VCE",
 101         [MMHUB_HWID]            = "MMHUB",
 102         [ATHUB_HWID]            = "ATHUB",
 103         [DBGU_NBIO_HWID]        = "DBGU_NBIO",
 104         [DFX_HWID]              = "DFX",
 105         [DBGU0_HWID]            = "DBGU0",
 106         [DBGU1_HWID]            = "DBGU1",
 107         [OSSSYS_HWID]           = "OSSSYS",
 108         [HDP_HWID]              = "HDP",
 109         [SDMA0_HWID]            = "SDMA0",
 110         [SDMA1_HWID]            = "SDMA1",
 111         [SDMA2_HWID]            = "SDMA2",
 112         [SDMA3_HWID]            = "SDMA3",
 113         [ISP_HWID]              = "ISP",
 114         [DBGU_IO_HWID]          = "DBGU_IO",
 115         [DF_HWID]               = "DF",
 116         [CLKB_HWID]             = "CLKB",
 117         [FCH_HWID]              = "FCH",
 118         [DFX_DAP_HWID]          = "DFX_DAP",
 119         [L1IMU_PCIE_HWID]       = "L1IMU_PCIE",
 120         [L1IMU_NBIF_HWID]       = "L1IMU_NBIF",
 121         [L1IMU_IOAGR_HWID]      = "L1IMU_IOAGR",
 122         [L1IMU3_HWID]           = "L1IMU3",
 123         [L1IMU4_HWID]           = "L1IMU4",
 124         [L1IMU5_HWID]           = "L1IMU5",
 125         [L1IMU6_HWID]           = "L1IMU6",
 126         [L1IMU7_HWID]           = "L1IMU7",
 127         [L1IMU8_HWID]           = "L1IMU8",
 128         [L1IMU9_HWID]           = "L1IMU9",
 129         [L1IMU10_HWID]          = "L1IMU10",
 130         [L1IMU11_HWID]          = "L1IMU11",
 131         [L1IMU12_HWID]          = "L1IMU12",
 132         [L1IMU13_HWID]          = "L1IMU13",
 133         [L1IMU14_HWID]          = "L1IMU14",
 134         [L1IMU15_HWID]          = "L1IMU15",
 135         [WAFLC_HWID]            = "WAFLC",
 136         [FCH_USB_PD_HWID]       = "FCH_USB_PD",
 137         [PCIE_HWID]             = "PCIE",
 138         [PCS_HWID]              = "PCS",
 139         [DDCL_HWID]             = "DDCL",
 140         [SST_HWID]              = "SST",
 141         [IOAGR_HWID]            = "IOAGR",
 142         [NBIF_HWID]             = "NBIF",
 143         [IOAPIC_HWID]           = "IOAPIC",
 144         [SYSTEMHUB_HWID]        = "SYSTEMHUB",
 145         [NTBCCP_HWID]           = "NTBCCP",
 146         [UMC_HWID]              = "UMC",
 147         [SATA_HWID]             = "SATA",
 148         [USB_HWID]              = "USB",
 149         [CCXSEC_HWID]           = "CCXSEC",
 150         [XGMI_HWID]             = "XGMI",
 151         [XGBE_HWID]             = "XGBE",
 152         [MP0_HWID]              = "MP0",
 153 };
 154
 155 static int hw_id_map[MAX_HWIP] = {
 156         [GC_HWIP]       = GC_HWID,
 157         [HDP_HWIP]      = HDP_HWID,
 158         [SDMA0_HWIP]    = SDMA0_HWID,
 159         [SDMA1_HWIP]    = SDMA1_HWID,
 160         [MMHUB_HWIP]    = MMHUB_HWID,
 161         [ATHUB_HWIP]    = ATHUB_HWID,
 162         [NBIO_HWIP]     = NBIF_HWID,
 163         [MP0_HWIP]      = MP0_HWID,
 164         [MP1_HWIP]      = MP1_HWID,
 165         [UVD_HWIP]      = UVD_HWID,
 166         [VCE_HWIP]      = VCE_HWID,
 167         [DF_HWIP]       = DF_HWID,
 168         [DCE_HWIP]      = DMU_HWID,
 169         [OSSSYS_HWIP]   = OSSSYS_HWID,
 170         [SMUIO_HWIP]    = SMUIO_HWID,
 171         [PWR_HWIP]      = PWR_HWID,
 172         [NBIF_HWIP]     = NBIF_HWID,
 173         [THM_HWIP]      = THM_HWID,
 174         [CLK_HWIP]      = CLKA_HWID,
 175         [UMC_HWIP]      = UMC_HWID,
 176         [XGMI_HWIP]     = XGMI_HWID,
 177         [DCI_HWIP]      = DCI_HWID,
 178 };
 179
 180 static int amdgpu_discovery_read_binary(struct amdgpu_device *adev, uint8_t *binary)
 181 {
 182         uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
 183         uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET;
 184
 185         amdgpu_device_vram_access(adev, pos, (uint32_t *)binary,
 186                                   adev->mman.discovery_tmr_size, false);
 187         return 0;
 188 }
 189
 190 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size)
 191 {
 192         uint16_t checksum = 0;
 193         int i;
 194
 195         for (i = 0; i < size; i++)
 196                 checksum += data[i];
 197
 198         return checksum;
 199 }
 200
 201 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size,
 202                                                     uint16_t expected)
 203 {
 204         return !!(amdgpu_discovery_calculate_checksum(data, size) == expected);
 205 }
 206
 207 static int amdgpu_discovery_init(struct amdgpu_device *adev)
 208 {
 209         struct table_info *info;
 210         struct binary_header *bhdr;
 211         struct ip_discovery_header *ihdr;
 212         struct gpu_info_header *ghdr;
 213         const struct firmware *fw;
 214         uint16_t offset;
 215         uint16_t size;
 216         uint16_t checksum;
 217         int r;
 218
 219         adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE;
 220         adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL);
 221         if (!adev->mman.discovery_bin)
 222                 return -ENOMEM;
 223
 224         if (amdgpu_discovery == 2) {
 225                 r = request_firmware(&fw, "amdgpu/ip_discovery.bin", adev->dev);
 226                 if (r)
 227                         goto get_from_vram;
 228                 dev_info(adev->dev, "Using IP discovery from file\n");
 229                 memcpy((u8 *)adev->mman.discovery_bin, (u8 *)fw->data,
 230                        adev->mman.discovery_tmr_size);
 231                 release_firmware(fw);
 232         } else {
 233 get_from_vram:
 234                 r = amdgpu_discovery_read_binary(adev, adev->mman.discovery_bin);
 235                 if (r) {
 236                         DRM_ERROR("failed to read ip discovery binary\n");
 237                         goto out;
 238                 }
 239         }
 240
 241         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 242
 243         if (le32_to_cpu(bhdr->binary_signature) != BINARY_SIGNATURE) {
 244                 DRM_ERROR("invalid ip discovery binary signature\n");
 245                 r = -EINVAL;
 246                 goto out;
 247         }
 248
 249         offset = offsetof(struct binary_header, binary_checksum) +
 250                 sizeof(bhdr->binary_checksum);
 251         size = bhdr->binary_size - offset;
 252         checksum = bhdr->binary_checksum;
 253
 254         if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 255                                               size, checksum)) {
 256                 DRM_ERROR("invalid ip discovery binary checksum\n");
 257                 r = -EINVAL;
 258                 goto out;
 259         }
 260
 261         info = &bhdr->table_list[IP_DISCOVERY];
 262         offset = le16_to_cpu(info->offset);
 263         checksum = le16_to_cpu(info->checksum);
 264         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + offset);
 265
 266         if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) {
 267                 DRM_ERROR("invalid ip discovery data table signature\n");
 268                 r = -EINVAL;
 269                 goto out;
 270         }
 271
 272         if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 273                                               ihdr->size, checksum)) {
 274                 DRM_ERROR("invalid ip discovery data table checksum\n");
 275                 r = -EINVAL;
 276                 goto out;
 277         }
 278
 279         info = &bhdr->table_list[GC];
 280         offset = le16_to_cpu(info->offset);
 281         checksum = le16_to_cpu(info->checksum);
 282         ghdr = (struct gpu_info_header *)(adev->mman.discovery_bin + offset);
 283
 284         if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 285                                               ghdr->size, checksum)) {
 286                 DRM_ERROR("invalid gc data table checksum\n");
 287                 r = -EINVAL;
 288                 goto out;
 289         }
 290
 291         return 0;
 292
 293 out:
 294         kfree(adev->mman.discovery_bin);
 295         adev->mman.discovery_bin = NULL;
 296
 297         return r;
 298 }
 299
 300 void amdgpu_discovery_fini(struct amdgpu_device *adev)
 301 {
 302         kfree(adev->mman.discovery_bin);
 303         adev->mman.discovery_bin = NULL;
 304 }
 305
 306 static int amdgpu_discovery_validate_ip(const struct ip *ip)
 307 {
 308         if (ip->number_instance >= HWIP_MAX_INSTANCE) {
 309                 DRM_ERROR("Unexpected number_instance (%d) from ip discovery blob\n",
 310                           ip->number_instance);
 311                 return -EINVAL;
 312         }
 313         if (le16_to_cpu(ip->hw_id) >= HW_ID_MAX) {
 314                 DRM_ERROR("Unexpected hw_id (%d) from ip discovery blob\n",
 315                           le16_to_cpu(ip->hw_id));
 316                 return -EINVAL;
 317         }
 318
 319         return 0;
 320 }
 321
 322 int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
 323 {
 324         struct binary_header *bhdr;
 325         struct ip_discovery_header *ihdr;
 326         struct die_header *dhdr;
 327         struct ip *ip;
 328         uint16_t die_offset;
 329         uint16_t ip_offset;
 330         uint16_t num_dies;
 331         uint16_t num_ips;
 332         uint8_t num_base_address;
 333         int hw_ip;
 334         int i, j, k;
 335         int r;
 336
 337         r = amdgpu_discovery_init(adev);
 338         if (r) {
 339                 DRM_ERROR("amdgpu_discovery_init failed\n");
 340                 return r;
 341         }
 342
 343         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 344         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
 345                         le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
 346         num_dies = le16_to_cpu(ihdr->num_dies);
 347
 348         DRM_DEBUG("number of dies: %d\n", num_dies);
 349
 350         for (i = 0; i < num_dies; i++) {
 351                 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
 352                 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
 353                 num_ips = le16_to_cpu(dhdr->num_ips);
 354                 ip_offset = die_offset + sizeof(*dhdr);
 355
 356                 if (le16_to_cpu(dhdr->die_id) != i) {
 357                         DRM_ERROR("invalid die id %d, expected %d\n",
 358                                         le16_to_cpu(dhdr->die_id), i);
 359                         return -EINVAL;
 360                 }
 361
 362                 DRM_DEBUG("number of hardware IPs on die%d: %d\n",
 363                                 le16_to_cpu(dhdr->die_id), num_ips);
 364
 365                 for (j = 0; j < num_ips; j++) {
 366                         ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
 367
 368                         if (amdgpu_discovery_validate_ip(ip))
 369                                 goto next_ip;
 370
 371                         num_base_address = ip->num_base_address;
 372
 373                         DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n",
 374                                   hw_id_names[le16_to_cpu(ip->hw_id)],
 375                                   le16_to_cpu(ip->hw_id),
 376                                   ip->number_instance,
 377                                   ip->major, ip->minor,
 378                                   ip->revision);
 379
 380                         if (le16_to_cpu(ip->hw_id) == VCN_HWID)
 381                                 adev->vcn.num_vcn_inst++;
 382                         if (le16_to_cpu(ip->hw_id) == SDMA0_HWID ||
 383                             le16_to_cpu(ip->hw_id) == SDMA1_HWID ||
 384                             le16_to_cpu(ip->hw_id) == SDMA2_HWID ||
 385                             le16_to_cpu(ip->hw_id) == SDMA3_HWID)
 386                                 adev->sdma.num_instances++;
 387
 388                         for (k = 0; k < num_base_address; k++) {
 389                                 /*
 390                                  * convert the endianness of base addresses in place,
 391                                  * so that we don't need to convert them when accessing adev->reg_offset.
 392                                  */
 393                                 ip->base_address[k] = le32_to_cpu(ip->base_address[k]);
 394                                 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]);
 395                         }
 396
 397                         for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) {
 398                                 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id)) {
 399                                         DRM_DEBUG("set register base offset for %s\n",
 400                                                         hw_id_names[le16_to_cpu(ip->hw_id)]);
 401                                         adev->reg_offset[hw_ip][ip->number_instance] =
 402                                                 ip->base_address;
 403                                         /* Instance support is somewhat inconsistent.
 404                                          * SDMA is a good example.  Sienna cichlid has 4 total
 405                                          * SDMA instances, each enumerated separately (HWIDs
 406                                          * 42, 43, 68, 69).  Arcturus has 8 total SDMA instances,
 407                                          * but they are enumerated as multiple instances of the
 408                                          * same HWIDs (4x HWID 42, 4x HWID 43).  UMC is another
 409                                          * example.  On most chips there are multiple instances
 410                                          * with the same HWID.
 411                                          */
 412                                         adev->ip_versions[hw_ip][ip->number_instance] =
 413                                                 IP_VERSION(ip->major, ip->minor, ip->revision);
 414                                 }
 415                         }
 416
 417 next_ip:
 418                         ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1);
 419                 }
 420         }
 421
 422         return 0;
 423 }
 424
 425 int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int number_instance,
 426                                     int *major, int *minor, int *revision)
 427 {
 428         struct binary_header *bhdr;
 429         struct ip_discovery_header *ihdr;
 430         struct die_header *dhdr;
 431         struct ip *ip;
 432         uint16_t die_offset;
 433         uint16_t ip_offset;
 434         uint16_t num_dies;
 435         uint16_t num_ips;
 436         int i, j;
 437
 438         if (!adev->mman.discovery_bin) {
 439                 DRM_ERROR("ip discovery uninitialized\n");
 440                 return -EINVAL;
 441         }
 442
 443         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 444         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
 445                         le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
 446         num_dies = le16_to_cpu(ihdr->num_dies);
 447
 448         for (i = 0; i < num_dies; i++) {
 449                 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
 450                 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
 451                 num_ips = le16_to_cpu(dhdr->num_ips);
 452                 ip_offset = die_offset + sizeof(*dhdr);
 453
 454                 for (j = 0; j < num_ips; j++) {
 455                         ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
 456
 457                         if ((le16_to_cpu(ip->hw_id) == hw_id) && (ip->number_instance == number_instance)) {
 458                                 if (major)
 459                                         *major = ip->major;
 460                                 if (minor)
 461                                         *minor = ip->minor;
 462                                 if (revision)
 463                                         *revision = ip->revision;
 464                                 return 0;
 465                         }
 466                         ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1);
 467                 }
 468         }
 469
 470         return -EINVAL;
 471 }
 472
 473
 474 int amdgpu_discovery_get_vcn_version(struct amdgpu_device *adev, int vcn_instance,
 475                                      int *major, int *minor, int *revision)
 476 {
 477         return amdgpu_discovery_get_ip_version(adev, VCN_HWID,
 478                                                vcn_instance, major, minor, revision);
 479 }
 480
 481 void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
 482 {
 483         struct binary_header *bhdr;
 484         struct harvest_table *harvest_info;
 485         int i, vcn_harvest_count = 0;
 486
 487         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 488         harvest_info = (struct harvest_table *)(adev->mman.discovery_bin +
 489                         le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset));
 490
 491         for (i = 0; i < 32; i++) {
 492                 if (le32_to_cpu(harvest_info->list[i].hw_id) == 0)
 493                         break;
 494
 495                 switch (le32_to_cpu(harvest_info->list[i].hw_id)) {
 496                 case VCN_HWID:
 497                         vcn_harvest_count++;
 498                         if (harvest_info->list[i].number_instance == 0)
 499                                 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0;
 500                         else
 501                                 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
 502                         break;
 503                 case DMU_HWID:
 504                         adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
 505                         break;
 506                 default:
 507                         break;
 508                 }
 509         }
 510         /* some IP discovery tables on Navy Flounder don't have this set correctly */
 511         if ((adev->ip_versions[UVD_HWIP][1] == IP_VERSION(3, 0, 1)) &&
 512             (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 2)))
 513                 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
 514         if (vcn_harvest_count == adev->vcn.num_vcn_inst) {
 515                 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
 516                 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
 517         }
 518         if ((adev->pdev->device == 0x731E &&
 519              (adev->pdev->revision == 0xC6 || adev->pdev->revision == 0xC7)) ||
 520             (adev->pdev->device == 0x7340 && adev->pdev->revision == 0xC9)  ||
 521             (adev->pdev->device == 0x7360 && adev->pdev->revision == 0xC7)) {
 522                 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
 523                 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
 524         }
 525 }
 526
 527 int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
 528 {
 529         struct binary_header *bhdr;
 530         struct gc_info_v1_0 *gc_info;
 531
 532         if (!adev->mman.discovery_bin) {
 533                 DRM_ERROR("ip discovery uninitialized\n");
 534                 return -EINVAL;
 535         }
 536
 537         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 538         gc_info = (struct gc_info_v1_0 *)(adev->mman.discovery_bin +
 539                         le16_to_cpu(bhdr->table_list[GC].offset));
 540
 541         adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->gc_num_se);
 542         adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->gc_num_wgp0_per_sa) +
 543                                               le32_to_cpu(gc_info->gc_num_wgp1_per_sa));
 544         adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->gc_num_sa_per_se);
 545         adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->gc_num_rb_per_se);
 546         adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->gc_num_gl2c);
 547         adev->gfx.config.max_gprs = le32_to_cpu(gc_info->gc_num_gprs);
 548         adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->gc_num_max_gs_thds);
 549         adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->gc_gs_table_depth);
 550         adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->gc_gsprim_buff_depth);
 551         adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->gc_double_offchip_lds_buffer);
 552         adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->gc_wave_size);
 553         adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->gc_max_waves_per_simd);
 554         adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->gc_max_scratch_slots_per_cu);
 555         adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->gc_lds_size);
 556         adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->gc_num_sc_per_se) /
 557                                          le32_to_cpu(gc_info->gc_num_sa_per_se);
 558         adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->gc_num_packer_per_sc);
 559
 560         return 0;
 561 }
 562
 563 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev)
 564 {
 565         /* what IP to use for this? */
 566         switch (adev->ip_versions[GC_HWIP][0]) {
 567         case IP_VERSION(9, 0, 1):
 568         case IP_VERSION(9, 1, 0):
 569         case IP_VERSION(9, 2, 1):
 570         case IP_VERSION(9, 2, 2):
 571         case IP_VERSION(9, 3, 0):
 572         case IP_VERSION(9, 4, 0):
 573         case IP_VERSION(9, 4, 1):
 574         case IP_VERSION(9, 4, 2):
 575                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 576                 break;
 577         case IP_VERSION(10, 1, 10):
 578         case IP_VERSION(10, 1, 1):
 579         case IP_VERSION(10, 1, 2):
 580         case IP_VERSION(10, 1, 3):
 581         case IP_VERSION(10, 3, 0):
 582         case IP_VERSION(10, 3, 1):
 583         case IP_VERSION(10, 3, 2):
 584         case IP_VERSION(10, 3, 3):
 585         case IP_VERSION(10, 3, 4):
 586         case IP_VERSION(10, 3, 5):
 587                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 588                 break;
 589         default:
 590                 return -EINVAL;
 591         }
 592         return 0;
 593 }
 594
 595 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev)
 596 {
 597         /* use GC or MMHUB IP version */
 598         switch (adev->ip_versions[GC_HWIP][0]) {
 599         case IP_VERSION(9, 0, 1):
 600         case IP_VERSION(9, 1, 0):
 601         case IP_VERSION(9, 2, 1):
 602         case IP_VERSION(9, 2, 2):
 603         case IP_VERSION(9, 3, 0):
 604         case IP_VERSION(9, 4, 0):
 605         case IP_VERSION(9, 4, 1):
 606         case IP_VERSION(9, 4, 2):
 607                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 608                 break;
 609         case IP_VERSION(10, 1, 10):
 610         case IP_VERSION(10, 1, 1):
 611         case IP_VERSION(10, 1, 2):
 612         case IP_VERSION(10, 1, 3):
 613         case IP_VERSION(10, 3, 0):
 614         case IP_VERSION(10, 3, 1):
 615         case IP_VERSION(10, 3, 2):
 616         case IP_VERSION(10, 3, 3):
 617         case IP_VERSION(10, 3, 4):
 618         case IP_VERSION(10, 3, 5):
 619                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 620                 break;
 621         default:
 622                 return -EINVAL;
 623         }
 624         return 0;
 625 }
 626
 627 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev)
 628 {
 629         switch (adev->ip_versions[OSSSYS_HWIP][0]) {
 630         case IP_VERSION(4, 0, 0):
 631         case IP_VERSION(4, 0, 1):
 632         case IP_VERSION(4, 1, 0):
 633         case IP_VERSION(4, 1, 1):
 634         case IP_VERSION(4, 3, 0):
 635                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 636                 break;
 637         case IP_VERSION(4, 2, 0):
 638         case IP_VERSION(4, 2, 1):
 639         case IP_VERSION(4, 4, 0):
 640                 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
 641                 break;
 642         case IP_VERSION(5, 0, 0):
 643         case IP_VERSION(5, 0, 1):
 644         case IP_VERSION(5, 0, 2):
 645         case IP_VERSION(5, 0, 3):
 646         case IP_VERSION(5, 2, 0):
 647         case IP_VERSION(5, 2, 1):
 648                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 649                 break;
 650         default:
 651                 return -EINVAL;
 652         }
 653         return 0;
 654 }
 655
 656 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev)
 657 {
 658         switch (adev->ip_versions[MP0_HWIP][0]) {
 659         case IP_VERSION(9, 0, 0):
 660                 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
 661                 break;
 662         case IP_VERSION(10, 0, 0):
 663         case IP_VERSION(10, 0, 1):
 664                 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
 665                 break;
 666         case IP_VERSION(11, 0, 0):
 667         case IP_VERSION(11, 0, 2):
 668         case IP_VERSION(11, 0, 4):
 669         case IP_VERSION(11, 0, 5):
 670         case IP_VERSION(11, 0, 9):
 671         case IP_VERSION(11, 0, 7):
 672         case IP_VERSION(11, 0, 11):
 673         case IP_VERSION(11, 0, 12):
 674         case IP_VERSION(11, 0, 13):
 675         case IP_VERSION(11, 5, 0):
 676                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 677                 break;
 678         case IP_VERSION(11, 0, 8):
 679                 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block);
 680                 break;
 681         case IP_VERSION(11, 0, 3):
 682         case IP_VERSION(12, 0, 1):
 683                 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
 684                 break;
 685         case IP_VERSION(13, 0, 1):
 686         case IP_VERSION(13, 0, 2):
 687         case IP_VERSION(13, 0, 3):
 688                 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
 689                 break;
 690         default:
 691                 return -EINVAL;
 692         }
 693         return 0;
 694 }
 695
 696 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev)
 697 {
 698         switch (adev->ip_versions[MP1_HWIP][0]) {
 699         case IP_VERSION(9, 0, 0):
 700         case IP_VERSION(10, 0, 0):
 701         case IP_VERSION(10, 0, 1):
 702         case IP_VERSION(11, 0, 2):
 703                 if (adev->asic_type == CHIP_ARCTURUS)
 704                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 705                 else
 706                         amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
 707                 break;
 708         case IP_VERSION(11, 0, 0):
 709         case IP_VERSION(11, 0, 5):
 710         case IP_VERSION(11, 0, 9):
 711         case IP_VERSION(11, 0, 7):
 712         case IP_VERSION(11, 0, 8):
 713         case IP_VERSION(11, 0, 11):
 714         case IP_VERSION(11, 0, 12):
 715         case IP_VERSION(11, 0, 13):
 716         case IP_VERSION(11, 5, 0):
 717                 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 718                 break;
 719         case IP_VERSION(12, 0, 0):
 720         case IP_VERSION(12, 0, 1):
 721                 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
 722                 break;
 723         case IP_VERSION(13, 0, 1):
 724         case IP_VERSION(13, 0, 2):
 725         case IP_VERSION(13, 0, 3):
 726                 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
 727                 break;
 728         default:
 729                 return -EINVAL;
 730         }
 731         return 0;
 732 }
 733
 734 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev)
 735 {
 736         if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) {
 737                 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
 738 #if defined(CONFIG_DRM_AMD_DC)
 739         } else if (adev->ip_versions[DCE_HWIP][0]) {
 740                 switch (adev->ip_versions[DCE_HWIP][0]) {
 741                 case IP_VERSION(1, 0, 0):
 742                 case IP_VERSION(1, 0, 1):
 743                 case IP_VERSION(2, 0, 2):
 744                 case IP_VERSION(2, 0, 0):
 745                 case IP_VERSION(2, 0, 3):
 746                 case IP_VERSION(2, 1, 0):
 747                 case IP_VERSION(3, 0, 0):
 748                 case IP_VERSION(3, 0, 2):
 749                 case IP_VERSION(3, 0, 3):
 750                 case IP_VERSION(3, 0, 1):
 751                 case IP_VERSION(3, 1, 2):
 752                 case IP_VERSION(3, 1, 3):
 753                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 754                         break;
 755                 default:
 756                         return -EINVAL;
 757                 }
 758         } else if (adev->ip_versions[DCI_HWIP][0]) {
 759                 switch (adev->ip_versions[DCI_HWIP][0]) {
 760                 case IP_VERSION(12, 0, 0):
 761                 case IP_VERSION(12, 0, 1):
 762                 case IP_VERSION(12, 1, 0):
 763                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 764                         break;
 765                 default:
 766                         return -EINVAL;
 767                 }
 768 #endif
 769         }
 770         return 0;
 771 }
 772
 773 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev)
 774 {
 775         switch (adev->ip_versions[GC_HWIP][0]) {
 776         case IP_VERSION(9, 0, 1):
 777         case IP_VERSION(9, 1, 0):
 778         case IP_VERSION(9, 2, 1):
 779         case IP_VERSION(9, 2, 2):
 780         case IP_VERSION(9, 3, 0):
 781         case IP_VERSION(9, 4, 0):
 782         case IP_VERSION(9, 4, 1):
 783         case IP_VERSION(9, 4, 2):
 784                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 785                 break;
 786         case IP_VERSION(10, 1, 10):
 787         case IP_VERSION(10, 1, 2):
 788         case IP_VERSION(10, 1, 1):
 789         case IP_VERSION(10, 1, 3):
 790         case IP_VERSION(10, 3, 0):
 791         case IP_VERSION(10, 3, 2):
 792         case IP_VERSION(10, 3, 1):
 793         case IP_VERSION(10, 3, 4):
 794         case IP_VERSION(10, 3, 5):
 795         case IP_VERSION(10, 3, 3):
 796                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 797                 break;
 798         default:
 799                 return -EINVAL;
 800         }
 801         return 0;
 802 }
 803
 804 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev)
 805 {
 806         switch (adev->ip_versions[SDMA0_HWIP][0]) {
 807         case IP_VERSION(4, 0, 0):
 808         case IP_VERSION(4, 0, 1):
 809         case IP_VERSION(4, 1, 0):
 810         case IP_VERSION(4, 1, 1):
 811         case IP_VERSION(4, 1, 2):
 812         case IP_VERSION(4, 2, 0):
 813         case IP_VERSION(4, 2, 2):
 814         case IP_VERSION(4, 4, 0):
 815                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 816                 break;
 817         case IP_VERSION(5, 0, 0):
 818         case IP_VERSION(5, 0, 1):
 819         case IP_VERSION(5, 0, 2):
 820         case IP_VERSION(5, 0, 5):
 821                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
 822                 break;
 823         case IP_VERSION(5, 2, 0):
 824         case IP_VERSION(5, 2, 2):
 825         case IP_VERSION(5, 2, 4):
 826         case IP_VERSION(5, 2, 5):
 827         case IP_VERSION(5, 2, 3):
 828         case IP_VERSION(5, 2, 1):
 829                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 830                 break;
 831         default:
 832                 return -EINVAL;
 833         }
 834         return 0;
 835 }
 836
 837 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
 838 {
 839         if (adev->ip_versions[VCE_HWIP][0]) {
 840                 switch (adev->ip_versions[UVD_HWIP][0]) {
 841                 case IP_VERSION(7, 0, 0):
 842                 case IP_VERSION(7, 2, 0):
 843                         /* UVD is not supported on vega20 SR-IOV */
 844                         if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
 845                                 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
 846                         break;
 847                 default:
 848                         return -EINVAL;
 849                 }
 850                 switch (adev->ip_versions[VCE_HWIP][0]) {
 851                 case IP_VERSION(4, 0, 0):
 852                 case IP_VERSION(4, 1, 0):
 853                         /* VCE is not supported on vega20 SR-IOV */
 854                         if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
 855                                 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
 856                         break;
 857                 default:
 858                         return -EINVAL;
 859                 }
 860         } else {
 861                 switch (adev->ip_versions[UVD_HWIP][0]) {
 862                 case IP_VERSION(1, 0, 0):
 863                 case IP_VERSION(1, 0, 1):
 864                         amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
 865                         break;
 866                 case IP_VERSION(2, 0, 0):
 867                 case IP_VERSION(2, 0, 2):
 868                 case IP_VERSION(2, 2, 0):
 869                         amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
 870                         amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
 871                         break;
 872                 case IP_VERSION(2, 0, 3):
 873                         break;
 874                 case IP_VERSION(2, 5, 0):
 875                         amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
 876                         amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
 877                         break;
 878                 case IP_VERSION(2, 6, 0):
 879                         amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block);
 880                         amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block);
 881                         break;
 882                 case IP_VERSION(3, 0, 0):
 883                 case IP_VERSION(3, 0, 16):
 884                 case IP_VERSION(3, 1, 1):
 885                 case IP_VERSION(3, 0, 2):
 886                         amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 887                         if (!amdgpu_sriov_vf(adev))
 888                                 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
 889                         break;
 890                 case IP_VERSION(3, 0, 33):
 891                         amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 892                         break;
 893                 default:
 894                         return -EINVAL;
 895                 }
 896         }
 897         return 0;
 898 }
 899
 900 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)
 901 {
 902         switch (adev->ip_versions[GC_HWIP][0]) {
 903         case IP_VERSION(10, 1, 10):
 904         case IP_VERSION(10, 1, 1):
 905         case IP_VERSION(10, 1, 2):
 906         case IP_VERSION(10, 1, 3):
 907         case IP_VERSION(10, 3, 0):
 908         case IP_VERSION(10, 3, 1):
 909         case IP_VERSION(10, 3, 2):
 910         case IP_VERSION(10, 3, 3):
 911         case IP_VERSION(10, 3, 4):
 912         case IP_VERSION(10, 3, 5):
 913                 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
 914                 break;
 915         default:
 916                 break;;
 917         }
 918         return 0;
 919 }
 920
 921 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
 922 {
 923         int r;
 924
 925         switch (adev->asic_type) {
 926         case CHIP_VEGA10:
 927                 vega10_reg_base_init(adev);
 928                 adev->sdma.num_instances = 2;
 929                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0);
 930                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0);
 931                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0);
 932                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0);
 933                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0);
 934                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0);
 935                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
 936                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0);
 937                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0);
 938                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
 939                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
 940                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
 941                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0);
 942                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1);
 943                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
 944                 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
 945                 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0);
 946                 break;
 947         case CHIP_VEGA12:
 948                 vega10_reg_base_init(adev);
 949                 adev->sdma.num_instances = 2;
 950                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0);
 951                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0);
 952                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1);
 953                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1);
 954                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1);
 955                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1);
 956                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0);
 957                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0);
 958                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0);
 959                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
 960                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
 961                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
 962                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1);
 963                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1);
 964                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
 965                 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
 966                 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1);
 967                 break;
 968         case CHIP_RAVEN:
 969                 vega10_reg_base_init(adev);
 970                 adev->sdma.num_instances = 1;
 971                 adev->vcn.num_vcn_inst = 1;
 972                 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
 973                         adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0);
 974                         adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0);
 975                         adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1);
 976                         adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1);
 977                         adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1);
 978                         adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1);
 979                         adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1);
 980                         adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0);
 981                         adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1);
 982                         adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1);
 983                         adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0);
 984                         adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1);
 985                         adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2);
 986                         adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1);
 987                         adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1);
 988                 } else {
 989                         adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0);
 990                         adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0);
 991                         adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0);
 992                         adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0);
 993                         adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0);
 994                         adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
 995                         adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0);
 996                         adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0);
 997                         adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0);
 998                         adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0);
 999                         adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0);
1000                         adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0);
1001                         adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0);
1002                         adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0);
1003                         adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0);
1004                 }
1005                 break;
1006         case CHIP_VEGA20:
1007                 vega20_reg_base_init(adev);
1008                 adev->sdma.num_instances = 2;
1009                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0);
1010                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0);
1011                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0);
1012                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0);
1013                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0);
1014                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0);
1015                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0);
1016                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0);
1017                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1);
1018                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2);
1019                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
1020                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2);
1021                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2);
1022                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0);
1023                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0);
1024                 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0);
1025                 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0);
1026                 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0);
1027                 break;
1028         case CHIP_ARCTURUS:
1029                 arct_reg_base_init(adev);
1030                 adev->sdma.num_instances = 8;
1031                 adev->vcn.num_vcn_inst = 2;
1032                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1);
1033                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1);
1034                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1);
1035                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1);
1036                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2);
1037                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2);
1038                 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2);
1039                 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2);
1040                 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2);
1041                 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2);
1042                 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2);
1043                 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2);
1044                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1);
1045                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1);
1046                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2);
1047                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4);
1048                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
1049                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3);
1050                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3);
1051                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1);
1052                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0);
1053                 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0);
1054                 break;
1055         case CHIP_ALDEBARAN:
1056                 aldebaran_reg_base_init(adev);
1057                 adev->sdma.num_instances = 5;
1058                 adev->vcn.num_vcn_inst = 2;
1059                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2);
1060                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2);
1061                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0);
1062                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0);
1063                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0);
1064                 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0);
1065                 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0);
1066                 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0);
1067                 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0);
1068                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2);
1069                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4);
1070                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0);
1071                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2);
1072                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2);
1073                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2);
1074                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2);
1075                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2);
1076                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0);
1077                 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0);
1078                 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0);
1079                 break;
1080         default:
1081                 r = amdgpu_discovery_reg_base_init(adev);
1082                 if (r)
1083                         return -EINVAL;
1084
1085                 amdgpu_discovery_harvest_ip(adev);
1086
1087                 if (!adev->mman.discovery_bin) {
1088                         DRM_ERROR("ip discovery uninitialized\n");
1089                         return -EINVAL;
1090                 }
1091                 break;
1092         }
1093
1094         switch (adev->ip_versions[GC_HWIP][0]) {
1095         case IP_VERSION(9, 0, 1):
1096         case IP_VERSION(9, 2, 1):
1097         case IP_VERSION(9, 4, 0):
1098         case IP_VERSION(9, 4, 1):
1099         case IP_VERSION(9, 4, 2):
1100                 adev->family = AMDGPU_FAMILY_AI;
1101                 break;
1102         case IP_VERSION(9, 1, 0):
1103         case IP_VERSION(9, 2, 2):
1104         case IP_VERSION(9, 3, 0):
1105                 adev->family = AMDGPU_FAMILY_RV;
1106                 break;
1107         case IP_VERSION(10, 1, 10):
1108         case IP_VERSION(10, 1, 1):
1109         case IP_VERSION(10, 1, 2):
1110         case IP_VERSION(10, 1, 3):
1111         case IP_VERSION(10, 3, 0):
1112         case IP_VERSION(10, 3, 2):
1113         case IP_VERSION(10, 3, 4):
1114         case IP_VERSION(10, 3, 5):
1115                 adev->family = AMDGPU_FAMILY_NV;
1116                 break;
1117         case IP_VERSION(10, 3, 1):
1118                 adev->family = AMDGPU_FAMILY_VGH;
1119                 break;
1120         case IP_VERSION(10, 3, 3):
1121                 adev->family = AMDGPU_FAMILY_YC;
1122                 break;
1123         default:
1124                 return -EINVAL;
1125         }
1126
1127         if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0))
1128                 adev->gmc.xgmi.supported = true;
1129
1130         /* set NBIO version */
1131         switch (adev->ip_versions[NBIO_HWIP][0]) {
1132         case IP_VERSION(6, 1, 0):
1133         case IP_VERSION(6, 2, 0):
1134                 adev->nbio.funcs = &nbio_v6_1_funcs;
1135                 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
1136                 break;
1137         case IP_VERSION(7, 0, 0):
1138         case IP_VERSION(7, 0, 1):
1139         case IP_VERSION(2, 5, 0):
1140                 adev->nbio.funcs = &nbio_v7_0_funcs;
1141                 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
1142                 break;
1143         case IP_VERSION(7, 4, 0):
1144         case IP_VERSION(7, 4, 1):
1145                 adev->nbio.funcs = &nbio_v7_4_funcs;
1146                 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
1147                 break;
1148         case IP_VERSION(7, 4, 4):
1149                 adev->nbio.funcs = &nbio_v7_4_funcs;
1150                 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg_ald;
1151                 break;
1152         case IP_VERSION(7, 2, 0):
1153         case IP_VERSION(7, 2, 1):
1154         case IP_VERSION(7, 5, 0):
1155                 adev->nbio.funcs = &nbio_v7_2_funcs;
1156                 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
1157                 break;
1158         case IP_VERSION(2, 1, 1):
1159         case IP_VERSION(2, 3, 0):
1160         case IP_VERSION(2, 3, 1):
1161         case IP_VERSION(2, 3, 2):
1162                 adev->nbio.funcs = &nbio_v2_3_funcs;
1163                 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
1164                 break;
1165         case IP_VERSION(3, 3, 0):
1166         case IP_VERSION(3, 3, 1):
1167         case IP_VERSION(3, 3, 2):
1168         case IP_VERSION(3, 3, 3):
1169                 adev->nbio.funcs = &nbio_v2_3_funcs;
1170                 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg_sc;
1171                 break;
1172         default:
1173                 break;
1174         }
1175
1176         switch (adev->ip_versions[HDP_HWIP][0]) {
1177         case IP_VERSION(4, 0, 0):
1178         case IP_VERSION(4, 0, 1):
1179         case IP_VERSION(4, 1, 0):
1180         case IP_VERSION(4, 1, 1):
1181         case IP_VERSION(4, 1, 2):
1182         case IP_VERSION(4, 2, 0):
1183         case IP_VERSION(4, 2, 1):
1184         case IP_VERSION(4, 4, 0):
1185                 adev->hdp.funcs = &hdp_v4_0_funcs;
1186                 break;
1187         case IP_VERSION(5, 0, 0):
1188         case IP_VERSION(5, 0, 1):
1189         case IP_VERSION(5, 0, 2):
1190         case IP_VERSION(5, 0, 3):
1191         case IP_VERSION(5, 0, 4):
1192         case IP_VERSION(5, 2, 0):
1193                 adev->hdp.funcs = &hdp_v5_0_funcs;
1194                 break;
1195         default:
1196                 break;
1197         }
1198
1199         switch (adev->ip_versions[DF_HWIP][0]) {
1200         case IP_VERSION(3, 6, 0):
1201         case IP_VERSION(3, 6, 1):
1202         case IP_VERSION(3, 6, 2):
1203                 adev->df.funcs = &df_v3_6_funcs;
1204                 break;
1205         case IP_VERSION(2, 1, 0):
1206         case IP_VERSION(2, 1, 1):
1207         case IP_VERSION(2, 5, 0):
1208         case IP_VERSION(3, 5, 1):
1209         case IP_VERSION(3, 5, 2):
1210                 adev->df.funcs = &df_v1_7_funcs;
1211                 break;
1212         default:
1213                 break;
1214         }
1215
1216         switch (adev->ip_versions[SMUIO_HWIP][0]) {
1217         case IP_VERSION(9, 0, 0):
1218         case IP_VERSION(9, 0, 1):
1219         case IP_VERSION(10, 0, 0):
1220         case IP_VERSION(10, 0, 1):
1221         case IP_VERSION(10, 0, 2):
1222                 adev->smuio.funcs = &smuio_v9_0_funcs;
1223                 break;
1224         case IP_VERSION(11, 0, 0):
1225         case IP_VERSION(11, 0, 2):
1226         case IP_VERSION(11, 0, 3):
1227         case IP_VERSION(11, 0, 4):
1228         case IP_VERSION(11, 0, 7):
1229         case IP_VERSION(11, 0, 8):
1230                 adev->smuio.funcs = &smuio_v11_0_funcs;
1231                 break;
1232         case IP_VERSION(11, 0, 6):
1233         case IP_VERSION(11, 0, 10):
1234         case IP_VERSION(11, 0, 11):
1235         case IP_VERSION(11, 5, 0):
1236         case IP_VERSION(13, 0, 1):
1237                 adev->smuio.funcs = &smuio_v11_0_6_funcs;
1238                 break;
1239         case IP_VERSION(13, 0, 2):
1240                 adev->smuio.funcs = &smuio_v13_0_funcs;
1241                 break;
1242         default:
1243                 break;
1244         }
1245
1246         r = amdgpu_discovery_set_common_ip_blocks(adev);
1247         if (r)
1248                 return r;
1249
1250         r = amdgpu_discovery_set_gmc_ip_blocks(adev);
1251         if (r)
1252                 return r;
1253
1254         /* For SR-IOV, PSP needs to be initialized before IH */
1255         if (amdgpu_sriov_vf(adev)) {
1256                 r = amdgpu_discovery_set_psp_ip_blocks(adev);
1257                 if (r)
1258                         return r;
1259                 r = amdgpu_discovery_set_ih_ip_blocks(adev);
1260                 if (r)
1261                         return r;
1262         } else {
1263                 r = amdgpu_discovery_set_ih_ip_blocks(adev);
1264                 if (r)
1265                         return r;
1266
1267                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
1268                         r = amdgpu_discovery_set_psp_ip_blocks(adev);
1269                         if (r)
1270                                 return r;
1271                 }
1272         }
1273
1274         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
1275                 r = amdgpu_discovery_set_smu_ip_blocks(adev);
1276                 if (r)
1277                         return r;
1278         }
1279
1280         r = amdgpu_discovery_set_display_ip_blocks(adev);
1281         if (r)
1282                 return r;
1283
1284         r = amdgpu_discovery_set_gc_ip_blocks(adev);
1285         if (r)
1286                 return r;
1287
1288         r = amdgpu_discovery_set_sdma_ip_blocks(adev);
1289         if (r)
1290                 return r;
1291
1292         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
1293             !amdgpu_sriov_vf(adev)) {
1294                 r = amdgpu_discovery_set_smu_ip_blocks(adev);
1295                 if (r)
1296                         return r;
1297         }
1298
1299         r = amdgpu_discovery_set_mm_ip_blocks(adev);
1300         if (r)
1301                 return r;
1302
1303         if (adev->enable_mes) {
1304                 r = amdgpu_discovery_set_mes_ip_blocks(adev);
1305                 if (r)
1306                         return r;
1307         }
1308
1309         return 0;
1310 }
1311