drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

   1 /*
   2  * Copyright 2008 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jerome Glisse <[email protected]>
  26  */
  27
  28 #include <linux/file.h>
  29 #include <linux/pagemap.h>
  30 #include <linux/sync_file.h>
  31 #include <linux/dma-buf.h>
  32
  33 #include <drm/amdgpu_drm.h>
  34 #include <drm/drm_syncobj.h>
  35 #include "amdgpu.h"
  36 #include "amdgpu_trace.h"
  37 #include "amdgpu_gmc.h"
  38 #include "amdgpu_gem.h"
  39 #include "amdgpu_ras.h"
  40
  41 static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
  42                                       struct drm_amdgpu_cs_chunk_fence *data,
  43                                       uint32_t *offset)
  44 {
  45         struct drm_gem_object *gobj;
  46         struct amdgpu_bo *bo;
  47         unsigned long size;
  48         int r;
  49
  50         gobj = drm_gem_object_lookup(p->filp, data->handle);
  51         if (gobj == NULL)
  52                 return -EINVAL;
  53
  54         bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
  55         p->uf_entry.priority = 0;
  56         p->uf_entry.tv.bo = &bo->tbo;
  57         /* One for TTM and one for the CS job */
  58         p->uf_entry.tv.num_shared = 2;
  59
  60         drm_gem_object_put(gobj);
  61
  62         size = amdgpu_bo_size(bo);
  63         if (size != PAGE_SIZE || (data->offset + 8) > size) {
  64                 r = -EINVAL;
  65                 goto error_unref;
  66         }
  67
  68         if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
  69                 r = -EINVAL;
  70                 goto error_unref;
  71         }
  72
  73         *offset = data->offset;
  74
  75         return 0;
  76
  77 error_unref:
  78         amdgpu_bo_unref(&bo);
  79         return r;
  80 }
  81
  82 static int amdgpu_cs_bo_handles_chunk(struct amdgpu_cs_parser *p,
  83                                       struct drm_amdgpu_bo_list_in *data)
  84 {
  85         int r;
  86         struct drm_amdgpu_bo_list_entry *info = NULL;
  87
  88         r = amdgpu_bo_create_list_entry_array(data, &info);
  89         if (r)
  90                 return r;
  91
  92         r = amdgpu_bo_list_create(p->adev, p->filp, info, data->bo_number,
  93                                   &p->bo_list);
  94         if (r)
  95                 goto error_free;
  96
  97         kvfree(info);
  98         return 0;
  99
 100 error_free:
 101         kvfree(info);
 102
 103         return r;
 104 }
 105
 106 static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, union drm_amdgpu_cs *cs)
 107 {
 108         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 109         struct amdgpu_vm *vm = &fpriv->vm;
 110         uint64_t *chunk_array_user;
 111         uint64_t *chunk_array;
 112         unsigned size, num_ibs = 0;
 113         uint32_t uf_offset = 0;
 114         int i;
 115         int ret;
 116
 117         if (cs->in.num_chunks == 0)
 118                 return 0;
 119
 120         chunk_array = kvmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
 121         if (!chunk_array)
 122                 return -ENOMEM;
 123
 124         p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
 125         if (!p->ctx) {
 126                 ret = -EINVAL;
 127                 goto free_chunk;
 128         }
 129
 130         mutex_lock(&p->ctx->lock);
 131
 132         /* skip guilty context job */
 133         if (atomic_read(&p->ctx->guilty) == 1) {
 134                 ret = -ECANCELED;
 135                 goto free_chunk;
 136         }
 137
 138         /* get chunks */
 139         chunk_array_user = u64_to_user_ptr(cs->in.chunks);
 140         if (copy_from_user(chunk_array, chunk_array_user,
 141                            sizeof(uint64_t)*cs->in.num_chunks)) {
 142                 ret = -EFAULT;
 143                 goto free_chunk;
 144         }
 145
 146         p->nchunks = cs->in.num_chunks;
 147         p->chunks = kvmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
 148                             GFP_KERNEL);
 149         if (!p->chunks) {
 150                 ret = -ENOMEM;
 151                 goto free_chunk;
 152         }
 153
 154         for (i = 0; i < p->nchunks; i++) {
 155                 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
 156                 struct drm_amdgpu_cs_chunk user_chunk;
 157                 uint32_t __user *cdata;
 158
 159                 chunk_ptr = u64_to_user_ptr(chunk_array[i]);
 160                 if (copy_from_user(&user_chunk, chunk_ptr,
 161                                        sizeof(struct drm_amdgpu_cs_chunk))) {
 162                         ret = -EFAULT;
 163                         i--;
 164                         goto free_partial_kdata;
 165                 }
 166                 p->chunks[i].chunk_id = user_chunk.chunk_id;
 167                 p->chunks[i].length_dw = user_chunk.length_dw;
 168
 169                 size = p->chunks[i].length_dw;
 170                 cdata = u64_to_user_ptr(user_chunk.chunk_data);
 171
 172                 p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
 173                 if (p->chunks[i].kdata == NULL) {
 174                         ret = -ENOMEM;
 175                         i--;
 176                         goto free_partial_kdata;
 177                 }
 178                 size *= sizeof(uint32_t);
 179                 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
 180                         ret = -EFAULT;
 181                         goto free_partial_kdata;
 182                 }
 183
 184                 switch (p->chunks[i].chunk_id) {
 185                 case AMDGPU_CHUNK_ID_IB:
 186                         ++num_ibs;
 187                         break;
 188
 189                 case AMDGPU_CHUNK_ID_FENCE:
 190                         size = sizeof(struct drm_amdgpu_cs_chunk_fence);
 191                         if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
 192                                 ret = -EINVAL;
 193                                 goto free_partial_kdata;
 194                         }
 195
 196                         ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata,
 197                                                          &uf_offset);
 198                         if (ret)
 199                                 goto free_partial_kdata;
 200
 201                         break;
 202
 203                 case AMDGPU_CHUNK_ID_BO_HANDLES:
 204                         size = sizeof(struct drm_amdgpu_bo_list_in);
 205                         if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
 206                                 ret = -EINVAL;
 207                                 goto free_partial_kdata;
 208                         }
 209
 210                         ret = amdgpu_cs_bo_handles_chunk(p, p->chunks[i].kdata);
 211                         if (ret)
 212                                 goto free_partial_kdata;
 213
 214                         break;
 215
 216                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
 217                 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
 218                 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
 219                 case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
 220                 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
 221                 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
 222                         break;
 223
 224                 default:
 225                         ret = -EINVAL;
 226                         goto free_partial_kdata;
 227                 }
 228         }
 229
 230         ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm);
 231         if (ret)
 232                 goto free_all_kdata;
 233
 234         if (p->ctx->vram_lost_counter != p->job->vram_lost_counter) {
 235                 ret = -ECANCELED;
 236                 goto free_all_kdata;
 237         }
 238
 239         if (p->uf_entry.tv.bo)
 240                 p->job->uf_addr = uf_offset;
 241         kvfree(chunk_array);
 242
 243         /* Use this opportunity to fill in task info for the vm */
 244         amdgpu_vm_set_task_info(vm);
 245
 246         return 0;
 247
 248 free_all_kdata:
 249         i = p->nchunks - 1;
 250 free_partial_kdata:
 251         for (; i >= 0; i--)
 252                 kvfree(p->chunks[i].kdata);
 253         kvfree(p->chunks);
 254         p->chunks = NULL;
 255         p->nchunks = 0;
 256 free_chunk:
 257         kvfree(chunk_array);
 258
 259         return ret;
 260 }
 261
 262 /* Convert microseconds to bytes. */
 263 static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)
 264 {
 265         if (us <= 0 || !adev->mm_stats.log2_max_MBps)
 266                 return 0;
 267
 268         /* Since accum_us is incremented by a million per second, just
 269          * multiply it by the number of MB/s to get the number of bytes.
 270          */
 271         return us << adev->mm_stats.log2_max_MBps;
 272 }
 273
 274 static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)
 275 {
 276         if (!adev->mm_stats.log2_max_MBps)
 277                 return 0;
 278
 279         return bytes >> adev->mm_stats.log2_max_MBps;
 280 }
 281
 282 /* Returns how many bytes TTM can move right now. If no bytes can be moved,
 283  * it returns 0. If it returns non-zero, it's OK to move at least one buffer,
 284  * which means it can go over the threshold once. If that happens, the driver
 285  * will be in debt and no other buffer migrations can be done until that debt
 286  * is repaid.
 287  *
 288  * This approach allows moving a buffer of any size (it's important to allow
 289  * that).
 290  *
 291  * The currency is simply time in microseconds and it increases as the clock
 292  * ticks. The accumulated microseconds (us) are converted to bytes and
 293  * returned.
 294  */
 295 static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
 296                                               u64 *max_bytes,
 297                                               u64 *max_vis_bytes)
 298 {
 299         s64 time_us, increment_us;
 300         u64 free_vram, total_vram, used_vram;
 301         struct ttm_resource_manager *vram_man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
 302         /* Allow a maximum of 200 accumulated ms. This is basically per-IB
 303          * throttling.
 304          *
 305          * It means that in order to get full max MBps, at least 5 IBs per
 306          * second must be submitted and not more than 200ms apart from each
 307          * other.
 308          */
 309         const s64 us_upper_bound = 200000;
 310
 311         if (!adev->mm_stats.log2_max_MBps) {
 312                 *max_bytes = 0;
 313                 *max_vis_bytes = 0;
 314                 return;
 315         }
 316
 317         total_vram = adev->gmc.real_vram_size - atomic64_read(&adev->vram_pin_size);
 318         used_vram = amdgpu_vram_mgr_usage(vram_man);
 319         free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
 320
 321         spin_lock(&adev->mm_stats.lock);
 322
 323         /* Increase the amount of accumulated us. */
 324         time_us = ktime_to_us(ktime_get());
 325         increment_us = time_us - adev->mm_stats.last_update_us;
 326         adev->mm_stats.last_update_us = time_us;
 327         adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,
 328                                       us_upper_bound);
 329
 330         /* This prevents the short period of low performance when the VRAM
 331          * usage is low and the driver is in debt or doesn't have enough
 332          * accumulated us to fill VRAM quickly.
 333          *
 334          * The situation can occur in these cases:
 335          * - a lot of VRAM is freed by userspace
 336          * - the presence of a big buffer causes a lot of evictions
 337          *   (solution: split buffers into smaller ones)
 338          *
 339          * If 128 MB or 1/8th of VRAM is free, start filling it now by setting
 340          * accum_us to a positive number.
 341          */
 342         if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) {
 343                 s64 min_us;
 344
 345                 /* Be more aggresive on dGPUs. Try to fill a portion of free
 346                  * VRAM now.
 347                  */
 348                 if (!(adev->flags & AMD_IS_APU))
 349                         min_us = bytes_to_us(adev, free_vram / 4);
 350                 else
 351                         min_us = 0; /* Reset accum_us on APUs. */
 352
 353                 adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us);
 354         }
 355
 356         /* This is set to 0 if the driver is in debt to disallow (optional)
 357          * buffer moves.
 358          */
 359         *max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);
 360
 361         /* Do the same for visible VRAM if half of it is free */
 362         if (!amdgpu_gmc_vram_full_visible(&adev->gmc)) {
 363                 u64 total_vis_vram = adev->gmc.visible_vram_size;
 364                 u64 used_vis_vram =
 365                   amdgpu_vram_mgr_vis_usage(vram_man);
 366
 367                 if (used_vis_vram < total_vis_vram) {
 368                         u64 free_vis_vram = total_vis_vram - used_vis_vram;
 369                         adev->mm_stats.accum_us_vis = min(adev->mm_stats.accum_us_vis +
 370                                                           increment_us, us_upper_bound);
 371
 372                         if (free_vis_vram >= total_vis_vram / 2)
 373                                 adev->mm_stats.accum_us_vis =
 374                                         max(bytes_to_us(adev, free_vis_vram / 2),
 375                                             adev->mm_stats.accum_us_vis);
 376                 }
 377
 378                 *max_vis_bytes = us_to_bytes(adev, adev->mm_stats.accum_us_vis);
 379         } else {
 380                 *max_vis_bytes = 0;
 381         }
 382
 383         spin_unlock(&adev->mm_stats.lock);
 384 }
 385
 386 /* Report how many bytes have really been moved for the last command
 387  * submission. This can result in a debt that can stop buffer migrations
 388  * temporarily.
 389  */
 390 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
 391                                   u64 num_vis_bytes)
 392 {
 393         spin_lock(&adev->mm_stats.lock);
 394         adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
 395         adev->mm_stats.accum_us_vis -= bytes_to_us(adev, num_vis_bytes);
 396         spin_unlock(&adev->mm_stats.lock);
 397 }
 398
 399 static int amdgpu_cs_bo_validate(void *param, struct amdgpu_bo *bo)
 400 {
 401         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 402         struct amdgpu_cs_parser *p = param;
 403         struct ttm_operation_ctx ctx = {
 404                 .interruptible = true,
 405                 .no_wait_gpu = false,
 406                 .resv = bo->tbo.base.resv
 407         };
 408         uint32_t domain;
 409         int r;
 410
 411         if (bo->tbo.pin_count)
 412                 return 0;
 413
 414         /* Don't move this buffer if we have depleted our allowance
 415          * to move it. Don't move anything if the threshold is zero.
 416          */
 417         if (p->bytes_moved < p->bytes_moved_threshold &&
 418             (!bo->tbo.base.dma_buf ||
 419             list_empty(&bo->tbo.base.dma_buf->attachments))) {
 420                 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 421                     (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
 422                         /* And don't move a CPU_ACCESS_REQUIRED BO to limited
 423                          * visible VRAM if we've depleted our allowance to do
 424                          * that.
 425                          */
 426                         if (p->bytes_moved_vis < p->bytes_moved_vis_threshold)
 427                                 domain = bo->preferred_domains;
 428                         else
 429                                 domain = bo->allowed_domains;
 430                 } else {
 431                         domain = bo->preferred_domains;
 432                 }
 433         } else {
 434                 domain = bo->allowed_domains;
 435         }
 436
 437 retry:
 438         amdgpu_bo_placement_from_domain(bo, domain);
 439         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 440
 441         p->bytes_moved += ctx.bytes_moved;
 442         if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 443             amdgpu_bo_in_cpu_visible_vram(bo))
 444                 p->bytes_moved_vis += ctx.bytes_moved;
 445
 446         if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
 447                 domain = bo->allowed_domains;
 448                 goto retry;
 449         }
 450
 451         return r;
 452 }
 453
 454 static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
 455                             struct list_head *validated)
 456 {
 457         struct ttm_operation_ctx ctx = { true, false };
 458         struct amdgpu_bo_list_entry *lobj;
 459         int r;
 460
 461         list_for_each_entry(lobj, validated, tv.head) {
 462                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(lobj->tv.bo);
 463                 struct mm_struct *usermm;
 464
 465                 usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
 466                 if (usermm && usermm != current->mm)
 467                         return -EPERM;
 468
 469                 if (amdgpu_ttm_tt_is_userptr(bo->tbo.ttm) &&
 470                     lobj->user_invalidated && lobj->user_pages) {
 471                         amdgpu_bo_placement_from_domain(bo,
 472                                                         AMDGPU_GEM_DOMAIN_CPU);
 473                         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 474                         if (r)
 475                                 return r;
 476
 477                         amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
 478                                                      lobj->user_pages);
 479                 }
 480
 481                 r = amdgpu_cs_bo_validate(p, bo);
 482                 if (r)
 483                         return r;
 484
 485                 kvfree(lobj->user_pages);
 486                 lobj->user_pages = NULL;
 487         }
 488         return 0;
 489 }
 490
 491 static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
 492                                 union drm_amdgpu_cs *cs)
 493 {
 494         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 495         struct amdgpu_vm *vm = &fpriv->vm;
 496         struct amdgpu_bo_list_entry *e;
 497         struct list_head duplicates;
 498         struct amdgpu_bo *gds;
 499         struct amdgpu_bo *gws;
 500         struct amdgpu_bo *oa;
 501         int r;
 502
 503         INIT_LIST_HEAD(&p->validated);
 504
 505         /* p->bo_list could already be assigned if AMDGPU_CHUNK_ID_BO_HANDLES is present */
 506         if (cs->in.bo_list_handle) {
 507                 if (p->bo_list)
 508                         return -EINVAL;
 509
 510                 r = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle,
 511                                        &p->bo_list);
 512                 if (r)
 513                         return r;
 514         } else if (!p->bo_list) {
 515                 /* Create a empty bo_list when no handle is provided */
 516                 r = amdgpu_bo_list_create(p->adev, p->filp, NULL, 0,
 517                                           &p->bo_list);
 518                 if (r)
 519                         return r;
 520         }
 521
 522         /* One for TTM and one for the CS job */
 523         amdgpu_bo_list_for_each_entry(e, p->bo_list)
 524                 e->tv.num_shared = 2;
 525
 526         amdgpu_bo_list_get_list(p->bo_list, &p->validated);
 527
 528         INIT_LIST_HEAD(&duplicates);
 529         amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
 530
 531         if (p->uf_entry.tv.bo && !ttm_to_amdgpu_bo(p->uf_entry.tv.bo)->parent)
 532                 list_add(&p->uf_entry.tv.head, &p->validated);
 533
 534         /* Get userptr backing pages. If pages are updated after registered
 535          * in amdgpu_gem_userptr_ioctl(), amdgpu_cs_list_validate() will do
 536          * amdgpu_ttm_backend_bind() to flush and invalidate new pages
 537          */
 538         amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
 539                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 540                 bool userpage_invalidated = false;
 541                 int i;
 542
 543                 e->user_pages = kvmalloc_array(bo->tbo.ttm->num_pages,
 544                                         sizeof(struct page *),
 545                                         GFP_KERNEL | __GFP_ZERO);
 546                 if (!e->user_pages) {
 547                         DRM_ERROR("kvmalloc_array failure\n");
 548                         return -ENOMEM;
 549                 }
 550
 551                 r = amdgpu_ttm_tt_get_user_pages(bo, e->user_pages);
 552                 if (r) {
 553                         kvfree(e->user_pages);
 554                         e->user_pages = NULL;
 555                         return r;
 556                 }
 557
 558                 for (i = 0; i < bo->tbo.ttm->num_pages; i++) {
 559                         if (bo->tbo.ttm->pages[i] != e->user_pages[i]) {
 560                                 userpage_invalidated = true;
 561                                 break;
 562                         }
 563                 }
 564                 e->user_invalidated = userpage_invalidated;
 565         }
 566
 567         r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
 568                                    &duplicates);
 569         if (unlikely(r != 0)) {
 570                 if (r != -ERESTARTSYS)
 571                         DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
 572                 goto out;
 573         }
 574
 575         amdgpu_bo_list_for_each_entry(e, p->bo_list) {
 576                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 577
 578                 e->bo_va = amdgpu_vm_bo_find(vm, bo);
 579
 580                 if (bo->tbo.base.dma_buf && !amdgpu_bo_explicit_sync(bo)) {
 581                         e->chain = dma_fence_chain_alloc();
 582                         if (!e->chain) {
 583                                 r = -ENOMEM;
 584                                 goto error_validate;
 585                         }
 586                 }
 587         }
 588
 589         amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold,
 590                                           &p->bytes_moved_vis_threshold);
 591         p->bytes_moved = 0;
 592         p->bytes_moved_vis = 0;
 593
 594         r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm,
 595                                       amdgpu_cs_bo_validate, p);
 596         if (r) {
 597                 DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
 598                 goto error_validate;
 599         }
 600
 601         r = amdgpu_cs_list_validate(p, &duplicates);
 602         if (r)
 603                 goto error_validate;
 604
 605         r = amdgpu_cs_list_validate(p, &p->validated);
 606         if (r)
 607                 goto error_validate;
 608
 609         amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved,
 610                                      p->bytes_moved_vis);
 611
 612         gds = p->bo_list->gds_obj;
 613         gws = p->bo_list->gws_obj;
 614         oa = p->bo_list->oa_obj;
 615
 616         if (gds) {
 617                 p->job->gds_base = amdgpu_bo_gpu_offset(gds) >> PAGE_SHIFT;
 618                 p->job->gds_size = amdgpu_bo_size(gds) >> PAGE_SHIFT;
 619         }
 620         if (gws) {
 621                 p->job->gws_base = amdgpu_bo_gpu_offset(gws) >> PAGE_SHIFT;
 622                 p->job->gws_size = amdgpu_bo_size(gws) >> PAGE_SHIFT;
 623         }
 624         if (oa) {
 625                 p->job->oa_base = amdgpu_bo_gpu_offset(oa) >> PAGE_SHIFT;
 626                 p->job->oa_size = amdgpu_bo_size(oa) >> PAGE_SHIFT;
 627         }
 628
 629         if (!r && p->uf_entry.tv.bo) {
 630                 struct amdgpu_bo *uf = ttm_to_amdgpu_bo(p->uf_entry.tv.bo);
 631
 632                 r = amdgpu_ttm_alloc_gart(&uf->tbo);
 633                 p->job->uf_addr += amdgpu_bo_gpu_offset(uf);
 634         }
 635
 636 error_validate:
 637         if (r) {
 638                 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
 639                         dma_fence_chain_free(e->chain);
 640                         e->chain = NULL;
 641                 }
 642                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 643         }
 644 out:
 645         return r;
 646 }
 647
 648 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
 649 {
 650         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 651         struct amdgpu_bo_list_entry *e;
 652         int r;
 653
 654         list_for_each_entry(e, &p->validated, tv.head) {
 655                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 656                 struct dma_resv *resv = bo->tbo.base.resv;
 657                 enum amdgpu_sync_mode sync_mode;
 658
 659                 sync_mode = amdgpu_bo_explicit_sync(bo) ?
 660                         AMDGPU_SYNC_EXPLICIT : AMDGPU_SYNC_NE_OWNER;
 661                 r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, sync_mode,
 662                                      &fpriv->vm);
 663                 if (r)
 664                         return r;
 665         }
 666         return 0;
 667 }
 668
 669 /**
 670  * amdgpu_cs_parser_fini() - clean parser states
 671  * @parser:     parser structure holding parsing context.
 672  * @error:      error number
 673  * @backoff:    indicator to backoff the reservation
 674  *
 675  * If error is set then unvalidate buffer, otherwise just free memory
 676  * used by parsing context.
 677  **/
 678 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error,
 679                                   bool backoff)
 680 {
 681         unsigned i;
 682
 683         if (error && backoff) {
 684                 struct amdgpu_bo_list_entry *e;
 685
 686                 amdgpu_bo_list_for_each_entry(e, parser->bo_list) {
 687                         dma_fence_chain_free(e->chain);
 688                         e->chain = NULL;
 689                 }
 690
 691                 ttm_eu_backoff_reservation(&parser->ticket,
 692                                            &parser->validated);
 693         }
 694
 695         for (i = 0; i < parser->num_post_deps; i++) {
 696                 drm_syncobj_put(parser->post_deps[i].syncobj);
 697                 kfree(parser->post_deps[i].chain);
 698         }
 699         kfree(parser->post_deps);
 700
 701         dma_fence_put(parser->fence);
 702
 703         if (parser->ctx) {
 704                 mutex_unlock(&parser->ctx->lock);
 705                 amdgpu_ctx_put(parser->ctx);
 706         }
 707         if (parser->bo_list)
 708                 amdgpu_bo_list_put(parser->bo_list);
 709
 710         for (i = 0; i < parser->nchunks; i++)
 711                 kvfree(parser->chunks[i].kdata);
 712         kvfree(parser->chunks);
 713         if (parser->job)
 714                 amdgpu_job_free(parser->job);
 715         if (parser->uf_entry.tv.bo) {
 716                 struct amdgpu_bo *uf = ttm_to_amdgpu_bo(parser->uf_entry.tv.bo);
 717
 718                 amdgpu_bo_unref(&uf);
 719         }
 720 }
 721
 722 static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
 723 {
 724         struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched);
 725         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 726         struct amdgpu_device *adev = p->adev;
 727         struct amdgpu_vm *vm = &fpriv->vm;
 728         struct amdgpu_bo_list_entry *e;
 729         struct amdgpu_bo_va *bo_va;
 730         struct amdgpu_bo *bo;
 731         int r;
 732
 733         /* Only for UVD/VCE VM emulation */
 734         if (ring->funcs->parse_cs || ring->funcs->patch_cs_in_place) {
 735                 unsigned i, j;
 736
 737                 for (i = 0, j = 0; i < p->nchunks && j < p->job->num_ibs; i++) {
 738                         struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 739                         struct amdgpu_bo_va_mapping *m;
 740                         struct amdgpu_bo *aobj = NULL;
 741                         struct amdgpu_cs_chunk *chunk;
 742                         uint64_t offset, va_start;
 743                         struct amdgpu_ib *ib;
 744                         uint8_t *kptr;
 745
 746                         chunk = &p->chunks[i];
 747                         ib = &p->job->ibs[j];
 748                         chunk_ib = chunk->kdata;
 749
 750                         if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 751                                 continue;
 752
 753                         va_start = chunk_ib->va_start & AMDGPU_GMC_HOLE_MASK;
 754                         r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m);
 755                         if (r) {
 756                                 DRM_ERROR("IB va_start is invalid\n");
 757                                 return r;
 758                         }
 759
 760                         if ((va_start + chunk_ib->ib_bytes) >
 761                             (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 762                                 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
 763                                 return -EINVAL;
 764                         }
 765
 766                         /* the IB should be reserved at this point */
 767                         r = amdgpu_bo_kmap(aobj, (void **)&kptr);
 768                         if (r) {
 769                                 return r;
 770                         }
 771
 772                         offset = m->start * AMDGPU_GPU_PAGE_SIZE;
 773                         kptr += va_start - offset;
 774
 775                         if (ring->funcs->parse_cs) {
 776                                 memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
 777                                 amdgpu_bo_kunmap(aobj);
 778
 779                                 r = amdgpu_ring_parse_cs(ring, p, j);
 780                                 if (r)
 781                                         return r;
 782                         } else {
 783                                 ib->ptr = (uint32_t *)kptr;
 784                                 r = amdgpu_ring_patch_cs_in_place(ring, p, j);
 785                                 amdgpu_bo_kunmap(aobj);
 786                                 if (r)
 787                                         return r;
 788                         }
 789
 790                         j++;
 791                 }
 792         }
 793
 794         if (!p->job->vm)
 795                 return amdgpu_cs_sync_rings(p);
 796
 797
 798         r = amdgpu_vm_clear_freed(adev, vm, NULL);
 799         if (r)
 800                 return r;
 801
 802         r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false, NULL);
 803         if (r)
 804                 return r;
 805
 806         r = amdgpu_sync_vm_fence(&p->job->sync, fpriv->prt_va->last_pt_update);
 807         if (r)
 808                 return r;
 809
 810         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
 811                 bo_va = fpriv->csa_va;
 812                 BUG_ON(!bo_va);
 813                 r = amdgpu_vm_bo_update(adev, bo_va, false, NULL);
 814                 if (r)
 815                         return r;
 816
 817                 r = amdgpu_sync_vm_fence(&p->job->sync, bo_va->last_pt_update);
 818                 if (r)
 819                         return r;
 820         }
 821
 822         amdgpu_bo_list_for_each_entry(e, p->bo_list) {
 823                 /* ignore duplicates */
 824                 bo = ttm_to_amdgpu_bo(e->tv.bo);
 825                 if (!bo)
 826                         continue;
 827
 828                 bo_va = e->bo_va;
 829                 if (bo_va == NULL)
 830                         continue;
 831
 832                 r = amdgpu_vm_bo_update(adev, bo_va, false, NULL);
 833                 if (r)
 834                         return r;
 835
 836                 r = amdgpu_sync_vm_fence(&p->job->sync, bo_va->last_pt_update);
 837                 if (r)
 838                         return r;
 839         }
 840
 841         r = amdgpu_vm_handle_moved(adev, vm);
 842         if (r)
 843                 return r;
 844
 845         r = amdgpu_vm_update_pdes(adev, vm, false);
 846         if (r)
 847                 return r;
 848
 849         r = amdgpu_sync_vm_fence(&p->job->sync, vm->last_update);
 850         if (r)
 851                 return r;
 852
 853         p->job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.bo);
 854
 855         if (amdgpu_vm_debug) {
 856                 /* Invalidate all BOs to test for userspace bugs */
 857                 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
 858                         struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 859
 860                         /* ignore duplicates */
 861                         if (!bo)
 862                                 continue;
 863
 864                         amdgpu_vm_bo_invalidate(adev, bo, false);
 865                 }
 866         }
 867
 868         return amdgpu_cs_sync_rings(p);
 869 }
 870
 871 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
 872                              struct amdgpu_cs_parser *parser)
 873 {
 874         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 875         struct amdgpu_vm *vm = &fpriv->vm;
 876         int r, ce_preempt = 0, de_preempt = 0;
 877         struct amdgpu_ring *ring;
 878         int i, j;
 879
 880         for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) {
 881                 struct amdgpu_cs_chunk *chunk;
 882                 struct amdgpu_ib *ib;
 883                 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 884                 struct drm_sched_entity *entity;
 885
 886                 chunk = &parser->chunks[i];
 887                 ib = &parser->job->ibs[j];
 888                 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
 889
 890                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 891                         continue;
 892
 893                 if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX &&
 894                     (amdgpu_mcbp || amdgpu_sriov_vf(adev))) {
 895                         if (chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
 896                                 if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
 897                                         ce_preempt++;
 898                                 else
 899                                         de_preempt++;
 900                         }
 901
 902                         /* each GFX command submit allows 0 or 1 IB preemptible for CE & DE */
 903                         if (ce_preempt > 1 || de_preempt > 1)
 904                                 return -EINVAL;
 905                 }
 906
 907                 r = amdgpu_ctx_get_entity(parser->ctx, chunk_ib->ip_type,
 908                                           chunk_ib->ip_instance, chunk_ib->ring,
 909                                           &entity);
 910                 if (r)
 911                         return r;
 912
 913                 if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE)
 914                         parser->job->preamble_status |=
 915                                 AMDGPU_PREAMBLE_IB_PRESENT;
 916
 917                 if (parser->entity && parser->entity != entity)
 918                         return -EINVAL;
 919
 920                 /* Return if there is no run queue associated with this entity.
 921                  * Possibly because of disabled HW IP*/
 922                 if (entity->rq == NULL)
 923                         return -EINVAL;
 924
 925                 parser->entity = entity;
 926
 927                 ring = to_amdgpu_ring(entity->rq->sched);
 928                 r =  amdgpu_ib_get(adev, vm, ring->funcs->parse_cs ?
 929                                    chunk_ib->ib_bytes : 0,
 930                                    AMDGPU_IB_POOL_DELAYED, ib);
 931                 if (r) {
 932                         DRM_ERROR("Failed to get ib !\n");
 933                         return r;
 934                 }
 935
 936                 ib->gpu_addr = chunk_ib->va_start;
 937                 ib->length_dw = chunk_ib->ib_bytes / 4;
 938                 ib->flags = chunk_ib->flags;
 939
 940                 j++;
 941         }
 942
 943         /* MM engine doesn't support user fences */
 944         ring = to_amdgpu_ring(parser->entity->rq->sched);
 945         if (parser->job->uf_addr && ring->funcs->no_user_fence)
 946                 return -EINVAL;
 947
 948         return amdgpu_ctx_wait_prev_fence(parser->ctx, parser->entity);
 949 }
 950
 951 static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,
 952                                        struct amdgpu_cs_chunk *chunk)
 953 {
 954         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 955         unsigned num_deps;
 956         int i, r;
 957         struct drm_amdgpu_cs_chunk_dep *deps;
 958
 959         deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
 960         num_deps = chunk->length_dw * 4 /
 961                 sizeof(struct drm_amdgpu_cs_chunk_dep);
 962
 963         for (i = 0; i < num_deps; ++i) {
 964                 struct amdgpu_ctx *ctx;
 965                 struct drm_sched_entity *entity;
 966                 struct dma_fence *fence;
 967
 968                 ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
 969                 if (ctx == NULL)
 970                         return -EINVAL;
 971
 972                 r = amdgpu_ctx_get_entity(ctx, deps[i].ip_type,
 973                                           deps[i].ip_instance,
 974                                           deps[i].ring, &entity);
 975                 if (r) {
 976                         amdgpu_ctx_put(ctx);
 977                         return r;
 978                 }
 979
 980                 fence = amdgpu_ctx_get_fence(ctx, entity, deps[i].handle);
 981                 amdgpu_ctx_put(ctx);
 982
 983                 if (IS_ERR(fence))
 984                         return PTR_ERR(fence);
 985                 else if (!fence)
 986                         continue;
 987
 988                 if (chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) {
 989                         struct drm_sched_fence *s_fence;
 990                         struct dma_fence *old = fence;
 991
 992                         s_fence = to_drm_sched_fence(fence);
 993                         fence = dma_fence_get(&s_fence->scheduled);
 994                         dma_fence_put(old);
 995                 }
 996
 997                 r = amdgpu_sync_fence(&p->job->sync, fence);
 998                 dma_fence_put(fence);
 999                 if (r)
1000                         return r;
1001         }
1002         return 0;
1003 }
1004
1005 static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,
1006                                                  uint32_t handle, u64 point,
1007                                                  u64 flags)
1008 {
1009         struct dma_fence *fence;
1010         int r;
1011
1012         r = drm_syncobj_find_fence(p->filp, handle, point, flags, &fence);
1013         if (r) {
1014                 DRM_ERROR("syncobj %u failed to find fence @ %llu (%d)!\n",
1015                           handle, point, r);
1016                 return r;
1017         }
1018
1019         r = amdgpu_sync_fence(&p->job->sync, fence);
1020         dma_fence_put(fence);
1021
1022         return r;
1023 }
1024
1025 static int amdgpu_cs_process_syncobj_in_dep(struct amdgpu_cs_parser *p,
1026                                             struct amdgpu_cs_chunk *chunk)
1027 {
1028         struct drm_amdgpu_cs_chunk_sem *deps;
1029         unsigned num_deps;
1030         int i, r;
1031
1032         deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1033         num_deps = chunk->length_dw * 4 /
1034                 sizeof(struct drm_amdgpu_cs_chunk_sem);
1035         for (i = 0; i < num_deps; ++i) {
1036                 r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle,
1037                                                           0, 0);
1038                 if (r)
1039                         return r;
1040         }
1041
1042         return 0;
1043 }
1044
1045
1046 static int amdgpu_cs_process_syncobj_timeline_in_dep(struct amdgpu_cs_parser *p,
1047                                                      struct amdgpu_cs_chunk *chunk)
1048 {
1049         struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps;
1050         unsigned num_deps;
1051         int i, r;
1052
1053         syncobj_deps = (struct drm_amdgpu_cs_chunk_syncobj *)chunk->kdata;
1054         num_deps = chunk->length_dw * 4 /
1055                 sizeof(struct drm_amdgpu_cs_chunk_syncobj);
1056         for (i = 0; i < num_deps; ++i) {
1057                 r = amdgpu_syncobj_lookup_and_add_to_sync(p,
1058                                                           syncobj_deps[i].handle,
1059                                                           syncobj_deps[i].point,
1060                                                           syncobj_deps[i].flags);
1061                 if (r)
1062                         return r;
1063         }
1064
1065         return 0;
1066 }
1067
1068 static int amdgpu_cs_process_syncobj_out_dep(struct amdgpu_cs_parser *p,
1069                                              struct amdgpu_cs_chunk *chunk)
1070 {
1071         struct drm_amdgpu_cs_chunk_sem *deps;
1072         unsigned num_deps;
1073         int i;
1074
1075         deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1076         num_deps = chunk->length_dw * 4 /
1077                 sizeof(struct drm_amdgpu_cs_chunk_sem);
1078
1079         if (p->post_deps)
1080                 return -EINVAL;
1081
1082         p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
1083                                      GFP_KERNEL);
1084         p->num_post_deps = 0;
1085
1086         if (!p->post_deps)
1087                 return -ENOMEM;
1088
1089
1090         for (i = 0; i < num_deps; ++i) {
1091                 p->post_deps[i].syncobj =
1092                         drm_syncobj_find(p->filp, deps[i].handle);
1093                 if (!p->post_deps[i].syncobj)
1094                         return -EINVAL;
1095                 p->post_deps[i].chain = NULL;
1096                 p->post_deps[i].point = 0;
1097                 p->num_post_deps++;
1098         }
1099
1100         return 0;
1101 }
1102
1103
1104 static int amdgpu_cs_process_syncobj_timeline_out_dep(struct amdgpu_cs_parser *p,
1105                                                       struct amdgpu_cs_chunk *chunk)
1106 {
1107         struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps;
1108         unsigned num_deps;
1109         int i;
1110
1111         syncobj_deps = (struct drm_amdgpu_cs_chunk_syncobj *)chunk->kdata;
1112         num_deps = chunk->length_dw * 4 /
1113                 sizeof(struct drm_amdgpu_cs_chunk_syncobj);
1114
1115         if (p->post_deps)
1116                 return -EINVAL;
1117
1118         p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
1119                                      GFP_KERNEL);
1120         p->num_post_deps = 0;
1121
1122         if (!p->post_deps)
1123                 return -ENOMEM;
1124
1125         for (i = 0; i < num_deps; ++i) {
1126                 struct amdgpu_cs_post_dep *dep = &p->post_deps[i];
1127
1128                 dep->chain = NULL;
1129                 if (syncobj_deps[i].point) {
1130                         dep->chain = dma_fence_chain_alloc();
1131                         if (!dep->chain)
1132                                 return -ENOMEM;
1133                 }
1134
1135                 dep->syncobj = drm_syncobj_find(p->filp,
1136                                                 syncobj_deps[i].handle);
1137                 if (!dep->syncobj) {
1138                         dma_fence_chain_free(dep->chain);
1139                         return -EINVAL;
1140                 }
1141                 dep->point = syncobj_deps[i].point;
1142                 p->num_post_deps++;
1143         }
1144
1145         return 0;
1146 }
1147
1148 static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
1149                                   struct amdgpu_cs_parser *p)
1150 {
1151         int i, r;
1152
1153         for (i = 0; i < p->nchunks; ++i) {
1154                 struct amdgpu_cs_chunk *chunk;
1155
1156                 chunk = &p->chunks[i];
1157
1158                 switch (chunk->chunk_id) {
1159                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
1160                 case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
1161                         r = amdgpu_cs_process_fence_dep(p, chunk);
1162                         if (r)
1163                                 return r;
1164                         break;
1165                 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
1166                         r = amdgpu_cs_process_syncobj_in_dep(p, chunk);
1167                         if (r)
1168                                 return r;
1169                         break;
1170                 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
1171                         r = amdgpu_cs_process_syncobj_out_dep(p, chunk);
1172                         if (r)
1173                                 return r;
1174                         break;
1175                 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
1176                         r = amdgpu_cs_process_syncobj_timeline_in_dep(p, chunk);
1177                         if (r)
1178                                 return r;
1179                         break;
1180                 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
1181                         r = amdgpu_cs_process_syncobj_timeline_out_dep(p, chunk);
1182                         if (r)
1183                                 return r;
1184                         break;
1185                 }
1186         }
1187
1188         return 0;
1189 }
1190
1191 static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p)
1192 {
1193         int i;
1194
1195         for (i = 0; i < p->num_post_deps; ++i) {
1196                 if (p->post_deps[i].chain && p->post_deps[i].point) {
1197                         drm_syncobj_add_point(p->post_deps[i].syncobj,
1198                                               p->post_deps[i].chain,
1199                                               p->fence, p->post_deps[i].point);
1200                         p->post_deps[i].chain = NULL;
1201                 } else {
1202                         drm_syncobj_replace_fence(p->post_deps[i].syncobj,
1203                                                   p->fence);
1204                 }
1205         }
1206 }
1207
1208 static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
1209                             union drm_amdgpu_cs *cs)
1210 {
1211         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1212         struct drm_sched_entity *entity = p->entity;
1213         struct amdgpu_bo_list_entry *e;
1214         struct amdgpu_job *job;
1215         uint64_t seq;
1216         int r;
1217
1218         job = p->job;
1219         p->job = NULL;
1220
1221         r = drm_sched_job_init(&job->base, entity, &fpriv->vm);
1222         if (r)
1223                 goto error_unlock;
1224
1225         drm_sched_job_arm(&job->base);
1226
1227         /* No memory allocation is allowed while holding the notifier lock.
1228          * The lock is held until amdgpu_cs_submit is finished and fence is
1229          * added to BOs.
1230          */
1231         mutex_lock(&p->adev->notifier_lock);
1232
1233         /* If userptr are invalidated after amdgpu_cs_parser_bos(), return
1234          * -EAGAIN, drmIoctl in libdrm will restart the amdgpu_cs_ioctl.
1235          */
1236         amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
1237                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
1238
1239                 r |= !amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
1240         }
1241         if (r) {
1242                 r = -EAGAIN;
1243                 goto error_abort;
1244         }
1245
1246         p->fence = dma_fence_get(&job->base.s_fence->finished);
1247
1248         amdgpu_ctx_add_fence(p->ctx, entity, p->fence, &seq);
1249         amdgpu_cs_post_dependencies(p);
1250
1251         if ((job->preamble_status & AMDGPU_PREAMBLE_IB_PRESENT) &&
1252             !p->ctx->preamble_presented) {
1253                 job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;
1254                 p->ctx->preamble_presented = true;
1255         }
1256
1257         cs->out.handle = seq;
1258         job->uf_sequence = seq;
1259
1260         amdgpu_job_free_resources(job);
1261
1262         trace_amdgpu_cs_ioctl(job);
1263         amdgpu_vm_bo_trace_cs(&fpriv->vm, &p->ticket);
1264         drm_sched_entity_push_job(&job->base);
1265
1266         amdgpu_vm_move_to_lru_tail(p->adev, &fpriv->vm);
1267
1268         amdgpu_bo_list_for_each_entry(e, p->bo_list) {
1269                 struct dma_resv *resv = e->tv.bo->base.resv;
1270                 struct dma_fence_chain *chain = e->chain;
1271
1272                 if (!chain)
1273                         continue;
1274
1275                 /*
1276                  * Work around dma_resv shortcommings by wrapping up the
1277                  * submission in a dma_fence_chain and add it as exclusive
1278                  * fence, but first add the submission as shared fence to make
1279                  * sure that shared fences never signal before the exclusive
1280                  * one.
1281                  */
1282                 dma_fence_chain_init(chain, dma_resv_excl_fence(resv),
1283                                      dma_fence_get(p->fence), 1);
1284
1285                 dma_resv_add_shared_fence(resv, p->fence);
1286                 rcu_assign_pointer(resv->fence_excl, &chain->base);
1287                 e->chain = NULL;
1288         }
1289
1290         ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence);
1291         mutex_unlock(&p->adev->notifier_lock);
1292
1293         return 0;
1294
1295 error_abort:
1296         drm_sched_job_cleanup(&job->base);
1297         mutex_unlock(&p->adev->notifier_lock);
1298
1299 error_unlock:
1300         amdgpu_job_free(job);
1301         return r;
1302 }
1303
1304 static void trace_amdgpu_cs_ibs(struct amdgpu_cs_parser *parser)
1305 {
1306         int i;
1307
1308         if (!trace_amdgpu_cs_enabled())
1309                 return;
1310
1311         for (i = 0; i < parser->job->num_ibs; i++)
1312                 trace_amdgpu_cs(parser, i);
1313 }
1314
1315 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
1316 {
1317         struct amdgpu_device *adev = drm_to_adev(dev);
1318         union drm_amdgpu_cs *cs = data;
1319         struct amdgpu_cs_parser parser = {};
1320         bool reserved_buffers = false;
1321         int r;
1322
1323         if (amdgpu_ras_intr_triggered())
1324                 return -EHWPOISON;
1325
1326         if (!adev->accel_working)
1327                 return -EBUSY;
1328
1329         parser.adev = adev;
1330         parser.filp = filp;
1331
1332         r = amdgpu_cs_parser_init(&parser, data);
1333         if (r) {
1334                 if (printk_ratelimit())
1335                         DRM_ERROR("Failed to initialize parser %d!\n", r);
1336                 goto out;
1337         }
1338
1339         r = amdgpu_cs_ib_fill(adev, &parser);
1340         if (r)
1341                 goto out;
1342
1343         r = amdgpu_cs_dependencies(adev, &parser);
1344         if (r) {
1345                 DRM_ERROR("Failed in the dependencies handling %d!\n", r);
1346                 goto out;
1347         }
1348
1349         r = amdgpu_cs_parser_bos(&parser, data);
1350         if (r) {
1351                 if (r == -ENOMEM)
1352                         DRM_ERROR("Not enough memory for command submission!\n");
1353                 else if (r != -ERESTARTSYS && r != -EAGAIN)
1354                         DRM_ERROR("Failed to process the buffer list %d!\n", r);
1355                 goto out;
1356         }
1357
1358         reserved_buffers = true;
1359
1360         trace_amdgpu_cs_ibs(&parser);
1361
1362         r = amdgpu_cs_vm_handling(&parser);
1363         if (r)
1364                 goto out;
1365
1366         r = amdgpu_cs_submit(&parser, cs);
1367
1368 out:
1369         amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
1370
1371         return r;
1372 }
1373
1374 /**
1375  * amdgpu_cs_wait_ioctl - wait for a command submission to finish
1376  *
1377  * @dev: drm device
1378  * @data: data from userspace
1379  * @filp: file private
1380  *
1381  * Wait for the command submission identified by handle to finish.
1382  */
1383 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
1384                          struct drm_file *filp)
1385 {
1386         union drm_amdgpu_wait_cs *wait = data;
1387         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
1388         struct drm_sched_entity *entity;
1389         struct amdgpu_ctx *ctx;
1390         struct dma_fence *fence;
1391         long r;
1392
1393         ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
1394         if (ctx == NULL)
1395                 return -EINVAL;
1396
1397         r = amdgpu_ctx_get_entity(ctx, wait->in.ip_type, wait->in.ip_instance,
1398                                   wait->in.ring, &entity);
1399         if (r) {
1400                 amdgpu_ctx_put(ctx);
1401                 return r;
1402         }
1403
1404         fence = amdgpu_ctx_get_fence(ctx, entity, wait->in.handle);
1405         if (IS_ERR(fence))
1406                 r = PTR_ERR(fence);
1407         else if (fence) {
1408                 r = dma_fence_wait_timeout(fence, true, timeout);
1409                 if (r > 0 && fence->error)
1410                         r = fence->error;
1411                 dma_fence_put(fence);
1412         } else
1413                 r = 1;
1414
1415         amdgpu_ctx_put(ctx);
1416         if (r < 0)
1417                 return r;
1418
1419         memset(wait, 0, sizeof(*wait));
1420         wait->out.status = (r == 0);
1421
1422         return 0;
1423 }
1424
1425 /**
1426  * amdgpu_cs_get_fence - helper to get fence from drm_amdgpu_fence
1427  *
1428  * @adev: amdgpu device
1429  * @filp: file private
1430  * @user: drm_amdgpu_fence copied from user space
1431  */
1432 static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev,
1433                                              struct drm_file *filp,
1434                                              struct drm_amdgpu_fence *user)
1435 {
1436         struct drm_sched_entity *entity;
1437         struct amdgpu_ctx *ctx;
1438         struct dma_fence *fence;
1439         int r;
1440
1441         ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id);
1442         if (ctx == NULL)
1443                 return ERR_PTR(-EINVAL);
1444
1445         r = amdgpu_ctx_get_entity(ctx, user->ip_type, user->ip_instance,
1446                                   user->ring, &entity);
1447         if (r) {
1448                 amdgpu_ctx_put(ctx);
1449                 return ERR_PTR(r);
1450         }
1451
1452         fence = amdgpu_ctx_get_fence(ctx, entity, user->seq_no);
1453         amdgpu_ctx_put(ctx);
1454
1455         return fence;
1456 }
1457
1458 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
1459                                     struct drm_file *filp)
1460 {
1461         struct amdgpu_device *adev = drm_to_adev(dev);
1462         union drm_amdgpu_fence_to_handle *info = data;
1463         struct dma_fence *fence;
1464         struct drm_syncobj *syncobj;
1465         struct sync_file *sync_file;
1466         int fd, r;
1467
1468         fence = amdgpu_cs_get_fence(adev, filp, &info->in.fence);
1469         if (IS_ERR(fence))
1470                 return PTR_ERR(fence);
1471
1472         if (!fence)
1473                 fence = dma_fence_get_stub();
1474
1475         switch (info->in.what) {
1476         case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
1477                 r = drm_syncobj_create(&syncobj, 0, fence);
1478                 dma_fence_put(fence);
1479                 if (r)
1480                         return r;
1481                 r = drm_syncobj_get_handle(filp, syncobj, &info->out.handle);
1482                 drm_syncobj_put(syncobj);
1483                 return r;
1484
1485         case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD:
1486                 r = drm_syncobj_create(&syncobj, 0, fence);
1487                 dma_fence_put(fence);
1488                 if (r)
1489                         return r;
1490                 r = drm_syncobj_get_fd(syncobj, (int *)&info->out.handle);
1491                 drm_syncobj_put(syncobj);
1492                 return r;
1493
1494         case AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD:
1495                 fd = get_unused_fd_flags(O_CLOEXEC);
1496                 if (fd < 0) {
1497                         dma_fence_put(fence);
1498                         return fd;
1499                 }
1500
1501                 sync_file = sync_file_create(fence);
1502                 dma_fence_put(fence);
1503                 if (!sync_file) {
1504                         put_unused_fd(fd);
1505                         return -ENOMEM;
1506                 }
1507
1508                 fd_install(fd, sync_file->file);
1509                 info->out.handle = fd;
1510                 return 0;
1511
1512         default:
1513                 return -EINVAL;
1514         }
1515 }
1516
1517 /**
1518  * amdgpu_cs_wait_all_fences - wait on all fences to signal
1519  *
1520  * @adev: amdgpu device
1521  * @filp: file private
1522  * @wait: wait parameters
1523  * @fences: array of drm_amdgpu_fence
1524  */
1525 static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
1526                                      struct drm_file *filp,
1527                                      union drm_amdgpu_wait_fences *wait,
1528                                      struct drm_amdgpu_fence *fences)
1529 {
1530         uint32_t fence_count = wait->in.fence_count;
1531         unsigned int i;
1532         long r = 1;
1533
1534         for (i = 0; i < fence_count; i++) {
1535                 struct dma_fence *fence;
1536                 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1537
1538                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1539                 if (IS_ERR(fence))
1540                         return PTR_ERR(fence);
1541                 else if (!fence)
1542                         continue;
1543
1544                 r = dma_fence_wait_timeout(fence, true, timeout);
1545                 dma_fence_put(fence);
1546                 if (r < 0)
1547                         return r;
1548
1549                 if (r == 0)
1550                         break;
1551
1552                 if (fence->error)
1553                         return fence->error;
1554         }
1555
1556         memset(wait, 0, sizeof(*wait));
1557         wait->out.status = (r > 0);
1558
1559         return 0;
1560 }
1561
1562 /**
1563  * amdgpu_cs_wait_any_fence - wait on any fence to signal
1564  *
1565  * @adev: amdgpu device
1566  * @filp: file private
1567  * @wait: wait parameters
1568  * @fences: array of drm_amdgpu_fence
1569  */
1570 static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev,
1571                                     struct drm_file *filp,
1572                                     union drm_amdgpu_wait_fences *wait,
1573                                     struct drm_amdgpu_fence *fences)
1574 {
1575         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1576         uint32_t fence_count = wait->in.fence_count;
1577         uint32_t first = ~0;
1578         struct dma_fence **array;
1579         unsigned int i;
1580         long r;
1581
1582         /* Prepare the fence array */
1583         array = kcalloc(fence_count, sizeof(struct dma_fence *), GFP_KERNEL);
1584
1585         if (array == NULL)
1586                 return -ENOMEM;
1587
1588         for (i = 0; i < fence_count; i++) {
1589                 struct dma_fence *fence;
1590
1591                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1592                 if (IS_ERR(fence)) {
1593                         r = PTR_ERR(fence);
1594                         goto err_free_fence_array;
1595                 } else if (fence) {
1596                         array[i] = fence;
1597                 } else { /* NULL, the fence has been already signaled */
1598                         r = 1;
1599                         first = i;
1600                         goto out;
1601                 }
1602         }
1603
1604         r = dma_fence_wait_any_timeout(array, fence_count, true, timeout,
1605                                        &first);
1606         if (r < 0)
1607                 goto err_free_fence_array;
1608
1609 out:
1610         memset(wait, 0, sizeof(*wait));
1611         wait->out.status = (r > 0);
1612         wait->out.first_signaled = first;
1613
1614         if (first < fence_count && array[first])
1615                 r = array[first]->error;
1616         else
1617                 r = 0;
1618
1619 err_free_fence_array:
1620         for (i = 0; i < fence_count; i++)
1621                 dma_fence_put(array[i]);
1622         kfree(array);
1623
1624         return r;
1625 }
1626
1627 /**
1628  * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to finish
1629  *
1630  * @dev: drm device
1631  * @data: data from userspace
1632  * @filp: file private
1633  */
1634 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1635                                 struct drm_file *filp)
1636 {
1637         struct amdgpu_device *adev = drm_to_adev(dev);
1638         union drm_amdgpu_wait_fences *wait = data;
1639         uint32_t fence_count = wait->in.fence_count;
1640         struct drm_amdgpu_fence *fences_user;
1641         struct drm_amdgpu_fence *fences;
1642         int r;
1643
1644         /* Get the fences from userspace */
1645         fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence),
1646                         GFP_KERNEL);
1647         if (fences == NULL)
1648                 return -ENOMEM;
1649
1650         fences_user = u64_to_user_ptr(wait->in.fences);
1651         if (copy_from_user(fences, fences_user,
1652                 sizeof(struct drm_amdgpu_fence) * fence_count)) {
1653                 r = -EFAULT;
1654                 goto err_free_fences;
1655         }
1656
1657         if (wait->in.wait_all)
1658                 r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences);
1659         else
1660                 r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences);
1661
1662 err_free_fences:
1663         kfree(fences);
1664
1665         return r;
1666 }
1667
1668 /**
1669  * amdgpu_cs_find_mapping - find bo_va for VM address
1670  *
1671  * @parser: command submission parser context
1672  * @addr: VM address
1673  * @bo: resulting BO of the mapping found
1674  * @map: Placeholder to return found BO mapping
1675  *
1676  * Search the buffer objects in the command submission context for a certain
1677  * virtual memory address. Returns allocation structure when found, NULL
1678  * otherwise.
1679  */
1680 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1681                            uint64_t addr, struct amdgpu_bo **bo,
1682                            struct amdgpu_bo_va_mapping **map)
1683 {
1684         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
1685         struct ttm_operation_ctx ctx = { false, false };
1686         struct amdgpu_vm *vm = &fpriv->vm;
1687         struct amdgpu_bo_va_mapping *mapping;
1688         int r;
1689
1690         addr /= AMDGPU_GPU_PAGE_SIZE;
1691
1692         mapping = amdgpu_vm_bo_lookup_mapping(vm, addr);
1693         if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo)
1694                 return -EINVAL;
1695
1696         *bo = mapping->bo_va->base.bo;
1697         *map = mapping;
1698
1699         /* Double check that the BO is reserved by this CS */
1700         if (dma_resv_locking_ctx((*bo)->tbo.base.resv) != &parser->ticket)
1701                 return -EINVAL;
1702
1703         if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {
1704                 (*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1705                 amdgpu_bo_placement_from_domain(*bo, (*bo)->allowed_domains);
1706                 r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, &ctx);
1707                 if (r)
1708                         return r;
1709         }
1710
1711         return amdgpu_ttm_alloc_gart(&(*bo)->tbo);
1712 }