drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_vcn.h"
  27 #include "amdgpu_pm.h"
  28 #include "soc15.h"
  29 #include "soc15d.h"
  30 #include "vcn_v2_0.h"
  31 #include "mmsch_v3_0.h"
  32
  33 #include "vcn/vcn_3_0_0_offset.h"
  34 #include "vcn/vcn_3_0_0_sh_mask.h"
  35 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
  36
  37 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET                        0x27
  38 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET                    0x0f
  39 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET                  0x10
  40 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET                  0x11
  41 #define mmUVD_NO_OP_INTERNAL_OFFSET                             0x29
  42 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET                       0x66
  43 #define mmUVD_SCRATCH9_INTERNAL_OFFSET                          0xc01d
  44
  45 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET                   0x431
  46 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET          0x3b4
  47 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET         0x3b5
  48 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET                       0x25c
  49
  50 #define VCN_INSTANCES_SIENNA_CICHLID                            2
  51 #define DEC_SW_RING_ENABLED                                     FALSE
  52
  53 #define RDECODE_MSG_CREATE                                      0x00000000
  54 #define RDECODE_MESSAGE_CREATE                                  0x00000001
  55
  56 static int amdgpu_ih_clientid_vcns[] = {
  57         SOC15_IH_CLIENTID_VCN,
  58         SOC15_IH_CLIENTID_VCN1
  59 };
  60
  61 static int amdgpu_ucode_id_vcns[] = {
  62         AMDGPU_UCODE_ID_VCN,
  63         AMDGPU_UCODE_ID_VCN1
  64 };
  65
  66 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev);
  67 static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev);
  68 static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev);
  69 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev);
  70 static int vcn_v3_0_set_powergating_state(void *handle,
  71                         enum amd_powergating_state state);
  72 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
  73                         int inst_idx, struct dpg_pause_state *new_state);
  74
  75 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring);
  76 static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring);
  77
  78 /**
  79  * vcn_v3_0_early_init - set function pointers
  80  *
  81  * @handle: amdgpu_device pointer
  82  *
  83  * Set ring and irq function pointers
  84  */
  85 static int vcn_v3_0_early_init(void *handle)
  86 {
  87         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  88
  89         if (amdgpu_sriov_vf(adev)) {
  90                 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID;
  91                 adev->vcn.harvest_config = 0;
  92                 adev->vcn.num_enc_rings = 1;
  93
  94         if (adev->asic_type == CHIP_BEIGE_GOBY) {
  95                 adev->vcn.num_vcn_inst = 1;
  96                 adev->vcn.num_enc_rings = 0;
  97         }
  98
  99         } else {
 100                 if (adev->asic_type == CHIP_SIENNA_CICHLID) {
 101                         u32 harvest;
 102                         int i;
 103
 104                         adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID;
 105                         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 106                                 harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING);
 107                                 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
 108                                         adev->vcn.harvest_config |= 1 << i;
 109                         }
 110
 111                         if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 |
 112                                                 AMDGPU_VCN_HARVEST_VCN1))
 113                                 /* both instances are harvested, disable the block */
 114                                 return -ENOENT;
 115                 } else
 116                         adev->vcn.num_vcn_inst = 1;
 117
 118                 if (adev->asic_type == CHIP_BEIGE_GOBY)
 119                         adev->vcn.num_enc_rings = 0;
 120                 else
 121                         adev->vcn.num_enc_rings = 2;
 122         }
 123
 124         vcn_v3_0_set_dec_ring_funcs(adev);
 125         vcn_v3_0_set_enc_ring_funcs(adev);
 126         vcn_v3_0_set_irq_funcs(adev);
 127
 128         return 0;
 129 }
 130
 131 /**
 132  * vcn_v3_0_sw_init - sw init for VCN block
 133  *
 134  * @handle: amdgpu_device pointer
 135  *
 136  * Load firmware and sw initialization
 137  */
 138 static int vcn_v3_0_sw_init(void *handle)
 139 {
 140         struct amdgpu_ring *ring;
 141         int i, j, r;
 142         int vcn_doorbell_index = 0;
 143         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 144
 145         r = amdgpu_vcn_sw_init(adev);
 146         if (r)
 147                 return r;
 148
 149         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 150                 const struct common_firmware_header *hdr;
 151                 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
 152                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
 153                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
 154                 adev->firmware.fw_size +=
 155                         ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
 156
 157                 if (adev->vcn.num_vcn_inst == VCN_INSTANCES_SIENNA_CICHLID) {
 158                         adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].ucode_id = AMDGPU_UCODE_ID_VCN1;
 159                         adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].fw = adev->vcn.fw;
 160                         adev->firmware.fw_size +=
 161                                 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
 162                 }
 163                 DRM_INFO("PSP loading VCN firmware\n");
 164         }
 165
 166         r = amdgpu_vcn_resume(adev);
 167         if (r)
 168                 return r;
 169
 170         /*
 171          * Note: doorbell assignment is fixed for SRIOV multiple VCN engines
 172          * Formula:
 173          *   vcn_db_base  = adev->doorbell_index.vcn.vcn_ring0_1 << 1;
 174          *   dec_ring_i   = vcn_db_base + i * (adev->vcn.num_enc_rings + 1)
 175          *   enc_ring_i,j = vcn_db_base + i * (adev->vcn.num_enc_rings + 1) + 1 + j
 176          */
 177         if (amdgpu_sriov_vf(adev)) {
 178                 vcn_doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1;
 179                 /* get DWORD offset */
 180                 vcn_doorbell_index = vcn_doorbell_index << 1;
 181         }
 182
 183         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 184                 volatile struct amdgpu_fw_shared *fw_shared;
 185
 186                 if (adev->vcn.harvest_config & (1 << i))
 187                         continue;
 188
 189                 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
 190                 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
 191                 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
 192                 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
 193                 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
 194                 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
 195
 196                 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
 197                 adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9);
 198                 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
 199                 adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0);
 200                 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
 201                 adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1);
 202                 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
 203                 adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD);
 204                 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
 205                 adev->vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP);
 206
 207                 /* VCN DEC TRAP */
 208                 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
 209                                 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[i].irq);
 210                 if (r)
 211                         return r;
 212
 213                 atomic_set(&adev->vcn.inst[i].sched_score, 0);
 214
 215                 ring = &adev->vcn.inst[i].ring_dec;
 216                 ring->use_doorbell = true;
 217                 if (amdgpu_sriov_vf(adev)) {
 218                         ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1);
 219                 } else {
 220                         ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i;
 221                 }
 222                 sprintf(ring->name, "vcn_dec_%d", i);
 223                 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
 224                                      AMDGPU_RING_PRIO_DEFAULT,
 225                                      &adev->vcn.inst[i].sched_score);
 226                 if (r)
 227                         return r;
 228
 229                 for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
 230                         /* VCN ENC TRAP */
 231                         r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
 232                                 j + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);
 233                         if (r)
 234                                 return r;
 235
 236                         ring = &adev->vcn.inst[i].ring_enc[j];
 237                         ring->use_doorbell = true;
 238                         if (amdgpu_sriov_vf(adev)) {
 239                                 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1) + 1 + j;
 240                         } else {
 241                                 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 * i;
 242                         }
 243                         sprintf(ring->name, "vcn_enc_%d.%d", i, j);
 244                         r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
 245                                              AMDGPU_RING_PRIO_DEFAULT,
 246                                              &adev->vcn.inst[i].sched_score);
 247                         if (r)
 248                                 return r;
 249                 }
 250
 251                 fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;
 252                 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SW_RING_FLAG) |
 253                                              cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG) |
 254                                              cpu_to_le32(AMDGPU_VCN_FW_SHARED_FLAG_0_RB);
 255                 fw_shared->sw_ring.is_enabled = cpu_to_le32(DEC_SW_RING_ENABLED);
 256         }
 257
 258         if (amdgpu_sriov_vf(adev)) {
 259                 r = amdgpu_virt_alloc_mm_table(adev);
 260                 if (r)
 261                         return r;
 262         }
 263         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
 264                 adev->vcn.pause_dpg_mode = vcn_v3_0_pause_dpg_mode;
 265
 266         return 0;
 267 }
 268
 269 /**
 270  * vcn_v3_0_sw_fini - sw fini for VCN block
 271  *
 272  * @handle: amdgpu_device pointer
 273  *
 274  * VCN suspend and free up sw allocation
 275  */
 276 static int vcn_v3_0_sw_fini(void *handle)
 277 {
 278         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 279         int i, r;
 280
 281         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 282                 volatile struct amdgpu_fw_shared *fw_shared;
 283
 284                 if (adev->vcn.harvest_config & (1 << i))
 285                         continue;
 286                 fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;
 287                 fw_shared->present_flag_0 = 0;
 288                 fw_shared->sw_ring.is_enabled = false;
 289         }
 290
 291         if (amdgpu_sriov_vf(adev))
 292                 amdgpu_virt_free_mm_table(adev);
 293
 294         r = amdgpu_vcn_suspend(adev);
 295         if (r)
 296                 return r;
 297
 298         r = amdgpu_vcn_sw_fini(adev);
 299
 300         return r;
 301 }
 302
 303 /**
 304  * vcn_v3_0_hw_init - start and test VCN block
 305  *
 306  * @handle: amdgpu_device pointer
 307  *
 308  * Initialize the hardware, boot up the VCPU and do some testing
 309  */
 310 static int vcn_v3_0_hw_init(void *handle)
 311 {
 312         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 313         struct amdgpu_ring *ring;
 314         int i, j, r;
 315
 316         if (amdgpu_sriov_vf(adev)) {
 317                 r = vcn_v3_0_start_sriov(adev);
 318                 if (r)
 319                         goto done;
 320
 321                 /* initialize VCN dec and enc ring buffers */
 322                 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 323                         if (adev->vcn.harvest_config & (1 << i))
 324                                 continue;
 325
 326                         ring = &adev->vcn.inst[i].ring_dec;
 327                         if (ring->sched.ready) {
 328                                 ring->wptr = 0;
 329                                 ring->wptr_old = 0;
 330                                 vcn_v3_0_dec_ring_set_wptr(ring);
 331                         }
 332
 333                         for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
 334                                 ring = &adev->vcn.inst[i].ring_enc[j];
 335                                 if (ring->sched.ready) {
 336                                         ring->wptr = 0;
 337                                         ring->wptr_old = 0;
 338                                         vcn_v3_0_enc_ring_set_wptr(ring);
 339                                 }
 340                         }
 341                 }
 342         } else {
 343                 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 344                         if (adev->vcn.harvest_config & (1 << i))
 345                                 continue;
 346
 347                         ring = &adev->vcn.inst[i].ring_dec;
 348
 349                         adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
 350                                                      ring->doorbell_index, i);
 351
 352                         r = amdgpu_ring_test_helper(ring);
 353                         if (r)
 354                                 goto done;
 355
 356                         for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
 357                                 ring = &adev->vcn.inst[i].ring_enc[j];
 358                                 r = amdgpu_ring_test_helper(ring);
 359                                 if (r)
 360                                         goto done;
 361                         }
 362                 }
 363         }
 364
 365 done:
 366         if (!r)
 367                 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
 368                         (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
 369
 370         return r;
 371 }
 372
 373 /**
 374  * vcn_v3_0_hw_fini - stop the hardware block
 375  *
 376  * @handle: amdgpu_device pointer
 377  *
 378  * Stop the VCN block, mark ring as not ready any more
 379  */
 380 static int vcn_v3_0_hw_fini(void *handle)
 381 {
 382         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 383         struct amdgpu_ring *ring;
 384         int i;
 385
 386         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 387                 if (adev->vcn.harvest_config & (1 << i))
 388                         continue;
 389
 390                 ring = &adev->vcn.inst[i].ring_dec;
 391
 392                 if (!amdgpu_sriov_vf(adev)) {
 393                         if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
 394                                         (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
 395                                          RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
 396                                 vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
 397                         }
 398                 }
 399         }
 400
 401         return 0;
 402 }
 403
 404 /**
 405  * vcn_v3_0_suspend - suspend VCN block
 406  *
 407  * @handle: amdgpu_device pointer
 408  *
 409  * HW fini and suspend VCN block
 410  */
 411 static int vcn_v3_0_suspend(void *handle)
 412 {
 413         int r;
 414         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 415
 416         r = vcn_v3_0_hw_fini(adev);
 417         if (r)
 418                 return r;
 419
 420         r = amdgpu_vcn_suspend(adev);
 421
 422         return r;
 423 }
 424
 425 /**
 426  * vcn_v3_0_resume - resume VCN block
 427  *
 428  * @handle: amdgpu_device pointer
 429  *
 430  * Resume firmware and hw init VCN block
 431  */
 432 static int vcn_v3_0_resume(void *handle)
 433 {
 434         int r;
 435         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 436
 437         r = amdgpu_vcn_resume(adev);
 438         if (r)
 439                 return r;
 440
 441         r = vcn_v3_0_hw_init(adev);
 442
 443         return r;
 444 }
 445
 446 /**
 447  * vcn_v3_0_mc_resume - memory controller programming
 448  *
 449  * @adev: amdgpu_device pointer
 450  * @inst: instance number
 451  *
 452  * Let the VCN memory controller know it's offsets
 453  */
 454 static void vcn_v3_0_mc_resume(struct amdgpu_device *adev, int inst)
 455 {
 456         uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
 457         uint32_t offset;
 458
 459         /* cache window 0: fw */
 460         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 461                 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 462                         (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo));
 463                 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 464                         (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi));
 465                 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 0);
 466                 offset = 0;
 467         } else {
 468                 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 469                         lower_32_bits(adev->vcn.inst[inst].gpu_addr));
 470                 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 471                         upper_32_bits(adev->vcn.inst[inst].gpu_addr));
 472                 offset = size;
 473                 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0,
 474                         AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 475         }
 476         WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE0, size);
 477
 478         /* cache window 1: stack */
 479         WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 480                 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
 481         WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 482                 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
 483         WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET1, 0);
 484         WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
 485
 486         /* cache window 2: context */
 487         WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 488                 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 489         WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 490                 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 491         WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET2, 0);
 492         WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
 493
 494         /* non-cache window */
 495         WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,
 496                 lower_32_bits(adev->vcn.inst[inst].fw_shared_gpu_addr));
 497         WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,
 498                 upper_32_bits(adev->vcn.inst[inst].fw_shared_gpu_addr));
 499         WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_OFFSET0, 0);
 500         WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_SIZE0,
 501                 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)));
 502 }
 503
 504 static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
 505 {
 506         uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
 507         uint32_t offset;
 508
 509         /* cache window 0: fw */
 510         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 511                 if (!indirect) {
 512                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 513                                 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 514                                 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);
 515                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 516                                 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 517                                 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);
 518                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 519                                 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
 520                 } else {
 521                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 522                                 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
 523                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 524                                 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
 525                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 526                                 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
 527                 }
 528                 offset = 0;
 529         } else {
 530                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 531                         VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 532                         lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
 533                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 534                         VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 535                         upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
 536                 offset = size;
 537                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 538                         VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0),
 539                         AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
 540         }
 541
 542         if (!indirect)
 543                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 544                         VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
 545         else
 546                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 547                         VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
 548
 549         /* cache window 1: stack */
 550         if (!indirect) {
 551                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 552                         VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
 553                         lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
 554                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 555                         VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
 556                         upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
 557                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 558                         VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
 559         } else {
 560                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 561                         VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
 562                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 563                         VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
 564                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 565                         VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
 566         }
 567         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 568                         VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
 569
 570         /* cache window 2: context */
 571         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 572                         VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
 573                         lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
 574         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 575                         VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
 576                         upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
 577         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 578                         VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
 579         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 580                         VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
 581
 582         /* non-cache window */
 583         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 584                         VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
 585                         lower_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect);
 586         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 587                         VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
 588                         upper_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect);
 589         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 590                         VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
 591         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 592                         VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0),
 593                         AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect);
 594
 595         /* VCN global tiling registers */
 596         WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
 597                 UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
 598 }
 599
 600 static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int inst)
 601 {
 602         uint32_t data = 0;
 603
 604         if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
 605                 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 606                         | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
 607                         | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 608                         | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
 609                         | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 610                         | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT
 611                         | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
 612                         | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 613                         | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 614                         | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 615                         | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
 616                         | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT
 617                         | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
 618                         | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
 619
 620                 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);
 621                 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS,
 622                         UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF);
 623         } else {
 624                 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 625                         | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
 626                         | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 627                         | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
 628                         | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 629                         | 1 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT
 630                         | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
 631                         | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 632                         | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 633                         | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 634                         | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
 635                         | 1 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT
 636                         | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
 637                         | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
 638                 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);
 639                 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0,  0x3F3FFFFF);
 640         }
 641
 642         data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
 643         data &= ~0x103;
 644         if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
 645                 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON |
 646                         UVD_POWER_STATUS__UVD_PG_EN_MASK;
 647
 648         WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data);
 649 }
 650
 651 static void vcn_v3_0_enable_static_power_gating(struct amdgpu_device *adev, int inst)
 652 {
 653         uint32_t data;
 654
 655         if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
 656                 /* Before power off, this indicator has to be turned on */
 657                 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
 658                 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
 659                 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
 660                 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data);
 661
 662                 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 663                         | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
 664                         | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 665                         | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
 666                         | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 667                         | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT
 668                         | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
 669                         | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 670                         | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 671                         | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 672                         | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
 673                         | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT
 674                         | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
 675                         | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
 676                 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);
 677
 678                 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
 679                         | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
 680                         | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
 681                         | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
 682                         | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
 683                         | 2 << UVD_PGFSM_STATUS__UVDIRL_PWR_STATUS__SHIFT
 684                         | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT
 685                         | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
 686                         | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
 687                         | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT
 688                         | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT
 689                         | 2 << UVD_PGFSM_STATUS__UVDATD_PWR_STATUS__SHIFT
 690                         | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT
 691                         | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT);
 692                 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, data, 0x3F3FFFFF);
 693         }
 694 }
 695
 696 /**
 697  * vcn_v3_0_disable_clock_gating - disable VCN clock gating
 698  *
 699  * @adev: amdgpu_device pointer
 700  * @inst: instance number
 701  *
 702  * Disable clock gating for VCN block
 703  */
 704 static void vcn_v3_0_disable_clock_gating(struct amdgpu_device *adev, int inst)
 705 {
 706         uint32_t data;
 707
 708         /* VCN disable CGC */
 709         data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
 710         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 711                 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 712         else
 713                 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 714         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 715         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 716         WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
 717
 718         data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE);
 719         data &= ~(UVD_CGC_GATE__SYS_MASK
 720                 | UVD_CGC_GATE__UDEC_MASK
 721                 | UVD_CGC_GATE__MPEG2_MASK
 722                 | UVD_CGC_GATE__REGS_MASK
 723                 | UVD_CGC_GATE__RBC_MASK
 724                 | UVD_CGC_GATE__LMI_MC_MASK
 725                 | UVD_CGC_GATE__LMI_UMC_MASK
 726                 | UVD_CGC_GATE__IDCT_MASK
 727                 | UVD_CGC_GATE__MPRD_MASK
 728                 | UVD_CGC_GATE__MPC_MASK
 729                 | UVD_CGC_GATE__LBSI_MASK
 730                 | UVD_CGC_GATE__LRBBM_MASK
 731                 | UVD_CGC_GATE__UDEC_RE_MASK
 732                 | UVD_CGC_GATE__UDEC_CM_MASK
 733                 | UVD_CGC_GATE__UDEC_IT_MASK
 734                 | UVD_CGC_GATE__UDEC_DB_MASK
 735                 | UVD_CGC_GATE__UDEC_MP_MASK
 736                 | UVD_CGC_GATE__WCB_MASK
 737                 | UVD_CGC_GATE__VCPU_MASK
 738                 | UVD_CGC_GATE__MMSCH_MASK);
 739
 740         WREG32_SOC15(VCN, inst, mmUVD_CGC_GATE, data);
 741
 742         SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0,  0xFFFFFFFF);
 743
 744         data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
 745         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 746                 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 747                 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 748                 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 749                 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 750                 | UVD_CGC_CTRL__SYS_MODE_MASK
 751                 | UVD_CGC_CTRL__UDEC_MODE_MASK
 752                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 753                 | UVD_CGC_CTRL__REGS_MODE_MASK
 754                 | UVD_CGC_CTRL__RBC_MODE_MASK
 755                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 756                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 757                 | UVD_CGC_CTRL__IDCT_MODE_MASK
 758                 | UVD_CGC_CTRL__MPRD_MODE_MASK
 759                 | UVD_CGC_CTRL__MPC_MODE_MASK
 760                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 761                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 762                 | UVD_CGC_CTRL__WCB_MODE_MASK
 763                 | UVD_CGC_CTRL__VCPU_MODE_MASK
 764                 | UVD_CGC_CTRL__MMSCH_MODE_MASK);
 765         WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
 766
 767         data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE);
 768         data |= (UVD_SUVD_CGC_GATE__SRE_MASK
 769                 | UVD_SUVD_CGC_GATE__SIT_MASK
 770                 | UVD_SUVD_CGC_GATE__SMP_MASK
 771                 | UVD_SUVD_CGC_GATE__SCM_MASK
 772                 | UVD_SUVD_CGC_GATE__SDB_MASK
 773                 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
 774                 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
 775                 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
 776                 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
 777                 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
 778                 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
 779                 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
 780                 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
 781                 | UVD_SUVD_CGC_GATE__SCLR_MASK
 782                 | UVD_SUVD_CGC_GATE__ENT_MASK
 783                 | UVD_SUVD_CGC_GATE__IME_MASK
 784                 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
 785                 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
 786                 | UVD_SUVD_CGC_GATE__SITE_MASK
 787                 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
 788                 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
 789                 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
 790                 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
 791                 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK
 792                 | UVD_SUVD_CGC_GATE__EFC_MASK
 793                 | UVD_SUVD_CGC_GATE__SAOE_MASK
 794                 | UVD_SUVD_CGC_GATE__SRE_AV1_MASK
 795                 | UVD_SUVD_CGC_GATE__FBC_PCLK_MASK
 796                 | UVD_SUVD_CGC_GATE__FBC_CCLK_MASK
 797                 | UVD_SUVD_CGC_GATE__SCM_AV1_MASK
 798                 | UVD_SUVD_CGC_GATE__SMPA_MASK);
 799         WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data);
 800
 801         data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2);
 802         data |= (UVD_SUVD_CGC_GATE2__MPBE0_MASK
 803                 | UVD_SUVD_CGC_GATE2__MPBE1_MASK
 804                 | UVD_SUVD_CGC_GATE2__SIT_AV1_MASK
 805                 | UVD_SUVD_CGC_GATE2__SDB_AV1_MASK
 806                 | UVD_SUVD_CGC_GATE2__MPC1_MASK);
 807         WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2, data);
 808
 809         data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL);
 810         data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 811                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 812                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 813                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 814                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 815                 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 816                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 817                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 818                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK
 819                 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK
 820                 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK
 821                 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK
 822                 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK
 823                 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK
 824                 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK
 825                 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK
 826                 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK
 827                 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK
 828                 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK);
 829         WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data);
 830 }
 831
 832 static void vcn_v3_0_clock_gating_dpg_mode(struct amdgpu_device *adev,
 833                 uint8_t sram_sel, int inst_idx, uint8_t indirect)
 834 {
 835         uint32_t reg_data = 0;
 836
 837         /* enable sw clock gating control */
 838         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 839                 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 840         else
 841                 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 842         reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 843         reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 844         reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
 845                  UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
 846                  UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
 847                  UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
 848                  UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
 849                  UVD_CGC_CTRL__SYS_MODE_MASK |
 850                  UVD_CGC_CTRL__UDEC_MODE_MASK |
 851                  UVD_CGC_CTRL__MPEG2_MODE_MASK |
 852                  UVD_CGC_CTRL__REGS_MODE_MASK |
 853                  UVD_CGC_CTRL__RBC_MODE_MASK |
 854                  UVD_CGC_CTRL__LMI_MC_MODE_MASK |
 855                  UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
 856                  UVD_CGC_CTRL__IDCT_MODE_MASK |
 857                  UVD_CGC_CTRL__MPRD_MODE_MASK |
 858                  UVD_CGC_CTRL__MPC_MODE_MASK |
 859                  UVD_CGC_CTRL__LBSI_MODE_MASK |
 860                  UVD_CGC_CTRL__LRBBM_MODE_MASK |
 861                  UVD_CGC_CTRL__WCB_MODE_MASK |
 862                  UVD_CGC_CTRL__VCPU_MODE_MASK |
 863                  UVD_CGC_CTRL__MMSCH_MODE_MASK);
 864         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 865                 VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
 866
 867         /* turn off clock gating */
 868         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 869                 VCN, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect);
 870
 871         /* turn on SUVD clock gating */
 872         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 873                 VCN, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
 874
 875         /* turn on sw mode in UVD_SUVD_CGC_CTRL */
 876         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 877                 VCN, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
 878 }
 879
 880 /**
 881  * vcn_v3_0_enable_clock_gating - enable VCN clock gating
 882  *
 883  * @adev: amdgpu_device pointer
 884  * @inst: instance number
 885  *
 886  * Enable clock gating for VCN block
 887  */
 888 static void vcn_v3_0_enable_clock_gating(struct amdgpu_device *adev, int inst)
 889 {
 890         uint32_t data;
 891
 892         /* enable VCN CGC */
 893         data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
 894         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 895                 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 896         else
 897                 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 898         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 899         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 900         WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
 901
 902         data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
 903         data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 904                 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 905                 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 906                 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 907                 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 908                 | UVD_CGC_CTRL__SYS_MODE_MASK
 909                 | UVD_CGC_CTRL__UDEC_MODE_MASK
 910                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 911                 | UVD_CGC_CTRL__REGS_MODE_MASK
 912                 | UVD_CGC_CTRL__RBC_MODE_MASK
 913                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 914                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 915                 | UVD_CGC_CTRL__IDCT_MODE_MASK
 916                 | UVD_CGC_CTRL__MPRD_MODE_MASK
 917                 | UVD_CGC_CTRL__MPC_MODE_MASK
 918                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 919                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 920                 | UVD_CGC_CTRL__WCB_MODE_MASK
 921                 | UVD_CGC_CTRL__VCPU_MODE_MASK
 922                 | UVD_CGC_CTRL__MMSCH_MODE_MASK);
 923         WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
 924
 925         data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL);
 926         data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 927                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 928                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 929                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 930                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 931                 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 932                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 933                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 934                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK
 935                 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK
 936                 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK
 937                 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK
 938                 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK
 939                 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK
 940                 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK
 941                 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK
 942                 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK
 943                 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK
 944                 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK);
 945         WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data);
 946 }
 947
 948 static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
 949 {
 950         volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr;
 951         struct amdgpu_ring *ring;
 952         uint32_t rb_bufsz, tmp;
 953
 954         /* disable register anti-hang mechanism */
 955         WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1,
 956                 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
 957         /* enable dynamic power gating mode */
 958         tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS);
 959         tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
 960         tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
 961         WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp);
 962
 963         if (indirect)
 964                 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
 965
 966         /* enable clock gating */
 967         vcn_v3_0_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);
 968
 969         /* enable VCPU clock */
 970         tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
 971         tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
 972         tmp |= UVD_VCPU_CNTL__BLK_RST_MASK;
 973         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 974                 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
 975
 976         /* disable master interupt */
 977         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 978                 VCN, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect);
 979
 980         /* setup mmUVD_LMI_CTRL */
 981         tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 982                 UVD_LMI_CTRL__REQ_MODE_MASK |
 983                 UVD_LMI_CTRL__CRC_RESET_MASK |
 984                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
 985                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 986                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 987                 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 988                 0x00100000L);
 989         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 990                 VCN, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect);
 991
 992         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 993                 VCN, inst_idx, mmUVD_MPC_CNTL),
 994                 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
 995
 996         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 997                 VCN, inst_idx, mmUVD_MPC_SET_MUXA0),
 998                 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
 999                  (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1000                  (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1001                  (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
1002
1003         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1004                 VCN, inst_idx, mmUVD_MPC_SET_MUXB0),
1005                  ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1006                  (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1007                  (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1008                  (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
1009
1010         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1011                 VCN, inst_idx, mmUVD_MPC_SET_MUX),
1012                 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1013                  (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1014                  (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
1015
1016         vcn_v3_0_mc_resume_dpg_mode(adev, inst_idx, indirect);
1017
1018         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1019                 VCN, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
1020         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1021                 VCN, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
1022
1023         /* enable LMI MC and UMC channels */
1024         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1025                 VCN, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect);
1026
1027         /* unblock VCPU register access */
1028         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1029                 VCN, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect);
1030
1031         tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
1032         tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
1033         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1034                 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
1035
1036         /* enable master interrupt */
1037         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1038                 VCN, inst_idx, mmUVD_MASTINT_EN),
1039                 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
1040
1041         /* add nop to workaround PSP size check */
1042         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1043                 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
1044
1045         if (indirect)
1046                 psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr,
1047                         (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -
1048                                 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr));
1049
1050         ring = &adev->vcn.inst[inst_idx].ring_dec;
1051         /* force RBC into idle state */
1052         rb_bufsz = order_base_2(ring->ring_size);
1053         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1054         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1055         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1056         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1057         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1058         WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp);
1059
1060         /* Stall DPG before WPTR/RPTR reset */
1061         WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
1062                 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
1063                 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1064         fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
1065
1066         /* set the write pointer delay */
1067         WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0);
1068
1069         /* set the wb address */
1070         WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR,
1071                 (upper_32_bits(ring->gpu_addr) >> 2));
1072
1073         /* programm the RB_BASE for ring buffer */
1074         WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1075                 lower_32_bits(ring->gpu_addr));
1076         WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1077                 upper_32_bits(ring->gpu_addr));
1078
1079         /* Initialize the ring buffer's read and write pointers */
1080         WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0);
1081
1082         WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0);
1083
1084         ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR);
1085         WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR,
1086                 lower_32_bits(ring->wptr));
1087
1088         /* Reset FW shared memory RBC WPTR/RPTR */
1089         fw_shared->rb.rptr = 0;
1090         fw_shared->rb.wptr = lower_32_bits(ring->wptr);
1091
1092         /*resetting done, fw can check RB ring */
1093         fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
1094
1095         /* Unstall DPG */
1096         WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
1097                 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1098
1099         return 0;
1100 }
1101
1102 static int vcn_v3_0_start(struct amdgpu_device *adev)
1103 {
1104         volatile struct amdgpu_fw_shared *fw_shared;
1105         struct amdgpu_ring *ring;
1106         uint32_t rb_bufsz, tmp;
1107         int i, j, k, r;
1108
1109         if (adev->pm.dpm_enabled)
1110                 amdgpu_dpm_enable_uvd(adev, true);
1111
1112         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1113                 if (adev->vcn.harvest_config & (1 << i))
1114                         continue;
1115
1116                 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG){
1117                         r = vcn_v3_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
1118                         continue;
1119                 }
1120
1121                 /* disable VCN power gating */
1122                 vcn_v3_0_disable_static_power_gating(adev, i);
1123
1124                 /* set VCN status busy */
1125                 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
1126                 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp);
1127
1128                 /*SW clock gating */
1129                 vcn_v3_0_disable_clock_gating(adev, i);
1130
1131                 /* enable VCPU clock */
1132                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
1133                         UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
1134
1135                 /* disable master interrupt */
1136                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0,
1137                         ~UVD_MASTINT_EN__VCPU_EN_MASK);
1138
1139                 /* enable LMI MC and UMC channels */
1140                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0,
1141                         ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1142
1143                 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);
1144                 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1145                 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1146                 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);
1147
1148                 /* setup mmUVD_LMI_CTRL */
1149                 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL);
1150                 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp |
1151                         UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1152                         UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1153                         UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1154                         UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
1155
1156                 /* setup mmUVD_MPC_CNTL */
1157                 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL);
1158                 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
1159                 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
1160                 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp);
1161
1162                 /* setup UVD_MPC_SET_MUXA0 */
1163                 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0,
1164                         ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1165                         (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1166                         (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1167                         (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
1168
1169                 /* setup UVD_MPC_SET_MUXB0 */
1170                 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0,
1171                         ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1172                         (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1173                         (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1174                         (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
1175
1176                 /* setup mmUVD_MPC_SET_MUX */
1177                 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX,
1178                         ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1179                         (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1180                         (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
1181
1182                 vcn_v3_0_mc_resume(adev, i);
1183
1184                 /* VCN global tiling registers */
1185                 WREG32_SOC15(VCN, i, mmUVD_GFX10_ADDR_CONFIG,
1186                         adev->gfx.config.gb_addr_config);
1187
1188                 /* unblock VCPU register access */
1189                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0,
1190                         ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1191
1192                 /* release VCPU reset to boot */
1193                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
1194                         ~UVD_VCPU_CNTL__BLK_RST_MASK);
1195
1196                 for (j = 0; j < 10; ++j) {
1197                         uint32_t status;
1198
1199                         for (k = 0; k < 100; ++k) {
1200                                 status = RREG32_SOC15(VCN, i, mmUVD_STATUS);
1201                                 if (status & 2)
1202                                         break;
1203                                 mdelay(10);
1204                         }
1205                         r = 0;
1206                         if (status & 2)
1207                                 break;
1208
1209                         DRM_ERROR("VCN[%d] decode not responding, trying to reset the VCPU!!!\n", i);
1210                         WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
1211                                 UVD_VCPU_CNTL__BLK_RST_MASK,
1212                                 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1213                         mdelay(10);
1214                         WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
1215                                 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1216
1217                         mdelay(10);
1218                         r = -1;
1219                 }
1220
1221                 if (r) {
1222                         DRM_ERROR("VCN[%d] decode not responding, giving up!!!\n", i);
1223                         return r;
1224                 }
1225
1226                 /* enable master interrupt */
1227                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN),
1228                         UVD_MASTINT_EN__VCPU_EN_MASK,
1229                         ~UVD_MASTINT_EN__VCPU_EN_MASK);
1230
1231                 /* clear the busy bit of VCN_STATUS */
1232                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0,
1233                         ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1234
1235                 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0);
1236
1237                 ring = &adev->vcn.inst[i].ring_dec;
1238                 /* force RBC into idle state */
1239                 rb_bufsz = order_base_2(ring->ring_size);
1240                 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1241                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1242                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1243                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1244                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1245                 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp);
1246
1247                 fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;
1248                 fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
1249
1250                 /* programm the RB_BASE for ring buffer */
1251                 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1252                         lower_32_bits(ring->gpu_addr));
1253                 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1254                         upper_32_bits(ring->gpu_addr));
1255
1256                 /* Initialize the ring buffer's read and write pointers */
1257                 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0);
1258
1259                 WREG32_SOC15(VCN, i, mmUVD_SCRATCH2, 0);
1260                 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);
1261                 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR,
1262                         lower_32_bits(ring->wptr));
1263                 fw_shared->rb.wptr = lower_32_bits(ring->wptr);
1264                 fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
1265
1266                 if (adev->asic_type != CHIP_BEIGE_GOBY) {
1267                         fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
1268                         ring = &adev->vcn.inst[i].ring_enc[0];
1269                         WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1270                         WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1271                         WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr);
1272                         WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1273                         WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4);
1274                         fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
1275
1276                         fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
1277                         ring = &adev->vcn.inst[i].ring_enc[1];
1278                         WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1279                         WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1280                         WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1281                         WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1282                         WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4);
1283                         fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
1284                 }
1285         }
1286
1287         return 0;
1288 }
1289
1290 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev)
1291 {
1292         int i, j;
1293         struct amdgpu_ring *ring;
1294         uint64_t cache_addr;
1295         uint64_t rb_addr;
1296         uint64_t ctx_addr;
1297         uint32_t param, resp, expected;
1298         uint32_t offset, cache_size;
1299         uint32_t tmp, timeout;
1300         uint32_t id;
1301
1302         struct amdgpu_mm_table *table = &adev->virt.mm_table;
1303         uint32_t *table_loc;
1304         uint32_t table_size;
1305         uint32_t size, size_dw;
1306
1307         bool is_vcn_ready;
1308
1309         struct mmsch_v3_0_cmd_direct_write
1310                 direct_wt = { {0} };
1311         struct mmsch_v3_0_cmd_direct_read_modify_write
1312                 direct_rd_mod_wt = { {0} };
1313         struct mmsch_v3_0_cmd_end end = { {0} };
1314         struct mmsch_v3_0_init_header header;
1315
1316         direct_wt.cmd_header.command_type =
1317                 MMSCH_COMMAND__DIRECT_REG_WRITE;
1318         direct_rd_mod_wt.cmd_header.command_type =
1319                 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
1320         end.cmd_header.command_type =
1321                 MMSCH_COMMAND__END;
1322
1323         header.version = MMSCH_VERSION;
1324         header.total_size = sizeof(struct mmsch_v3_0_init_header) >> 2;
1325         for (i = 0; i < AMDGPU_MAX_VCN_INSTANCES; i++) {
1326                 header.inst[i].init_status = 0;
1327                 header.inst[i].table_offset = 0;
1328                 header.inst[i].table_size = 0;
1329         }
1330
1331         table_loc = (uint32_t *)table->cpu_addr;
1332         table_loc += header.total_size;
1333         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1334                 if (adev->vcn.harvest_config & (1 << i))
1335                         continue;
1336
1337                 table_size = 0;
1338
1339                 MMSCH_V3_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i,
1340                         mmUVD_STATUS),
1341                         ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);
1342
1343                 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
1344
1345                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1346                         id = amdgpu_ucode_id_vcns[i];
1347                         MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1348                                 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1349                                 adev->firmware.ucode[id].tmr_mc_addr_lo);
1350                         MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1351                                 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1352                                 adev->firmware.ucode[id].tmr_mc_addr_hi);
1353                         offset = 0;
1354                         MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1355                                 mmUVD_VCPU_CACHE_OFFSET0),
1356                                 0);
1357                 } else {
1358                         MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1359                                 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1360                                 lower_32_bits(adev->vcn.inst[i].gpu_addr));
1361                         MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1362                                 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1363                                 upper_32_bits(adev->vcn.inst[i].gpu_addr));
1364                         offset = cache_size;
1365                         MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1366                                 mmUVD_VCPU_CACHE_OFFSET0),
1367                                 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
1368                 }
1369
1370                 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1371                         mmUVD_VCPU_CACHE_SIZE0),
1372                         cache_size);
1373
1374                 cache_addr = adev->vcn.inst[i].gpu_addr + offset;
1375                 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1376                         mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
1377                         lower_32_bits(cache_addr));
1378                 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1379                         mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
1380                         upper_32_bits(cache_addr));
1381                 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1382                         mmUVD_VCPU_CACHE_OFFSET1),
1383                         0);
1384                 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1385                         mmUVD_VCPU_CACHE_SIZE1),
1386                         AMDGPU_VCN_STACK_SIZE);
1387
1388                 cache_addr = adev->vcn.inst[i].gpu_addr + offset +
1389                         AMDGPU_VCN_STACK_SIZE;
1390                 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1391                         mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
1392                         lower_32_bits(cache_addr));
1393                 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1394                         mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
1395                         upper_32_bits(cache_addr));
1396                 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1397                         mmUVD_VCPU_CACHE_OFFSET2),
1398                         0);
1399                 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1400                         mmUVD_VCPU_CACHE_SIZE2),
1401                         AMDGPU_VCN_CONTEXT_SIZE);
1402
1403                 for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
1404                         ring = &adev->vcn.inst[i].ring_enc[j];
1405                         ring->wptr = 0;
1406                         rb_addr = ring->gpu_addr;
1407                         MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1408                                 mmUVD_RB_BASE_LO),
1409                                 lower_32_bits(rb_addr));
1410                         MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1411                                 mmUVD_RB_BASE_HI),
1412                                 upper_32_bits(rb_addr));
1413                         MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1414                                 mmUVD_RB_SIZE),
1415                                 ring->ring_size / 4);
1416                 }
1417
1418                 ring = &adev->vcn.inst[i].ring_dec;
1419                 ring->wptr = 0;
1420                 rb_addr = ring->gpu_addr;
1421                 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1422                         mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),
1423                         lower_32_bits(rb_addr));
1424                 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1425                         mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),
1426                         upper_32_bits(rb_addr));
1427                 /* force RBC into idle state */
1428                 tmp = order_base_2(ring->ring_size);
1429                 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp);
1430                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1431                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1432                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1433                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1434                 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1435                         mmUVD_RBC_RB_CNTL),
1436                         tmp);
1437
1438                 /* add end packet */
1439                 MMSCH_V3_0_INSERT_END();
1440
1441                 /* refine header */
1442                 header.inst[i].init_status = 0;
1443                 header.inst[i].table_offset = header.total_size;
1444                 header.inst[i].table_size = table_size;
1445                 header.total_size += table_size;
1446         }
1447
1448         /* Update init table header in memory */
1449         size = sizeof(struct mmsch_v3_0_init_header);
1450         table_loc = (uint32_t *)table->cpu_addr;
1451         memcpy((void *)table_loc, &header, size);
1452
1453         /* message MMSCH (in VCN[0]) to initialize this client
1454          * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr
1455          * of memory descriptor location
1456          */
1457         ctx_addr = table->gpu_addr;
1458         WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr));
1459         WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr));
1460
1461         /* 2, update vmid of descriptor */
1462         tmp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID);
1463         tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
1464         /* use domain0 for MM scheduler */
1465         tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
1466         WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, tmp);
1467
1468         /* 3, notify mmsch about the size of this descriptor */
1469         size = header.total_size;
1470         WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size);
1471
1472         /* 4, set resp to zero */
1473         WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0);
1474
1475         /* 5, kick off the initialization and wait until
1476          * MMSCH_VF_MAILBOX_RESP becomes non-zero
1477          */
1478         param = 0x10000001;
1479         WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, param);
1480         tmp = 0;
1481         timeout = 1000;
1482         resp = 0;
1483         expected = param + 1;
1484         while (resp != expected) {
1485                 resp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP);
1486                 if (resp == expected)
1487                         break;
1488
1489                 udelay(10);
1490                 tmp = tmp + 10;
1491                 if (tmp >= timeout) {
1492                         DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\
1493                                 " waiting for mmMMSCH_VF_MAILBOX_RESP "\
1494                                 "(expected=0x%08x, readback=0x%08x)\n",
1495                                 tmp, expected, resp);
1496                         return -EBUSY;
1497                 }
1498         }
1499
1500         /* 6, check each VCN's init_status
1501          * if it remains as 0, then this VCN is not assigned to current VF
1502          * do not start ring for this VCN
1503          */
1504         size = sizeof(struct mmsch_v3_0_init_header);
1505         table_loc = (uint32_t *)table->cpu_addr;
1506         memcpy(&header, (void *)table_loc, size);
1507
1508         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1509                 if (adev->vcn.harvest_config & (1 << i))
1510                         continue;
1511
1512                 is_vcn_ready = (header.inst[i].init_status == 1);
1513                 if (!is_vcn_ready)
1514                         DRM_INFO("VCN(%d) engine is disabled by hypervisor\n", i);
1515
1516                 ring = &adev->vcn.inst[i].ring_dec;
1517                 ring->sched.ready = is_vcn_ready;
1518                 for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
1519                         ring = &adev->vcn.inst[i].ring_enc[j];
1520                         ring->sched.ready = is_vcn_ready;
1521                 }
1522         }
1523
1524         return 0;
1525 }
1526
1527 static int vcn_v3_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
1528 {
1529         uint32_t tmp;
1530
1531         /* Wait for power status to be 1 */
1532         SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
1533                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1534
1535         /* wait for read ptr to be equal to write ptr */
1536         tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR);
1537         SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1538
1539         tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2);
1540         SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);
1541
1542         tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1543         SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);
1544
1545         SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
1546                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1547
1548         /* disable dynamic power gating mode */
1549         WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0,
1550                 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1551
1552         return 0;
1553 }
1554
1555 static int vcn_v3_0_stop(struct amdgpu_device *adev)
1556 {
1557         uint32_t tmp;
1558         int i, r = 0;
1559
1560         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1561                 if (adev->vcn.harvest_config & (1 << i))
1562                         continue;
1563
1564                 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1565                         r = vcn_v3_0_stop_dpg_mode(adev, i);
1566                         continue;
1567                 }
1568
1569                 /* wait for vcn idle */
1570                 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
1571                 if (r)
1572                         return r;
1573
1574                 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1575                         UVD_LMI_STATUS__READ_CLEAN_MASK |
1576                         UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1577                         UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1578                 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
1579                 if (r)
1580                         return r;
1581
1582                 /* disable LMI UMC channel */
1583                 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2);
1584                 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
1585                 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp);
1586                 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
1587                         UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1588                 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
1589                 if (r)
1590                         return r;
1591
1592                 /* block VCPU register access */
1593                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL),
1594                         UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
1595                         ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1596
1597                 /* reset VCPU */
1598                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
1599                         UVD_VCPU_CNTL__BLK_RST_MASK,
1600                         ~UVD_VCPU_CNTL__BLK_RST_MASK);
1601
1602                 /* disable VCPU clock */
1603                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
1604                         ~(UVD_VCPU_CNTL__CLK_EN_MASK));
1605
1606                 /* apply soft reset */
1607                 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);
1608                 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1609                 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);
1610                 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);
1611                 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1612                 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);
1613
1614                 /* clear status */
1615                 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0);
1616
1617                 /* apply HW clock gating */
1618                 vcn_v3_0_enable_clock_gating(adev, i);
1619
1620                 /* enable VCN power gating */
1621                 vcn_v3_0_enable_static_power_gating(adev, i);
1622         }
1623
1624         if (adev->pm.dpm_enabled)
1625                 amdgpu_dpm_enable_uvd(adev, false);
1626
1627         return 0;
1628 }
1629
1630 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
1631                    int inst_idx, struct dpg_pause_state *new_state)
1632 {
1633         volatile struct amdgpu_fw_shared *fw_shared;
1634         struct amdgpu_ring *ring;
1635         uint32_t reg_data = 0;
1636         int ret_code;
1637
1638         /* pause/unpause if state is changed */
1639         if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1640                 DRM_DEBUG("dpg pause state changed %d -> %d",
1641                         adev->vcn.inst[inst_idx].pause_state.fw_based,  new_state->fw_based);
1642                 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) &
1643                         (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1644
1645                 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1646                         ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1,
1647                                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1648
1649                         if (!ret_code) {
1650                                 /* pause DPG */
1651                                 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1652                                 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data);
1653
1654                                 /* wait for ACK */
1655                                 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE,
1656                                         UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1657                                         UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1658
1659                                 /* Stall DPG before WPTR/RPTR reset */
1660                                 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
1661                                         UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
1662                                         ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1663
1664                                 if (adev->asic_type != CHIP_BEIGE_GOBY) {
1665                                         /* Restore */
1666                                         fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr;
1667                                         fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
1668                                         ring = &adev->vcn.inst[inst_idx].ring_enc[0];
1669                                         ring->wptr = 0;
1670                                         WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr);
1671                                         WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1672                                         WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4);
1673                                         WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1674                                         WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1675                                         fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
1676
1677                                         fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
1678                                         ring = &adev->vcn.inst[inst_idx].ring_enc[1];
1679                                         ring->wptr = 0;
1680                                         WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1681                                         WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1682                                         WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4);
1683                                         WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1684                                         WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1685                                         fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
1686
1687                                         /* restore wptr/rptr with pointers saved in FW shared memory*/
1688                                         WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, fw_shared->rb.rptr);
1689                                         WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, fw_shared->rb.wptr);
1690                                 }
1691
1692                                 /* Unstall DPG */
1693                                 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
1694                                         0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1695
1696                                 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS,
1697                                         UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1698                         }
1699                 } else {
1700                         /* unpause dpg, no need to wait */
1701                         reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1702                         WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data);
1703                 }
1704                 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
1705         }
1706
1707         return 0;
1708 }
1709
1710 /**
1711  * vcn_v3_0_dec_ring_get_rptr - get read pointer
1712  *
1713  * @ring: amdgpu_ring pointer
1714  *
1715  * Returns the current hardware read pointer
1716  */
1717 static uint64_t vcn_v3_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
1718 {
1719         struct amdgpu_device *adev = ring->adev;
1720
1721         return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR);
1722 }
1723
1724 /**
1725  * vcn_v3_0_dec_ring_get_wptr - get write pointer
1726  *
1727  * @ring: amdgpu_ring pointer
1728  *
1729  * Returns the current hardware write pointer
1730  */
1731 static uint64_t vcn_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
1732 {
1733         struct amdgpu_device *adev = ring->adev;
1734
1735         if (ring->use_doorbell)
1736                 return adev->wb.wb[ring->wptr_offs];
1737         else
1738                 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR);
1739 }
1740
1741 /**
1742  * vcn_v3_0_dec_ring_set_wptr - set write pointer
1743  *
1744  * @ring: amdgpu_ring pointer
1745  *
1746  * Commits the write pointer to the hardware
1747  */
1748 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
1749 {
1750         struct amdgpu_device *adev = ring->adev;
1751         volatile struct amdgpu_fw_shared *fw_shared;
1752
1753         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1754                 /*whenever update RBC_RB_WPTR, we save the wptr in shared rb.wptr and scratch2 */
1755                 fw_shared = adev->vcn.inst[ring->me].fw_shared_cpu_addr;
1756                 fw_shared->rb.wptr = lower_32_bits(ring->wptr);
1757                 WREG32_SOC15(VCN, ring->me, mmUVD_SCRATCH2,
1758                         lower_32_bits(ring->wptr));
1759         }
1760
1761         if (ring->use_doorbell) {
1762                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1763                 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1764         } else {
1765                 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1766         }
1767 }
1768
1769 static void vcn_v3_0_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1770                                 u64 seq, uint32_t flags)
1771 {
1772         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1773
1774         amdgpu_ring_write(ring, VCN_DEC_SW_CMD_FENCE);
1775         amdgpu_ring_write(ring, addr);
1776         amdgpu_ring_write(ring, upper_32_bits(addr));
1777         amdgpu_ring_write(ring, seq);
1778         amdgpu_ring_write(ring, VCN_DEC_SW_CMD_TRAP);
1779 }
1780
1781 static void vcn_v3_0_dec_sw_ring_insert_end(struct amdgpu_ring *ring)
1782 {
1783         amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END);
1784 }
1785
1786 static void vcn_v3_0_dec_sw_ring_emit_ib(struct amdgpu_ring *ring,
1787                                struct amdgpu_job *job,
1788                                struct amdgpu_ib *ib,
1789                                uint32_t flags)
1790 {
1791         uint32_t vmid = AMDGPU_JOB_GET_VMID(job);
1792
1793         amdgpu_ring_write(ring, VCN_DEC_SW_CMD_IB);
1794         amdgpu_ring_write(ring, vmid);
1795         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1796         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1797         amdgpu_ring_write(ring, ib->length_dw);
1798 }
1799
1800 static void vcn_v3_0_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1801                                 uint32_t val, uint32_t mask)
1802 {
1803         amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WAIT);
1804         amdgpu_ring_write(ring, reg << 2);
1805         amdgpu_ring_write(ring, mask);
1806         amdgpu_ring_write(ring, val);
1807 }
1808
1809 static void vcn_v3_0_dec_sw_ring_emit_vm_flush(struct amdgpu_ring *ring,
1810                                 uint32_t vmid, uint64_t pd_addr)
1811 {
1812         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1813         uint32_t data0, data1, mask;
1814
1815         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1816
1817         /* wait for register write */
1818         data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance;
1819         data1 = lower_32_bits(pd_addr);
1820         mask = 0xffffffff;
1821         vcn_v3_0_dec_sw_ring_emit_reg_wait(ring, data0, data1, mask);
1822 }
1823
1824 static void vcn_v3_0_dec_sw_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
1825 {
1826         amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WRITE);
1827         amdgpu_ring_write(ring, reg << 2);
1828         amdgpu_ring_write(ring, val);
1829 }
1830
1831 static const struct amdgpu_ring_funcs vcn_v3_0_dec_sw_ring_vm_funcs = {
1832         .type = AMDGPU_RING_TYPE_VCN_DEC,
1833         .align_mask = 0x3f,
1834         .nop = VCN_DEC_SW_CMD_NO_OP,
1835         .vmhub = AMDGPU_MMHUB_0,
1836         .get_rptr = vcn_v3_0_dec_ring_get_rptr,
1837         .get_wptr = vcn_v3_0_dec_ring_get_wptr,
1838         .set_wptr = vcn_v3_0_dec_ring_set_wptr,
1839         .emit_frame_size =
1840                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1841                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1842                 4 + /* vcn_v3_0_dec_sw_ring_emit_vm_flush */
1843                 5 + 5 + /* vcn_v3_0_dec_sw_ring_emit_fdec_swe x2 vm fdec_swe */
1844                 1, /* vcn_v3_0_dec_sw_ring_insert_end */
1845         .emit_ib_size = 5, /* vcn_v3_0_dec_sw_ring_emit_ib */
1846         .emit_ib = vcn_v3_0_dec_sw_ring_emit_ib,
1847         .emit_fence = vcn_v3_0_dec_sw_ring_emit_fence,
1848         .emit_vm_flush = vcn_v3_0_dec_sw_ring_emit_vm_flush,
1849         .test_ring = amdgpu_vcn_dec_sw_ring_test_ring,
1850         .test_ib = NULL,//amdgpu_vcn_dec_sw_ring_test_ib,
1851         .insert_nop = amdgpu_ring_insert_nop,
1852         .insert_end = vcn_v3_0_dec_sw_ring_insert_end,
1853         .pad_ib = amdgpu_ring_generic_pad_ib,
1854         .begin_use = amdgpu_vcn_ring_begin_use,
1855         .end_use = amdgpu_vcn_ring_end_use,
1856         .emit_wreg = vcn_v3_0_dec_sw_ring_emit_wreg,
1857         .emit_reg_wait = vcn_v3_0_dec_sw_ring_emit_reg_wait,
1858         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1859 };
1860
1861 static int vcn_v3_0_limit_sched(struct amdgpu_cs_parser *p)
1862 {
1863         struct drm_gpu_scheduler **scheds;
1864
1865         /* The create msg must be in the first IB submitted */
1866         if (atomic_read(&p->entity->fence_seq))
1867                 return -EINVAL;
1868
1869         scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_DEC]
1870                 [AMDGPU_RING_PRIO_DEFAULT].sched;
1871         drm_sched_entity_modify_sched(p->entity, scheds, 1);
1872         return 0;
1873 }
1874
1875 static int vcn_v3_0_dec_msg(struct amdgpu_cs_parser *p, uint64_t addr)
1876 {
1877         struct ttm_operation_ctx ctx = { false, false };
1878         struct amdgpu_bo_va_mapping *map;
1879         uint32_t *msg, num_buffers;
1880         struct amdgpu_bo *bo;
1881         uint64_t start, end;
1882         unsigned int i;
1883         void * ptr;
1884         int r;
1885
1886         addr &= AMDGPU_GMC_HOLE_MASK;
1887         r = amdgpu_cs_find_mapping(p, addr, &bo, &map);
1888         if (r) {
1889                 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
1890                 return r;
1891         }
1892
1893         start = map->start * AMDGPU_GPU_PAGE_SIZE;
1894         end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE;
1895         if (addr & 0x7) {
1896                 DRM_ERROR("VCN messages must be 8 byte aligned!\n");
1897                 return -EINVAL;
1898         }
1899
1900         bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
1901         amdgpu_bo_placement_from_domain(bo, bo->allowed_domains);
1902         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1903         if (r) {
1904                 DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r);
1905                 return r;
1906         }
1907
1908         r = amdgpu_bo_kmap(bo, &ptr);
1909         if (r) {
1910                 DRM_ERROR("Failed mapping the VCN message (%d)!\n", r);
1911                 return r;
1912         }
1913
1914         msg = ptr + addr - start;
1915
1916         /* Check length */
1917         if (msg[1] > end - addr) {
1918                 r = -EINVAL;
1919                 goto out;
1920         }
1921
1922         if (msg[3] != RDECODE_MSG_CREATE)
1923                 goto out;
1924
1925         num_buffers = msg[2];
1926         for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) {
1927                 uint32_t offset, size, *create;
1928
1929                 if (msg[0] != RDECODE_MESSAGE_CREATE)
1930                         continue;
1931
1932                 offset = msg[1];
1933                 size = msg[2];
1934
1935                 if (offset + size > end) {
1936                         r = -EINVAL;
1937                         goto out;
1938                 }
1939
1940                 create = ptr + addr + offset - start;
1941
1942                 /* H246, HEVC and VP9 can run on any instance */
1943                 if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11)
1944                         continue;
1945
1946                 r = vcn_v3_0_limit_sched(p);
1947                 if (r)
1948                         goto out;
1949         }
1950
1951 out:
1952         amdgpu_bo_kunmap(bo);
1953         return r;
1954 }
1955
1956 static int vcn_v3_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,
1957                                            uint32_t ib_idx)
1958 {
1959         struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched);
1960         struct amdgpu_ib *ib = &p->job->ibs[ib_idx];
1961         uint32_t msg_lo = 0, msg_hi = 0;
1962         unsigned i;
1963         int r;
1964
1965         /* The first instance can decode anything */
1966         if (!ring->me)
1967                 return 0;
1968
1969         for (i = 0; i < ib->length_dw; i += 2) {
1970                 uint32_t reg = amdgpu_get_ib_value(p, ib_idx, i);
1971                 uint32_t val = amdgpu_get_ib_value(p, ib_idx, i + 1);
1972
1973                 if (reg == PACKET0(p->adev->vcn.internal.data0, 0)) {
1974                         msg_lo = val;
1975                 } else if (reg == PACKET0(p->adev->vcn.internal.data1, 0)) {
1976                         msg_hi = val;
1977                 } else if (reg == PACKET0(p->adev->vcn.internal.cmd, 0) &&
1978                            val == 0) {
1979                         r = vcn_v3_0_dec_msg(p, ((u64)msg_hi) << 32 | msg_lo);
1980                         if (r)
1981                                 return r;
1982                 }
1983         }
1984         return 0;
1985 }
1986
1987 static const struct amdgpu_ring_funcs vcn_v3_0_dec_ring_vm_funcs = {
1988         .type = AMDGPU_RING_TYPE_VCN_DEC,
1989         .align_mask = 0xf,
1990         .vmhub = AMDGPU_MMHUB_0,
1991         .get_rptr = vcn_v3_0_dec_ring_get_rptr,
1992         .get_wptr = vcn_v3_0_dec_ring_get_wptr,
1993         .set_wptr = vcn_v3_0_dec_ring_set_wptr,
1994         .patch_cs_in_place = vcn_v3_0_ring_patch_cs_in_place,
1995         .emit_frame_size =
1996                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1997                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
1998                 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */
1999                 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */
2000                 6,
2001         .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */
2002         .emit_ib = vcn_v2_0_dec_ring_emit_ib,
2003         .emit_fence = vcn_v2_0_dec_ring_emit_fence,
2004         .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
2005         .test_ring = vcn_v2_0_dec_ring_test_ring,
2006         .test_ib = amdgpu_vcn_dec_ring_test_ib,
2007         .insert_nop = vcn_v2_0_dec_ring_insert_nop,
2008         .insert_start = vcn_v2_0_dec_ring_insert_start,
2009         .insert_end = vcn_v2_0_dec_ring_insert_end,
2010         .pad_ib = amdgpu_ring_generic_pad_ib,
2011         .begin_use = amdgpu_vcn_ring_begin_use,
2012         .end_use = amdgpu_vcn_ring_end_use,
2013         .emit_wreg = vcn_v2_0_dec_ring_emit_wreg,
2014         .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,
2015         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2016 };
2017
2018 /**
2019  * vcn_v3_0_enc_ring_get_rptr - get enc read pointer
2020  *
2021  * @ring: amdgpu_ring pointer
2022  *
2023  * Returns the current hardware enc read pointer
2024  */
2025 static uint64_t vcn_v3_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
2026 {
2027         struct amdgpu_device *adev = ring->adev;
2028
2029         if (ring == &adev->vcn.inst[ring->me].ring_enc[0])
2030                 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR);
2031         else
2032                 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2);
2033 }
2034
2035 /**
2036  * vcn_v3_0_enc_ring_get_wptr - get enc write pointer
2037  *
2038  * @ring: amdgpu_ring pointer
2039  *
2040  * Returns the current hardware enc write pointer
2041  */
2042 static uint64_t vcn_v3_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
2043 {
2044         struct amdgpu_device *adev = ring->adev;
2045
2046         if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
2047                 if (ring->use_doorbell)
2048                         return adev->wb.wb[ring->wptr_offs];
2049                 else
2050                         return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR);
2051         } else {
2052                 if (ring->use_doorbell)
2053                         return adev->wb.wb[ring->wptr_offs];
2054                 else
2055                         return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2);
2056         }
2057 }
2058
2059 /**
2060  * vcn_v3_0_enc_ring_set_wptr - set enc write pointer
2061  *
2062  * @ring: amdgpu_ring pointer
2063  *
2064  * Commits the enc write pointer to the hardware
2065  */
2066 static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
2067 {
2068         struct amdgpu_device *adev = ring->adev;
2069
2070         if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
2071                 if (ring->use_doorbell) {
2072                         adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
2073                         WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
2074                 } else {
2075                         WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
2076                 }
2077         } else {
2078                 if (ring->use_doorbell) {
2079                         adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
2080                         WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
2081                 } else {
2082                         WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
2083                 }
2084         }
2085 }
2086
2087 static const struct amdgpu_ring_funcs vcn_v3_0_enc_ring_vm_funcs = {
2088         .type = AMDGPU_RING_TYPE_VCN_ENC,
2089         .align_mask = 0x3f,
2090         .nop = VCN_ENC_CMD_NO_OP,
2091         .vmhub = AMDGPU_MMHUB_0,
2092         .get_rptr = vcn_v3_0_enc_ring_get_rptr,
2093         .get_wptr = vcn_v3_0_enc_ring_get_wptr,
2094         .set_wptr = vcn_v3_0_enc_ring_set_wptr,
2095         .emit_frame_size =
2096                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2097                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
2098                 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
2099                 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
2100                 1, /* vcn_v2_0_enc_ring_insert_end */
2101         .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
2102         .emit_ib = vcn_v2_0_enc_ring_emit_ib,
2103         .emit_fence = vcn_v2_0_enc_ring_emit_fence,
2104         .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
2105         .test_ring = amdgpu_vcn_enc_ring_test_ring,
2106         .test_ib = amdgpu_vcn_enc_ring_test_ib,
2107         .insert_nop = amdgpu_ring_insert_nop,
2108         .insert_end = vcn_v2_0_enc_ring_insert_end,
2109         .pad_ib = amdgpu_ring_generic_pad_ib,
2110         .begin_use = amdgpu_vcn_ring_begin_use,
2111         .end_use = amdgpu_vcn_ring_end_use,
2112         .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
2113         .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
2114         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2115 };
2116
2117 static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev)
2118 {
2119         int i;
2120
2121         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2122                 if (adev->vcn.harvest_config & (1 << i))
2123                         continue;
2124
2125                 if (!DEC_SW_RING_ENABLED)
2126                         adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_ring_vm_funcs;
2127                 else
2128                         adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_sw_ring_vm_funcs;
2129                 adev->vcn.inst[i].ring_dec.me = i;
2130                 DRM_INFO("VCN(%d) decode%s is enabled in VM mode\n", i,
2131                           DEC_SW_RING_ENABLED?"(Software Ring)":"");
2132         }
2133 }
2134
2135 static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev)
2136 {
2137         int i, j;
2138
2139         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2140                 if (adev->vcn.harvest_config & (1 << i))
2141                         continue;
2142
2143                 for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
2144                         adev->vcn.inst[i].ring_enc[j].funcs = &vcn_v3_0_enc_ring_vm_funcs;
2145                         adev->vcn.inst[i].ring_enc[j].me = i;
2146                 }
2147                 if (adev->vcn.num_enc_rings > 0)
2148                         DRM_INFO("VCN(%d) encode is enabled in VM mode\n", i);
2149         }
2150 }
2151
2152 static bool vcn_v3_0_is_idle(void *handle)
2153 {
2154         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2155         int i, ret = 1;
2156
2157         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2158                 if (adev->vcn.harvest_config & (1 << i))
2159                         continue;
2160
2161                 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE);
2162         }
2163
2164         return ret;
2165 }
2166
2167 static int vcn_v3_0_wait_for_idle(void *handle)
2168 {
2169         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2170         int i, ret = 0;
2171
2172         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2173                 if (adev->vcn.harvest_config & (1 << i))
2174                         continue;
2175
2176                 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE,
2177                         UVD_STATUS__IDLE);
2178                 if (ret)
2179                         return ret;
2180         }
2181
2182         return ret;
2183 }
2184
2185 static int vcn_v3_0_set_clockgating_state(void *handle,
2186                                           enum amd_clockgating_state state)
2187 {
2188         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2189         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
2190         int i;
2191
2192         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2193                 if (adev->vcn.harvest_config & (1 << i))
2194                         continue;
2195
2196                 if (enable) {
2197                         if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE)
2198                                 return -EBUSY;
2199                         vcn_v3_0_enable_clock_gating(adev, i);
2200                 } else {
2201                         vcn_v3_0_disable_clock_gating(adev, i);
2202                 }
2203         }
2204
2205         return 0;
2206 }
2207
2208 static int vcn_v3_0_set_powergating_state(void *handle,
2209                                           enum amd_powergating_state state)
2210 {
2211         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2212         int ret;
2213
2214         /* for SRIOV, guest should not control VCN Power-gating
2215          * MMSCH FW should control Power-gating and clock-gating
2216          * guest should avoid touching CGC and PG
2217          */
2218         if (amdgpu_sriov_vf(adev)) {
2219                 adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
2220                 return 0;
2221         }
2222
2223         if(state == adev->vcn.cur_state)
2224                 return 0;
2225
2226         if (state == AMD_PG_STATE_GATE)
2227                 ret = vcn_v3_0_stop(adev);
2228         else
2229                 ret = vcn_v3_0_start(adev);
2230
2231         if(!ret)
2232                 adev->vcn.cur_state = state;
2233
2234         return ret;
2235 }
2236
2237 static int vcn_v3_0_set_interrupt_state(struct amdgpu_device *adev,
2238                                         struct amdgpu_irq_src *source,
2239                                         unsigned type,
2240                                         enum amdgpu_interrupt_state state)
2241 {
2242         return 0;
2243 }
2244
2245 static int vcn_v3_0_process_interrupt(struct amdgpu_device *adev,
2246                                       struct amdgpu_irq_src *source,
2247                                       struct amdgpu_iv_entry *entry)
2248 {
2249         uint32_t ip_instance;
2250
2251         switch (entry->client_id) {
2252         case SOC15_IH_CLIENTID_VCN:
2253                 ip_instance = 0;
2254                 break;
2255         case SOC15_IH_CLIENTID_VCN1:
2256                 ip_instance = 1;
2257                 break;
2258         default:
2259                 DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
2260                 return 0;
2261         }
2262
2263         DRM_DEBUG("IH: VCN TRAP\n");
2264
2265         switch (entry->src_id) {
2266         case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT:
2267                 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec);
2268                 break;
2269         case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
2270                 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);
2271                 break;
2272         case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:
2273                 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]);
2274                 break;
2275         default:
2276                 DRM_ERROR("Unhandled interrupt: %d %d\n",
2277                           entry->src_id, entry->src_data[0]);
2278                 break;
2279         }
2280
2281         return 0;
2282 }
2283
2284 static const struct amdgpu_irq_src_funcs vcn_v3_0_irq_funcs = {
2285         .set = vcn_v3_0_set_interrupt_state,
2286         .process = vcn_v3_0_process_interrupt,
2287 };
2288
2289 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev)
2290 {
2291         int i;
2292
2293         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2294                 if (adev->vcn.harvest_config & (1 << i))
2295                         continue;
2296
2297                 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1;
2298                 adev->vcn.inst[i].irq.funcs = &vcn_v3_0_irq_funcs;
2299         }
2300 }
2301
2302 static const struct amd_ip_funcs vcn_v3_0_ip_funcs = {
2303         .name = "vcn_v3_0",
2304         .early_init = vcn_v3_0_early_init,
2305         .late_init = NULL,
2306         .sw_init = vcn_v3_0_sw_init,
2307         .sw_fini = vcn_v3_0_sw_fini,
2308         .hw_init = vcn_v3_0_hw_init,
2309         .hw_fini = vcn_v3_0_hw_fini,
2310         .suspend = vcn_v3_0_suspend,
2311         .resume = vcn_v3_0_resume,
2312         .is_idle = vcn_v3_0_is_idle,
2313         .wait_for_idle = vcn_v3_0_wait_for_idle,
2314         .check_soft_reset = NULL,
2315         .pre_soft_reset = NULL,
2316         .soft_reset = NULL,
2317         .post_soft_reset = NULL,
2318         .set_clockgating_state = vcn_v3_0_set_clockgating_state,
2319         .set_powergating_state = vcn_v3_0_set_powergating_state,
2320 };
2321
2322 const struct amdgpu_ip_block_version vcn_v3_0_ip_block =
2323 {
2324         .type = AMD_IP_BLOCK_TYPE_VCN,
2325         .major = 3,
2326         .minor = 0,
2327         .rev = 0,
2328         .funcs = &vcn_v3_0_ip_funcs,
2329 };