drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32
  33 #include <linux/dma-mapping.h>
  34 #include <linux/iommu.h>
  35 #include <linux/pagemap.h>
  36 #include <linux/sched/task.h>
  37 #include <linux/sched/mm.h>
  38 #include <linux/seq_file.h>
  39 #include <linux/slab.h>
  40 #include <linux/swap.h>
  41 #include <linux/swiotlb.h>
  42 #include <linux/dma-buf.h>
  43 #include <linux/sizes.h>
  44
  45 #include <drm/ttm/ttm_bo_api.h>
  46 #include <drm/ttm/ttm_bo_driver.h>
  47 #include <drm/ttm/ttm_placement.h>
  48
  49 #include <drm/amdgpu_drm.h>
  50
  51 #include "amdgpu.h"
  52 #include "amdgpu_object.h"
  53 #include "amdgpu_trace.h"
  54 #include "amdgpu_amdkfd.h"
  55 #include "amdgpu_sdma.h"
  56 #include "amdgpu_ras.h"
  57 #include "amdgpu_atomfirmware.h"
  58 #include "amdgpu_res_cursor.h"
  59 #include "bif/bif_4_1_d.h"
  60
  61 #define AMDGPU_TTM_VRAM_MAX_DW_READ     (size_t)128
  62
  63 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
  64                                    struct ttm_tt *ttm,
  65                                    struct ttm_resource *bo_mem);
  66 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
  67                                       struct ttm_tt *ttm);
  68
  69 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
  70                                     unsigned int type,
  71                                     uint64_t size_in_page)
  72 {
  73         return ttm_range_man_init(&adev->mman.bdev, type,
  74                                   false, size_in_page);
  75 }
  76
  77 /**
  78  * amdgpu_evict_flags - Compute placement flags
  79  *
  80  * @bo: The buffer object to evict
  81  * @placement: Possible destination(s) for evicted BO
  82  *
  83  * Fill in placement data when ttm_bo_evict() is called
  84  */
  85 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
  86                                 struct ttm_placement *placement)
  87 {
  88         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
  89         struct amdgpu_bo *abo;
  90         static const struct ttm_place placements = {
  91                 .fpfn = 0,
  92                 .lpfn = 0,
  93                 .mem_type = TTM_PL_SYSTEM,
  94                 .flags = 0
  95         };
  96
  97         /* Don't handle scatter gather BOs */
  98         if (bo->type == ttm_bo_type_sg) {
  99                 placement->num_placement = 0;
 100                 placement->num_busy_placement = 0;
 101                 return;
 102         }
 103
 104         /* Object isn't an AMDGPU object so ignore */
 105         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 106                 placement->placement = &placements;
 107                 placement->busy_placement = &placements;
 108                 placement->num_placement = 1;
 109                 placement->num_busy_placement = 1;
 110                 return;
 111         }
 112
 113         abo = ttm_to_amdgpu_bo(bo);
 114         if (abo->flags & AMDGPU_AMDKFD_CREATE_SVM_BO) {
 115                 struct dma_fence *fence;
 116                 struct dma_resv *resv = &bo->base._resv;
 117
 118                 rcu_read_lock();
 119                 fence = rcu_dereference(resv->fence_excl);
 120                 if (fence && !fence->ops->signaled)
 121                         dma_fence_enable_sw_signaling(fence);
 122
 123                 placement->num_placement = 0;
 124                 placement->num_busy_placement = 0;
 125                 rcu_read_unlock();
 126                 return;
 127         }
 128         switch (bo->mem.mem_type) {
 129         case AMDGPU_PL_GDS:
 130         case AMDGPU_PL_GWS:
 131         case AMDGPU_PL_OA:
 132                 placement->num_placement = 0;
 133                 placement->num_busy_placement = 0;
 134                 return;
 135
 136         case TTM_PL_VRAM:
 137                 if (!adev->mman.buffer_funcs_enabled) {
 138                         /* Move to system memory */
 139                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 140                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 141                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 142                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 143
 144                         /* Try evicting to the CPU inaccessible part of VRAM
 145                          * first, but only set GTT as busy placement, so this
 146                          * BO will be evicted to GTT rather than causing other
 147                          * BOs to be evicted from VRAM
 148                          */
 149                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 150                                                          AMDGPU_GEM_DOMAIN_GTT);
 151                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 152                         abo->placements[0].lpfn = 0;
 153                         abo->placement.busy_placement = &abo->placements[1];
 154                         abo->placement.num_busy_placement = 1;
 155                 } else {
 156                         /* Move to GTT memory */
 157                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 158                 }
 159                 break;
 160         case TTM_PL_TT:
 161         default:
 162                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 163                 break;
 164         }
 165         *placement = abo->placement;
 166 }
 167
 168 /**
 169  * amdgpu_verify_access - Verify access for a mmap call
 170  *
 171  * @bo: The buffer object to map
 172  * @filp: The file pointer from the process performing the mmap
 173  *
 174  * This is called by ttm_bo_mmap() to verify whether a process
 175  * has the right to mmap a BO to their process space.
 176  */
 177 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 178 {
 179         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 180
 181         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 182                 return -EPERM;
 183         return drm_vma_node_verify_access(&abo->tbo.base.vma_node,
 184                                           filp->private_data);
 185 }
 186
 187 /**
 188  * amdgpu_ttm_map_buffer - Map memory into the GART windows
 189  * @bo: buffer object to map
 190  * @mem: memory object to map
 191  * @mm_cur: range to map
 192  * @num_pages: number of pages to map
 193  * @window: which GART window to use
 194  * @ring: DMA ring to use for the copy
 195  * @tmz: if we should setup a TMZ enabled mapping
 196  * @addr: resulting address inside the MC address space
 197  *
 198  * Setup one of the GART windows to access a specific piece of memory or return
 199  * the physical address for local memory.
 200  */
 201 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
 202                                  struct ttm_resource *mem,
 203                                  struct amdgpu_res_cursor *mm_cur,
 204                                  unsigned num_pages, unsigned window,
 205                                  struct amdgpu_ring *ring, bool tmz,
 206                                  uint64_t *addr)
 207 {
 208         struct amdgpu_device *adev = ring->adev;
 209         struct amdgpu_job *job;
 210         unsigned num_dw, num_bytes;
 211         struct dma_fence *fence;
 212         uint64_t src_addr, dst_addr;
 213         void *cpu_addr;
 214         uint64_t flags;
 215         unsigned int i;
 216         int r;
 217
 218         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
 219                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
 220
 221         /* Map only what can't be accessed directly */
 222         if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
 223                 *addr = amdgpu_ttm_domain_start(adev, mem->mem_type) +
 224                         mm_cur->start;
 225                 return 0;
 226         }
 227
 228         *addr = adev->gmc.gart_start;
 229         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
 230                 AMDGPU_GPU_PAGE_SIZE;
 231         *addr += mm_cur->start & ~PAGE_MASK;
 232
 233         num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
 234         num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE;
 235
 236         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,
 237                                      AMDGPU_IB_POOL_DELAYED, &job);
 238         if (r)
 239                 return r;
 240
 241         src_addr = num_dw * 4;
 242         src_addr += job->ibs[0].gpu_addr;
 243
 244         dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 245         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
 246         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
 247                                 dst_addr, num_bytes, false);
 248
 249         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 250         WARN_ON(job->ibs[0].length_dw > num_dw);
 251
 252         flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
 253         if (tmz)
 254                 flags |= AMDGPU_PTE_TMZ;
 255
 256         cpu_addr = &job->ibs[0].ptr[num_dw];
 257
 258         if (mem->mem_type == TTM_PL_TT) {
 259                 dma_addr_t *dma_addr;
 260
 261                 dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT];
 262                 r = amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags,
 263                                     cpu_addr);
 264                 if (r)
 265                         goto error_free;
 266         } else {
 267                 dma_addr_t dma_address;
 268
 269                 dma_address = mm_cur->start;
 270                 dma_address += adev->vm_manager.vram_base_offset;
 271
 272                 for (i = 0; i < num_pages; ++i) {
 273                         r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1,
 274                                             &dma_address, flags, cpu_addr);
 275                         if (r)
 276                                 goto error_free;
 277
 278                         dma_address += PAGE_SIZE;
 279                 }
 280         }
 281
 282         r = amdgpu_job_submit(job, &adev->mman.entity,
 283                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
 284         if (r)
 285                 goto error_free;
 286
 287         dma_fence_put(fence);
 288
 289         return r;
 290
 291 error_free:
 292         amdgpu_job_free(job);
 293         return r;
 294 }
 295
 296 /**
 297  * amdgpu_ttm_copy_mem_to_mem - Helper function for copy
 298  * @adev: amdgpu device
 299  * @src: buffer/address where to read from
 300  * @dst: buffer/address where to write to
 301  * @size: number of bytes to copy
 302  * @tmz: if a secure copy should be used
 303  * @resv: resv object to sync to
 304  * @f: Returns the last fence if multiple jobs are submitted.
 305  *
 306  * The function copies @size bytes from {src->mem + src->offset} to
 307  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 308  * move and different for a BO to BO copy.
 309  *
 310  */
 311 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 312                                const struct amdgpu_copy_mem *src,
 313                                const struct amdgpu_copy_mem *dst,
 314                                uint64_t size, bool tmz,
 315                                struct dma_resv *resv,
 316                                struct dma_fence **f)
 317 {
 318         const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 319                                         AMDGPU_GPU_PAGE_SIZE);
 320
 321         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 322         struct amdgpu_res_cursor src_mm, dst_mm;
 323         struct dma_fence *fence = NULL;
 324         int r = 0;
 325
 326         if (!adev->mman.buffer_funcs_enabled) {
 327                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 328                 return -EINVAL;
 329         }
 330
 331         amdgpu_res_first(src->mem, src->offset, size, &src_mm);
 332         amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm);
 333
 334         mutex_lock(&adev->mman.gtt_window_lock);
 335         while (src_mm.remaining) {
 336                 uint32_t src_page_offset = src_mm.start & ~PAGE_MASK;
 337                 uint32_t dst_page_offset = dst_mm.start & ~PAGE_MASK;
 338                 struct dma_fence *next;
 339                 uint32_t cur_size;
 340                 uint64_t from, to;
 341
 342                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 343                  * begins at an offset, then adjust the size accordingly
 344                  */
 345                 cur_size = max(src_page_offset, dst_page_offset);
 346                 cur_size = min(min3(src_mm.size, dst_mm.size, size),
 347                                (uint64_t)(GTT_MAX_BYTES - cur_size));
 348
 349                 /* Map src to window 0 and dst to window 1. */
 350                 r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm,
 351                                           PFN_UP(cur_size + src_page_offset),
 352                                           0, ring, tmz, &from);
 353                 if (r)
 354                         goto error;
 355
 356                 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm,
 357                                           PFN_UP(cur_size + dst_page_offset),
 358                                           1, ring, tmz, &to);
 359                 if (r)
 360                         goto error;
 361
 362                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 363                                        resv, &next, false, true, tmz);
 364                 if (r)
 365                         goto error;
 366
 367                 dma_fence_put(fence);
 368                 fence = next;
 369
 370                 amdgpu_res_next(&src_mm, cur_size);
 371                 amdgpu_res_next(&dst_mm, cur_size);
 372         }
 373 error:
 374         mutex_unlock(&adev->mman.gtt_window_lock);
 375         if (f)
 376                 *f = dma_fence_get(fence);
 377         dma_fence_put(fence);
 378         return r;
 379 }
 380
 381 /*
 382  * amdgpu_move_blit - Copy an entire buffer to another buffer
 383  *
 384  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 385  * help move buffers to and from VRAM.
 386  */
 387 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 388                             bool evict,
 389                             struct ttm_resource *new_mem,
 390                             struct ttm_resource *old_mem)
 391 {
 392         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 393         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 394         struct amdgpu_copy_mem src, dst;
 395         struct dma_fence *fence = NULL;
 396         int r;
 397
 398         src.bo = bo;
 399         dst.bo = bo;
 400         src.mem = old_mem;
 401         dst.mem = new_mem;
 402         src.offset = 0;
 403         dst.offset = 0;
 404
 405         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 406                                        new_mem->num_pages << PAGE_SHIFT,
 407                                        amdgpu_bo_encrypted(abo),
 408                                        bo->base.resv, &fence);
 409         if (r)
 410                 goto error;
 411
 412         /* clear the space being freed */
 413         if (old_mem->mem_type == TTM_PL_VRAM &&
 414             (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
 415                 struct dma_fence *wipe_fence = NULL;
 416
 417                 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
 418                                        NULL, &wipe_fence);
 419                 if (r) {
 420                         goto error;
 421                 } else if (wipe_fence) {
 422                         dma_fence_put(fence);
 423                         fence = wipe_fence;
 424                 }
 425         }
 426
 427         /* Always block for VM page tables before committing the new location */
 428         if (bo->type == ttm_bo_type_kernel)
 429                 r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem);
 430         else
 431                 r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem);
 432         dma_fence_put(fence);
 433         return r;
 434
 435 error:
 436         if (fence)
 437                 dma_fence_wait(fence, false);
 438         dma_fence_put(fence);
 439         return r;
 440 }
 441
 442 /*
 443  * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
 444  *
 445  * Called by amdgpu_bo_move()
 446  */
 447 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
 448                                struct ttm_resource *mem)
 449 {
 450         uint64_t mem_size = (u64)mem->num_pages << PAGE_SHIFT;
 451         struct amdgpu_res_cursor cursor;
 452
 453         if (mem->mem_type == TTM_PL_SYSTEM ||
 454             mem->mem_type == TTM_PL_TT)
 455                 return true;
 456         if (mem->mem_type != TTM_PL_VRAM)
 457                 return false;
 458
 459         amdgpu_res_first(mem, 0, mem_size, &cursor);
 460
 461         /* ttm_resource_ioremap only supports contiguous memory */
 462         if (cursor.size != mem_size)
 463                 return false;
 464
 465         return cursor.start + cursor.size <= adev->gmc.visible_vram_size;
 466 }
 467
 468 /*
 469  * amdgpu_bo_move - Move a buffer object to a new memory location
 470  *
 471  * Called by ttm_bo_handle_move_mem()
 472  */
 473 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 474                           struct ttm_operation_ctx *ctx,
 475                           struct ttm_resource *new_mem,
 476                           struct ttm_place *hop)
 477 {
 478         struct amdgpu_device *adev;
 479         struct amdgpu_bo *abo;
 480         struct ttm_resource *old_mem = &bo->mem;
 481         int r;
 482
 483         if (new_mem->mem_type == TTM_PL_TT) {
 484                 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem);
 485                 if (r)
 486                         return r;
 487         }
 488
 489         /* Can't move a pinned BO */
 490         abo = ttm_to_amdgpu_bo(bo);
 491         if (WARN_ON_ONCE(abo->tbo.pin_count > 0))
 492                 return -EINVAL;
 493
 494         adev = amdgpu_ttm_adev(bo->bdev);
 495
 496         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 497                 ttm_bo_move_null(bo, new_mem);
 498                 goto out;
 499         }
 500         if (old_mem->mem_type == TTM_PL_SYSTEM &&
 501             new_mem->mem_type == TTM_PL_TT) {
 502                 ttm_bo_move_null(bo, new_mem);
 503                 goto out;
 504         }
 505         if (old_mem->mem_type == TTM_PL_TT &&
 506             new_mem->mem_type == TTM_PL_SYSTEM) {
 507                 r = ttm_bo_wait_ctx(bo, ctx);
 508                 if (r)
 509                         return r;
 510
 511                 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm);
 512                 ttm_resource_free(bo, &bo->mem);
 513                 ttm_bo_assign_mem(bo, new_mem);
 514                 goto out;
 515         }
 516
 517         if (old_mem->mem_type == AMDGPU_PL_GDS ||
 518             old_mem->mem_type == AMDGPU_PL_GWS ||
 519             old_mem->mem_type == AMDGPU_PL_OA ||
 520             new_mem->mem_type == AMDGPU_PL_GDS ||
 521             new_mem->mem_type == AMDGPU_PL_GWS ||
 522             new_mem->mem_type == AMDGPU_PL_OA) {
 523                 /* Nothing to save here */
 524                 ttm_bo_move_null(bo, new_mem);
 525                 goto out;
 526         }
 527
 528         if (adev->mman.buffer_funcs_enabled) {
 529                 if (((old_mem->mem_type == TTM_PL_SYSTEM &&
 530                       new_mem->mem_type == TTM_PL_VRAM) ||
 531                      (old_mem->mem_type == TTM_PL_VRAM &&
 532                       new_mem->mem_type == TTM_PL_SYSTEM))) {
 533                         hop->fpfn = 0;
 534                         hop->lpfn = 0;
 535                         hop->mem_type = TTM_PL_TT;
 536                         hop->flags = 0;
 537                         return -EMULTIHOP;
 538                 }
 539
 540                 r = amdgpu_move_blit(bo, evict, new_mem, old_mem);
 541         } else {
 542                 r = -ENODEV;
 543         }
 544
 545         if (r) {
 546                 /* Check that all memory is CPU accessible */
 547                 if (!amdgpu_mem_visible(adev, old_mem) ||
 548                     !amdgpu_mem_visible(adev, new_mem)) {
 549                         pr_err("Move buffer fallback to memcpy unavailable\n");
 550                         return r;
 551                 }
 552
 553                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 554                 if (r)
 555                         return r;
 556         }
 557
 558         if (bo->type == ttm_bo_type_device &&
 559             new_mem->mem_type == TTM_PL_VRAM &&
 560             old_mem->mem_type != TTM_PL_VRAM) {
 561                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 562                  * accesses the BO after it's moved.
 563                  */
 564                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 565         }
 566
 567 out:
 568         /* update statistics */
 569         atomic64_add(bo->base.size, &adev->num_bytes_moved);
 570         amdgpu_bo_move_notify(bo, evict, new_mem);
 571         return 0;
 572 }
 573
 574 /*
 575  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 576  *
 577  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 578  */
 579 static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev,
 580                                      struct ttm_resource *mem)
 581 {
 582         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 583         size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT;
 584
 585         switch (mem->mem_type) {
 586         case TTM_PL_SYSTEM:
 587                 /* system memory */
 588                 return 0;
 589         case TTM_PL_TT:
 590                 break;
 591         case TTM_PL_VRAM:
 592                 mem->bus.offset = mem->start << PAGE_SHIFT;
 593                 /* check if it's visible */
 594                 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size)
 595                         return -EINVAL;
 596
 597                 if (adev->mman.aper_base_kaddr &&
 598                     mem->placement & TTM_PL_FLAG_CONTIGUOUS)
 599                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 600                                         mem->bus.offset;
 601
 602                 mem->bus.offset += adev->gmc.aper_base;
 603                 mem->bus.is_iomem = true;
 604                 if (adev->gmc.xgmi.connected_to_cpu)
 605                         mem->bus.caching = ttm_cached;
 606                 else
 607                         mem->bus.caching = ttm_write_combined;
 608                 break;
 609         default:
 610                 return -EINVAL;
 611         }
 612         return 0;
 613 }
 614
 615 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 616                                            unsigned long page_offset)
 617 {
 618         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 619         struct amdgpu_res_cursor cursor;
 620
 621         amdgpu_res_first(&bo->mem, (u64)page_offset << PAGE_SHIFT, 0, &cursor);
 622         return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT;
 623 }
 624
 625 /**
 626  * amdgpu_ttm_domain_start - Returns GPU start address
 627  * @adev: amdgpu device object
 628  * @type: type of the memory
 629  *
 630  * Returns:
 631  * GPU start address of a memory domain
 632  */
 633
 634 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
 635 {
 636         switch (type) {
 637         case TTM_PL_TT:
 638                 return adev->gmc.gart_start;
 639         case TTM_PL_VRAM:
 640                 return adev->gmc.vram_start;
 641         }
 642
 643         return 0;
 644 }
 645
 646 /*
 647  * TTM backend functions.
 648  */
 649 struct amdgpu_ttm_tt {
 650         struct ttm_tt   ttm;
 651         struct drm_gem_object   *gobj;
 652         u64                     offset;
 653         uint64_t                userptr;
 654         struct task_struct      *usertask;
 655         uint32_t                userflags;
 656         bool                    bound;
 657 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 658         struct hmm_range        *range;
 659 #endif
 660 };
 661
 662 #ifdef CONFIG_DRM_AMDGPU_USERPTR
 663 /*
 664  * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 665  * memory and start HMM tracking CPU page table update
 666  *
 667  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 668  * once afterwards to stop HMM tracking
 669  */
 670 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
 671 {
 672         struct ttm_tt *ttm = bo->tbo.ttm;
 673         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 674         unsigned long start = gtt->userptr;
 675         struct vm_area_struct *vma;
 676         struct mm_struct *mm;
 677         bool readonly;
 678         int r = 0;
 679
 680         mm = bo->notifier.mm;
 681         if (unlikely(!mm)) {
 682                 DRM_DEBUG_DRIVER("BO is not registered?\n");
 683                 return -EFAULT;
 684         }
 685
 686         /* Another get_user_pages is running at the same time?? */
 687         if (WARN_ON(gtt->range))
 688                 return -EFAULT;
 689
 690         if (!mmget_not_zero(mm)) /* Happens during process shutdown */
 691                 return -ESRCH;
 692
 693         mmap_read_lock(mm);
 694         vma = find_vma(mm, start);
 695         mmap_read_unlock(mm);
 696         if (unlikely(!vma || start < vma->vm_start)) {
 697                 r = -EFAULT;
 698                 goto out_putmm;
 699         }
 700         if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
 701                 vma->vm_file)) {
 702                 r = -EPERM;
 703                 goto out_putmm;
 704         }
 705
 706         readonly = amdgpu_ttm_tt_is_readonly(ttm);
 707         r = amdgpu_hmm_range_get_pages(&bo->notifier, mm, pages, start,
 708                                        ttm->num_pages, &gtt->range, readonly,
 709                                        false);
 710 out_putmm:
 711         mmput(mm);
 712
 713         return r;
 714 }
 715
 716 /*
 717  * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
 718  * Check if the pages backing this ttm range have been invalidated
 719  *
 720  * Returns: true if pages are still valid
 721  */
 722 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
 723 {
 724         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 725         bool r = false;
 726
 727         if (!gtt || !gtt->userptr)
 728                 return false;
 729
 730         DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n",
 731                 gtt->userptr, ttm->num_pages);
 732
 733         WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns,
 734                 "No user pages to check\n");
 735
 736         if (gtt->range) {
 737                 /*
 738                  * FIXME: Must always hold notifier_lock for this, and must
 739                  * not ignore the return code.
 740                  */
 741                 r = amdgpu_hmm_range_get_pages_done(gtt->range);
 742                 gtt->range = NULL;
 743         }
 744
 745         return !r;
 746 }
 747 #endif
 748
 749 /*
 750  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
 751  *
 752  * Called by amdgpu_cs_list_validate(). This creates the page list
 753  * that backs user memory and will ultimately be mapped into the device
 754  * address space.
 755  */
 756 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 757 {
 758         unsigned long i;
 759
 760         for (i = 0; i < ttm->num_pages; ++i)
 761                 ttm->pages[i] = pages ? pages[i] : NULL;
 762 }
 763
 764 /*
 765  * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages
 766  *
 767  * Called by amdgpu_ttm_backend_bind()
 768  **/
 769 static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev,
 770                                      struct ttm_tt *ttm)
 771 {
 772         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 773         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 774         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 775         enum dma_data_direction direction = write ?
 776                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 777         int r;
 778
 779         /* Allocate an SG array and squash pages into it */
 780         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 781                                       (u64)ttm->num_pages << PAGE_SHIFT,
 782                                       GFP_KERNEL);
 783         if (r)
 784                 goto release_sg;
 785
 786         /* Map SG to device */
 787         r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
 788         if (r)
 789                 goto release_sg;
 790
 791         /* convert SG to linear array of pages and dma addresses */
 792         drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
 793                                        ttm->num_pages);
 794
 795         return 0;
 796
 797 release_sg:
 798         kfree(ttm->sg);
 799         ttm->sg = NULL;
 800         return r;
 801 }
 802
 803 /*
 804  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
 805  */
 806 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev,
 807                                         struct ttm_tt *ttm)
 808 {
 809         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 810         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 811         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 812         enum dma_data_direction direction = write ?
 813                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 814
 815         /* double check that we don't free the table twice */
 816         if (!ttm->sg || !ttm->sg->sgl)
 817                 return;
 818
 819         /* unmap the pages mapped to the device */
 820         dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
 821         sg_free_table(ttm->sg);
 822
 823 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 824         if (gtt->range) {
 825                 unsigned long i;
 826
 827                 for (i = 0; i < ttm->num_pages; i++) {
 828                         if (ttm->pages[i] !=
 829                             hmm_pfn_to_page(gtt->range->hmm_pfns[i]))
 830                                 break;
 831                 }
 832
 833                 WARN((i == ttm->num_pages), "Missing get_user_page_done\n");
 834         }
 835 #endif
 836 }
 837
 838 static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
 839                                 struct ttm_buffer_object *tbo,
 840                                 uint64_t flags)
 841 {
 842         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
 843         struct ttm_tt *ttm = tbo->ttm;
 844         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 845         int r;
 846
 847         if (amdgpu_bo_encrypted(abo))
 848                 flags |= AMDGPU_PTE_TMZ;
 849
 850         if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
 851                 uint64_t page_idx = 1;
 852
 853                 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
 854                                 ttm->pages, gtt->ttm.dma_address, flags);
 855                 if (r)
 856                         goto gart_bind_fail;
 857
 858                 /* The memory type of the first page defaults to UC. Now
 859                  * modify the memory type to NC from the second page of
 860                  * the BO onward.
 861                  */
 862                 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
 863                 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
 864
 865                 r = amdgpu_gart_bind(adev,
 866                                 gtt->offset + (page_idx << PAGE_SHIFT),
 867                                 ttm->num_pages - page_idx,
 868                                 &ttm->pages[page_idx],
 869                                 &(gtt->ttm.dma_address[page_idx]), flags);
 870         } else {
 871                 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 872                                      ttm->pages, gtt->ttm.dma_address, flags);
 873         }
 874
 875 gart_bind_fail:
 876         if (r)
 877                 DRM_ERROR("failed to bind %u pages at 0x%08llX\n",
 878                           ttm->num_pages, gtt->offset);
 879
 880         return r;
 881 }
 882
 883 /*
 884  * amdgpu_ttm_backend_bind - Bind GTT memory
 885  *
 886  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
 887  * This handles binding GTT memory to the device address space.
 888  */
 889 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
 890                                    struct ttm_tt *ttm,
 891                                    struct ttm_resource *bo_mem)
 892 {
 893         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 894         struct amdgpu_ttm_tt *gtt = (void*)ttm;
 895         uint64_t flags;
 896         int r = 0;
 897
 898         if (!bo_mem)
 899                 return -EINVAL;
 900
 901         if (gtt->bound)
 902                 return 0;
 903
 904         if (gtt->userptr) {
 905                 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm);
 906                 if (r) {
 907                         DRM_ERROR("failed to pin userptr\n");
 908                         return r;
 909                 }
 910         } else if (ttm->page_flags & TTM_PAGE_FLAG_SG) {
 911                 if (!ttm->sg) {
 912                         struct dma_buf_attachment *attach;
 913                         struct sg_table *sgt;
 914
 915                         attach = gtt->gobj->import_attach;
 916                         sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
 917                         if (IS_ERR(sgt))
 918                                 return PTR_ERR(sgt);
 919
 920                         ttm->sg = sgt;
 921                 }
 922
 923                 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
 924                                                ttm->num_pages);
 925         }
 926
 927         if (!ttm->num_pages) {
 928                 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n",
 929                      ttm->num_pages, bo_mem, ttm);
 930         }
 931
 932         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
 933             bo_mem->mem_type == AMDGPU_PL_GWS ||
 934             bo_mem->mem_type == AMDGPU_PL_OA)
 935                 return -EINVAL;
 936
 937         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
 938                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
 939                 return 0;
 940         }
 941
 942         /* compute PTE flags relevant to this BO memory */
 943         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
 944
 945         /* bind pages into GART page tables */
 946         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
 947         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 948                 ttm->pages, gtt->ttm.dma_address, flags);
 949
 950         if (r)
 951                 DRM_ERROR("failed to bind %u pages at 0x%08llX\n",
 952                           ttm->num_pages, gtt->offset);
 953         gtt->bound = true;
 954         return r;
 955 }
 956
 957 /*
 958  * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either
 959  * through AGP or GART aperture.
 960  *
 961  * If bo is accessible through AGP aperture, then use AGP aperture
 962  * to access bo; otherwise allocate logical space in GART aperture
 963  * and map bo to GART aperture.
 964  */
 965 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
 966 {
 967         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 968         struct ttm_operation_ctx ctx = { false, false };
 969         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
 970         struct ttm_resource tmp;
 971         struct ttm_placement placement;
 972         struct ttm_place placements;
 973         uint64_t addr, flags;
 974         int r;
 975
 976         if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
 977                 return 0;
 978
 979         addr = amdgpu_gmc_agp_addr(bo);
 980         if (addr != AMDGPU_BO_INVALID_OFFSET) {
 981                 bo->mem.start = addr >> PAGE_SHIFT;
 982         } else {
 983
 984                 /* allocate GART space */
 985                 placement.num_placement = 1;
 986                 placement.placement = &placements;
 987                 placement.num_busy_placement = 1;
 988                 placement.busy_placement = &placements;
 989                 placements.fpfn = 0;
 990                 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
 991                 placements.mem_type = TTM_PL_TT;
 992                 placements.flags = bo->mem.placement;
 993
 994                 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
 995                 if (unlikely(r))
 996                         return r;
 997
 998                 /* compute PTE flags for this buffer object */
 999                 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
1000
1001                 /* Bind pages */
1002                 gtt->offset = (u64)tmp.start << PAGE_SHIFT;
1003                 r = amdgpu_ttm_gart_bind(adev, bo, flags);
1004                 if (unlikely(r)) {
1005                         ttm_resource_free(bo, &tmp);
1006                         return r;
1007                 }
1008
1009                 ttm_resource_free(bo, &bo->mem);
1010                 bo->mem = tmp;
1011         }
1012
1013         return 0;
1014 }
1015
1016 /*
1017  * amdgpu_ttm_recover_gart - Rebind GTT pages
1018  *
1019  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1020  * rebind GTT pages during a GPU reset.
1021  */
1022 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1023 {
1024         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1025         uint64_t flags;
1026         int r;
1027
1028         if (!tbo->ttm)
1029                 return 0;
1030
1031         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1032         r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1033
1034         return r;
1035 }
1036
1037 /*
1038  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1039  *
1040  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1041  * ttm_tt_destroy().
1042  */
1043 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
1044                                       struct ttm_tt *ttm)
1045 {
1046         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1047         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1048         int r;
1049
1050         /* if the pages have userptr pinning then clear that first */
1051         if (gtt->userptr) {
1052                 amdgpu_ttm_tt_unpin_userptr(bdev, ttm);
1053         } else if (ttm->sg && gtt->gobj->import_attach) {
1054                 struct dma_buf_attachment *attach;
1055
1056                 attach = gtt->gobj->import_attach;
1057                 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1058                 ttm->sg = NULL;
1059         }
1060
1061         if (!gtt->bound)
1062                 return;
1063
1064         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1065                 return;
1066
1067         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1068         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1069         if (r)
1070                 DRM_ERROR("failed to unbind %u pages at 0x%08llX\n",
1071                           gtt->ttm.num_pages, gtt->offset);
1072         gtt->bound = false;
1073 }
1074
1075 static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev,
1076                                        struct ttm_tt *ttm)
1077 {
1078         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1079
1080         amdgpu_ttm_backend_unbind(bdev, ttm);
1081         ttm_tt_destroy_common(bdev, ttm);
1082         if (gtt->usertask)
1083                 put_task_struct(gtt->usertask);
1084
1085         ttm_tt_fini(&gtt->ttm);
1086         kfree(gtt);
1087 }
1088
1089 /**
1090  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1091  *
1092  * @bo: The buffer object to create a GTT ttm_tt object around
1093  * @page_flags: Page flags to be added to the ttm_tt object
1094  *
1095  * Called by ttm_tt_create().
1096  */
1097 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1098                                            uint32_t page_flags)
1099 {
1100         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1101         struct amdgpu_ttm_tt *gtt;
1102         enum ttm_caching caching;
1103
1104         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1105         if (gtt == NULL) {
1106                 return NULL;
1107         }
1108         gtt->gobj = &bo->base;
1109
1110         if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
1111                 caching = ttm_write_combined;
1112         else
1113                 caching = ttm_cached;
1114
1115         /* allocate space for the uninitialized page entries */
1116         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags, caching)) {
1117                 kfree(gtt);
1118                 return NULL;
1119         }
1120         return &gtt->ttm;
1121 }
1122
1123 /*
1124  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1125  *
1126  * Map the pages of a ttm_tt object to an address space visible
1127  * to the underlying device.
1128  */
1129 static int amdgpu_ttm_tt_populate(struct ttm_device *bdev,
1130                                   struct ttm_tt *ttm,
1131                                   struct ttm_operation_ctx *ctx)
1132 {
1133         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1134         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1135
1136         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1137         if (gtt && gtt->userptr) {
1138                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1139                 if (!ttm->sg)
1140                         return -ENOMEM;
1141
1142                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1143                 return 0;
1144         }
1145
1146         if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1147                 return 0;
1148
1149         return ttm_pool_alloc(&adev->mman.bdev.pool, ttm, ctx);
1150 }
1151
1152 /*
1153  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1154  *
1155  * Unmaps pages of a ttm_tt object from the device address space and
1156  * unpopulates the page array backing it.
1157  */
1158 static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev,
1159                                      struct ttm_tt *ttm)
1160 {
1161         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1162         struct amdgpu_device *adev;
1163
1164         if (gtt && gtt->userptr) {
1165                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1166                 kfree(ttm->sg);
1167                 ttm->sg = NULL;
1168                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1169                 return;
1170         }
1171
1172         if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1173                 return;
1174
1175         adev = amdgpu_ttm_adev(bdev);
1176         return ttm_pool_free(&adev->mman.bdev.pool, ttm);
1177 }
1178
1179 /**
1180  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1181  * task
1182  *
1183  * @bo: The ttm_buffer_object to bind this userptr to
1184  * @addr:  The address in the current tasks VM space to use
1185  * @flags: Requirements of userptr object.
1186  *
1187  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1188  * to current task
1189  */
1190 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
1191                               uint64_t addr, uint32_t flags)
1192 {
1193         struct amdgpu_ttm_tt *gtt;
1194
1195         if (!bo->ttm) {
1196                 /* TODO: We want a separate TTM object type for userptrs */
1197                 bo->ttm = amdgpu_ttm_tt_create(bo, 0);
1198                 if (bo->ttm == NULL)
1199                         return -ENOMEM;
1200         }
1201
1202         gtt = (void *)bo->ttm;
1203         gtt->userptr = addr;
1204         gtt->userflags = flags;
1205
1206         if (gtt->usertask)
1207                 put_task_struct(gtt->usertask);
1208         gtt->usertask = current->group_leader;
1209         get_task_struct(gtt->usertask);
1210
1211         return 0;
1212 }
1213
1214 /*
1215  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1216  */
1217 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1218 {
1219         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1220
1221         if (gtt == NULL)
1222                 return NULL;
1223
1224         if (gtt->usertask == NULL)
1225                 return NULL;
1226
1227         return gtt->usertask->mm;
1228 }
1229
1230 /*
1231  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1232  * address range for the current task.
1233  *
1234  */
1235 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1236                                   unsigned long end)
1237 {
1238         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1239         unsigned long size;
1240
1241         if (gtt == NULL || !gtt->userptr)
1242                 return false;
1243
1244         /* Return false if no part of the ttm_tt object lies within
1245          * the range
1246          */
1247         size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE;
1248         if (gtt->userptr > end || gtt->userptr + size <= start)
1249                 return false;
1250
1251         return true;
1252 }
1253
1254 /*
1255  * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1256  */
1257 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1258 {
1259         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1260
1261         if (gtt == NULL || !gtt->userptr)
1262                 return false;
1263
1264         return true;
1265 }
1266
1267 /*
1268  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1269  */
1270 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1271 {
1272         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1273
1274         if (gtt == NULL)
1275                 return false;
1276
1277         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1278 }
1279
1280 /**
1281  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1282  *
1283  * @ttm: The ttm_tt object to compute the flags for
1284  * @mem: The memory registry backing this ttm_tt object
1285  *
1286  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1287  */
1288 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
1289 {
1290         uint64_t flags = 0;
1291
1292         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1293                 flags |= AMDGPU_PTE_VALID;
1294
1295         if (mem && mem->mem_type == TTM_PL_TT) {
1296                 flags |= AMDGPU_PTE_SYSTEM;
1297
1298                 if (ttm->caching == ttm_cached)
1299                         flags |= AMDGPU_PTE_SNOOPED;
1300         }
1301
1302         if (mem && mem->mem_type == TTM_PL_VRAM &&
1303                         mem->bus.caching == ttm_cached)
1304                 flags |= AMDGPU_PTE_SNOOPED;
1305
1306         return flags;
1307 }
1308
1309 /**
1310  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1311  *
1312  * @adev: amdgpu_device pointer
1313  * @ttm: The ttm_tt object to compute the flags for
1314  * @mem: The memory registry backing this ttm_tt object
1315  *
1316  * Figure out the flags to use for a VM PTE (Page Table Entry).
1317  */
1318 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1319                                  struct ttm_resource *mem)
1320 {
1321         uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1322
1323         flags |= adev->gart.gart_pte_flags;
1324         flags |= AMDGPU_PTE_READABLE;
1325
1326         if (!amdgpu_ttm_tt_is_readonly(ttm))
1327                 flags |= AMDGPU_PTE_WRITEABLE;
1328
1329         return flags;
1330 }
1331
1332 /*
1333  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1334  * object.
1335  *
1336  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1337  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1338  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1339  * used to clean out a memory space.
1340  */
1341 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1342                                             const struct ttm_place *place)
1343 {
1344         unsigned long num_pages = bo->mem.num_pages;
1345         struct amdgpu_res_cursor cursor;
1346         struct dma_resv_list *flist;
1347         struct dma_fence *f;
1348         int i;
1349
1350         if (bo->type == ttm_bo_type_kernel &&
1351             !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1352                 return false;
1353
1354         /* If bo is a KFD BO, check if the bo belongs to the current process.
1355          * If true, then return false as any KFD process needs all its BOs to
1356          * be resident to run successfully
1357          */
1358         flist = dma_resv_get_list(bo->base.resv);
1359         if (flist) {
1360                 for (i = 0; i < flist->shared_count; ++i) {
1361                         f = rcu_dereference_protected(flist->shared[i],
1362                                 dma_resv_held(bo->base.resv));
1363                         if (amdkfd_fence_check_mm(f, current->mm))
1364                                 return false;
1365                 }
1366         }
1367
1368         switch (bo->mem.mem_type) {
1369         case TTM_PL_TT:
1370                 if (amdgpu_bo_is_amdgpu_bo(bo) &&
1371                     amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1372                         return false;
1373                 return true;
1374
1375         case TTM_PL_VRAM:
1376                 /* Check each drm MM node individually */
1377                 amdgpu_res_first(&bo->mem, 0, (u64)num_pages << PAGE_SHIFT,
1378                                  &cursor);
1379                 while (cursor.remaining) {
1380                         if (place->fpfn < PFN_DOWN(cursor.start + cursor.size)
1381                             && !(place->lpfn &&
1382                                  place->lpfn <= PFN_DOWN(cursor.start)))
1383                                 return true;
1384
1385                         amdgpu_res_next(&cursor, cursor.size);
1386                 }
1387                 return false;
1388
1389         default:
1390                 break;
1391         }
1392
1393         return ttm_bo_eviction_valuable(bo, place);
1394 }
1395
1396 /**
1397  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1398  *
1399  * @bo:  The buffer object to read/write
1400  * @offset:  Offset into buffer object
1401  * @buf:  Secondary buffer to write/read from
1402  * @len: Length in bytes of access
1403  * @write:  true if writing
1404  *
1405  * This is used to access VRAM that backs a buffer object via MMIO
1406  * access for debugging purposes.
1407  */
1408 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1409                                     unsigned long offset, void *buf, int len,
1410                                     int write)
1411 {
1412         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1413         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1414         struct amdgpu_res_cursor cursor;
1415         unsigned long flags;
1416         uint32_t value = 0;
1417         int ret = 0;
1418
1419         if (bo->mem.mem_type != TTM_PL_VRAM)
1420                 return -EIO;
1421
1422         amdgpu_res_first(&bo->mem, offset, len, &cursor);
1423         while (cursor.remaining) {
1424                 uint64_t aligned_pos = cursor.start & ~(uint64_t)3;
1425                 uint64_t bytes = 4 - (cursor.start & 3);
1426                 uint32_t shift = (cursor.start & 3) * 8;
1427                 uint32_t mask = 0xffffffff << shift;
1428
1429                 if (cursor.size < bytes) {
1430                         mask &= 0xffffffff >> (bytes - cursor.size) * 8;
1431                         bytes = cursor.size;
1432                 }
1433
1434                 if (mask != 0xffffffff) {
1435                         spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1436                         WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1437                         WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1438                         value = RREG32_NO_KIQ(mmMM_DATA);
1439                         if (write) {
1440                                 value &= ~mask;
1441                                 value |= (*(uint32_t *)buf << shift) & mask;
1442                                 WREG32_NO_KIQ(mmMM_DATA, value);
1443                         }
1444                         spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1445                         if (!write) {
1446                                 value = (value & mask) >> shift;
1447                                 memcpy(buf, &value, bytes);
1448                         }
1449                 } else {
1450                         bytes = cursor.size & ~0x3ULL;
1451                         amdgpu_device_vram_access(adev, cursor.start,
1452                                                   (uint32_t *)buf, bytes,
1453                                                   write);
1454                 }
1455
1456                 ret += bytes;
1457                 buf = (uint8_t *)buf + bytes;
1458                 amdgpu_res_next(&cursor, bytes);
1459         }
1460
1461         return ret;
1462 }
1463
1464 static void
1465 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo)
1466 {
1467         amdgpu_bo_move_notify(bo, false, NULL);
1468 }
1469
1470 static struct ttm_device_funcs amdgpu_bo_driver = {
1471         .ttm_tt_create = &amdgpu_ttm_tt_create,
1472         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1473         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1474         .ttm_tt_destroy = &amdgpu_ttm_backend_destroy,
1475         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1476         .evict_flags = &amdgpu_evict_flags,
1477         .move = &amdgpu_bo_move,
1478         .verify_access = &amdgpu_verify_access,
1479         .delete_mem_notify = &amdgpu_bo_delete_mem_notify,
1480         .release_notify = &amdgpu_bo_release_notify,
1481         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1482         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1483         .access_memory = &amdgpu_ttm_access_memory,
1484         .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1485 };
1486
1487 /*
1488  * Firmware Reservation functions
1489  */
1490 /**
1491  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1492  *
1493  * @adev: amdgpu_device pointer
1494  *
1495  * free fw reserved vram if it has been reserved.
1496  */
1497 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1498 {
1499         amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo,
1500                 NULL, &adev->mman.fw_vram_usage_va);
1501 }
1502
1503 /**
1504  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1505  *
1506  * @adev: amdgpu_device pointer
1507  *
1508  * create bo vram reservation from fw.
1509  */
1510 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1511 {
1512         uint64_t vram_size = adev->gmc.visible_vram_size;
1513
1514         adev->mman.fw_vram_usage_va = NULL;
1515         adev->mman.fw_vram_usage_reserved_bo = NULL;
1516
1517         if (adev->mman.fw_vram_usage_size == 0 ||
1518             adev->mman.fw_vram_usage_size > vram_size)
1519                 return 0;
1520
1521         return amdgpu_bo_create_kernel_at(adev,
1522                                           adev->mman.fw_vram_usage_start_offset,
1523                                           adev->mman.fw_vram_usage_size,
1524                                           AMDGPU_GEM_DOMAIN_VRAM,
1525                                           &adev->mman.fw_vram_usage_reserved_bo,
1526                                           &adev->mman.fw_vram_usage_va);
1527 }
1528
1529 /*
1530  * Memoy training reservation functions
1531  */
1532
1533 /**
1534  * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1535  *
1536  * @adev: amdgpu_device pointer
1537  *
1538  * free memory training reserved vram if it has been reserved.
1539  */
1540 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1541 {
1542         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1543
1544         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1545         amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1546         ctx->c2p_bo = NULL;
1547
1548         return 0;
1549 }
1550
1551 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev)
1552 {
1553         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1554
1555         memset(ctx, 0, sizeof(*ctx));
1556
1557         ctx->c2p_train_data_offset =
1558                 ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M);
1559         ctx->p2c_train_data_offset =
1560                 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1561         ctx->train_data_size =
1562                 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1563
1564         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1565                         ctx->train_data_size,
1566                         ctx->p2c_train_data_offset,
1567                         ctx->c2p_train_data_offset);
1568 }
1569
1570 /*
1571  * reserve TMR memory at the top of VRAM which holds
1572  * IP Discovery data and is protected by PSP.
1573  */
1574 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
1575 {
1576         int ret;
1577         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1578         bool mem_train_support = false;
1579
1580         if (!amdgpu_sriov_vf(adev)) {
1581                 if (amdgpu_atomfirmware_mem_training_supported(adev))
1582                         mem_train_support = true;
1583                 else
1584                         DRM_DEBUG("memory training does not support!\n");
1585         }
1586
1587         /*
1588          * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all
1589          * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc)
1590          *
1591          * Otherwise, fallback to legacy approach to check and reserve tmr block for ip
1592          * discovery data and G6 memory training data respectively
1593          */
1594         adev->mman.discovery_tmr_size =
1595                 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
1596         if (!adev->mman.discovery_tmr_size)
1597                 adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET;
1598
1599         if (mem_train_support) {
1600                 /* reserve vram for mem train according to TMR location */
1601                 amdgpu_ttm_training_data_block_init(adev);
1602                 ret = amdgpu_bo_create_kernel_at(adev,
1603                                          ctx->c2p_train_data_offset,
1604                                          ctx->train_data_size,
1605                                          AMDGPU_GEM_DOMAIN_VRAM,
1606                                          &ctx->c2p_bo,
1607                                          NULL);
1608                 if (ret) {
1609                         DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1610                         amdgpu_ttm_training_reserve_vram_fini(adev);
1611                         return ret;
1612                 }
1613                 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1614         }
1615
1616         ret = amdgpu_bo_create_kernel_at(adev,
1617                                 adev->gmc.real_vram_size - adev->mman.discovery_tmr_size,
1618                                 adev->mman.discovery_tmr_size,
1619                                 AMDGPU_GEM_DOMAIN_VRAM,
1620                                 &adev->mman.discovery_memory,
1621                                 NULL);
1622         if (ret) {
1623                 DRM_ERROR("alloc tmr failed(%d)!\n", ret);
1624                 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1625                 return ret;
1626         }
1627
1628         return 0;
1629 }
1630
1631 /*
1632  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1633  * gtt/vram related fields.
1634  *
1635  * This initializes all of the memory space pools that the TTM layer
1636  * will need such as the GTT space (system memory mapped to the device),
1637  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1638  * can be mapped per VMID.
1639  */
1640 int amdgpu_ttm_init(struct amdgpu_device *adev)
1641 {
1642         uint64_t gtt_size;
1643         int r;
1644         u64 vis_vram_limit;
1645
1646         mutex_init(&adev->mman.gtt_window_lock);
1647
1648         /* No others user of address space so set it to 0 */
1649         r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev,
1650                                adev_to_drm(adev)->anon_inode->i_mapping,
1651                                adev_to_drm(adev)->vma_offset_manager,
1652                                adev->need_swiotlb,
1653                                dma_addressing_limited(adev->dev));
1654         if (r) {
1655                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1656                 return r;
1657         }
1658         adev->mman.initialized = true;
1659
1660         /* Initialize VRAM pool with all of VRAM divided into pages */
1661         r = amdgpu_vram_mgr_init(adev);
1662         if (r) {
1663                 DRM_ERROR("Failed initializing VRAM heap.\n");
1664                 return r;
1665         }
1666
1667         /* Reduce size of CPU-visible VRAM if requested */
1668         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1669         if (amdgpu_vis_vram_limit > 0 &&
1670             vis_vram_limit <= adev->gmc.visible_vram_size)
1671                 adev->gmc.visible_vram_size = vis_vram_limit;
1672
1673         /* Change the size here instead of the init above so only lpfn is affected */
1674         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1675 #ifdef CONFIG_64BIT
1676 #ifdef CONFIG_X86
1677         if (adev->gmc.xgmi.connected_to_cpu)
1678                 adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base,
1679                                 adev->gmc.visible_vram_size);
1680
1681         else
1682 #endif
1683                 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1684                                 adev->gmc.visible_vram_size);
1685 #endif
1686
1687         /*
1688          *The reserved vram for firmware must be pinned to the specified
1689          *place on the VRAM, so reserve it early.
1690          */
1691         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1692         if (r) {
1693                 return r;
1694         }
1695
1696         /*
1697          * only NAVI10 and onwards ASIC support for IP discovery.
1698          * If IP discovery enabled, a block of memory should be
1699          * reserved for IP discovey.
1700          */
1701         if (adev->mman.discovery_bin) {
1702                 r = amdgpu_ttm_reserve_tmr(adev);
1703                 if (r)
1704                         return r;
1705         }
1706
1707         /* allocate memory as required for VGA
1708          * This is used for VGA emulation and pre-OS scanout buffers to
1709          * avoid display artifacts while transitioning between pre-OS
1710          * and driver.  */
1711         r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size,
1712                                        AMDGPU_GEM_DOMAIN_VRAM,
1713                                        &adev->mman.stolen_vga_memory,
1714                                        NULL);
1715         if (r)
1716                 return r;
1717         r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size,
1718                                        adev->mman.stolen_extended_size,
1719                                        AMDGPU_GEM_DOMAIN_VRAM,
1720                                        &adev->mman.stolen_extended_memory,
1721                                        NULL);
1722         if (r)
1723                 return r;
1724
1725         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1726                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1727
1728         /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1729          * or whatever the user passed on module init */
1730         if (amdgpu_gtt_size == -1) {
1731                 struct sysinfo si;
1732
1733                 si_meminfo(&si);
1734                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1735                                adev->gmc.mc_vram_size),
1736                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1737         }
1738         else
1739                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1740
1741         /* Initialize GTT memory pool */
1742         r = amdgpu_gtt_mgr_init(adev, gtt_size);
1743         if (r) {
1744                 DRM_ERROR("Failed initializing GTT heap.\n");
1745                 return r;
1746         }
1747         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1748                  (unsigned)(gtt_size / (1024 * 1024)));
1749
1750         /* Initialize various on-chip memory pools */
1751         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size);
1752         if (r) {
1753                 DRM_ERROR("Failed initializing GDS heap.\n");
1754                 return r;
1755         }
1756
1757         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size);
1758         if (r) {
1759                 DRM_ERROR("Failed initializing gws heap.\n");
1760                 return r;
1761         }
1762
1763         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size);
1764         if (r) {
1765                 DRM_ERROR("Failed initializing oa heap.\n");
1766                 return r;
1767         }
1768
1769         return 0;
1770 }
1771
1772 /*
1773  * amdgpu_ttm_fini - De-initialize the TTM memory pools
1774  */
1775 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1776 {
1777         if (!adev->mman.initialized)
1778                 return;
1779
1780         amdgpu_ttm_training_reserve_vram_fini(adev);
1781         /* return the stolen vga memory back to VRAM */
1782         amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
1783         amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
1784         /* return the IP Discovery TMR memory back to VRAM */
1785         amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1786         amdgpu_ttm_fw_reserve_vram_fini(adev);
1787
1788         if (adev->mman.aper_base_kaddr)
1789                 iounmap(adev->mman.aper_base_kaddr);
1790         adev->mman.aper_base_kaddr = NULL;
1791
1792         amdgpu_vram_mgr_fini(adev);
1793         amdgpu_gtt_mgr_fini(adev);
1794         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS);
1795         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS);
1796         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA);
1797         ttm_device_fini(&adev->mman.bdev);
1798         adev->mman.initialized = false;
1799         DRM_INFO("amdgpu: ttm finalized\n");
1800 }
1801
1802 /**
1803  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
1804  *
1805  * @adev: amdgpu_device pointer
1806  * @enable: true when we can use buffer functions.
1807  *
1808  * Enable/disable use of buffer functions during suspend/resume. This should
1809  * only be called at bootup or when userspace isn't running.
1810  */
1811 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
1812 {
1813         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
1814         uint64_t size;
1815         int r;
1816
1817         if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
1818             adev->mman.buffer_funcs_enabled == enable)
1819                 return;
1820
1821         if (enable) {
1822                 struct amdgpu_ring *ring;
1823                 struct drm_gpu_scheduler *sched;
1824
1825                 ring = adev->mman.buffer_funcs_ring;
1826                 sched = &ring->sched;
1827                 r = drm_sched_entity_init(&adev->mman.entity,
1828                                           DRM_SCHED_PRIORITY_KERNEL, &sched,
1829                                           1, NULL);
1830                 if (r) {
1831                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
1832                                   r);
1833                         return;
1834                 }
1835         } else {
1836                 drm_sched_entity_destroy(&adev->mman.entity);
1837                 dma_fence_put(man->move);
1838                 man->move = NULL;
1839         }
1840
1841         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1842         if (enable)
1843                 size = adev->gmc.real_vram_size;
1844         else
1845                 size = adev->gmc.visible_vram_size;
1846         man->size = size >> PAGE_SHIFT;
1847         adev->mman.buffer_funcs_enabled = enable;
1848 }
1849
1850 static vm_fault_t amdgpu_ttm_fault(struct vm_fault *vmf)
1851 {
1852         struct ttm_buffer_object *bo = vmf->vma->vm_private_data;
1853         vm_fault_t ret;
1854
1855         ret = ttm_bo_vm_reserve(bo, vmf);
1856         if (ret)
1857                 return ret;
1858
1859         ret = amdgpu_bo_fault_reserve_notify(bo);
1860         if (ret)
1861                 goto unlock;
1862
1863         ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot,
1864                                        TTM_BO_VM_NUM_PREFAULT, 1);
1865         if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT))
1866                 return ret;
1867
1868 unlock:
1869         dma_resv_unlock(bo->base.resv);
1870         return ret;
1871 }
1872
1873 static const struct vm_operations_struct amdgpu_ttm_vm_ops = {
1874         .fault = amdgpu_ttm_fault,
1875         .open = ttm_bo_vm_open,
1876         .close = ttm_bo_vm_close,
1877         .access = ttm_bo_vm_access
1878 };
1879
1880 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1881 {
1882         struct drm_file *file_priv = filp->private_data;
1883         struct amdgpu_device *adev = drm_to_adev(file_priv->minor->dev);
1884         int r;
1885
1886         r = ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1887         if (unlikely(r != 0))
1888                 return r;
1889
1890         vma->vm_ops = &amdgpu_ttm_vm_ops;
1891         return 0;
1892 }
1893
1894 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
1895                        uint64_t dst_offset, uint32_t byte_count,
1896                        struct dma_resv *resv,
1897                        struct dma_fence **fence, bool direct_submit,
1898                        bool vm_needs_flush, bool tmz)
1899 {
1900         enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT :
1901                 AMDGPU_IB_POOL_DELAYED;
1902         struct amdgpu_device *adev = ring->adev;
1903         struct amdgpu_job *job;
1904
1905         uint32_t max_bytes;
1906         unsigned num_loops, num_dw;
1907         unsigned i;
1908         int r;
1909
1910         if (direct_submit && !ring->sched.ready) {
1911                 DRM_ERROR("Trying to move memory with ring turned off.\n");
1912                 return -EINVAL;
1913         }
1914
1915         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1916         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1917         num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
1918
1919         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job);
1920         if (r)
1921                 return r;
1922
1923         if (vm_needs_flush) {
1924                 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ?
1925                                         adev->gmc.pdb0_bo : adev->gart.bo);
1926                 job->vm_needs_flush = true;
1927         }
1928         if (resv) {
1929                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1930                                      AMDGPU_SYNC_ALWAYS,
1931                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1932                 if (r) {
1933                         DRM_ERROR("sync failed (%d).\n", r);
1934                         goto error_free;
1935                 }
1936         }
1937
1938         for (i = 0; i < num_loops; i++) {
1939                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1940
1941                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1942                                         dst_offset, cur_size_in_bytes, tmz);
1943
1944                 src_offset += cur_size_in_bytes;
1945                 dst_offset += cur_size_in_bytes;
1946                 byte_count -= cur_size_in_bytes;
1947         }
1948
1949         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1950         WARN_ON(job->ibs[0].length_dw > num_dw);
1951         if (direct_submit)
1952                 r = amdgpu_job_submit_direct(job, ring, fence);
1953         else
1954                 r = amdgpu_job_submit(job, &adev->mman.entity,
1955                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1956         if (r)
1957                 goto error_free;
1958
1959         return r;
1960
1961 error_free:
1962         amdgpu_job_free(job);
1963         DRM_ERROR("Error scheduling IBs (%d)\n", r);
1964         return r;
1965 }
1966
1967 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1968                        uint32_t src_data,
1969                        struct dma_resv *resv,
1970                        struct dma_fence **fence)
1971 {
1972         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1973         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
1974         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1975
1976         struct amdgpu_res_cursor cursor;
1977         unsigned int num_loops, num_dw;
1978         uint64_t num_bytes;
1979
1980         struct amdgpu_job *job;
1981         int r;
1982
1983         if (!adev->mman.buffer_funcs_enabled) {
1984                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
1985                 return -EINVAL;
1986         }
1987
1988         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
1989                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
1990                 if (r)
1991                         return r;
1992         }
1993
1994         num_bytes = bo->tbo.mem.num_pages << PAGE_SHIFT;
1995         num_loops = 0;
1996
1997         amdgpu_res_first(&bo->tbo.mem, 0, num_bytes, &cursor);
1998         while (cursor.remaining) {
1999                 num_loops += DIV_ROUND_UP_ULL(cursor.size, max_bytes);
2000                 amdgpu_res_next(&cursor, cursor.size);
2001         }
2002         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2003
2004         /* for IB padding */
2005         num_dw += 64;
2006
2007         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED,
2008                                      &job);
2009         if (r)
2010                 return r;
2011
2012         if (resv) {
2013                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2014                                      AMDGPU_SYNC_ALWAYS,
2015                                      AMDGPU_FENCE_OWNER_UNDEFINED);
2016                 if (r) {
2017                         DRM_ERROR("sync failed (%d).\n", r);
2018                         goto error_free;
2019                 }
2020         }
2021
2022         amdgpu_res_first(&bo->tbo.mem, 0, num_bytes, &cursor);
2023         while (cursor.remaining) {
2024                 uint32_t cur_size = min_t(uint64_t, cursor.size, max_bytes);
2025                 uint64_t dst_addr = cursor.start;
2026
2027                 dst_addr += amdgpu_ttm_domain_start(adev, bo->tbo.mem.mem_type);
2028                 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr,
2029                                         cur_size);
2030
2031                 amdgpu_res_next(&cursor, cur_size);
2032         }
2033
2034         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2035         WARN_ON(job->ibs[0].length_dw > num_dw);
2036         r = amdgpu_job_submit(job, &adev->mman.entity,
2037                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2038         if (r)
2039                 goto error_free;
2040
2041         return 0;
2042
2043 error_free:
2044         amdgpu_job_free(job);
2045         return r;
2046 }
2047
2048 #if defined(CONFIG_DEBUG_FS)
2049
2050 static int amdgpu_mm_vram_table_show(struct seq_file *m, void *unused)
2051 {
2052         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2053         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2054                                                             TTM_PL_VRAM);
2055         struct drm_printer p = drm_seq_file_printer(m);
2056
2057         man->func->debug(man, &p);
2058         return 0;
2059 }
2060
2061 static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused)
2062 {
2063         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2064
2065         return ttm_pool_debugfs(&adev->mman.bdev.pool, m);
2066 }
2067
2068 static int amdgpu_mm_tt_table_show(struct seq_file *m, void *unused)
2069 {
2070         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2071         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2072                                                             TTM_PL_TT);
2073         struct drm_printer p = drm_seq_file_printer(m);
2074
2075         man->func->debug(man, &p);
2076         return 0;
2077 }
2078
2079 static int amdgpu_mm_gds_table_show(struct seq_file *m, void *unused)
2080 {
2081         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2082         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2083                                                             AMDGPU_PL_GDS);
2084         struct drm_printer p = drm_seq_file_printer(m);
2085
2086         man->func->debug(man, &p);
2087         return 0;
2088 }
2089
2090 static int amdgpu_mm_gws_table_show(struct seq_file *m, void *unused)
2091 {
2092         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2093         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2094                                                             AMDGPU_PL_GWS);
2095         struct drm_printer p = drm_seq_file_printer(m);
2096
2097         man->func->debug(man, &p);
2098         return 0;
2099 }
2100
2101 static int amdgpu_mm_oa_table_show(struct seq_file *m, void *unused)
2102 {
2103         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2104         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2105                                                             AMDGPU_PL_OA);
2106         struct drm_printer p = drm_seq_file_printer(m);
2107
2108         man->func->debug(man, &p);
2109         return 0;
2110 }
2111
2112 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_vram_table);
2113 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_tt_table);
2114 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gds_table);
2115 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gws_table);
2116 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_oa_table);
2117 DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool);
2118
2119 /*
2120  * amdgpu_ttm_vram_read - Linear read access to VRAM
2121  *
2122  * Accesses VRAM via MMIO for debugging purposes.
2123  */
2124 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2125                                     size_t size, loff_t *pos)
2126 {
2127         struct amdgpu_device *adev = file_inode(f)->i_private;
2128         ssize_t result = 0;
2129
2130         if (size & 0x3 || *pos & 0x3)
2131                 return -EINVAL;
2132
2133         if (*pos >= adev->gmc.mc_vram_size)
2134                 return -ENXIO;
2135
2136         size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2137         while (size) {
2138                 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2139                 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2140
2141                 amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2142                 if (copy_to_user(buf, value, bytes))
2143                         return -EFAULT;
2144
2145                 result += bytes;
2146                 buf += bytes;
2147                 *pos += bytes;
2148                 size -= bytes;
2149         }
2150
2151         return result;
2152 }
2153
2154 /*
2155  * amdgpu_ttm_vram_write - Linear write access to VRAM
2156  *
2157  * Accesses VRAM via MMIO for debugging purposes.
2158  */
2159 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2160                                     size_t size, loff_t *pos)
2161 {
2162         struct amdgpu_device *adev = file_inode(f)->i_private;
2163         ssize_t result = 0;
2164         int r;
2165
2166         if (size & 0x3 || *pos & 0x3)
2167                 return -EINVAL;
2168
2169         if (*pos >= adev->gmc.mc_vram_size)
2170                 return -ENXIO;
2171
2172         while (size) {
2173                 unsigned long flags;
2174                 uint32_t value;
2175
2176                 if (*pos >= adev->gmc.mc_vram_size)
2177                         return result;
2178
2179                 r = get_user(value, (uint32_t *)buf);
2180                 if (r)
2181                         return r;
2182
2183                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2184                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2185                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2186                 WREG32_NO_KIQ(mmMM_DATA, value);
2187                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2188
2189                 result += 4;
2190                 buf += 4;
2191                 *pos += 4;
2192                 size -= 4;
2193         }
2194
2195         return result;
2196 }
2197
2198 static const struct file_operations amdgpu_ttm_vram_fops = {
2199         .owner = THIS_MODULE,
2200         .read = amdgpu_ttm_vram_read,
2201         .write = amdgpu_ttm_vram_write,
2202         .llseek = default_llseek,
2203 };
2204
2205 /*
2206  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2207  *
2208  * This function is used to read memory that has been mapped to the
2209  * GPU and the known addresses are not physical addresses but instead
2210  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2211  */
2212 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2213                                  size_t size, loff_t *pos)
2214 {
2215         struct amdgpu_device *adev = file_inode(f)->i_private;
2216         struct iommu_domain *dom;
2217         ssize_t result = 0;
2218         int r;
2219
2220         /* retrieve the IOMMU domain if any for this device */
2221         dom = iommu_get_domain_for_dev(adev->dev);
2222
2223         while (size) {
2224                 phys_addr_t addr = *pos & PAGE_MASK;
2225                 loff_t off = *pos & ~PAGE_MASK;
2226                 size_t bytes = PAGE_SIZE - off;
2227                 unsigned long pfn;
2228                 struct page *p;
2229                 void *ptr;
2230
2231                 bytes = bytes < size ? bytes : size;
2232
2233                 /* Translate the bus address to a physical address.  If
2234                  * the domain is NULL it means there is no IOMMU active
2235                  * and the address translation is the identity
2236                  */
2237                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2238
2239                 pfn = addr >> PAGE_SHIFT;
2240                 if (!pfn_valid(pfn))
2241                         return -EPERM;
2242
2243                 p = pfn_to_page(pfn);
2244                 if (p->mapping != adev->mman.bdev.dev_mapping)
2245                         return -EPERM;
2246
2247                 ptr = kmap(p);
2248                 r = copy_to_user(buf, ptr + off, bytes);
2249                 kunmap(p);
2250                 if (r)
2251                         return -EFAULT;
2252
2253                 size -= bytes;
2254                 *pos += bytes;
2255                 result += bytes;
2256         }
2257
2258         return result;
2259 }
2260
2261 /*
2262  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2263  *
2264  * This function is used to write memory that has been mapped to the
2265  * GPU and the known addresses are not physical addresses but instead
2266  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2267  */
2268 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2269                                  size_t size, loff_t *pos)
2270 {
2271         struct amdgpu_device *adev = file_inode(f)->i_private;
2272         struct iommu_domain *dom;
2273         ssize_t result = 0;
2274         int r;
2275
2276         dom = iommu_get_domain_for_dev(adev->dev);
2277
2278         while (size) {
2279                 phys_addr_t addr = *pos & PAGE_MASK;
2280                 loff_t off = *pos & ~PAGE_MASK;
2281                 size_t bytes = PAGE_SIZE - off;
2282                 unsigned long pfn;
2283                 struct page *p;
2284                 void *ptr;
2285
2286                 bytes = bytes < size ? bytes : size;
2287
2288                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2289
2290                 pfn = addr >> PAGE_SHIFT;
2291                 if (!pfn_valid(pfn))
2292                         return -EPERM;
2293
2294                 p = pfn_to_page(pfn);
2295                 if (p->mapping != adev->mman.bdev.dev_mapping)
2296                         return -EPERM;
2297
2298                 ptr = kmap(p);
2299                 r = copy_from_user(ptr + off, buf, bytes);
2300                 kunmap(p);
2301                 if (r)
2302                         return -EFAULT;
2303
2304                 size -= bytes;
2305                 *pos += bytes;
2306                 result += bytes;
2307         }
2308
2309         return result;
2310 }
2311
2312 static const struct file_operations amdgpu_ttm_iomem_fops = {
2313         .owner = THIS_MODULE,
2314         .read = amdgpu_iomem_read,
2315         .write = amdgpu_iomem_write,
2316         .llseek = default_llseek
2317 };
2318
2319 #endif
2320
2321 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2322 {
2323 #if defined(CONFIG_DEBUG_FS)
2324         struct drm_minor *minor = adev_to_drm(adev)->primary;
2325         struct dentry *root = minor->debugfs_root;
2326
2327         debugfs_create_file_size("amdgpu_vram", 0444, root, adev,
2328                                  &amdgpu_ttm_vram_fops, adev->gmc.mc_vram_size);
2329         debugfs_create_file("amdgpu_iomem", 0444, root, adev,
2330                             &amdgpu_ttm_iomem_fops);
2331         debugfs_create_file("amdgpu_vram_mm", 0444, root, adev,
2332                             &amdgpu_mm_vram_table_fops);
2333         debugfs_create_file("amdgpu_gtt_mm", 0444, root, adev,
2334                             &amdgpu_mm_tt_table_fops);
2335         debugfs_create_file("amdgpu_gds_mm", 0444, root, adev,
2336                             &amdgpu_mm_gds_table_fops);
2337         debugfs_create_file("amdgpu_gws_mm", 0444, root, adev,
2338                             &amdgpu_mm_gws_table_fops);
2339         debugfs_create_file("amdgpu_oa_mm", 0444, root, adev,
2340                             &amdgpu_mm_oa_table_fops);
2341         debugfs_create_file("ttm_page_pool", 0444, root, adev,
2342                             &amdgpu_ttm_page_pool_fops);
2343 #endif
2344 }