drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include <linux/dma-mapping.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_psp.h"
  31 #include "amdgpu_ucode.h"
  32 #include "soc15_common.h"
  33 #include "psp_v3_1.h"
  34 #include "psp_v10_0.h"
  35 #include "psp_v11_0.h"
  36 #include "psp_v12_0.h"
  37 #include "psp_v13_0.h"
  38
  39 #include "amdgpu_ras.h"
  40 #include "amdgpu_securedisplay.h"
  41 #include "amdgpu_atomfirmware.h"
  42
  43 static int psp_sysfs_init(struct amdgpu_device *adev);
  44 static void psp_sysfs_fini(struct amdgpu_device *adev);
  45
  46 static int psp_load_smu_fw(struct psp_context *psp);
  47
  48 /*
  49  * Due to DF Cstate management centralized to PMFW, the firmware
  50  * loading sequence will be updated as below:
  51  *   - Load KDB
  52  *   - Load SYS_DRV
  53  *   - Load tOS
  54  *   - Load PMFW
  55  *   - Setup TMR
  56  *   - Load other non-psp fw
  57  *   - Load ASD
  58  *   - Load XGMI/RAS/HDCP/DTM TA if any
  59  *
  60  * This new sequence is required for
  61  *   - Arcturus and onwards
  62  *   - Navi12 and onwards
  63  */
  64 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp)
  65 {
  66         struct amdgpu_device *adev = psp->adev;
  67
  68         psp->pmfw_centralized_cstate_management = false;
  69
  70         if (amdgpu_sriov_vf(adev))
  71                 return;
  72
  73         if (adev->flags & AMD_IS_APU)
  74                 return;
  75
  76         if ((adev->asic_type >= CHIP_ARCTURUS) ||
  77             (adev->asic_type >= CHIP_NAVI12))
  78                 psp->pmfw_centralized_cstate_management = true;
  79 }
  80
  81 static int psp_early_init(void *handle)
  82 {
  83         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  84         struct psp_context *psp = &adev->psp;
  85
  86         switch (adev->asic_type) {
  87         case CHIP_VEGA10:
  88         case CHIP_VEGA12:
  89                 psp_v3_1_set_psp_funcs(psp);
  90                 psp->autoload_supported = false;
  91                 break;
  92         case CHIP_RAVEN:
  93                 psp_v10_0_set_psp_funcs(psp);
  94                 psp->autoload_supported = false;
  95                 break;
  96         case CHIP_VEGA20:
  97         case CHIP_ARCTURUS:
  98                 psp_v11_0_set_psp_funcs(psp);
  99                 psp->autoload_supported = false;
 100                 break;
 101         case CHIP_NAVI10:
 102         case CHIP_NAVI14:
 103         case CHIP_NAVI12:
 104         case CHIP_SIENNA_CICHLID:
 105         case CHIP_NAVY_FLOUNDER:
 106         case CHIP_VANGOGH:
 107         case CHIP_DIMGREY_CAVEFISH:
 108         case CHIP_BEIGE_GOBY:
 109                 psp_v11_0_set_psp_funcs(psp);
 110                 psp->autoload_supported = true;
 111                 break;
 112         case CHIP_RENOIR:
 113                 psp_v12_0_set_psp_funcs(psp);
 114                 break;
 115         case CHIP_ALDEBARAN:
 116                 psp_v13_0_set_psp_funcs(psp);
 117                 break;
 118         default:
 119                 return -EINVAL;
 120         }
 121
 122         psp->adev = adev;
 123
 124         psp_check_pmfw_centralized_cstate_management(psp);
 125
 126         return 0;
 127 }
 128
 129 static void psp_memory_training_fini(struct psp_context *psp)
 130 {
 131         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 132
 133         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
 134         kfree(ctx->sys_cache);
 135         ctx->sys_cache = NULL;
 136 }
 137
 138 static int psp_memory_training_init(struct psp_context *psp)
 139 {
 140         int ret;
 141         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 142
 143         if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
 144                 DRM_DEBUG("memory training is not supported!\n");
 145                 return 0;
 146         }
 147
 148         ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
 149         if (ctx->sys_cache == NULL) {
 150                 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
 151                 ret = -ENOMEM;
 152                 goto Err_out;
 153         }
 154
 155         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
 156                   ctx->train_data_size,
 157                   ctx->p2c_train_data_offset,
 158                   ctx->c2p_train_data_offset);
 159         ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
 160         return 0;
 161
 162 Err_out:
 163         psp_memory_training_fini(psp);
 164         return ret;
 165 }
 166
 167 static int psp_sw_init(void *handle)
 168 {
 169         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 170         struct psp_context *psp = &adev->psp;
 171         int ret;
 172
 173         if (!amdgpu_sriov_vf(adev)) {
 174                 ret = psp_init_microcode(psp);
 175                 if (ret) {
 176                         DRM_ERROR("Failed to load psp firmware!\n");
 177                         return ret;
 178                 }
 179         }
 180
 181         ret = psp_memory_training_init(psp);
 182         if (ret) {
 183                 DRM_ERROR("Failed to initialize memory training!\n");
 184                 return ret;
 185         }
 186         ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
 187         if (ret) {
 188                 DRM_ERROR("Failed to process memory training!\n");
 189                 return ret;
 190         }
 191
 192         if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_SIENNA_CICHLID) {
 193                 ret= psp_sysfs_init(adev);
 194                 if (ret) {
 195                         return ret;
 196                 }
 197         }
 198
 199         return 0;
 200 }
 201
 202 static int psp_sw_fini(void *handle)
 203 {
 204         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 205
 206         psp_memory_training_fini(&adev->psp);
 207         if (adev->psp.sos_fw) {
 208                 release_firmware(adev->psp.sos_fw);
 209                 adev->psp.sos_fw = NULL;
 210         }
 211         if (adev->psp.asd_fw) {
 212                 release_firmware(adev->psp.asd_fw);
 213                 adev->psp.asd_fw = NULL;
 214         }
 215         if (adev->psp.ta_fw) {
 216                 release_firmware(adev->psp.ta_fw);
 217                 adev->psp.ta_fw = NULL;
 218         }
 219
 220         if (adev->asic_type == CHIP_NAVI10 ||
 221             adev->asic_type == CHIP_SIENNA_CICHLID)
 222                 psp_sysfs_fini(adev);
 223
 224         return 0;
 225 }
 226
 227 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
 228                  uint32_t reg_val, uint32_t mask, bool check_changed)
 229 {
 230         uint32_t val;
 231         int i;
 232         struct amdgpu_device *adev = psp->adev;
 233
 234         if (psp->adev->in_pci_err_recovery)
 235                 return 0;
 236
 237         for (i = 0; i < adev->usec_timeout; i++) {
 238                 val = RREG32(reg_index);
 239                 if (check_changed) {
 240                         if (val != reg_val)
 241                                 return 0;
 242                 } else {
 243                         if ((val & mask) == reg_val)
 244                                 return 0;
 245                 }
 246                 udelay(1);
 247         }
 248
 249         return -ETIME;
 250 }
 251
 252 static int
 253 psp_cmd_submit_buf(struct psp_context *psp,
 254                    struct amdgpu_firmware_info *ucode,
 255                    struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
 256 {
 257         int ret;
 258         int index;
 259         int timeout = 20000;
 260         bool ras_intr = false;
 261         bool skip_unsupport = false;
 262
 263         if (psp->adev->in_pci_err_recovery)
 264                 return 0;
 265
 266         mutex_lock(&psp->mutex);
 267
 268         memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
 269
 270         memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 271
 272         index = atomic_inc_return(&psp->fence_value);
 273         ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
 274         if (ret) {
 275                 atomic_dec(&psp->fence_value);
 276                 mutex_unlock(&psp->mutex);
 277                 return ret;
 278         }
 279
 280         amdgpu_asic_invalidate_hdp(psp->adev, NULL);
 281         while (*((unsigned int *)psp->fence_buf) != index) {
 282                 if (--timeout == 0)
 283                         break;
 284                 /*
 285                  * Shouldn't wait for timeout when err_event_athub occurs,
 286                  * because gpu reset thread triggered and lock resource should
 287                  * be released for psp resume sequence.
 288                  */
 289                 ras_intr = amdgpu_ras_intr_triggered();
 290                 if (ras_intr)
 291                         break;
 292                 usleep_range(10, 100);
 293                 amdgpu_asic_invalidate_hdp(psp->adev, NULL);
 294         }
 295
 296         /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
 297         skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED ||
 298                 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev);
 299
 300         memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp));
 301
 302         /* In some cases, psp response status is not 0 even there is no
 303          * problem while the command is submitted. Some version of PSP FW
 304          * doesn't write 0 to that field.
 305          * So here we would like to only print a warning instead of an error
 306          * during psp initialization to avoid breaking hw_init and it doesn't
 307          * return -EINVAL.
 308          */
 309         if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
 310                 if (ucode)
 311                         DRM_WARN("failed to load ucode id (%d) ",
 312                                   ucode->ucode_id);
 313                 DRM_WARN("psp command (0x%X) failed and response status is (0x%X)\n",
 314                          psp->cmd_buf_mem->cmd_id,
 315                          psp->cmd_buf_mem->resp.status);
 316                 if (!timeout) {
 317                         mutex_unlock(&psp->mutex);
 318                         return -EINVAL;
 319                 }
 320         }
 321
 322         if (ucode) {
 323                 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
 324                 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
 325         }
 326         mutex_unlock(&psp->mutex);
 327
 328         return ret;
 329 }
 330
 331 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
 332                                  struct psp_gfx_cmd_resp *cmd,
 333                                  uint64_t tmr_mc, struct amdgpu_bo *tmr_bo)
 334 {
 335         struct amdgpu_device *adev = psp->adev;
 336         uint32_t size = amdgpu_bo_size(tmr_bo);
 337         uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo);
 338
 339         if (amdgpu_sriov_vf(psp->adev))
 340                 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
 341         else
 342                 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
 343         cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
 344         cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
 345         cmd->cmd.cmd_setup_tmr.buf_size = size;
 346         cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1;
 347         cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa);
 348         cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa);
 349 }
 350
 351 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 352                                       uint64_t pri_buf_mc, uint32_t size)
 353 {
 354         cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
 355         cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
 356         cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
 357         cmd->cmd.cmd_load_toc.toc_size = size;
 358 }
 359
 360 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
 361 static int psp_load_toc(struct psp_context *psp,
 362                         uint32_t *tmr_size)
 363 {
 364         int ret;
 365         struct psp_gfx_cmd_resp *cmd;
 366
 367         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 368         if (!cmd)
 369                 return -ENOMEM;
 370         /* Copy toc to psp firmware private buffer */
 371         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 372         memcpy(psp->fw_pri_buf, psp->toc_start_addr, psp->toc_bin_size);
 373
 374         psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size);
 375
 376         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 377                                  psp->fence_buf_mc_addr);
 378         if (!ret)
 379                 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
 380         kfree(cmd);
 381         return ret;
 382 }
 383
 384 /* Set up Trusted Memory Region */
 385 static int psp_tmr_init(struct psp_context *psp)
 386 {
 387         int ret;
 388         int tmr_size;
 389         void *tmr_buf;
 390         void **pptr;
 391
 392         /*
 393          * According to HW engineer, they prefer the TMR address be "naturally
 394          * aligned" , e.g. the start address be an integer divide of TMR size.
 395          *
 396          * Note: this memory need be reserved till the driver
 397          * uninitializes.
 398          */
 399         tmr_size = PSP_TMR_SIZE(psp->adev);
 400
 401         /* For ASICs support RLC autoload, psp will parse the toc
 402          * and calculate the total size of TMR needed */
 403         if (!amdgpu_sriov_vf(psp->adev) &&
 404             psp->toc_start_addr &&
 405             psp->toc_bin_size &&
 406             psp->fw_pri_buf) {
 407                 ret = psp_load_toc(psp, &tmr_size);
 408                 if (ret) {
 409                         DRM_ERROR("Failed to load toc\n");
 410                         return ret;
 411                 }
 412         }
 413
 414         pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 415         ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev),
 416                                       AMDGPU_GEM_DOMAIN_VRAM,
 417                                       &psp->tmr_bo, &psp->tmr_mc_addr, pptr);
 418
 419         return ret;
 420 }
 421
 422 static bool psp_skip_tmr(struct psp_context *psp)
 423 {
 424         switch (psp->adev->asic_type) {
 425         case CHIP_NAVI12:
 426         case CHIP_SIENNA_CICHLID:
 427         case CHIP_ALDEBARAN:
 428                 return true;
 429         default:
 430                 return false;
 431         }
 432 }
 433
 434 static int psp_tmr_load(struct psp_context *psp)
 435 {
 436         int ret;
 437         struct psp_gfx_cmd_resp *cmd;
 438
 439         /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR.
 440          * Already set up by host driver.
 441          */
 442         if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
 443                 return 0;
 444
 445         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 446         if (!cmd)
 447                 return -ENOMEM;
 448
 449         psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo);
 450         DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
 451                  amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
 452
 453         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 454                                  psp->fence_buf_mc_addr);
 455
 456         kfree(cmd);
 457
 458         return ret;
 459 }
 460
 461 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp,
 462                                         struct psp_gfx_cmd_resp *cmd)
 463 {
 464         if (amdgpu_sriov_vf(psp->adev))
 465                 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR;
 466         else
 467                 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR;
 468 }
 469
 470 static int psp_tmr_unload(struct psp_context *psp)
 471 {
 472         int ret;
 473         struct psp_gfx_cmd_resp *cmd;
 474
 475         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 476         if (!cmd)
 477                 return -ENOMEM;
 478
 479         psp_prep_tmr_unload_cmd_buf(psp, cmd);
 480         DRM_INFO("free PSP TMR buffer\n");
 481
 482         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 483                                  psp->fence_buf_mc_addr);
 484
 485         kfree(cmd);
 486
 487         return ret;
 488 }
 489
 490 static int psp_tmr_terminate(struct psp_context *psp)
 491 {
 492         int ret;
 493         void *tmr_buf;
 494         void **pptr;
 495
 496         ret = psp_tmr_unload(psp);
 497         if (ret)
 498                 return ret;
 499
 500         /* free TMR memory buffer */
 501         pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 502         amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
 503
 504         return 0;
 505 }
 506
 507 int psp_get_fw_attestation_records_addr(struct psp_context *psp,
 508                                         uint64_t *output_ptr)
 509 {
 510         int ret;
 511         struct psp_gfx_cmd_resp *cmd;
 512
 513         if (!output_ptr)
 514                 return -EINVAL;
 515
 516         if (amdgpu_sriov_vf(psp->adev))
 517                 return 0;
 518
 519         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 520         if (!cmd)
 521                 return -ENOMEM;
 522
 523         cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION;
 524
 525         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 526                                  psp->fence_buf_mc_addr);
 527
 528         if (!ret) {
 529                 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) +
 530                               ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32);
 531         }
 532
 533         kfree(cmd);
 534
 535         return ret;
 536 }
 537
 538 static int psp_boot_config_set(struct amdgpu_device *adev)
 539 {
 540         struct psp_context *psp = &adev->psp;
 541         struct psp_gfx_cmd_resp *cmd = psp->cmd;
 542
 543         if (amdgpu_sriov_vf(adev))
 544                 return 0;
 545
 546         memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
 547
 548         cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
 549         cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET;
 550         cmd->cmd.boot_cfg.boot_config = BOOT_CONFIG_GECC;
 551         cmd->cmd.boot_cfg.boot_config_valid = BOOT_CONFIG_GECC;
 552
 553         return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 554 }
 555
 556 static int psp_rl_load(struct amdgpu_device *adev)
 557 {
 558         struct psp_context *psp = &adev->psp;
 559         struct psp_gfx_cmd_resp *cmd = psp->cmd;
 560
 561         if (psp->rl_bin_size == 0)
 562                 return 0;
 563
 564         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 565         memcpy(psp->fw_pri_buf, psp->rl_start_addr, psp->rl_bin_size);
 566
 567         memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
 568
 569         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
 570         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr);
 571         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr);
 572         cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl_bin_size;
 573         cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST;
 574
 575         return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 576 }
 577
 578 static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 579                                 uint64_t asd_mc, uint32_t size)
 580 {
 581         cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
 582         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
 583         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
 584         cmd->cmd.cmd_load_ta.app_len = size;
 585
 586         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0;
 587         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0;
 588         cmd->cmd.cmd_load_ta.cmd_buf_len = 0;
 589 }
 590
 591 static int psp_asd_load(struct psp_context *psp)
 592 {
 593         int ret;
 594         struct psp_gfx_cmd_resp *cmd;
 595
 596         /* If PSP version doesn't match ASD version, asd loading will be failed.
 597          * add workaround to bypass it for sriov now.
 598          * TODO: add version check to make it common
 599          */
 600         if (amdgpu_sriov_vf(psp->adev) || !psp->asd_ucode_size)
 601                 return 0;
 602
 603         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 604         if (!cmd)
 605                 return -ENOMEM;
 606
 607         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 608         memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
 609
 610         psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
 611                                   psp->asd_ucode_size);
 612
 613         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 614                                  psp->fence_buf_mc_addr);
 615         if (!ret) {
 616                 psp->asd_context.asd_initialized = true;
 617                 psp->asd_context.session_id = cmd->resp.session_id;
 618         }
 619
 620         kfree(cmd);
 621
 622         return ret;
 623 }
 624
 625 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 626                                        uint32_t session_id)
 627 {
 628         cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
 629         cmd->cmd.cmd_unload_ta.session_id = session_id;
 630 }
 631
 632 static int psp_asd_unload(struct psp_context *psp)
 633 {
 634         int ret;
 635         struct psp_gfx_cmd_resp *cmd;
 636
 637         if (amdgpu_sriov_vf(psp->adev))
 638                 return 0;
 639
 640         if (!psp->asd_context.asd_initialized)
 641                 return 0;
 642
 643         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 644         if (!cmd)
 645                 return -ENOMEM;
 646
 647         psp_prep_ta_unload_cmd_buf(cmd, psp->asd_context.session_id);
 648
 649         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 650                                  psp->fence_buf_mc_addr);
 651         if (!ret)
 652                 psp->asd_context.asd_initialized = false;
 653
 654         kfree(cmd);
 655
 656         return ret;
 657 }
 658
 659 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 660                 uint32_t id, uint32_t value)
 661 {
 662         cmd->cmd_id = GFX_CMD_ID_PROG_REG;
 663         cmd->cmd.cmd_setup_reg_prog.reg_value = value;
 664         cmd->cmd.cmd_setup_reg_prog.reg_id = id;
 665 }
 666
 667 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
 668                 uint32_t value)
 669 {
 670         struct psp_gfx_cmd_resp *cmd = NULL;
 671         int ret = 0;
 672
 673         if (reg >= PSP_REG_LAST)
 674                 return -EINVAL;
 675
 676         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 677         if (!cmd)
 678                 return -ENOMEM;
 679
 680         psp_prep_reg_prog_cmd_buf(cmd, reg, value);
 681         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 682
 683         kfree(cmd);
 684         return ret;
 685 }
 686
 687 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 688                                      uint64_t ta_bin_mc,
 689                                      uint32_t ta_bin_size,
 690                                      uint64_t ta_shared_mc,
 691                                      uint32_t ta_shared_size)
 692 {
 693         cmd->cmd_id                             = GFX_CMD_ID_LOAD_TA;
 694         cmd->cmd.cmd_load_ta.app_phy_addr_lo    = lower_32_bits(ta_bin_mc);
 695         cmd->cmd.cmd_load_ta.app_phy_addr_hi    = upper_32_bits(ta_bin_mc);
 696         cmd->cmd.cmd_load_ta.app_len            = ta_bin_size;
 697
 698         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ta_shared_mc);
 699         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ta_shared_mc);
 700         cmd->cmd.cmd_load_ta.cmd_buf_len         = ta_shared_size;
 701 }
 702
 703 static int psp_xgmi_init_shared_buf(struct psp_context *psp)
 704 {
 705         int ret;
 706
 707         /*
 708          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 709          * physical) for xgmi ta <-> Driver
 710          */
 711         ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE,
 712                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 713                                       &psp->xgmi_context.xgmi_shared_bo,
 714                                       &psp->xgmi_context.xgmi_shared_mc_addr,
 715                                       &psp->xgmi_context.xgmi_shared_buf);
 716
 717         return ret;
 718 }
 719
 720 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 721                                        uint32_t ta_cmd_id,
 722                                        uint32_t session_id)
 723 {
 724         cmd->cmd_id                             = GFX_CMD_ID_INVOKE_CMD;
 725         cmd->cmd.cmd_invoke_cmd.session_id      = session_id;
 726         cmd->cmd.cmd_invoke_cmd.ta_cmd_id       = ta_cmd_id;
 727 }
 728
 729 static int psp_ta_invoke(struct psp_context *psp,
 730                   uint32_t ta_cmd_id,
 731                   uint32_t session_id)
 732 {
 733         int ret;
 734         struct psp_gfx_cmd_resp *cmd;
 735
 736         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 737         if (!cmd)
 738                 return -ENOMEM;
 739
 740         psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, session_id);
 741
 742         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 743                                  psp->fence_buf_mc_addr);
 744
 745         kfree(cmd);
 746
 747         return ret;
 748 }
 749
 750 static int psp_xgmi_load(struct psp_context *psp)
 751 {
 752         int ret;
 753         struct psp_gfx_cmd_resp *cmd;
 754
 755         /*
 756          * TODO: bypass the loading in sriov for now
 757          */
 758
 759         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 760         if (!cmd)
 761                 return -ENOMEM;
 762
 763         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 764         memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size);
 765
 766         psp_prep_ta_load_cmd_buf(cmd,
 767                                  psp->fw_pri_mc_addr,
 768                                  psp->ta_xgmi_ucode_size,
 769                                  psp->xgmi_context.xgmi_shared_mc_addr,
 770                                  PSP_XGMI_SHARED_MEM_SIZE);
 771
 772         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 773                                  psp->fence_buf_mc_addr);
 774
 775         if (!ret) {
 776                 psp->xgmi_context.initialized = 1;
 777                 psp->xgmi_context.session_id = cmd->resp.session_id;
 778         }
 779
 780         kfree(cmd);
 781
 782         return ret;
 783 }
 784
 785 static int psp_xgmi_unload(struct psp_context *psp)
 786 {
 787         int ret;
 788         struct psp_gfx_cmd_resp *cmd;
 789         struct amdgpu_device *adev = psp->adev;
 790
 791         /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
 792         if (adev->asic_type == CHIP_ARCTURUS ||
 793                 (adev->asic_type == CHIP_ALDEBARAN && adev->gmc.xgmi.connected_to_cpu))
 794                 return 0;
 795
 796         /*
 797          * TODO: bypass the unloading in sriov for now
 798          */
 799
 800         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 801         if (!cmd)
 802                 return -ENOMEM;
 803
 804         psp_prep_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id);
 805
 806         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 807                                  psp->fence_buf_mc_addr);
 808
 809         kfree(cmd);
 810
 811         return ret;
 812 }
 813
 814 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
 815 {
 816         return psp_ta_invoke(psp, ta_cmd_id, psp->xgmi_context.session_id);
 817 }
 818
 819 int psp_xgmi_terminate(struct psp_context *psp)
 820 {
 821         int ret;
 822
 823         if (!psp->xgmi_context.initialized)
 824                 return 0;
 825
 826         ret = psp_xgmi_unload(psp);
 827         if (ret)
 828                 return ret;
 829
 830         psp->xgmi_context.initialized = 0;
 831
 832         /* free xgmi shared memory */
 833         amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo,
 834                         &psp->xgmi_context.xgmi_shared_mc_addr,
 835                         &psp->xgmi_context.xgmi_shared_buf);
 836
 837         return 0;
 838 }
 839
 840 int psp_xgmi_initialize(struct psp_context *psp)
 841 {
 842         struct ta_xgmi_shared_memory *xgmi_cmd;
 843         int ret;
 844
 845         if (!psp->adev->psp.ta_fw ||
 846             !psp->adev->psp.ta_xgmi_ucode_size ||
 847             !psp->adev->psp.ta_xgmi_start_addr)
 848                 return -ENOENT;
 849
 850         if (!psp->xgmi_context.initialized) {
 851                 ret = psp_xgmi_init_shared_buf(psp);
 852                 if (ret)
 853                         return ret;
 854         }
 855
 856         /* Load XGMI TA */
 857         ret = psp_xgmi_load(psp);
 858         if (ret)
 859                 return ret;
 860
 861         /* Initialize XGMI session */
 862         xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf);
 863         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 864         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
 865
 866         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 867
 868         return ret;
 869 }
 870
 871 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
 872 {
 873         struct ta_xgmi_shared_memory *xgmi_cmd;
 874         int ret;
 875
 876         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf;
 877         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 878
 879         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
 880
 881         /* Invoke xgmi ta to get hive id */
 882         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 883         if (ret)
 884                 return ret;
 885
 886         *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
 887
 888         return 0;
 889 }
 890
 891 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
 892 {
 893         struct ta_xgmi_shared_memory *xgmi_cmd;
 894         int ret;
 895
 896         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf;
 897         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 898
 899         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
 900
 901         /* Invoke xgmi ta to get the node id */
 902         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 903         if (ret)
 904                 return ret;
 905
 906         *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
 907
 908         return 0;
 909 }
 910
 911 int psp_xgmi_get_topology_info(struct psp_context *psp,
 912                                int number_devices,
 913                                struct psp_xgmi_topology_info *topology)
 914 {
 915         struct ta_xgmi_shared_memory *xgmi_cmd;
 916         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
 917         struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
 918         int i;
 919         int ret;
 920
 921         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
 922                 return -EINVAL;
 923
 924         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf;
 925         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 926
 927         /* Fill in the shared memory with topology information as input */
 928         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
 929         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
 930         topology_info_input->num_nodes = number_devices;
 931
 932         for (i = 0; i < topology_info_input->num_nodes; i++) {
 933                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
 934                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
 935                 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
 936                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
 937         }
 938
 939         /* Invoke xgmi ta to get the topology information */
 940         ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
 941         if (ret)
 942                 return ret;
 943
 944         /* Read the output topology information from the shared memory */
 945         topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
 946         topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
 947         for (i = 0; i < topology->num_nodes; i++) {
 948                 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
 949                 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
 950                 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled;
 951                 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine;
 952         }
 953
 954         return 0;
 955 }
 956
 957 int psp_xgmi_set_topology_info(struct psp_context *psp,
 958                                int number_devices,
 959                                struct psp_xgmi_topology_info *topology)
 960 {
 961         struct ta_xgmi_shared_memory *xgmi_cmd;
 962         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
 963         int i;
 964
 965         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
 966                 return -EINVAL;
 967
 968         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf;
 969         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 970
 971         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
 972         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
 973         topology_info_input->num_nodes = number_devices;
 974
 975         for (i = 0; i < topology_info_input->num_nodes; i++) {
 976                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
 977                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
 978                 topology_info_input->nodes[i].is_sharing_enabled = 1;
 979                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
 980         }
 981
 982         /* Invoke xgmi ta to set topology information */
 983         return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
 984 }
 985
 986 // ras begin
 987 static int psp_ras_init_shared_buf(struct psp_context *psp)
 988 {
 989         int ret;
 990
 991         /*
 992          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 993          * physical) for ras ta <-> Driver
 994          */
 995         ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE,
 996                         PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 997                         &psp->ras.ras_shared_bo,
 998                         &psp->ras.ras_shared_mc_addr,
 999                         &psp->ras.ras_shared_buf);
1000
1001         return ret;
1002 }
1003
1004 static int psp_ras_load(struct psp_context *psp)
1005 {
1006         int ret;
1007         struct psp_gfx_cmd_resp *cmd;
1008         struct ta_ras_shared_memory *ras_cmd;
1009
1010         /*
1011          * TODO: bypass the loading in sriov for now
1012          */
1013         if (amdgpu_sriov_vf(psp->adev))
1014                 return 0;
1015
1016         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1017         if (!cmd)
1018                 return -ENOMEM;
1019
1020         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
1021         memcpy(psp->fw_pri_buf, psp->ta_ras_start_addr, psp->ta_ras_ucode_size);
1022
1023         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
1024
1025         if (psp->adev->gmc.xgmi.connected_to_cpu)
1026                 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1;
1027         else
1028                 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1;
1029
1030         psp_prep_ta_load_cmd_buf(cmd,
1031                                  psp->fw_pri_mc_addr,
1032                                  psp->ta_ras_ucode_size,
1033                                  psp->ras.ras_shared_mc_addr,
1034                                  PSP_RAS_SHARED_MEM_SIZE);
1035
1036         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1037                         psp->fence_buf_mc_addr);
1038
1039         if (!ret) {
1040                 psp->ras.session_id = cmd->resp.session_id;
1041
1042                 if (!ras_cmd->ras_status)
1043                         psp->ras.ras_initialized = true;
1044                 else
1045                         dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status);
1046         }
1047
1048         if (ret || ras_cmd->ras_status)
1049                 amdgpu_ras_fini(psp->adev);
1050
1051         kfree(cmd);
1052
1053         return ret;
1054 }
1055
1056 static int psp_ras_unload(struct psp_context *psp)
1057 {
1058         int ret;
1059         struct psp_gfx_cmd_resp *cmd;
1060
1061         /*
1062          * TODO: bypass the unloading in sriov for now
1063          */
1064         if (amdgpu_sriov_vf(psp->adev))
1065                 return 0;
1066
1067         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1068         if (!cmd)
1069                 return -ENOMEM;
1070
1071         psp_prep_ta_unload_cmd_buf(cmd, psp->ras.session_id);
1072
1073         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1074                         psp->fence_buf_mc_addr);
1075
1076         kfree(cmd);
1077
1078         return ret;
1079 }
1080
1081 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1082 {
1083         struct ta_ras_shared_memory *ras_cmd;
1084         int ret;
1085
1086         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
1087
1088         /*
1089          * TODO: bypass the loading in sriov for now
1090          */
1091         if (amdgpu_sriov_vf(psp->adev))
1092                 return 0;
1093
1094         ret = psp_ta_invoke(psp, ta_cmd_id, psp->ras.session_id);
1095
1096         if (amdgpu_ras_intr_triggered())
1097                 return ret;
1098
1099         if (ras_cmd->if_version > RAS_TA_HOST_IF_VER)
1100         {
1101                 DRM_WARN("RAS: Unsupported Interface");
1102                 return -EINVAL;
1103         }
1104
1105         if (!ret) {
1106                 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) {
1107                         dev_warn(psp->adev->dev, "ECC switch disabled\n");
1108
1109                         ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE;
1110                 }
1111                 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag)
1112                         dev_warn(psp->adev->dev,
1113                                  "RAS internal register access blocked\n");
1114         }
1115
1116         return ret;
1117 }
1118
1119 static int psp_ras_status_to_errno(struct amdgpu_device *adev,
1120                                          enum ta_ras_status ras_status)
1121 {
1122         int ret = -EINVAL;
1123
1124         switch (ras_status) {
1125         case TA_RAS_STATUS__SUCCESS:
1126                 ret = 0;
1127                 break;
1128         case TA_RAS_STATUS__RESET_NEEDED:
1129                 ret = -EAGAIN;
1130                 break;
1131         case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE:
1132                 dev_warn(adev->dev, "RAS WARN: ras function unavailable\n");
1133                 break;
1134         case TA_RAS_STATUS__ERROR_ASD_READ_WRITE:
1135                 dev_warn(adev->dev, "RAS WARN: asd read or write failed\n");
1136                 break;
1137         default:
1138                 dev_err(adev->dev, "RAS ERROR: ras function failed ret 0x%X\n", ret);
1139         }
1140
1141         return ret;
1142 }
1143
1144 int psp_ras_enable_features(struct psp_context *psp,
1145                 union ta_ras_cmd_input *info, bool enable)
1146 {
1147         struct ta_ras_shared_memory *ras_cmd;
1148         int ret;
1149
1150         if (!psp->ras.ras_initialized)
1151                 return -EINVAL;
1152
1153         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
1154         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1155
1156         if (enable)
1157                 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
1158         else
1159                 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
1160
1161         ras_cmd->ras_in_message = *info;
1162
1163         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1164         if (ret)
1165                 return -EINVAL;
1166
1167         return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status);
1168 }
1169
1170 static int psp_ras_terminate(struct psp_context *psp)
1171 {
1172         int ret;
1173
1174         /*
1175          * TODO: bypass the terminate in sriov for now
1176          */
1177         if (amdgpu_sriov_vf(psp->adev))
1178                 return 0;
1179
1180         if (!psp->ras.ras_initialized)
1181                 return 0;
1182
1183         ret = psp_ras_unload(psp);
1184         if (ret)
1185                 return ret;
1186
1187         psp->ras.ras_initialized = false;
1188
1189         /* free ras shared memory */
1190         amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo,
1191                         &psp->ras.ras_shared_mc_addr,
1192                         &psp->ras.ras_shared_buf);
1193
1194         return 0;
1195 }
1196
1197 static int psp_ras_initialize(struct psp_context *psp)
1198 {
1199         int ret;
1200
1201         /*
1202          * TODO: bypass the initialize in sriov for now
1203          */
1204         if (amdgpu_sriov_vf(psp->adev))
1205                 return 0;
1206
1207         if (!psp->adev->psp.ta_ras_ucode_size ||
1208             !psp->adev->psp.ta_ras_start_addr) {
1209                 dev_info(psp->adev->dev, "RAS: optional ras ta ucode is not available\n");
1210                 return 0;
1211         }
1212
1213         if (!psp->ras.ras_initialized) {
1214                 ret = psp_ras_init_shared_buf(psp);
1215                 if (ret)
1216                         return ret;
1217         }
1218
1219         ret = psp_ras_load(psp);
1220         if (ret)
1221                 return ret;
1222
1223         return 0;
1224 }
1225
1226 int psp_ras_trigger_error(struct psp_context *psp,
1227                           struct ta_ras_trigger_error_input *info)
1228 {
1229         struct ta_ras_shared_memory *ras_cmd;
1230         int ret;
1231
1232         if (!psp->ras.ras_initialized)
1233                 return -EINVAL;
1234
1235         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
1236         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1237
1238         ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
1239         ras_cmd->ras_in_message.trigger_error = *info;
1240
1241         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1242         if (ret)
1243                 return -EINVAL;
1244
1245         /* If err_event_athub occurs error inject was successful, however
1246            return status from TA is no long reliable */
1247         if (amdgpu_ras_intr_triggered())
1248                 return 0;
1249
1250         return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status);
1251 }
1252 // ras end
1253
1254 // HDCP start
1255 static int psp_hdcp_init_shared_buf(struct psp_context *psp)
1256 {
1257         int ret;
1258
1259         /*
1260          * Allocate 16k memory aligned to 4k from Frame Buffer (local
1261          * physical) for hdcp ta <-> Driver
1262          */
1263         ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE,
1264                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1265                                       &psp->hdcp_context.hdcp_shared_bo,
1266                                       &psp->hdcp_context.hdcp_shared_mc_addr,
1267                                       &psp->hdcp_context.hdcp_shared_buf);
1268
1269         return ret;
1270 }
1271
1272 static int psp_hdcp_load(struct psp_context *psp)
1273 {
1274         int ret;
1275         struct psp_gfx_cmd_resp *cmd;
1276
1277         /*
1278          * TODO: bypass the loading in sriov for now
1279          */
1280         if (amdgpu_sriov_vf(psp->adev))
1281                 return 0;
1282
1283         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1284         if (!cmd)
1285                 return -ENOMEM;
1286
1287         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
1288         memcpy(psp->fw_pri_buf, psp->ta_hdcp_start_addr,
1289                psp->ta_hdcp_ucode_size);
1290
1291         psp_prep_ta_load_cmd_buf(cmd,
1292                                  psp->fw_pri_mc_addr,
1293                                  psp->ta_hdcp_ucode_size,
1294                                  psp->hdcp_context.hdcp_shared_mc_addr,
1295                                  PSP_HDCP_SHARED_MEM_SIZE);
1296
1297         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1298
1299         if (!ret) {
1300                 psp->hdcp_context.hdcp_initialized = true;
1301                 psp->hdcp_context.session_id = cmd->resp.session_id;
1302                 mutex_init(&psp->hdcp_context.mutex);
1303         }
1304
1305         kfree(cmd);
1306
1307         return ret;
1308 }
1309 static int psp_hdcp_initialize(struct psp_context *psp)
1310 {
1311         int ret;
1312
1313         /*
1314          * TODO: bypass the initialize in sriov for now
1315          */
1316         if (amdgpu_sriov_vf(psp->adev))
1317                 return 0;
1318
1319         if (!psp->adev->psp.ta_hdcp_ucode_size ||
1320             !psp->adev->psp.ta_hdcp_start_addr) {
1321                 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");
1322                 return 0;
1323         }
1324
1325         if (!psp->hdcp_context.hdcp_initialized) {
1326                 ret = psp_hdcp_init_shared_buf(psp);
1327                 if (ret)
1328                         return ret;
1329         }
1330
1331         ret = psp_hdcp_load(psp);
1332         if (ret)
1333                 return ret;
1334
1335         return 0;
1336 }
1337
1338 static int psp_hdcp_unload(struct psp_context *psp)
1339 {
1340         int ret;
1341         struct psp_gfx_cmd_resp *cmd;
1342
1343         /*
1344          * TODO: bypass the unloading in sriov for now
1345          */
1346         if (amdgpu_sriov_vf(psp->adev))
1347                 return 0;
1348
1349         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1350         if (!cmd)
1351                 return -ENOMEM;
1352
1353         psp_prep_ta_unload_cmd_buf(cmd, psp->hdcp_context.session_id);
1354
1355         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1356
1357         kfree(cmd);
1358
1359         return ret;
1360 }
1361
1362 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1363 {
1364         /*
1365          * TODO: bypass the loading in sriov for now
1366          */
1367         if (amdgpu_sriov_vf(psp->adev))
1368                 return 0;
1369
1370         return psp_ta_invoke(psp, ta_cmd_id, psp->hdcp_context.session_id);
1371 }
1372
1373 static int psp_hdcp_terminate(struct psp_context *psp)
1374 {
1375         int ret;
1376
1377         /*
1378          * TODO: bypass the terminate in sriov for now
1379          */
1380         if (amdgpu_sriov_vf(psp->adev))
1381                 return 0;
1382
1383         if (!psp->hdcp_context.hdcp_initialized) {
1384                 if (psp->hdcp_context.hdcp_shared_buf)
1385                         goto out;
1386                 else
1387                         return 0;
1388         }
1389
1390         ret = psp_hdcp_unload(psp);
1391         if (ret)
1392                 return ret;
1393
1394         psp->hdcp_context.hdcp_initialized = false;
1395
1396 out:
1397         /* free hdcp shared memory */
1398         amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo,
1399                               &psp->hdcp_context.hdcp_shared_mc_addr,
1400                               &psp->hdcp_context.hdcp_shared_buf);
1401
1402         return 0;
1403 }
1404 // HDCP end
1405
1406 // DTM start
1407 static int psp_dtm_init_shared_buf(struct psp_context *psp)
1408 {
1409         int ret;
1410
1411         /*
1412          * Allocate 16k memory aligned to 4k from Frame Buffer (local
1413          * physical) for dtm ta <-> Driver
1414          */
1415         ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE,
1416                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1417                                       &psp->dtm_context.dtm_shared_bo,
1418                                       &psp->dtm_context.dtm_shared_mc_addr,
1419                                       &psp->dtm_context.dtm_shared_buf);
1420
1421         return ret;
1422 }
1423
1424 static int psp_dtm_load(struct psp_context *psp)
1425 {
1426         int ret;
1427         struct psp_gfx_cmd_resp *cmd;
1428
1429         /*
1430          * TODO: bypass the loading in sriov for now
1431          */
1432         if (amdgpu_sriov_vf(psp->adev))
1433                 return 0;
1434
1435         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1436         if (!cmd)
1437                 return -ENOMEM;
1438
1439         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
1440         memcpy(psp->fw_pri_buf, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size);
1441
1442         psp_prep_ta_load_cmd_buf(cmd,
1443                                  psp->fw_pri_mc_addr,
1444                                  psp->ta_dtm_ucode_size,
1445                                  psp->dtm_context.dtm_shared_mc_addr,
1446                                  PSP_DTM_SHARED_MEM_SIZE);
1447
1448         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1449
1450         if (!ret) {
1451                 psp->dtm_context.dtm_initialized = true;
1452                 psp->dtm_context.session_id = cmd->resp.session_id;
1453                 mutex_init(&psp->dtm_context.mutex);
1454         }
1455
1456         kfree(cmd);
1457
1458         return ret;
1459 }
1460
1461 static int psp_dtm_initialize(struct psp_context *psp)
1462 {
1463         int ret;
1464
1465         /*
1466          * TODO: bypass the initialize in sriov for now
1467          */
1468         if (amdgpu_sriov_vf(psp->adev))
1469                 return 0;
1470
1471         if (!psp->adev->psp.ta_dtm_ucode_size ||
1472             !psp->adev->psp.ta_dtm_start_addr) {
1473                 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");
1474                 return 0;
1475         }
1476
1477         if (!psp->dtm_context.dtm_initialized) {
1478                 ret = psp_dtm_init_shared_buf(psp);
1479                 if (ret)
1480                         return ret;
1481         }
1482
1483         ret = psp_dtm_load(psp);
1484         if (ret)
1485                 return ret;
1486
1487         return 0;
1488 }
1489
1490 static int psp_dtm_unload(struct psp_context *psp)
1491 {
1492         int ret;
1493         struct psp_gfx_cmd_resp *cmd;
1494
1495         /*
1496          * TODO: bypass the unloading in sriov for now
1497          */
1498         if (amdgpu_sriov_vf(psp->adev))
1499                 return 0;
1500
1501         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1502         if (!cmd)
1503                 return -ENOMEM;
1504
1505         psp_prep_ta_unload_cmd_buf(cmd, psp->dtm_context.session_id);
1506
1507         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1508
1509         kfree(cmd);
1510
1511         return ret;
1512 }
1513
1514 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1515 {
1516         /*
1517          * TODO: bypass the loading in sriov for now
1518          */
1519         if (amdgpu_sriov_vf(psp->adev))
1520                 return 0;
1521
1522         return psp_ta_invoke(psp, ta_cmd_id, psp->dtm_context.session_id);
1523 }
1524
1525 static int psp_dtm_terminate(struct psp_context *psp)
1526 {
1527         int ret;
1528
1529         /*
1530          * TODO: bypass the terminate in sriov for now
1531          */
1532         if (amdgpu_sriov_vf(psp->adev))
1533                 return 0;
1534
1535         if (!psp->dtm_context.dtm_initialized) {
1536                 if (psp->dtm_context.dtm_shared_buf)
1537                         goto out;
1538                 else
1539                         return 0;
1540         }
1541
1542         ret = psp_dtm_unload(psp);
1543         if (ret)
1544                 return ret;
1545
1546         psp->dtm_context.dtm_initialized = false;
1547
1548 out:
1549         /* free hdcp shared memory */
1550         amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo,
1551                               &psp->dtm_context.dtm_shared_mc_addr,
1552                               &psp->dtm_context.dtm_shared_buf);
1553
1554         return 0;
1555 }
1556 // DTM end
1557
1558 // RAP start
1559 static int psp_rap_init_shared_buf(struct psp_context *psp)
1560 {
1561         int ret;
1562
1563         /*
1564          * Allocate 16k memory aligned to 4k from Frame Buffer (local
1565          * physical) for rap ta <-> Driver
1566          */
1567         ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAP_SHARED_MEM_SIZE,
1568                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1569                                       &psp->rap_context.rap_shared_bo,
1570                                       &psp->rap_context.rap_shared_mc_addr,
1571                                       &psp->rap_context.rap_shared_buf);
1572
1573         return ret;
1574 }
1575
1576 static int psp_rap_load(struct psp_context *psp)
1577 {
1578         int ret;
1579         struct psp_gfx_cmd_resp *cmd;
1580
1581         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1582         if (!cmd)
1583                 return -ENOMEM;
1584
1585         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
1586         memcpy(psp->fw_pri_buf, psp->ta_rap_start_addr, psp->ta_rap_ucode_size);
1587
1588         psp_prep_ta_load_cmd_buf(cmd,
1589                                  psp->fw_pri_mc_addr,
1590                                  psp->ta_rap_ucode_size,
1591                                  psp->rap_context.rap_shared_mc_addr,
1592                                  PSP_RAP_SHARED_MEM_SIZE);
1593
1594         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1595
1596         if (!ret) {
1597                 psp->rap_context.rap_initialized = true;
1598                 psp->rap_context.session_id = cmd->resp.session_id;
1599                 mutex_init(&psp->rap_context.mutex);
1600         }
1601
1602         kfree(cmd);
1603
1604         return ret;
1605 }
1606
1607 static int psp_rap_unload(struct psp_context *psp)
1608 {
1609         int ret;
1610         struct psp_gfx_cmd_resp *cmd;
1611
1612         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1613         if (!cmd)
1614                 return -ENOMEM;
1615
1616         psp_prep_ta_unload_cmd_buf(cmd, psp->rap_context.session_id);
1617
1618         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1619
1620         kfree(cmd);
1621
1622         return ret;
1623 }
1624
1625 static int psp_rap_initialize(struct psp_context *psp)
1626 {
1627         int ret;
1628         enum ta_rap_status status = TA_RAP_STATUS__SUCCESS;
1629
1630         /*
1631          * TODO: bypass the initialize in sriov for now
1632          */
1633         if (amdgpu_sriov_vf(psp->adev))
1634                 return 0;
1635
1636         if (!psp->adev->psp.ta_rap_ucode_size ||
1637             !psp->adev->psp.ta_rap_start_addr) {
1638                 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n");
1639                 return 0;
1640         }
1641
1642         if (!psp->rap_context.rap_initialized) {
1643                 ret = psp_rap_init_shared_buf(psp);
1644                 if (ret)
1645                         return ret;
1646         }
1647
1648         ret = psp_rap_load(psp);
1649         if (ret)
1650                 return ret;
1651
1652         ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status);
1653         if (ret || status != TA_RAP_STATUS__SUCCESS) {
1654                 psp_rap_unload(psp);
1655
1656                 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo,
1657                               &psp->rap_context.rap_shared_mc_addr,
1658                               &psp->rap_context.rap_shared_buf);
1659
1660                 psp->rap_context.rap_initialized = false;
1661
1662                 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n",
1663                          ret, status);
1664
1665                 return ret;
1666         }
1667
1668         return 0;
1669 }
1670
1671 static int psp_rap_terminate(struct psp_context *psp)
1672 {
1673         int ret;
1674
1675         if (!psp->rap_context.rap_initialized)
1676                 return 0;
1677
1678         ret = psp_rap_unload(psp);
1679
1680         psp->rap_context.rap_initialized = false;
1681
1682         /* free rap shared memory */
1683         amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo,
1684                               &psp->rap_context.rap_shared_mc_addr,
1685                               &psp->rap_context.rap_shared_buf);
1686
1687         return ret;
1688 }
1689
1690 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status)
1691 {
1692         struct ta_rap_shared_memory *rap_cmd;
1693         int ret = 0;
1694
1695         if (!psp->rap_context.rap_initialized)
1696                 return 0;
1697
1698         if (ta_cmd_id != TA_CMD_RAP__INITIALIZE &&
1699             ta_cmd_id != TA_CMD_RAP__VALIDATE_L0)
1700                 return -EINVAL;
1701
1702         mutex_lock(&psp->rap_context.mutex);
1703
1704         rap_cmd = (struct ta_rap_shared_memory *)
1705                   psp->rap_context.rap_shared_buf;
1706         memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory));
1707
1708         rap_cmd->cmd_id = ta_cmd_id;
1709         rap_cmd->validation_method_id = METHOD_A;
1710
1711         ret = psp_ta_invoke(psp, rap_cmd->cmd_id, psp->rap_context.session_id);
1712         if (ret)
1713                 goto out_unlock;
1714
1715         if (status)
1716                 *status = rap_cmd->rap_status;
1717
1718 out_unlock:
1719         mutex_unlock(&psp->rap_context.mutex);
1720
1721         return ret;
1722 }
1723 // RAP end
1724
1725 /* securedisplay start */
1726 static int psp_securedisplay_init_shared_buf(struct psp_context *psp)
1727 {
1728         int ret;
1729
1730         /*
1731          * Allocate 16k memory aligned to 4k from Frame Buffer (local
1732          * physical) for sa ta <-> Driver
1733          */
1734         ret = amdgpu_bo_create_kernel(psp->adev, PSP_SECUREDISPLAY_SHARED_MEM_SIZE,
1735                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1736                                       &psp->securedisplay_context.securedisplay_shared_bo,
1737                                       &psp->securedisplay_context.securedisplay_shared_mc_addr,
1738                                       &psp->securedisplay_context.securedisplay_shared_buf);
1739
1740         return ret;
1741 }
1742
1743 static int psp_securedisplay_load(struct psp_context *psp)
1744 {
1745         int ret;
1746         struct psp_gfx_cmd_resp *cmd;
1747
1748         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1749         if (!cmd)
1750                 return -ENOMEM;
1751
1752         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
1753         memcpy(psp->fw_pri_buf, psp->ta_securedisplay_start_addr, psp->ta_securedisplay_ucode_size);
1754
1755         psp_prep_ta_load_cmd_buf(cmd,
1756                                  psp->fw_pri_mc_addr,
1757                                  psp->ta_securedisplay_ucode_size,
1758                                  psp->securedisplay_context.securedisplay_shared_mc_addr,
1759                                  PSP_SECUREDISPLAY_SHARED_MEM_SIZE);
1760
1761         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1762
1763         if (ret)
1764                 goto failed;
1765
1766         psp->securedisplay_context.securedisplay_initialized = true;
1767         psp->securedisplay_context.session_id = cmd->resp.session_id;
1768         mutex_init(&psp->securedisplay_context.mutex);
1769
1770 failed:
1771         kfree(cmd);
1772         return ret;
1773 }
1774
1775 static int psp_securedisplay_unload(struct psp_context *psp)
1776 {
1777         int ret;
1778         struct psp_gfx_cmd_resp *cmd;
1779
1780         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1781         if (!cmd)
1782                 return -ENOMEM;
1783
1784         psp_prep_ta_unload_cmd_buf(cmd, psp->securedisplay_context.session_id);
1785
1786         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1787
1788         kfree(cmd);
1789
1790         return ret;
1791 }
1792
1793 static int psp_securedisplay_initialize(struct psp_context *psp)
1794 {
1795         int ret;
1796         struct securedisplay_cmd *securedisplay_cmd;
1797
1798         /*
1799          * TODO: bypass the initialize in sriov for now
1800          */
1801         if (amdgpu_sriov_vf(psp->adev))
1802                 return 0;
1803
1804         if (!psp->adev->psp.ta_securedisplay_ucode_size ||
1805             !psp->adev->psp.ta_securedisplay_start_addr) {
1806                 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n");
1807                 return 0;
1808         }
1809
1810         if (!psp->securedisplay_context.securedisplay_initialized) {
1811                 ret = psp_securedisplay_init_shared_buf(psp);
1812                 if (ret)
1813                         return ret;
1814         }
1815
1816         ret = psp_securedisplay_load(psp);
1817         if (ret)
1818                 return ret;
1819
1820         psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
1821                         TA_SECUREDISPLAY_COMMAND__QUERY_TA);
1822
1823         ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA);
1824         if (ret) {
1825                 psp_securedisplay_unload(psp);
1826
1827                 amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo,
1828                               &psp->securedisplay_context.securedisplay_shared_mc_addr,
1829                               &psp->securedisplay_context.securedisplay_shared_buf);
1830
1831                 psp->securedisplay_context.securedisplay_initialized = false;
1832
1833                 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n");
1834                 return -EINVAL;
1835         }
1836
1837         if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) {
1838                 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
1839                 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n",
1840                         securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret);
1841         }
1842
1843         return 0;
1844 }
1845
1846 static int psp_securedisplay_terminate(struct psp_context *psp)
1847 {
1848         int ret;
1849
1850         /*
1851          * TODO:bypass the terminate in sriov for now
1852          */
1853         if (amdgpu_sriov_vf(psp->adev))
1854                 return 0;
1855
1856         if (!psp->securedisplay_context.securedisplay_initialized)
1857                 return 0;
1858
1859         ret = psp_securedisplay_unload(psp);
1860         if (ret)
1861                 return ret;
1862
1863         psp->securedisplay_context.securedisplay_initialized = false;
1864
1865         /* free securedisplay shared memory */
1866         amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo,
1867                               &psp->securedisplay_context.securedisplay_shared_mc_addr,
1868                               &psp->securedisplay_context.securedisplay_shared_buf);
1869
1870         return ret;
1871 }
1872
1873 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1874 {
1875         int ret;
1876
1877         if (!psp->securedisplay_context.securedisplay_initialized)
1878                 return -EINVAL;
1879
1880         if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA &&
1881             ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC)
1882                 return -EINVAL;
1883
1884         mutex_lock(&psp->securedisplay_context.mutex);
1885
1886         ret = psp_ta_invoke(psp, ta_cmd_id, psp->securedisplay_context.session_id);
1887
1888         mutex_unlock(&psp->securedisplay_context.mutex);
1889
1890         return ret;
1891 }
1892 /* SECUREDISPLAY end */
1893
1894 static int psp_hw_start(struct psp_context *psp)
1895 {
1896         struct amdgpu_device *adev = psp->adev;
1897         int ret;
1898
1899         if (!amdgpu_sriov_vf(adev)) {
1900                 if (psp->kdb_bin_size &&
1901                     (psp->funcs->bootloader_load_kdb != NULL)) {
1902                         ret = psp_bootloader_load_kdb(psp);
1903                         if (ret) {
1904                                 DRM_ERROR("PSP load kdb failed!\n");
1905                                 return ret;
1906                         }
1907                 }
1908
1909                 if (psp->spl_bin_size) {
1910                         ret = psp_bootloader_load_spl(psp);
1911                         if (ret) {
1912                                 DRM_ERROR("PSP load spl failed!\n");
1913                                 return ret;
1914                         }
1915                 }
1916
1917                 ret = psp_bootloader_load_sysdrv(psp);
1918                 if (ret) {
1919                         DRM_ERROR("PSP load sysdrv failed!\n");
1920                         return ret;
1921                 }
1922
1923                 ret = psp_bootloader_load_sos(psp);
1924                 if (ret) {
1925                         DRM_ERROR("PSP load sos failed!\n");
1926                         return ret;
1927                 }
1928         }
1929
1930         ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
1931         if (ret) {
1932                 DRM_ERROR("PSP create ring failed!\n");
1933                 return ret;
1934         }
1935
1936         if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) {
1937                 ret = psp_boot_config_set(adev);
1938                 if (ret)
1939                         dev_warn(adev->dev, "PSP set boot config failed\n");
1940         }
1941
1942         ret = psp_tmr_init(psp);
1943         if (ret) {
1944                 DRM_ERROR("PSP tmr init failed!\n");
1945                 return ret;
1946         }
1947
1948         /*
1949          * For ASICs with DF Cstate management centralized
1950          * to PMFW, TMR setup should be performed after PMFW
1951          * loaded and before other non-psp firmware loaded.
1952          */
1953         if (psp->pmfw_centralized_cstate_management) {
1954                 ret = psp_load_smu_fw(psp);
1955                 if (ret)
1956                         return ret;
1957         }
1958
1959         ret = psp_tmr_load(psp);
1960         if (ret) {
1961                 DRM_ERROR("PSP load tmr failed!\n");
1962                 return ret;
1963         }
1964
1965         return 0;
1966 }
1967
1968 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
1969                            enum psp_gfx_fw_type *type)
1970 {
1971         switch (ucode->ucode_id) {
1972         case AMDGPU_UCODE_ID_SDMA0:
1973                 *type = GFX_FW_TYPE_SDMA0;
1974                 break;
1975         case AMDGPU_UCODE_ID_SDMA1:
1976                 *type = GFX_FW_TYPE_SDMA1;
1977                 break;
1978         case AMDGPU_UCODE_ID_SDMA2:
1979                 *type = GFX_FW_TYPE_SDMA2;
1980                 break;
1981         case AMDGPU_UCODE_ID_SDMA3:
1982                 *type = GFX_FW_TYPE_SDMA3;
1983                 break;
1984         case AMDGPU_UCODE_ID_SDMA4:
1985                 *type = GFX_FW_TYPE_SDMA4;
1986                 break;
1987         case AMDGPU_UCODE_ID_SDMA5:
1988                 *type = GFX_FW_TYPE_SDMA5;
1989                 break;
1990         case AMDGPU_UCODE_ID_SDMA6:
1991                 *type = GFX_FW_TYPE_SDMA6;
1992                 break;
1993         case AMDGPU_UCODE_ID_SDMA7:
1994                 *type = GFX_FW_TYPE_SDMA7;
1995                 break;
1996         case AMDGPU_UCODE_ID_CP_MES:
1997                 *type = GFX_FW_TYPE_CP_MES;
1998                 break;
1999         case AMDGPU_UCODE_ID_CP_MES_DATA:
2000                 *type = GFX_FW_TYPE_MES_STACK;
2001                 break;
2002         case AMDGPU_UCODE_ID_CP_CE:
2003                 *type = GFX_FW_TYPE_CP_CE;
2004                 break;
2005         case AMDGPU_UCODE_ID_CP_PFP:
2006                 *type = GFX_FW_TYPE_CP_PFP;
2007                 break;
2008         case AMDGPU_UCODE_ID_CP_ME:
2009                 *type = GFX_FW_TYPE_CP_ME;
2010                 break;
2011         case AMDGPU_UCODE_ID_CP_MEC1:
2012                 *type = GFX_FW_TYPE_CP_MEC;
2013                 break;
2014         case AMDGPU_UCODE_ID_CP_MEC1_JT:
2015                 *type = GFX_FW_TYPE_CP_MEC_ME1;
2016                 break;
2017         case AMDGPU_UCODE_ID_CP_MEC2:
2018                 *type = GFX_FW_TYPE_CP_MEC;
2019                 break;
2020         case AMDGPU_UCODE_ID_CP_MEC2_JT:
2021                 *type = GFX_FW_TYPE_CP_MEC_ME2;
2022                 break;
2023         case AMDGPU_UCODE_ID_RLC_G:
2024                 *type = GFX_FW_TYPE_RLC_G;
2025                 break;
2026         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
2027                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
2028                 break;
2029         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
2030                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
2031                 break;
2032         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
2033                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
2034                 break;
2035         case AMDGPU_UCODE_ID_RLC_IRAM:
2036                 *type = GFX_FW_TYPE_RLC_IRAM;
2037                 break;
2038         case AMDGPU_UCODE_ID_RLC_DRAM:
2039                 *type = GFX_FW_TYPE_RLC_DRAM_BOOT;
2040                 break;
2041         case AMDGPU_UCODE_ID_SMC:
2042                 *type = GFX_FW_TYPE_SMU;
2043                 break;
2044         case AMDGPU_UCODE_ID_UVD:
2045                 *type = GFX_FW_TYPE_UVD;
2046                 break;
2047         case AMDGPU_UCODE_ID_UVD1:
2048                 *type = GFX_FW_TYPE_UVD1;
2049                 break;
2050         case AMDGPU_UCODE_ID_VCE:
2051                 *type = GFX_FW_TYPE_VCE;
2052                 break;
2053         case AMDGPU_UCODE_ID_VCN:
2054                 *type = GFX_FW_TYPE_VCN;
2055                 break;
2056         case AMDGPU_UCODE_ID_VCN1:
2057                 *type = GFX_FW_TYPE_VCN1;
2058                 break;
2059         case AMDGPU_UCODE_ID_DMCU_ERAM:
2060                 *type = GFX_FW_TYPE_DMCU_ERAM;
2061                 break;
2062         case AMDGPU_UCODE_ID_DMCU_INTV:
2063                 *type = GFX_FW_TYPE_DMCU_ISR;
2064                 break;
2065         case AMDGPU_UCODE_ID_VCN0_RAM:
2066                 *type = GFX_FW_TYPE_VCN0_RAM;
2067                 break;
2068         case AMDGPU_UCODE_ID_VCN1_RAM:
2069                 *type = GFX_FW_TYPE_VCN1_RAM;
2070                 break;
2071         case AMDGPU_UCODE_ID_DMCUB:
2072                 *type = GFX_FW_TYPE_DMUB;
2073                 break;
2074         case AMDGPU_UCODE_ID_MAXIMUM:
2075         default:
2076                 return -EINVAL;
2077         }
2078
2079         return 0;
2080 }
2081
2082 static void psp_print_fw_hdr(struct psp_context *psp,
2083                              struct amdgpu_firmware_info *ucode)
2084 {
2085         struct amdgpu_device *adev = psp->adev;
2086         struct common_firmware_header *hdr;
2087
2088         switch (ucode->ucode_id) {
2089         case AMDGPU_UCODE_ID_SDMA0:
2090         case AMDGPU_UCODE_ID_SDMA1:
2091         case AMDGPU_UCODE_ID_SDMA2:
2092         case AMDGPU_UCODE_ID_SDMA3:
2093         case AMDGPU_UCODE_ID_SDMA4:
2094         case AMDGPU_UCODE_ID_SDMA5:
2095         case AMDGPU_UCODE_ID_SDMA6:
2096         case AMDGPU_UCODE_ID_SDMA7:
2097                 hdr = (struct common_firmware_header *)
2098                         adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
2099                 amdgpu_ucode_print_sdma_hdr(hdr);
2100                 break;
2101         case AMDGPU_UCODE_ID_CP_CE:
2102                 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
2103                 amdgpu_ucode_print_gfx_hdr(hdr);
2104                 break;
2105         case AMDGPU_UCODE_ID_CP_PFP:
2106                 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
2107                 amdgpu_ucode_print_gfx_hdr(hdr);
2108                 break;
2109         case AMDGPU_UCODE_ID_CP_ME:
2110                 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
2111                 amdgpu_ucode_print_gfx_hdr(hdr);
2112                 break;
2113         case AMDGPU_UCODE_ID_CP_MEC1:
2114                 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
2115                 amdgpu_ucode_print_gfx_hdr(hdr);
2116                 break;
2117         case AMDGPU_UCODE_ID_RLC_G:
2118                 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
2119                 amdgpu_ucode_print_rlc_hdr(hdr);
2120                 break;
2121         case AMDGPU_UCODE_ID_SMC:
2122                 hdr = (struct common_firmware_header *)adev->pm.fw->data;
2123                 amdgpu_ucode_print_smc_hdr(hdr);
2124                 break;
2125         default:
2126                 break;
2127         }
2128 }
2129
2130 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
2131                                        struct psp_gfx_cmd_resp *cmd)
2132 {
2133         int ret;
2134         uint64_t fw_mem_mc_addr = ucode->mc_addr;
2135
2136         memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
2137
2138         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
2139         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
2140         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
2141         cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
2142
2143         ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
2144         if (ret)
2145                 DRM_ERROR("Unknown firmware type\n");
2146
2147         return ret;
2148 }
2149
2150 static int psp_execute_np_fw_load(struct psp_context *psp,
2151                                   struct amdgpu_firmware_info *ucode)
2152 {
2153         int ret = 0;
2154
2155         ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd);
2156         if (ret)
2157                 return ret;
2158
2159         ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
2160                                  psp->fence_buf_mc_addr);
2161
2162         return ret;
2163 }
2164
2165 static int psp_load_smu_fw(struct psp_context *psp)
2166 {
2167         int ret;
2168         struct amdgpu_device *adev = psp->adev;
2169         struct amdgpu_firmware_info *ucode =
2170                         &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
2171         struct amdgpu_ras *ras = psp->ras.ras;
2172
2173         if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
2174                 return 0;
2175
2176         if ((amdgpu_in_reset(adev) &&
2177              ras && adev->ras_enabled &&
2178              (adev->asic_type == CHIP_ARCTURUS ||
2179               adev->asic_type == CHIP_VEGA20)) ||
2180              (adev->in_runpm &&
2181               adev->asic_type >= CHIP_NAVI10 &&
2182               adev->asic_type <= CHIP_NAVI12)) {
2183                 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
2184                 if (ret) {
2185                         DRM_WARN("Failed to set MP1 state prepare for reload\n");
2186                 }
2187         }
2188
2189         ret = psp_execute_np_fw_load(psp, ucode);
2190
2191         if (ret)
2192                 DRM_ERROR("PSP load smu failed!\n");
2193
2194         return ret;
2195 }
2196
2197 static bool fw_load_skip_check(struct psp_context *psp,
2198                                struct amdgpu_firmware_info *ucode)
2199 {
2200         if (!ucode->fw)
2201                 return true;
2202
2203         if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2204             (psp_smu_reload_quirk(psp) ||
2205              psp->autoload_supported ||
2206              psp->pmfw_centralized_cstate_management))
2207                 return true;
2208
2209         if (amdgpu_sriov_vf(psp->adev) &&
2210            (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
2211             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
2212             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2
2213             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3
2214             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4
2215             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5
2216             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6
2217             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7
2218             || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G
2219             || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
2220             || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
2221             || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
2222             || ucode->ucode_id == AMDGPU_UCODE_ID_SMC))
2223                 /*skip ucode loading in SRIOV VF */
2224                 return true;
2225
2226         if (psp->autoload_supported &&
2227             (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
2228              ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
2229                 /* skip mec JT when autoload is enabled */
2230                 return true;
2231
2232         return false;
2233 }
2234
2235 int psp_load_fw_list(struct psp_context *psp,
2236                      struct amdgpu_firmware_info **ucode_list, int ucode_count)
2237 {
2238         int ret = 0, i;
2239         struct amdgpu_firmware_info *ucode;
2240
2241         for (i = 0; i < ucode_count; ++i) {
2242                 ucode = ucode_list[i];
2243                 psp_print_fw_hdr(psp, ucode);
2244                 ret = psp_execute_np_fw_load(psp, ucode);
2245                 if (ret)
2246                         return ret;
2247         }
2248         return ret;
2249 }
2250
2251 static int psp_np_fw_load(struct psp_context *psp)
2252 {
2253         int i, ret;
2254         struct amdgpu_firmware_info *ucode;
2255         struct amdgpu_device *adev = psp->adev;
2256
2257         if (psp->autoload_supported &&
2258             !psp->pmfw_centralized_cstate_management) {
2259                 ret = psp_load_smu_fw(psp);
2260                 if (ret)
2261                         return ret;
2262         }
2263
2264         for (i = 0; i < adev->firmware.max_ucodes; i++) {
2265                 ucode = &adev->firmware.ucode[i];
2266
2267                 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2268                     !fw_load_skip_check(psp, ucode)) {
2269                         ret = psp_load_smu_fw(psp);
2270                         if (ret)
2271                                 return ret;
2272                         continue;
2273                 }
2274
2275                 if (fw_load_skip_check(psp, ucode))
2276                         continue;
2277
2278                 if (psp->autoload_supported &&
2279                     (adev->asic_type >= CHIP_SIENNA_CICHLID &&
2280                      adev->asic_type <= CHIP_DIMGREY_CAVEFISH) &&
2281                     (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
2282                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
2283                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
2284                         /* PSP only receive one SDMA fw for sienna_cichlid,
2285                          * as all four sdma fw are same */
2286                         continue;
2287
2288                 psp_print_fw_hdr(psp, ucode);
2289
2290                 ret = psp_execute_np_fw_load(psp, ucode);
2291                 if (ret)
2292                         return ret;
2293
2294                 /* Start rlc autoload after psp recieved all the gfx firmware */
2295                 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
2296                     AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) {
2297                         ret = psp_rlc_autoload_start(psp);
2298                         if (ret) {
2299                                 DRM_ERROR("Failed to start rlc autoload\n");
2300                                 return ret;
2301                         }
2302                 }
2303         }
2304
2305         return 0;
2306 }
2307
2308 static int psp_load_fw(struct amdgpu_device *adev)
2309 {
2310         int ret;
2311         struct psp_context *psp = &adev->psp;
2312
2313         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2314                 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */
2315                 goto skip_memalloc;
2316         }
2317
2318         psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
2319         if (!psp->cmd)
2320                 return -ENOMEM;
2321
2322         ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
2323                                         AMDGPU_GEM_DOMAIN_GTT,
2324                                         &psp->fw_pri_bo,
2325                                         &psp->fw_pri_mc_addr,
2326                                         &psp->fw_pri_buf);
2327         if (ret)
2328                 goto failed;
2329
2330         ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
2331                                         AMDGPU_GEM_DOMAIN_VRAM,
2332                                         &psp->fence_buf_bo,
2333                                         &psp->fence_buf_mc_addr,
2334                                         &psp->fence_buf);
2335         if (ret)
2336                 goto failed;
2337
2338         ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
2339                                       AMDGPU_GEM_DOMAIN_VRAM,
2340                                       &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
2341                                       (void **)&psp->cmd_buf_mem);
2342         if (ret)
2343                 goto failed;
2344
2345         memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
2346
2347         ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
2348         if (ret) {
2349                 DRM_ERROR("PSP ring init failed!\n");
2350                 goto failed;
2351         }
2352
2353 skip_memalloc:
2354         ret = psp_hw_start(psp);
2355         if (ret)
2356                 goto failed;
2357
2358         ret = psp_np_fw_load(psp);
2359         if (ret)
2360                 goto failed;
2361
2362         ret = psp_asd_load(psp);
2363         if (ret) {
2364                 DRM_ERROR("PSP load asd failed!\n");
2365                 return ret;
2366         }
2367
2368         ret = psp_rl_load(adev);
2369         if (ret) {
2370                 DRM_ERROR("PSP load RL failed!\n");
2371                 return ret;
2372         }
2373
2374         if (psp->adev->psp.ta_fw) {
2375                 ret = psp_ras_initialize(psp);
2376                 if (ret)
2377                         dev_err(psp->adev->dev,
2378                                         "RAS: Failed to initialize RAS\n");
2379
2380                 ret = psp_hdcp_initialize(psp);
2381                 if (ret)
2382                         dev_err(psp->adev->dev,
2383                                 "HDCP: Failed to initialize HDCP\n");
2384
2385                 ret = psp_dtm_initialize(psp);
2386                 if (ret)
2387                         dev_err(psp->adev->dev,
2388                                 "DTM: Failed to initialize DTM\n");
2389
2390                 ret = psp_rap_initialize(psp);
2391                 if (ret)
2392                         dev_err(psp->adev->dev,
2393                                 "RAP: Failed to initialize RAP\n");
2394
2395                 ret = psp_securedisplay_initialize(psp);
2396                 if (ret)
2397                         dev_err(psp->adev->dev,
2398                                 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2399         }
2400
2401         return 0;
2402
2403 failed:
2404         /*
2405          * all cleanup jobs (xgmi terminate, ras terminate,
2406          * ring destroy, cmd/fence/fw buffers destory,
2407          * psp->cmd destory) are delayed to psp_hw_fini
2408          */
2409         return ret;
2410 }
2411
2412 static int psp_hw_init(void *handle)
2413 {
2414         int ret;
2415         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2416
2417         mutex_lock(&adev->firmware.mutex);
2418         /*
2419          * This sequence is just used on hw_init only once, no need on
2420          * resume.
2421          */
2422         ret = amdgpu_ucode_init_bo(adev);
2423         if (ret)
2424                 goto failed;
2425
2426         ret = psp_load_fw(adev);
2427         if (ret) {
2428                 DRM_ERROR("PSP firmware loading failed\n");
2429                 goto failed;
2430         }
2431
2432         mutex_unlock(&adev->firmware.mutex);
2433         return 0;
2434
2435 failed:
2436         adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
2437         mutex_unlock(&adev->firmware.mutex);
2438         return -EINVAL;
2439 }
2440
2441 static int psp_hw_fini(void *handle)
2442 {
2443         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2444         struct psp_context *psp = &adev->psp;
2445
2446         if (psp->adev->psp.ta_fw) {
2447                 psp_ras_terminate(psp);
2448                 psp_securedisplay_terminate(psp);
2449                 psp_rap_terminate(psp);
2450                 psp_dtm_terminate(psp);
2451                 psp_hdcp_terminate(psp);
2452         }
2453
2454         psp_asd_unload(psp);
2455
2456         psp_tmr_terminate(psp);
2457         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2458
2459         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
2460                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
2461         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
2462                               &psp->fence_buf_mc_addr, &psp->fence_buf);
2463         amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
2464                               (void **)&psp->cmd_buf_mem);
2465
2466         kfree(psp->cmd);
2467         psp->cmd = NULL;
2468
2469         return 0;
2470 }
2471
2472 static int psp_suspend(void *handle)
2473 {
2474         int ret;
2475         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2476         struct psp_context *psp = &adev->psp;
2477
2478         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
2479             psp->xgmi_context.initialized == 1) {
2480                 ret = psp_xgmi_terminate(psp);
2481                 if (ret) {
2482                         DRM_ERROR("Failed to terminate xgmi ta\n");
2483                         return ret;
2484                 }
2485         }
2486
2487         if (psp->adev->psp.ta_fw) {
2488                 ret = psp_ras_terminate(psp);
2489                 if (ret) {
2490                         DRM_ERROR("Failed to terminate ras ta\n");
2491                         return ret;
2492                 }
2493                 ret = psp_hdcp_terminate(psp);
2494                 if (ret) {
2495                         DRM_ERROR("Failed to terminate hdcp ta\n");
2496                         return ret;
2497                 }
2498                 ret = psp_dtm_terminate(psp);
2499                 if (ret) {
2500                         DRM_ERROR("Failed to terminate dtm ta\n");
2501                         return ret;
2502                 }
2503                 ret = psp_rap_terminate(psp);
2504                 if (ret) {
2505                         DRM_ERROR("Failed to terminate rap ta\n");
2506                         return ret;
2507                 }
2508                 ret = psp_securedisplay_terminate(psp);
2509                 if (ret) {
2510                         DRM_ERROR("Failed to terminate securedisplay ta\n");
2511                         return ret;
2512                 }
2513         }
2514
2515         ret = psp_asd_unload(psp);
2516         if (ret) {
2517                 DRM_ERROR("Failed to unload asd\n");
2518                 return ret;
2519         }
2520
2521         ret = psp_tmr_terminate(psp);
2522         if (ret) {
2523                 DRM_ERROR("Failed to terminate tmr\n");
2524                 return ret;
2525         }
2526
2527         ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
2528         if (ret) {
2529                 DRM_ERROR("PSP ring stop failed\n");
2530                 return ret;
2531         }
2532
2533         return 0;
2534 }
2535
2536 static int psp_resume(void *handle)
2537 {
2538         int ret;
2539         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2540         struct psp_context *psp = &adev->psp;
2541
2542         DRM_INFO("PSP is resuming...\n");
2543
2544         ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
2545         if (ret) {
2546                 DRM_ERROR("Failed to process memory training!\n");
2547                 return ret;
2548         }
2549
2550         mutex_lock(&adev->firmware.mutex);
2551
2552         ret = psp_hw_start(psp);
2553         if (ret)
2554                 goto failed;
2555
2556         ret = psp_np_fw_load(psp);
2557         if (ret)
2558                 goto failed;
2559
2560         ret = psp_asd_load(psp);
2561         if (ret) {
2562                 DRM_ERROR("PSP load asd failed!\n");
2563                 goto failed;
2564         }
2565
2566         if (adev->gmc.xgmi.num_physical_nodes > 1) {
2567                 ret = psp_xgmi_initialize(psp);
2568                 /* Warning the XGMI seesion initialize failure
2569                  * Instead of stop driver initialization
2570                  */
2571                 if (ret)
2572                         dev_err(psp->adev->dev,
2573                                 "XGMI: Failed to initialize XGMI session\n");
2574         }
2575
2576         if (psp->adev->psp.ta_fw) {
2577                 ret = psp_ras_initialize(psp);
2578                 if (ret)
2579                         dev_err(psp->adev->dev,
2580                                         "RAS: Failed to initialize RAS\n");
2581
2582                 ret = psp_hdcp_initialize(psp);
2583                 if (ret)
2584                         dev_err(psp->adev->dev,
2585                                 "HDCP: Failed to initialize HDCP\n");
2586
2587                 ret = psp_dtm_initialize(psp);
2588                 if (ret)
2589                         dev_err(psp->adev->dev,
2590                                 "DTM: Failed to initialize DTM\n");
2591
2592                 ret = psp_rap_initialize(psp);
2593                 if (ret)
2594                         dev_err(psp->adev->dev,
2595                                 "RAP: Failed to initialize RAP\n");
2596
2597                 ret = psp_securedisplay_initialize(psp);
2598                 if (ret)
2599                         dev_err(psp->adev->dev,
2600                                 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2601         }
2602
2603         mutex_unlock(&adev->firmware.mutex);
2604
2605         return 0;
2606
2607 failed:
2608         DRM_ERROR("PSP resume failed\n");
2609         mutex_unlock(&adev->firmware.mutex);
2610         return ret;
2611 }
2612
2613 int psp_gpu_reset(struct amdgpu_device *adev)
2614 {
2615         int ret;
2616
2617         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
2618                 return 0;
2619
2620         mutex_lock(&adev->psp.mutex);
2621         ret = psp_mode1_reset(&adev->psp);
2622         mutex_unlock(&adev->psp.mutex);
2623
2624         return ret;
2625 }
2626
2627 int psp_rlc_autoload_start(struct psp_context *psp)
2628 {
2629         int ret;
2630         struct psp_gfx_cmd_resp *cmd;
2631
2632         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
2633         if (!cmd)
2634                 return -ENOMEM;
2635
2636         cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
2637
2638         ret = psp_cmd_submit_buf(psp, NULL, cmd,
2639                                  psp->fence_buf_mc_addr);
2640         kfree(cmd);
2641         return ret;
2642 }
2643
2644 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
2645                         uint64_t cmd_gpu_addr, int cmd_size)
2646 {
2647         struct amdgpu_firmware_info ucode = {0};
2648
2649         ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
2650                 AMDGPU_UCODE_ID_VCN0_RAM;
2651         ucode.mc_addr = cmd_gpu_addr;
2652         ucode.ucode_size = cmd_size;
2653
2654         return psp_execute_np_fw_load(&adev->psp, &ucode);
2655 }
2656
2657 int psp_ring_cmd_submit(struct psp_context *psp,
2658                         uint64_t cmd_buf_mc_addr,
2659                         uint64_t fence_mc_addr,
2660                         int index)
2661 {
2662         unsigned int psp_write_ptr_reg = 0;
2663         struct psp_gfx_rb_frame *write_frame;
2664         struct psp_ring *ring = &psp->km_ring;
2665         struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
2666         struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
2667                 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
2668         struct amdgpu_device *adev = psp->adev;
2669         uint32_t ring_size_dw = ring->ring_size / 4;
2670         uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
2671
2672         /* KM (GPCOM) prepare write pointer */
2673         psp_write_ptr_reg = psp_ring_get_wptr(psp);
2674
2675         /* Update KM RB frame pointer to new frame */
2676         /* write_frame ptr increments by size of rb_frame in bytes */
2677         /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
2678         if ((psp_write_ptr_reg % ring_size_dw) == 0)
2679                 write_frame = ring_buffer_start;
2680         else
2681                 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
2682         /* Check invalid write_frame ptr address */
2683         if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
2684                 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
2685                           ring_buffer_start, ring_buffer_end, write_frame);
2686                 DRM_ERROR("write_frame is pointing to address out of bounds\n");
2687                 return -EINVAL;
2688         }
2689
2690         /* Initialize KM RB frame */
2691         memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
2692
2693         /* Update KM RB frame */
2694         write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
2695         write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
2696         write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
2697         write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
2698         write_frame->fence_value = index;
2699         amdgpu_asic_flush_hdp(adev, NULL);
2700
2701         /* Update the write Pointer in DWORDs */
2702         psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
2703         psp_ring_set_wptr(psp, psp_write_ptr_reg);
2704         return 0;
2705 }
2706
2707 int psp_init_asd_microcode(struct psp_context *psp,
2708                            const char *chip_name)
2709 {
2710         struct amdgpu_device *adev = psp->adev;
2711         char fw_name[PSP_FW_NAME_LEN];
2712         const struct psp_firmware_header_v1_0 *asd_hdr;
2713         int err = 0;
2714
2715         if (!chip_name) {
2716                 dev_err(adev->dev, "invalid chip name for asd microcode\n");
2717                 return -EINVAL;
2718         }
2719
2720         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
2721         err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
2722         if (err)
2723                 goto out;
2724
2725         err = amdgpu_ucode_validate(adev->psp.asd_fw);
2726         if (err)
2727                 goto out;
2728
2729         asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
2730         adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
2731         adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version);
2732         adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
2733         adev->psp.asd_start_addr = (uint8_t *)asd_hdr +
2734                                 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
2735         return 0;
2736 out:
2737         dev_err(adev->dev, "fail to initialize asd microcode\n");
2738         release_firmware(adev->psp.asd_fw);
2739         adev->psp.asd_fw = NULL;
2740         return err;
2741 }
2742
2743 int psp_init_toc_microcode(struct psp_context *psp,
2744                            const char *chip_name)
2745 {
2746         struct amdgpu_device *adev = psp->adev;
2747         char fw_name[30];
2748         const struct psp_firmware_header_v1_0 *toc_hdr;
2749         int err = 0;
2750
2751         if (!chip_name) {
2752                 dev_err(adev->dev, "invalid chip name for toc microcode\n");
2753                 return -EINVAL;
2754         }
2755
2756         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
2757         err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev);
2758         if (err)
2759                 goto out;
2760
2761         err = amdgpu_ucode_validate(adev->psp.toc_fw);
2762         if (err)
2763                 goto out;
2764
2765         toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
2766         adev->psp.toc_fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
2767         adev->psp.toc_feature_version = le32_to_cpu(toc_hdr->ucode_feature_version);
2768         adev->psp.toc_bin_size = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
2769         adev->psp.toc_start_addr = (uint8_t *)toc_hdr +
2770                                 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
2771         return 0;
2772 out:
2773         dev_err(adev->dev, "fail to request/validate toc microcode\n");
2774         release_firmware(adev->psp.toc_fw);
2775         adev->psp.toc_fw = NULL;
2776         return err;
2777 }
2778
2779 int psp_init_sos_microcode(struct psp_context *psp,
2780                            const char *chip_name)
2781 {
2782         struct amdgpu_device *adev = psp->adev;
2783         char fw_name[PSP_FW_NAME_LEN];
2784         const struct psp_firmware_header_v1_0 *sos_hdr;
2785         const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
2786         const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
2787         const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
2788         int err = 0;
2789
2790         if (!chip_name) {
2791                 dev_err(adev->dev, "invalid chip name for sos microcode\n");
2792                 return -EINVAL;
2793         }
2794
2795         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
2796         err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
2797         if (err)
2798                 goto out;
2799
2800         err = amdgpu_ucode_validate(adev->psp.sos_fw);
2801         if (err)
2802                 goto out;
2803
2804         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
2805         amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
2806
2807         switch (sos_hdr->header.header_version_major) {
2808         case 1:
2809                 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
2810                 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version);
2811                 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes);
2812                 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes);
2813                 adev->psp.sys_start_addr = (uint8_t *)sos_hdr +
2814                                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
2815                 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2816                                 le32_to_cpu(sos_hdr->sos_offset_bytes);
2817                 if (sos_hdr->header.header_version_minor == 1) {
2818                         sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
2819                         adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes);
2820                         adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2821                                         le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes);
2822                         adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes);
2823                         adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2824                                         le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes);
2825                 }
2826                 if (sos_hdr->header.header_version_minor == 2) {
2827                         sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
2828                         adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes);
2829                         adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2830                                                     le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes);
2831                 }
2832                 if (sos_hdr->header.header_version_minor == 3) {
2833                         sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
2834                         adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.toc_size_bytes);
2835                         adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2836                                 le32_to_cpu(sos_hdr_v1_3->v1_1.toc_offset_bytes);
2837                         adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_size_bytes);
2838                         adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2839                                 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_offset_bytes);
2840                         adev->psp.spl_bin_size = le32_to_cpu(sos_hdr_v1_3->spl_size_bytes);
2841                         adev->psp.spl_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2842                                 le32_to_cpu(sos_hdr_v1_3->spl_offset_bytes);
2843                         adev->psp.rl_bin_size = le32_to_cpu(sos_hdr_v1_3->rl_size_bytes);
2844                         adev->psp.rl_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2845                                 le32_to_cpu(sos_hdr_v1_3->rl_offset_bytes);
2846                 }
2847                 break;
2848         default:
2849                 dev_err(adev->dev,
2850                         "unsupported psp sos firmware\n");
2851                 err = -EINVAL;
2852                 goto out;
2853         }
2854
2855         return 0;
2856 out:
2857         dev_err(adev->dev,
2858                 "failed to init sos firmware\n");
2859         release_firmware(adev->psp.sos_fw);
2860         adev->psp.sos_fw = NULL;
2861
2862         return err;
2863 }
2864
2865 static int parse_ta_bin_descriptor(struct psp_context *psp,
2866                                    const struct ta_fw_bin_desc *desc,
2867                                    const struct ta_firmware_header_v2_0 *ta_hdr)
2868 {
2869         uint8_t *ucode_start_addr  = NULL;
2870
2871         if (!psp || !desc || !ta_hdr)
2872                 return -EINVAL;
2873
2874         ucode_start_addr  = (uint8_t *)ta_hdr +
2875                             le32_to_cpu(desc->offset_bytes) +
2876                             le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
2877
2878         switch (desc->fw_type) {
2879         case TA_FW_TYPE_PSP_ASD:
2880                 psp->asd_fw_version        = le32_to_cpu(desc->fw_version);
2881                 psp->asd_feature_version   = le32_to_cpu(desc->fw_version);
2882                 psp->asd_ucode_size        = le32_to_cpu(desc->size_bytes);
2883                 psp->asd_start_addr        = ucode_start_addr;
2884                 break;
2885         case TA_FW_TYPE_PSP_XGMI:
2886                 psp->ta_xgmi_ucode_version = le32_to_cpu(desc->fw_version);
2887                 psp->ta_xgmi_ucode_size    = le32_to_cpu(desc->size_bytes);
2888                 psp->ta_xgmi_start_addr    = ucode_start_addr;
2889                 break;
2890         case TA_FW_TYPE_PSP_RAS:
2891                 psp->ta_ras_ucode_version  = le32_to_cpu(desc->fw_version);
2892                 psp->ta_ras_ucode_size     = le32_to_cpu(desc->size_bytes);
2893                 psp->ta_ras_start_addr     = ucode_start_addr;
2894                 break;
2895         case TA_FW_TYPE_PSP_HDCP:
2896                 psp->ta_hdcp_ucode_version = le32_to_cpu(desc->fw_version);
2897                 psp->ta_hdcp_ucode_size    = le32_to_cpu(desc->size_bytes);
2898                 psp->ta_hdcp_start_addr    = ucode_start_addr;
2899                 break;
2900         case TA_FW_TYPE_PSP_DTM:
2901                 psp->ta_dtm_ucode_version  = le32_to_cpu(desc->fw_version);
2902                 psp->ta_dtm_ucode_size     = le32_to_cpu(desc->size_bytes);
2903                 psp->ta_dtm_start_addr     = ucode_start_addr;
2904                 break;
2905         case TA_FW_TYPE_PSP_RAP:
2906                 psp->ta_rap_ucode_version  = le32_to_cpu(desc->fw_version);
2907                 psp->ta_rap_ucode_size     = le32_to_cpu(desc->size_bytes);
2908                 psp->ta_rap_start_addr     = ucode_start_addr;
2909                 break;
2910         case TA_FW_TYPE_PSP_SECUREDISPLAY:
2911                 psp->ta_securedisplay_ucode_version  = le32_to_cpu(desc->fw_version);
2912                 psp->ta_securedisplay_ucode_size     = le32_to_cpu(desc->size_bytes);
2913                 psp->ta_securedisplay_start_addr     = ucode_start_addr;
2914                 break;
2915         default:
2916                 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type);
2917                 break;
2918         }
2919
2920         return 0;
2921 }
2922
2923 int psp_init_ta_microcode(struct psp_context *psp,
2924                           const char *chip_name)
2925 {
2926         struct amdgpu_device *adev = psp->adev;
2927         char fw_name[PSP_FW_NAME_LEN];
2928         const struct ta_firmware_header_v2_0 *ta_hdr;
2929         int err = 0;
2930         int ta_index = 0;
2931
2932         if (!chip_name) {
2933                 dev_err(adev->dev, "invalid chip name for ta microcode\n");
2934                 return -EINVAL;
2935         }
2936
2937         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
2938         err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
2939         if (err)
2940                 goto out;
2941
2942         err = amdgpu_ucode_validate(adev->psp.ta_fw);
2943         if (err)
2944                 goto out;
2945
2946         ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data;
2947
2948         if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) {
2949                 dev_err(adev->dev, "unsupported TA header version\n");
2950                 err = -EINVAL;
2951                 goto out;
2952         }
2953
2954         if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_TA_PACKAGING) {
2955                 dev_err(adev->dev, "packed TA count exceeds maximum limit\n");
2956                 err = -EINVAL;
2957                 goto out;
2958         }
2959
2960         for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) {
2961                 err = parse_ta_bin_descriptor(psp,
2962                                               &ta_hdr->ta_fw_bin[ta_index],
2963                                               ta_hdr);
2964                 if (err)
2965                         goto out;
2966         }
2967
2968         return 0;
2969 out:
2970         dev_err(adev->dev, "fail to initialize ta microcode\n");
2971         release_firmware(adev->psp.ta_fw);
2972         adev->psp.ta_fw = NULL;
2973         return err;
2974 }
2975
2976 static int psp_set_clockgating_state(void *handle,
2977                                      enum amd_clockgating_state state)
2978 {
2979         return 0;
2980 }
2981
2982 static int psp_set_powergating_state(void *handle,
2983                                      enum amd_powergating_state state)
2984 {
2985         return 0;
2986 }
2987
2988 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,
2989                                          struct device_attribute *attr,
2990                                          char *buf)
2991 {
2992         struct drm_device *ddev = dev_get_drvdata(dev);
2993         struct amdgpu_device *adev = drm_to_adev(ddev);
2994         uint32_t fw_ver;
2995         int ret;
2996
2997         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
2998                 DRM_INFO("PSP block is not ready yet.");
2999                 return -EBUSY;
3000         }
3001
3002         mutex_lock(&adev->psp.mutex);
3003         ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver);
3004         mutex_unlock(&adev->psp.mutex);
3005
3006         if (ret) {
3007                 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret);
3008                 return ret;
3009         }
3010
3011         return sysfs_emit(buf, "%x\n", fw_ver);
3012 }
3013
3014 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
3015                                                        struct device_attribute *attr,
3016                                                        const char *buf,
3017                                                        size_t count)
3018 {
3019         struct drm_device *ddev = dev_get_drvdata(dev);
3020         struct amdgpu_device *adev = drm_to_adev(ddev);
3021         void *cpu_addr;
3022         dma_addr_t dma_addr;
3023         int ret;
3024         char fw_name[100];
3025         const struct firmware *usbc_pd_fw;
3026
3027         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3028                 DRM_INFO("PSP block is not ready yet.");
3029                 return -EBUSY;
3030         }
3031
3032         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf);
3033         ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev);
3034         if (ret)
3035                 goto fail;
3036
3037         /* We need contiguous physical mem to place the FW  for psp to access */
3038         cpu_addr = dma_alloc_coherent(adev->dev, usbc_pd_fw->size, &dma_addr, GFP_KERNEL);
3039
3040         ret = dma_mapping_error(adev->dev, dma_addr);
3041         if (ret)
3042                 goto rel_buf;
3043
3044         memcpy_toio(cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size);
3045
3046         /*
3047          * x86 specific workaround.
3048          * Without it the buffer is invisible in PSP.
3049          *
3050          * TODO Remove once PSP starts snooping CPU cache
3051          */
3052 #ifdef CONFIG_X86
3053         clflush_cache_range(cpu_addr, (usbc_pd_fw->size & ~(L1_CACHE_BYTES - 1)));
3054 #endif
3055
3056         mutex_lock(&adev->psp.mutex);
3057         ret = psp_load_usbc_pd_fw(&adev->psp, dma_addr);
3058         mutex_unlock(&adev->psp.mutex);
3059
3060 rel_buf:
3061         dma_free_coherent(adev->dev, usbc_pd_fw->size, cpu_addr, dma_addr);
3062         release_firmware(usbc_pd_fw);
3063
3064 fail:
3065         if (ret) {
3066                 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret);
3067                 return ret;
3068         }
3069
3070         return count;
3071 }
3072
3073 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR,
3074                    psp_usbc_pd_fw_sysfs_read,
3075                    psp_usbc_pd_fw_sysfs_write);
3076
3077
3078
3079 const struct amd_ip_funcs psp_ip_funcs = {
3080         .name = "psp",
3081         .early_init = psp_early_init,
3082         .late_init = NULL,
3083         .sw_init = psp_sw_init,
3084         .sw_fini = psp_sw_fini,
3085         .hw_init = psp_hw_init,
3086         .hw_fini = psp_hw_fini,
3087         .suspend = psp_suspend,
3088         .resume = psp_resume,
3089         .is_idle = NULL,
3090         .check_soft_reset = NULL,
3091         .wait_for_idle = NULL,
3092         .soft_reset = NULL,
3093         .set_clockgating_state = psp_set_clockgating_state,
3094         .set_powergating_state = psp_set_powergating_state,
3095 };
3096
3097 static int psp_sysfs_init(struct amdgpu_device *adev)
3098 {
3099         int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw);
3100
3101         if (ret)
3102                 DRM_ERROR("Failed to create USBC PD FW control file!");
3103
3104         return ret;
3105 }
3106
3107 static void psp_sysfs_fini(struct amdgpu_device *adev)
3108 {
3109         device_remove_file(adev->dev, &dev_attr_usbc_pd_fw);
3110 }
3111
3112 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
3113 {
3114         .type = AMD_IP_BLOCK_TYPE_PSP,
3115         .major = 3,
3116         .minor = 1,
3117         .rev = 0,
3118         .funcs = &psp_ip_funcs,
3119 };
3120
3121 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
3122 {
3123         .type = AMD_IP_BLOCK_TYPE_PSP,
3124         .major = 10,
3125         .minor = 0,
3126         .rev = 0,
3127         .funcs = &psp_ip_funcs,
3128 };
3129
3130 const struct amdgpu_ip_block_version psp_v11_0_ip_block =
3131 {
3132         .type = AMD_IP_BLOCK_TYPE_PSP,
3133         .major = 11,
3134         .minor = 0,
3135         .rev = 0,
3136         .funcs = &psp_ip_funcs,
3137 };
3138
3139 const struct amdgpu_ip_block_version psp_v12_0_ip_block =
3140 {
3141         .type = AMD_IP_BLOCK_TYPE_PSP,
3142         .major = 12,
3143         .minor = 0,
3144         .rev = 0,
3145         .funcs = &psp_ip_funcs,
3146 };
3147
3148 const struct amdgpu_ip_block_version psp_v13_0_ip_block = {
3149         .type = AMD_IP_BLOCK_TYPE_PSP,
3150         .major = 13,
3151         .minor = 0,
3152         .rev = 0,
3153         .funcs = &psp_ip_funcs,
3154 };