include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63 };
  64
  65 enum {
  66         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  67         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  68         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  69         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  70 };
  71
  72 enum {
  73         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  74         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  75 };
  76
  77 enum {
  78         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  79         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  80         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  81         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  82         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  83         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  84         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  85         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  86         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  87         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  88         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  89         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
  90         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  91         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  92         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  93         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
  94         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
  95         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
  96         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
  97         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
  98         MLX5_CMD_OP_GEN_EQE                       = 0x304,
  99         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 100         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 101         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 102         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 103         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 104         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 105         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 106         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 107         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 108         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 109         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 110         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 111         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 112         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 113         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 114         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 115         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 116         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 117         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 118         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 119         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 120         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 121         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 122         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 123         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 124         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 125         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 126         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 127         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 128         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 129         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 130         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 131         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 132         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 133         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 134         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 135         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 136         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 137         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 138         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 139         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 140         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 141         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 142         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 143         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 144         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 145         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 146         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 147         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 148         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 149         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 150         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
 151         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 152         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 153         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 154         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 155         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 156         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 157         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 158         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 159         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 160         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 161         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 162         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 163         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 164         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 165         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 166         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 167         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 168         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 169         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 170         MLX5_CMD_OP_NOP                           = 0x80d,
 171         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 172         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 173         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 174         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 175         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 176         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 177         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 178         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 179         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 180         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 181         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 182         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 183         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 184         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 185         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 186         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 187         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 188         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 189         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 190         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 191         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 192         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 193         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 194         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 195         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 196         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 197         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 198         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 199         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 200         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 201         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 202         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 203         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 204         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 205         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 206         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 207         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 208         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 209         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 210         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 211         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 212         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 213         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 214         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 215         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 216         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 217         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 218         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 219         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 220         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 221         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 222         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 223         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 224         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 225         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 226         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 227         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 228         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 229         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 230         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 231         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 232         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
 233         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
 234         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 235         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 236         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 237         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 238         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 239         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 240         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 241         MLX5_CMD_OP_MAX
 242 };
 243
 244 struct mlx5_ifc_flow_table_fields_supported_bits {
 245         u8         outer_dmac[0x1];
 246         u8         outer_smac[0x1];
 247         u8         outer_ether_type[0x1];
 248         u8         outer_ip_version[0x1];
 249         u8         outer_first_prio[0x1];
 250         u8         outer_first_cfi[0x1];
 251         u8         outer_first_vid[0x1];
 252         u8         outer_ipv4_ttl[0x1];
 253         u8         outer_second_prio[0x1];
 254         u8         outer_second_cfi[0x1];
 255         u8         outer_second_vid[0x1];
 256         u8         reserved_at_b[0x1];
 257         u8         outer_sip[0x1];
 258         u8         outer_dip[0x1];
 259         u8         outer_frag[0x1];
 260         u8         outer_ip_protocol[0x1];
 261         u8         outer_ip_ecn[0x1];
 262         u8         outer_ip_dscp[0x1];
 263         u8         outer_udp_sport[0x1];
 264         u8         outer_udp_dport[0x1];
 265         u8         outer_tcp_sport[0x1];
 266         u8         outer_tcp_dport[0x1];
 267         u8         outer_tcp_flags[0x1];
 268         u8         outer_gre_protocol[0x1];
 269         u8         outer_gre_key[0x1];
 270         u8         outer_vxlan_vni[0x1];
 271         u8         reserved_at_1a[0x5];
 272         u8         source_eswitch_port[0x1];
 273
 274         u8         inner_dmac[0x1];
 275         u8         inner_smac[0x1];
 276         u8         inner_ether_type[0x1];
 277         u8         inner_ip_version[0x1];
 278         u8         inner_first_prio[0x1];
 279         u8         inner_first_cfi[0x1];
 280         u8         inner_first_vid[0x1];
 281         u8         reserved_at_27[0x1];
 282         u8         inner_second_prio[0x1];
 283         u8         inner_second_cfi[0x1];
 284         u8         inner_second_vid[0x1];
 285         u8         reserved_at_2b[0x1];
 286         u8         inner_sip[0x1];
 287         u8         inner_dip[0x1];
 288         u8         inner_frag[0x1];
 289         u8         inner_ip_protocol[0x1];
 290         u8         inner_ip_ecn[0x1];
 291         u8         inner_ip_dscp[0x1];
 292         u8         inner_udp_sport[0x1];
 293         u8         inner_udp_dport[0x1];
 294         u8         inner_tcp_sport[0x1];
 295         u8         inner_tcp_dport[0x1];
 296         u8         inner_tcp_flags[0x1];
 297         u8         reserved_at_37[0x9];
 298         u8         reserved_at_40[0x1a];
 299         u8         bth_dst_qp[0x1];
 300
 301         u8         reserved_at_5b[0x25];
 302 };
 303
 304 struct mlx5_ifc_flow_table_prop_layout_bits {
 305         u8         ft_support[0x1];
 306         u8         reserved_at_1[0x1];
 307         u8         flow_counter[0x1];
 308         u8         flow_modify_en[0x1];
 309         u8         modify_root[0x1];
 310         u8         identified_miss_table_mode[0x1];
 311         u8         flow_table_modify[0x1];
 312         u8         encap[0x1];
 313         u8         decap[0x1];
 314         u8         reserved_at_9[0x17];
 315
 316         u8         reserved_at_20[0x2];
 317         u8         log_max_ft_size[0x6];
 318         u8         log_max_modify_header_context[0x8];
 319         u8         max_modify_header_actions[0x8];
 320         u8         max_ft_level[0x8];
 321
 322         u8         reserved_at_40[0x20];
 323
 324         u8         reserved_at_60[0x18];
 325         u8         log_max_ft_num[0x8];
 326
 327         u8         reserved_at_80[0x18];
 328         u8         log_max_destination[0x8];
 329
 330         u8         log_max_flow_counter[0x8];
 331         u8         reserved_at_a8[0x10];
 332         u8         log_max_flow[0x8];
 333
 334         u8         reserved_at_c0[0x40];
 335
 336         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 337
 338         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 339 };
 340
 341 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 342         u8         send[0x1];
 343         u8         receive[0x1];
 344         u8         write[0x1];
 345         u8         read[0x1];
 346         u8         atomic[0x1];
 347         u8         srq_receive[0x1];
 348         u8         reserved_at_6[0x1a];
 349 };
 350
 351 struct mlx5_ifc_ipv4_layout_bits {
 352         u8         reserved_at_0[0x60];
 353
 354         u8         ipv4[0x20];
 355 };
 356
 357 struct mlx5_ifc_ipv6_layout_bits {
 358         u8         ipv6[16][0x8];
 359 };
 360
 361 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 362         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 363         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 364         u8         reserved_at_0[0x80];
 365 };
 366
 367 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 368         u8         smac_47_16[0x20];
 369
 370         u8         smac_15_0[0x10];
 371         u8         ethertype[0x10];
 372
 373         u8         dmac_47_16[0x20];
 374
 375         u8         dmac_15_0[0x10];
 376         u8         first_prio[0x3];
 377         u8         first_cfi[0x1];
 378         u8         first_vid[0xc];
 379
 380         u8         ip_protocol[0x8];
 381         u8         ip_dscp[0x6];
 382         u8         ip_ecn[0x2];
 383         u8         cvlan_tag[0x1];
 384         u8         svlan_tag[0x1];
 385         u8         frag[0x1];
 386         u8         ip_version[0x4];
 387         u8         tcp_flags[0x9];
 388
 389         u8         tcp_sport[0x10];
 390         u8         tcp_dport[0x10];
 391
 392         u8         reserved_at_c0[0x18];
 393         u8         ttl_hoplimit[0x8];
 394
 395         u8         udp_sport[0x10];
 396         u8         udp_dport[0x10];
 397
 398         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 399
 400         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 401 };
 402
 403 struct mlx5_ifc_fte_match_set_misc_bits {
 404         u8         reserved_at_0[0x8];
 405         u8         source_sqn[0x18];
 406
 407         u8         reserved_at_20[0x10];
 408         u8         source_port[0x10];
 409
 410         u8         outer_second_prio[0x3];
 411         u8         outer_second_cfi[0x1];
 412         u8         outer_second_vid[0xc];
 413         u8         inner_second_prio[0x3];
 414         u8         inner_second_cfi[0x1];
 415         u8         inner_second_vid[0xc];
 416
 417         u8         outer_second_cvlan_tag[0x1];
 418         u8         inner_second_cvlan_tag[0x1];
 419         u8         outer_second_svlan_tag[0x1];
 420         u8         inner_second_svlan_tag[0x1];
 421         u8         reserved_at_64[0xc];
 422         u8         gre_protocol[0x10];
 423
 424         u8         gre_key_h[0x18];
 425         u8         gre_key_l[0x8];
 426
 427         u8         vxlan_vni[0x18];
 428         u8         reserved_at_b8[0x8];
 429
 430         u8         reserved_at_c0[0x20];
 431
 432         u8         reserved_at_e0[0xc];
 433         u8         outer_ipv6_flow_label[0x14];
 434
 435         u8         reserved_at_100[0xc];
 436         u8         inner_ipv6_flow_label[0x14];
 437
 438         u8         reserved_at_120[0x28];
 439         u8         bth_dst_qp[0x18];
 440         u8         reserved_at_160[0xa0];
 441 };
 442
 443 struct mlx5_ifc_cmd_pas_bits {
 444         u8         pa_h[0x20];
 445
 446         u8         pa_l[0x14];
 447         u8         reserved_at_34[0xc];
 448 };
 449
 450 struct mlx5_ifc_uint64_bits {
 451         u8         hi[0x20];
 452
 453         u8         lo[0x20];
 454 };
 455
 456 enum {
 457         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 458         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 459         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 460         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 461         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 462         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 463         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 464         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 465         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 466         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 467 };
 468
 469 struct mlx5_ifc_ads_bits {
 470         u8         fl[0x1];
 471         u8         free_ar[0x1];
 472         u8         reserved_at_2[0xe];
 473         u8         pkey_index[0x10];
 474
 475         u8         reserved_at_20[0x8];
 476         u8         grh[0x1];
 477         u8         mlid[0x7];
 478         u8         rlid[0x10];
 479
 480         u8         ack_timeout[0x5];
 481         u8         reserved_at_45[0x3];
 482         u8         src_addr_index[0x8];
 483         u8         reserved_at_50[0x4];
 484         u8         stat_rate[0x4];
 485         u8         hop_limit[0x8];
 486
 487         u8         reserved_at_60[0x4];
 488         u8         tclass[0x8];
 489         u8         flow_label[0x14];
 490
 491         u8         rgid_rip[16][0x8];
 492
 493         u8         reserved_at_100[0x4];
 494         u8         f_dscp[0x1];
 495         u8         f_ecn[0x1];
 496         u8         reserved_at_106[0x1];
 497         u8         f_eth_prio[0x1];
 498         u8         ecn[0x2];
 499         u8         dscp[0x6];
 500         u8         udp_sport[0x10];
 501
 502         u8         dei_cfi[0x1];
 503         u8         eth_prio[0x3];
 504         u8         sl[0x4];
 505         u8         vhca_port_num[0x8];
 506         u8         rmac_47_32[0x10];
 507
 508         u8         rmac_31_0[0x20];
 509 };
 510
 511 struct mlx5_ifc_flow_table_nic_cap_bits {
 512         u8         nic_rx_multi_path_tirs[0x1];
 513         u8         nic_rx_multi_path_tirs_fts[0x1];
 514         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 515         u8         reserved_at_3[0x1fd];
 516
 517         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 518
 519         u8         reserved_at_400[0x200];
 520
 521         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 522
 523         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 524
 525         u8         reserved_at_a00[0x200];
 526
 527         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 528
 529         u8         reserved_at_e00[0x7200];
 530 };
 531
 532 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 533         u8     reserved_at_0[0x200];
 534
 535         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 536
 537         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 538
 539         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 540
 541         u8      reserved_at_800[0x7800];
 542 };
 543
 544 struct mlx5_ifc_e_switch_cap_bits {
 545         u8         vport_svlan_strip[0x1];
 546         u8         vport_cvlan_strip[0x1];
 547         u8         vport_svlan_insert[0x1];
 548         u8         vport_cvlan_insert_if_not_exist[0x1];
 549         u8         vport_cvlan_insert_overwrite[0x1];
 550         u8         reserved_at_5[0x19];
 551         u8         nic_vport_node_guid_modify[0x1];
 552         u8         nic_vport_port_guid_modify[0x1];
 553
 554         u8         vxlan_encap_decap[0x1];
 555         u8         nvgre_encap_decap[0x1];
 556         u8         reserved_at_22[0x9];
 557         u8         log_max_encap_headers[0x5];
 558         u8         reserved_2b[0x6];
 559         u8         max_encap_header_size[0xa];
 560
 561         u8         reserved_40[0x7c0];
 562
 563 };
 564
 565 struct mlx5_ifc_qos_cap_bits {
 566         u8         packet_pacing[0x1];
 567         u8         esw_scheduling[0x1];
 568         u8         esw_bw_share[0x1];
 569         u8         esw_rate_limit[0x1];
 570         u8         reserved_at_4[0x1c];
 571
 572         u8         reserved_at_20[0x20];
 573
 574         u8         packet_pacing_max_rate[0x20];
 575
 576         u8         packet_pacing_min_rate[0x20];
 577
 578         u8         reserved_at_80[0x10];
 579         u8         packet_pacing_rate_table_size[0x10];
 580
 581         u8         esw_element_type[0x10];
 582         u8         esw_tsar_type[0x10];
 583
 584         u8         reserved_at_c0[0x10];
 585         u8         max_qos_para_vport[0x10];
 586
 587         u8         max_tsar_bw_share[0x20];
 588
 589         u8         reserved_at_100[0x700];
 590 };
 591
 592 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 593         u8         csum_cap[0x1];
 594         u8         vlan_cap[0x1];
 595         u8         lro_cap[0x1];
 596         u8         lro_psh_flag[0x1];
 597         u8         lro_time_stamp[0x1];
 598         u8         reserved_at_5[0x2];
 599         u8         wqe_vlan_insert[0x1];
 600         u8         self_lb_en_modifiable[0x1];
 601         u8         reserved_at_9[0x2];
 602         u8         max_lso_cap[0x5];
 603         u8         multi_pkt_send_wqe[0x2];
 604         u8         wqe_inline_mode[0x2];
 605         u8         rss_ind_tbl_cap[0x4];
 606         u8         reg_umr_sq[0x1];
 607         u8         scatter_fcs[0x1];
 608         u8         enhanced_multi_pkt_send_wqe[0x1];
 609         u8         tunnel_lso_const_out_ip_id[0x1];
 610         u8         reserved_at_1c[0x2];
 611         u8         tunnel_stateless_gre[0x1];
 612         u8         tunnel_stateless_vxlan[0x1];
 613
 614         u8         swp[0x1];
 615         u8         swp_csum[0x1];
 616         u8         swp_lso[0x1];
 617         u8         reserved_at_23[0x1b];
 618         u8         max_geneve_opt_len[0x1];
 619         u8         tunnel_stateless_geneve_rx[0x1];
 620
 621         u8         reserved_at_40[0x10];
 622         u8         lro_min_mss_size[0x10];
 623
 624         u8         reserved_at_60[0x120];
 625
 626         u8         lro_timer_supported_periods[4][0x20];
 627
 628         u8         reserved_at_200[0x600];
 629 };
 630
 631 struct mlx5_ifc_roce_cap_bits {
 632         u8         roce_apm[0x1];
 633         u8         reserved_at_1[0x1f];
 634
 635         u8         reserved_at_20[0x60];
 636
 637         u8         reserved_at_80[0xc];
 638         u8         l3_type[0x4];
 639         u8         reserved_at_90[0x8];
 640         u8         roce_version[0x8];
 641
 642         u8         reserved_at_a0[0x10];
 643         u8         r_roce_dest_udp_port[0x10];
 644
 645         u8         r_roce_max_src_udp_port[0x10];
 646         u8         r_roce_min_src_udp_port[0x10];
 647
 648         u8         reserved_at_e0[0x10];
 649         u8         roce_address_table_size[0x10];
 650
 651         u8         reserved_at_100[0x700];
 652 };
 653
 654 enum {
 655         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 656         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 657         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 658         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 659         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 660         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 661         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 662         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 663         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 664 };
 665
 666 enum {
 667         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 668         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 669         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 670         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 671         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 672         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 673         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 674         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 675         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 676 };
 677
 678 struct mlx5_ifc_atomic_caps_bits {
 679         u8         reserved_at_0[0x40];
 680
 681         u8         atomic_req_8B_endianness_mode[0x2];
 682         u8         reserved_at_42[0x4];
 683         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
 684
 685         u8         reserved_at_47[0x19];
 686
 687         u8         reserved_at_60[0x20];
 688
 689         u8         reserved_at_80[0x10];
 690         u8         atomic_operations[0x10];
 691
 692         u8         reserved_at_a0[0x10];
 693         u8         atomic_size_qp[0x10];
 694
 695         u8         reserved_at_c0[0x10];
 696         u8         atomic_size_dc[0x10];
 697
 698         u8         reserved_at_e0[0x720];
 699 };
 700
 701 struct mlx5_ifc_odp_cap_bits {
 702         u8         reserved_at_0[0x40];
 703
 704         u8         sig[0x1];
 705         u8         reserved_at_41[0x1f];
 706
 707         u8         reserved_at_60[0x20];
 708
 709         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 710
 711         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 712
 713         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 714
 715         u8         reserved_at_e0[0x720];
 716 };
 717
 718 struct mlx5_ifc_calc_op {
 719         u8        reserved_at_0[0x10];
 720         u8        reserved_at_10[0x9];
 721         u8        op_swap_endianness[0x1];
 722         u8        op_min[0x1];
 723         u8        op_xor[0x1];
 724         u8        op_or[0x1];
 725         u8        op_and[0x1];
 726         u8        op_max[0x1];
 727         u8        op_add[0x1];
 728 };
 729
 730 struct mlx5_ifc_vector_calc_cap_bits {
 731         u8         calc_matrix[0x1];
 732         u8         reserved_at_1[0x1f];
 733         u8         reserved_at_20[0x8];
 734         u8         max_vec_count[0x8];
 735         u8         reserved_at_30[0xd];
 736         u8         max_chunk_size[0x3];
 737         struct mlx5_ifc_calc_op calc0;
 738         struct mlx5_ifc_calc_op calc1;
 739         struct mlx5_ifc_calc_op calc2;
 740         struct mlx5_ifc_calc_op calc3;
 741
 742         u8         reserved_at_e0[0x720];
 743 };
 744
 745 enum {
 746         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 747         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 748         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
 749         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
 750 };
 751
 752 enum {
 753         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 754         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 755 };
 756
 757 enum {
 758         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 759         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 760         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 761         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 762         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 763 };
 764
 765 enum {
 766         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 767         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 768         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 769         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 770         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 771         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 772 };
 773
 774 enum {
 775         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 776         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 777 };
 778
 779 enum {
 780         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 781         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 782         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 783 };
 784
 785 enum {
 786         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 787         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 788 };
 789
 790 enum {
 791         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
 792         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
 793         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
 794 };
 795
 796 struct mlx5_ifc_cmd_hca_cap_bits {
 797         u8         reserved_at_0[0x30];
 798         u8         vhca_id[0x10];
 799
 800         u8         reserved_at_40[0x40];
 801
 802         u8         log_max_srq_sz[0x8];
 803         u8         log_max_qp_sz[0x8];
 804         u8         reserved_at_90[0xb];
 805         u8         log_max_qp[0x5];
 806
 807         u8         reserved_at_a0[0xb];
 808         u8         log_max_srq[0x5];
 809         u8         reserved_at_b0[0x10];
 810
 811         u8         reserved_at_c0[0x8];
 812         u8         log_max_cq_sz[0x8];
 813         u8         reserved_at_d0[0xb];
 814         u8         log_max_cq[0x5];
 815
 816         u8         log_max_eq_sz[0x8];
 817         u8         reserved_at_e8[0x2];
 818         u8         log_max_mkey[0x6];
 819         u8         reserved_at_f0[0xc];
 820         u8         log_max_eq[0x4];
 821
 822         u8         max_indirection[0x8];
 823         u8         fixed_buffer_size[0x1];
 824         u8         log_max_mrw_sz[0x7];
 825         u8         force_teardown[0x1];
 826         u8         reserved_at_111[0x1];
 827         u8         log_max_bsf_list_size[0x6];
 828         u8         umr_extended_translation_offset[0x1];
 829         u8         null_mkey[0x1];
 830         u8         log_max_klm_list_size[0x6];
 831
 832         u8         reserved_at_120[0xa];
 833         u8         log_max_ra_req_dc[0x6];
 834         u8         reserved_at_130[0xa];
 835         u8         log_max_ra_res_dc[0x6];
 836
 837         u8         reserved_at_140[0xa];
 838         u8         log_max_ra_req_qp[0x6];
 839         u8         reserved_at_150[0xa];
 840         u8         log_max_ra_res_qp[0x6];
 841
 842         u8         end_pad[0x1];
 843         u8         cc_query_allowed[0x1];
 844         u8         cc_modify_allowed[0x1];
 845         u8         start_pad[0x1];
 846         u8         cache_line_128byte[0x1];
 847         u8         reserved_at_165[0xa];
 848         u8         qcam_reg[0x1];
 849         u8         gid_table_size[0x10];
 850
 851         u8         out_of_seq_cnt[0x1];
 852         u8         vport_counters[0x1];
 853         u8         retransmission_q_counters[0x1];
 854         u8         reserved_at_183[0x1];
 855         u8         modify_rq_counter_set_id[0x1];
 856         u8         rq_delay_drop[0x1];
 857         u8         max_qp_cnt[0xa];
 858         u8         pkey_table_size[0x10];
 859
 860         u8         vport_group_manager[0x1];
 861         u8         vhca_group_manager[0x1];
 862         u8         ib_virt[0x1];
 863         u8         eth_virt[0x1];
 864         u8         reserved_at_1a4[0x1];
 865         u8         ets[0x1];
 866         u8         nic_flow_table[0x1];
 867         u8         eswitch_flow_table[0x1];
 868         u8         early_vf_enable[0x1];
 869         u8         mcam_reg[0x1];
 870         u8         pcam_reg[0x1];
 871         u8         local_ca_ack_delay[0x5];
 872         u8         port_module_event[0x1];
 873         u8         enhanced_error_q_counters[0x1];
 874         u8         ports_check[0x1];
 875         u8         reserved_at_1b3[0x1];
 876         u8         disable_link_up[0x1];
 877         u8         beacon_led[0x1];
 878         u8         port_type[0x2];
 879         u8         num_ports[0x8];
 880
 881         u8         reserved_at_1c0[0x1];
 882         u8         pps[0x1];
 883         u8         pps_modify[0x1];
 884         u8         log_max_msg[0x5];
 885         u8         reserved_at_1c8[0x4];
 886         u8         max_tc[0x4];
 887         u8         reserved_at_1d0[0x1];
 888         u8         dcbx[0x1];
 889         u8         general_notification_event[0x1];
 890         u8         reserved_at_1d3[0x2];
 891         u8         fpga[0x1];
 892         u8         rol_s[0x1];
 893         u8         rol_g[0x1];
 894         u8         reserved_at_1d8[0x1];
 895         u8         wol_s[0x1];
 896         u8         wol_g[0x1];
 897         u8         wol_a[0x1];
 898         u8         wol_b[0x1];
 899         u8         wol_m[0x1];
 900         u8         wol_u[0x1];
 901         u8         wol_p[0x1];
 902
 903         u8         stat_rate_support[0x10];
 904         u8         reserved_at_1f0[0xc];
 905         u8         cqe_version[0x4];
 906
 907         u8         compact_address_vector[0x1];
 908         u8         striding_rq[0x1];
 909         u8         reserved_at_202[0x1];
 910         u8         ipoib_enhanced_offloads[0x1];
 911         u8         ipoib_basic_offloads[0x1];
 912         u8         reserved_at_205[0x5];
 913         u8         umr_fence[0x2];
 914         u8         reserved_at_20c[0x3];
 915         u8         drain_sigerr[0x1];
 916         u8         cmdif_checksum[0x2];
 917         u8         sigerr_cqe[0x1];
 918         u8         reserved_at_213[0x1];
 919         u8         wq_signature[0x1];
 920         u8         sctr_data_cqe[0x1];
 921         u8         reserved_at_216[0x1];
 922         u8         sho[0x1];
 923         u8         tph[0x1];
 924         u8         rf[0x1];
 925         u8         dct[0x1];
 926         u8         qos[0x1];
 927         u8         eth_net_offloads[0x1];
 928         u8         roce[0x1];
 929         u8         atomic[0x1];
 930         u8         reserved_at_21f[0x1];
 931
 932         u8         cq_oi[0x1];
 933         u8         cq_resize[0x1];
 934         u8         cq_moderation[0x1];
 935         u8         reserved_at_223[0x3];
 936         u8         cq_eq_remap[0x1];
 937         u8         pg[0x1];
 938         u8         block_lb_mc[0x1];
 939         u8         reserved_at_229[0x1];
 940         u8         scqe_break_moderation[0x1];
 941         u8         cq_period_start_from_cqe[0x1];
 942         u8         cd[0x1];
 943         u8         reserved_at_22d[0x1];
 944         u8         apm[0x1];
 945         u8         vector_calc[0x1];
 946         u8         umr_ptr_rlky[0x1];
 947         u8         imaicl[0x1];
 948         u8         reserved_at_232[0x4];
 949         u8         qkv[0x1];
 950         u8         pkv[0x1];
 951         u8         set_deth_sqpn[0x1];
 952         u8         reserved_at_239[0x3];
 953         u8         xrc[0x1];
 954         u8         ud[0x1];
 955         u8         uc[0x1];
 956         u8         rc[0x1];
 957
 958         u8         uar_4k[0x1];
 959         u8         reserved_at_241[0x9];
 960         u8         uar_sz[0x6];
 961         u8         reserved_at_250[0x8];
 962         u8         log_pg_sz[0x8];
 963
 964         u8         bf[0x1];
 965         u8         driver_version[0x1];
 966         u8         pad_tx_eth_packet[0x1];
 967         u8         reserved_at_263[0x8];
 968         u8         log_bf_reg_size[0x5];
 969
 970         u8         reserved_at_270[0xb];
 971         u8         lag_master[0x1];
 972         u8         num_lag_ports[0x4];
 973
 974         u8         reserved_at_280[0x10];
 975         u8         max_wqe_sz_sq[0x10];
 976
 977         u8         reserved_at_2a0[0x10];
 978         u8         max_wqe_sz_rq[0x10];
 979
 980         u8         max_flow_counter_31_16[0x10];
 981         u8         max_wqe_sz_sq_dc[0x10];
 982
 983         u8         reserved_at_2e0[0x7];
 984         u8         max_qp_mcg[0x19];
 985
 986         u8         reserved_at_300[0x18];
 987         u8         log_max_mcg[0x8];
 988
 989         u8         reserved_at_320[0x3];
 990         u8         log_max_transport_domain[0x5];
 991         u8         reserved_at_328[0x3];
 992         u8         log_max_pd[0x5];
 993         u8         reserved_at_330[0xb];
 994         u8         log_max_xrcd[0x5];
 995
 996         u8         reserved_at_340[0x8];
 997         u8         log_max_flow_counter_bulk[0x8];
 998         u8         max_flow_counter_15_0[0x10];
 999
1000
1001         u8         reserved_at_360[0x3];
1002         u8         log_max_rq[0x5];
1003         u8         reserved_at_368[0x3];
1004         u8         log_max_sq[0x5];
1005         u8         reserved_at_370[0x3];
1006         u8         log_max_tir[0x5];
1007         u8         reserved_at_378[0x3];
1008         u8         log_max_tis[0x5];
1009
1010         u8         basic_cyclic_rcv_wqe[0x1];
1011         u8         reserved_at_381[0x2];
1012         u8         log_max_rmp[0x5];
1013         u8         reserved_at_388[0x3];
1014         u8         log_max_rqt[0x5];
1015         u8         reserved_at_390[0x3];
1016         u8         log_max_rqt_size[0x5];
1017         u8         reserved_at_398[0x3];
1018         u8         log_max_tis_per_sq[0x5];
1019
1020         u8         reserved_at_3a0[0x3];
1021         u8         log_max_stride_sz_rq[0x5];
1022         u8         reserved_at_3a8[0x3];
1023         u8         log_min_stride_sz_rq[0x5];
1024         u8         reserved_at_3b0[0x3];
1025         u8         log_max_stride_sz_sq[0x5];
1026         u8         reserved_at_3b8[0x3];
1027         u8         log_min_stride_sz_sq[0x5];
1028
1029         u8         hairpin[0x1];
1030         u8         reserved_at_3c1[0x2];
1031         u8         log_max_hairpin_queues[0x5];
1032         u8         reserved_at_3c8[0x3];
1033         u8         log_max_hairpin_wq_data_sz[0x5];
1034         u8         reserved_at_3d0[0x3];
1035         u8         log_max_hairpin_num_packets[0x5];
1036         u8         reserved_at_3d8[0x3];
1037         u8         log_max_wq_sz[0x5];
1038
1039         u8         nic_vport_change_event[0x1];
1040         u8         disable_local_lb_uc[0x1];
1041         u8         disable_local_lb_mc[0x1];
1042         u8         log_min_hairpin_wq_data_sz[0x5];
1043         u8         reserved_at_3e8[0x3];
1044         u8         log_max_vlan_list[0x5];
1045         u8         reserved_at_3f0[0x3];
1046         u8         log_max_current_mc_list[0x5];
1047         u8         reserved_at_3f8[0x3];
1048         u8         log_max_current_uc_list[0x5];
1049
1050         u8         reserved_at_400[0x80];
1051
1052         u8         reserved_at_480[0x3];
1053         u8         log_max_l2_table[0x5];
1054         u8         reserved_at_488[0x8];
1055         u8         log_uar_page_sz[0x10];
1056
1057         u8         reserved_at_4a0[0x20];
1058         u8         device_frequency_mhz[0x20];
1059         u8         device_frequency_khz[0x20];
1060
1061         u8         reserved_at_500[0x20];
1062         u8         num_of_uars_per_page[0x20];
1063         u8         reserved_at_540[0x40];
1064
1065         u8         reserved_at_580[0x3d];
1066         u8         cqe_128_always[0x1];
1067         u8         cqe_compression_128[0x1];
1068         u8         cqe_compression[0x1];
1069
1070         u8         cqe_compression_timeout[0x10];
1071         u8         cqe_compression_max_num[0x10];
1072
1073         u8         reserved_at_5e0[0x10];
1074         u8         tag_matching[0x1];
1075         u8         rndv_offload_rc[0x1];
1076         u8         rndv_offload_dc[0x1];
1077         u8         log_tag_matching_list_sz[0x5];
1078         u8         reserved_at_5f8[0x3];
1079         u8         log_max_xrq[0x5];
1080
1081         u8         affiliate_nic_vport_criteria[0x8];
1082         u8         native_port_num[0x8];
1083         u8         num_vhca_ports[0x8];
1084         u8         reserved_at_618[0x6];
1085         u8         sw_owner_id[0x1];
1086         u8         reserved_at_61f[0x1e1];
1087 };
1088
1089 enum mlx5_flow_destination_type {
1090         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1091         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1092         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1093
1094         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1095 };
1096
1097 struct mlx5_ifc_dest_format_struct_bits {
1098         u8         destination_type[0x8];
1099         u8         destination_id[0x18];
1100
1101         u8         reserved_at_20[0x20];
1102 };
1103
1104 struct mlx5_ifc_flow_counter_list_bits {
1105         u8         flow_counter_id[0x20];
1106
1107         u8         reserved_at_20[0x20];
1108 };
1109
1110 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1111         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1112         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1113         u8         reserved_at_0[0x40];
1114 };
1115
1116 struct mlx5_ifc_fte_match_param_bits {
1117         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1118
1119         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1120
1121         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1122
1123         u8         reserved_at_600[0xa00];
1124 };
1125
1126 enum {
1127         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1128         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1129         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1130         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1131         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1132 };
1133
1134 struct mlx5_ifc_rx_hash_field_select_bits {
1135         u8         l3_prot_type[0x1];
1136         u8         l4_prot_type[0x1];
1137         u8         selected_fields[0x1e];
1138 };
1139
1140 enum {
1141         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1142         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1143 };
1144
1145 enum {
1146         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1147         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1148 };
1149
1150 struct mlx5_ifc_wq_bits {
1151         u8         wq_type[0x4];
1152         u8         wq_signature[0x1];
1153         u8         end_padding_mode[0x2];
1154         u8         cd_slave[0x1];
1155         u8         reserved_at_8[0x18];
1156
1157         u8         hds_skip_first_sge[0x1];
1158         u8         log2_hds_buf_size[0x3];
1159         u8         reserved_at_24[0x7];
1160         u8         page_offset[0x5];
1161         u8         lwm[0x10];
1162
1163         u8         reserved_at_40[0x8];
1164         u8         pd[0x18];
1165
1166         u8         reserved_at_60[0x8];
1167         u8         uar_page[0x18];
1168
1169         u8         dbr_addr[0x40];
1170
1171         u8         hw_counter[0x20];
1172
1173         u8         sw_counter[0x20];
1174
1175         u8         reserved_at_100[0xc];
1176         u8         log_wq_stride[0x4];
1177         u8         reserved_at_110[0x3];
1178         u8         log_wq_pg_sz[0x5];
1179         u8         reserved_at_118[0x3];
1180         u8         log_wq_sz[0x5];
1181
1182         u8         reserved_at_120[0x3];
1183         u8         log_hairpin_num_packets[0x5];
1184         u8         reserved_at_128[0x3];
1185         u8         log_hairpin_data_sz[0x5];
1186         u8         reserved_at_130[0x5];
1187
1188         u8         log_wqe_num_of_strides[0x3];
1189         u8         two_byte_shift_en[0x1];
1190         u8         reserved_at_139[0x4];
1191         u8         log_wqe_stride_size[0x3];
1192
1193         u8         reserved_at_140[0x4c0];
1194
1195         struct mlx5_ifc_cmd_pas_bits pas[0];
1196 };
1197
1198 struct mlx5_ifc_rq_num_bits {
1199         u8         reserved_at_0[0x8];
1200         u8         rq_num[0x18];
1201 };
1202
1203 struct mlx5_ifc_mac_address_layout_bits {
1204         u8         reserved_at_0[0x10];
1205         u8         mac_addr_47_32[0x10];
1206
1207         u8         mac_addr_31_0[0x20];
1208 };
1209
1210 struct mlx5_ifc_vlan_layout_bits {
1211         u8         reserved_at_0[0x14];
1212         u8         vlan[0x0c];
1213
1214         u8         reserved_at_20[0x20];
1215 };
1216
1217 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1218         u8         reserved_at_0[0xa0];
1219
1220         u8         min_time_between_cnps[0x20];
1221
1222         u8         reserved_at_c0[0x12];
1223         u8         cnp_dscp[0x6];
1224         u8         reserved_at_d8[0x4];
1225         u8         cnp_prio_mode[0x1];
1226         u8         cnp_802p_prio[0x3];
1227
1228         u8         reserved_at_e0[0x720];
1229 };
1230
1231 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1232         u8         reserved_at_0[0x60];
1233
1234         u8         reserved_at_60[0x4];
1235         u8         clamp_tgt_rate[0x1];
1236         u8         reserved_at_65[0x3];
1237         u8         clamp_tgt_rate_after_time_inc[0x1];
1238         u8         reserved_at_69[0x17];
1239
1240         u8         reserved_at_80[0x20];
1241
1242         u8         rpg_time_reset[0x20];
1243
1244         u8         rpg_byte_reset[0x20];
1245
1246         u8         rpg_threshold[0x20];
1247
1248         u8         rpg_max_rate[0x20];
1249
1250         u8         rpg_ai_rate[0x20];
1251
1252         u8         rpg_hai_rate[0x20];
1253
1254         u8         rpg_gd[0x20];
1255
1256         u8         rpg_min_dec_fac[0x20];
1257
1258         u8         rpg_min_rate[0x20];
1259
1260         u8         reserved_at_1c0[0xe0];
1261
1262         u8         rate_to_set_on_first_cnp[0x20];
1263
1264         u8         dce_tcp_g[0x20];
1265
1266         u8         dce_tcp_rtt[0x20];
1267
1268         u8         rate_reduce_monitor_period[0x20];
1269
1270         u8         reserved_at_320[0x20];
1271
1272         u8         initial_alpha_value[0x20];
1273
1274         u8         reserved_at_360[0x4a0];
1275 };
1276
1277 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1278         u8         reserved_at_0[0x80];
1279
1280         u8         rppp_max_rps[0x20];
1281
1282         u8         rpg_time_reset[0x20];
1283
1284         u8         rpg_byte_reset[0x20];
1285
1286         u8         rpg_threshold[0x20];
1287
1288         u8         rpg_max_rate[0x20];
1289
1290         u8         rpg_ai_rate[0x20];
1291
1292         u8         rpg_hai_rate[0x20];
1293
1294         u8         rpg_gd[0x20];
1295
1296         u8         rpg_min_dec_fac[0x20];
1297
1298         u8         rpg_min_rate[0x20];
1299
1300         u8         reserved_at_1c0[0x640];
1301 };
1302
1303 enum {
1304         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1305         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1306         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1307 };
1308
1309 struct mlx5_ifc_resize_field_select_bits {
1310         u8         resize_field_select[0x20];
1311 };
1312
1313 enum {
1314         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1315         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1316         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1317         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1318 };
1319
1320 struct mlx5_ifc_modify_field_select_bits {
1321         u8         modify_field_select[0x20];
1322 };
1323
1324 struct mlx5_ifc_field_select_r_roce_np_bits {
1325         u8         field_select_r_roce_np[0x20];
1326 };
1327
1328 struct mlx5_ifc_field_select_r_roce_rp_bits {
1329         u8         field_select_r_roce_rp[0x20];
1330 };
1331
1332 enum {
1333         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1334         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1335         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1336         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1337         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1338         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1339         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1340         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1341         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1342         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1343 };
1344
1345 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1346         u8         field_select_8021qaurp[0x20];
1347 };
1348
1349 struct mlx5_ifc_phys_layer_cntrs_bits {
1350         u8         time_since_last_clear_high[0x20];
1351
1352         u8         time_since_last_clear_low[0x20];
1353
1354         u8         symbol_errors_high[0x20];
1355
1356         u8         symbol_errors_low[0x20];
1357
1358         u8         sync_headers_errors_high[0x20];
1359
1360         u8         sync_headers_errors_low[0x20];
1361
1362         u8         edpl_bip_errors_lane0_high[0x20];
1363
1364         u8         edpl_bip_errors_lane0_low[0x20];
1365
1366         u8         edpl_bip_errors_lane1_high[0x20];
1367
1368         u8         edpl_bip_errors_lane1_low[0x20];
1369
1370         u8         edpl_bip_errors_lane2_high[0x20];
1371
1372         u8         edpl_bip_errors_lane2_low[0x20];
1373
1374         u8         edpl_bip_errors_lane3_high[0x20];
1375
1376         u8         edpl_bip_errors_lane3_low[0x20];
1377
1378         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1379
1380         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1381
1382         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1383
1384         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1385
1386         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1387
1388         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1389
1390         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1391
1392         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1393
1394         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1395
1396         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1397
1398         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1399
1400         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1401
1402         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1403
1404         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1405
1406         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1407
1408         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1409
1410         u8         rs_fec_corrected_blocks_high[0x20];
1411
1412         u8         rs_fec_corrected_blocks_low[0x20];
1413
1414         u8         rs_fec_uncorrectable_blocks_high[0x20];
1415
1416         u8         rs_fec_uncorrectable_blocks_low[0x20];
1417
1418         u8         rs_fec_no_errors_blocks_high[0x20];
1419
1420         u8         rs_fec_no_errors_blocks_low[0x20];
1421
1422         u8         rs_fec_single_error_blocks_high[0x20];
1423
1424         u8         rs_fec_single_error_blocks_low[0x20];
1425
1426         u8         rs_fec_corrected_symbols_total_high[0x20];
1427
1428         u8         rs_fec_corrected_symbols_total_low[0x20];
1429
1430         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1431
1432         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1433
1434         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1435
1436         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1437
1438         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1439
1440         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1441
1442         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1443
1444         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1445
1446         u8         link_down_events[0x20];
1447
1448         u8         successful_recovery_events[0x20];
1449
1450         u8         reserved_at_640[0x180];
1451 };
1452
1453 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1454         u8         time_since_last_clear_high[0x20];
1455
1456         u8         time_since_last_clear_low[0x20];
1457
1458         u8         phy_received_bits_high[0x20];
1459
1460         u8         phy_received_bits_low[0x20];
1461
1462         u8         phy_symbol_errors_high[0x20];
1463
1464         u8         phy_symbol_errors_low[0x20];
1465
1466         u8         phy_corrected_bits_high[0x20];
1467
1468         u8         phy_corrected_bits_low[0x20];
1469
1470         u8         phy_corrected_bits_lane0_high[0x20];
1471
1472         u8         phy_corrected_bits_lane0_low[0x20];
1473
1474         u8         phy_corrected_bits_lane1_high[0x20];
1475
1476         u8         phy_corrected_bits_lane1_low[0x20];
1477
1478         u8         phy_corrected_bits_lane2_high[0x20];
1479
1480         u8         phy_corrected_bits_lane2_low[0x20];
1481
1482         u8         phy_corrected_bits_lane3_high[0x20];
1483
1484         u8         phy_corrected_bits_lane3_low[0x20];
1485
1486         u8         reserved_at_200[0x5c0];
1487 };
1488
1489 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1490         u8         symbol_error_counter[0x10];
1491
1492         u8         link_error_recovery_counter[0x8];
1493
1494         u8         link_downed_counter[0x8];
1495
1496         u8         port_rcv_errors[0x10];
1497
1498         u8         port_rcv_remote_physical_errors[0x10];
1499
1500         u8         port_rcv_switch_relay_errors[0x10];
1501
1502         u8         port_xmit_discards[0x10];
1503
1504         u8         port_xmit_constraint_errors[0x8];
1505
1506         u8         port_rcv_constraint_errors[0x8];
1507
1508         u8         reserved_at_70[0x8];
1509
1510         u8         link_overrun_errors[0x8];
1511
1512         u8         reserved_at_80[0x10];
1513
1514         u8         vl_15_dropped[0x10];
1515
1516         u8         reserved_at_a0[0x80];
1517
1518         u8         port_xmit_wait[0x20];
1519 };
1520
1521 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1522         u8         transmit_queue_high[0x20];
1523
1524         u8         transmit_queue_low[0x20];
1525
1526         u8         reserved_at_40[0x780];
1527 };
1528
1529 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1530         u8         rx_octets_high[0x20];
1531
1532         u8         rx_octets_low[0x20];
1533
1534         u8         reserved_at_40[0xc0];
1535
1536         u8         rx_frames_high[0x20];
1537
1538         u8         rx_frames_low[0x20];
1539
1540         u8         tx_octets_high[0x20];
1541
1542         u8         tx_octets_low[0x20];
1543
1544         u8         reserved_at_180[0xc0];
1545
1546         u8         tx_frames_high[0x20];
1547
1548         u8         tx_frames_low[0x20];
1549
1550         u8         rx_pause_high[0x20];
1551
1552         u8         rx_pause_low[0x20];
1553
1554         u8         rx_pause_duration_high[0x20];
1555
1556         u8         rx_pause_duration_low[0x20];
1557
1558         u8         tx_pause_high[0x20];
1559
1560         u8         tx_pause_low[0x20];
1561
1562         u8         tx_pause_duration_high[0x20];
1563
1564         u8         tx_pause_duration_low[0x20];
1565
1566         u8         rx_pause_transition_high[0x20];
1567
1568         u8         rx_pause_transition_low[0x20];
1569
1570         u8         reserved_at_3c0[0x400];
1571 };
1572
1573 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1574         u8         port_transmit_wait_high[0x20];
1575
1576         u8         port_transmit_wait_low[0x20];
1577
1578         u8         reserved_at_40[0x100];
1579
1580         u8         rx_buffer_almost_full_high[0x20];
1581
1582         u8         rx_buffer_almost_full_low[0x20];
1583
1584         u8         rx_buffer_full_high[0x20];
1585
1586         u8         rx_buffer_full_low[0x20];
1587
1588         u8         reserved_at_1c0[0x600];
1589 };
1590
1591 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1592         u8         dot3stats_alignment_errors_high[0x20];
1593
1594         u8         dot3stats_alignment_errors_low[0x20];
1595
1596         u8         dot3stats_fcs_errors_high[0x20];
1597
1598         u8         dot3stats_fcs_errors_low[0x20];
1599
1600         u8         dot3stats_single_collision_frames_high[0x20];
1601
1602         u8         dot3stats_single_collision_frames_low[0x20];
1603
1604         u8         dot3stats_multiple_collision_frames_high[0x20];
1605
1606         u8         dot3stats_multiple_collision_frames_low[0x20];
1607
1608         u8         dot3stats_sqe_test_errors_high[0x20];
1609
1610         u8         dot3stats_sqe_test_errors_low[0x20];
1611
1612         u8         dot3stats_deferred_transmissions_high[0x20];
1613
1614         u8         dot3stats_deferred_transmissions_low[0x20];
1615
1616         u8         dot3stats_late_collisions_high[0x20];
1617
1618         u8         dot3stats_late_collisions_low[0x20];
1619
1620         u8         dot3stats_excessive_collisions_high[0x20];
1621
1622         u8         dot3stats_excessive_collisions_low[0x20];
1623
1624         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1625
1626         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1627
1628         u8         dot3stats_carrier_sense_errors_high[0x20];
1629
1630         u8         dot3stats_carrier_sense_errors_low[0x20];
1631
1632         u8         dot3stats_frame_too_longs_high[0x20];
1633
1634         u8         dot3stats_frame_too_longs_low[0x20];
1635
1636         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1637
1638         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1639
1640         u8         dot3stats_symbol_errors_high[0x20];
1641
1642         u8         dot3stats_symbol_errors_low[0x20];
1643
1644         u8         dot3control_in_unknown_opcodes_high[0x20];
1645
1646         u8         dot3control_in_unknown_opcodes_low[0x20];
1647
1648         u8         dot3in_pause_frames_high[0x20];
1649
1650         u8         dot3in_pause_frames_low[0x20];
1651
1652         u8         dot3out_pause_frames_high[0x20];
1653
1654         u8         dot3out_pause_frames_low[0x20];
1655
1656         u8         reserved_at_400[0x3c0];
1657 };
1658
1659 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1660         u8         ether_stats_drop_events_high[0x20];
1661
1662         u8         ether_stats_drop_events_low[0x20];
1663
1664         u8         ether_stats_octets_high[0x20];
1665
1666         u8         ether_stats_octets_low[0x20];
1667
1668         u8         ether_stats_pkts_high[0x20];
1669
1670         u8         ether_stats_pkts_low[0x20];
1671
1672         u8         ether_stats_broadcast_pkts_high[0x20];
1673
1674         u8         ether_stats_broadcast_pkts_low[0x20];
1675
1676         u8         ether_stats_multicast_pkts_high[0x20];
1677
1678         u8         ether_stats_multicast_pkts_low[0x20];
1679
1680         u8         ether_stats_crc_align_errors_high[0x20];
1681
1682         u8         ether_stats_crc_align_errors_low[0x20];
1683
1684         u8         ether_stats_undersize_pkts_high[0x20];
1685
1686         u8         ether_stats_undersize_pkts_low[0x20];
1687
1688         u8         ether_stats_oversize_pkts_high[0x20];
1689
1690         u8         ether_stats_oversize_pkts_low[0x20];
1691
1692         u8         ether_stats_fragments_high[0x20];
1693
1694         u8         ether_stats_fragments_low[0x20];
1695
1696         u8         ether_stats_jabbers_high[0x20];
1697
1698         u8         ether_stats_jabbers_low[0x20];
1699
1700         u8         ether_stats_collisions_high[0x20];
1701
1702         u8         ether_stats_collisions_low[0x20];
1703
1704         u8         ether_stats_pkts64octets_high[0x20];
1705
1706         u8         ether_stats_pkts64octets_low[0x20];
1707
1708         u8         ether_stats_pkts65to127octets_high[0x20];
1709
1710         u8         ether_stats_pkts65to127octets_low[0x20];
1711
1712         u8         ether_stats_pkts128to255octets_high[0x20];
1713
1714         u8         ether_stats_pkts128to255octets_low[0x20];
1715
1716         u8         ether_stats_pkts256to511octets_high[0x20];
1717
1718         u8         ether_stats_pkts256to511octets_low[0x20];
1719
1720         u8         ether_stats_pkts512to1023octets_high[0x20];
1721
1722         u8         ether_stats_pkts512to1023octets_low[0x20];
1723
1724         u8         ether_stats_pkts1024to1518octets_high[0x20];
1725
1726         u8         ether_stats_pkts1024to1518octets_low[0x20];
1727
1728         u8         ether_stats_pkts1519to2047octets_high[0x20];
1729
1730         u8         ether_stats_pkts1519to2047octets_low[0x20];
1731
1732         u8         ether_stats_pkts2048to4095octets_high[0x20];
1733
1734         u8         ether_stats_pkts2048to4095octets_low[0x20];
1735
1736         u8         ether_stats_pkts4096to8191octets_high[0x20];
1737
1738         u8         ether_stats_pkts4096to8191octets_low[0x20];
1739
1740         u8         ether_stats_pkts8192to10239octets_high[0x20];
1741
1742         u8         ether_stats_pkts8192to10239octets_low[0x20];
1743
1744         u8         reserved_at_540[0x280];
1745 };
1746
1747 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1748         u8         if_in_octets_high[0x20];
1749
1750         u8         if_in_octets_low[0x20];
1751
1752         u8         if_in_ucast_pkts_high[0x20];
1753
1754         u8         if_in_ucast_pkts_low[0x20];
1755
1756         u8         if_in_discards_high[0x20];
1757
1758         u8         if_in_discards_low[0x20];
1759
1760         u8         if_in_errors_high[0x20];
1761
1762         u8         if_in_errors_low[0x20];
1763
1764         u8         if_in_unknown_protos_high[0x20];
1765
1766         u8         if_in_unknown_protos_low[0x20];
1767
1768         u8         if_out_octets_high[0x20];
1769
1770         u8         if_out_octets_low[0x20];
1771
1772         u8         if_out_ucast_pkts_high[0x20];
1773
1774         u8         if_out_ucast_pkts_low[0x20];
1775
1776         u8         if_out_discards_high[0x20];
1777
1778         u8         if_out_discards_low[0x20];
1779
1780         u8         if_out_errors_high[0x20];
1781
1782         u8         if_out_errors_low[0x20];
1783
1784         u8         if_in_multicast_pkts_high[0x20];
1785
1786         u8         if_in_multicast_pkts_low[0x20];
1787
1788         u8         if_in_broadcast_pkts_high[0x20];
1789
1790         u8         if_in_broadcast_pkts_low[0x20];
1791
1792         u8         if_out_multicast_pkts_high[0x20];
1793
1794         u8         if_out_multicast_pkts_low[0x20];
1795
1796         u8         if_out_broadcast_pkts_high[0x20];
1797
1798         u8         if_out_broadcast_pkts_low[0x20];
1799
1800         u8         reserved_at_340[0x480];
1801 };
1802
1803 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1804         u8         a_frames_transmitted_ok_high[0x20];
1805
1806         u8         a_frames_transmitted_ok_low[0x20];
1807
1808         u8         a_frames_received_ok_high[0x20];
1809
1810         u8         a_frames_received_ok_low[0x20];
1811
1812         u8         a_frame_check_sequence_errors_high[0x20];
1813
1814         u8         a_frame_check_sequence_errors_low[0x20];
1815
1816         u8         a_alignment_errors_high[0x20];
1817
1818         u8         a_alignment_errors_low[0x20];
1819
1820         u8         a_octets_transmitted_ok_high[0x20];
1821
1822         u8         a_octets_transmitted_ok_low[0x20];
1823
1824         u8         a_octets_received_ok_high[0x20];
1825
1826         u8         a_octets_received_ok_low[0x20];
1827
1828         u8         a_multicast_frames_xmitted_ok_high[0x20];
1829
1830         u8         a_multicast_frames_xmitted_ok_low[0x20];
1831
1832         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1833
1834         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1835
1836         u8         a_multicast_frames_received_ok_high[0x20];
1837
1838         u8         a_multicast_frames_received_ok_low[0x20];
1839
1840         u8         a_broadcast_frames_received_ok_high[0x20];
1841
1842         u8         a_broadcast_frames_received_ok_low[0x20];
1843
1844         u8         a_in_range_length_errors_high[0x20];
1845
1846         u8         a_in_range_length_errors_low[0x20];
1847
1848         u8         a_out_of_range_length_field_high[0x20];
1849
1850         u8         a_out_of_range_length_field_low[0x20];
1851
1852         u8         a_frame_too_long_errors_high[0x20];
1853
1854         u8         a_frame_too_long_errors_low[0x20];
1855
1856         u8         a_symbol_error_during_carrier_high[0x20];
1857
1858         u8         a_symbol_error_during_carrier_low[0x20];
1859
1860         u8         a_mac_control_frames_transmitted_high[0x20];
1861
1862         u8         a_mac_control_frames_transmitted_low[0x20];
1863
1864         u8         a_mac_control_frames_received_high[0x20];
1865
1866         u8         a_mac_control_frames_received_low[0x20];
1867
1868         u8         a_unsupported_opcodes_received_high[0x20];
1869
1870         u8         a_unsupported_opcodes_received_low[0x20];
1871
1872         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1873
1874         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1875
1876         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1877
1878         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1879
1880         u8         reserved_at_4c0[0x300];
1881 };
1882
1883 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1884         u8         life_time_counter_high[0x20];
1885
1886         u8         life_time_counter_low[0x20];
1887
1888         u8         rx_errors[0x20];
1889
1890         u8         tx_errors[0x20];
1891
1892         u8         l0_to_recovery_eieos[0x20];
1893
1894         u8         l0_to_recovery_ts[0x20];
1895
1896         u8         l0_to_recovery_framing[0x20];
1897
1898         u8         l0_to_recovery_retrain[0x20];
1899
1900         u8         crc_error_dllp[0x20];
1901
1902         u8         crc_error_tlp[0x20];
1903
1904         u8         tx_overflow_buffer_pkt_high[0x20];
1905
1906         u8         tx_overflow_buffer_pkt_low[0x20];
1907
1908         u8         outbound_stalled_reads[0x20];
1909
1910         u8         outbound_stalled_writes[0x20];
1911
1912         u8         outbound_stalled_reads_events[0x20];
1913
1914         u8         outbound_stalled_writes_events[0x20];
1915
1916         u8         reserved_at_200[0x5c0];
1917 };
1918
1919 struct mlx5_ifc_cmd_inter_comp_event_bits {
1920         u8         command_completion_vector[0x20];
1921
1922         u8         reserved_at_20[0xc0];
1923 };
1924
1925 struct mlx5_ifc_stall_vl_event_bits {
1926         u8         reserved_at_0[0x18];
1927         u8         port_num[0x1];
1928         u8         reserved_at_19[0x3];
1929         u8         vl[0x4];
1930
1931         u8         reserved_at_20[0xa0];
1932 };
1933
1934 struct mlx5_ifc_db_bf_congestion_event_bits {
1935         u8         event_subtype[0x8];
1936         u8         reserved_at_8[0x8];
1937         u8         congestion_level[0x8];
1938         u8         reserved_at_18[0x8];
1939
1940         u8         reserved_at_20[0xa0];
1941 };
1942
1943 struct mlx5_ifc_gpio_event_bits {
1944         u8         reserved_at_0[0x60];
1945
1946         u8         gpio_event_hi[0x20];
1947
1948         u8         gpio_event_lo[0x20];
1949
1950         u8         reserved_at_a0[0x40];
1951 };
1952
1953 struct mlx5_ifc_port_state_change_event_bits {
1954         u8         reserved_at_0[0x40];
1955
1956         u8         port_num[0x4];
1957         u8         reserved_at_44[0x1c];
1958
1959         u8         reserved_at_60[0x80];
1960 };
1961
1962 struct mlx5_ifc_dropped_packet_logged_bits {
1963         u8         reserved_at_0[0xe0];
1964 };
1965
1966 enum {
1967         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1968         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1969 };
1970
1971 struct mlx5_ifc_cq_error_bits {
1972         u8         reserved_at_0[0x8];
1973         u8         cqn[0x18];
1974
1975         u8         reserved_at_20[0x20];
1976
1977         u8         reserved_at_40[0x18];
1978         u8         syndrome[0x8];
1979
1980         u8         reserved_at_60[0x80];
1981 };
1982
1983 struct mlx5_ifc_rdma_page_fault_event_bits {
1984         u8         bytes_committed[0x20];
1985
1986         u8         r_key[0x20];
1987
1988         u8         reserved_at_40[0x10];
1989         u8         packet_len[0x10];
1990
1991         u8         rdma_op_len[0x20];
1992
1993         u8         rdma_va[0x40];
1994
1995         u8         reserved_at_c0[0x5];
1996         u8         rdma[0x1];
1997         u8         write[0x1];
1998         u8         requestor[0x1];
1999         u8         qp_number[0x18];
2000 };
2001
2002 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2003         u8         bytes_committed[0x20];
2004
2005         u8         reserved_at_20[0x10];
2006         u8         wqe_index[0x10];
2007
2008         u8         reserved_at_40[0x10];
2009         u8         len[0x10];
2010
2011         u8         reserved_at_60[0x60];
2012
2013         u8         reserved_at_c0[0x5];
2014         u8         rdma[0x1];
2015         u8         write_read[0x1];
2016         u8         requestor[0x1];
2017         u8         qpn[0x18];
2018 };
2019
2020 struct mlx5_ifc_qp_events_bits {
2021         u8         reserved_at_0[0xa0];
2022
2023         u8         type[0x8];
2024         u8         reserved_at_a8[0x18];
2025
2026         u8         reserved_at_c0[0x8];
2027         u8         qpn_rqn_sqn[0x18];
2028 };
2029
2030 struct mlx5_ifc_dct_events_bits {
2031         u8         reserved_at_0[0xc0];
2032
2033         u8         reserved_at_c0[0x8];
2034         u8         dct_number[0x18];
2035 };
2036
2037 struct mlx5_ifc_comp_event_bits {
2038         u8         reserved_at_0[0xc0];
2039
2040         u8         reserved_at_c0[0x8];
2041         u8         cq_number[0x18];
2042 };
2043
2044 enum {
2045         MLX5_QPC_STATE_RST        = 0x0,
2046         MLX5_QPC_STATE_INIT       = 0x1,
2047         MLX5_QPC_STATE_RTR        = 0x2,
2048         MLX5_QPC_STATE_RTS        = 0x3,
2049         MLX5_QPC_STATE_SQER       = 0x4,
2050         MLX5_QPC_STATE_ERR        = 0x6,
2051         MLX5_QPC_STATE_SQD        = 0x7,
2052         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2053 };
2054
2055 enum {
2056         MLX5_QPC_ST_RC            = 0x0,
2057         MLX5_QPC_ST_UC            = 0x1,
2058         MLX5_QPC_ST_UD            = 0x2,
2059         MLX5_QPC_ST_XRC           = 0x3,
2060         MLX5_QPC_ST_DCI           = 0x5,
2061         MLX5_QPC_ST_QP0           = 0x7,
2062         MLX5_QPC_ST_QP1           = 0x8,
2063         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2064         MLX5_QPC_ST_REG_UMR       = 0xc,
2065 };
2066
2067 enum {
2068         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2069         MLX5_QPC_PM_STATE_REARM     = 0x1,
2070         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2071         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2072 };
2073
2074 enum {
2075         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2076 };
2077
2078 enum {
2079         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2080         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2081 };
2082
2083 enum {
2084         MLX5_QPC_MTU_256_BYTES        = 0x1,
2085         MLX5_QPC_MTU_512_BYTES        = 0x2,
2086         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2087         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2088         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2089         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2090 };
2091
2092 enum {
2093         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2094         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2095         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2096         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2097         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2098         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2099         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2100         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2101 };
2102
2103 enum {
2104         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2105         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2106         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2107 };
2108
2109 enum {
2110         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2111         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2112         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2113 };
2114
2115 struct mlx5_ifc_qpc_bits {
2116         u8         state[0x4];
2117         u8         lag_tx_port_affinity[0x4];
2118         u8         st[0x8];
2119         u8         reserved_at_10[0x3];
2120         u8         pm_state[0x2];
2121         u8         reserved_at_15[0x3];
2122         u8         offload_type[0x4];
2123         u8         end_padding_mode[0x2];
2124         u8         reserved_at_1e[0x2];
2125
2126         u8         wq_signature[0x1];
2127         u8         block_lb_mc[0x1];
2128         u8         atomic_like_write_en[0x1];
2129         u8         latency_sensitive[0x1];
2130         u8         reserved_at_24[0x1];
2131         u8         drain_sigerr[0x1];
2132         u8         reserved_at_26[0x2];
2133         u8         pd[0x18];
2134
2135         u8         mtu[0x3];
2136         u8         log_msg_max[0x5];
2137         u8         reserved_at_48[0x1];
2138         u8         log_rq_size[0x4];
2139         u8         log_rq_stride[0x3];
2140         u8         no_sq[0x1];
2141         u8         log_sq_size[0x4];
2142         u8         reserved_at_55[0x6];
2143         u8         rlky[0x1];
2144         u8         ulp_stateless_offload_mode[0x4];
2145
2146         u8         counter_set_id[0x8];
2147         u8         uar_page[0x18];
2148
2149         u8         reserved_at_80[0x8];
2150         u8         user_index[0x18];
2151
2152         u8         reserved_at_a0[0x3];
2153         u8         log_page_size[0x5];
2154         u8         remote_qpn[0x18];
2155
2156         struct mlx5_ifc_ads_bits primary_address_path;
2157
2158         struct mlx5_ifc_ads_bits secondary_address_path;
2159
2160         u8         log_ack_req_freq[0x4];
2161         u8         reserved_at_384[0x4];
2162         u8         log_sra_max[0x3];
2163         u8         reserved_at_38b[0x2];
2164         u8         retry_count[0x3];
2165         u8         rnr_retry[0x3];
2166         u8         reserved_at_393[0x1];
2167         u8         fre[0x1];
2168         u8         cur_rnr_retry[0x3];
2169         u8         cur_retry_count[0x3];
2170         u8         reserved_at_39b[0x5];
2171
2172         u8         reserved_at_3a0[0x20];
2173
2174         u8         reserved_at_3c0[0x8];
2175         u8         next_send_psn[0x18];
2176
2177         u8         reserved_at_3e0[0x8];
2178         u8         cqn_snd[0x18];
2179
2180         u8         reserved_at_400[0x8];
2181         u8         deth_sqpn[0x18];
2182
2183         u8         reserved_at_420[0x20];
2184
2185         u8         reserved_at_440[0x8];
2186         u8         last_acked_psn[0x18];
2187
2188         u8         reserved_at_460[0x8];
2189         u8         ssn[0x18];
2190
2191         u8         reserved_at_480[0x8];
2192         u8         log_rra_max[0x3];
2193         u8         reserved_at_48b[0x1];
2194         u8         atomic_mode[0x4];
2195         u8         rre[0x1];
2196         u8         rwe[0x1];
2197         u8         rae[0x1];
2198         u8         reserved_at_493[0x1];
2199         u8         page_offset[0x6];
2200         u8         reserved_at_49a[0x3];
2201         u8         cd_slave_receive[0x1];
2202         u8         cd_slave_send[0x1];
2203         u8         cd_master[0x1];
2204
2205         u8         reserved_at_4a0[0x3];
2206         u8         min_rnr_nak[0x5];
2207         u8         next_rcv_psn[0x18];
2208
2209         u8         reserved_at_4c0[0x8];
2210         u8         xrcd[0x18];
2211
2212         u8         reserved_at_4e0[0x8];
2213         u8         cqn_rcv[0x18];
2214
2215         u8         dbr_addr[0x40];
2216
2217         u8         q_key[0x20];
2218
2219         u8         reserved_at_560[0x5];
2220         u8         rq_type[0x3];
2221         u8         srqn_rmpn_xrqn[0x18];
2222
2223         u8         reserved_at_580[0x8];
2224         u8         rmsn[0x18];
2225
2226         u8         hw_sq_wqebb_counter[0x10];
2227         u8         sw_sq_wqebb_counter[0x10];
2228
2229         u8         hw_rq_counter[0x20];
2230
2231         u8         sw_rq_counter[0x20];
2232
2233         u8         reserved_at_600[0x20];
2234
2235         u8         reserved_at_620[0xf];
2236         u8         cgs[0x1];
2237         u8         cs_req[0x8];
2238         u8         cs_res[0x8];
2239
2240         u8         dc_access_key[0x40];
2241
2242         u8         reserved_at_680[0xc0];
2243 };
2244
2245 struct mlx5_ifc_roce_addr_layout_bits {
2246         u8         source_l3_address[16][0x8];
2247
2248         u8         reserved_at_80[0x3];
2249         u8         vlan_valid[0x1];
2250         u8         vlan_id[0xc];
2251         u8         source_mac_47_32[0x10];
2252
2253         u8         source_mac_31_0[0x20];
2254
2255         u8         reserved_at_c0[0x14];
2256         u8         roce_l3_type[0x4];
2257         u8         roce_version[0x8];
2258
2259         u8         reserved_at_e0[0x20];
2260 };
2261
2262 union mlx5_ifc_hca_cap_union_bits {
2263         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2264         struct mlx5_ifc_odp_cap_bits odp_cap;
2265         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2266         struct mlx5_ifc_roce_cap_bits roce_cap;
2267         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2268         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2269         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2270         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2271         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2272         struct mlx5_ifc_qos_cap_bits qos_cap;
2273         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2274         u8         reserved_at_0[0x8000];
2275 };
2276
2277 enum {
2278         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2279         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2280         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2281         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2282         MLX5_FLOW_CONTEXT_ACTION_ENCAP     = 0x10,
2283         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2284         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2285 };
2286
2287 struct mlx5_ifc_flow_context_bits {
2288         u8         reserved_at_0[0x20];
2289
2290         u8         group_id[0x20];
2291
2292         u8         reserved_at_40[0x8];
2293         u8         flow_tag[0x18];
2294
2295         u8         reserved_at_60[0x10];
2296         u8         action[0x10];
2297
2298         u8         reserved_at_80[0x8];
2299         u8         destination_list_size[0x18];
2300
2301         u8         reserved_at_a0[0x8];
2302         u8         flow_counter_list_size[0x18];
2303
2304         u8         encap_id[0x20];
2305
2306         u8         modify_header_id[0x20];
2307
2308         u8         reserved_at_100[0x100];
2309
2310         struct mlx5_ifc_fte_match_param_bits match_value;
2311
2312         u8         reserved_at_1200[0x600];
2313
2314         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2315 };
2316
2317 enum {
2318         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2319         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2320 };
2321
2322 struct mlx5_ifc_xrc_srqc_bits {
2323         u8         state[0x4];
2324         u8         log_xrc_srq_size[0x4];
2325         u8         reserved_at_8[0x18];
2326
2327         u8         wq_signature[0x1];
2328         u8         cont_srq[0x1];
2329         u8         reserved_at_22[0x1];
2330         u8         rlky[0x1];
2331         u8         basic_cyclic_rcv_wqe[0x1];
2332         u8         log_rq_stride[0x3];
2333         u8         xrcd[0x18];
2334
2335         u8         page_offset[0x6];
2336         u8         reserved_at_46[0x2];
2337         u8         cqn[0x18];
2338
2339         u8         reserved_at_60[0x20];
2340
2341         u8         user_index_equal_xrc_srqn[0x1];
2342         u8         reserved_at_81[0x1];
2343         u8         log_page_size[0x6];
2344         u8         user_index[0x18];
2345
2346         u8         reserved_at_a0[0x20];
2347
2348         u8         reserved_at_c0[0x8];
2349         u8         pd[0x18];
2350
2351         u8         lwm[0x10];
2352         u8         wqe_cnt[0x10];
2353
2354         u8         reserved_at_100[0x40];
2355
2356         u8         db_record_addr_h[0x20];
2357
2358         u8         db_record_addr_l[0x1e];
2359         u8         reserved_at_17e[0x2];
2360
2361         u8         reserved_at_180[0x80];
2362 };
2363
2364 struct mlx5_ifc_traffic_counter_bits {
2365         u8         packets[0x40];
2366
2367         u8         octets[0x40];
2368 };
2369
2370 struct mlx5_ifc_tisc_bits {
2371         u8         strict_lag_tx_port_affinity[0x1];
2372         u8         reserved_at_1[0x3];
2373         u8         lag_tx_port_affinity[0x04];
2374
2375         u8         reserved_at_8[0x4];
2376         u8         prio[0x4];
2377         u8         reserved_at_10[0x10];
2378
2379         u8         reserved_at_20[0x100];
2380
2381         u8         reserved_at_120[0x8];
2382         u8         transport_domain[0x18];
2383
2384         u8         reserved_at_140[0x8];
2385         u8         underlay_qpn[0x18];
2386         u8         reserved_at_160[0x3a0];
2387 };
2388
2389 enum {
2390         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2391         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2392 };
2393
2394 enum {
2395         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2396         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2397 };
2398
2399 enum {
2400         MLX5_RX_HASH_FN_NONE           = 0x0,
2401         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2402         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2403 };
2404
2405 enum {
2406         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2407         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2408 };
2409
2410 struct mlx5_ifc_tirc_bits {
2411         u8         reserved_at_0[0x20];
2412
2413         u8         disp_type[0x4];
2414         u8         reserved_at_24[0x1c];
2415
2416         u8         reserved_at_40[0x40];
2417
2418         u8         reserved_at_80[0x4];
2419         u8         lro_timeout_period_usecs[0x10];
2420         u8         lro_enable_mask[0x4];
2421         u8         lro_max_ip_payload_size[0x8];
2422
2423         u8         reserved_at_a0[0x40];
2424
2425         u8         reserved_at_e0[0x8];
2426         u8         inline_rqn[0x18];
2427
2428         u8         rx_hash_symmetric[0x1];
2429         u8         reserved_at_101[0x1];
2430         u8         tunneled_offload_en[0x1];
2431         u8         reserved_at_103[0x5];
2432         u8         indirect_table[0x18];
2433
2434         u8         rx_hash_fn[0x4];
2435         u8         reserved_at_124[0x2];
2436         u8         self_lb_block[0x2];
2437         u8         transport_domain[0x18];
2438
2439         u8         rx_hash_toeplitz_key[10][0x20];
2440
2441         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2442
2443         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2444
2445         u8         reserved_at_2c0[0x4c0];
2446 };
2447
2448 enum {
2449         MLX5_SRQC_STATE_GOOD   = 0x0,
2450         MLX5_SRQC_STATE_ERROR  = 0x1,
2451 };
2452
2453 struct mlx5_ifc_srqc_bits {
2454         u8         state[0x4];
2455         u8         log_srq_size[0x4];
2456         u8         reserved_at_8[0x18];
2457
2458         u8         wq_signature[0x1];
2459         u8         cont_srq[0x1];
2460         u8         reserved_at_22[0x1];
2461         u8         rlky[0x1];
2462         u8         reserved_at_24[0x1];
2463         u8         log_rq_stride[0x3];
2464         u8         xrcd[0x18];
2465
2466         u8         page_offset[0x6];
2467         u8         reserved_at_46[0x2];
2468         u8         cqn[0x18];
2469
2470         u8         reserved_at_60[0x20];
2471
2472         u8         reserved_at_80[0x2];
2473         u8         log_page_size[0x6];
2474         u8         reserved_at_88[0x18];
2475
2476         u8         reserved_at_a0[0x20];
2477
2478         u8         reserved_at_c0[0x8];
2479         u8         pd[0x18];
2480
2481         u8         lwm[0x10];
2482         u8         wqe_cnt[0x10];
2483
2484         u8         reserved_at_100[0x40];
2485
2486         u8         dbr_addr[0x40];
2487
2488         u8         reserved_at_180[0x80];
2489 };
2490
2491 enum {
2492         MLX5_SQC_STATE_RST  = 0x0,
2493         MLX5_SQC_STATE_RDY  = 0x1,
2494         MLX5_SQC_STATE_ERR  = 0x3,
2495 };
2496
2497 struct mlx5_ifc_sqc_bits {
2498         u8         rlky[0x1];
2499         u8         cd_master[0x1];
2500         u8         fre[0x1];
2501         u8         flush_in_error_en[0x1];
2502         u8         allow_multi_pkt_send_wqe[0x1];
2503         u8         min_wqe_inline_mode[0x3];
2504         u8         state[0x4];
2505         u8         reg_umr[0x1];
2506         u8         allow_swp[0x1];
2507         u8         hairpin[0x1];
2508         u8         reserved_at_f[0x11];
2509
2510         u8         reserved_at_20[0x8];
2511         u8         user_index[0x18];
2512
2513         u8         reserved_at_40[0x8];
2514         u8         cqn[0x18];
2515
2516         u8         reserved_at_60[0x8];
2517         u8         hairpin_peer_rq[0x18];
2518
2519         u8         reserved_at_80[0x10];
2520         u8         hairpin_peer_vhca[0x10];
2521
2522         u8         reserved_at_a0[0x50];
2523
2524         u8         packet_pacing_rate_limit_index[0x10];
2525         u8         tis_lst_sz[0x10];
2526         u8         reserved_at_110[0x10];
2527
2528         u8         reserved_at_120[0x40];
2529
2530         u8         reserved_at_160[0x8];
2531         u8         tis_num_0[0x18];
2532
2533         struct mlx5_ifc_wq_bits wq;
2534 };
2535
2536 enum {
2537         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2538         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2539         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2540         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2541 };
2542
2543 struct mlx5_ifc_scheduling_context_bits {
2544         u8         element_type[0x8];
2545         u8         reserved_at_8[0x18];
2546
2547         u8         element_attributes[0x20];
2548
2549         u8         parent_element_id[0x20];
2550
2551         u8         reserved_at_60[0x40];
2552
2553         u8         bw_share[0x20];
2554
2555         u8         max_average_bw[0x20];
2556
2557         u8         reserved_at_e0[0x120];
2558 };
2559
2560 struct mlx5_ifc_rqtc_bits {
2561         u8         reserved_at_0[0xa0];
2562
2563         u8         reserved_at_a0[0x10];
2564         u8         rqt_max_size[0x10];
2565
2566         u8         reserved_at_c0[0x10];
2567         u8         rqt_actual_size[0x10];
2568
2569         u8         reserved_at_e0[0x6a0];
2570
2571         struct mlx5_ifc_rq_num_bits rq_num[0];
2572 };
2573
2574 enum {
2575         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2576         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2577 };
2578
2579 enum {
2580         MLX5_RQC_STATE_RST  = 0x0,
2581         MLX5_RQC_STATE_RDY  = 0x1,
2582         MLX5_RQC_STATE_ERR  = 0x3,
2583 };
2584
2585 struct mlx5_ifc_rqc_bits {
2586         u8         rlky[0x1];
2587         u8         delay_drop_en[0x1];
2588         u8         scatter_fcs[0x1];
2589         u8         vsd[0x1];
2590         u8         mem_rq_type[0x4];
2591         u8         state[0x4];
2592         u8         reserved_at_c[0x1];
2593         u8         flush_in_error_en[0x1];
2594         u8         hairpin[0x1];
2595         u8         reserved_at_f[0x11];
2596
2597         u8         reserved_at_20[0x8];
2598         u8         user_index[0x18];
2599
2600         u8         reserved_at_40[0x8];
2601         u8         cqn[0x18];
2602
2603         u8         counter_set_id[0x8];
2604         u8         reserved_at_68[0x18];
2605
2606         u8         reserved_at_80[0x8];
2607         u8         rmpn[0x18];
2608
2609         u8         reserved_at_a0[0x8];
2610         u8         hairpin_peer_sq[0x18];
2611
2612         u8         reserved_at_c0[0x10];
2613         u8         hairpin_peer_vhca[0x10];
2614
2615         u8         reserved_at_e0[0xa0];
2616
2617         struct mlx5_ifc_wq_bits wq;
2618 };
2619
2620 enum {
2621         MLX5_RMPC_STATE_RDY  = 0x1,
2622         MLX5_RMPC_STATE_ERR  = 0x3,
2623 };
2624
2625 struct mlx5_ifc_rmpc_bits {
2626         u8         reserved_at_0[0x8];
2627         u8         state[0x4];
2628         u8         reserved_at_c[0x14];
2629
2630         u8         basic_cyclic_rcv_wqe[0x1];
2631         u8         reserved_at_21[0x1f];
2632
2633         u8         reserved_at_40[0x140];
2634
2635         struct mlx5_ifc_wq_bits wq;
2636 };
2637
2638 struct mlx5_ifc_nic_vport_context_bits {
2639         u8         reserved_at_0[0x5];
2640         u8         min_wqe_inline_mode[0x3];
2641         u8         reserved_at_8[0x15];
2642         u8         disable_mc_local_lb[0x1];
2643         u8         disable_uc_local_lb[0x1];
2644         u8         roce_en[0x1];
2645
2646         u8         arm_change_event[0x1];
2647         u8         reserved_at_21[0x1a];
2648         u8         event_on_mtu[0x1];
2649         u8         event_on_promisc_change[0x1];
2650         u8         event_on_vlan_change[0x1];
2651         u8         event_on_mc_address_change[0x1];
2652         u8         event_on_uc_address_change[0x1];
2653
2654         u8         reserved_at_40[0xc];
2655
2656         u8         affiliation_criteria[0x4];
2657         u8         affiliated_vhca_id[0x10];
2658
2659         u8         reserved_at_60[0xd0];
2660
2661         u8         mtu[0x10];
2662
2663         u8         system_image_guid[0x40];
2664         u8         port_guid[0x40];
2665         u8         node_guid[0x40];
2666
2667         u8         reserved_at_200[0x140];
2668         u8         qkey_violation_counter[0x10];
2669         u8         reserved_at_350[0x430];
2670
2671         u8         promisc_uc[0x1];
2672         u8         promisc_mc[0x1];
2673         u8         promisc_all[0x1];
2674         u8         reserved_at_783[0x2];
2675         u8         allowed_list_type[0x3];
2676         u8         reserved_at_788[0xc];
2677         u8         allowed_list_size[0xc];
2678
2679         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2680
2681         u8         reserved_at_7e0[0x20];
2682
2683         u8         current_uc_mac_address[0][0x40];
2684 };
2685
2686 enum {
2687         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2688         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2689         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2690         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
2691 };
2692
2693 struct mlx5_ifc_mkc_bits {
2694         u8         reserved_at_0[0x1];
2695         u8         free[0x1];
2696         u8         reserved_at_2[0xd];
2697         u8         small_fence_on_rdma_read_response[0x1];
2698         u8         umr_en[0x1];
2699         u8         a[0x1];
2700         u8         rw[0x1];
2701         u8         rr[0x1];
2702         u8         lw[0x1];
2703         u8         lr[0x1];
2704         u8         access_mode[0x2];
2705         u8         reserved_at_18[0x8];
2706
2707         u8         qpn[0x18];
2708         u8         mkey_7_0[0x8];
2709
2710         u8         reserved_at_40[0x20];
2711
2712         u8         length64[0x1];
2713         u8         bsf_en[0x1];
2714         u8         sync_umr[0x1];
2715         u8         reserved_at_63[0x2];
2716         u8         expected_sigerr_count[0x1];
2717         u8         reserved_at_66[0x1];
2718         u8         en_rinval[0x1];
2719         u8         pd[0x18];
2720
2721         u8         start_addr[0x40];
2722
2723         u8         len[0x40];
2724
2725         u8         bsf_octword_size[0x20];
2726
2727         u8         reserved_at_120[0x80];
2728
2729         u8         translations_octword_size[0x20];
2730
2731         u8         reserved_at_1c0[0x1b];
2732         u8         log_page_size[0x5];
2733
2734         u8         reserved_at_1e0[0x20];
2735 };
2736
2737 struct mlx5_ifc_pkey_bits {
2738         u8         reserved_at_0[0x10];
2739         u8         pkey[0x10];
2740 };
2741
2742 struct mlx5_ifc_array128_auto_bits {
2743         u8         array128_auto[16][0x8];
2744 };
2745
2746 struct mlx5_ifc_hca_vport_context_bits {
2747         u8         field_select[0x20];
2748
2749         u8         reserved_at_20[0xe0];
2750
2751         u8         sm_virt_aware[0x1];
2752         u8         has_smi[0x1];
2753         u8         has_raw[0x1];
2754         u8         grh_required[0x1];
2755         u8         reserved_at_104[0xc];
2756         u8         port_physical_state[0x4];
2757         u8         vport_state_policy[0x4];
2758         u8         port_state[0x4];
2759         u8         vport_state[0x4];
2760
2761         u8         reserved_at_120[0x20];
2762
2763         u8         system_image_guid[0x40];
2764
2765         u8         port_guid[0x40];
2766
2767         u8         node_guid[0x40];
2768
2769         u8         cap_mask1[0x20];
2770
2771         u8         cap_mask1_field_select[0x20];
2772
2773         u8         cap_mask2[0x20];
2774
2775         u8         cap_mask2_field_select[0x20];
2776
2777         u8         reserved_at_280[0x80];
2778
2779         u8         lid[0x10];
2780         u8         reserved_at_310[0x4];
2781         u8         init_type_reply[0x4];
2782         u8         lmc[0x3];
2783         u8         subnet_timeout[0x5];
2784
2785         u8         sm_lid[0x10];
2786         u8         sm_sl[0x4];
2787         u8         reserved_at_334[0xc];
2788
2789         u8         qkey_violation_counter[0x10];
2790         u8         pkey_violation_counter[0x10];
2791
2792         u8         reserved_at_360[0xca0];
2793 };
2794
2795 struct mlx5_ifc_esw_vport_context_bits {
2796         u8         reserved_at_0[0x3];
2797         u8         vport_svlan_strip[0x1];
2798         u8         vport_cvlan_strip[0x1];
2799         u8         vport_svlan_insert[0x1];
2800         u8         vport_cvlan_insert[0x2];
2801         u8         reserved_at_8[0x18];
2802
2803         u8         reserved_at_20[0x20];
2804
2805         u8         svlan_cfi[0x1];
2806         u8         svlan_pcp[0x3];
2807         u8         svlan_id[0xc];
2808         u8         cvlan_cfi[0x1];
2809         u8         cvlan_pcp[0x3];
2810         u8         cvlan_id[0xc];
2811
2812         u8         reserved_at_60[0x7a0];
2813 };
2814
2815 enum {
2816         MLX5_EQC_STATUS_OK                = 0x0,
2817         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2818 };
2819
2820 enum {
2821         MLX5_EQC_ST_ARMED  = 0x9,
2822         MLX5_EQC_ST_FIRED  = 0xa,
2823 };
2824
2825 struct mlx5_ifc_eqc_bits {
2826         u8         status[0x4];
2827         u8         reserved_at_4[0x9];
2828         u8         ec[0x1];
2829         u8         oi[0x1];
2830         u8         reserved_at_f[0x5];
2831         u8         st[0x4];
2832         u8         reserved_at_18[0x8];
2833
2834         u8         reserved_at_20[0x20];
2835
2836         u8         reserved_at_40[0x14];
2837         u8         page_offset[0x6];
2838         u8         reserved_at_5a[0x6];
2839
2840         u8         reserved_at_60[0x3];
2841         u8         log_eq_size[0x5];
2842         u8         uar_page[0x18];
2843
2844         u8         reserved_at_80[0x20];
2845
2846         u8         reserved_at_a0[0x18];
2847         u8         intr[0x8];
2848
2849         u8         reserved_at_c0[0x3];
2850         u8         log_page_size[0x5];
2851         u8         reserved_at_c8[0x18];
2852
2853         u8         reserved_at_e0[0x60];
2854
2855         u8         reserved_at_140[0x8];
2856         u8         consumer_counter[0x18];
2857
2858         u8         reserved_at_160[0x8];
2859         u8         producer_counter[0x18];
2860
2861         u8         reserved_at_180[0x80];
2862 };
2863
2864 enum {
2865         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2866         MLX5_DCTC_STATE_DRAINING  = 0x1,
2867         MLX5_DCTC_STATE_DRAINED   = 0x2,
2868 };
2869
2870 enum {
2871         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2872         MLX5_DCTC_CS_RES_NA         = 0x1,
2873         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2874 };
2875
2876 enum {
2877         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2878         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2879         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2880         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2881         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2882 };
2883
2884 struct mlx5_ifc_dctc_bits {
2885         u8         reserved_at_0[0x4];
2886         u8         state[0x4];
2887         u8         reserved_at_8[0x18];
2888
2889         u8         reserved_at_20[0x8];
2890         u8         user_index[0x18];
2891
2892         u8         reserved_at_40[0x8];
2893         u8         cqn[0x18];
2894
2895         u8         counter_set_id[0x8];
2896         u8         atomic_mode[0x4];
2897         u8         rre[0x1];
2898         u8         rwe[0x1];
2899         u8         rae[0x1];
2900         u8         atomic_like_write_en[0x1];
2901         u8         latency_sensitive[0x1];
2902         u8         rlky[0x1];
2903         u8         free_ar[0x1];
2904         u8         reserved_at_73[0xd];
2905
2906         u8         reserved_at_80[0x8];
2907         u8         cs_res[0x8];
2908         u8         reserved_at_90[0x3];
2909         u8         min_rnr_nak[0x5];
2910         u8         reserved_at_98[0x8];
2911
2912         u8         reserved_at_a0[0x8];
2913         u8         srqn_xrqn[0x18];
2914
2915         u8         reserved_at_c0[0x8];
2916         u8         pd[0x18];
2917
2918         u8         tclass[0x8];
2919         u8         reserved_at_e8[0x4];
2920         u8         flow_label[0x14];
2921
2922         u8         dc_access_key[0x40];
2923
2924         u8         reserved_at_140[0x5];
2925         u8         mtu[0x3];
2926         u8         port[0x8];
2927         u8         pkey_index[0x10];
2928
2929         u8         reserved_at_160[0x8];
2930         u8         my_addr_index[0x8];
2931         u8         reserved_at_170[0x8];
2932         u8         hop_limit[0x8];
2933
2934         u8         dc_access_key_violation_count[0x20];
2935
2936         u8         reserved_at_1a0[0x14];
2937         u8         dei_cfi[0x1];
2938         u8         eth_prio[0x3];
2939         u8         ecn[0x2];
2940         u8         dscp[0x6];
2941
2942         u8         reserved_at_1c0[0x40];
2943 };
2944
2945 enum {
2946         MLX5_CQC_STATUS_OK             = 0x0,
2947         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2948         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2949 };
2950
2951 enum {
2952         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
2953         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
2954 };
2955
2956 enum {
2957         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
2958         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
2959         MLX5_CQC_ST_FIRED                                 = 0xa,
2960 };
2961
2962 enum {
2963         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2964         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2965         MLX5_CQ_PERIOD_NUM_MODES
2966 };
2967
2968 struct mlx5_ifc_cqc_bits {
2969         u8         status[0x4];
2970         u8         reserved_at_4[0x4];
2971         u8         cqe_sz[0x3];
2972         u8         cc[0x1];
2973         u8         reserved_at_c[0x1];
2974         u8         scqe_break_moderation_en[0x1];
2975         u8         oi[0x1];
2976         u8         cq_period_mode[0x2];
2977         u8         cqe_comp_en[0x1];
2978         u8         mini_cqe_res_format[0x2];
2979         u8         st[0x4];
2980         u8         reserved_at_18[0x8];
2981
2982         u8         reserved_at_20[0x20];
2983
2984         u8         reserved_at_40[0x14];
2985         u8         page_offset[0x6];
2986         u8         reserved_at_5a[0x6];
2987
2988         u8         reserved_at_60[0x3];
2989         u8         log_cq_size[0x5];
2990         u8         uar_page[0x18];
2991
2992         u8         reserved_at_80[0x4];
2993         u8         cq_period[0xc];
2994         u8         cq_max_count[0x10];
2995
2996         u8         reserved_at_a0[0x18];
2997         u8         c_eqn[0x8];
2998
2999         u8         reserved_at_c0[0x3];
3000         u8         log_page_size[0x5];
3001         u8         reserved_at_c8[0x18];
3002
3003         u8         reserved_at_e0[0x20];
3004
3005         u8         reserved_at_100[0x8];
3006         u8         last_notified_index[0x18];
3007
3008         u8         reserved_at_120[0x8];
3009         u8         last_solicit_index[0x18];
3010
3011         u8         reserved_at_140[0x8];
3012         u8         consumer_counter[0x18];
3013
3014         u8         reserved_at_160[0x8];
3015         u8         producer_counter[0x18];
3016
3017         u8         reserved_at_180[0x40];
3018
3019         u8         dbr_addr[0x40];
3020 };
3021
3022 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3023         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3024         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3025         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3026         u8         reserved_at_0[0x800];
3027 };
3028
3029 struct mlx5_ifc_query_adapter_param_block_bits {
3030         u8         reserved_at_0[0xc0];
3031
3032         u8         reserved_at_c0[0x8];
3033         u8         ieee_vendor_id[0x18];
3034
3035         u8         reserved_at_e0[0x10];
3036         u8         vsd_vendor_id[0x10];
3037
3038         u8         vsd[208][0x8];
3039
3040         u8         vsd_contd_psid[16][0x8];
3041 };
3042
3043 enum {
3044         MLX5_XRQC_STATE_GOOD   = 0x0,
3045         MLX5_XRQC_STATE_ERROR  = 0x1,
3046 };
3047
3048 enum {
3049         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3050         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3051 };
3052
3053 enum {
3054         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3055 };
3056
3057 struct mlx5_ifc_tag_matching_topology_context_bits {
3058         u8         log_matching_list_sz[0x4];
3059         u8         reserved_at_4[0xc];
3060         u8         append_next_index[0x10];
3061
3062         u8         sw_phase_cnt[0x10];
3063         u8         hw_phase_cnt[0x10];
3064
3065         u8         reserved_at_40[0x40];
3066 };
3067
3068 struct mlx5_ifc_xrqc_bits {
3069         u8         state[0x4];
3070         u8         rlkey[0x1];
3071         u8         reserved_at_5[0xf];
3072         u8         topology[0x4];
3073         u8         reserved_at_18[0x4];
3074         u8         offload[0x4];
3075
3076         u8         reserved_at_20[0x8];
3077         u8         user_index[0x18];
3078
3079         u8         reserved_at_40[0x8];
3080         u8         cqn[0x18];
3081
3082         u8         reserved_at_60[0xa0];
3083
3084         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3085
3086         u8         reserved_at_180[0x280];
3087
3088         struct mlx5_ifc_wq_bits wq;
3089 };
3090
3091 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3092         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3093         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3094         u8         reserved_at_0[0x20];
3095 };
3096
3097 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3098         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3099         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3100         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3101         u8         reserved_at_0[0x20];
3102 };
3103
3104 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3105         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3106         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3107         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3108         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3109         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3110         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3111         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3112         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3113         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3114         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3115         u8         reserved_at_0[0x7c0];
3116 };
3117
3118 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3119         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3120         u8         reserved_at_0[0x7c0];
3121 };
3122
3123 union mlx5_ifc_event_auto_bits {
3124         struct mlx5_ifc_comp_event_bits comp_event;
3125         struct mlx5_ifc_dct_events_bits dct_events;
3126         struct mlx5_ifc_qp_events_bits qp_events;
3127         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3128         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3129         struct mlx5_ifc_cq_error_bits cq_error;
3130         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3131         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3132         struct mlx5_ifc_gpio_event_bits gpio_event;
3133         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3134         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3135         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3136         u8         reserved_at_0[0xe0];
3137 };
3138
3139 struct mlx5_ifc_health_buffer_bits {
3140         u8         reserved_at_0[0x100];
3141
3142         u8         assert_existptr[0x20];
3143
3144         u8         assert_callra[0x20];
3145
3146         u8         reserved_at_140[0x40];
3147
3148         u8         fw_version[0x20];
3149
3150         u8         hw_id[0x20];
3151
3152         u8         reserved_at_1c0[0x20];
3153
3154         u8         irisc_index[0x8];
3155         u8         synd[0x8];
3156         u8         ext_synd[0x10];
3157 };
3158
3159 struct mlx5_ifc_register_loopback_control_bits {
3160         u8         no_lb[0x1];
3161         u8         reserved_at_1[0x7];
3162         u8         port[0x8];
3163         u8         reserved_at_10[0x10];
3164
3165         u8         reserved_at_20[0x60];
3166 };
3167
3168 struct mlx5_ifc_vport_tc_element_bits {
3169         u8         traffic_class[0x4];
3170         u8         reserved_at_4[0xc];
3171         u8         vport_number[0x10];
3172 };
3173
3174 struct mlx5_ifc_vport_element_bits {
3175         u8         reserved_at_0[0x10];
3176         u8         vport_number[0x10];
3177 };
3178
3179 enum {
3180         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3181         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3182         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3183 };
3184
3185 struct mlx5_ifc_tsar_element_bits {
3186         u8         reserved_at_0[0x8];
3187         u8         tsar_type[0x8];
3188         u8         reserved_at_10[0x10];
3189 };
3190
3191 enum {
3192         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3193         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3194 };
3195
3196 struct mlx5_ifc_teardown_hca_out_bits {
3197         u8         status[0x8];
3198         u8         reserved_at_8[0x18];
3199
3200         u8         syndrome[0x20];
3201
3202         u8         reserved_at_40[0x3f];
3203
3204         u8         force_state[0x1];
3205 };
3206
3207 enum {
3208         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3209         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3210 };
3211
3212 struct mlx5_ifc_teardown_hca_in_bits {
3213         u8         opcode[0x10];
3214         u8         reserved_at_10[0x10];
3215
3216         u8         reserved_at_20[0x10];
3217         u8         op_mod[0x10];
3218
3219         u8         reserved_at_40[0x10];
3220         u8         profile[0x10];
3221
3222         u8         reserved_at_60[0x20];
3223 };
3224
3225 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3226         u8         status[0x8];
3227         u8         reserved_at_8[0x18];
3228
3229         u8         syndrome[0x20];
3230
3231         u8         reserved_at_40[0x40];
3232 };
3233
3234 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3235         u8         opcode[0x10];
3236         u8         reserved_at_10[0x10];
3237
3238         u8         reserved_at_20[0x10];
3239         u8         op_mod[0x10];
3240
3241         u8         reserved_at_40[0x8];
3242         u8         qpn[0x18];
3243
3244         u8         reserved_at_60[0x20];
3245
3246         u8         opt_param_mask[0x20];
3247
3248         u8         reserved_at_a0[0x20];
3249
3250         struct mlx5_ifc_qpc_bits qpc;
3251
3252         u8         reserved_at_800[0x80];
3253 };
3254
3255 struct mlx5_ifc_sqd2rts_qp_out_bits {
3256         u8         status[0x8];
3257         u8         reserved_at_8[0x18];
3258
3259         u8         syndrome[0x20];
3260
3261         u8         reserved_at_40[0x40];
3262 };
3263
3264 struct mlx5_ifc_sqd2rts_qp_in_bits {
3265         u8         opcode[0x10];
3266         u8         reserved_at_10[0x10];
3267
3268         u8         reserved_at_20[0x10];
3269         u8         op_mod[0x10];
3270
3271         u8         reserved_at_40[0x8];
3272         u8         qpn[0x18];
3273
3274         u8         reserved_at_60[0x20];
3275
3276         u8         opt_param_mask[0x20];
3277
3278         u8         reserved_at_a0[0x20];
3279
3280         struct mlx5_ifc_qpc_bits qpc;
3281
3282         u8         reserved_at_800[0x80];
3283 };
3284
3285 struct mlx5_ifc_set_roce_address_out_bits {
3286         u8         status[0x8];
3287         u8         reserved_at_8[0x18];
3288
3289         u8         syndrome[0x20];
3290
3291         u8         reserved_at_40[0x40];
3292 };
3293
3294 struct mlx5_ifc_set_roce_address_in_bits {
3295         u8         opcode[0x10];
3296         u8         reserved_at_10[0x10];
3297
3298         u8         reserved_at_20[0x10];
3299         u8         op_mod[0x10];
3300
3301         u8         roce_address_index[0x10];
3302         u8         reserved_at_50[0xc];
3303         u8         vhca_port_num[0x4];
3304
3305         u8         reserved_at_60[0x20];
3306
3307         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3308 };
3309
3310 struct mlx5_ifc_set_mad_demux_out_bits {
3311         u8         status[0x8];
3312         u8         reserved_at_8[0x18];
3313
3314         u8         syndrome[0x20];
3315
3316         u8         reserved_at_40[0x40];
3317 };
3318
3319 enum {
3320         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3321         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3322 };
3323
3324 struct mlx5_ifc_set_mad_demux_in_bits {
3325         u8         opcode[0x10];
3326         u8         reserved_at_10[0x10];
3327
3328         u8         reserved_at_20[0x10];
3329         u8         op_mod[0x10];
3330
3331         u8         reserved_at_40[0x20];
3332
3333         u8         reserved_at_60[0x6];
3334         u8         demux_mode[0x2];
3335         u8         reserved_at_68[0x18];
3336 };
3337
3338 struct mlx5_ifc_set_l2_table_entry_out_bits {
3339         u8         status[0x8];
3340         u8         reserved_at_8[0x18];
3341
3342         u8         syndrome[0x20];
3343
3344         u8         reserved_at_40[0x40];
3345 };
3346
3347 struct mlx5_ifc_set_l2_table_entry_in_bits {
3348         u8         opcode[0x10];
3349         u8         reserved_at_10[0x10];
3350
3351         u8         reserved_at_20[0x10];
3352         u8         op_mod[0x10];
3353
3354         u8         reserved_at_40[0x60];
3355
3356         u8         reserved_at_a0[0x8];
3357         u8         table_index[0x18];
3358
3359         u8         reserved_at_c0[0x20];
3360
3361         u8         reserved_at_e0[0x13];
3362         u8         vlan_valid[0x1];
3363         u8         vlan[0xc];
3364
3365         struct mlx5_ifc_mac_address_layout_bits mac_address;
3366
3367         u8         reserved_at_140[0xc0];
3368 };
3369
3370 struct mlx5_ifc_set_issi_out_bits {
3371         u8         status[0x8];
3372         u8         reserved_at_8[0x18];
3373
3374         u8         syndrome[0x20];
3375
3376         u8         reserved_at_40[0x40];
3377 };
3378
3379 struct mlx5_ifc_set_issi_in_bits {
3380         u8         opcode[0x10];
3381         u8         reserved_at_10[0x10];
3382
3383         u8         reserved_at_20[0x10];
3384         u8         op_mod[0x10];
3385
3386         u8         reserved_at_40[0x10];
3387         u8         current_issi[0x10];
3388
3389         u8         reserved_at_60[0x20];
3390 };
3391
3392 struct mlx5_ifc_set_hca_cap_out_bits {
3393         u8         status[0x8];
3394         u8         reserved_at_8[0x18];
3395
3396         u8         syndrome[0x20];
3397
3398         u8         reserved_at_40[0x40];
3399 };
3400
3401 struct mlx5_ifc_set_hca_cap_in_bits {
3402         u8         opcode[0x10];
3403         u8         reserved_at_10[0x10];
3404
3405         u8         reserved_at_20[0x10];
3406         u8         op_mod[0x10];
3407
3408         u8         reserved_at_40[0x40];
3409
3410         union mlx5_ifc_hca_cap_union_bits capability;
3411 };
3412
3413 enum {
3414         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
3415         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
3416         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
3417         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
3418 };
3419
3420 struct mlx5_ifc_set_fte_out_bits {
3421         u8         status[0x8];
3422         u8         reserved_at_8[0x18];
3423
3424         u8         syndrome[0x20];
3425
3426         u8         reserved_at_40[0x40];
3427 };
3428
3429 struct mlx5_ifc_set_fte_in_bits {
3430         u8         opcode[0x10];
3431         u8         reserved_at_10[0x10];
3432
3433         u8         reserved_at_20[0x10];
3434         u8         op_mod[0x10];
3435
3436         u8         other_vport[0x1];
3437         u8         reserved_at_41[0xf];
3438         u8         vport_number[0x10];
3439
3440         u8         reserved_at_60[0x20];
3441
3442         u8         table_type[0x8];
3443         u8         reserved_at_88[0x18];
3444
3445         u8         reserved_at_a0[0x8];
3446         u8         table_id[0x18];
3447
3448         u8         reserved_at_c0[0x18];
3449         u8         modify_enable_mask[0x8];
3450
3451         u8         reserved_at_e0[0x20];
3452
3453         u8         flow_index[0x20];
3454
3455         u8         reserved_at_120[0xe0];
3456
3457         struct mlx5_ifc_flow_context_bits flow_context;
3458 };
3459
3460 struct mlx5_ifc_rts2rts_qp_out_bits {
3461         u8         status[0x8];
3462         u8         reserved_at_8[0x18];
3463
3464         u8         syndrome[0x20];
3465
3466         u8         reserved_at_40[0x40];
3467 };
3468
3469 struct mlx5_ifc_rts2rts_qp_in_bits {
3470         u8         opcode[0x10];
3471         u8         reserved_at_10[0x10];
3472
3473         u8         reserved_at_20[0x10];
3474         u8         op_mod[0x10];
3475
3476         u8         reserved_at_40[0x8];
3477         u8         qpn[0x18];
3478
3479         u8         reserved_at_60[0x20];
3480
3481         u8         opt_param_mask[0x20];
3482
3483         u8         reserved_at_a0[0x20];
3484
3485         struct mlx5_ifc_qpc_bits qpc;
3486
3487         u8         reserved_at_800[0x80];
3488 };
3489
3490 struct mlx5_ifc_rtr2rts_qp_out_bits {
3491         u8         status[0x8];
3492         u8         reserved_at_8[0x18];
3493
3494         u8         syndrome[0x20];
3495
3496         u8         reserved_at_40[0x40];
3497 };
3498
3499 struct mlx5_ifc_rtr2rts_qp_in_bits {
3500         u8         opcode[0x10];
3501         u8         reserved_at_10[0x10];
3502
3503         u8         reserved_at_20[0x10];
3504         u8         op_mod[0x10];
3505
3506         u8         reserved_at_40[0x8];
3507         u8         qpn[0x18];
3508
3509         u8         reserved_at_60[0x20];
3510
3511         u8         opt_param_mask[0x20];
3512
3513         u8         reserved_at_a0[0x20];
3514
3515         struct mlx5_ifc_qpc_bits qpc;
3516
3517         u8         reserved_at_800[0x80];
3518 };
3519
3520 struct mlx5_ifc_rst2init_qp_out_bits {
3521         u8         status[0x8];
3522         u8         reserved_at_8[0x18];
3523
3524         u8         syndrome[0x20];
3525
3526         u8         reserved_at_40[0x40];
3527 };
3528
3529 struct mlx5_ifc_rst2init_qp_in_bits {
3530         u8         opcode[0x10];
3531         u8         reserved_at_10[0x10];
3532
3533         u8         reserved_at_20[0x10];
3534         u8         op_mod[0x10];
3535
3536         u8         reserved_at_40[0x8];
3537         u8         qpn[0x18];
3538
3539         u8         reserved_at_60[0x20];
3540
3541         u8         opt_param_mask[0x20];
3542
3543         u8         reserved_at_a0[0x20];
3544
3545         struct mlx5_ifc_qpc_bits qpc;
3546
3547         u8         reserved_at_800[0x80];
3548 };
3549
3550 struct mlx5_ifc_query_xrq_out_bits {
3551         u8         status[0x8];
3552         u8         reserved_at_8[0x18];
3553
3554         u8         syndrome[0x20];
3555
3556         u8         reserved_at_40[0x40];
3557
3558         struct mlx5_ifc_xrqc_bits xrq_context;
3559 };
3560
3561 struct mlx5_ifc_query_xrq_in_bits {
3562         u8         opcode[0x10];
3563         u8         reserved_at_10[0x10];
3564
3565         u8         reserved_at_20[0x10];
3566         u8         op_mod[0x10];
3567
3568         u8         reserved_at_40[0x8];
3569         u8         xrqn[0x18];
3570
3571         u8         reserved_at_60[0x20];
3572 };
3573
3574 struct mlx5_ifc_query_xrc_srq_out_bits {
3575         u8         status[0x8];
3576         u8         reserved_at_8[0x18];
3577
3578         u8         syndrome[0x20];
3579
3580         u8         reserved_at_40[0x40];
3581
3582         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3583
3584         u8         reserved_at_280[0x600];
3585
3586         u8         pas[0][0x40];
3587 };
3588
3589 struct mlx5_ifc_query_xrc_srq_in_bits {
3590         u8         opcode[0x10];
3591         u8         reserved_at_10[0x10];
3592
3593         u8         reserved_at_20[0x10];
3594         u8         op_mod[0x10];
3595
3596         u8         reserved_at_40[0x8];
3597         u8         xrc_srqn[0x18];
3598
3599         u8         reserved_at_60[0x20];
3600 };
3601
3602 enum {
3603         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3604         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3605 };
3606
3607 struct mlx5_ifc_query_vport_state_out_bits {
3608         u8         status[0x8];
3609         u8         reserved_at_8[0x18];
3610
3611         u8         syndrome[0x20];
3612
3613         u8         reserved_at_40[0x20];
3614
3615         u8         reserved_at_60[0x18];
3616         u8         admin_state[0x4];
3617         u8         state[0x4];
3618 };
3619
3620 enum {
3621         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3622         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3623 };
3624
3625 struct mlx5_ifc_query_vport_state_in_bits {
3626         u8         opcode[0x10];
3627         u8         reserved_at_10[0x10];
3628
3629         u8         reserved_at_20[0x10];
3630         u8         op_mod[0x10];
3631
3632         u8         other_vport[0x1];
3633         u8         reserved_at_41[0xf];
3634         u8         vport_number[0x10];
3635
3636         u8         reserved_at_60[0x20];
3637 };
3638
3639 struct mlx5_ifc_query_vport_counter_out_bits {
3640         u8         status[0x8];
3641         u8         reserved_at_8[0x18];
3642
3643         u8         syndrome[0x20];
3644
3645         u8         reserved_at_40[0x40];
3646
3647         struct mlx5_ifc_traffic_counter_bits received_errors;
3648
3649         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3650
3651         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3652
3653         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3654
3655         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3656
3657         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3658
3659         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3660
3661         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3662
3663         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3664
3665         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3666
3667         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3668
3669         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3670
3671         u8         reserved_at_680[0xa00];
3672 };
3673
3674 enum {
3675         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3676 };
3677
3678 struct mlx5_ifc_query_vport_counter_in_bits {
3679         u8         opcode[0x10];
3680         u8         reserved_at_10[0x10];
3681
3682         u8         reserved_at_20[0x10];
3683         u8         op_mod[0x10];
3684
3685         u8         other_vport[0x1];
3686         u8         reserved_at_41[0xb];
3687         u8         port_num[0x4];
3688         u8         vport_number[0x10];
3689
3690         u8         reserved_at_60[0x60];
3691
3692         u8         clear[0x1];
3693         u8         reserved_at_c1[0x1f];
3694
3695         u8         reserved_at_e0[0x20];
3696 };
3697
3698 struct mlx5_ifc_query_tis_out_bits {
3699         u8         status[0x8];
3700         u8         reserved_at_8[0x18];
3701
3702         u8         syndrome[0x20];
3703
3704         u8         reserved_at_40[0x40];
3705
3706         struct mlx5_ifc_tisc_bits tis_context;
3707 };
3708
3709 struct mlx5_ifc_query_tis_in_bits {
3710         u8         opcode[0x10];
3711         u8         reserved_at_10[0x10];
3712
3713         u8         reserved_at_20[0x10];
3714         u8         op_mod[0x10];
3715
3716         u8         reserved_at_40[0x8];
3717         u8         tisn[0x18];
3718
3719         u8         reserved_at_60[0x20];
3720 };
3721
3722 struct mlx5_ifc_query_tir_out_bits {
3723         u8         status[0x8];
3724         u8         reserved_at_8[0x18];
3725
3726         u8         syndrome[0x20];
3727
3728         u8         reserved_at_40[0xc0];
3729
3730         struct mlx5_ifc_tirc_bits tir_context;
3731 };
3732
3733 struct mlx5_ifc_query_tir_in_bits {
3734         u8         opcode[0x10];
3735         u8         reserved_at_10[0x10];
3736
3737         u8         reserved_at_20[0x10];
3738         u8         op_mod[0x10];
3739
3740         u8         reserved_at_40[0x8];
3741         u8         tirn[0x18];
3742
3743         u8         reserved_at_60[0x20];
3744 };
3745
3746 struct mlx5_ifc_query_srq_out_bits {
3747         u8         status[0x8];
3748         u8         reserved_at_8[0x18];
3749
3750         u8         syndrome[0x20];
3751
3752         u8         reserved_at_40[0x40];
3753
3754         struct mlx5_ifc_srqc_bits srq_context_entry;
3755
3756         u8         reserved_at_280[0x600];
3757
3758         u8         pas[0][0x40];
3759 };
3760
3761 struct mlx5_ifc_query_srq_in_bits {
3762         u8         opcode[0x10];
3763         u8         reserved_at_10[0x10];
3764
3765         u8         reserved_at_20[0x10];
3766         u8         op_mod[0x10];
3767
3768         u8         reserved_at_40[0x8];
3769         u8         srqn[0x18];
3770
3771         u8         reserved_at_60[0x20];
3772 };
3773
3774 struct mlx5_ifc_query_sq_out_bits {
3775         u8         status[0x8];
3776         u8         reserved_at_8[0x18];
3777
3778         u8         syndrome[0x20];
3779
3780         u8         reserved_at_40[0xc0];
3781
3782         struct mlx5_ifc_sqc_bits sq_context;
3783 };
3784
3785 struct mlx5_ifc_query_sq_in_bits {
3786         u8         opcode[0x10];
3787         u8         reserved_at_10[0x10];
3788
3789         u8         reserved_at_20[0x10];
3790         u8         op_mod[0x10];
3791
3792         u8         reserved_at_40[0x8];
3793         u8         sqn[0x18];
3794
3795         u8         reserved_at_60[0x20];
3796 };
3797
3798 struct mlx5_ifc_query_special_contexts_out_bits {
3799         u8         status[0x8];
3800         u8         reserved_at_8[0x18];
3801
3802         u8         syndrome[0x20];
3803
3804         u8         dump_fill_mkey[0x20];
3805
3806         u8         resd_lkey[0x20];
3807
3808         u8         null_mkey[0x20];
3809
3810         u8         reserved_at_a0[0x60];
3811 };
3812
3813 struct mlx5_ifc_query_special_contexts_in_bits {
3814         u8         opcode[0x10];
3815         u8         reserved_at_10[0x10];
3816
3817         u8         reserved_at_20[0x10];
3818         u8         op_mod[0x10];
3819
3820         u8         reserved_at_40[0x40];
3821 };
3822
3823 struct mlx5_ifc_query_scheduling_element_out_bits {
3824         u8         opcode[0x10];
3825         u8         reserved_at_10[0x10];
3826
3827         u8         reserved_at_20[0x10];
3828         u8         op_mod[0x10];
3829
3830         u8         reserved_at_40[0xc0];
3831
3832         struct mlx5_ifc_scheduling_context_bits scheduling_context;
3833
3834         u8         reserved_at_300[0x100];
3835 };
3836
3837 enum {
3838         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3839 };
3840
3841 struct mlx5_ifc_query_scheduling_element_in_bits {
3842         u8         opcode[0x10];
3843         u8         reserved_at_10[0x10];
3844
3845         u8         reserved_at_20[0x10];
3846         u8         op_mod[0x10];
3847
3848         u8         scheduling_hierarchy[0x8];
3849         u8         reserved_at_48[0x18];
3850
3851         u8         scheduling_element_id[0x20];
3852
3853         u8         reserved_at_80[0x180];
3854 };
3855
3856 struct mlx5_ifc_query_rqt_out_bits {
3857         u8         status[0x8];
3858         u8         reserved_at_8[0x18];
3859
3860         u8         syndrome[0x20];
3861
3862         u8         reserved_at_40[0xc0];
3863
3864         struct mlx5_ifc_rqtc_bits rqt_context;
3865 };
3866
3867 struct mlx5_ifc_query_rqt_in_bits {
3868         u8         opcode[0x10];
3869         u8         reserved_at_10[0x10];
3870
3871         u8         reserved_at_20[0x10];
3872         u8         op_mod[0x10];
3873
3874         u8         reserved_at_40[0x8];
3875         u8         rqtn[0x18];
3876
3877         u8         reserved_at_60[0x20];
3878 };
3879
3880 struct mlx5_ifc_query_rq_out_bits {
3881         u8         status[0x8];
3882         u8         reserved_at_8[0x18];
3883
3884         u8         syndrome[0x20];
3885
3886         u8         reserved_at_40[0xc0];
3887
3888         struct mlx5_ifc_rqc_bits rq_context;
3889 };
3890
3891 struct mlx5_ifc_query_rq_in_bits {
3892         u8         opcode[0x10];
3893         u8         reserved_at_10[0x10];
3894
3895         u8         reserved_at_20[0x10];
3896         u8         op_mod[0x10];
3897
3898         u8         reserved_at_40[0x8];
3899         u8         rqn[0x18];
3900
3901         u8         reserved_at_60[0x20];
3902 };
3903
3904 struct mlx5_ifc_query_roce_address_out_bits {
3905         u8         status[0x8];
3906         u8         reserved_at_8[0x18];
3907
3908         u8         syndrome[0x20];
3909
3910         u8         reserved_at_40[0x40];
3911
3912         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3913 };
3914
3915 struct mlx5_ifc_query_roce_address_in_bits {
3916         u8         opcode[0x10];
3917         u8         reserved_at_10[0x10];
3918
3919         u8         reserved_at_20[0x10];
3920         u8         op_mod[0x10];
3921
3922         u8         roce_address_index[0x10];
3923         u8         reserved_at_50[0xc];
3924         u8         vhca_port_num[0x4];
3925
3926         u8         reserved_at_60[0x20];
3927 };
3928
3929 struct mlx5_ifc_query_rmp_out_bits {
3930         u8         status[0x8];
3931         u8         reserved_at_8[0x18];
3932
3933         u8         syndrome[0x20];
3934
3935         u8         reserved_at_40[0xc0];
3936
3937         struct mlx5_ifc_rmpc_bits rmp_context;
3938 };
3939
3940 struct mlx5_ifc_query_rmp_in_bits {
3941         u8         opcode[0x10];
3942         u8         reserved_at_10[0x10];
3943
3944         u8         reserved_at_20[0x10];
3945         u8         op_mod[0x10];
3946
3947         u8         reserved_at_40[0x8];
3948         u8         rmpn[0x18];
3949
3950         u8         reserved_at_60[0x20];
3951 };
3952
3953 struct mlx5_ifc_query_qp_out_bits {
3954         u8         status[0x8];
3955         u8         reserved_at_8[0x18];
3956
3957         u8         syndrome[0x20];
3958
3959         u8         reserved_at_40[0x40];
3960
3961         u8         opt_param_mask[0x20];
3962
3963         u8         reserved_at_a0[0x20];
3964
3965         struct mlx5_ifc_qpc_bits qpc;
3966
3967         u8         reserved_at_800[0x80];
3968
3969         u8         pas[0][0x40];
3970 };
3971
3972 struct mlx5_ifc_query_qp_in_bits {
3973         u8         opcode[0x10];
3974         u8         reserved_at_10[0x10];
3975
3976         u8         reserved_at_20[0x10];
3977         u8         op_mod[0x10];
3978
3979         u8         reserved_at_40[0x8];
3980         u8         qpn[0x18];
3981
3982         u8         reserved_at_60[0x20];
3983 };
3984
3985 struct mlx5_ifc_query_q_counter_out_bits {
3986         u8         status[0x8];
3987         u8         reserved_at_8[0x18];
3988
3989         u8         syndrome[0x20];
3990
3991         u8         reserved_at_40[0x40];
3992
3993         u8         rx_write_requests[0x20];
3994
3995         u8         reserved_at_a0[0x20];
3996
3997         u8         rx_read_requests[0x20];
3998
3999         u8         reserved_at_e0[0x20];
4000
4001         u8         rx_atomic_requests[0x20];
4002
4003         u8         reserved_at_120[0x20];
4004
4005         u8         rx_dct_connect[0x20];
4006
4007         u8         reserved_at_160[0x20];
4008
4009         u8         out_of_buffer[0x20];
4010
4011         u8         reserved_at_1a0[0x20];
4012
4013         u8         out_of_sequence[0x20];
4014
4015         u8         reserved_at_1e0[0x20];
4016
4017         u8         duplicate_request[0x20];
4018
4019         u8         reserved_at_220[0x20];
4020
4021         u8         rnr_nak_retry_err[0x20];
4022
4023         u8         reserved_at_260[0x20];
4024
4025         u8         packet_seq_err[0x20];
4026
4027         u8         reserved_at_2a0[0x20];
4028
4029         u8         implied_nak_seq_err[0x20];
4030
4031         u8         reserved_at_2e0[0x20];
4032
4033         u8         local_ack_timeout_err[0x20];
4034
4035         u8         reserved_at_320[0xa0];
4036
4037         u8         resp_local_length_error[0x20];
4038
4039         u8         req_local_length_error[0x20];
4040
4041         u8         resp_local_qp_error[0x20];
4042
4043         u8         local_operation_error[0x20];
4044
4045         u8         resp_local_protection[0x20];
4046
4047         u8         req_local_protection[0x20];
4048
4049         u8         resp_cqe_error[0x20];
4050
4051         u8         req_cqe_error[0x20];
4052
4053         u8         req_mw_binding[0x20];
4054
4055         u8         req_bad_response[0x20];
4056
4057         u8         req_remote_invalid_request[0x20];
4058
4059         u8         resp_remote_invalid_request[0x20];
4060
4061         u8         req_remote_access_errors[0x20];
4062
4063         u8         resp_remote_access_errors[0x20];
4064
4065         u8         req_remote_operation_errors[0x20];
4066
4067         u8         req_transport_retries_exceeded[0x20];
4068
4069         u8         cq_overflow[0x20];
4070
4071         u8         resp_cqe_flush_error[0x20];
4072
4073         u8         req_cqe_flush_error[0x20];
4074
4075         u8         reserved_at_620[0x1e0];
4076 };
4077
4078 struct mlx5_ifc_query_q_counter_in_bits {
4079         u8         opcode[0x10];
4080         u8         reserved_at_10[0x10];
4081
4082         u8         reserved_at_20[0x10];
4083         u8         op_mod[0x10];
4084
4085         u8         reserved_at_40[0x80];
4086
4087         u8         clear[0x1];
4088         u8         reserved_at_c1[0x1f];
4089
4090         u8         reserved_at_e0[0x18];
4091         u8         counter_set_id[0x8];
4092 };
4093
4094 struct mlx5_ifc_query_pages_out_bits {
4095         u8         status[0x8];
4096         u8         reserved_at_8[0x18];
4097
4098         u8         syndrome[0x20];
4099
4100         u8         reserved_at_40[0x10];
4101         u8         function_id[0x10];
4102
4103         u8         num_pages[0x20];
4104 };
4105
4106 enum {
4107         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
4108         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
4109         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
4110 };
4111
4112 struct mlx5_ifc_query_pages_in_bits {
4113         u8         opcode[0x10];
4114         u8         reserved_at_10[0x10];
4115
4116         u8         reserved_at_20[0x10];
4117         u8         op_mod[0x10];
4118
4119         u8         reserved_at_40[0x10];
4120         u8         function_id[0x10];
4121
4122         u8         reserved_at_60[0x20];
4123 };
4124
4125 struct mlx5_ifc_query_nic_vport_context_out_bits {
4126         u8         status[0x8];
4127         u8         reserved_at_8[0x18];
4128
4129         u8         syndrome[0x20];
4130
4131         u8         reserved_at_40[0x40];
4132
4133         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4134 };
4135
4136 struct mlx5_ifc_query_nic_vport_context_in_bits {
4137         u8         opcode[0x10];
4138         u8         reserved_at_10[0x10];
4139
4140         u8         reserved_at_20[0x10];
4141         u8         op_mod[0x10];
4142
4143         u8         other_vport[0x1];
4144         u8         reserved_at_41[0xf];
4145         u8         vport_number[0x10];
4146
4147         u8         reserved_at_60[0x5];
4148         u8         allowed_list_type[0x3];
4149         u8         reserved_at_68[0x18];
4150 };
4151
4152 struct mlx5_ifc_query_mkey_out_bits {
4153         u8         status[0x8];
4154         u8         reserved_at_8[0x18];
4155
4156         u8         syndrome[0x20];
4157
4158         u8         reserved_at_40[0x40];
4159
4160         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4161
4162         u8         reserved_at_280[0x600];
4163
4164         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4165
4166         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4167 };
4168
4169 struct mlx5_ifc_query_mkey_in_bits {
4170         u8         opcode[0x10];
4171         u8         reserved_at_10[0x10];
4172
4173         u8         reserved_at_20[0x10];
4174         u8         op_mod[0x10];
4175
4176         u8         reserved_at_40[0x8];
4177         u8         mkey_index[0x18];
4178
4179         u8         pg_access[0x1];
4180         u8         reserved_at_61[0x1f];
4181 };
4182
4183 struct mlx5_ifc_query_mad_demux_out_bits {
4184         u8         status[0x8];
4185         u8         reserved_at_8[0x18];
4186
4187         u8         syndrome[0x20];
4188
4189         u8         reserved_at_40[0x40];
4190
4191         u8         mad_dumux_parameters_block[0x20];
4192 };
4193
4194 struct mlx5_ifc_query_mad_demux_in_bits {
4195         u8         opcode[0x10];
4196         u8         reserved_at_10[0x10];
4197
4198         u8         reserved_at_20[0x10];
4199         u8         op_mod[0x10];
4200
4201         u8         reserved_at_40[0x40];
4202 };
4203
4204 struct mlx5_ifc_query_l2_table_entry_out_bits {
4205         u8         status[0x8];
4206         u8         reserved_at_8[0x18];
4207
4208         u8         syndrome[0x20];
4209
4210         u8         reserved_at_40[0xa0];
4211
4212         u8         reserved_at_e0[0x13];
4213         u8         vlan_valid[0x1];
4214         u8         vlan[0xc];
4215
4216         struct mlx5_ifc_mac_address_layout_bits mac_address;
4217
4218         u8         reserved_at_140[0xc0];
4219 };
4220
4221 struct mlx5_ifc_query_l2_table_entry_in_bits {
4222         u8         opcode[0x10];
4223         u8         reserved_at_10[0x10];
4224
4225         u8         reserved_at_20[0x10];
4226         u8         op_mod[0x10];
4227
4228         u8         reserved_at_40[0x60];
4229
4230         u8         reserved_at_a0[0x8];
4231         u8         table_index[0x18];
4232
4233         u8         reserved_at_c0[0x140];
4234 };
4235
4236 struct mlx5_ifc_query_issi_out_bits {
4237         u8         status[0x8];
4238         u8         reserved_at_8[0x18];
4239
4240         u8         syndrome[0x20];
4241
4242         u8         reserved_at_40[0x10];
4243         u8         current_issi[0x10];
4244
4245         u8         reserved_at_60[0xa0];
4246
4247         u8         reserved_at_100[76][0x8];
4248         u8         supported_issi_dw0[0x20];
4249 };
4250
4251 struct mlx5_ifc_query_issi_in_bits {
4252         u8         opcode[0x10];
4253         u8         reserved_at_10[0x10];
4254
4255         u8         reserved_at_20[0x10];
4256         u8         op_mod[0x10];
4257
4258         u8         reserved_at_40[0x40];
4259 };
4260
4261 struct mlx5_ifc_set_driver_version_out_bits {
4262         u8         status[0x8];
4263         u8         reserved_0[0x18];
4264
4265         u8         syndrome[0x20];
4266         u8         reserved_1[0x40];
4267 };
4268
4269 struct mlx5_ifc_set_driver_version_in_bits {
4270         u8         opcode[0x10];
4271         u8         reserved_0[0x10];
4272
4273         u8         reserved_1[0x10];
4274         u8         op_mod[0x10];
4275
4276         u8         reserved_2[0x40];
4277         u8         driver_version[64][0x8];
4278 };
4279
4280 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4281         u8         status[0x8];
4282         u8         reserved_at_8[0x18];
4283
4284         u8         syndrome[0x20];
4285
4286         u8         reserved_at_40[0x40];
4287
4288         struct mlx5_ifc_pkey_bits pkey[0];
4289 };
4290
4291 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4292         u8         opcode[0x10];
4293         u8         reserved_at_10[0x10];
4294
4295         u8         reserved_at_20[0x10];
4296         u8         op_mod[0x10];
4297
4298         u8         other_vport[0x1];
4299         u8         reserved_at_41[0xb];
4300         u8         port_num[0x4];
4301         u8         vport_number[0x10];
4302
4303         u8         reserved_at_60[0x10];
4304         u8         pkey_index[0x10];
4305 };
4306
4307 enum {
4308         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
4309         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
4310         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4311 };
4312
4313 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4314         u8         status[0x8];
4315         u8         reserved_at_8[0x18];
4316
4317         u8         syndrome[0x20];
4318
4319         u8         reserved_at_40[0x20];
4320
4321         u8         gids_num[0x10];
4322         u8         reserved_at_70[0x10];
4323
4324         struct mlx5_ifc_array128_auto_bits gid[0];
4325 };
4326
4327 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4328         u8         opcode[0x10];
4329         u8         reserved_at_10[0x10];
4330
4331         u8         reserved_at_20[0x10];
4332         u8         op_mod[0x10];
4333
4334         u8         other_vport[0x1];
4335         u8         reserved_at_41[0xb];
4336         u8         port_num[0x4];
4337         u8         vport_number[0x10];
4338
4339         u8         reserved_at_60[0x10];
4340         u8         gid_index[0x10];
4341 };
4342
4343 struct mlx5_ifc_query_hca_vport_context_out_bits {
4344         u8         status[0x8];
4345         u8         reserved_at_8[0x18];
4346
4347         u8         syndrome[0x20];
4348
4349         u8         reserved_at_40[0x40];
4350
4351         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4352 };
4353
4354 struct mlx5_ifc_query_hca_vport_context_in_bits {
4355         u8         opcode[0x10];
4356         u8         reserved_at_10[0x10];
4357
4358         u8         reserved_at_20[0x10];
4359         u8         op_mod[0x10];
4360
4361         u8         other_vport[0x1];
4362         u8         reserved_at_41[0xb];
4363         u8         port_num[0x4];
4364         u8         vport_number[0x10];
4365
4366         u8         reserved_at_60[0x20];
4367 };
4368
4369 struct mlx5_ifc_query_hca_cap_out_bits {
4370         u8         status[0x8];
4371         u8         reserved_at_8[0x18];
4372
4373         u8         syndrome[0x20];
4374
4375         u8         reserved_at_40[0x40];
4376
4377         union mlx5_ifc_hca_cap_union_bits capability;
4378 };
4379
4380 struct mlx5_ifc_query_hca_cap_in_bits {
4381         u8         opcode[0x10];
4382         u8         reserved_at_10[0x10];
4383
4384         u8         reserved_at_20[0x10];
4385         u8         op_mod[0x10];
4386
4387         u8         reserved_at_40[0x40];
4388 };
4389
4390 struct mlx5_ifc_query_flow_table_out_bits {
4391         u8         status[0x8];
4392         u8         reserved_at_8[0x18];
4393
4394         u8         syndrome[0x20];
4395
4396         u8         reserved_at_40[0x80];
4397
4398         u8         reserved_at_c0[0x8];
4399         u8         level[0x8];
4400         u8         reserved_at_d0[0x8];
4401         u8         log_size[0x8];
4402
4403         u8         reserved_at_e0[0x120];
4404 };
4405
4406 struct mlx5_ifc_query_flow_table_in_bits {
4407         u8         opcode[0x10];
4408         u8         reserved_at_10[0x10];
4409
4410         u8         reserved_at_20[0x10];
4411         u8         op_mod[0x10];
4412
4413         u8         reserved_at_40[0x40];
4414
4415         u8         table_type[0x8];
4416         u8         reserved_at_88[0x18];
4417
4418         u8         reserved_at_a0[0x8];
4419         u8         table_id[0x18];
4420
4421         u8         reserved_at_c0[0x140];
4422 };
4423
4424 struct mlx5_ifc_query_fte_out_bits {
4425         u8         status[0x8];
4426         u8         reserved_at_8[0x18];
4427
4428         u8         syndrome[0x20];
4429
4430         u8         reserved_at_40[0x1c0];
4431
4432         struct mlx5_ifc_flow_context_bits flow_context;
4433 };
4434
4435 struct mlx5_ifc_query_fte_in_bits {
4436         u8         opcode[0x10];
4437         u8         reserved_at_10[0x10];
4438
4439         u8         reserved_at_20[0x10];
4440         u8         op_mod[0x10];
4441
4442         u8         reserved_at_40[0x40];
4443
4444         u8         table_type[0x8];
4445         u8         reserved_at_88[0x18];
4446
4447         u8         reserved_at_a0[0x8];
4448         u8         table_id[0x18];
4449
4450         u8         reserved_at_c0[0x40];
4451
4452         u8         flow_index[0x20];
4453
4454         u8         reserved_at_120[0xe0];
4455 };
4456
4457 enum {
4458         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4459         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4460         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4461 };
4462
4463 struct mlx5_ifc_query_flow_group_out_bits {
4464         u8         status[0x8];
4465         u8         reserved_at_8[0x18];
4466
4467         u8         syndrome[0x20];
4468
4469         u8         reserved_at_40[0xa0];
4470
4471         u8         start_flow_index[0x20];
4472
4473         u8         reserved_at_100[0x20];
4474
4475         u8         end_flow_index[0x20];
4476
4477         u8         reserved_at_140[0xa0];
4478
4479         u8         reserved_at_1e0[0x18];
4480         u8         match_criteria_enable[0x8];
4481
4482         struct mlx5_ifc_fte_match_param_bits match_criteria;
4483
4484         u8         reserved_at_1200[0xe00];
4485 };
4486
4487 struct mlx5_ifc_query_flow_group_in_bits {
4488         u8         opcode[0x10];
4489         u8         reserved_at_10[0x10];
4490
4491         u8         reserved_at_20[0x10];
4492         u8         op_mod[0x10];
4493
4494         u8         reserved_at_40[0x40];
4495
4496         u8         table_type[0x8];
4497         u8         reserved_at_88[0x18];
4498
4499         u8         reserved_at_a0[0x8];
4500         u8         table_id[0x18];
4501
4502         u8         group_id[0x20];
4503
4504         u8         reserved_at_e0[0x120];
4505 };
4506
4507 struct mlx5_ifc_query_flow_counter_out_bits {
4508         u8         status[0x8];
4509         u8         reserved_at_8[0x18];
4510
4511         u8         syndrome[0x20];
4512
4513         u8         reserved_at_40[0x40];
4514
4515         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4516 };
4517
4518 struct mlx5_ifc_query_flow_counter_in_bits {
4519         u8         opcode[0x10];
4520         u8         reserved_at_10[0x10];
4521
4522         u8         reserved_at_20[0x10];
4523         u8         op_mod[0x10];
4524
4525         u8         reserved_at_40[0x80];
4526
4527         u8         clear[0x1];
4528         u8         reserved_at_c1[0xf];
4529         u8         num_of_counters[0x10];
4530
4531         u8         flow_counter_id[0x20];
4532 };
4533
4534 struct mlx5_ifc_query_esw_vport_context_out_bits {
4535         u8         status[0x8];
4536         u8         reserved_at_8[0x18];
4537
4538         u8         syndrome[0x20];
4539
4540         u8         reserved_at_40[0x40];
4541
4542         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4543 };
4544
4545 struct mlx5_ifc_query_esw_vport_context_in_bits {
4546         u8         opcode[0x10];
4547         u8         reserved_at_10[0x10];
4548
4549         u8         reserved_at_20[0x10];
4550         u8         op_mod[0x10];
4551
4552         u8         other_vport[0x1];
4553         u8         reserved_at_41[0xf];
4554         u8         vport_number[0x10];
4555
4556         u8         reserved_at_60[0x20];
4557 };
4558
4559 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4560         u8         status[0x8];
4561         u8         reserved_at_8[0x18];
4562
4563         u8         syndrome[0x20];
4564
4565         u8         reserved_at_40[0x40];
4566 };
4567
4568 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4569         u8         reserved_at_0[0x1c];
4570         u8         vport_cvlan_insert[0x1];
4571         u8         vport_svlan_insert[0x1];
4572         u8         vport_cvlan_strip[0x1];
4573         u8         vport_svlan_strip[0x1];
4574 };
4575
4576 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4577         u8         opcode[0x10];
4578         u8         reserved_at_10[0x10];
4579
4580         u8         reserved_at_20[0x10];
4581         u8         op_mod[0x10];
4582
4583         u8         other_vport[0x1];
4584         u8         reserved_at_41[0xf];
4585         u8         vport_number[0x10];
4586
4587         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4588
4589         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4590 };
4591
4592 struct mlx5_ifc_query_eq_out_bits {
4593         u8         status[0x8];
4594         u8         reserved_at_8[0x18];
4595
4596         u8         syndrome[0x20];
4597
4598         u8         reserved_at_40[0x40];
4599
4600         struct mlx5_ifc_eqc_bits eq_context_entry;
4601
4602         u8         reserved_at_280[0x40];
4603
4604         u8         event_bitmask[0x40];
4605
4606         u8         reserved_at_300[0x580];
4607
4608         u8         pas[0][0x40];
4609 };
4610
4611 struct mlx5_ifc_query_eq_in_bits {
4612         u8         opcode[0x10];
4613         u8         reserved_at_10[0x10];
4614
4615         u8         reserved_at_20[0x10];
4616         u8         op_mod[0x10];
4617
4618         u8         reserved_at_40[0x18];
4619         u8         eq_number[0x8];
4620
4621         u8         reserved_at_60[0x20];
4622 };
4623
4624 struct mlx5_ifc_encap_header_in_bits {
4625         u8         reserved_at_0[0x5];
4626         u8         header_type[0x3];
4627         u8         reserved_at_8[0xe];
4628         u8         encap_header_size[0xa];
4629
4630         u8         reserved_at_20[0x10];
4631         u8         encap_header[2][0x8];
4632
4633         u8         more_encap_header[0][0x8];
4634 };
4635
4636 struct mlx5_ifc_query_encap_header_out_bits {
4637         u8         status[0x8];
4638         u8         reserved_at_8[0x18];
4639
4640         u8         syndrome[0x20];
4641
4642         u8         reserved_at_40[0xa0];
4643
4644         struct mlx5_ifc_encap_header_in_bits encap_header[0];
4645 };
4646
4647 struct mlx5_ifc_query_encap_header_in_bits {
4648         u8         opcode[0x10];
4649         u8         reserved_at_10[0x10];
4650
4651         u8         reserved_at_20[0x10];
4652         u8         op_mod[0x10];
4653
4654         u8         encap_id[0x20];
4655
4656         u8         reserved_at_60[0xa0];
4657 };
4658
4659 struct mlx5_ifc_alloc_encap_header_out_bits {
4660         u8         status[0x8];
4661         u8         reserved_at_8[0x18];
4662
4663         u8         syndrome[0x20];
4664
4665         u8         encap_id[0x20];
4666
4667         u8         reserved_at_60[0x20];
4668 };
4669
4670 struct mlx5_ifc_alloc_encap_header_in_bits {
4671         u8         opcode[0x10];
4672         u8         reserved_at_10[0x10];
4673
4674         u8         reserved_at_20[0x10];
4675         u8         op_mod[0x10];
4676
4677         u8         reserved_at_40[0xa0];
4678
4679         struct mlx5_ifc_encap_header_in_bits encap_header;
4680 };
4681
4682 struct mlx5_ifc_dealloc_encap_header_out_bits {
4683         u8         status[0x8];
4684         u8         reserved_at_8[0x18];
4685
4686         u8         syndrome[0x20];
4687
4688         u8         reserved_at_40[0x40];
4689 };
4690
4691 struct mlx5_ifc_dealloc_encap_header_in_bits {
4692         u8         opcode[0x10];
4693         u8         reserved_at_10[0x10];
4694
4695         u8         reserved_20[0x10];
4696         u8         op_mod[0x10];
4697
4698         u8         encap_id[0x20];
4699
4700         u8         reserved_60[0x20];
4701 };
4702
4703 struct mlx5_ifc_set_action_in_bits {
4704         u8         action_type[0x4];
4705         u8         field[0xc];
4706         u8         reserved_at_10[0x3];
4707         u8         offset[0x5];
4708         u8         reserved_at_18[0x3];
4709         u8         length[0x5];
4710
4711         u8         data[0x20];
4712 };
4713
4714 struct mlx5_ifc_add_action_in_bits {
4715         u8         action_type[0x4];
4716         u8         field[0xc];
4717         u8         reserved_at_10[0x10];
4718
4719         u8         data[0x20];
4720 };
4721
4722 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4723         struct mlx5_ifc_set_action_in_bits set_action_in;
4724         struct mlx5_ifc_add_action_in_bits add_action_in;
4725         u8         reserved_at_0[0x40];
4726 };
4727
4728 enum {
4729         MLX5_ACTION_TYPE_SET   = 0x1,
4730         MLX5_ACTION_TYPE_ADD   = 0x2,
4731 };
4732
4733 enum {
4734         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
4735         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
4736         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
4737         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
4738         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
4739         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
4740         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
4741         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
4742         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
4743         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
4744         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
4745         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
4746         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
4747         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
4748         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
4749         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
4750         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
4751         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
4752         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
4753         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
4754         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
4755         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
4756         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
4757 };
4758
4759 struct mlx5_ifc_alloc_modify_header_context_out_bits {
4760         u8         status[0x8];
4761         u8         reserved_at_8[0x18];
4762
4763         u8         syndrome[0x20];
4764
4765         u8         modify_header_id[0x20];
4766
4767         u8         reserved_at_60[0x20];
4768 };
4769
4770 struct mlx5_ifc_alloc_modify_header_context_in_bits {
4771         u8         opcode[0x10];
4772         u8         reserved_at_10[0x10];
4773
4774         u8         reserved_at_20[0x10];
4775         u8         op_mod[0x10];
4776
4777         u8         reserved_at_40[0x20];
4778
4779         u8         table_type[0x8];
4780         u8         reserved_at_68[0x10];
4781         u8         num_of_actions[0x8];
4782
4783         union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4784 };
4785
4786 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4787         u8         status[0x8];
4788         u8         reserved_at_8[0x18];
4789
4790         u8         syndrome[0x20];
4791
4792         u8         reserved_at_40[0x40];
4793 };
4794
4795 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4796         u8         opcode[0x10];
4797         u8         reserved_at_10[0x10];
4798
4799         u8         reserved_at_20[0x10];
4800         u8         op_mod[0x10];
4801
4802         u8         modify_header_id[0x20];
4803
4804         u8         reserved_at_60[0x20];
4805 };
4806
4807 struct mlx5_ifc_query_dct_out_bits {
4808         u8         status[0x8];
4809         u8         reserved_at_8[0x18];
4810
4811         u8         syndrome[0x20];
4812
4813         u8         reserved_at_40[0x40];
4814
4815         struct mlx5_ifc_dctc_bits dct_context_entry;
4816
4817         u8         reserved_at_280[0x180];
4818 };
4819
4820 struct mlx5_ifc_query_dct_in_bits {
4821         u8         opcode[0x10];
4822         u8         reserved_at_10[0x10];
4823
4824         u8         reserved_at_20[0x10];
4825         u8         op_mod[0x10];
4826
4827         u8         reserved_at_40[0x8];
4828         u8         dctn[0x18];
4829
4830         u8         reserved_at_60[0x20];
4831 };
4832
4833 struct mlx5_ifc_query_cq_out_bits {
4834         u8         status[0x8];
4835         u8         reserved_at_8[0x18];
4836
4837         u8         syndrome[0x20];
4838
4839         u8         reserved_at_40[0x40];
4840
4841         struct mlx5_ifc_cqc_bits cq_context;
4842
4843         u8         reserved_at_280[0x600];
4844
4845         u8         pas[0][0x40];
4846 };
4847
4848 struct mlx5_ifc_query_cq_in_bits {
4849         u8         opcode[0x10];
4850         u8         reserved_at_10[0x10];
4851
4852         u8         reserved_at_20[0x10];
4853         u8         op_mod[0x10];
4854
4855         u8         reserved_at_40[0x8];
4856         u8         cqn[0x18];
4857
4858         u8         reserved_at_60[0x20];
4859 };
4860
4861 struct mlx5_ifc_query_cong_status_out_bits {
4862         u8         status[0x8];
4863         u8         reserved_at_8[0x18];
4864
4865         u8         syndrome[0x20];
4866
4867         u8         reserved_at_40[0x20];
4868
4869         u8         enable[0x1];
4870         u8         tag_enable[0x1];
4871         u8         reserved_at_62[0x1e];
4872 };
4873
4874 struct mlx5_ifc_query_cong_status_in_bits {
4875         u8         opcode[0x10];
4876         u8         reserved_at_10[0x10];
4877
4878         u8         reserved_at_20[0x10];
4879         u8         op_mod[0x10];
4880
4881         u8         reserved_at_40[0x18];
4882         u8         priority[0x4];
4883         u8         cong_protocol[0x4];
4884
4885         u8         reserved_at_60[0x20];
4886 };
4887
4888 struct mlx5_ifc_query_cong_statistics_out_bits {
4889         u8         status[0x8];
4890         u8         reserved_at_8[0x18];
4891
4892         u8         syndrome[0x20];
4893
4894         u8         reserved_at_40[0x40];
4895
4896         u8         rp_cur_flows[0x20];
4897
4898         u8         sum_flows[0x20];
4899
4900         u8         rp_cnp_ignored_high[0x20];
4901
4902         u8         rp_cnp_ignored_low[0x20];
4903
4904         u8         rp_cnp_handled_high[0x20];
4905
4906         u8         rp_cnp_handled_low[0x20];
4907
4908         u8         reserved_at_140[0x100];
4909
4910         u8         time_stamp_high[0x20];
4911
4912         u8         time_stamp_low[0x20];
4913
4914         u8         accumulators_period[0x20];
4915
4916         u8         np_ecn_marked_roce_packets_high[0x20];
4917
4918         u8         np_ecn_marked_roce_packets_low[0x20];
4919
4920         u8         np_cnp_sent_high[0x20];
4921
4922         u8         np_cnp_sent_low[0x20];
4923
4924         u8         reserved_at_320[0x560];
4925 };
4926
4927 struct mlx5_ifc_query_cong_statistics_in_bits {
4928         u8         opcode[0x10];
4929         u8         reserved_at_10[0x10];
4930
4931         u8         reserved_at_20[0x10];
4932         u8         op_mod[0x10];
4933
4934         u8         clear[0x1];
4935         u8         reserved_at_41[0x1f];
4936
4937         u8         reserved_at_60[0x20];
4938 };
4939
4940 struct mlx5_ifc_query_cong_params_out_bits {
4941         u8         status[0x8];
4942         u8         reserved_at_8[0x18];
4943
4944         u8         syndrome[0x20];
4945
4946         u8         reserved_at_40[0x40];
4947
4948         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4949 };
4950
4951 struct mlx5_ifc_query_cong_params_in_bits {
4952         u8         opcode[0x10];
4953         u8         reserved_at_10[0x10];
4954
4955         u8         reserved_at_20[0x10];
4956         u8         op_mod[0x10];
4957
4958         u8         reserved_at_40[0x1c];
4959         u8         cong_protocol[0x4];
4960
4961         u8         reserved_at_60[0x20];
4962 };
4963
4964 struct mlx5_ifc_query_adapter_out_bits {
4965         u8         status[0x8];
4966         u8         reserved_at_8[0x18];
4967
4968         u8         syndrome[0x20];
4969
4970         u8         reserved_at_40[0x40];
4971
4972         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4973 };
4974
4975 struct mlx5_ifc_query_adapter_in_bits {
4976         u8         opcode[0x10];
4977         u8         reserved_at_10[0x10];
4978
4979         u8         reserved_at_20[0x10];
4980         u8         op_mod[0x10];
4981
4982         u8         reserved_at_40[0x40];
4983 };
4984
4985 struct mlx5_ifc_qp_2rst_out_bits {
4986         u8         status[0x8];
4987         u8         reserved_at_8[0x18];
4988
4989         u8         syndrome[0x20];
4990
4991         u8         reserved_at_40[0x40];
4992 };
4993
4994 struct mlx5_ifc_qp_2rst_in_bits {
4995         u8         opcode[0x10];
4996         u8         reserved_at_10[0x10];
4997
4998         u8         reserved_at_20[0x10];
4999         u8         op_mod[0x10];
5000
5001         u8         reserved_at_40[0x8];
5002         u8         qpn[0x18];
5003
5004         u8         reserved_at_60[0x20];
5005 };
5006
5007 struct mlx5_ifc_qp_2err_out_bits {
5008         u8         status[0x8];
5009         u8         reserved_at_8[0x18];
5010
5011         u8         syndrome[0x20];
5012
5013         u8         reserved_at_40[0x40];
5014 };
5015
5016 struct mlx5_ifc_qp_2err_in_bits {
5017         u8         opcode[0x10];
5018         u8         reserved_at_10[0x10];
5019
5020         u8         reserved_at_20[0x10];
5021         u8         op_mod[0x10];
5022
5023         u8         reserved_at_40[0x8];
5024         u8         qpn[0x18];
5025
5026         u8         reserved_at_60[0x20];
5027 };
5028
5029 struct mlx5_ifc_page_fault_resume_out_bits {
5030         u8         status[0x8];
5031         u8         reserved_at_8[0x18];
5032
5033         u8         syndrome[0x20];
5034
5035         u8         reserved_at_40[0x40];
5036 };
5037
5038 struct mlx5_ifc_page_fault_resume_in_bits {
5039         u8         opcode[0x10];
5040         u8         reserved_at_10[0x10];
5041
5042         u8         reserved_at_20[0x10];
5043         u8         op_mod[0x10];
5044
5045         u8         error[0x1];
5046         u8         reserved_at_41[0x4];
5047         u8         page_fault_type[0x3];
5048         u8         wq_number[0x18];
5049
5050         u8         reserved_at_60[0x8];
5051         u8         token[0x18];
5052 };
5053
5054 struct mlx5_ifc_nop_out_bits {
5055         u8         status[0x8];
5056         u8         reserved_at_8[0x18];
5057
5058         u8         syndrome[0x20];
5059
5060         u8         reserved_at_40[0x40];
5061 };
5062
5063 struct mlx5_ifc_nop_in_bits {
5064         u8         opcode[0x10];
5065         u8         reserved_at_10[0x10];
5066
5067         u8         reserved_at_20[0x10];
5068         u8         op_mod[0x10];
5069
5070         u8         reserved_at_40[0x40];
5071 };
5072
5073 struct mlx5_ifc_modify_vport_state_out_bits {
5074         u8         status[0x8];
5075         u8         reserved_at_8[0x18];
5076
5077         u8         syndrome[0x20];
5078
5079         u8         reserved_at_40[0x40];
5080 };
5081
5082 struct mlx5_ifc_modify_vport_state_in_bits {
5083         u8         opcode[0x10];
5084         u8         reserved_at_10[0x10];
5085
5086         u8         reserved_at_20[0x10];
5087         u8         op_mod[0x10];
5088
5089         u8         other_vport[0x1];
5090         u8         reserved_at_41[0xf];
5091         u8         vport_number[0x10];
5092
5093         u8         reserved_at_60[0x18];
5094         u8         admin_state[0x4];
5095         u8         reserved_at_7c[0x4];
5096 };
5097
5098 struct mlx5_ifc_modify_tis_out_bits {
5099         u8         status[0x8];
5100         u8         reserved_at_8[0x18];
5101
5102         u8         syndrome[0x20];
5103
5104         u8         reserved_at_40[0x40];
5105 };
5106
5107 struct mlx5_ifc_modify_tis_bitmask_bits {
5108         u8         reserved_at_0[0x20];
5109
5110         u8         reserved_at_20[0x1d];
5111         u8         lag_tx_port_affinity[0x1];
5112         u8         strict_lag_tx_port_affinity[0x1];
5113         u8         prio[0x1];
5114 };
5115
5116 struct mlx5_ifc_modify_tis_in_bits {
5117         u8         opcode[0x10];
5118         u8         reserved_at_10[0x10];
5119
5120         u8         reserved_at_20[0x10];
5121         u8         op_mod[0x10];
5122
5123         u8         reserved_at_40[0x8];
5124         u8         tisn[0x18];
5125
5126         u8         reserved_at_60[0x20];
5127
5128         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5129
5130         u8         reserved_at_c0[0x40];
5131
5132         struct mlx5_ifc_tisc_bits ctx;
5133 };
5134
5135 struct mlx5_ifc_modify_tir_bitmask_bits {
5136         u8         reserved_at_0[0x20];
5137
5138         u8         reserved_at_20[0x1b];
5139         u8         self_lb_en[0x1];
5140         u8         reserved_at_3c[0x1];
5141         u8         hash[0x1];
5142         u8         reserved_at_3e[0x1];
5143         u8         lro[0x1];
5144 };
5145
5146 struct mlx5_ifc_modify_tir_out_bits {
5147         u8         status[0x8];
5148         u8         reserved_at_8[0x18];
5149
5150         u8         syndrome[0x20];
5151
5152         u8         reserved_at_40[0x40];
5153 };
5154
5155 struct mlx5_ifc_modify_tir_in_bits {
5156         u8         opcode[0x10];
5157         u8         reserved_at_10[0x10];
5158
5159         u8         reserved_at_20[0x10];
5160         u8         op_mod[0x10];
5161
5162         u8         reserved_at_40[0x8];
5163         u8         tirn[0x18];
5164
5165         u8         reserved_at_60[0x20];
5166
5167         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5168
5169         u8         reserved_at_c0[0x40];
5170
5171         struct mlx5_ifc_tirc_bits ctx;
5172 };
5173
5174 struct mlx5_ifc_modify_sq_out_bits {
5175         u8         status[0x8];
5176         u8         reserved_at_8[0x18];
5177
5178         u8         syndrome[0x20];
5179
5180         u8         reserved_at_40[0x40];
5181 };
5182
5183 struct mlx5_ifc_modify_sq_in_bits {
5184         u8         opcode[0x10];
5185         u8         reserved_at_10[0x10];
5186
5187         u8         reserved_at_20[0x10];
5188         u8         op_mod[0x10];
5189
5190         u8         sq_state[0x4];
5191         u8         reserved_at_44[0x4];
5192         u8         sqn[0x18];
5193
5194         u8         reserved_at_60[0x20];
5195
5196         u8         modify_bitmask[0x40];
5197
5198         u8         reserved_at_c0[0x40];
5199
5200         struct mlx5_ifc_sqc_bits ctx;
5201 };
5202
5203 struct mlx5_ifc_modify_scheduling_element_out_bits {
5204         u8         status[0x8];
5205         u8         reserved_at_8[0x18];
5206
5207         u8         syndrome[0x20];
5208
5209         u8         reserved_at_40[0x1c0];
5210 };
5211
5212 enum {
5213         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5214         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5215 };
5216
5217 struct mlx5_ifc_modify_scheduling_element_in_bits {
5218         u8         opcode[0x10];
5219         u8         reserved_at_10[0x10];
5220
5221         u8         reserved_at_20[0x10];
5222         u8         op_mod[0x10];
5223
5224         u8         scheduling_hierarchy[0x8];
5225         u8         reserved_at_48[0x18];
5226
5227         u8         scheduling_element_id[0x20];
5228
5229         u8         reserved_at_80[0x20];
5230
5231         u8         modify_bitmask[0x20];
5232
5233         u8         reserved_at_c0[0x40];
5234
5235         struct mlx5_ifc_scheduling_context_bits scheduling_context;
5236
5237         u8         reserved_at_300[0x100];
5238 };
5239
5240 struct mlx5_ifc_modify_rqt_out_bits {
5241         u8         status[0x8];
5242         u8         reserved_at_8[0x18];
5243
5244         u8         syndrome[0x20];
5245
5246         u8         reserved_at_40[0x40];
5247 };
5248
5249 struct mlx5_ifc_rqt_bitmask_bits {
5250         u8         reserved_at_0[0x20];
5251
5252         u8         reserved_at_20[0x1f];
5253         u8         rqn_list[0x1];
5254 };
5255
5256 struct mlx5_ifc_modify_rqt_in_bits {
5257         u8         opcode[0x10];
5258         u8         reserved_at_10[0x10];
5259
5260         u8         reserved_at_20[0x10];
5261         u8         op_mod[0x10];
5262
5263         u8         reserved_at_40[0x8];
5264         u8         rqtn[0x18];
5265
5266         u8         reserved_at_60[0x20];
5267
5268         struct mlx5_ifc_rqt_bitmask_bits bitmask;
5269
5270         u8         reserved_at_c0[0x40];
5271
5272         struct mlx5_ifc_rqtc_bits ctx;
5273 };
5274
5275 struct mlx5_ifc_modify_rq_out_bits {
5276         u8         status[0x8];
5277         u8         reserved_at_8[0x18];
5278
5279         u8         syndrome[0x20];
5280
5281         u8         reserved_at_40[0x40];
5282 };
5283
5284 enum {
5285         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5286         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5287         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5288 };
5289
5290 struct mlx5_ifc_modify_rq_in_bits {
5291         u8         opcode[0x10];
5292         u8         reserved_at_10[0x10];
5293
5294         u8         reserved_at_20[0x10];
5295         u8         op_mod[0x10];
5296
5297         u8         rq_state[0x4];
5298         u8         reserved_at_44[0x4];
5299         u8         rqn[0x18];
5300
5301         u8         reserved_at_60[0x20];
5302
5303         u8         modify_bitmask[0x40];
5304
5305         u8         reserved_at_c0[0x40];
5306
5307         struct mlx5_ifc_rqc_bits ctx;
5308 };
5309
5310 struct mlx5_ifc_modify_rmp_out_bits {
5311         u8         status[0x8];
5312         u8         reserved_at_8[0x18];
5313
5314         u8         syndrome[0x20];
5315
5316         u8         reserved_at_40[0x40];
5317 };
5318
5319 struct mlx5_ifc_rmp_bitmask_bits {
5320         u8         reserved_at_0[0x20];
5321
5322         u8         reserved_at_20[0x1f];
5323         u8         lwm[0x1];
5324 };
5325
5326 struct mlx5_ifc_modify_rmp_in_bits {
5327         u8         opcode[0x10];
5328         u8         reserved_at_10[0x10];
5329
5330         u8         reserved_at_20[0x10];
5331         u8         op_mod[0x10];
5332
5333         u8         rmp_state[0x4];
5334         u8         reserved_at_44[0x4];
5335         u8         rmpn[0x18];
5336
5337         u8         reserved_at_60[0x20];
5338
5339         struct mlx5_ifc_rmp_bitmask_bits bitmask;
5340
5341         u8         reserved_at_c0[0x40];
5342
5343         struct mlx5_ifc_rmpc_bits ctx;
5344 };
5345
5346 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5347         u8         status[0x8];
5348         u8         reserved_at_8[0x18];
5349
5350         u8         syndrome[0x20];
5351
5352         u8         reserved_at_40[0x40];
5353 };
5354
5355 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5356         u8         reserved_at_0[0x12];
5357         u8         affiliation[0x1];
5358         u8         reserved_at_e[0x1];
5359         u8         disable_uc_local_lb[0x1];
5360         u8         disable_mc_local_lb[0x1];
5361         u8         node_guid[0x1];
5362         u8         port_guid[0x1];
5363         u8         min_inline[0x1];
5364         u8         mtu[0x1];
5365         u8         change_event[0x1];
5366         u8         promisc[0x1];
5367         u8         permanent_address[0x1];
5368         u8         addresses_list[0x1];
5369         u8         roce_en[0x1];
5370         u8         reserved_at_1f[0x1];
5371 };
5372
5373 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5374         u8         opcode[0x10];
5375         u8         reserved_at_10[0x10];
5376
5377         u8         reserved_at_20[0x10];
5378         u8         op_mod[0x10];
5379
5380         u8         other_vport[0x1];
5381         u8         reserved_at_41[0xf];
5382         u8         vport_number[0x10];
5383
5384         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5385
5386         u8         reserved_at_80[0x780];
5387
5388         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5389 };
5390
5391 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5392         u8         status[0x8];
5393         u8         reserved_at_8[0x18];
5394
5395         u8         syndrome[0x20];
5396
5397         u8         reserved_at_40[0x40];
5398 };
5399
5400 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5401         u8         opcode[0x10];
5402         u8         reserved_at_10[0x10];
5403
5404         u8         reserved_at_20[0x10];
5405         u8         op_mod[0x10];
5406
5407         u8         other_vport[0x1];
5408         u8         reserved_at_41[0xb];
5409         u8         port_num[0x4];
5410         u8         vport_number[0x10];
5411
5412         u8         reserved_at_60[0x20];
5413
5414         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5415 };
5416
5417 struct mlx5_ifc_modify_cq_out_bits {
5418         u8         status[0x8];
5419         u8         reserved_at_8[0x18];
5420
5421         u8         syndrome[0x20];
5422
5423         u8         reserved_at_40[0x40];
5424 };
5425
5426 enum {
5427         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5428         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5429 };
5430
5431 struct mlx5_ifc_modify_cq_in_bits {
5432         u8         opcode[0x10];
5433         u8         reserved_at_10[0x10];
5434
5435         u8         reserved_at_20[0x10];
5436         u8         op_mod[0x10];
5437
5438         u8         reserved_at_40[0x8];
5439         u8         cqn[0x18];
5440
5441         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5442
5443         struct mlx5_ifc_cqc_bits cq_context;
5444
5445         u8         reserved_at_280[0x600];
5446
5447         u8         pas[0][0x40];
5448 };
5449
5450 struct mlx5_ifc_modify_cong_status_out_bits {
5451         u8         status[0x8];
5452         u8         reserved_at_8[0x18];
5453
5454         u8         syndrome[0x20];
5455
5456         u8         reserved_at_40[0x40];
5457 };
5458
5459 struct mlx5_ifc_modify_cong_status_in_bits {
5460         u8         opcode[0x10];
5461         u8         reserved_at_10[0x10];
5462
5463         u8         reserved_at_20[0x10];
5464         u8         op_mod[0x10];
5465
5466         u8         reserved_at_40[0x18];
5467         u8         priority[0x4];
5468         u8         cong_protocol[0x4];
5469
5470         u8         enable[0x1];
5471         u8         tag_enable[0x1];
5472         u8         reserved_at_62[0x1e];
5473 };
5474
5475 struct mlx5_ifc_modify_cong_params_out_bits {
5476         u8         status[0x8];
5477         u8         reserved_at_8[0x18];
5478
5479         u8         syndrome[0x20];
5480
5481         u8         reserved_at_40[0x40];
5482 };
5483
5484 struct mlx5_ifc_modify_cong_params_in_bits {
5485         u8         opcode[0x10];
5486         u8         reserved_at_10[0x10];
5487
5488         u8         reserved_at_20[0x10];
5489         u8         op_mod[0x10];
5490
5491         u8         reserved_at_40[0x1c];
5492         u8         cong_protocol[0x4];
5493
5494         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5495
5496         u8         reserved_at_80[0x80];
5497
5498         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5499 };
5500
5501 struct mlx5_ifc_manage_pages_out_bits {
5502         u8         status[0x8];
5503         u8         reserved_at_8[0x18];
5504
5505         u8         syndrome[0x20];
5506
5507         u8         output_num_entries[0x20];
5508
5509         u8         reserved_at_60[0x20];
5510
5511         u8         pas[0][0x40];
5512 };
5513
5514 enum {
5515         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
5516         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
5517         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
5518 };
5519
5520 struct mlx5_ifc_manage_pages_in_bits {
5521         u8         opcode[0x10];
5522         u8         reserved_at_10[0x10];
5523
5524         u8         reserved_at_20[0x10];
5525         u8         op_mod[0x10];
5526
5527         u8         reserved_at_40[0x10];
5528         u8         function_id[0x10];
5529
5530         u8         input_num_entries[0x20];
5531
5532         u8         pas[0][0x40];
5533 };
5534
5535 struct mlx5_ifc_mad_ifc_out_bits {
5536         u8         status[0x8];
5537         u8         reserved_at_8[0x18];
5538
5539         u8         syndrome[0x20];
5540
5541         u8         reserved_at_40[0x40];
5542
5543         u8         response_mad_packet[256][0x8];
5544 };
5545
5546 struct mlx5_ifc_mad_ifc_in_bits {
5547         u8         opcode[0x10];
5548         u8         reserved_at_10[0x10];
5549
5550         u8         reserved_at_20[0x10];
5551         u8         op_mod[0x10];
5552
5553         u8         remote_lid[0x10];
5554         u8         reserved_at_50[0x8];
5555         u8         port[0x8];
5556
5557         u8         reserved_at_60[0x20];
5558
5559         u8         mad[256][0x8];
5560 };
5561
5562 struct mlx5_ifc_init_hca_out_bits {
5563         u8         status[0x8];
5564         u8         reserved_at_8[0x18];
5565
5566         u8         syndrome[0x20];
5567
5568         u8         reserved_at_40[0x40];
5569 };
5570
5571 struct mlx5_ifc_init_hca_in_bits {
5572         u8         opcode[0x10];
5573         u8         reserved_at_10[0x10];
5574
5575         u8         reserved_at_20[0x10];
5576         u8         op_mod[0x10];
5577
5578         u8         reserved_at_40[0x40];
5579         u8         sw_owner_id[4][0x20];
5580 };
5581
5582 struct mlx5_ifc_init2rtr_qp_out_bits {
5583         u8         status[0x8];
5584         u8         reserved_at_8[0x18];
5585
5586         u8         syndrome[0x20];
5587
5588         u8         reserved_at_40[0x40];
5589 };
5590
5591 struct mlx5_ifc_init2rtr_qp_in_bits {
5592         u8         opcode[0x10];
5593         u8         reserved_at_10[0x10];
5594
5595         u8         reserved_at_20[0x10];
5596         u8         op_mod[0x10];
5597
5598         u8         reserved_at_40[0x8];
5599         u8         qpn[0x18];
5600
5601         u8         reserved_at_60[0x20];
5602
5603         u8         opt_param_mask[0x20];
5604
5605         u8         reserved_at_a0[0x20];
5606
5607         struct mlx5_ifc_qpc_bits qpc;
5608
5609         u8         reserved_at_800[0x80];
5610 };
5611
5612 struct mlx5_ifc_init2init_qp_out_bits {
5613         u8         status[0x8];
5614         u8         reserved_at_8[0x18];
5615
5616         u8         syndrome[0x20];
5617
5618         u8         reserved_at_40[0x40];
5619 };
5620
5621 struct mlx5_ifc_init2init_qp_in_bits {
5622         u8         opcode[0x10];
5623         u8         reserved_at_10[0x10];
5624
5625         u8         reserved_at_20[0x10];
5626         u8         op_mod[0x10];
5627
5628         u8         reserved_at_40[0x8];
5629         u8         qpn[0x18];
5630
5631         u8         reserved_at_60[0x20];
5632
5633         u8         opt_param_mask[0x20];
5634
5635         u8         reserved_at_a0[0x20];
5636
5637         struct mlx5_ifc_qpc_bits qpc;
5638
5639         u8         reserved_at_800[0x80];
5640 };
5641
5642 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5643         u8         status[0x8];
5644         u8         reserved_at_8[0x18];
5645
5646         u8         syndrome[0x20];
5647
5648         u8         reserved_at_40[0x40];
5649
5650         u8         packet_headers_log[128][0x8];
5651
5652         u8         packet_syndrome[64][0x8];
5653 };
5654
5655 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5656         u8         opcode[0x10];
5657         u8         reserved_at_10[0x10];
5658
5659         u8         reserved_at_20[0x10];
5660         u8         op_mod[0x10];
5661
5662         u8         reserved_at_40[0x40];
5663 };
5664
5665 struct mlx5_ifc_gen_eqe_in_bits {
5666         u8         opcode[0x10];
5667         u8         reserved_at_10[0x10];
5668
5669         u8         reserved_at_20[0x10];
5670         u8         op_mod[0x10];
5671
5672         u8         reserved_at_40[0x18];
5673         u8         eq_number[0x8];
5674
5675         u8         reserved_at_60[0x20];
5676
5677         u8         eqe[64][0x8];
5678 };
5679
5680 struct mlx5_ifc_gen_eq_out_bits {
5681         u8         status[0x8];
5682         u8         reserved_at_8[0x18];
5683
5684         u8         syndrome[0x20];
5685
5686         u8         reserved_at_40[0x40];
5687 };
5688
5689 struct mlx5_ifc_enable_hca_out_bits {
5690         u8         status[0x8];
5691         u8         reserved_at_8[0x18];
5692
5693         u8         syndrome[0x20];
5694
5695         u8         reserved_at_40[0x20];
5696 };
5697
5698 struct mlx5_ifc_enable_hca_in_bits {
5699         u8         opcode[0x10];
5700         u8         reserved_at_10[0x10];
5701
5702         u8         reserved_at_20[0x10];
5703         u8         op_mod[0x10];
5704
5705         u8         reserved_at_40[0x10];
5706         u8         function_id[0x10];
5707
5708         u8         reserved_at_60[0x20];
5709 };
5710
5711 struct mlx5_ifc_drain_dct_out_bits {
5712         u8         status[0x8];
5713         u8         reserved_at_8[0x18];
5714
5715         u8         syndrome[0x20];
5716
5717         u8         reserved_at_40[0x40];
5718 };
5719
5720 struct mlx5_ifc_drain_dct_in_bits {
5721         u8         opcode[0x10];
5722         u8         reserved_at_10[0x10];
5723
5724         u8         reserved_at_20[0x10];
5725         u8         op_mod[0x10];
5726
5727         u8         reserved_at_40[0x8];
5728         u8         dctn[0x18];
5729
5730         u8         reserved_at_60[0x20];
5731 };
5732
5733 struct mlx5_ifc_disable_hca_out_bits {
5734         u8         status[0x8];
5735         u8         reserved_at_8[0x18];
5736
5737         u8         syndrome[0x20];
5738
5739         u8         reserved_at_40[0x20];
5740 };
5741
5742 struct mlx5_ifc_disable_hca_in_bits {
5743         u8         opcode[0x10];
5744         u8         reserved_at_10[0x10];
5745
5746         u8         reserved_at_20[0x10];
5747         u8         op_mod[0x10];
5748
5749         u8         reserved_at_40[0x10];
5750         u8         function_id[0x10];
5751
5752         u8         reserved_at_60[0x20];
5753 };
5754
5755 struct mlx5_ifc_detach_from_mcg_out_bits {
5756         u8         status[0x8];
5757         u8         reserved_at_8[0x18];
5758
5759         u8         syndrome[0x20];
5760
5761         u8         reserved_at_40[0x40];
5762 };
5763
5764 struct mlx5_ifc_detach_from_mcg_in_bits {
5765         u8         opcode[0x10];
5766         u8         reserved_at_10[0x10];
5767
5768         u8         reserved_at_20[0x10];
5769         u8         op_mod[0x10];
5770
5771         u8         reserved_at_40[0x8];
5772         u8         qpn[0x18];
5773
5774         u8         reserved_at_60[0x20];
5775
5776         u8         multicast_gid[16][0x8];
5777 };
5778
5779 struct mlx5_ifc_destroy_xrq_out_bits {
5780         u8         status[0x8];
5781         u8         reserved_at_8[0x18];
5782
5783         u8         syndrome[0x20];
5784
5785         u8         reserved_at_40[0x40];
5786 };
5787
5788 struct mlx5_ifc_destroy_xrq_in_bits {
5789         u8         opcode[0x10];
5790         u8         reserved_at_10[0x10];
5791
5792         u8         reserved_at_20[0x10];
5793         u8         op_mod[0x10];
5794
5795         u8         reserved_at_40[0x8];
5796         u8         xrqn[0x18];
5797
5798         u8         reserved_at_60[0x20];
5799 };
5800
5801 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5802         u8         status[0x8];
5803         u8         reserved_at_8[0x18];
5804
5805         u8         syndrome[0x20];
5806
5807         u8         reserved_at_40[0x40];
5808 };
5809
5810 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5811         u8         opcode[0x10];
5812         u8         reserved_at_10[0x10];
5813
5814         u8         reserved_at_20[0x10];
5815         u8         op_mod[0x10];
5816
5817         u8         reserved_at_40[0x8];
5818         u8         xrc_srqn[0x18];
5819
5820         u8         reserved_at_60[0x20];
5821 };
5822
5823 struct mlx5_ifc_destroy_tis_out_bits {
5824         u8         status[0x8];
5825         u8         reserved_at_8[0x18];
5826
5827         u8         syndrome[0x20];
5828
5829         u8         reserved_at_40[0x40];
5830 };
5831
5832 struct mlx5_ifc_destroy_tis_in_bits {
5833         u8         opcode[0x10];
5834         u8         reserved_at_10[0x10];
5835
5836         u8         reserved_at_20[0x10];
5837         u8         op_mod[0x10];
5838
5839         u8         reserved_at_40[0x8];
5840         u8         tisn[0x18];
5841
5842         u8         reserved_at_60[0x20];
5843 };
5844
5845 struct mlx5_ifc_destroy_tir_out_bits {
5846         u8         status[0x8];
5847         u8         reserved_at_8[0x18];
5848
5849         u8         syndrome[0x20];
5850
5851         u8         reserved_at_40[0x40];
5852 };
5853
5854 struct mlx5_ifc_destroy_tir_in_bits {
5855         u8         opcode[0x10];
5856         u8         reserved_at_10[0x10];
5857
5858         u8         reserved_at_20[0x10];
5859         u8         op_mod[0x10];
5860
5861         u8         reserved_at_40[0x8];
5862         u8         tirn[0x18];
5863
5864         u8         reserved_at_60[0x20];
5865 };
5866
5867 struct mlx5_ifc_destroy_srq_out_bits {
5868         u8         status[0x8];
5869         u8         reserved_at_8[0x18];
5870
5871         u8         syndrome[0x20];
5872
5873         u8         reserved_at_40[0x40];
5874 };
5875
5876 struct mlx5_ifc_destroy_srq_in_bits {
5877         u8         opcode[0x10];
5878         u8         reserved_at_10[0x10];
5879
5880         u8         reserved_at_20[0x10];
5881         u8         op_mod[0x10];
5882
5883         u8         reserved_at_40[0x8];
5884         u8         srqn[0x18];
5885
5886         u8         reserved_at_60[0x20];
5887 };
5888
5889 struct mlx5_ifc_destroy_sq_out_bits {
5890         u8         status[0x8];
5891         u8         reserved_at_8[0x18];
5892
5893         u8         syndrome[0x20];
5894
5895         u8         reserved_at_40[0x40];
5896 };
5897
5898 struct mlx5_ifc_destroy_sq_in_bits {
5899         u8         opcode[0x10];
5900         u8         reserved_at_10[0x10];
5901
5902         u8         reserved_at_20[0x10];
5903         u8         op_mod[0x10];
5904
5905         u8         reserved_at_40[0x8];
5906         u8         sqn[0x18];
5907
5908         u8         reserved_at_60[0x20];
5909 };
5910
5911 struct mlx5_ifc_destroy_scheduling_element_out_bits {
5912         u8         status[0x8];
5913         u8         reserved_at_8[0x18];
5914
5915         u8         syndrome[0x20];
5916
5917         u8         reserved_at_40[0x1c0];
5918 };
5919
5920 struct mlx5_ifc_destroy_scheduling_element_in_bits {
5921         u8         opcode[0x10];
5922         u8         reserved_at_10[0x10];
5923
5924         u8         reserved_at_20[0x10];
5925         u8         op_mod[0x10];
5926
5927         u8         scheduling_hierarchy[0x8];
5928         u8         reserved_at_48[0x18];
5929
5930         u8         scheduling_element_id[0x20];
5931
5932         u8         reserved_at_80[0x180];
5933 };
5934
5935 struct mlx5_ifc_destroy_rqt_out_bits {
5936         u8         status[0x8];
5937         u8         reserved_at_8[0x18];
5938
5939         u8         syndrome[0x20];
5940
5941         u8         reserved_at_40[0x40];
5942 };
5943
5944 struct mlx5_ifc_destroy_rqt_in_bits {
5945         u8         opcode[0x10];
5946         u8         reserved_at_10[0x10];
5947
5948         u8         reserved_at_20[0x10];
5949         u8         op_mod[0x10];
5950
5951         u8         reserved_at_40[0x8];
5952         u8         rqtn[0x18];
5953
5954         u8         reserved_at_60[0x20];
5955 };
5956
5957 struct mlx5_ifc_destroy_rq_out_bits {
5958         u8         status[0x8];
5959         u8         reserved_at_8[0x18];
5960
5961         u8         syndrome[0x20];
5962
5963         u8         reserved_at_40[0x40];
5964 };
5965
5966 struct mlx5_ifc_destroy_rq_in_bits {
5967         u8         opcode[0x10];
5968         u8         reserved_at_10[0x10];
5969
5970         u8         reserved_at_20[0x10];
5971         u8         op_mod[0x10];
5972
5973         u8         reserved_at_40[0x8];
5974         u8         rqn[0x18];
5975
5976         u8         reserved_at_60[0x20];
5977 };
5978
5979 struct mlx5_ifc_set_delay_drop_params_in_bits {
5980         u8         opcode[0x10];
5981         u8         reserved_at_10[0x10];
5982
5983         u8         reserved_at_20[0x10];
5984         u8         op_mod[0x10];
5985
5986         u8         reserved_at_40[0x20];
5987
5988         u8         reserved_at_60[0x10];
5989         u8         delay_drop_timeout[0x10];
5990 };
5991
5992 struct mlx5_ifc_set_delay_drop_params_out_bits {
5993         u8         status[0x8];
5994         u8         reserved_at_8[0x18];
5995
5996         u8         syndrome[0x20];
5997
5998         u8         reserved_at_40[0x40];
5999 };
6000
6001 struct mlx5_ifc_destroy_rmp_out_bits {
6002         u8         status[0x8];
6003         u8         reserved_at_8[0x18];
6004
6005         u8         syndrome[0x20];
6006
6007         u8         reserved_at_40[0x40];
6008 };
6009
6010 struct mlx5_ifc_destroy_rmp_in_bits {
6011         u8         opcode[0x10];
6012         u8         reserved_at_10[0x10];
6013
6014         u8         reserved_at_20[0x10];
6015         u8         op_mod[0x10];
6016
6017         u8         reserved_at_40[0x8];
6018         u8         rmpn[0x18];
6019
6020         u8         reserved_at_60[0x20];
6021 };
6022
6023 struct mlx5_ifc_destroy_qp_out_bits {
6024         u8         status[0x8];
6025         u8         reserved_at_8[0x18];
6026
6027         u8         syndrome[0x20];
6028
6029         u8         reserved_at_40[0x40];
6030 };
6031
6032 struct mlx5_ifc_destroy_qp_in_bits {
6033         u8         opcode[0x10];
6034         u8         reserved_at_10[0x10];
6035
6036         u8         reserved_at_20[0x10];
6037         u8         op_mod[0x10];
6038
6039         u8         reserved_at_40[0x8];
6040         u8         qpn[0x18];
6041
6042         u8         reserved_at_60[0x20];
6043 };
6044
6045 struct mlx5_ifc_destroy_psv_out_bits {
6046         u8         status[0x8];
6047         u8         reserved_at_8[0x18];
6048
6049         u8         syndrome[0x20];
6050
6051         u8         reserved_at_40[0x40];
6052 };
6053
6054 struct mlx5_ifc_destroy_psv_in_bits {
6055         u8         opcode[0x10];
6056         u8         reserved_at_10[0x10];
6057
6058         u8         reserved_at_20[0x10];
6059         u8         op_mod[0x10];
6060
6061         u8         reserved_at_40[0x8];
6062         u8         psvn[0x18];
6063
6064         u8         reserved_at_60[0x20];
6065 };
6066
6067 struct mlx5_ifc_destroy_mkey_out_bits {
6068         u8         status[0x8];
6069         u8         reserved_at_8[0x18];
6070
6071         u8         syndrome[0x20];
6072
6073         u8         reserved_at_40[0x40];
6074 };
6075
6076 struct mlx5_ifc_destroy_mkey_in_bits {
6077         u8         opcode[0x10];
6078         u8         reserved_at_10[0x10];
6079
6080         u8         reserved_at_20[0x10];
6081         u8         op_mod[0x10];
6082
6083         u8         reserved_at_40[0x8];
6084         u8         mkey_index[0x18];
6085
6086         u8         reserved_at_60[0x20];
6087 };
6088
6089 struct mlx5_ifc_destroy_flow_table_out_bits {
6090         u8         status[0x8];
6091         u8         reserved_at_8[0x18];
6092
6093         u8         syndrome[0x20];
6094
6095         u8         reserved_at_40[0x40];
6096 };
6097
6098 struct mlx5_ifc_destroy_flow_table_in_bits {
6099         u8         opcode[0x10];
6100         u8         reserved_at_10[0x10];
6101
6102         u8         reserved_at_20[0x10];
6103         u8         op_mod[0x10];
6104
6105         u8         other_vport[0x1];
6106         u8         reserved_at_41[0xf];
6107         u8         vport_number[0x10];
6108
6109         u8         reserved_at_60[0x20];
6110
6111         u8         table_type[0x8];
6112         u8         reserved_at_88[0x18];
6113
6114         u8         reserved_at_a0[0x8];
6115         u8         table_id[0x18];
6116
6117         u8         reserved_at_c0[0x140];
6118 };
6119
6120 struct mlx5_ifc_destroy_flow_group_out_bits {
6121         u8         status[0x8];
6122         u8         reserved_at_8[0x18];
6123
6124         u8         syndrome[0x20];
6125
6126         u8         reserved_at_40[0x40];
6127 };
6128
6129 struct mlx5_ifc_destroy_flow_group_in_bits {
6130         u8         opcode[0x10];
6131         u8         reserved_at_10[0x10];
6132
6133         u8         reserved_at_20[0x10];
6134         u8         op_mod[0x10];
6135
6136         u8         other_vport[0x1];
6137         u8         reserved_at_41[0xf];
6138         u8         vport_number[0x10];
6139
6140         u8         reserved_at_60[0x20];
6141
6142         u8         table_type[0x8];
6143         u8         reserved_at_88[0x18];
6144
6145         u8         reserved_at_a0[0x8];
6146         u8         table_id[0x18];
6147
6148         u8         group_id[0x20];
6149
6150         u8         reserved_at_e0[0x120];
6151 };
6152
6153 struct mlx5_ifc_destroy_eq_out_bits {
6154         u8         status[0x8];
6155         u8         reserved_at_8[0x18];
6156
6157         u8         syndrome[0x20];
6158
6159         u8         reserved_at_40[0x40];
6160 };
6161
6162 struct mlx5_ifc_destroy_eq_in_bits {
6163         u8         opcode[0x10];
6164         u8         reserved_at_10[0x10];
6165
6166         u8         reserved_at_20[0x10];
6167         u8         op_mod[0x10];
6168
6169         u8         reserved_at_40[0x18];
6170         u8         eq_number[0x8];
6171
6172         u8         reserved_at_60[0x20];
6173 };
6174
6175 struct mlx5_ifc_destroy_dct_out_bits {
6176         u8         status[0x8];
6177         u8         reserved_at_8[0x18];
6178
6179         u8         syndrome[0x20];
6180
6181         u8         reserved_at_40[0x40];
6182 };
6183
6184 struct mlx5_ifc_destroy_dct_in_bits {
6185         u8         opcode[0x10];
6186         u8         reserved_at_10[0x10];
6187
6188         u8         reserved_at_20[0x10];
6189         u8         op_mod[0x10];
6190
6191         u8         reserved_at_40[0x8];
6192         u8         dctn[0x18];
6193
6194         u8         reserved_at_60[0x20];
6195 };
6196
6197 struct mlx5_ifc_destroy_cq_out_bits {
6198         u8         status[0x8];
6199         u8         reserved_at_8[0x18];
6200
6201         u8         syndrome[0x20];
6202
6203         u8         reserved_at_40[0x40];
6204 };
6205
6206 struct mlx5_ifc_destroy_cq_in_bits {
6207         u8         opcode[0x10];
6208         u8         reserved_at_10[0x10];
6209
6210         u8         reserved_at_20[0x10];
6211         u8         op_mod[0x10];
6212
6213         u8         reserved_at_40[0x8];
6214         u8         cqn[0x18];
6215
6216         u8         reserved_at_60[0x20];
6217 };
6218
6219 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6220         u8         status[0x8];
6221         u8         reserved_at_8[0x18];
6222
6223         u8         syndrome[0x20];
6224
6225         u8         reserved_at_40[0x40];
6226 };
6227
6228 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6229         u8         opcode[0x10];
6230         u8         reserved_at_10[0x10];
6231
6232         u8         reserved_at_20[0x10];
6233         u8         op_mod[0x10];
6234
6235         u8         reserved_at_40[0x20];
6236
6237         u8         reserved_at_60[0x10];
6238         u8         vxlan_udp_port[0x10];
6239 };
6240
6241 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6242         u8         status[0x8];
6243         u8         reserved_at_8[0x18];
6244
6245         u8         syndrome[0x20];
6246
6247         u8         reserved_at_40[0x40];
6248 };
6249
6250 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6251         u8         opcode[0x10];
6252         u8         reserved_at_10[0x10];
6253
6254         u8         reserved_at_20[0x10];
6255         u8         op_mod[0x10];
6256
6257         u8         reserved_at_40[0x60];
6258
6259         u8         reserved_at_a0[0x8];
6260         u8         table_index[0x18];
6261
6262         u8         reserved_at_c0[0x140];
6263 };
6264
6265 struct mlx5_ifc_delete_fte_out_bits {
6266         u8         status[0x8];
6267         u8         reserved_at_8[0x18];
6268
6269         u8         syndrome[0x20];
6270
6271         u8         reserved_at_40[0x40];
6272 };
6273
6274 struct mlx5_ifc_delete_fte_in_bits {
6275         u8         opcode[0x10];
6276         u8         reserved_at_10[0x10];
6277
6278         u8         reserved_at_20[0x10];
6279         u8         op_mod[0x10];
6280
6281         u8         other_vport[0x1];
6282         u8         reserved_at_41[0xf];
6283         u8         vport_number[0x10];
6284
6285         u8         reserved_at_60[0x20];
6286
6287         u8         table_type[0x8];
6288         u8         reserved_at_88[0x18];
6289
6290         u8         reserved_at_a0[0x8];
6291         u8         table_id[0x18];
6292
6293         u8         reserved_at_c0[0x40];
6294
6295         u8         flow_index[0x20];
6296
6297         u8         reserved_at_120[0xe0];
6298 };
6299
6300 struct mlx5_ifc_dealloc_xrcd_out_bits {
6301         u8         status[0x8];
6302         u8         reserved_at_8[0x18];
6303
6304         u8         syndrome[0x20];
6305
6306         u8         reserved_at_40[0x40];
6307 };
6308
6309 struct mlx5_ifc_dealloc_xrcd_in_bits {
6310         u8         opcode[0x10];
6311         u8         reserved_at_10[0x10];
6312
6313         u8         reserved_at_20[0x10];
6314         u8         op_mod[0x10];
6315
6316         u8         reserved_at_40[0x8];
6317         u8         xrcd[0x18];
6318
6319         u8         reserved_at_60[0x20];
6320 };
6321
6322 struct mlx5_ifc_dealloc_uar_out_bits {
6323         u8         status[0x8];
6324         u8         reserved_at_8[0x18];
6325
6326         u8         syndrome[0x20];
6327
6328         u8         reserved_at_40[0x40];
6329 };
6330
6331 struct mlx5_ifc_dealloc_uar_in_bits {
6332         u8         opcode[0x10];
6333         u8         reserved_at_10[0x10];
6334
6335         u8         reserved_at_20[0x10];
6336         u8         op_mod[0x10];
6337
6338         u8         reserved_at_40[0x8];
6339         u8         uar[0x18];
6340
6341         u8         reserved_at_60[0x20];
6342 };
6343
6344 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6345         u8         status[0x8];
6346         u8         reserved_at_8[0x18];
6347
6348         u8         syndrome[0x20];
6349
6350         u8         reserved_at_40[0x40];
6351 };
6352
6353 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6354         u8         opcode[0x10];
6355         u8         reserved_at_10[0x10];
6356
6357         u8         reserved_at_20[0x10];
6358         u8         op_mod[0x10];
6359
6360         u8         reserved_at_40[0x8];
6361         u8         transport_domain[0x18];
6362
6363         u8         reserved_at_60[0x20];
6364 };
6365
6366 struct mlx5_ifc_dealloc_q_counter_out_bits {
6367         u8         status[0x8];
6368         u8         reserved_at_8[0x18];
6369
6370         u8         syndrome[0x20];
6371
6372         u8         reserved_at_40[0x40];
6373 };
6374
6375 struct mlx5_ifc_dealloc_q_counter_in_bits {
6376         u8         opcode[0x10];
6377         u8         reserved_at_10[0x10];
6378
6379         u8         reserved_at_20[0x10];
6380         u8         op_mod[0x10];
6381
6382         u8         reserved_at_40[0x18];
6383         u8         counter_set_id[0x8];
6384
6385         u8         reserved_at_60[0x20];
6386 };
6387
6388 struct mlx5_ifc_dealloc_pd_out_bits {
6389         u8         status[0x8];
6390         u8         reserved_at_8[0x18];
6391
6392         u8         syndrome[0x20];
6393
6394         u8         reserved_at_40[0x40];
6395 };
6396
6397 struct mlx5_ifc_dealloc_pd_in_bits {
6398         u8         opcode[0x10];
6399         u8         reserved_at_10[0x10];
6400
6401         u8         reserved_at_20[0x10];
6402         u8         op_mod[0x10];
6403
6404         u8         reserved_at_40[0x8];
6405         u8         pd[0x18];
6406
6407         u8         reserved_at_60[0x20];
6408 };
6409
6410 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6411         u8         status[0x8];
6412         u8         reserved_at_8[0x18];
6413
6414         u8         syndrome[0x20];
6415
6416         u8         reserved_at_40[0x40];
6417 };
6418
6419 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6420         u8         opcode[0x10];
6421         u8         reserved_at_10[0x10];
6422
6423         u8         reserved_at_20[0x10];
6424         u8         op_mod[0x10];
6425
6426         u8         flow_counter_id[0x20];
6427
6428         u8         reserved_at_60[0x20];
6429 };
6430
6431 struct mlx5_ifc_create_xrq_out_bits {
6432         u8         status[0x8];
6433         u8         reserved_at_8[0x18];
6434
6435         u8         syndrome[0x20];
6436
6437         u8         reserved_at_40[0x8];
6438         u8         xrqn[0x18];
6439
6440         u8         reserved_at_60[0x20];
6441 };
6442
6443 struct mlx5_ifc_create_xrq_in_bits {
6444         u8         opcode[0x10];
6445         u8         reserved_at_10[0x10];
6446
6447         u8         reserved_at_20[0x10];
6448         u8         op_mod[0x10];
6449
6450         u8         reserved_at_40[0x40];
6451
6452         struct mlx5_ifc_xrqc_bits xrq_context;
6453 };
6454
6455 struct mlx5_ifc_create_xrc_srq_out_bits {
6456         u8         status[0x8];
6457         u8         reserved_at_8[0x18];
6458
6459         u8         syndrome[0x20];
6460
6461         u8         reserved_at_40[0x8];
6462         u8         xrc_srqn[0x18];
6463
6464         u8         reserved_at_60[0x20];
6465 };
6466
6467 struct mlx5_ifc_create_xrc_srq_in_bits {
6468         u8         opcode[0x10];
6469         u8         reserved_at_10[0x10];
6470
6471         u8         reserved_at_20[0x10];
6472         u8         op_mod[0x10];
6473
6474         u8         reserved_at_40[0x40];
6475
6476         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6477
6478         u8         reserved_at_280[0x600];
6479
6480         u8         pas[0][0x40];
6481 };
6482
6483 struct mlx5_ifc_create_tis_out_bits {
6484         u8         status[0x8];
6485         u8         reserved_at_8[0x18];
6486
6487         u8         syndrome[0x20];
6488
6489         u8         reserved_at_40[0x8];
6490         u8         tisn[0x18];
6491
6492         u8         reserved_at_60[0x20];
6493 };
6494
6495 struct mlx5_ifc_create_tis_in_bits {
6496         u8         opcode[0x10];
6497         u8         reserved_at_10[0x10];
6498
6499         u8         reserved_at_20[0x10];
6500         u8         op_mod[0x10];
6501
6502         u8         reserved_at_40[0xc0];
6503
6504         struct mlx5_ifc_tisc_bits ctx;
6505 };
6506
6507 struct mlx5_ifc_create_tir_out_bits {
6508         u8         status[0x8];
6509         u8         reserved_at_8[0x18];
6510
6511         u8         syndrome[0x20];
6512
6513         u8         reserved_at_40[0x8];
6514         u8         tirn[0x18];
6515
6516         u8         reserved_at_60[0x20];
6517 };
6518
6519 struct mlx5_ifc_create_tir_in_bits {
6520         u8         opcode[0x10];
6521         u8         reserved_at_10[0x10];
6522
6523         u8         reserved_at_20[0x10];
6524         u8         op_mod[0x10];
6525
6526         u8         reserved_at_40[0xc0];
6527
6528         struct mlx5_ifc_tirc_bits ctx;
6529 };
6530
6531 struct mlx5_ifc_create_srq_out_bits {
6532         u8         status[0x8];
6533         u8         reserved_at_8[0x18];
6534
6535         u8         syndrome[0x20];
6536
6537         u8         reserved_at_40[0x8];
6538         u8         srqn[0x18];
6539
6540         u8         reserved_at_60[0x20];
6541 };
6542
6543 struct mlx5_ifc_create_srq_in_bits {
6544         u8         opcode[0x10];
6545         u8         reserved_at_10[0x10];
6546
6547         u8         reserved_at_20[0x10];
6548         u8         op_mod[0x10];
6549
6550         u8         reserved_at_40[0x40];
6551
6552         struct mlx5_ifc_srqc_bits srq_context_entry;
6553
6554         u8         reserved_at_280[0x600];
6555
6556         u8         pas[0][0x40];
6557 };
6558
6559 struct mlx5_ifc_create_sq_out_bits {
6560         u8         status[0x8];
6561         u8         reserved_at_8[0x18];
6562
6563         u8         syndrome[0x20];
6564
6565         u8         reserved_at_40[0x8];
6566         u8         sqn[0x18];
6567
6568         u8         reserved_at_60[0x20];
6569 };
6570
6571 struct mlx5_ifc_create_sq_in_bits {
6572         u8         opcode[0x10];
6573         u8         reserved_at_10[0x10];
6574
6575         u8         reserved_at_20[0x10];
6576         u8         op_mod[0x10];
6577
6578         u8         reserved_at_40[0xc0];
6579
6580         struct mlx5_ifc_sqc_bits ctx;
6581 };
6582
6583 struct mlx5_ifc_create_scheduling_element_out_bits {
6584         u8         status[0x8];
6585         u8         reserved_at_8[0x18];
6586
6587         u8         syndrome[0x20];
6588
6589         u8         reserved_at_40[0x40];
6590
6591         u8         scheduling_element_id[0x20];
6592
6593         u8         reserved_at_a0[0x160];
6594 };
6595
6596 struct mlx5_ifc_create_scheduling_element_in_bits {
6597         u8         opcode[0x10];
6598         u8         reserved_at_10[0x10];
6599
6600         u8         reserved_at_20[0x10];
6601         u8         op_mod[0x10];
6602
6603         u8         scheduling_hierarchy[0x8];
6604         u8         reserved_at_48[0x18];
6605
6606         u8         reserved_at_60[0xa0];
6607
6608         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6609
6610         u8         reserved_at_300[0x100];
6611 };
6612
6613 struct mlx5_ifc_create_rqt_out_bits {
6614         u8         status[0x8];
6615         u8         reserved_at_8[0x18];
6616
6617         u8         syndrome[0x20];
6618
6619         u8         reserved_at_40[0x8];
6620         u8         rqtn[0x18];
6621
6622         u8         reserved_at_60[0x20];
6623 };
6624
6625 struct mlx5_ifc_create_rqt_in_bits {
6626         u8         opcode[0x10];
6627         u8         reserved_at_10[0x10];
6628
6629         u8         reserved_at_20[0x10];
6630         u8         op_mod[0x10];
6631
6632         u8         reserved_at_40[0xc0];
6633
6634         struct mlx5_ifc_rqtc_bits rqt_context;
6635 };
6636
6637 struct mlx5_ifc_create_rq_out_bits {
6638         u8         status[0x8];
6639         u8         reserved_at_8[0x18];
6640
6641         u8         syndrome[0x20];
6642
6643         u8         reserved_at_40[0x8];
6644         u8         rqn[0x18];
6645
6646         u8         reserved_at_60[0x20];
6647 };
6648
6649 struct mlx5_ifc_create_rq_in_bits {
6650         u8         opcode[0x10];
6651         u8         reserved_at_10[0x10];
6652
6653         u8         reserved_at_20[0x10];
6654         u8         op_mod[0x10];
6655
6656         u8         reserved_at_40[0xc0];
6657
6658         struct mlx5_ifc_rqc_bits ctx;
6659 };
6660
6661 struct mlx5_ifc_create_rmp_out_bits {
6662         u8         status[0x8];
6663         u8         reserved_at_8[0x18];
6664
6665         u8         syndrome[0x20];
6666
6667         u8         reserved_at_40[0x8];
6668         u8         rmpn[0x18];
6669
6670         u8         reserved_at_60[0x20];
6671 };
6672
6673 struct mlx5_ifc_create_rmp_in_bits {
6674         u8         opcode[0x10];
6675         u8         reserved_at_10[0x10];
6676
6677         u8         reserved_at_20[0x10];
6678         u8         op_mod[0x10];
6679
6680         u8         reserved_at_40[0xc0];
6681
6682         struct mlx5_ifc_rmpc_bits ctx;
6683 };
6684
6685 struct mlx5_ifc_create_qp_out_bits {
6686         u8         status[0x8];
6687         u8         reserved_at_8[0x18];
6688
6689         u8         syndrome[0x20];
6690
6691         u8         reserved_at_40[0x8];
6692         u8         qpn[0x18];
6693
6694         u8         reserved_at_60[0x20];
6695 };
6696
6697 struct mlx5_ifc_create_qp_in_bits {
6698         u8         opcode[0x10];
6699         u8         reserved_at_10[0x10];
6700
6701         u8         reserved_at_20[0x10];
6702         u8         op_mod[0x10];
6703
6704         u8         reserved_at_40[0x40];
6705
6706         u8         opt_param_mask[0x20];
6707
6708         u8         reserved_at_a0[0x20];
6709
6710         struct mlx5_ifc_qpc_bits qpc;
6711
6712         u8         reserved_at_800[0x80];
6713
6714         u8         pas[0][0x40];
6715 };
6716
6717 struct mlx5_ifc_create_psv_out_bits {
6718         u8         status[0x8];
6719         u8         reserved_at_8[0x18];
6720
6721         u8         syndrome[0x20];
6722
6723         u8         reserved_at_40[0x40];
6724
6725         u8         reserved_at_80[0x8];
6726         u8         psv0_index[0x18];
6727
6728         u8         reserved_at_a0[0x8];
6729         u8         psv1_index[0x18];
6730
6731         u8         reserved_at_c0[0x8];
6732         u8         psv2_index[0x18];
6733
6734         u8         reserved_at_e0[0x8];
6735         u8         psv3_index[0x18];
6736 };
6737
6738 struct mlx5_ifc_create_psv_in_bits {
6739         u8         opcode[0x10];
6740         u8         reserved_at_10[0x10];
6741
6742         u8         reserved_at_20[0x10];
6743         u8         op_mod[0x10];
6744
6745         u8         num_psv[0x4];
6746         u8         reserved_at_44[0x4];
6747         u8         pd[0x18];
6748
6749         u8         reserved_at_60[0x20];
6750 };
6751
6752 struct mlx5_ifc_create_mkey_out_bits {
6753         u8         status[0x8];
6754         u8         reserved_at_8[0x18];
6755
6756         u8         syndrome[0x20];
6757
6758         u8         reserved_at_40[0x8];
6759         u8         mkey_index[0x18];
6760
6761         u8         reserved_at_60[0x20];
6762 };
6763
6764 struct mlx5_ifc_create_mkey_in_bits {
6765         u8         opcode[0x10];
6766         u8         reserved_at_10[0x10];
6767
6768         u8         reserved_at_20[0x10];
6769         u8         op_mod[0x10];
6770
6771         u8         reserved_at_40[0x20];
6772
6773         u8         pg_access[0x1];
6774         u8         reserved_at_61[0x1f];
6775
6776         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6777
6778         u8         reserved_at_280[0x80];
6779
6780         u8         translations_octword_actual_size[0x20];
6781
6782         u8         reserved_at_320[0x560];
6783
6784         u8         klm_pas_mtt[0][0x20];
6785 };
6786
6787 struct mlx5_ifc_create_flow_table_out_bits {
6788         u8         status[0x8];
6789         u8         reserved_at_8[0x18];
6790
6791         u8         syndrome[0x20];
6792
6793         u8         reserved_at_40[0x8];
6794         u8         table_id[0x18];
6795
6796         u8         reserved_at_60[0x20];
6797 };
6798
6799 struct mlx5_ifc_flow_table_context_bits {
6800         u8         encap_en[0x1];
6801         u8         decap_en[0x1];
6802         u8         reserved_at_2[0x2];
6803         u8         table_miss_action[0x4];
6804         u8         level[0x8];
6805         u8         reserved_at_10[0x8];
6806         u8         log_size[0x8];
6807
6808         u8         reserved_at_20[0x8];
6809         u8         table_miss_id[0x18];
6810
6811         u8         reserved_at_40[0x8];
6812         u8         lag_master_next_table_id[0x18];
6813
6814         u8         reserved_at_60[0xe0];
6815 };
6816
6817 struct mlx5_ifc_create_flow_table_in_bits {
6818         u8         opcode[0x10];
6819         u8         reserved_at_10[0x10];
6820
6821         u8         reserved_at_20[0x10];
6822         u8         op_mod[0x10];
6823
6824         u8         other_vport[0x1];
6825         u8         reserved_at_41[0xf];
6826         u8         vport_number[0x10];
6827
6828         u8         reserved_at_60[0x20];
6829
6830         u8         table_type[0x8];
6831         u8         reserved_at_88[0x18];
6832
6833         u8         reserved_at_a0[0x20];
6834
6835         struct mlx5_ifc_flow_table_context_bits flow_table_context;
6836 };
6837
6838 struct mlx5_ifc_create_flow_group_out_bits {
6839         u8         status[0x8];
6840         u8         reserved_at_8[0x18];
6841
6842         u8         syndrome[0x20];
6843
6844         u8         reserved_at_40[0x8];
6845         u8         group_id[0x18];
6846
6847         u8         reserved_at_60[0x20];
6848 };
6849
6850 enum {
6851         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6852         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6853         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6854 };
6855
6856 struct mlx5_ifc_create_flow_group_in_bits {
6857         u8         opcode[0x10];
6858         u8         reserved_at_10[0x10];
6859
6860         u8         reserved_at_20[0x10];
6861         u8         op_mod[0x10];
6862
6863         u8         other_vport[0x1];
6864         u8         reserved_at_41[0xf];
6865         u8         vport_number[0x10];
6866
6867         u8         reserved_at_60[0x20];
6868
6869         u8         table_type[0x8];
6870         u8         reserved_at_88[0x18];
6871
6872         u8         reserved_at_a0[0x8];
6873         u8         table_id[0x18];
6874
6875         u8         reserved_at_c0[0x20];
6876
6877         u8         start_flow_index[0x20];
6878
6879         u8         reserved_at_100[0x20];
6880
6881         u8         end_flow_index[0x20];
6882
6883         u8         reserved_at_140[0xa0];
6884
6885         u8         reserved_at_1e0[0x18];
6886         u8         match_criteria_enable[0x8];
6887
6888         struct mlx5_ifc_fte_match_param_bits match_criteria;
6889
6890         u8         reserved_at_1200[0xe00];
6891 };
6892
6893 struct mlx5_ifc_create_eq_out_bits {
6894         u8         status[0x8];
6895         u8         reserved_at_8[0x18];
6896
6897         u8         syndrome[0x20];
6898
6899         u8         reserved_at_40[0x18];
6900         u8         eq_number[0x8];
6901
6902         u8         reserved_at_60[0x20];
6903 };
6904
6905 struct mlx5_ifc_create_eq_in_bits {
6906         u8         opcode[0x10];
6907         u8         reserved_at_10[0x10];
6908
6909         u8         reserved_at_20[0x10];
6910         u8         op_mod[0x10];
6911
6912         u8         reserved_at_40[0x40];
6913
6914         struct mlx5_ifc_eqc_bits eq_context_entry;
6915
6916         u8         reserved_at_280[0x40];
6917
6918         u8         event_bitmask[0x40];
6919
6920         u8         reserved_at_300[0x580];
6921
6922         u8         pas[0][0x40];
6923 };
6924
6925 struct mlx5_ifc_create_dct_out_bits {
6926         u8         status[0x8];
6927         u8         reserved_at_8[0x18];
6928
6929         u8         syndrome[0x20];
6930
6931         u8         reserved_at_40[0x8];
6932         u8         dctn[0x18];
6933
6934         u8         reserved_at_60[0x20];
6935 };
6936
6937 struct mlx5_ifc_create_dct_in_bits {
6938         u8         opcode[0x10];
6939         u8         reserved_at_10[0x10];
6940
6941         u8         reserved_at_20[0x10];
6942         u8         op_mod[0x10];
6943
6944         u8         reserved_at_40[0x40];
6945
6946         struct mlx5_ifc_dctc_bits dct_context_entry;
6947
6948         u8         reserved_at_280[0x180];
6949 };
6950
6951 struct mlx5_ifc_create_cq_out_bits {
6952         u8         status[0x8];
6953         u8         reserved_at_8[0x18];
6954
6955         u8         syndrome[0x20];
6956
6957         u8         reserved_at_40[0x8];
6958         u8         cqn[0x18];
6959
6960         u8         reserved_at_60[0x20];
6961 };
6962
6963 struct mlx5_ifc_create_cq_in_bits {
6964         u8         opcode[0x10];
6965         u8         reserved_at_10[0x10];
6966
6967         u8         reserved_at_20[0x10];
6968         u8         op_mod[0x10];
6969
6970         u8         reserved_at_40[0x40];
6971
6972         struct mlx5_ifc_cqc_bits cq_context;
6973
6974         u8         reserved_at_280[0x600];
6975
6976         u8         pas[0][0x40];
6977 };
6978
6979 struct mlx5_ifc_config_int_moderation_out_bits {
6980         u8         status[0x8];
6981         u8         reserved_at_8[0x18];
6982
6983         u8         syndrome[0x20];
6984
6985         u8         reserved_at_40[0x4];
6986         u8         min_delay[0xc];
6987         u8         int_vector[0x10];
6988
6989         u8         reserved_at_60[0x20];
6990 };
6991
6992 enum {
6993         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
6994         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
6995 };
6996
6997 struct mlx5_ifc_config_int_moderation_in_bits {
6998         u8         opcode[0x10];
6999         u8         reserved_at_10[0x10];
7000
7001         u8         reserved_at_20[0x10];
7002         u8         op_mod[0x10];
7003
7004         u8         reserved_at_40[0x4];
7005         u8         min_delay[0xc];
7006         u8         int_vector[0x10];
7007
7008         u8         reserved_at_60[0x20];
7009 };
7010
7011 struct mlx5_ifc_attach_to_mcg_out_bits {
7012         u8         status[0x8];
7013         u8         reserved_at_8[0x18];
7014
7015         u8         syndrome[0x20];
7016
7017         u8         reserved_at_40[0x40];
7018 };
7019
7020 struct mlx5_ifc_attach_to_mcg_in_bits {
7021         u8         opcode[0x10];
7022         u8         reserved_at_10[0x10];
7023
7024         u8         reserved_at_20[0x10];
7025         u8         op_mod[0x10];
7026
7027         u8         reserved_at_40[0x8];
7028         u8         qpn[0x18];
7029
7030         u8         reserved_at_60[0x20];
7031
7032         u8         multicast_gid[16][0x8];
7033 };
7034
7035 struct mlx5_ifc_arm_xrq_out_bits {
7036         u8         status[0x8];
7037         u8         reserved_at_8[0x18];
7038
7039         u8         syndrome[0x20];
7040
7041         u8         reserved_at_40[0x40];
7042 };
7043
7044 struct mlx5_ifc_arm_xrq_in_bits {
7045         u8         opcode[0x10];
7046         u8         reserved_at_10[0x10];
7047
7048         u8         reserved_at_20[0x10];
7049         u8         op_mod[0x10];
7050
7051         u8         reserved_at_40[0x8];
7052         u8         xrqn[0x18];
7053
7054         u8         reserved_at_60[0x10];
7055         u8         lwm[0x10];
7056 };
7057
7058 struct mlx5_ifc_arm_xrc_srq_out_bits {
7059         u8         status[0x8];
7060         u8         reserved_at_8[0x18];
7061
7062         u8         syndrome[0x20];
7063
7064         u8         reserved_at_40[0x40];
7065 };
7066
7067 enum {
7068         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
7069 };
7070
7071 struct mlx5_ifc_arm_xrc_srq_in_bits {
7072         u8         opcode[0x10];
7073         u8         reserved_at_10[0x10];
7074
7075         u8         reserved_at_20[0x10];
7076         u8         op_mod[0x10];
7077
7078         u8         reserved_at_40[0x8];
7079         u8         xrc_srqn[0x18];
7080
7081         u8         reserved_at_60[0x10];
7082         u8         lwm[0x10];
7083 };
7084
7085 struct mlx5_ifc_arm_rq_out_bits {
7086         u8         status[0x8];
7087         u8         reserved_at_8[0x18];
7088
7089         u8         syndrome[0x20];
7090
7091         u8         reserved_at_40[0x40];
7092 };
7093
7094 enum {
7095         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7096         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
7097 };
7098
7099 struct mlx5_ifc_arm_rq_in_bits {
7100         u8         opcode[0x10];
7101         u8         reserved_at_10[0x10];
7102
7103         u8         reserved_at_20[0x10];
7104         u8         op_mod[0x10];
7105
7106         u8         reserved_at_40[0x8];
7107         u8         srq_number[0x18];
7108
7109         u8         reserved_at_60[0x10];
7110         u8         lwm[0x10];
7111 };
7112
7113 struct mlx5_ifc_arm_dct_out_bits {
7114         u8         status[0x8];
7115         u8         reserved_at_8[0x18];
7116
7117         u8         syndrome[0x20];
7118
7119         u8         reserved_at_40[0x40];
7120 };
7121
7122 struct mlx5_ifc_arm_dct_in_bits {
7123         u8         opcode[0x10];
7124         u8         reserved_at_10[0x10];
7125
7126         u8         reserved_at_20[0x10];
7127         u8         op_mod[0x10];
7128
7129         u8         reserved_at_40[0x8];
7130         u8         dct_number[0x18];
7131
7132         u8         reserved_at_60[0x20];
7133 };
7134
7135 struct mlx5_ifc_alloc_xrcd_out_bits {
7136         u8         status[0x8];
7137         u8         reserved_at_8[0x18];
7138
7139         u8         syndrome[0x20];
7140
7141         u8         reserved_at_40[0x8];
7142         u8         xrcd[0x18];
7143
7144         u8         reserved_at_60[0x20];
7145 };
7146
7147 struct mlx5_ifc_alloc_xrcd_in_bits {
7148         u8         opcode[0x10];
7149         u8         reserved_at_10[0x10];
7150
7151         u8         reserved_at_20[0x10];
7152         u8         op_mod[0x10];
7153
7154         u8         reserved_at_40[0x40];
7155 };
7156
7157 struct mlx5_ifc_alloc_uar_out_bits {
7158         u8         status[0x8];
7159         u8         reserved_at_8[0x18];
7160
7161         u8         syndrome[0x20];
7162
7163         u8         reserved_at_40[0x8];
7164         u8         uar[0x18];
7165
7166         u8         reserved_at_60[0x20];
7167 };
7168
7169 struct mlx5_ifc_alloc_uar_in_bits {
7170         u8         opcode[0x10];
7171         u8         reserved_at_10[0x10];
7172
7173         u8         reserved_at_20[0x10];
7174         u8         op_mod[0x10];
7175
7176         u8         reserved_at_40[0x40];
7177 };
7178
7179 struct mlx5_ifc_alloc_transport_domain_out_bits {
7180         u8         status[0x8];
7181         u8         reserved_at_8[0x18];
7182
7183         u8         syndrome[0x20];
7184
7185         u8         reserved_at_40[0x8];
7186         u8         transport_domain[0x18];
7187
7188         u8         reserved_at_60[0x20];
7189 };
7190
7191 struct mlx5_ifc_alloc_transport_domain_in_bits {
7192         u8         opcode[0x10];
7193         u8         reserved_at_10[0x10];
7194
7195         u8         reserved_at_20[0x10];
7196         u8         op_mod[0x10];
7197
7198         u8         reserved_at_40[0x40];
7199 };
7200
7201 struct mlx5_ifc_alloc_q_counter_out_bits {
7202         u8         status[0x8];
7203         u8         reserved_at_8[0x18];
7204
7205         u8         syndrome[0x20];
7206
7207         u8         reserved_at_40[0x18];
7208         u8         counter_set_id[0x8];
7209
7210         u8         reserved_at_60[0x20];
7211 };
7212
7213 struct mlx5_ifc_alloc_q_counter_in_bits {
7214         u8         opcode[0x10];
7215         u8         reserved_at_10[0x10];
7216
7217         u8         reserved_at_20[0x10];
7218         u8         op_mod[0x10];
7219
7220         u8         reserved_at_40[0x40];
7221 };
7222
7223 struct mlx5_ifc_alloc_pd_out_bits {
7224         u8         status[0x8];
7225         u8         reserved_at_8[0x18];
7226
7227         u8         syndrome[0x20];
7228
7229         u8         reserved_at_40[0x8];
7230         u8         pd[0x18];
7231
7232         u8         reserved_at_60[0x20];
7233 };
7234
7235 struct mlx5_ifc_alloc_pd_in_bits {
7236         u8         opcode[0x10];
7237         u8         reserved_at_10[0x10];
7238
7239         u8         reserved_at_20[0x10];
7240         u8         op_mod[0x10];
7241
7242         u8         reserved_at_40[0x40];
7243 };
7244
7245 struct mlx5_ifc_alloc_flow_counter_out_bits {
7246         u8         status[0x8];
7247         u8         reserved_at_8[0x18];
7248
7249         u8         syndrome[0x20];
7250
7251         u8         flow_counter_id[0x20];
7252
7253         u8         reserved_at_60[0x20];
7254 };
7255
7256 struct mlx5_ifc_alloc_flow_counter_in_bits {
7257         u8         opcode[0x10];
7258         u8         reserved_at_10[0x10];
7259
7260         u8         reserved_at_20[0x10];
7261         u8         op_mod[0x10];
7262
7263         u8         reserved_at_40[0x40];
7264 };
7265
7266 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7267         u8         status[0x8];
7268         u8         reserved_at_8[0x18];
7269
7270         u8         syndrome[0x20];
7271
7272         u8         reserved_at_40[0x40];
7273 };
7274
7275 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7276         u8         opcode[0x10];
7277         u8         reserved_at_10[0x10];
7278
7279         u8         reserved_at_20[0x10];
7280         u8         op_mod[0x10];
7281
7282         u8         reserved_at_40[0x20];
7283
7284         u8         reserved_at_60[0x10];
7285         u8         vxlan_udp_port[0x10];
7286 };
7287
7288 struct mlx5_ifc_set_pp_rate_limit_out_bits {
7289         u8         status[0x8];
7290         u8         reserved_at_8[0x18];
7291
7292         u8         syndrome[0x20];
7293
7294         u8         reserved_at_40[0x40];
7295 };
7296
7297 struct mlx5_ifc_set_pp_rate_limit_in_bits {
7298         u8         opcode[0x10];
7299         u8         reserved_at_10[0x10];
7300
7301         u8         reserved_at_20[0x10];
7302         u8         op_mod[0x10];
7303
7304         u8         reserved_at_40[0x10];
7305         u8         rate_limit_index[0x10];
7306
7307         u8         reserved_at_60[0x20];
7308
7309         u8         rate_limit[0x20];
7310
7311         u8         reserved_at_a0[0x160];
7312 };
7313
7314 struct mlx5_ifc_access_register_out_bits {
7315         u8         status[0x8];
7316         u8         reserved_at_8[0x18];
7317
7318         u8         syndrome[0x20];
7319
7320         u8         reserved_at_40[0x40];
7321
7322         u8         register_data[0][0x20];
7323 };
7324
7325 enum {
7326         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
7327         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
7328 };
7329
7330 struct mlx5_ifc_access_register_in_bits {
7331         u8         opcode[0x10];
7332         u8         reserved_at_10[0x10];
7333
7334         u8         reserved_at_20[0x10];
7335         u8         op_mod[0x10];
7336
7337         u8         reserved_at_40[0x10];
7338         u8         register_id[0x10];
7339
7340         u8         argument[0x20];
7341
7342         u8         register_data[0][0x20];
7343 };
7344
7345 struct mlx5_ifc_sltp_reg_bits {
7346         u8         status[0x4];
7347         u8         version[0x4];
7348         u8         local_port[0x8];
7349         u8         pnat[0x2];
7350         u8         reserved_at_12[0x2];
7351         u8         lane[0x4];
7352         u8         reserved_at_18[0x8];
7353
7354         u8         reserved_at_20[0x20];
7355
7356         u8         reserved_at_40[0x7];
7357         u8         polarity[0x1];
7358         u8         ob_tap0[0x8];
7359         u8         ob_tap1[0x8];
7360         u8         ob_tap2[0x8];
7361
7362         u8         reserved_at_60[0xc];
7363         u8         ob_preemp_mode[0x4];
7364         u8         ob_reg[0x8];
7365         u8         ob_bias[0x8];
7366
7367         u8         reserved_at_80[0x20];
7368 };
7369
7370 struct mlx5_ifc_slrg_reg_bits {
7371         u8         status[0x4];
7372         u8         version[0x4];
7373         u8         local_port[0x8];
7374         u8         pnat[0x2];
7375         u8         reserved_at_12[0x2];
7376         u8         lane[0x4];
7377         u8         reserved_at_18[0x8];
7378
7379         u8         time_to_link_up[0x10];
7380         u8         reserved_at_30[0xc];
7381         u8         grade_lane_speed[0x4];
7382
7383         u8         grade_version[0x8];
7384         u8         grade[0x18];
7385
7386         u8         reserved_at_60[0x4];
7387         u8         height_grade_type[0x4];
7388         u8         height_grade[0x18];
7389
7390         u8         height_dz[0x10];
7391         u8         height_dv[0x10];
7392
7393         u8         reserved_at_a0[0x10];
7394         u8         height_sigma[0x10];
7395
7396         u8         reserved_at_c0[0x20];
7397
7398         u8         reserved_at_e0[0x4];
7399         u8         phase_grade_type[0x4];
7400         u8         phase_grade[0x18];
7401
7402         u8         reserved_at_100[0x8];
7403         u8         phase_eo_pos[0x8];
7404         u8         reserved_at_110[0x8];
7405         u8         phase_eo_neg[0x8];
7406
7407         u8         ffe_set_tested[0x10];
7408         u8         test_errors_per_lane[0x10];
7409 };
7410
7411 struct mlx5_ifc_pvlc_reg_bits {
7412         u8         reserved_at_0[0x8];
7413         u8         local_port[0x8];
7414         u8         reserved_at_10[0x10];
7415
7416         u8         reserved_at_20[0x1c];
7417         u8         vl_hw_cap[0x4];
7418
7419         u8         reserved_at_40[0x1c];
7420         u8         vl_admin[0x4];
7421
7422         u8         reserved_at_60[0x1c];
7423         u8         vl_operational[0x4];
7424 };
7425
7426 struct mlx5_ifc_pude_reg_bits {
7427         u8         swid[0x8];
7428         u8         local_port[0x8];
7429         u8         reserved_at_10[0x4];
7430         u8         admin_status[0x4];
7431         u8         reserved_at_18[0x4];
7432         u8         oper_status[0x4];
7433
7434         u8         reserved_at_20[0x60];
7435 };
7436
7437 struct mlx5_ifc_ptys_reg_bits {
7438         u8         reserved_at_0[0x1];
7439         u8         an_disable_admin[0x1];
7440         u8         an_disable_cap[0x1];
7441         u8         reserved_at_3[0x5];
7442         u8         local_port[0x8];
7443         u8         reserved_at_10[0xd];
7444         u8         proto_mask[0x3];
7445
7446         u8         an_status[0x4];
7447         u8         reserved_at_24[0x3c];
7448
7449         u8         eth_proto_capability[0x20];
7450
7451         u8         ib_link_width_capability[0x10];
7452         u8         ib_proto_capability[0x10];
7453
7454         u8         reserved_at_a0[0x20];
7455
7456         u8         eth_proto_admin[0x20];
7457
7458         u8         ib_link_width_admin[0x10];
7459         u8         ib_proto_admin[0x10];
7460
7461         u8         reserved_at_100[0x20];
7462
7463         u8         eth_proto_oper[0x20];
7464
7465         u8         ib_link_width_oper[0x10];
7466         u8         ib_proto_oper[0x10];
7467
7468         u8         reserved_at_160[0x1c];
7469         u8         connector_type[0x4];
7470
7471         u8         eth_proto_lp_advertise[0x20];
7472
7473         u8         reserved_at_1a0[0x60];
7474 };
7475
7476 struct mlx5_ifc_mlcr_reg_bits {
7477         u8         reserved_at_0[0x8];
7478         u8         local_port[0x8];
7479         u8         reserved_at_10[0x20];
7480
7481         u8         beacon_duration[0x10];
7482         u8         reserved_at_40[0x10];
7483
7484         u8         beacon_remain[0x10];
7485 };
7486
7487 struct mlx5_ifc_ptas_reg_bits {
7488         u8         reserved_at_0[0x20];
7489
7490         u8         algorithm_options[0x10];
7491         u8         reserved_at_30[0x4];
7492         u8         repetitions_mode[0x4];
7493         u8         num_of_repetitions[0x8];
7494
7495         u8         grade_version[0x8];
7496         u8         height_grade_type[0x4];
7497         u8         phase_grade_type[0x4];
7498         u8         height_grade_weight[0x8];
7499         u8         phase_grade_weight[0x8];
7500
7501         u8         gisim_measure_bits[0x10];
7502         u8         adaptive_tap_measure_bits[0x10];
7503
7504         u8         ber_bath_high_error_threshold[0x10];
7505         u8         ber_bath_mid_error_threshold[0x10];
7506
7507         u8         ber_bath_low_error_threshold[0x10];
7508         u8         one_ratio_high_threshold[0x10];
7509
7510         u8         one_ratio_high_mid_threshold[0x10];
7511         u8         one_ratio_low_mid_threshold[0x10];
7512
7513         u8         one_ratio_low_threshold[0x10];
7514         u8         ndeo_error_threshold[0x10];
7515
7516         u8         mixer_offset_step_size[0x10];
7517         u8         reserved_at_110[0x8];
7518         u8         mix90_phase_for_voltage_bath[0x8];
7519
7520         u8         mixer_offset_start[0x10];
7521         u8         mixer_offset_end[0x10];
7522
7523         u8         reserved_at_140[0x15];
7524         u8         ber_test_time[0xb];
7525 };
7526
7527 struct mlx5_ifc_pspa_reg_bits {
7528         u8         swid[0x8];
7529         u8         local_port[0x8];
7530         u8         sub_port[0x8];
7531         u8         reserved_at_18[0x8];
7532
7533         u8         reserved_at_20[0x20];
7534 };
7535
7536 struct mlx5_ifc_pqdr_reg_bits {
7537         u8         reserved_at_0[0x8];
7538         u8         local_port[0x8];
7539         u8         reserved_at_10[0x5];
7540         u8         prio[0x3];
7541         u8         reserved_at_18[0x6];
7542         u8         mode[0x2];
7543
7544         u8         reserved_at_20[0x20];
7545
7546         u8         reserved_at_40[0x10];
7547         u8         min_threshold[0x10];
7548
7549         u8         reserved_at_60[0x10];
7550         u8         max_threshold[0x10];
7551
7552         u8         reserved_at_80[0x10];
7553         u8         mark_probability_denominator[0x10];
7554
7555         u8         reserved_at_a0[0x60];
7556 };
7557
7558 struct mlx5_ifc_ppsc_reg_bits {
7559         u8         reserved_at_0[0x8];
7560         u8         local_port[0x8];
7561         u8         reserved_at_10[0x10];
7562
7563         u8         reserved_at_20[0x60];
7564
7565         u8         reserved_at_80[0x1c];
7566         u8         wrps_admin[0x4];
7567
7568         u8         reserved_at_a0[0x1c];
7569         u8         wrps_status[0x4];
7570
7571         u8         reserved_at_c0[0x8];
7572         u8         up_threshold[0x8];
7573         u8         reserved_at_d0[0x8];
7574         u8         down_threshold[0x8];
7575
7576         u8         reserved_at_e0[0x20];
7577
7578         u8         reserved_at_100[0x1c];
7579         u8         srps_admin[0x4];
7580
7581         u8         reserved_at_120[0x1c];
7582         u8         srps_status[0x4];
7583
7584         u8         reserved_at_140[0x40];
7585 };
7586
7587 struct mlx5_ifc_pplr_reg_bits {
7588         u8         reserved_at_0[0x8];
7589         u8         local_port[0x8];
7590         u8         reserved_at_10[0x10];
7591
7592         u8         reserved_at_20[0x8];
7593         u8         lb_cap[0x8];
7594         u8         reserved_at_30[0x8];
7595         u8         lb_en[0x8];
7596 };
7597
7598 struct mlx5_ifc_pplm_reg_bits {
7599         u8         reserved_at_0[0x8];
7600         u8         local_port[0x8];
7601         u8         reserved_at_10[0x10];
7602
7603         u8         reserved_at_20[0x20];
7604
7605         u8         port_profile_mode[0x8];
7606         u8         static_port_profile[0x8];
7607         u8         active_port_profile[0x8];
7608         u8         reserved_at_58[0x8];
7609
7610         u8         retransmission_active[0x8];
7611         u8         fec_mode_active[0x18];
7612
7613         u8         reserved_at_80[0x20];
7614 };
7615
7616 struct mlx5_ifc_ppcnt_reg_bits {
7617         u8         swid[0x8];
7618         u8         local_port[0x8];
7619         u8         pnat[0x2];
7620         u8         reserved_at_12[0x8];
7621         u8         grp[0x6];
7622
7623         u8         clr[0x1];
7624         u8         reserved_at_21[0x1c];
7625         u8         prio_tc[0x3];
7626
7627         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7628 };
7629
7630 struct mlx5_ifc_mpcnt_reg_bits {
7631         u8         reserved_at_0[0x8];
7632         u8         pcie_index[0x8];
7633         u8         reserved_at_10[0xa];
7634         u8         grp[0x6];
7635
7636         u8         clr[0x1];
7637         u8         reserved_at_21[0x1f];
7638
7639         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7640 };
7641
7642 struct mlx5_ifc_ppad_reg_bits {
7643         u8         reserved_at_0[0x3];
7644         u8         single_mac[0x1];
7645         u8         reserved_at_4[0x4];
7646         u8         local_port[0x8];
7647         u8         mac_47_32[0x10];
7648
7649         u8         mac_31_0[0x20];
7650
7651         u8         reserved_at_40[0x40];
7652 };
7653
7654 struct mlx5_ifc_pmtu_reg_bits {
7655         u8         reserved_at_0[0x8];
7656         u8         local_port[0x8];
7657         u8         reserved_at_10[0x10];
7658
7659         u8         max_mtu[0x10];
7660         u8         reserved_at_30[0x10];
7661
7662         u8         admin_mtu[0x10];
7663         u8         reserved_at_50[0x10];
7664
7665         u8         oper_mtu[0x10];
7666         u8         reserved_at_70[0x10];
7667 };
7668
7669 struct mlx5_ifc_pmpr_reg_bits {
7670         u8         reserved_at_0[0x8];
7671         u8         module[0x8];
7672         u8         reserved_at_10[0x10];
7673
7674         u8         reserved_at_20[0x18];
7675         u8         attenuation_5g[0x8];
7676
7677         u8         reserved_at_40[0x18];
7678         u8         attenuation_7g[0x8];
7679
7680         u8         reserved_at_60[0x18];
7681         u8         attenuation_12g[0x8];
7682 };
7683
7684 struct mlx5_ifc_pmpe_reg_bits {
7685         u8         reserved_at_0[0x8];
7686         u8         module[0x8];
7687         u8         reserved_at_10[0xc];
7688         u8         module_status[0x4];
7689
7690         u8         reserved_at_20[0x60];
7691 };
7692
7693 struct mlx5_ifc_pmpc_reg_bits {
7694         u8         module_state_updated[32][0x8];
7695 };
7696
7697 struct mlx5_ifc_pmlpn_reg_bits {
7698         u8         reserved_at_0[0x4];
7699         u8         mlpn_status[0x4];
7700         u8         local_port[0x8];
7701         u8         reserved_at_10[0x10];
7702
7703         u8         e[0x1];
7704         u8         reserved_at_21[0x1f];
7705 };
7706
7707 struct mlx5_ifc_pmlp_reg_bits {
7708         u8         rxtx[0x1];
7709         u8         reserved_at_1[0x7];
7710         u8         local_port[0x8];
7711         u8         reserved_at_10[0x8];
7712         u8         width[0x8];
7713
7714         u8         lane0_module_mapping[0x20];
7715
7716         u8         lane1_module_mapping[0x20];
7717
7718         u8         lane2_module_mapping[0x20];
7719
7720         u8         lane3_module_mapping[0x20];
7721
7722         u8         reserved_at_a0[0x160];
7723 };
7724
7725 struct mlx5_ifc_pmaos_reg_bits {
7726         u8         reserved_at_0[0x8];
7727         u8         module[0x8];
7728         u8         reserved_at_10[0x4];
7729         u8         admin_status[0x4];
7730         u8         reserved_at_18[0x4];
7731         u8         oper_status[0x4];
7732
7733         u8         ase[0x1];
7734         u8         ee[0x1];
7735         u8         reserved_at_22[0x1c];
7736         u8         e[0x2];
7737
7738         u8         reserved_at_40[0x40];
7739 };
7740
7741 struct mlx5_ifc_plpc_reg_bits {
7742         u8         reserved_at_0[0x4];
7743         u8         profile_id[0xc];
7744         u8         reserved_at_10[0x4];
7745         u8         proto_mask[0x4];
7746         u8         reserved_at_18[0x8];
7747
7748         u8         reserved_at_20[0x10];
7749         u8         lane_speed[0x10];
7750
7751         u8         reserved_at_40[0x17];
7752         u8         lpbf[0x1];
7753         u8         fec_mode_policy[0x8];
7754
7755         u8         retransmission_capability[0x8];
7756         u8         fec_mode_capability[0x18];
7757
7758         u8         retransmission_support_admin[0x8];
7759         u8         fec_mode_support_admin[0x18];
7760
7761         u8         retransmission_request_admin[0x8];
7762         u8         fec_mode_request_admin[0x18];
7763
7764         u8         reserved_at_c0[0x80];
7765 };
7766
7767 struct mlx5_ifc_plib_reg_bits {
7768         u8         reserved_at_0[0x8];
7769         u8         local_port[0x8];
7770         u8         reserved_at_10[0x8];
7771         u8         ib_port[0x8];
7772
7773         u8         reserved_at_20[0x60];
7774 };
7775
7776 struct mlx5_ifc_plbf_reg_bits {
7777         u8         reserved_at_0[0x8];
7778         u8         local_port[0x8];
7779         u8         reserved_at_10[0xd];
7780         u8         lbf_mode[0x3];
7781
7782         u8         reserved_at_20[0x20];
7783 };
7784
7785 struct mlx5_ifc_pipg_reg_bits {
7786         u8         reserved_at_0[0x8];
7787         u8         local_port[0x8];
7788         u8         reserved_at_10[0x10];
7789
7790         u8         dic[0x1];
7791         u8         reserved_at_21[0x19];
7792         u8         ipg[0x4];
7793         u8         reserved_at_3e[0x2];
7794 };
7795
7796 struct mlx5_ifc_pifr_reg_bits {
7797         u8         reserved_at_0[0x8];
7798         u8         local_port[0x8];
7799         u8         reserved_at_10[0x10];
7800
7801         u8         reserved_at_20[0xe0];
7802
7803         u8         port_filter[8][0x20];
7804
7805         u8         port_filter_update_en[8][0x20];
7806 };
7807
7808 struct mlx5_ifc_pfcc_reg_bits {
7809         u8         reserved_at_0[0x8];
7810         u8         local_port[0x8];
7811         u8         reserved_at_10[0x10];
7812
7813         u8         ppan[0x4];
7814         u8         reserved_at_24[0x4];
7815         u8         prio_mask_tx[0x8];
7816         u8         reserved_at_30[0x8];
7817         u8         prio_mask_rx[0x8];
7818
7819         u8         pptx[0x1];
7820         u8         aptx[0x1];
7821         u8         reserved_at_42[0x6];
7822         u8         pfctx[0x8];
7823         u8         reserved_at_50[0x10];
7824
7825         u8         pprx[0x1];
7826         u8         aprx[0x1];
7827         u8         reserved_at_62[0x6];
7828         u8         pfcrx[0x8];
7829         u8         reserved_at_70[0x10];
7830
7831         u8         reserved_at_80[0x80];
7832 };
7833
7834 struct mlx5_ifc_pelc_reg_bits {
7835         u8         op[0x4];
7836         u8         reserved_at_4[0x4];
7837         u8         local_port[0x8];
7838         u8         reserved_at_10[0x10];
7839
7840         u8         op_admin[0x8];
7841         u8         op_capability[0x8];
7842         u8         op_request[0x8];
7843         u8         op_active[0x8];
7844
7845         u8         admin[0x40];
7846
7847         u8         capability[0x40];
7848
7849         u8         request[0x40];
7850
7851         u8         active[0x40];
7852
7853         u8         reserved_at_140[0x80];
7854 };
7855
7856 struct mlx5_ifc_peir_reg_bits {
7857         u8         reserved_at_0[0x8];
7858         u8         local_port[0x8];
7859         u8         reserved_at_10[0x10];
7860
7861         u8         reserved_at_20[0xc];
7862         u8         error_count[0x4];
7863         u8         reserved_at_30[0x10];
7864
7865         u8         reserved_at_40[0xc];
7866         u8         lane[0x4];
7867         u8         reserved_at_50[0x8];
7868         u8         error_type[0x8];
7869 };
7870
7871 struct mlx5_ifc_pcam_enhanced_features_bits {
7872         u8         reserved_at_0[0x7b];
7873
7874         u8         rx_buffer_fullness_counters[0x1];
7875         u8         ptys_connector_type[0x1];
7876         u8         reserved_at_7d[0x1];
7877         u8         ppcnt_discard_group[0x1];
7878         u8         ppcnt_statistical_group[0x1];
7879 };
7880
7881 struct mlx5_ifc_pcam_reg_bits {
7882         u8         reserved_at_0[0x8];
7883         u8         feature_group[0x8];
7884         u8         reserved_at_10[0x8];
7885         u8         access_reg_group[0x8];
7886
7887         u8         reserved_at_20[0x20];
7888
7889         union {
7890                 u8         reserved_at_0[0x80];
7891         } port_access_reg_cap_mask;
7892
7893         u8         reserved_at_c0[0x80];
7894
7895         union {
7896                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
7897                 u8         reserved_at_0[0x80];
7898         } feature_cap_mask;
7899
7900         u8         reserved_at_1c0[0xc0];
7901 };
7902
7903 struct mlx5_ifc_mcam_enhanced_features_bits {
7904         u8         reserved_at_0[0x7b];
7905         u8         pcie_outbound_stalled[0x1];
7906         u8         tx_overflow_buffer_pkt[0x1];
7907         u8         mtpps_enh_out_per_adj[0x1];
7908         u8         mtpps_fs[0x1];
7909         u8         pcie_performance_group[0x1];
7910 };
7911
7912 struct mlx5_ifc_mcam_access_reg_bits {
7913         u8         reserved_at_0[0x1c];
7914         u8         mcda[0x1];
7915         u8         mcc[0x1];
7916         u8         mcqi[0x1];
7917         u8         reserved_at_1f[0x1];
7918
7919         u8         regs_95_to_64[0x20];
7920         u8         regs_63_to_32[0x20];
7921         u8         regs_31_to_0[0x20];
7922 };
7923
7924 struct mlx5_ifc_mcam_reg_bits {
7925         u8         reserved_at_0[0x8];
7926         u8         feature_group[0x8];
7927         u8         reserved_at_10[0x8];
7928         u8         access_reg_group[0x8];
7929
7930         u8         reserved_at_20[0x20];
7931
7932         union {
7933                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
7934                 u8         reserved_at_0[0x80];
7935         } mng_access_reg_cap_mask;
7936
7937         u8         reserved_at_c0[0x80];
7938
7939         union {
7940                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
7941                 u8         reserved_at_0[0x80];
7942         } mng_feature_cap_mask;
7943
7944         u8         reserved_at_1c0[0x80];
7945 };
7946
7947 struct mlx5_ifc_qcam_access_reg_cap_mask {
7948         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
7949         u8         qpdpm[0x1];
7950         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
7951         u8         qdpm[0x1];
7952         u8         qpts[0x1];
7953         u8         qcap[0x1];
7954         u8         qcam_access_reg_cap_mask_0[0x1];
7955 };
7956
7957 struct mlx5_ifc_qcam_qos_feature_cap_mask {
7958         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
7959         u8         qpts_trust_both[0x1];
7960 };
7961
7962 struct mlx5_ifc_qcam_reg_bits {
7963         u8         reserved_at_0[0x8];
7964         u8         feature_group[0x8];
7965         u8         reserved_at_10[0x8];
7966         u8         access_reg_group[0x8];
7967         u8         reserved_at_20[0x20];
7968
7969         union {
7970                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
7971                 u8  reserved_at_0[0x80];
7972         } qos_access_reg_cap_mask;
7973
7974         u8         reserved_at_c0[0x80];
7975
7976         union {
7977                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
7978                 u8  reserved_at_0[0x80];
7979         } qos_feature_cap_mask;
7980
7981         u8         reserved_at_1c0[0x80];
7982 };
7983
7984 struct mlx5_ifc_pcap_reg_bits {
7985         u8         reserved_at_0[0x8];
7986         u8         local_port[0x8];
7987         u8         reserved_at_10[0x10];
7988
7989         u8         port_capability_mask[4][0x20];
7990 };
7991
7992 struct mlx5_ifc_paos_reg_bits {
7993         u8         swid[0x8];
7994         u8         local_port[0x8];
7995         u8         reserved_at_10[0x4];
7996         u8         admin_status[0x4];
7997         u8         reserved_at_18[0x4];
7998         u8         oper_status[0x4];
7999
8000         u8         ase[0x1];
8001         u8         ee[0x1];
8002         u8         reserved_at_22[0x1c];
8003         u8         e[0x2];
8004
8005         u8         reserved_at_40[0x40];
8006 };
8007
8008 struct mlx5_ifc_pamp_reg_bits {
8009         u8         reserved_at_0[0x8];
8010         u8         opamp_group[0x8];
8011         u8         reserved_at_10[0xc];
8012         u8         opamp_group_type[0x4];
8013
8014         u8         start_index[0x10];
8015         u8         reserved_at_30[0x4];
8016         u8         num_of_indices[0xc];
8017
8018         u8         index_data[18][0x10];
8019 };
8020
8021 struct mlx5_ifc_pcmr_reg_bits {
8022         u8         reserved_at_0[0x8];
8023         u8         local_port[0x8];
8024         u8         reserved_at_10[0x2e];
8025         u8         fcs_cap[0x1];
8026         u8         reserved_at_3f[0x1f];
8027         u8         fcs_chk[0x1];
8028         u8         reserved_at_5f[0x1];
8029 };
8030
8031 struct mlx5_ifc_lane_2_module_mapping_bits {
8032         u8         reserved_at_0[0x6];
8033         u8         rx_lane[0x2];
8034         u8         reserved_at_8[0x6];
8035         u8         tx_lane[0x2];
8036         u8         reserved_at_10[0x8];
8037         u8         module[0x8];
8038 };
8039
8040 struct mlx5_ifc_bufferx_reg_bits {
8041         u8         reserved_at_0[0x6];
8042         u8         lossy[0x1];
8043         u8         epsb[0x1];
8044         u8         reserved_at_8[0xc];
8045         u8         size[0xc];
8046
8047         u8         xoff_threshold[0x10];
8048         u8         xon_threshold[0x10];
8049 };
8050
8051 struct mlx5_ifc_set_node_in_bits {
8052         u8         node_description[64][0x8];
8053 };
8054
8055 struct mlx5_ifc_register_power_settings_bits {
8056         u8         reserved_at_0[0x18];
8057         u8         power_settings_level[0x8];
8058
8059         u8         reserved_at_20[0x60];
8060 };
8061
8062 struct mlx5_ifc_register_host_endianness_bits {
8063         u8         he[0x1];
8064         u8         reserved_at_1[0x1f];
8065
8066         u8         reserved_at_20[0x60];
8067 };
8068
8069 struct mlx5_ifc_umr_pointer_desc_argument_bits {
8070         u8         reserved_at_0[0x20];
8071
8072         u8         mkey[0x20];
8073
8074         u8         addressh_63_32[0x20];
8075
8076         u8         addressl_31_0[0x20];
8077 };
8078
8079 struct mlx5_ifc_ud_adrs_vector_bits {
8080         u8         dc_key[0x40];
8081
8082         u8         ext[0x1];
8083         u8         reserved_at_41[0x7];
8084         u8         destination_qp_dct[0x18];
8085
8086         u8         static_rate[0x4];
8087         u8         sl_eth_prio[0x4];
8088         u8         fl[0x1];
8089         u8         mlid[0x7];
8090         u8         rlid_udp_sport[0x10];
8091
8092         u8         reserved_at_80[0x20];
8093
8094         u8         rmac_47_16[0x20];
8095
8096         u8         rmac_15_0[0x10];
8097         u8         tclass[0x8];
8098         u8         hop_limit[0x8];
8099
8100         u8         reserved_at_e0[0x1];
8101         u8         grh[0x1];
8102         u8         reserved_at_e2[0x2];
8103         u8         src_addr_index[0x8];
8104         u8         flow_label[0x14];
8105
8106         u8         rgid_rip[16][0x8];
8107 };
8108
8109 struct mlx5_ifc_pages_req_event_bits {
8110         u8         reserved_at_0[0x10];
8111         u8         function_id[0x10];
8112
8113         u8         num_pages[0x20];
8114
8115         u8         reserved_at_40[0xa0];
8116 };
8117
8118 struct mlx5_ifc_eqe_bits {
8119         u8         reserved_at_0[0x8];
8120         u8         event_type[0x8];
8121         u8         reserved_at_10[0x8];
8122         u8         event_sub_type[0x8];
8123
8124         u8         reserved_at_20[0xe0];
8125
8126         union mlx5_ifc_event_auto_bits event_data;
8127
8128         u8         reserved_at_1e0[0x10];
8129         u8         signature[0x8];
8130         u8         reserved_at_1f8[0x7];
8131         u8         owner[0x1];
8132 };
8133
8134 enum {
8135         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
8136 };
8137
8138 struct mlx5_ifc_cmd_queue_entry_bits {
8139         u8         type[0x8];
8140         u8         reserved_at_8[0x18];
8141
8142         u8         input_length[0x20];
8143
8144         u8         input_mailbox_pointer_63_32[0x20];
8145
8146         u8         input_mailbox_pointer_31_9[0x17];
8147         u8         reserved_at_77[0x9];
8148
8149         u8         command_input_inline_data[16][0x8];
8150
8151         u8         command_output_inline_data[16][0x8];
8152
8153         u8         output_mailbox_pointer_63_32[0x20];
8154
8155         u8         output_mailbox_pointer_31_9[0x17];
8156         u8         reserved_at_1b7[0x9];
8157
8158         u8         output_length[0x20];
8159
8160         u8         token[0x8];
8161         u8         signature[0x8];
8162         u8         reserved_at_1f0[0x8];
8163         u8         status[0x7];
8164         u8         ownership[0x1];
8165 };
8166
8167 struct mlx5_ifc_cmd_out_bits {
8168         u8         status[0x8];
8169         u8         reserved_at_8[0x18];
8170
8171         u8         syndrome[0x20];
8172
8173         u8         command_output[0x20];
8174 };
8175
8176 struct mlx5_ifc_cmd_in_bits {
8177         u8         opcode[0x10];
8178         u8         reserved_at_10[0x10];
8179
8180         u8         reserved_at_20[0x10];
8181         u8         op_mod[0x10];
8182
8183         u8         command[0][0x20];
8184 };
8185
8186 struct mlx5_ifc_cmd_if_box_bits {
8187         u8         mailbox_data[512][0x8];
8188
8189         u8         reserved_at_1000[0x180];
8190
8191         u8         next_pointer_63_32[0x20];
8192
8193         u8         next_pointer_31_10[0x16];
8194         u8         reserved_at_11b6[0xa];
8195
8196         u8         block_number[0x20];
8197
8198         u8         reserved_at_11e0[0x8];
8199         u8         token[0x8];
8200         u8         ctrl_signature[0x8];
8201         u8         signature[0x8];
8202 };
8203
8204 struct mlx5_ifc_mtt_bits {
8205         u8         ptag_63_32[0x20];
8206
8207         u8         ptag_31_8[0x18];
8208         u8         reserved_at_38[0x6];
8209         u8         wr_en[0x1];
8210         u8         rd_en[0x1];
8211 };
8212
8213 struct mlx5_ifc_query_wol_rol_out_bits {
8214         u8         status[0x8];
8215         u8         reserved_at_8[0x18];
8216
8217         u8         syndrome[0x20];
8218
8219         u8         reserved_at_40[0x10];
8220         u8         rol_mode[0x8];
8221         u8         wol_mode[0x8];
8222
8223         u8         reserved_at_60[0x20];
8224 };
8225
8226 struct mlx5_ifc_query_wol_rol_in_bits {
8227         u8         opcode[0x10];
8228         u8         reserved_at_10[0x10];
8229
8230         u8         reserved_at_20[0x10];
8231         u8         op_mod[0x10];
8232
8233         u8         reserved_at_40[0x40];
8234 };
8235
8236 struct mlx5_ifc_set_wol_rol_out_bits {
8237         u8         status[0x8];
8238         u8         reserved_at_8[0x18];
8239
8240         u8         syndrome[0x20];
8241
8242         u8         reserved_at_40[0x40];
8243 };
8244
8245 struct mlx5_ifc_set_wol_rol_in_bits {
8246         u8         opcode[0x10];
8247         u8         reserved_at_10[0x10];
8248
8249         u8         reserved_at_20[0x10];
8250         u8         op_mod[0x10];
8251
8252         u8         rol_mode_valid[0x1];
8253         u8         wol_mode_valid[0x1];
8254         u8         reserved_at_42[0xe];
8255         u8         rol_mode[0x8];
8256         u8         wol_mode[0x8];
8257
8258         u8         reserved_at_60[0x20];
8259 };
8260
8261 enum {
8262         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
8263         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
8264         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
8265 };
8266
8267 enum {
8268         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
8269         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
8270         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
8271 };
8272
8273 enum {
8274         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
8275         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
8276         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
8277         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
8278         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
8279         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
8280         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
8281         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
8282         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
8283         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
8284         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
8285 };
8286
8287 struct mlx5_ifc_initial_seg_bits {
8288         u8         fw_rev_minor[0x10];
8289         u8         fw_rev_major[0x10];
8290
8291         u8         cmd_interface_rev[0x10];
8292         u8         fw_rev_subminor[0x10];
8293
8294         u8         reserved_at_40[0x40];
8295
8296         u8         cmdq_phy_addr_63_32[0x20];
8297
8298         u8         cmdq_phy_addr_31_12[0x14];
8299         u8         reserved_at_b4[0x2];
8300         u8         nic_interface[0x2];
8301         u8         log_cmdq_size[0x4];
8302         u8         log_cmdq_stride[0x4];
8303
8304         u8         command_doorbell_vector[0x20];
8305
8306         u8         reserved_at_e0[0xf00];
8307
8308         u8         initializing[0x1];
8309         u8         reserved_at_fe1[0x4];
8310         u8         nic_interface_supported[0x3];
8311         u8         reserved_at_fe8[0x18];
8312
8313         struct mlx5_ifc_health_buffer_bits health_buffer;
8314
8315         u8         no_dram_nic_offset[0x20];
8316
8317         u8         reserved_at_1220[0x6e40];
8318
8319         u8         reserved_at_8060[0x1f];
8320         u8         clear_int[0x1];
8321
8322         u8         health_syndrome[0x8];
8323         u8         health_counter[0x18];
8324
8325         u8         reserved_at_80a0[0x17fc0];
8326 };
8327
8328 struct mlx5_ifc_mtpps_reg_bits {
8329         u8         reserved_at_0[0xc];
8330         u8         cap_number_of_pps_pins[0x4];
8331         u8         reserved_at_10[0x4];
8332         u8         cap_max_num_of_pps_in_pins[0x4];
8333         u8         reserved_at_18[0x4];
8334         u8         cap_max_num_of_pps_out_pins[0x4];
8335
8336         u8         reserved_at_20[0x24];
8337         u8         cap_pin_3_mode[0x4];
8338         u8         reserved_at_48[0x4];
8339         u8         cap_pin_2_mode[0x4];
8340         u8         reserved_at_50[0x4];
8341         u8         cap_pin_1_mode[0x4];
8342         u8         reserved_at_58[0x4];
8343         u8         cap_pin_0_mode[0x4];
8344
8345         u8         reserved_at_60[0x4];
8346         u8         cap_pin_7_mode[0x4];
8347         u8         reserved_at_68[0x4];
8348         u8         cap_pin_6_mode[0x4];
8349         u8         reserved_at_70[0x4];
8350         u8         cap_pin_5_mode[0x4];
8351         u8         reserved_at_78[0x4];
8352         u8         cap_pin_4_mode[0x4];
8353
8354         u8         field_select[0x20];
8355         u8         reserved_at_a0[0x60];
8356
8357         u8         enable[0x1];
8358         u8         reserved_at_101[0xb];
8359         u8         pattern[0x4];
8360         u8         reserved_at_110[0x4];
8361         u8         pin_mode[0x4];
8362         u8         pin[0x8];
8363
8364         u8         reserved_at_120[0x20];
8365
8366         u8         time_stamp[0x40];
8367
8368         u8         out_pulse_duration[0x10];
8369         u8         out_periodic_adjustment[0x10];
8370         u8         enhanced_out_periodic_adjustment[0x20];
8371
8372         u8         reserved_at_1c0[0x20];
8373 };
8374
8375 struct mlx5_ifc_mtppse_reg_bits {
8376         u8         reserved_at_0[0x18];
8377         u8         pin[0x8];
8378         u8         event_arm[0x1];
8379         u8         reserved_at_21[0x1b];
8380         u8         event_generation_mode[0x4];
8381         u8         reserved_at_40[0x40];
8382 };
8383
8384 struct mlx5_ifc_mcqi_cap_bits {
8385         u8         supported_info_bitmask[0x20];
8386
8387         u8         component_size[0x20];
8388
8389         u8         max_component_size[0x20];
8390
8391         u8         log_mcda_word_size[0x4];
8392         u8         reserved_at_64[0xc];
8393         u8         mcda_max_write_size[0x10];
8394
8395         u8         rd_en[0x1];
8396         u8         reserved_at_81[0x1];
8397         u8         match_chip_id[0x1];
8398         u8         match_psid[0x1];
8399         u8         check_user_timestamp[0x1];
8400         u8         match_base_guid_mac[0x1];
8401         u8         reserved_at_86[0x1a];
8402 };
8403
8404 struct mlx5_ifc_mcqi_reg_bits {
8405         u8         read_pending_component[0x1];
8406         u8         reserved_at_1[0xf];
8407         u8         component_index[0x10];
8408
8409         u8         reserved_at_20[0x20];
8410
8411         u8         reserved_at_40[0x1b];
8412         u8         info_type[0x5];
8413
8414         u8         info_size[0x20];
8415
8416         u8         offset[0x20];
8417
8418         u8         reserved_at_a0[0x10];
8419         u8         data_size[0x10];
8420
8421         u8         data[0][0x20];
8422 };
8423
8424 struct mlx5_ifc_mcc_reg_bits {
8425         u8         reserved_at_0[0x4];
8426         u8         time_elapsed_since_last_cmd[0xc];
8427         u8         reserved_at_10[0x8];
8428         u8         instruction[0x8];
8429
8430         u8         reserved_at_20[0x10];
8431         u8         component_index[0x10];
8432
8433         u8         reserved_at_40[0x8];
8434         u8         update_handle[0x18];
8435
8436         u8         handle_owner_type[0x4];
8437         u8         handle_owner_host_id[0x4];
8438         u8         reserved_at_68[0x1];
8439         u8         control_progress[0x7];
8440         u8         error_code[0x8];
8441         u8         reserved_at_78[0x4];
8442         u8         control_state[0x4];
8443
8444         u8         component_size[0x20];
8445
8446         u8         reserved_at_a0[0x60];
8447 };
8448
8449 struct mlx5_ifc_mcda_reg_bits {
8450         u8         reserved_at_0[0x8];
8451         u8         update_handle[0x18];
8452
8453         u8         offset[0x20];
8454
8455         u8         reserved_at_40[0x10];
8456         u8         size[0x10];
8457
8458         u8         reserved_at_60[0x20];
8459
8460         u8         data[0][0x20];
8461 };
8462
8463 union mlx5_ifc_ports_control_registers_document_bits {
8464         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8465         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8466         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8467         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8468         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8469         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8470         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8471         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8472         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8473         struct mlx5_ifc_pamp_reg_bits pamp_reg;
8474         struct mlx5_ifc_paos_reg_bits paos_reg;
8475         struct mlx5_ifc_pcap_reg_bits pcap_reg;
8476         struct mlx5_ifc_peir_reg_bits peir_reg;
8477         struct mlx5_ifc_pelc_reg_bits pelc_reg;
8478         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8479         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
8480         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8481         struct mlx5_ifc_pifr_reg_bits pifr_reg;
8482         struct mlx5_ifc_pipg_reg_bits pipg_reg;
8483         struct mlx5_ifc_plbf_reg_bits plbf_reg;
8484         struct mlx5_ifc_plib_reg_bits plib_reg;
8485         struct mlx5_ifc_plpc_reg_bits plpc_reg;
8486         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8487         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8488         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8489         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8490         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8491         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8492         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8493         struct mlx5_ifc_ppad_reg_bits ppad_reg;
8494         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8495         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
8496         struct mlx5_ifc_pplm_reg_bits pplm_reg;
8497         struct mlx5_ifc_pplr_reg_bits pplr_reg;
8498         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8499         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8500         struct mlx5_ifc_pspa_reg_bits pspa_reg;
8501         struct mlx5_ifc_ptas_reg_bits ptas_reg;
8502         struct mlx5_ifc_ptys_reg_bits ptys_reg;
8503         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
8504         struct mlx5_ifc_pude_reg_bits pude_reg;
8505         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8506         struct mlx5_ifc_slrg_reg_bits slrg_reg;
8507         struct mlx5_ifc_sltp_reg_bits sltp_reg;
8508         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8509         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
8510         struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
8511         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8512         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
8513         struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8514         struct mlx5_ifc_mcc_reg_bits mcc_reg;
8515         struct mlx5_ifc_mcda_reg_bits mcda_reg;
8516         u8         reserved_at_0[0x60e0];
8517 };
8518
8519 union mlx5_ifc_debug_enhancements_document_bits {
8520         struct mlx5_ifc_health_buffer_bits health_buffer;
8521         u8         reserved_at_0[0x200];
8522 };
8523
8524 union mlx5_ifc_uplink_pci_interface_document_bits {
8525         struct mlx5_ifc_initial_seg_bits initial_seg;
8526         u8         reserved_at_0[0x20060];
8527 };
8528
8529 struct mlx5_ifc_set_flow_table_root_out_bits {
8530         u8         status[0x8];
8531         u8         reserved_at_8[0x18];
8532
8533         u8         syndrome[0x20];
8534
8535         u8         reserved_at_40[0x40];
8536 };
8537
8538 struct mlx5_ifc_set_flow_table_root_in_bits {
8539         u8         opcode[0x10];
8540         u8         reserved_at_10[0x10];
8541
8542         u8         reserved_at_20[0x10];
8543         u8         op_mod[0x10];
8544
8545         u8         other_vport[0x1];
8546         u8         reserved_at_41[0xf];
8547         u8         vport_number[0x10];
8548
8549         u8         reserved_at_60[0x20];
8550
8551         u8         table_type[0x8];
8552         u8         reserved_at_88[0x18];
8553
8554         u8         reserved_at_a0[0x8];
8555         u8         table_id[0x18];
8556
8557         u8         reserved_at_c0[0x8];
8558         u8         underlay_qpn[0x18];
8559         u8         reserved_at_e0[0x120];
8560 };
8561
8562 enum {
8563         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
8564         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8565 };
8566
8567 struct mlx5_ifc_modify_flow_table_out_bits {
8568         u8         status[0x8];
8569         u8         reserved_at_8[0x18];
8570
8571         u8         syndrome[0x20];
8572
8573         u8         reserved_at_40[0x40];
8574 };
8575
8576 struct mlx5_ifc_modify_flow_table_in_bits {
8577         u8         opcode[0x10];
8578         u8         reserved_at_10[0x10];
8579
8580         u8         reserved_at_20[0x10];
8581         u8         op_mod[0x10];
8582
8583         u8         other_vport[0x1];
8584         u8         reserved_at_41[0xf];
8585         u8         vport_number[0x10];
8586
8587         u8         reserved_at_60[0x10];
8588         u8         modify_field_select[0x10];
8589
8590         u8         table_type[0x8];
8591         u8         reserved_at_88[0x18];
8592
8593         u8         reserved_at_a0[0x8];
8594         u8         table_id[0x18];
8595
8596         struct mlx5_ifc_flow_table_context_bits flow_table_context;
8597 };
8598
8599 struct mlx5_ifc_ets_tcn_config_reg_bits {
8600         u8         g[0x1];
8601         u8         b[0x1];
8602         u8         r[0x1];
8603         u8         reserved_at_3[0x9];
8604         u8         group[0x4];
8605         u8         reserved_at_10[0x9];
8606         u8         bw_allocation[0x7];
8607
8608         u8         reserved_at_20[0xc];
8609         u8         max_bw_units[0x4];
8610         u8         reserved_at_30[0x8];
8611         u8         max_bw_value[0x8];
8612 };
8613
8614 struct mlx5_ifc_ets_global_config_reg_bits {
8615         u8         reserved_at_0[0x2];
8616         u8         r[0x1];
8617         u8         reserved_at_3[0x1d];
8618
8619         u8         reserved_at_20[0xc];
8620         u8         max_bw_units[0x4];
8621         u8         reserved_at_30[0x8];
8622         u8         max_bw_value[0x8];
8623 };
8624
8625 struct mlx5_ifc_qetc_reg_bits {
8626         u8                                         reserved_at_0[0x8];
8627         u8                                         port_number[0x8];
8628         u8                                         reserved_at_10[0x30];
8629
8630         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
8631         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8632 };
8633
8634 struct mlx5_ifc_qpdpm_dscp_reg_bits {
8635         u8         e[0x1];
8636         u8         reserved_at_01[0x0b];
8637         u8         prio[0x04];
8638 };
8639
8640 struct mlx5_ifc_qpdpm_reg_bits {
8641         u8                                     reserved_at_0[0x8];
8642         u8                                     local_port[0x8];
8643         u8                                     reserved_at_10[0x10];
8644         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
8645 };
8646
8647 struct mlx5_ifc_qpts_reg_bits {
8648         u8         reserved_at_0[0x8];
8649         u8         local_port[0x8];
8650         u8         reserved_at_10[0x2d];
8651         u8         trust_state[0x3];
8652 };
8653
8654 struct mlx5_ifc_qtct_reg_bits {
8655         u8         reserved_at_0[0x8];
8656         u8         port_number[0x8];
8657         u8         reserved_at_10[0xd];
8658         u8         prio[0x3];
8659
8660         u8         reserved_at_20[0x1d];
8661         u8         tclass[0x3];
8662 };
8663
8664 struct mlx5_ifc_mcia_reg_bits {
8665         u8         l[0x1];
8666         u8         reserved_at_1[0x7];
8667         u8         module[0x8];
8668         u8         reserved_at_10[0x8];
8669         u8         status[0x8];
8670
8671         u8         i2c_device_address[0x8];
8672         u8         page_number[0x8];
8673         u8         device_address[0x10];
8674
8675         u8         reserved_at_40[0x10];
8676         u8         size[0x10];
8677
8678         u8         reserved_at_60[0x20];
8679
8680         u8         dword_0[0x20];
8681         u8         dword_1[0x20];
8682         u8         dword_2[0x20];
8683         u8         dword_3[0x20];
8684         u8         dword_4[0x20];
8685         u8         dword_5[0x20];
8686         u8         dword_6[0x20];
8687         u8         dword_7[0x20];
8688         u8         dword_8[0x20];
8689         u8         dword_9[0x20];
8690         u8         dword_10[0x20];
8691         u8         dword_11[0x20];
8692 };
8693
8694 struct mlx5_ifc_dcbx_param_bits {
8695         u8         dcbx_cee_cap[0x1];
8696         u8         dcbx_ieee_cap[0x1];
8697         u8         dcbx_standby_cap[0x1];
8698         u8         reserved_at_0[0x5];
8699         u8         port_number[0x8];
8700         u8         reserved_at_10[0xa];
8701         u8         max_application_table_size[6];
8702         u8         reserved_at_20[0x15];
8703         u8         version_oper[0x3];
8704         u8         reserved_at_38[5];
8705         u8         version_admin[0x3];
8706         u8         willing_admin[0x1];
8707         u8         reserved_at_41[0x3];
8708         u8         pfc_cap_oper[0x4];
8709         u8         reserved_at_48[0x4];
8710         u8         pfc_cap_admin[0x4];
8711         u8         reserved_at_50[0x4];
8712         u8         num_of_tc_oper[0x4];
8713         u8         reserved_at_58[0x4];
8714         u8         num_of_tc_admin[0x4];
8715         u8         remote_willing[0x1];
8716         u8         reserved_at_61[3];
8717         u8         remote_pfc_cap[4];
8718         u8         reserved_at_68[0x14];
8719         u8         remote_num_of_tc[0x4];
8720         u8         reserved_at_80[0x18];
8721         u8         error[0x8];
8722         u8         reserved_at_a0[0x160];
8723 };
8724
8725 struct mlx5_ifc_lagc_bits {
8726         u8         reserved_at_0[0x1d];
8727         u8         lag_state[0x3];
8728
8729         u8         reserved_at_20[0x14];
8730         u8         tx_remap_affinity_2[0x4];
8731         u8         reserved_at_38[0x4];
8732         u8         tx_remap_affinity_1[0x4];
8733 };
8734
8735 struct mlx5_ifc_create_lag_out_bits {
8736         u8         status[0x8];
8737         u8         reserved_at_8[0x18];
8738
8739         u8         syndrome[0x20];
8740
8741         u8         reserved_at_40[0x40];
8742 };
8743
8744 struct mlx5_ifc_create_lag_in_bits {
8745         u8         opcode[0x10];
8746         u8         reserved_at_10[0x10];
8747
8748         u8         reserved_at_20[0x10];
8749         u8         op_mod[0x10];
8750
8751         struct mlx5_ifc_lagc_bits ctx;
8752 };
8753
8754 struct mlx5_ifc_modify_lag_out_bits {
8755         u8         status[0x8];
8756         u8         reserved_at_8[0x18];
8757
8758         u8         syndrome[0x20];
8759
8760         u8         reserved_at_40[0x40];
8761 };
8762
8763 struct mlx5_ifc_modify_lag_in_bits {
8764         u8         opcode[0x10];
8765         u8         reserved_at_10[0x10];
8766
8767         u8         reserved_at_20[0x10];
8768         u8         op_mod[0x10];
8769
8770         u8         reserved_at_40[0x20];
8771         u8         field_select[0x20];
8772
8773         struct mlx5_ifc_lagc_bits ctx;
8774 };
8775
8776 struct mlx5_ifc_query_lag_out_bits {
8777         u8         status[0x8];
8778         u8         reserved_at_8[0x18];
8779
8780         u8         syndrome[0x20];
8781
8782         u8         reserved_at_40[0x40];
8783
8784         struct mlx5_ifc_lagc_bits ctx;
8785 };
8786
8787 struct mlx5_ifc_query_lag_in_bits {
8788         u8         opcode[0x10];
8789         u8         reserved_at_10[0x10];
8790
8791         u8         reserved_at_20[0x10];
8792         u8         op_mod[0x10];
8793
8794         u8         reserved_at_40[0x40];
8795 };
8796
8797 struct mlx5_ifc_destroy_lag_out_bits {
8798         u8         status[0x8];
8799         u8         reserved_at_8[0x18];
8800
8801         u8         syndrome[0x20];
8802
8803         u8         reserved_at_40[0x40];
8804 };
8805
8806 struct mlx5_ifc_destroy_lag_in_bits {
8807         u8         opcode[0x10];
8808         u8         reserved_at_10[0x10];
8809
8810         u8         reserved_at_20[0x10];
8811         u8         op_mod[0x10];
8812
8813         u8         reserved_at_40[0x40];
8814 };
8815
8816 struct mlx5_ifc_create_vport_lag_out_bits {
8817         u8         status[0x8];
8818         u8         reserved_at_8[0x18];
8819
8820         u8         syndrome[0x20];
8821
8822         u8         reserved_at_40[0x40];
8823 };
8824
8825 struct mlx5_ifc_create_vport_lag_in_bits {
8826         u8         opcode[0x10];
8827         u8         reserved_at_10[0x10];
8828
8829         u8         reserved_at_20[0x10];
8830         u8         op_mod[0x10];
8831
8832         u8         reserved_at_40[0x40];
8833 };
8834
8835 struct mlx5_ifc_destroy_vport_lag_out_bits {
8836         u8         status[0x8];
8837         u8         reserved_at_8[0x18];
8838
8839         u8         syndrome[0x20];
8840
8841         u8         reserved_at_40[0x40];
8842 };
8843
8844 struct mlx5_ifc_destroy_vport_lag_in_bits {
8845         u8         opcode[0x10];
8846         u8         reserved_at_10[0x10];
8847
8848         u8         reserved_at_20[0x10];
8849         u8         op_mod[0x10];
8850
8851         u8         reserved_at_40[0x40];
8852 };
8853
8854 #endif /* MLX5_IFC_H */