drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <[email protected]>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include <drm/drm_plane_helper.h>
  30 #include "i915_drv.h"
  31 #include "intel_drv.h"
  32 #include "../../../platform/x86/intel_ips.h"
  33 #include <linux/module.h>
  34
  35 /**
  36  * DOC: RC6
  37  *
  38  * RC6 is a special power stage which allows the GPU to enter an very
  39  * low-voltage mode when idle, using down to 0V while at this stage.  This
  40  * stage is entered automatically when the GPU is idle when RC6 support is
  41  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  42  *
  43  * There are different RC6 modes available in Intel GPU, which differentiate
  44  * among each other with the latency required to enter and leave RC6 and
  45  * voltage consumed by the GPU in different states.
  46  *
  47  * The combination of the following flags define which states GPU is allowed
  48  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  49  * RC6pp is deepest RC6. Their support by hardware varies according to the
  50  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  51  * which brings the most power savings; deeper states save more power, but
  52  * require higher latency to switch to and wake up.
  53  */
  54 #define INTEL_RC6_ENABLE                        (1<<0)
  55 #define INTEL_RC6p_ENABLE                       (1<<1)
  56 #define INTEL_RC6pp_ENABLE                      (1<<2)
  57
  58 static void gen9_init_clock_gating(struct drm_device *dev)
  59 {
  60         struct drm_i915_private *dev_priv = dev->dev_private;
  61
  62         /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
  63         I915_WRITE(CHICKEN_PAR1_1,
  64                    I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
  65
  66         I915_WRITE(GEN8_CONFIG0,
  67                    I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
  68
  69         /* WaEnableChickenDCPR:skl,bxt,kbl */
  70         I915_WRITE(GEN8_CHICKEN_DCPR_1,
  71                    I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
  72
  73         /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
  74         /* WaFbcWakeMemOn:skl,bxt,kbl */
  75         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
  76                    DISP_FBC_WM_DIS |
  77                    DISP_FBC_MEMORY_WAKE);
  78
  79         /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
  80         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
  81                    ILK_DPFC_DISABLE_DUMMY0);
  82 }
  83
  84 static void bxt_init_clock_gating(struct drm_device *dev)
  85 {
  86         struct drm_i915_private *dev_priv = to_i915(dev);
  87
  88         gen9_init_clock_gating(dev);
  89
  90         /* WaDisableSDEUnitClockGating:bxt */
  91         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  92                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
  93
  94         /*
  95          * FIXME:
  96          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
  97          */
  98         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  99                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
 100
 101         /*
 102          * Wa: Backlight PWM may stop in the asserted state, causing backlight
 103          * to stay fully on.
 104          */
 105         if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
 106                 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
 107                            PWM1_GATING_DIS | PWM2_GATING_DIS);
 108 }
 109
 110 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 111 {
 112         struct drm_i915_private *dev_priv = to_i915(dev);
 113         u32 tmp;
 114
 115         tmp = I915_READ(CLKCFG);
 116
 117         switch (tmp & CLKCFG_FSB_MASK) {
 118         case CLKCFG_FSB_533:
 119                 dev_priv->fsb_freq = 533; /* 133*4 */
 120                 break;
 121         case CLKCFG_FSB_800:
 122                 dev_priv->fsb_freq = 800; /* 200*4 */
 123                 break;
 124         case CLKCFG_FSB_667:
 125                 dev_priv->fsb_freq =  667; /* 167*4 */
 126                 break;
 127         case CLKCFG_FSB_400:
 128                 dev_priv->fsb_freq = 400; /* 100*4 */
 129                 break;
 130         }
 131
 132         switch (tmp & CLKCFG_MEM_MASK) {
 133         case CLKCFG_MEM_533:
 134                 dev_priv->mem_freq = 533;
 135                 break;
 136         case CLKCFG_MEM_667:
 137                 dev_priv->mem_freq = 667;
 138                 break;
 139         case CLKCFG_MEM_800:
 140                 dev_priv->mem_freq = 800;
 141                 break;
 142         }
 143
 144         /* detect pineview DDR3 setting */
 145         tmp = I915_READ(CSHRDDR3CTL);
 146         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 147 }
 148
 149 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 150 {
 151         struct drm_i915_private *dev_priv = to_i915(dev);
 152         u16 ddrpll, csipll;
 153
 154         ddrpll = I915_READ16(DDRMPLL1);
 155         csipll = I915_READ16(CSIPLL0);
 156
 157         switch (ddrpll & 0xff) {
 158         case 0xc:
 159                 dev_priv->mem_freq = 800;
 160                 break;
 161         case 0x10:
 162                 dev_priv->mem_freq = 1066;
 163                 break;
 164         case 0x14:
 165                 dev_priv->mem_freq = 1333;
 166                 break;
 167         case 0x18:
 168                 dev_priv->mem_freq = 1600;
 169                 break;
 170         default:
 171                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 172                                  ddrpll & 0xff);
 173                 dev_priv->mem_freq = 0;
 174                 break;
 175         }
 176
 177         dev_priv->ips.r_t = dev_priv->mem_freq;
 178
 179         switch (csipll & 0x3ff) {
 180         case 0x00c:
 181                 dev_priv->fsb_freq = 3200;
 182                 break;
 183         case 0x00e:
 184                 dev_priv->fsb_freq = 3733;
 185                 break;
 186         case 0x010:
 187                 dev_priv->fsb_freq = 4266;
 188                 break;
 189         case 0x012:
 190                 dev_priv->fsb_freq = 4800;
 191                 break;
 192         case 0x014:
 193                 dev_priv->fsb_freq = 5333;
 194                 break;
 195         case 0x016:
 196                 dev_priv->fsb_freq = 5866;
 197                 break;
 198         case 0x018:
 199                 dev_priv->fsb_freq = 6400;
 200                 break;
 201         default:
 202                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 203                                  csipll & 0x3ff);
 204                 dev_priv->fsb_freq = 0;
 205                 break;
 206         }
 207
 208         if (dev_priv->fsb_freq == 3200) {
 209                 dev_priv->ips.c_m = 0;
 210         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 211                 dev_priv->ips.c_m = 1;
 212         } else {
 213                 dev_priv->ips.c_m = 2;
 214         }
 215 }
 216
 217 static const struct cxsr_latency cxsr_latency_table[] = {
 218         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 219         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 220         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 221         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 222         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 223
 224         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 225         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 226         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 227         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 228         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 229
 230         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 231         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 232         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 233         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 234         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 235
 236         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 237         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 238         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 239         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 240         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 241
 242         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 243         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 244         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 245         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 246         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 247
 248         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 249         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 250         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 251         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 252         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 253 };
 254
 255 static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
 256                                                          bool is_ddr3,
 257                                                          int fsb,
 258                                                          int mem)
 259 {
 260         const struct cxsr_latency *latency;
 261         int i;
 262
 263         if (fsb == 0 || mem == 0)
 264                 return NULL;
 265
 266         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 267                 latency = &cxsr_latency_table[i];
 268                 if (is_desktop == latency->is_desktop &&
 269                     is_ddr3 == latency->is_ddr3 &&
 270                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 271                         return latency;
 272         }
 273
 274         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 275
 276         return NULL;
 277 }
 278
 279 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 280 {
 281         u32 val;
 282
 283         mutex_lock(&dev_priv->rps.hw_lock);
 284
 285         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 286         if (enable)
 287                 val &= ~FORCE_DDR_HIGH_FREQ;
 288         else
 289                 val |= FORCE_DDR_HIGH_FREQ;
 290         val &= ~FORCE_DDR_LOW_FREQ;
 291         val |= FORCE_DDR_FREQ_REQ_ACK;
 292         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 293
 294         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 295                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 296                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 297
 298         mutex_unlock(&dev_priv->rps.hw_lock);
 299 }
 300
 301 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 302 {
 303         u32 val;
 304
 305         mutex_lock(&dev_priv->rps.hw_lock);
 306
 307         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 308         if (enable)
 309                 val |= DSP_MAXFIFO_PM5_ENABLE;
 310         else
 311                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 312         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 313
 314         mutex_unlock(&dev_priv->rps.hw_lock);
 315 }
 316
 317 #define FW_WM(value, plane) \
 318         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 319
 320 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 321 {
 322         struct drm_device *dev = &dev_priv->drm;
 323         u32 val;
 324
 325         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 326                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 327                 POSTING_READ(FW_BLC_SELF_VLV);
 328                 dev_priv->wm.vlv.cxsr = enable;
 329         } else if (IS_G4X(dev_priv) || IS_CRESTLINE(dev_priv)) {
 330                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 331                 POSTING_READ(FW_BLC_SELF);
 332         } else if (IS_PINEVIEW(dev)) {
 333                 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
 334                 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
 335                 I915_WRITE(DSPFW3, val);
 336                 POSTING_READ(DSPFW3);
 337         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
 338                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 339                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 340                 I915_WRITE(FW_BLC_SELF, val);
 341                 POSTING_READ(FW_BLC_SELF);
 342         } else if (IS_I915GM(dev_priv)) {
 343                 /*
 344                  * FIXME can't find a bit like this for 915G, and
 345                  * and yet it does have the related watermark in
 346                  * FW_BLC_SELF. What's going on?
 347                  */
 348                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 349                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 350                 I915_WRITE(INSTPM, val);
 351                 POSTING_READ(INSTPM);
 352         } else {
 353                 return;
 354         }
 355
 356         DRM_DEBUG_KMS("memory self-refresh is %s\n",
 357                       enable ? "enabled" : "disabled");
 358 }
 359
 360
 361 /*
 362  * Latency for FIFO fetches is dependent on several factors:
 363  *   - memory configuration (speed, channels)
 364  *   - chipset
 365  *   - current MCH state
 366  * It can be fairly high in some situations, so here we assume a fairly
 367  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 368  * set this value too high, the FIFO will fetch frequently to stay full)
 369  * and power consumption (set it too low to save power and we might see
 370  * FIFO underruns and display "flicker").
 371  *
 372  * A value of 5us seems to be a good balance; safe for very low end
 373  * platforms but not overly aggressive on lower latency configs.
 374  */
 375 static const int pessimal_latency_ns = 5000;
 376
 377 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 378         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 379
 380 static int vlv_get_fifo_size(struct drm_device *dev,
 381                               enum pipe pipe, int plane)
 382 {
 383         struct drm_i915_private *dev_priv = to_i915(dev);
 384         int sprite0_start, sprite1_start, size;
 385
 386         switch (pipe) {
 387                 uint32_t dsparb, dsparb2, dsparb3;
 388         case PIPE_A:
 389                 dsparb = I915_READ(DSPARB);
 390                 dsparb2 = I915_READ(DSPARB2);
 391                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 392                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 393                 break;
 394         case PIPE_B:
 395                 dsparb = I915_READ(DSPARB);
 396                 dsparb2 = I915_READ(DSPARB2);
 397                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 398                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 399                 break;
 400         case PIPE_C:
 401                 dsparb2 = I915_READ(DSPARB2);
 402                 dsparb3 = I915_READ(DSPARB3);
 403                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 404                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 405                 break;
 406         default:
 407                 return 0;
 408         }
 409
 410         switch (plane) {
 411         case 0:
 412                 size = sprite0_start;
 413                 break;
 414         case 1:
 415                 size = sprite1_start - sprite0_start;
 416                 break;
 417         case 2:
 418                 size = 512 - 1 - sprite1_start;
 419                 break;
 420         default:
 421                 return 0;
 422         }
 423
 424         DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
 425                       pipe_name(pipe), plane == 0 ? "primary" : "sprite",
 426                       plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
 427                       size);
 428
 429         return size;
 430 }
 431
 432 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 433 {
 434         struct drm_i915_private *dev_priv = to_i915(dev);
 435         uint32_t dsparb = I915_READ(DSPARB);
 436         int size;
 437
 438         size = dsparb & 0x7f;
 439         if (plane)
 440                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 441
 442         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 443                       plane ? "B" : "A", size);
 444
 445         return size;
 446 }
 447
 448 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 449 {
 450         struct drm_i915_private *dev_priv = to_i915(dev);
 451         uint32_t dsparb = I915_READ(DSPARB);
 452         int size;
 453
 454         size = dsparb & 0x1ff;
 455         if (plane)
 456                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 457         size >>= 1; /* Convert to cachelines */
 458
 459         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 460                       plane ? "B" : "A", size);
 461
 462         return size;
 463 }
 464
 465 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 466 {
 467         struct drm_i915_private *dev_priv = to_i915(dev);
 468         uint32_t dsparb = I915_READ(DSPARB);
 469         int size;
 470
 471         size = dsparb & 0x7f;
 472         size >>= 2; /* Convert to cachelines */
 473
 474         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 475                       plane ? "B" : "A",
 476                       size);
 477
 478         return size;
 479 }
 480
 481 /* Pineview has different values for various configs */
 482 static const struct intel_watermark_params pineview_display_wm = {
 483         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 484         .max_wm = PINEVIEW_MAX_WM,
 485         .default_wm = PINEVIEW_DFT_WM,
 486         .guard_size = PINEVIEW_GUARD_WM,
 487         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 488 };
 489 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 490         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 491         .max_wm = PINEVIEW_MAX_WM,
 492         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 493         .guard_size = PINEVIEW_GUARD_WM,
 494         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 495 };
 496 static const struct intel_watermark_params pineview_cursor_wm = {
 497         .fifo_size = PINEVIEW_CURSOR_FIFO,
 498         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 499         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 500         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 501         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 502 };
 503 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 504         .fifo_size = PINEVIEW_CURSOR_FIFO,
 505         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 506         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 507         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 508         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 509 };
 510 static const struct intel_watermark_params g4x_wm_info = {
 511         .fifo_size = G4X_FIFO_SIZE,
 512         .max_wm = G4X_MAX_WM,
 513         .default_wm = G4X_MAX_WM,
 514         .guard_size = 2,
 515         .cacheline_size = G4X_FIFO_LINE_SIZE,
 516 };
 517 static const struct intel_watermark_params g4x_cursor_wm_info = {
 518         .fifo_size = I965_CURSOR_FIFO,
 519         .max_wm = I965_CURSOR_MAX_WM,
 520         .default_wm = I965_CURSOR_DFT_WM,
 521         .guard_size = 2,
 522         .cacheline_size = G4X_FIFO_LINE_SIZE,
 523 };
 524 static const struct intel_watermark_params i965_cursor_wm_info = {
 525         .fifo_size = I965_CURSOR_FIFO,
 526         .max_wm = I965_CURSOR_MAX_WM,
 527         .default_wm = I965_CURSOR_DFT_WM,
 528         .guard_size = 2,
 529         .cacheline_size = I915_FIFO_LINE_SIZE,
 530 };
 531 static const struct intel_watermark_params i945_wm_info = {
 532         .fifo_size = I945_FIFO_SIZE,
 533         .max_wm = I915_MAX_WM,
 534         .default_wm = 1,
 535         .guard_size = 2,
 536         .cacheline_size = I915_FIFO_LINE_SIZE,
 537 };
 538 static const struct intel_watermark_params i915_wm_info = {
 539         .fifo_size = I915_FIFO_SIZE,
 540         .max_wm = I915_MAX_WM,
 541         .default_wm = 1,
 542         .guard_size = 2,
 543         .cacheline_size = I915_FIFO_LINE_SIZE,
 544 };
 545 static const struct intel_watermark_params i830_a_wm_info = {
 546         .fifo_size = I855GM_FIFO_SIZE,
 547         .max_wm = I915_MAX_WM,
 548         .default_wm = 1,
 549         .guard_size = 2,
 550         .cacheline_size = I830_FIFO_LINE_SIZE,
 551 };
 552 static const struct intel_watermark_params i830_bc_wm_info = {
 553         .fifo_size = I855GM_FIFO_SIZE,
 554         .max_wm = I915_MAX_WM/2,
 555         .default_wm = 1,
 556         .guard_size = 2,
 557         .cacheline_size = I830_FIFO_LINE_SIZE,
 558 };
 559 static const struct intel_watermark_params i845_wm_info = {
 560         .fifo_size = I830_FIFO_SIZE,
 561         .max_wm = I915_MAX_WM,
 562         .default_wm = 1,
 563         .guard_size = 2,
 564         .cacheline_size = I830_FIFO_LINE_SIZE,
 565 };
 566
 567 /**
 568  * intel_calculate_wm - calculate watermark level
 569  * @clock_in_khz: pixel clock
 570  * @wm: chip FIFO params
 571  * @cpp: bytes per pixel
 572  * @latency_ns: memory latency for the platform
 573  *
 574  * Calculate the watermark level (the level at which the display plane will
 575  * start fetching from memory again).  Each chip has a different display
 576  * FIFO size and allocation, so the caller needs to figure that out and pass
 577  * in the correct intel_watermark_params structure.
 578  *
 579  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 580  * on the pixel size.  When it reaches the watermark level, it'll start
 581  * fetching FIFO line sized based chunks from memory until the FIFO fills
 582  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 583  * will occur, and a display engine hang could result.
 584  */
 585 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 586                                         const struct intel_watermark_params *wm,
 587                                         int fifo_size, int cpp,
 588                                         unsigned long latency_ns)
 589 {
 590         long entries_required, wm_size;
 591
 592         /*
 593          * Note: we need to make sure we don't overflow for various clock &
 594          * latency values.
 595          * clocks go from a few thousand to several hundred thousand.
 596          * latency is usually a few thousand
 597          */
 598         entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
 599                 1000;
 600         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 601
 602         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 603
 604         wm_size = fifo_size - (entries_required + wm->guard_size);
 605
 606         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 607
 608         /* Don't promote wm_size to unsigned... */
 609         if (wm_size > (long)wm->max_wm)
 610                 wm_size = wm->max_wm;
 611         if (wm_size <= 0)
 612                 wm_size = wm->default_wm;
 613
 614         /*
 615          * Bspec seems to indicate that the value shouldn't be lower than
 616          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 617          * Lets go for 8 which is the burst size since certain platforms
 618          * already use a hardcoded 8 (which is what the spec says should be
 619          * done).
 620          */
 621         if (wm_size <= 8)
 622                 wm_size = 8;
 623
 624         return wm_size;
 625 }
 626
 627 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
 628 {
 629         struct drm_crtc *crtc, *enabled = NULL;
 630
 631         for_each_crtc(dev, crtc) {
 632                 if (intel_crtc_active(crtc)) {
 633                         if (enabled)
 634                                 return NULL;
 635                         enabled = crtc;
 636                 }
 637         }
 638
 639         return enabled;
 640 }
 641
 642 static void pineview_update_wm(struct drm_crtc *unused_crtc)
 643 {
 644         struct drm_device *dev = unused_crtc->dev;
 645         struct drm_i915_private *dev_priv = to_i915(dev);
 646         struct drm_crtc *crtc;
 647         const struct cxsr_latency *latency;
 648         u32 reg;
 649         unsigned long wm;
 650
 651         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
 652                                          dev_priv->is_ddr3,
 653                                          dev_priv->fsb_freq,
 654                                          dev_priv->mem_freq);
 655         if (!latency) {
 656                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 657                 intel_set_memory_cxsr(dev_priv, false);
 658                 return;
 659         }
 660
 661         crtc = single_enabled_crtc(dev);
 662         if (crtc) {
 663                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 664                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 665                 int clock = adjusted_mode->crtc_clock;
 666
 667                 /* Display SR */
 668                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 669                                         pineview_display_wm.fifo_size,
 670                                         cpp, latency->display_sr);
 671                 reg = I915_READ(DSPFW1);
 672                 reg &= ~DSPFW_SR_MASK;
 673                 reg |= FW_WM(wm, SR);
 674                 I915_WRITE(DSPFW1, reg);
 675                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 676
 677                 /* cursor SR */
 678                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 679                                         pineview_display_wm.fifo_size,
 680                                         cpp, latency->cursor_sr);
 681                 reg = I915_READ(DSPFW3);
 682                 reg &= ~DSPFW_CURSOR_SR_MASK;
 683                 reg |= FW_WM(wm, CURSOR_SR);
 684                 I915_WRITE(DSPFW3, reg);
 685
 686                 /* Display HPLL off SR */
 687                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 688                                         pineview_display_hplloff_wm.fifo_size,
 689                                         cpp, latency->display_hpll_disable);
 690                 reg = I915_READ(DSPFW3);
 691                 reg &= ~DSPFW_HPLL_SR_MASK;
 692                 reg |= FW_WM(wm, HPLL_SR);
 693                 I915_WRITE(DSPFW3, reg);
 694
 695                 /* cursor HPLL off SR */
 696                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 697                                         pineview_display_hplloff_wm.fifo_size,
 698                                         cpp, latency->cursor_hpll_disable);
 699                 reg = I915_READ(DSPFW3);
 700                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 701                 reg |= FW_WM(wm, HPLL_CURSOR);
 702                 I915_WRITE(DSPFW3, reg);
 703                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 704
 705                 intel_set_memory_cxsr(dev_priv, true);
 706         } else {
 707                 intel_set_memory_cxsr(dev_priv, false);
 708         }
 709 }
 710
 711 static bool g4x_compute_wm0(struct drm_device *dev,
 712                             int plane,
 713                             const struct intel_watermark_params *display,
 714                             int display_latency_ns,
 715                             const struct intel_watermark_params *cursor,
 716                             int cursor_latency_ns,
 717                             int *plane_wm,
 718                             int *cursor_wm)
 719 {
 720         struct drm_crtc *crtc;
 721         const struct drm_display_mode *adjusted_mode;
 722         int htotal, hdisplay, clock, cpp;
 723         int line_time_us, line_count;
 724         int entries, tlb_miss;
 725
 726         crtc = intel_get_crtc_for_plane(dev, plane);
 727         if (!intel_crtc_active(crtc)) {
 728                 *cursor_wm = cursor->guard_size;
 729                 *plane_wm = display->guard_size;
 730                 return false;
 731         }
 732
 733         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 734         clock = adjusted_mode->crtc_clock;
 735         htotal = adjusted_mode->crtc_htotal;
 736         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 737         cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 738
 739         /* Use the small buffer method to calculate plane watermark */
 740         entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
 741         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
 742         if (tlb_miss > 0)
 743                 entries += tlb_miss;
 744         entries = DIV_ROUND_UP(entries, display->cacheline_size);
 745         *plane_wm = entries + display->guard_size;
 746         if (*plane_wm > (int)display->max_wm)
 747                 *plane_wm = display->max_wm;
 748
 749         /* Use the large buffer method to calculate cursor watermark */
 750         line_time_us = max(htotal * 1000 / clock, 1);
 751         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
 752         entries = line_count * crtc->cursor->state->crtc_w * cpp;
 753         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
 754         if (tlb_miss > 0)
 755                 entries += tlb_miss;
 756         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 757         *cursor_wm = entries + cursor->guard_size;
 758         if (*cursor_wm > (int)cursor->max_wm)
 759                 *cursor_wm = (int)cursor->max_wm;
 760
 761         return true;
 762 }
 763
 764 /*
 765  * Check the wm result.
 766  *
 767  * If any calculated watermark values is larger than the maximum value that
 768  * can be programmed into the associated watermark register, that watermark
 769  * must be disabled.
 770  */
 771 static bool g4x_check_srwm(struct drm_device *dev,
 772                            int display_wm, int cursor_wm,
 773                            const struct intel_watermark_params *display,
 774                            const struct intel_watermark_params *cursor)
 775 {
 776         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
 777                       display_wm, cursor_wm);
 778
 779         if (display_wm > display->max_wm) {
 780                 DRM_DEBUG_KMS("display watermark is too large(%d/%u), disabling\n",
 781                               display_wm, display->max_wm);
 782                 return false;
 783         }
 784
 785         if (cursor_wm > cursor->max_wm) {
 786                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%u), disabling\n",
 787                               cursor_wm, cursor->max_wm);
 788                 return false;
 789         }
 790
 791         if (!(display_wm || cursor_wm)) {
 792                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
 793                 return false;
 794         }
 795
 796         return true;
 797 }
 798
 799 static bool g4x_compute_srwm(struct drm_device *dev,
 800                              int plane,
 801                              int latency_ns,
 802                              const struct intel_watermark_params *display,
 803                              const struct intel_watermark_params *cursor,
 804                              int *display_wm, int *cursor_wm)
 805 {
 806         struct drm_crtc *crtc;
 807         const struct drm_display_mode *adjusted_mode;
 808         int hdisplay, htotal, cpp, clock;
 809         unsigned long line_time_us;
 810         int line_count, line_size;
 811         int small, large;
 812         int entries;
 813
 814         if (!latency_ns) {
 815                 *display_wm = *cursor_wm = 0;
 816                 return false;
 817         }
 818
 819         crtc = intel_get_crtc_for_plane(dev, plane);
 820         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 821         clock = adjusted_mode->crtc_clock;
 822         htotal = adjusted_mode->crtc_htotal;
 823         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 824         cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 825
 826         line_time_us = max(htotal * 1000 / clock, 1);
 827         line_count = (latency_ns / line_time_us + 1000) / 1000;
 828         line_size = hdisplay * cpp;
 829
 830         /* Use the minimum of the small and large buffer method for primary */
 831         small = ((clock * cpp / 1000) * latency_ns) / 1000;
 832         large = line_count * line_size;
 833
 834         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
 835         *display_wm = entries + display->guard_size;
 836
 837         /* calculate the self-refresh watermark for display cursor */
 838         entries = line_count * cpp * crtc->cursor->state->crtc_w;
 839         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 840         *cursor_wm = entries + cursor->guard_size;
 841
 842         return g4x_check_srwm(dev,
 843                               *display_wm, *cursor_wm,
 844                               display, cursor);
 845 }
 846
 847 #define FW_WM_VLV(value, plane) \
 848         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 849
 850 static void vlv_write_wm_values(struct intel_crtc *crtc,
 851                                 const struct vlv_wm_values *wm)
 852 {
 853         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 854         enum pipe pipe = crtc->pipe;
 855
 856         I915_WRITE(VLV_DDL(pipe),
 857                    (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
 858                    (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
 859                    (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
 860                    (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
 861
 862         I915_WRITE(DSPFW1,
 863                    FW_WM(wm->sr.plane, SR) |
 864                    FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
 865                    FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
 866                    FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
 867         I915_WRITE(DSPFW2,
 868                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
 869                    FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
 870                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
 871         I915_WRITE(DSPFW3,
 872                    FW_WM(wm->sr.cursor, CURSOR_SR));
 873
 874         if (IS_CHERRYVIEW(dev_priv)) {
 875                 I915_WRITE(DSPFW7_CHV,
 876                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 877                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 878                 I915_WRITE(DSPFW8_CHV,
 879                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
 880                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
 881                 I915_WRITE(DSPFW9_CHV,
 882                            FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
 883                            FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
 884                 I915_WRITE(DSPHOWM,
 885                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 886                            FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
 887                            FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
 888                            FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
 889                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 890                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 891                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 892                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 893                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 894                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 895         } else {
 896                 I915_WRITE(DSPFW7,
 897                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 898                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 899                 I915_WRITE(DSPHOWM,
 900                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 901                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 902                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 903                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 904                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 905                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 906                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 907         }
 908
 909         /* zero (unused) WM1 watermarks */
 910         I915_WRITE(DSPFW4, 0);
 911         I915_WRITE(DSPFW5, 0);
 912         I915_WRITE(DSPFW6, 0);
 913         I915_WRITE(DSPHOWM1, 0);
 914
 915         POSTING_READ(DSPFW1);
 916 }
 917
 918 #undef FW_WM_VLV
 919
 920 enum vlv_wm_level {
 921         VLV_WM_LEVEL_PM2,
 922         VLV_WM_LEVEL_PM5,
 923         VLV_WM_LEVEL_DDR_DVFS,
 924 };
 925
 926 /* latency must be in 0.1us units. */
 927 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
 928                                    unsigned int pipe_htotal,
 929                                    unsigned int horiz_pixels,
 930                                    unsigned int cpp,
 931                                    unsigned int latency)
 932 {
 933         unsigned int ret;
 934
 935         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
 936         ret = (ret + 1) * horiz_pixels * cpp;
 937         ret = DIV_ROUND_UP(ret, 64);
 938
 939         return ret;
 940 }
 941
 942 static void vlv_setup_wm_latency(struct drm_device *dev)
 943 {
 944         struct drm_i915_private *dev_priv = to_i915(dev);
 945
 946         /* all latencies in usec */
 947         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
 948
 949         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
 950
 951         if (IS_CHERRYVIEW(dev_priv)) {
 952                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
 953                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
 954
 955                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
 956         }
 957 }
 958
 959 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
 960                                      struct intel_crtc *crtc,
 961                                      const struct intel_plane_state *state,
 962                                      int level)
 963 {
 964         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 965         int clock, htotal, cpp, width, wm;
 966
 967         if (dev_priv->wm.pri_latency[level] == 0)
 968                 return USHRT_MAX;
 969
 970         if (!state->base.visible)
 971                 return 0;
 972
 973         cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 974         clock = crtc->config->base.adjusted_mode.crtc_clock;
 975         htotal = crtc->config->base.adjusted_mode.crtc_htotal;
 976         width = crtc->config->pipe_src_w;
 977         if (WARN_ON(htotal == 0))
 978                 htotal = 1;
 979
 980         if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
 981                 /*
 982                  * FIXME the formula gives values that are
 983                  * too big for the cursor FIFO, and hence we
 984                  * would never be able to use cursors. For
 985                  * now just hardcode the watermark.
 986                  */
 987                 wm = 63;
 988         } else {
 989                 wm = vlv_wm_method2(clock, htotal, width, cpp,
 990                                     dev_priv->wm.pri_latency[level] * 10);
 991         }
 992
 993         return min_t(int, wm, USHRT_MAX);
 994 }
 995
 996 static void vlv_compute_fifo(struct intel_crtc *crtc)
 997 {
 998         struct drm_device *dev = crtc->base.dev;
 999         struct vlv_wm_state *wm_state = &crtc->wm_state;
1000         struct intel_plane *plane;
1001         unsigned int total_rate = 0;
1002         const int fifo_size = 512 - 1;
1003         int fifo_extra, fifo_left = fifo_size;
1004
1005         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1006                 struct intel_plane_state *state =
1007                         to_intel_plane_state(plane->base.state);
1008
1009                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1010                         continue;
1011
1012                 if (state->base.visible) {
1013                         wm_state->num_active_planes++;
1014                         total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1015                 }
1016         }
1017
1018         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1019                 struct intel_plane_state *state =
1020                         to_intel_plane_state(plane->base.state);
1021                 unsigned int rate;
1022
1023                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1024                         plane->wm.fifo_size = 63;
1025                         continue;
1026                 }
1027
1028                 if (!state->base.visible) {
1029                         plane->wm.fifo_size = 0;
1030                         continue;
1031                 }
1032
1033                 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1034                 plane->wm.fifo_size = fifo_size * rate / total_rate;
1035                 fifo_left -= plane->wm.fifo_size;
1036         }
1037
1038         fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1039
1040         /* spread the remainder evenly */
1041         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1042                 int plane_extra;
1043
1044                 if (fifo_left == 0)
1045                         break;
1046
1047                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1048                         continue;
1049
1050                 /* give it all to the first plane if none are active */
1051                 if (plane->wm.fifo_size == 0 &&
1052                     wm_state->num_active_planes)
1053                         continue;
1054
1055                 plane_extra = min(fifo_extra, fifo_left);
1056                 plane->wm.fifo_size += plane_extra;
1057                 fifo_left -= plane_extra;
1058         }
1059
1060         WARN_ON(fifo_left != 0);
1061 }
1062
1063 static void vlv_invert_wms(struct intel_crtc *crtc)
1064 {
1065         struct vlv_wm_state *wm_state = &crtc->wm_state;
1066         int level;
1067
1068         for (level = 0; level < wm_state->num_levels; level++) {
1069                 struct drm_device *dev = crtc->base.dev;
1070                 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1071                 struct intel_plane *plane;
1072
1073                 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1074                 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1075
1076                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1077                         switch (plane->base.type) {
1078                                 int sprite;
1079                         case DRM_PLANE_TYPE_CURSOR:
1080                                 wm_state->wm[level].cursor = plane->wm.fifo_size -
1081                                         wm_state->wm[level].cursor;
1082                                 break;
1083                         case DRM_PLANE_TYPE_PRIMARY:
1084                                 wm_state->wm[level].primary = plane->wm.fifo_size -
1085                                         wm_state->wm[level].primary;
1086                                 break;
1087                         case DRM_PLANE_TYPE_OVERLAY:
1088                                 sprite = plane->plane;
1089                                 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1090                                         wm_state->wm[level].sprite[sprite];
1091                                 break;
1092                         }
1093                 }
1094         }
1095 }
1096
1097 static void vlv_compute_wm(struct intel_crtc *crtc)
1098 {
1099         struct drm_device *dev = crtc->base.dev;
1100         struct vlv_wm_state *wm_state = &crtc->wm_state;
1101         struct intel_plane *plane;
1102         int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1103         int level;
1104
1105         memset(wm_state, 0, sizeof(*wm_state));
1106
1107         wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1108         wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1109
1110         wm_state->num_active_planes = 0;
1111
1112         vlv_compute_fifo(crtc);
1113
1114         if (wm_state->num_active_planes != 1)
1115                 wm_state->cxsr = false;
1116
1117         if (wm_state->cxsr) {
1118                 for (level = 0; level < wm_state->num_levels; level++) {
1119                         wm_state->sr[level].plane = sr_fifo_size;
1120                         wm_state->sr[level].cursor = 63;
1121                 }
1122         }
1123
1124         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1125                 struct intel_plane_state *state =
1126                         to_intel_plane_state(plane->base.state);
1127
1128                 if (!state->base.visible)
1129                         continue;
1130
1131                 /* normal watermarks */
1132                 for (level = 0; level < wm_state->num_levels; level++) {
1133                         int wm = vlv_compute_wm_level(plane, crtc, state, level);
1134                         int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1135
1136                         /* hack */
1137                         if (WARN_ON(level == 0 && wm > max_wm))
1138                                 wm = max_wm;
1139
1140                         if (wm > plane->wm.fifo_size)
1141                                 break;
1142
1143                         switch (plane->base.type) {
1144                                 int sprite;
1145                         case DRM_PLANE_TYPE_CURSOR:
1146                                 wm_state->wm[level].cursor = wm;
1147                                 break;
1148                         case DRM_PLANE_TYPE_PRIMARY:
1149                                 wm_state->wm[level].primary = wm;
1150                                 break;
1151                         case DRM_PLANE_TYPE_OVERLAY:
1152                                 sprite = plane->plane;
1153                                 wm_state->wm[level].sprite[sprite] = wm;
1154                                 break;
1155                         }
1156                 }
1157
1158                 wm_state->num_levels = level;
1159
1160                 if (!wm_state->cxsr)
1161                         continue;
1162
1163                 /* maxfifo watermarks */
1164                 switch (plane->base.type) {
1165                         int sprite, level;
1166                 case DRM_PLANE_TYPE_CURSOR:
1167                         for (level = 0; level < wm_state->num_levels; level++)
1168                                 wm_state->sr[level].cursor =
1169                                         wm_state->wm[level].cursor;
1170                         break;
1171                 case DRM_PLANE_TYPE_PRIMARY:
1172                         for (level = 0; level < wm_state->num_levels; level++)
1173                                 wm_state->sr[level].plane =
1174                                         min(wm_state->sr[level].plane,
1175                                             wm_state->wm[level].primary);
1176                         break;
1177                 case DRM_PLANE_TYPE_OVERLAY:
1178                         sprite = plane->plane;
1179                         for (level = 0; level < wm_state->num_levels; level++)
1180                                 wm_state->sr[level].plane =
1181                                         min(wm_state->sr[level].plane,
1182                                             wm_state->wm[level].sprite[sprite]);
1183                         break;
1184                 }
1185         }
1186
1187         /* clear any (partially) filled invalid levels */
1188         for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1189                 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1190                 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1191         }
1192
1193         vlv_invert_wms(crtc);
1194 }
1195
1196 #define VLV_FIFO(plane, value) \
1197         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1198
1199 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1200 {
1201         struct drm_device *dev = crtc->base.dev;
1202         struct drm_i915_private *dev_priv = to_i915(dev);
1203         struct intel_plane *plane;
1204         int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1205
1206         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1207                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1208                         WARN_ON(plane->wm.fifo_size != 63);
1209                         continue;
1210                 }
1211
1212                 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1213                         sprite0_start = plane->wm.fifo_size;
1214                 else if (plane->plane == 0)
1215                         sprite1_start = sprite0_start + plane->wm.fifo_size;
1216                 else
1217                         fifo_size = sprite1_start + plane->wm.fifo_size;
1218         }
1219
1220         WARN_ON(fifo_size != 512 - 1);
1221
1222         DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1223                       pipe_name(crtc->pipe), sprite0_start,
1224                       sprite1_start, fifo_size);
1225
1226         switch (crtc->pipe) {
1227                 uint32_t dsparb, dsparb2, dsparb3;
1228         case PIPE_A:
1229                 dsparb = I915_READ(DSPARB);
1230                 dsparb2 = I915_READ(DSPARB2);
1231
1232                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1233                             VLV_FIFO(SPRITEB, 0xff));
1234                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1235                            VLV_FIFO(SPRITEB, sprite1_start));
1236
1237                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1238                              VLV_FIFO(SPRITEB_HI, 0x1));
1239                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1240                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1241
1242                 I915_WRITE(DSPARB, dsparb);
1243                 I915_WRITE(DSPARB2, dsparb2);
1244                 break;
1245         case PIPE_B:
1246                 dsparb = I915_READ(DSPARB);
1247                 dsparb2 = I915_READ(DSPARB2);
1248
1249                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1250                             VLV_FIFO(SPRITED, 0xff));
1251                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1252                            VLV_FIFO(SPRITED, sprite1_start));
1253
1254                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1255                              VLV_FIFO(SPRITED_HI, 0xff));
1256                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1257                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1258
1259                 I915_WRITE(DSPARB, dsparb);
1260                 I915_WRITE(DSPARB2, dsparb2);
1261                 break;
1262         case PIPE_C:
1263                 dsparb3 = I915_READ(DSPARB3);
1264                 dsparb2 = I915_READ(DSPARB2);
1265
1266                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1267                              VLV_FIFO(SPRITEF, 0xff));
1268                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1269                             VLV_FIFO(SPRITEF, sprite1_start));
1270
1271                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1272                              VLV_FIFO(SPRITEF_HI, 0xff));
1273                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1274                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1275
1276                 I915_WRITE(DSPARB3, dsparb3);
1277                 I915_WRITE(DSPARB2, dsparb2);
1278                 break;
1279         default:
1280                 break;
1281         }
1282 }
1283
1284 #undef VLV_FIFO
1285
1286 static void vlv_merge_wm(struct drm_device *dev,
1287                          struct vlv_wm_values *wm)
1288 {
1289         struct intel_crtc *crtc;
1290         int num_active_crtcs = 0;
1291
1292         wm->level = to_i915(dev)->wm.max_level;
1293         wm->cxsr = true;
1294
1295         for_each_intel_crtc(dev, crtc) {
1296                 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1297
1298                 if (!crtc->active)
1299                         continue;
1300
1301                 if (!wm_state->cxsr)
1302                         wm->cxsr = false;
1303
1304                 num_active_crtcs++;
1305                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1306         }
1307
1308         if (num_active_crtcs != 1)
1309                 wm->cxsr = false;
1310
1311         if (num_active_crtcs > 1)
1312                 wm->level = VLV_WM_LEVEL_PM2;
1313
1314         for_each_intel_crtc(dev, crtc) {
1315                 struct vlv_wm_state *wm_state = &crtc->wm_state;
1316                 enum pipe pipe = crtc->pipe;
1317
1318                 if (!crtc->active)
1319                         continue;
1320
1321                 wm->pipe[pipe] = wm_state->wm[wm->level];
1322                 if (wm->cxsr)
1323                         wm->sr = wm_state->sr[wm->level];
1324
1325                 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1326                 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1327                 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1328                 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1329         }
1330 }
1331
1332 static void vlv_update_wm(struct drm_crtc *crtc)
1333 {
1334         struct drm_device *dev = crtc->dev;
1335         struct drm_i915_private *dev_priv = to_i915(dev);
1336         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1337         enum pipe pipe = intel_crtc->pipe;
1338         struct vlv_wm_values wm = {};
1339
1340         vlv_compute_wm(intel_crtc);
1341         vlv_merge_wm(dev, &wm);
1342
1343         if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1344                 /* FIXME should be part of crtc atomic commit */
1345                 vlv_pipe_set_fifo_size(intel_crtc);
1346                 return;
1347         }
1348
1349         if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1350             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1351                 chv_set_memory_dvfs(dev_priv, false);
1352
1353         if (wm.level < VLV_WM_LEVEL_PM5 &&
1354             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1355                 chv_set_memory_pm5(dev_priv, false);
1356
1357         if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1358                 intel_set_memory_cxsr(dev_priv, false);
1359
1360         /* FIXME should be part of crtc atomic commit */
1361         vlv_pipe_set_fifo_size(intel_crtc);
1362
1363         vlv_write_wm_values(intel_crtc, &wm);
1364
1365         DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1366                       "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1367                       pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1368                       wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1369                       wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1370
1371         if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1372                 intel_set_memory_cxsr(dev_priv, true);
1373
1374         if (wm.level >= VLV_WM_LEVEL_PM5 &&
1375             dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1376                 chv_set_memory_pm5(dev_priv, true);
1377
1378         if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1379             dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1380                 chv_set_memory_dvfs(dev_priv, true);
1381
1382         dev_priv->wm.vlv = wm;
1383 }
1384
1385 #define single_plane_enabled(mask) is_power_of_2(mask)
1386
1387 static void g4x_update_wm(struct drm_crtc *crtc)
1388 {
1389         struct drm_device *dev = crtc->dev;
1390         static const int sr_latency_ns = 12000;
1391         struct drm_i915_private *dev_priv = to_i915(dev);
1392         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1393         int plane_sr, cursor_sr;
1394         unsigned int enabled = 0;
1395         bool cxsr_enabled;
1396
1397         if (g4x_compute_wm0(dev, PIPE_A,
1398                             &g4x_wm_info, pessimal_latency_ns,
1399                             &g4x_cursor_wm_info, pessimal_latency_ns,
1400                             &planea_wm, &cursora_wm))
1401                 enabled |= 1 << PIPE_A;
1402
1403         if (g4x_compute_wm0(dev, PIPE_B,
1404                             &g4x_wm_info, pessimal_latency_ns,
1405                             &g4x_cursor_wm_info, pessimal_latency_ns,
1406                             &planeb_wm, &cursorb_wm))
1407                 enabled |= 1 << PIPE_B;
1408
1409         if (single_plane_enabled(enabled) &&
1410             g4x_compute_srwm(dev, ffs(enabled) - 1,
1411                              sr_latency_ns,
1412                              &g4x_wm_info,
1413                              &g4x_cursor_wm_info,
1414                              &plane_sr, &cursor_sr)) {
1415                 cxsr_enabled = true;
1416         } else {
1417                 cxsr_enabled = false;
1418                 intel_set_memory_cxsr(dev_priv, false);
1419                 plane_sr = cursor_sr = 0;
1420         }
1421
1422         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1423                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1424                       planea_wm, cursora_wm,
1425                       planeb_wm, cursorb_wm,
1426                       plane_sr, cursor_sr);
1427
1428         I915_WRITE(DSPFW1,
1429                    FW_WM(plane_sr, SR) |
1430                    FW_WM(cursorb_wm, CURSORB) |
1431                    FW_WM(planeb_wm, PLANEB) |
1432                    FW_WM(planea_wm, PLANEA));
1433         I915_WRITE(DSPFW2,
1434                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1435                    FW_WM(cursora_wm, CURSORA));
1436         /* HPLL off in SR has some issues on G4x... disable it */
1437         I915_WRITE(DSPFW3,
1438                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1439                    FW_WM(cursor_sr, CURSOR_SR));
1440
1441         if (cxsr_enabled)
1442                 intel_set_memory_cxsr(dev_priv, true);
1443 }
1444
1445 static void i965_update_wm(struct drm_crtc *unused_crtc)
1446 {
1447         struct drm_device *dev = unused_crtc->dev;
1448         struct drm_i915_private *dev_priv = to_i915(dev);
1449         struct drm_crtc *crtc;
1450         int srwm = 1;
1451         int cursor_sr = 16;
1452         bool cxsr_enabled;
1453
1454         /* Calc sr entries for one plane configs */
1455         crtc = single_enabled_crtc(dev);
1456         if (crtc) {
1457                 /* self-refresh has much higher latency */
1458                 static const int sr_latency_ns = 12000;
1459                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1460                 int clock = adjusted_mode->crtc_clock;
1461                 int htotal = adjusted_mode->crtc_htotal;
1462                 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1463                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1464                 unsigned long line_time_us;
1465                 int entries;
1466
1467                 line_time_us = max(htotal * 1000 / clock, 1);
1468
1469                 /* Use ns/us then divide to preserve precision */
1470                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1471                         cpp * hdisplay;
1472                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1473                 srwm = I965_FIFO_SIZE - entries;
1474                 if (srwm < 0)
1475                         srwm = 1;
1476                 srwm &= 0x1ff;
1477                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1478                               entries, srwm);
1479
1480                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1481                         cpp * crtc->cursor->state->crtc_w;
1482                 entries = DIV_ROUND_UP(entries,
1483                                           i965_cursor_wm_info.cacheline_size);
1484                 cursor_sr = i965_cursor_wm_info.fifo_size -
1485                         (entries + i965_cursor_wm_info.guard_size);
1486
1487                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1488                         cursor_sr = i965_cursor_wm_info.max_wm;
1489
1490                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1491                               "cursor %d\n", srwm, cursor_sr);
1492
1493                 cxsr_enabled = true;
1494         } else {
1495                 cxsr_enabled = false;
1496                 /* Turn off self refresh if both pipes are enabled */
1497                 intel_set_memory_cxsr(dev_priv, false);
1498         }
1499
1500         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1501                       srwm);
1502
1503         /* 965 has limitations... */
1504         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1505                    FW_WM(8, CURSORB) |
1506                    FW_WM(8, PLANEB) |
1507                    FW_WM(8, PLANEA));
1508         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1509                    FW_WM(8, PLANEC_OLD));
1510         /* update cursor SR watermark */
1511         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1512
1513         if (cxsr_enabled)
1514                 intel_set_memory_cxsr(dev_priv, true);
1515 }
1516
1517 #undef FW_WM
1518
1519 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1520 {
1521         struct drm_device *dev = unused_crtc->dev;
1522         struct drm_i915_private *dev_priv = to_i915(dev);
1523         const struct intel_watermark_params *wm_info;
1524         uint32_t fwater_lo;
1525         uint32_t fwater_hi;
1526         int cwm, srwm = 1;
1527         int fifo_size;
1528         int planea_wm, planeb_wm;
1529         struct drm_crtc *crtc, *enabled = NULL;
1530
1531         if (IS_I945GM(dev))
1532                 wm_info = &i945_wm_info;
1533         else if (!IS_GEN2(dev_priv))
1534                 wm_info = &i915_wm_info;
1535         else
1536                 wm_info = &i830_a_wm_info;
1537
1538         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1539         crtc = intel_get_crtc_for_plane(dev, 0);
1540         if (intel_crtc_active(crtc)) {
1541                 const struct drm_display_mode *adjusted_mode;
1542                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1543                 if (IS_GEN2(dev_priv))
1544                         cpp = 4;
1545
1546                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1547                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1548                                                wm_info, fifo_size, cpp,
1549                                                pessimal_latency_ns);
1550                 enabled = crtc;
1551         } else {
1552                 planea_wm = fifo_size - wm_info->guard_size;
1553                 if (planea_wm > (long)wm_info->max_wm)
1554                         planea_wm = wm_info->max_wm;
1555         }
1556
1557         if (IS_GEN2(dev_priv))
1558                 wm_info = &i830_bc_wm_info;
1559
1560         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1561         crtc = intel_get_crtc_for_plane(dev, 1);
1562         if (intel_crtc_active(crtc)) {
1563                 const struct drm_display_mode *adjusted_mode;
1564                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1565                 if (IS_GEN2(dev_priv))
1566                         cpp = 4;
1567
1568                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1569                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1570                                                wm_info, fifo_size, cpp,
1571                                                pessimal_latency_ns);
1572                 if (enabled == NULL)
1573                         enabled = crtc;
1574                 else
1575                         enabled = NULL;
1576         } else {
1577                 planeb_wm = fifo_size - wm_info->guard_size;
1578                 if (planeb_wm > (long)wm_info->max_wm)
1579                         planeb_wm = wm_info->max_wm;
1580         }
1581
1582         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1583
1584         if (IS_I915GM(dev_priv) && enabled) {
1585                 struct drm_i915_gem_object *obj;
1586
1587                 obj = intel_fb_obj(enabled->primary->state->fb);
1588
1589                 /* self-refresh seems busted with untiled */
1590                 if (!i915_gem_object_is_tiled(obj))
1591                         enabled = NULL;
1592         }
1593
1594         /*
1595          * Overlay gets an aggressive default since video jitter is bad.
1596          */
1597         cwm = 2;
1598
1599         /* Play safe and disable self-refresh before adjusting watermarks. */
1600         intel_set_memory_cxsr(dev_priv, false);
1601
1602         /* Calc sr entries for one plane configs */
1603         if (HAS_FW_BLC(dev) && enabled) {
1604                 /* self-refresh has much higher latency */
1605                 static const int sr_latency_ns = 6000;
1606                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
1607                 int clock = adjusted_mode->crtc_clock;
1608                 int htotal = adjusted_mode->crtc_htotal;
1609                 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1610                 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
1611                 unsigned long line_time_us;
1612                 int entries;
1613
1614                 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
1615                         cpp = 4;
1616
1617                 line_time_us = max(htotal * 1000 / clock, 1);
1618
1619                 /* Use ns/us then divide to preserve precision */
1620                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1621                         cpp * hdisplay;
1622                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1623                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1624                 srwm = wm_info->fifo_size - entries;
1625                 if (srwm < 0)
1626                         srwm = 1;
1627
1628                 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1629                         I915_WRITE(FW_BLC_SELF,
1630                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1631                 else
1632                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1633         }
1634
1635         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1636                       planea_wm, planeb_wm, cwm, srwm);
1637
1638         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1639         fwater_hi = (cwm & 0x1f);
1640
1641         /* Set request length to 8 cachelines per fetch */
1642         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1643         fwater_hi = fwater_hi | (1 << 8);
1644
1645         I915_WRITE(FW_BLC, fwater_lo);
1646         I915_WRITE(FW_BLC2, fwater_hi);
1647
1648         if (enabled)
1649                 intel_set_memory_cxsr(dev_priv, true);
1650 }
1651
1652 static void i845_update_wm(struct drm_crtc *unused_crtc)
1653 {
1654         struct drm_device *dev = unused_crtc->dev;
1655         struct drm_i915_private *dev_priv = to_i915(dev);
1656         struct drm_crtc *crtc;
1657         const struct drm_display_mode *adjusted_mode;
1658         uint32_t fwater_lo;
1659         int planea_wm;
1660
1661         crtc = single_enabled_crtc(dev);
1662         if (crtc == NULL)
1663                 return;
1664
1665         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1666         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1667                                        &i845_wm_info,
1668                                        dev_priv->display.get_fifo_size(dev, 0),
1669                                        4, pessimal_latency_ns);
1670         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1671         fwater_lo |= (3<<8) | planea_wm;
1672
1673         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1674
1675         I915_WRITE(FW_BLC, fwater_lo);
1676 }
1677
1678 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1679 {
1680         uint32_t pixel_rate;
1681
1682         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1683
1684         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1685          * adjust the pixel_rate here. */
1686
1687         if (pipe_config->pch_pfit.enabled) {
1688                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1689                 uint32_t pfit_size = pipe_config->pch_pfit.size;
1690
1691                 pipe_w = pipe_config->pipe_src_w;
1692                 pipe_h = pipe_config->pipe_src_h;
1693
1694                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1695                 pfit_h = pfit_size & 0xFFFF;
1696                 if (pipe_w < pfit_w)
1697                         pipe_w = pfit_w;
1698                 if (pipe_h < pfit_h)
1699                         pipe_h = pfit_h;
1700
1701                 if (WARN_ON(!pfit_w || !pfit_h))
1702                         return pixel_rate;
1703
1704                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1705                                      pfit_w * pfit_h);
1706         }
1707
1708         return pixel_rate;
1709 }
1710
1711 /* latency must be in 0.1us units. */
1712 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
1713 {
1714         uint64_t ret;
1715
1716         if (WARN(latency == 0, "Latency value missing\n"))
1717                 return UINT_MAX;
1718
1719         ret = (uint64_t) pixel_rate * cpp * latency;
1720         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1721
1722         return ret;
1723 }
1724
1725 /* latency must be in 0.1us units. */
1726 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1727                                uint32_t horiz_pixels, uint8_t cpp,
1728                                uint32_t latency)
1729 {
1730         uint32_t ret;
1731
1732         if (WARN(latency == 0, "Latency value missing\n"))
1733                 return UINT_MAX;
1734         if (WARN_ON(!pipe_htotal))
1735                 return UINT_MAX;
1736
1737         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1738         ret = (ret + 1) * horiz_pixels * cpp;
1739         ret = DIV_ROUND_UP(ret, 64) + 2;
1740         return ret;
1741 }
1742
1743 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1744                            uint8_t cpp)
1745 {
1746         /*
1747          * Neither of these should be possible since this function shouldn't be
1748          * called if the CRTC is off or the plane is invisible.  But let's be
1749          * extra paranoid to avoid a potential divide-by-zero if we screw up
1750          * elsewhere in the driver.
1751          */
1752         if (WARN_ON(!cpp))
1753                 return 0;
1754         if (WARN_ON(!horiz_pixels))
1755                 return 0;
1756
1757         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
1758 }
1759
1760 struct ilk_wm_maximums {
1761         uint16_t pri;
1762         uint16_t spr;
1763         uint16_t cur;
1764         uint16_t fbc;
1765 };
1766
1767 /*
1768  * For both WM_PIPE and WM_LP.
1769  * mem_value must be in 0.1us units.
1770  */
1771 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1772                                    const struct intel_plane_state *pstate,
1773                                    uint32_t mem_value,
1774                                    bool is_lp)
1775 {
1776         int cpp = pstate->base.fb ?
1777                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1778         uint32_t method1, method2;
1779
1780         if (!cstate->base.active || !pstate->base.visible)
1781                 return 0;
1782
1783         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1784
1785         if (!is_lp)
1786                 return method1;
1787
1788         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1789                                  cstate->base.adjusted_mode.crtc_htotal,
1790                                  drm_rect_width(&pstate->base.dst),
1791                                  cpp, mem_value);
1792
1793         return min(method1, method2);
1794 }
1795
1796 /*
1797  * For both WM_PIPE and WM_LP.
1798  * mem_value must be in 0.1us units.
1799  */
1800 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1801                                    const struct intel_plane_state *pstate,
1802                                    uint32_t mem_value)
1803 {
1804         int cpp = pstate->base.fb ?
1805                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1806         uint32_t method1, method2;
1807
1808         if (!cstate->base.active || !pstate->base.visible)
1809                 return 0;
1810
1811         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1812         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1813                                  cstate->base.adjusted_mode.crtc_htotal,
1814                                  drm_rect_width(&pstate->base.dst),
1815                                  cpp, mem_value);
1816         return min(method1, method2);
1817 }
1818
1819 /*
1820  * For both WM_PIPE and WM_LP.
1821  * mem_value must be in 0.1us units.
1822  */
1823 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1824                                    const struct intel_plane_state *pstate,
1825                                    uint32_t mem_value)
1826 {
1827         /*
1828          * We treat the cursor plane as always-on for the purposes of watermark
1829          * calculation.  Until we have two-stage watermark programming merged,
1830          * this is necessary to avoid flickering.
1831          */
1832         int cpp = 4;
1833         int width = pstate->base.visible ? pstate->base.crtc_w : 64;
1834
1835         if (!cstate->base.active)
1836                 return 0;
1837
1838         return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1839                               cstate->base.adjusted_mode.crtc_htotal,
1840                               width, cpp, mem_value);
1841 }
1842
1843 /* Only for WM_LP. */
1844 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1845                                    const struct intel_plane_state *pstate,
1846                                    uint32_t pri_val)
1847 {
1848         int cpp = pstate->base.fb ?
1849                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1850
1851         if (!cstate->base.active || !pstate->base.visible)
1852                 return 0;
1853
1854         return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
1855 }
1856
1857 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1858 {
1859         if (INTEL_INFO(dev)->gen >= 8)
1860                 return 3072;
1861         else if (INTEL_INFO(dev)->gen >= 7)
1862                 return 768;
1863         else
1864                 return 512;
1865 }
1866
1867 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1868                                          int level, bool is_sprite)
1869 {
1870         if (INTEL_INFO(dev)->gen >= 8)
1871                 /* BDW primary/sprite plane watermarks */
1872                 return level == 0 ? 255 : 2047;
1873         else if (INTEL_INFO(dev)->gen >= 7)
1874                 /* IVB/HSW primary/sprite plane watermarks */
1875                 return level == 0 ? 127 : 1023;
1876         else if (!is_sprite)
1877                 /* ILK/SNB primary plane watermarks */
1878                 return level == 0 ? 127 : 511;
1879         else
1880                 /* ILK/SNB sprite plane watermarks */
1881                 return level == 0 ? 63 : 255;
1882 }
1883
1884 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1885                                           int level)
1886 {
1887         if (INTEL_INFO(dev)->gen >= 7)
1888                 return level == 0 ? 63 : 255;
1889         else
1890                 return level == 0 ? 31 : 63;
1891 }
1892
1893 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1894 {
1895         if (INTEL_INFO(dev)->gen >= 8)
1896                 return 31;
1897         else
1898                 return 15;
1899 }
1900
1901 /* Calculate the maximum primary/sprite plane watermark */
1902 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1903                                      int level,
1904                                      const struct intel_wm_config *config,
1905                                      enum intel_ddb_partitioning ddb_partitioning,
1906                                      bool is_sprite)
1907 {
1908         unsigned int fifo_size = ilk_display_fifo_size(dev);
1909
1910         /* if sprites aren't enabled, sprites get nothing */
1911         if (is_sprite && !config->sprites_enabled)
1912                 return 0;
1913
1914         /* HSW allows LP1+ watermarks even with multiple pipes */
1915         if (level == 0 || config->num_pipes_active > 1) {
1916                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1917
1918                 /*
1919                  * For some reason the non self refresh
1920                  * FIFO size is only half of the self
1921                  * refresh FIFO size on ILK/SNB.
1922                  */
1923                 if (INTEL_INFO(dev)->gen <= 6)
1924                         fifo_size /= 2;
1925         }
1926
1927         if (config->sprites_enabled) {
1928                 /* level 0 is always calculated with 1:1 split */
1929                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1930                         if (is_sprite)
1931                                 fifo_size *= 5;
1932                         fifo_size /= 6;
1933                 } else {
1934                         fifo_size /= 2;
1935                 }
1936         }
1937
1938         /* clamp to max that the registers can hold */
1939         return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1940 }
1941
1942 /* Calculate the maximum cursor plane watermark */
1943 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1944                                       int level,
1945                                       const struct intel_wm_config *config)
1946 {
1947         /* HSW LP1+ watermarks w/ multiple pipes */
1948         if (level > 0 && config->num_pipes_active > 1)
1949                 return 64;
1950
1951         /* otherwise just report max that registers can hold */
1952         return ilk_cursor_wm_reg_max(dev, level);
1953 }
1954
1955 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1956                                     int level,
1957                                     const struct intel_wm_config *config,
1958                                     enum intel_ddb_partitioning ddb_partitioning,
1959                                     struct ilk_wm_maximums *max)
1960 {
1961         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1962         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1963         max->cur = ilk_cursor_wm_max(dev, level, config);
1964         max->fbc = ilk_fbc_wm_reg_max(dev);
1965 }
1966
1967 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1968                                         int level,
1969                                         struct ilk_wm_maximums *max)
1970 {
1971         max->pri = ilk_plane_wm_reg_max(dev, level, false);
1972         max->spr = ilk_plane_wm_reg_max(dev, level, true);
1973         max->cur = ilk_cursor_wm_reg_max(dev, level);
1974         max->fbc = ilk_fbc_wm_reg_max(dev);
1975 }
1976
1977 static bool ilk_validate_wm_level(int level,
1978                                   const struct ilk_wm_maximums *max,
1979                                   struct intel_wm_level *result)
1980 {
1981         bool ret;
1982
1983         /* already determined to be invalid? */
1984         if (!result->enable)
1985                 return false;
1986
1987         result->enable = result->pri_val <= max->pri &&
1988                          result->spr_val <= max->spr &&
1989                          result->cur_val <= max->cur;
1990
1991         ret = result->enable;
1992
1993         /*
1994          * HACK until we can pre-compute everything,
1995          * and thus fail gracefully if LP0 watermarks
1996          * are exceeded...
1997          */
1998         if (level == 0 && !result->enable) {
1999                 if (result->pri_val > max->pri)
2000                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2001                                       level, result->pri_val, max->pri);
2002                 if (result->spr_val > max->spr)
2003                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2004                                       level, result->spr_val, max->spr);
2005                 if (result->cur_val > max->cur)
2006                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2007                                       level, result->cur_val, max->cur);
2008
2009                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2010                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2011                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2012                 result->enable = true;
2013         }
2014
2015         return ret;
2016 }
2017
2018 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2019                                  const struct intel_crtc *intel_crtc,
2020                                  int level,
2021                                  struct intel_crtc_state *cstate,
2022                                  struct intel_plane_state *pristate,
2023                                  struct intel_plane_state *sprstate,
2024                                  struct intel_plane_state *curstate,
2025                                  struct intel_wm_level *result)
2026 {
2027         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2028         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2029         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2030
2031         /* WM1+ latency values stored in 0.5us units */
2032         if (level > 0) {
2033                 pri_latency *= 5;
2034                 spr_latency *= 5;
2035                 cur_latency *= 5;
2036         }
2037
2038         if (pristate) {
2039                 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2040                                                      pri_latency, level);
2041                 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2042         }
2043
2044         if (sprstate)
2045                 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2046
2047         if (curstate)
2048                 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2049
2050         result->enable = true;
2051 }
2052
2053 static uint32_t
2054 hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
2055 {
2056         const struct intel_atomic_state *intel_state =
2057                 to_intel_atomic_state(cstate->base.state);
2058         const struct drm_display_mode *adjusted_mode =
2059                 &cstate->base.adjusted_mode;
2060         u32 linetime, ips_linetime;
2061
2062         if (!cstate->base.active)
2063                 return 0;
2064         if (WARN_ON(adjusted_mode->crtc_clock == 0))
2065                 return 0;
2066         if (WARN_ON(intel_state->cdclk == 0))
2067                 return 0;
2068
2069         /* The WM are computed with base on how long it takes to fill a single
2070          * row at the given clock rate, multiplied by 8.
2071          * */
2072         linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2073                                      adjusted_mode->crtc_clock);
2074         ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2075                                          intel_state->cdclk);
2076
2077         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2078                PIPE_WM_LINETIME_TIME(linetime);
2079 }
2080
2081 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2082 {
2083         struct drm_i915_private *dev_priv = to_i915(dev);
2084
2085         if (IS_GEN9(dev_priv)) {
2086                 uint32_t val;
2087                 int ret, i;
2088                 int level, max_level = ilk_wm_max_level(dev_priv);
2089
2090                 /* read the first set of memory latencies[0:3] */
2091                 val = 0; /* data0 to be programmed to 0 for first set */
2092                 mutex_lock(&dev_priv->rps.hw_lock);
2093                 ret = sandybridge_pcode_read(dev_priv,
2094                                              GEN9_PCODE_READ_MEM_LATENCY,
2095                                              &val);
2096                 mutex_unlock(&dev_priv->rps.hw_lock);
2097
2098                 if (ret) {
2099                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2100                         return;
2101                 }
2102
2103                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2104                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2105                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2106                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2107                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2108                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2109                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2110
2111                 /* read the second set of memory latencies[4:7] */
2112                 val = 1; /* data0 to be programmed to 1 for second set */
2113                 mutex_lock(&dev_priv->rps.hw_lock);
2114                 ret = sandybridge_pcode_read(dev_priv,
2115                                              GEN9_PCODE_READ_MEM_LATENCY,
2116                                              &val);
2117                 mutex_unlock(&dev_priv->rps.hw_lock);
2118                 if (ret) {
2119                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2120                         return;
2121                 }
2122
2123                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2124                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2125                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2126                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2127                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2128                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2129                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2130
2131                 /*
2132                  * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2133                  * need to be disabled. We make sure to sanitize the values out
2134                  * of the punit to satisfy this requirement.
2135                  */
2136                 for (level = 1; level <= max_level; level++) {
2137                         if (wm[level] == 0) {
2138                                 for (i = level + 1; i <= max_level; i++)
2139                                         wm[i] = 0;
2140                                 break;
2141                         }
2142                 }
2143
2144                 /*
2145                  * WaWmMemoryReadLatency:skl
2146                  *
2147                  * punit doesn't take into account the read latency so we need
2148                  * to add 2us to the various latency levels we retrieve from the
2149                  * punit when level 0 response data us 0us.
2150                  */
2151                 if (wm[0] == 0) {
2152                         wm[0] += 2;
2153                         for (level = 1; level <= max_level; level++) {
2154                                 if (wm[level] == 0)
2155                                         break;
2156                                 wm[level] += 2;
2157                         }
2158                 }
2159
2160         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2161                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2162
2163                 wm[0] = (sskpd >> 56) & 0xFF;
2164                 if (wm[0] == 0)
2165                         wm[0] = sskpd & 0xF;
2166                 wm[1] = (sskpd >> 4) & 0xFF;
2167                 wm[2] = (sskpd >> 12) & 0xFF;
2168                 wm[3] = (sskpd >> 20) & 0x1FF;
2169                 wm[4] = (sskpd >> 32) & 0x1FF;
2170         } else if (INTEL_INFO(dev)->gen >= 6) {
2171                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2172
2173                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2174                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2175                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2176                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2177         } else if (INTEL_INFO(dev)->gen >= 5) {
2178                 uint32_t mltr = I915_READ(MLTR_ILK);
2179
2180                 /* ILK primary LP0 latency is 700 ns */
2181                 wm[0] = 7;
2182                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2183                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2184         }
2185 }
2186
2187 static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
2188                                        uint16_t wm[5])
2189 {
2190         /* ILK sprite LP0 latency is 1300 ns */
2191         if (IS_GEN5(dev_priv))
2192                 wm[0] = 13;
2193 }
2194
2195 static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2196                                        uint16_t wm[5])
2197 {
2198         /* ILK cursor LP0 latency is 1300 ns */
2199         if (IS_GEN5(dev_priv))
2200                 wm[0] = 13;
2201
2202         /* WaDoubleCursorLP3Latency:ivb */
2203         if (IS_IVYBRIDGE(dev_priv))
2204                 wm[3] *= 2;
2205 }
2206
2207 int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
2208 {
2209         /* how many WM levels are we expecting */
2210         if (INTEL_GEN(dev_priv) >= 9)
2211                 return 7;
2212         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2213                 return 4;
2214         else if (INTEL_GEN(dev_priv) >= 6)
2215                 return 3;
2216         else
2217                 return 2;
2218 }
2219
2220 static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
2221                                    const char *name,
2222                                    const uint16_t wm[8])
2223 {
2224         int level, max_level = ilk_wm_max_level(dev_priv);
2225
2226         for (level = 0; level <= max_level; level++) {
2227                 unsigned int latency = wm[level];
2228
2229                 if (latency == 0) {
2230                         DRM_ERROR("%s WM%d latency not provided\n",
2231                                   name, level);
2232                         continue;
2233                 }
2234
2235                 /*
2236                  * - latencies are in us on gen9.
2237                  * - before then, WM1+ latency values are in 0.5us units
2238                  */
2239                 if (IS_GEN9(dev_priv))
2240                         latency *= 10;
2241                 else if (level > 0)
2242                         latency *= 5;
2243
2244                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2245                               name, level, wm[level],
2246                               latency / 10, latency % 10);
2247         }
2248 }
2249
2250 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2251                                     uint16_t wm[5], uint16_t min)
2252 {
2253         int level, max_level = ilk_wm_max_level(dev_priv);
2254
2255         if (wm[0] >= min)
2256                 return false;
2257
2258         wm[0] = max(wm[0], min);
2259         for (level = 1; level <= max_level; level++)
2260                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2261
2262         return true;
2263 }
2264
2265 static void snb_wm_latency_quirk(struct drm_device *dev)
2266 {
2267         struct drm_i915_private *dev_priv = to_i915(dev);
2268         bool changed;
2269
2270         /*
2271          * The BIOS provided WM memory latency values are often
2272          * inadequate for high resolution displays. Adjust them.
2273          */
2274         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2275                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2276                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2277
2278         if (!changed)
2279                 return;
2280
2281         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2282         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2283         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2284         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
2285 }
2286
2287 static void ilk_setup_wm_latency(struct drm_device *dev)
2288 {
2289         struct drm_i915_private *dev_priv = to_i915(dev);
2290
2291         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2292
2293         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2294                sizeof(dev_priv->wm.pri_latency));
2295         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2296                sizeof(dev_priv->wm.pri_latency));
2297
2298         intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
2299         intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
2300
2301         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2302         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2303         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
2304
2305         if (IS_GEN6(dev_priv))
2306                 snb_wm_latency_quirk(dev);
2307 }
2308
2309 static void skl_setup_wm_latency(struct drm_device *dev)
2310 {
2311         struct drm_i915_private *dev_priv = to_i915(dev);
2312
2313         intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2314         intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
2315 }
2316
2317 static bool ilk_validate_pipe_wm(struct drm_device *dev,
2318                                  struct intel_pipe_wm *pipe_wm)
2319 {
2320         /* LP0 watermark maximums depend on this pipe alone */
2321         const struct intel_wm_config config = {
2322                 .num_pipes_active = 1,
2323                 .sprites_enabled = pipe_wm->sprites_enabled,
2324                 .sprites_scaled = pipe_wm->sprites_scaled,
2325         };
2326         struct ilk_wm_maximums max;
2327
2328         /* LP0 watermarks always use 1/2 DDB partitioning */
2329         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2330
2331         /* At least LP0 must be valid */
2332         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2333                 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2334                 return false;
2335         }
2336
2337         return true;
2338 }
2339
2340 /* Compute new watermarks for the pipe */
2341 static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
2342 {
2343         struct drm_atomic_state *state = cstate->base.state;
2344         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2345         struct intel_pipe_wm *pipe_wm;
2346         struct drm_device *dev = state->dev;
2347         const struct drm_i915_private *dev_priv = to_i915(dev);
2348         struct intel_plane *intel_plane;
2349         struct intel_plane_state *pristate = NULL;
2350         struct intel_plane_state *sprstate = NULL;
2351         struct intel_plane_state *curstate = NULL;
2352         int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
2353         struct ilk_wm_maximums max;
2354
2355         pipe_wm = &cstate->wm.ilk.optimal;
2356
2357         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2358                 struct intel_plane_state *ps;
2359
2360                 ps = intel_atomic_get_existing_plane_state(state,
2361                                                            intel_plane);
2362                 if (!ps)
2363                         continue;
2364
2365                 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2366                         pristate = ps;
2367                 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2368                         sprstate = ps;
2369                 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2370                         curstate = ps;
2371         }
2372
2373         pipe_wm->pipe_enabled = cstate->base.active;
2374         if (sprstate) {
2375                 pipe_wm->sprites_enabled = sprstate->base.visible;
2376                 pipe_wm->sprites_scaled = sprstate->base.visible &&
2377                         (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
2378                          drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
2379         }
2380
2381         usable_level = max_level;
2382
2383         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2384         if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
2385                 usable_level = 1;
2386
2387         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2388         if (pipe_wm->sprites_scaled)
2389                 usable_level = 0;
2390
2391         ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2392                              pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2393
2394         memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2395         pipe_wm->wm[0] = pipe_wm->raw_wm[0];
2396
2397         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2398                 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
2399
2400         if (!ilk_validate_pipe_wm(dev, pipe_wm))
2401                 return -EINVAL;
2402
2403         ilk_compute_wm_reg_maximums(dev, 1, &max);
2404
2405         for (level = 1; level <= max_level; level++) {
2406                 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
2407
2408                 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2409                                      pristate, sprstate, curstate, wm);
2410
2411                 /*
2412                  * Disable any watermark level that exceeds the
2413                  * register maximums since such watermarks are
2414                  * always invalid.
2415                  */
2416                 if (level > usable_level)
2417                         continue;
2418
2419                 if (ilk_validate_wm_level(level, &max, wm))
2420                         pipe_wm->wm[level] = *wm;
2421                 else
2422                         usable_level = level;
2423         }
2424
2425         return 0;
2426 }
2427
2428 /*
2429  * Build a set of 'intermediate' watermark values that satisfy both the old
2430  * state and the new state.  These can be programmed to the hardware
2431  * immediately.
2432  */
2433 static int ilk_compute_intermediate_wm(struct drm_device *dev,
2434                                        struct intel_crtc *intel_crtc,
2435                                        struct intel_crtc_state *newstate)
2436 {
2437         struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
2438         struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2439         int level, max_level = ilk_wm_max_level(to_i915(dev));
2440
2441         /*
2442          * Start with the final, target watermarks, then combine with the
2443          * currently active watermarks to get values that are safe both before
2444          * and after the vblank.
2445          */
2446         *a = newstate->wm.ilk.optimal;
2447         a->pipe_enabled |= b->pipe_enabled;
2448         a->sprites_enabled |= b->sprites_enabled;
2449         a->sprites_scaled |= b->sprites_scaled;
2450
2451         for (level = 0; level <= max_level; level++) {
2452                 struct intel_wm_level *a_wm = &a->wm[level];
2453                 const struct intel_wm_level *b_wm = &b->wm[level];
2454
2455                 a_wm->enable &= b_wm->enable;
2456                 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2457                 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2458                 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2459                 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2460         }
2461
2462         /*
2463          * We need to make sure that these merged watermark values are
2464          * actually a valid configuration themselves.  If they're not,
2465          * there's no safe way to transition from the old state to
2466          * the new state, so we need to fail the atomic transaction.
2467          */
2468         if (!ilk_validate_pipe_wm(dev, a))
2469                 return -EINVAL;
2470
2471         /*
2472          * If our intermediate WM are identical to the final WM, then we can
2473          * omit the post-vblank programming; only update if it's different.
2474          */
2475         if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
2476                 newstate->wm.need_postvbl_update = false;
2477
2478         return 0;
2479 }
2480
2481 /*
2482  * Merge the watermarks from all active pipes for a specific level.
2483  */
2484 static void ilk_merge_wm_level(struct drm_device *dev,
2485                                int level,
2486                                struct intel_wm_level *ret_wm)
2487 {
2488         const struct intel_crtc *intel_crtc;
2489
2490         ret_wm->enable = true;
2491
2492         for_each_intel_crtc(dev, intel_crtc) {
2493                 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
2494                 const struct intel_wm_level *wm = &active->wm[level];
2495
2496                 if (!active->pipe_enabled)
2497                         continue;
2498
2499                 /*
2500                  * The watermark values may have been used in the past,
2501                  * so we must maintain them in the registers for some
2502                  * time even if the level is now disabled.
2503                  */
2504                 if (!wm->enable)
2505                         ret_wm->enable = false;
2506
2507                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2508                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2509                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2510                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2511         }
2512 }
2513
2514 /*
2515  * Merge all low power watermarks for all active pipes.
2516  */
2517 static void ilk_wm_merge(struct drm_device *dev,
2518                          const struct intel_wm_config *config,
2519                          const struct ilk_wm_maximums *max,
2520                          struct intel_pipe_wm *merged)
2521 {
2522         struct drm_i915_private *dev_priv = to_i915(dev);
2523         int level, max_level = ilk_wm_max_level(dev_priv);
2524         int last_enabled_level = max_level;
2525
2526         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2527         if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
2528             config->num_pipes_active > 1)
2529                 last_enabled_level = 0;
2530
2531         /* ILK: FBC WM must be disabled always */
2532         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2533
2534         /* merge each WM1+ level */
2535         for (level = 1; level <= max_level; level++) {
2536                 struct intel_wm_level *wm = &merged->wm[level];
2537
2538                 ilk_merge_wm_level(dev, level, wm);
2539
2540                 if (level > last_enabled_level)
2541                         wm->enable = false;
2542                 else if (!ilk_validate_wm_level(level, max, wm))
2543                         /* make sure all following levels get disabled */
2544                         last_enabled_level = level - 1;
2545
2546                 /*
2547                  * The spec says it is preferred to disable
2548                  * FBC WMs instead of disabling a WM level.
2549                  */
2550                 if (wm->fbc_val > max->fbc) {
2551                         if (wm->enable)
2552                                 merged->fbc_wm_enabled = false;
2553                         wm->fbc_val = 0;
2554                 }
2555         }
2556
2557         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2558         /*
2559          * FIXME this is racy. FBC might get enabled later.
2560          * What we should check here is whether FBC can be
2561          * enabled sometime later.
2562          */
2563         if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
2564             intel_fbc_is_active(dev_priv)) {
2565                 for (level = 2; level <= max_level; level++) {
2566                         struct intel_wm_level *wm = &merged->wm[level];
2567
2568                         wm->enable = false;
2569                 }
2570         }
2571 }
2572
2573 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2574 {
2575         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2576         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2577 }
2578
2579 /* The value we need to program into the WM_LPx latency field */
2580 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2581 {
2582         struct drm_i915_private *dev_priv = to_i915(dev);
2583
2584         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2585                 return 2 * level;
2586         else
2587                 return dev_priv->wm.pri_latency[level];
2588 }
2589
2590 static void ilk_compute_wm_results(struct drm_device *dev,
2591                                    const struct intel_pipe_wm *merged,
2592                                    enum intel_ddb_partitioning partitioning,
2593                                    struct ilk_wm_values *results)
2594 {
2595         struct intel_crtc *intel_crtc;
2596         int level, wm_lp;
2597
2598         results->enable_fbc_wm = merged->fbc_wm_enabled;
2599         results->partitioning = partitioning;
2600
2601         /* LP1+ register values */
2602         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2603                 const struct intel_wm_level *r;
2604
2605                 level = ilk_wm_lp_to_level(wm_lp, merged);
2606
2607                 r = &merged->wm[level];
2608
2609                 /*
2610                  * Maintain the watermark values even if the level is
2611                  * disabled. Doing otherwise could cause underruns.
2612                  */
2613                 results->wm_lp[wm_lp - 1] =
2614                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2615                         (r->pri_val << WM1_LP_SR_SHIFT) |
2616                         r->cur_val;
2617
2618                 if (r->enable)
2619                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2620
2621                 if (INTEL_INFO(dev)->gen >= 8)
2622                         results->wm_lp[wm_lp - 1] |=
2623                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2624                 else
2625                         results->wm_lp[wm_lp - 1] |=
2626                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2627
2628                 /*
2629                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2630                  * level is disabled. Doing otherwise could cause underruns.
2631                  */
2632                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2633                         WARN_ON(wm_lp != 1);
2634                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2635                 } else
2636                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2637         }
2638
2639         /* LP0 register values */
2640         for_each_intel_crtc(dev, intel_crtc) {
2641                 enum pipe pipe = intel_crtc->pipe;
2642                 const struct intel_wm_level *r =
2643                         &intel_crtc->wm.active.ilk.wm[0];
2644
2645                 if (WARN_ON(!r->enable))
2646                         continue;
2647
2648                 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
2649
2650                 results->wm_pipe[pipe] =
2651                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2652                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2653                         r->cur_val;
2654         }
2655 }
2656
2657 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2658  * case both are at the same level. Prefer r1 in case they're the same. */
2659 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2660                                                   struct intel_pipe_wm *r1,
2661                                                   struct intel_pipe_wm *r2)
2662 {
2663         int level, max_level = ilk_wm_max_level(to_i915(dev));
2664         int level1 = 0, level2 = 0;
2665
2666         for (level = 1; level <= max_level; level++) {
2667                 if (r1->wm[level].enable)
2668                         level1 = level;
2669                 if (r2->wm[level].enable)
2670                         level2 = level;
2671         }
2672
2673         if (level1 == level2) {
2674                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2675                         return r2;
2676                 else
2677                         return r1;
2678         } else if (level1 > level2) {
2679                 return r1;
2680         } else {
2681                 return r2;
2682         }
2683 }
2684
2685 /* dirty bits used to track which watermarks need changes */
2686 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2687 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2688 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2689 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2690 #define WM_DIRTY_FBC (1 << 24)
2691 #define WM_DIRTY_DDB (1 << 25)
2692
2693 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2694                                          const struct ilk_wm_values *old,
2695                                          const struct ilk_wm_values *new)
2696 {
2697         unsigned int dirty = 0;
2698         enum pipe pipe;
2699         int wm_lp;
2700
2701         for_each_pipe(dev_priv, pipe) {
2702                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2703                         dirty |= WM_DIRTY_LINETIME(pipe);
2704                         /* Must disable LP1+ watermarks too */
2705                         dirty |= WM_DIRTY_LP_ALL;
2706                 }
2707
2708                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2709                         dirty |= WM_DIRTY_PIPE(pipe);
2710                         /* Must disable LP1+ watermarks too */
2711                         dirty |= WM_DIRTY_LP_ALL;
2712                 }
2713         }
2714
2715         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2716                 dirty |= WM_DIRTY_FBC;
2717                 /* Must disable LP1+ watermarks too */
2718                 dirty |= WM_DIRTY_LP_ALL;
2719         }
2720
2721         if (old->partitioning != new->partitioning) {
2722                 dirty |= WM_DIRTY_DDB;
2723                 /* Must disable LP1+ watermarks too */
2724                 dirty |= WM_DIRTY_LP_ALL;
2725         }
2726
2727         /* LP1+ watermarks already deemed dirty, no need to continue */
2728         if (dirty & WM_DIRTY_LP_ALL)
2729                 return dirty;
2730
2731         /* Find the lowest numbered LP1+ watermark in need of an update... */
2732         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2733                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2734                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2735                         break;
2736         }
2737
2738         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2739         for (; wm_lp <= 3; wm_lp++)
2740                 dirty |= WM_DIRTY_LP(wm_lp);
2741
2742         return dirty;
2743 }
2744
2745 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2746                                unsigned int dirty)
2747 {
2748         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2749         bool changed = false;
2750
2751         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2752                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2753                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2754                 changed = true;
2755         }
2756         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2757                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2758                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2759                 changed = true;
2760         }
2761         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2762                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2763                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2764                 changed = true;
2765         }
2766
2767         /*
2768          * Don't touch WM1S_LP_EN here.
2769          * Doing so could cause underruns.
2770          */
2771
2772         return changed;
2773 }
2774
2775 /*
2776  * The spec says we shouldn't write when we don't need, because every write
2777  * causes WMs to be re-evaluated, expending some power.
2778  */
2779 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2780                                 struct ilk_wm_values *results)
2781 {
2782         struct drm_device *dev = &dev_priv->drm;
2783         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2784         unsigned int dirty;
2785         uint32_t val;
2786
2787         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2788         if (!dirty)
2789                 return;
2790
2791         _ilk_disable_lp_wm(dev_priv, dirty);
2792
2793         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2794                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2795         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2796                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2797         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2798                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2799
2800         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2801                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2802         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2803                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2804         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2805                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2806
2807         if (dirty & WM_DIRTY_DDB) {
2808                 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2809                         val = I915_READ(WM_MISC);
2810                         if (results->partitioning == INTEL_DDB_PART_1_2)
2811                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2812                         else
2813                                 val |= WM_MISC_DATA_PARTITION_5_6;
2814                         I915_WRITE(WM_MISC, val);
2815                 } else {
2816                         val = I915_READ(DISP_ARB_CTL2);
2817                         if (results->partitioning == INTEL_DDB_PART_1_2)
2818                                 val &= ~DISP_DATA_PARTITION_5_6;
2819                         else
2820                                 val |= DISP_DATA_PARTITION_5_6;
2821                         I915_WRITE(DISP_ARB_CTL2, val);
2822                 }
2823         }
2824
2825         if (dirty & WM_DIRTY_FBC) {
2826                 val = I915_READ(DISP_ARB_CTL);
2827                 if (results->enable_fbc_wm)
2828                         val &= ~DISP_FBC_WM_DIS;
2829                 else
2830                         val |= DISP_FBC_WM_DIS;
2831                 I915_WRITE(DISP_ARB_CTL, val);
2832         }
2833
2834         if (dirty & WM_DIRTY_LP(1) &&
2835             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2836                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2837
2838         if (INTEL_INFO(dev)->gen >= 7) {
2839                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2840                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2841                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2842                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2843         }
2844
2845         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2846                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2847         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2848                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2849         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2850                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2851
2852         dev_priv->wm.hw = *results;
2853 }
2854
2855 bool ilk_disable_lp_wm(struct drm_device *dev)
2856 {
2857         struct drm_i915_private *dev_priv = to_i915(dev);
2858
2859         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2860 }
2861
2862 #define SKL_SAGV_BLOCK_TIME     30 /* µs */
2863
2864 /*
2865  * Return the index of a plane in the SKL DDB and wm result arrays.  Primary
2866  * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2867  * other universal planes are in indices 1..n.  Note that this may leave unused
2868  * indices between the top "sprite" plane and the cursor.
2869  */
2870 static int
2871 skl_wm_plane_id(const struct intel_plane *plane)
2872 {
2873         switch (plane->base.type) {
2874         case DRM_PLANE_TYPE_PRIMARY:
2875                 return 0;
2876         case DRM_PLANE_TYPE_CURSOR:
2877                 return PLANE_CURSOR;
2878         case DRM_PLANE_TYPE_OVERLAY:
2879                 return plane->plane + 1;
2880         default:
2881                 MISSING_CASE(plane->base.type);
2882                 return plane->plane;
2883         }
2884 }
2885
2886 /*
2887  * FIXME: We still don't have the proper code detect if we need to apply the WA,
2888  * so assume we'll always need it in order to avoid underruns.
2889  */
2890 static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
2891 {
2892         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2893
2894         if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
2895             IS_KABYLAKE(dev_priv))
2896                 return true;
2897
2898         return false;
2899 }
2900
2901 static bool
2902 intel_has_sagv(struct drm_i915_private *dev_priv)
2903 {
2904         if (IS_KABYLAKE(dev_priv))
2905                 return true;
2906
2907         if (IS_SKYLAKE(dev_priv) &&
2908             dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
2909                 return true;
2910
2911         return false;
2912 }
2913
2914 /*
2915  * SAGV dynamically adjusts the system agent voltage and clock frequencies
2916  * depending on power and performance requirements. The display engine access
2917  * to system memory is blocked during the adjustment time. Because of the
2918  * blocking time, having this enabled can cause full system hangs and/or pipe
2919  * underruns if we don't meet all of the following requirements:
2920  *
2921  *  - <= 1 pipe enabled
2922  *  - All planes can enable watermarks for latencies >= SAGV engine block time
2923  *  - We're not using an interlaced display configuration
2924  */
2925 int
2926 intel_enable_sagv(struct drm_i915_private *dev_priv)
2927 {
2928         int ret;
2929
2930         if (!intel_has_sagv(dev_priv))
2931                 return 0;
2932
2933         if (dev_priv->sagv_status == I915_SAGV_ENABLED)
2934                 return 0;
2935
2936         DRM_DEBUG_KMS("Enabling the SAGV\n");
2937         mutex_lock(&dev_priv->rps.hw_lock);
2938
2939         ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2940                                       GEN9_SAGV_ENABLE);
2941
2942         /* We don't need to wait for the SAGV when enabling */
2943         mutex_unlock(&dev_priv->rps.hw_lock);
2944
2945         /*
2946          * Some skl systems, pre-release machines in particular,
2947          * don't actually have an SAGV.
2948          */
2949         if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
2950                 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
2951                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
2952                 return 0;
2953         } else if (ret < 0) {
2954                 DRM_ERROR("Failed to enable the SAGV\n");
2955                 return ret;
2956         }
2957
2958         dev_priv->sagv_status = I915_SAGV_ENABLED;
2959         return 0;
2960 }
2961
2962 static int
2963 intel_do_sagv_disable(struct drm_i915_private *dev_priv)
2964 {
2965         int ret;
2966         uint32_t temp = GEN9_SAGV_DISABLE;
2967
2968         ret = sandybridge_pcode_read(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2969                                      &temp);
2970         if (ret)
2971                 return ret;
2972         else
2973                 return temp & GEN9_SAGV_IS_DISABLED;
2974 }
2975
2976 int
2977 intel_disable_sagv(struct drm_i915_private *dev_priv)
2978 {
2979         int ret, result;
2980
2981         if (!intel_has_sagv(dev_priv))
2982                 return 0;
2983
2984         if (dev_priv->sagv_status == I915_SAGV_DISABLED)
2985                 return 0;
2986
2987         DRM_DEBUG_KMS("Disabling the SAGV\n");
2988         mutex_lock(&dev_priv->rps.hw_lock);
2989
2990         /* bspec says to keep retrying for at least 1 ms */
2991         ret = wait_for(result = intel_do_sagv_disable(dev_priv), 1);
2992         mutex_unlock(&dev_priv->rps.hw_lock);
2993
2994         if (ret == -ETIMEDOUT) {
2995                 DRM_ERROR("Request to disable SAGV timed out\n");
2996                 return -ETIMEDOUT;
2997         }
2998
2999         /*
3000          * Some skl systems, pre-release machines in particular,
3001          * don't actually have an SAGV.
3002          */
3003         if (IS_SKYLAKE(dev_priv) && result == -ENXIO) {
3004                 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
3005                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
3006                 return 0;
3007         } else if (result < 0) {
3008                 DRM_ERROR("Failed to disable the SAGV\n");
3009                 return result;
3010         }
3011
3012         dev_priv->sagv_status = I915_SAGV_DISABLED;
3013         return 0;
3014 }
3015
3016 bool intel_can_enable_sagv(struct drm_atomic_state *state)
3017 {
3018         struct drm_device *dev = state->dev;
3019         struct drm_i915_private *dev_priv = to_i915(dev);
3020         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3021         struct intel_crtc *crtc;
3022         struct intel_plane *plane;
3023         struct intel_crtc_state *cstate;
3024         struct skl_plane_wm *wm;
3025         enum pipe pipe;
3026         int level, latency;
3027
3028         if (!intel_has_sagv(dev_priv))
3029                 return false;
3030
3031         /*
3032          * SKL workaround: bspec recommends we disable the SAGV when we have
3033          * more then one pipe enabled
3034          *
3035          * If there are no active CRTCs, no additional checks need be performed
3036          */
3037         if (hweight32(intel_state->active_crtcs) == 0)
3038                 return true;
3039         else if (hweight32(intel_state->active_crtcs) > 1)
3040                 return false;
3041
3042         /* Since we're now guaranteed to only have one active CRTC... */
3043         pipe = ffs(intel_state->active_crtcs) - 1;
3044         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3045         cstate = to_intel_crtc_state(crtc->base.state);
3046
3047         if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3048                 return false;
3049
3050         for_each_intel_plane_on_crtc(dev, crtc, plane) {
3051                 wm = &cstate->wm.skl.optimal.planes[skl_wm_plane_id(plane)];
3052
3053                 /* Skip this plane if it's not enabled */
3054                 if (!wm->wm[0].plane_en)
3055                         continue;
3056
3057                 /* Find the highest enabled wm level for this plane */
3058                 for (level = ilk_wm_max_level(dev_priv);
3059                      !wm->wm[level].plane_en; --level)
3060                      { }
3061
3062                 latency = dev_priv->wm.skl_latency[level];
3063
3064                 if (skl_needs_memory_bw_wa(intel_state) &&
3065                     plane->base.state->fb->modifier[0] ==
3066                     I915_FORMAT_MOD_X_TILED)
3067                         latency += 15;
3068
3069                 /*
3070                  * If any of the planes on this pipe don't enable wm levels
3071                  * that incur memory latencies higher then 30µs we can't enable
3072                  * the SAGV
3073                  */
3074                 if (latency < SKL_SAGV_BLOCK_TIME)
3075                         return false;
3076         }
3077
3078         return true;
3079 }
3080
3081 static void
3082 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
3083                                    const struct intel_crtc_state *cstate,
3084                                    struct skl_ddb_entry *alloc, /* out */
3085                                    int *num_active /* out */)
3086 {
3087         struct drm_atomic_state *state = cstate->base.state;
3088         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3089         struct drm_i915_private *dev_priv = to_i915(dev);
3090         struct drm_crtc *for_crtc = cstate->base.crtc;
3091         unsigned int pipe_size, ddb_size;
3092         int nth_active_pipe;
3093
3094         if (WARN_ON(!state) || !cstate->base.active) {
3095                 alloc->start = 0;
3096                 alloc->end = 0;
3097                 *num_active = hweight32(dev_priv->active_crtcs);
3098                 return;
3099         }
3100
3101         if (intel_state->active_pipe_changes)
3102                 *num_active = hweight32(intel_state->active_crtcs);
3103         else
3104                 *num_active = hweight32(dev_priv->active_crtcs);
3105
3106         ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3107         WARN_ON(ddb_size == 0);
3108
3109         ddb_size -= 4; /* 4 blocks for bypass path allocation */
3110
3111         /*
3112          * If the state doesn't change the active CRTC's, then there's
3113          * no need to recalculate; the existing pipe allocation limits
3114          * should remain unchanged.  Note that we're safe from racing
3115          * commits since any racing commit that changes the active CRTC
3116          * list would need to grab _all_ crtc locks, including the one
3117          * we currently hold.
3118          */
3119         if (!intel_state->active_pipe_changes) {
3120                 *alloc = to_intel_crtc(for_crtc)->hw_ddb;
3121                 return;
3122         }
3123
3124         nth_active_pipe = hweight32(intel_state->active_crtcs &
3125                                     (drm_crtc_mask(for_crtc) - 1));
3126         pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3127         alloc->start = nth_active_pipe * ddb_size / *num_active;
3128         alloc->end = alloc->start + pipe_size;
3129 }
3130
3131 static unsigned int skl_cursor_allocation(int num_active)
3132 {
3133         if (num_active == 1)
3134                 return 32;
3135
3136         return 8;
3137 }
3138
3139 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3140 {
3141         entry->start = reg & 0x3ff;
3142         entry->end = (reg >> 16) & 0x3ff;
3143         if (entry->end)
3144                 entry->end += 1;
3145 }
3146
3147 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3148                           struct skl_ddb_allocation *ddb /* out */)
3149 {
3150         enum pipe pipe;
3151         int plane;
3152         u32 val;
3153
3154         memset(ddb, 0, sizeof(*ddb));
3155
3156         for_each_pipe(dev_priv, pipe) {
3157                 enum intel_display_power_domain power_domain;
3158
3159                 power_domain = POWER_DOMAIN_PIPE(pipe);
3160                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
3161                         continue;
3162
3163                 for_each_plane(dev_priv, pipe, plane) {
3164                         val = I915_READ(PLANE_BUF_CFG(pipe, plane));
3165                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
3166                                                    val);
3167                 }
3168
3169                 val = I915_READ(CUR_BUF_CFG(pipe));
3170                 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
3171                                            val);
3172
3173                 intel_display_power_put(dev_priv, power_domain);
3174         }
3175 }
3176
3177 /*
3178  * Determines the downscale amount of a plane for the purposes of watermark calculations.
3179  * The bspec defines downscale amount as:
3180  *
3181  * """
3182  * Horizontal down scale amount = maximum[1, Horizontal source size /
3183  *                                           Horizontal destination size]
3184  * Vertical down scale amount = maximum[1, Vertical source size /
3185  *                                         Vertical destination size]
3186  * Total down scale amount = Horizontal down scale amount *
3187  *                           Vertical down scale amount
3188  * """
3189  *
3190  * Return value is provided in 16.16 fixed point form to retain fractional part.
3191  * Caller should take care of dividing & rounding off the value.
3192  */
3193 static uint32_t
3194 skl_plane_downscale_amount(const struct intel_plane_state *pstate)
3195 {
3196         uint32_t downscale_h, downscale_w;
3197         uint32_t src_w, src_h, dst_w, dst_h;
3198
3199         if (WARN_ON(!pstate->base.visible))
3200                 return DRM_PLANE_HELPER_NO_SCALING;
3201
3202         /* n.b., src is 16.16 fixed point, dst is whole integer */
3203         src_w = drm_rect_width(&pstate->base.src);
3204         src_h = drm_rect_height(&pstate->base.src);
3205         dst_w = drm_rect_width(&pstate->base.dst);
3206         dst_h = drm_rect_height(&pstate->base.dst);
3207         if (drm_rotation_90_or_270(pstate->base.rotation))
3208                 swap(dst_w, dst_h);
3209
3210         downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3211         downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3212
3213         /* Provide result in 16.16 fixed point */
3214         return (uint64_t)downscale_w * downscale_h >> 16;
3215 }
3216
3217 static unsigned int
3218 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3219                              const struct drm_plane_state *pstate,
3220                              int y)
3221 {
3222         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3223         struct drm_framebuffer *fb = pstate->fb;
3224         uint32_t down_scale_amount, data_rate;
3225         uint32_t width = 0, height = 0;
3226         unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3227
3228         if (!intel_pstate->base.visible)
3229                 return 0;
3230         if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3231                 return 0;
3232         if (y && format != DRM_FORMAT_NV12)
3233                 return 0;
3234
3235         width = drm_rect_width(&intel_pstate->base.src) >> 16;
3236         height = drm_rect_height(&intel_pstate->base.src) >> 16;
3237
3238         if (drm_rotation_90_or_270(pstate->rotation))
3239                 swap(width, height);
3240
3241         /* for planar format */
3242         if (format == DRM_FORMAT_NV12) {
3243                 if (y)  /* y-plane data rate */
3244                         data_rate = width * height *
3245                                 drm_format_plane_cpp(format, 0);
3246                 else    /* uv-plane data rate */
3247                         data_rate = (width / 2) * (height / 2) *
3248                                 drm_format_plane_cpp(format, 1);
3249         } else {
3250                 /* for packed formats */
3251                 data_rate = width * height * drm_format_plane_cpp(format, 0);
3252         }
3253
3254         down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3255
3256         return (uint64_t)data_rate * down_scale_amount >> 16;
3257 }
3258
3259 /*
3260  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3261  * a 8192x4096@32bpp framebuffer:
3262  *   3 * 4096 * 8192  * 4 < 2^32
3263  */
3264 static unsigned int
3265 skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
3266 {
3267         struct drm_crtc_state *cstate = &intel_cstate->base;
3268         struct drm_atomic_state *state = cstate->state;
3269         struct drm_crtc *crtc = cstate->crtc;
3270         struct drm_device *dev = crtc->dev;
3271         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3272         const struct drm_plane *plane;
3273         const struct intel_plane *intel_plane;
3274         struct drm_plane_state *pstate;
3275         unsigned int rate, total_data_rate = 0;
3276         int id;
3277         int i;
3278
3279         if (WARN_ON(!state))
3280                 return 0;
3281
3282         /* Calculate and cache data rate for each plane */
3283         for_each_plane_in_state(state, plane, pstate, i) {
3284                 id = skl_wm_plane_id(to_intel_plane(plane));
3285                 intel_plane = to_intel_plane(plane);
3286
3287                 if (intel_plane->pipe != intel_crtc->pipe)
3288                         continue;
3289
3290                 /* packed/uv */
3291                 rate = skl_plane_relative_data_rate(intel_cstate,
3292                                                     pstate, 0);
3293                 intel_cstate->wm.skl.plane_data_rate[id] = rate;
3294
3295                 /* y-plane */
3296                 rate = skl_plane_relative_data_rate(intel_cstate,
3297                                                     pstate, 1);
3298                 intel_cstate->wm.skl.plane_y_data_rate[id] = rate;
3299         }
3300
3301         /* Calculate CRTC's total data rate from cached values */
3302         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3303                 int id = skl_wm_plane_id(intel_plane);
3304
3305                 /* packed/uv */
3306                 total_data_rate += intel_cstate->wm.skl.plane_data_rate[id];
3307                 total_data_rate += intel_cstate->wm.skl.plane_y_data_rate[id];
3308         }
3309
3310         return total_data_rate;
3311 }
3312
3313 static uint16_t
3314 skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3315                   const int y)
3316 {
3317         struct drm_framebuffer *fb = pstate->fb;
3318         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3319         uint32_t src_w, src_h;
3320         uint32_t min_scanlines = 8;
3321         uint8_t plane_bpp;
3322
3323         if (WARN_ON(!fb))
3324                 return 0;
3325
3326         /* For packed formats, no y-plane, return 0 */
3327         if (y && fb->pixel_format != DRM_FORMAT_NV12)
3328                 return 0;
3329
3330         /* For Non Y-tile return 8-blocks */
3331         if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
3332             fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
3333                 return 8;
3334
3335         src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
3336         src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
3337
3338         if (drm_rotation_90_or_270(pstate->rotation))
3339                 swap(src_w, src_h);
3340
3341         /* Halve UV plane width and height for NV12 */
3342         if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3343                 src_w /= 2;
3344                 src_h /= 2;
3345         }
3346
3347         if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3348                 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3349         else
3350                 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3351
3352         if (drm_rotation_90_or_270(pstate->rotation)) {
3353                 switch (plane_bpp) {
3354                 case 1:
3355                         min_scanlines = 32;
3356                         break;
3357                 case 2:
3358                         min_scanlines = 16;
3359                         break;
3360                 case 4:
3361                         min_scanlines = 8;
3362                         break;
3363                 case 8:
3364                         min_scanlines = 4;
3365                         break;
3366                 default:
3367                         WARN(1, "Unsupported pixel depth %u for rotation",
3368                              plane_bpp);
3369                         min_scanlines = 32;
3370                 }
3371         }
3372
3373         return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3374 }
3375
3376 static int
3377 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
3378                       struct skl_ddb_allocation *ddb /* out */)
3379 {
3380         struct drm_atomic_state *state = cstate->base.state;
3381         struct drm_crtc *crtc = cstate->base.crtc;
3382         struct drm_device *dev = crtc->dev;
3383         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3384         struct intel_plane *intel_plane;
3385         struct drm_plane *plane;
3386         struct drm_plane_state *pstate;
3387         enum pipe pipe = intel_crtc->pipe;
3388         struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
3389         uint16_t alloc_size, start, cursor_blocks;
3390         uint16_t *minimum = cstate->wm.skl.minimum_blocks;
3391         uint16_t *y_minimum = cstate->wm.skl.minimum_y_blocks;
3392         unsigned int total_data_rate;
3393         int num_active;
3394         int id, i;
3395
3396         /* Clear the partitioning for disabled planes. */
3397         memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3398         memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3399
3400         if (WARN_ON(!state))
3401                 return 0;
3402
3403         if (!cstate->base.active) {
3404                 alloc->start = alloc->end = 0;
3405                 return 0;
3406         }
3407
3408         skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
3409         alloc_size = skl_ddb_entry_size(alloc);
3410         if (alloc_size == 0) {
3411                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3412                 return 0;
3413         }
3414
3415         cursor_blocks = skl_cursor_allocation(num_active);
3416         ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3417         ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3418
3419         alloc_size -= cursor_blocks;
3420
3421         /* 1. Allocate the mininum required blocks for each active plane */
3422         for_each_plane_in_state(state, plane, pstate, i) {
3423                 intel_plane = to_intel_plane(plane);
3424                 id = skl_wm_plane_id(intel_plane);
3425
3426                 if (intel_plane->pipe != pipe)
3427                         continue;
3428
3429                 if (!to_intel_plane_state(pstate)->base.visible) {
3430                         minimum[id] = 0;
3431                         y_minimum[id] = 0;
3432                         continue;
3433                 }
3434                 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3435                         minimum[id] = 0;
3436                         y_minimum[id] = 0;
3437                         continue;
3438                 }
3439
3440                 minimum[id] = skl_ddb_min_alloc(pstate, 0);
3441                 y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
3442         }
3443
3444         for (i = 0; i < PLANE_CURSOR; i++) {
3445                 alloc_size -= minimum[i];
3446                 alloc_size -= y_minimum[i];
3447         }
3448
3449         /*
3450          * 2. Distribute the remaining space in proportion to the amount of
3451          * data each plane needs to fetch from memory.
3452          *
3453          * FIXME: we may not allocate every single block here.
3454          */
3455         total_data_rate = skl_get_total_relative_data_rate(cstate);
3456         if (total_data_rate == 0)
3457                 return 0;
3458
3459         start = alloc->start;
3460         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3461                 unsigned int data_rate, y_data_rate;
3462                 uint16_t plane_blocks, y_plane_blocks = 0;
3463                 int id = skl_wm_plane_id(intel_plane);
3464
3465                 data_rate = cstate->wm.skl.plane_data_rate[id];
3466
3467                 /*
3468                  * allocation for (packed formats) or (uv-plane part of planar format):
3469                  * promote the expression to 64 bits to avoid overflowing, the
3470                  * result is < available as data_rate / total_data_rate < 1
3471                  */
3472                 plane_blocks = minimum[id];
3473                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3474                                         total_data_rate);
3475
3476                 /* Leave disabled planes at (0,0) */
3477                 if (data_rate) {
3478                         ddb->plane[pipe][id].start = start;
3479                         ddb->plane[pipe][id].end = start + plane_blocks;
3480                 }
3481
3482                 start += plane_blocks;
3483
3484                 /*
3485                  * allocation for y_plane part of planar format:
3486                  */
3487                 y_data_rate = cstate->wm.skl.plane_y_data_rate[id];
3488
3489                 y_plane_blocks = y_minimum[id];
3490                 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3491                                         total_data_rate);
3492
3493                 if (y_data_rate) {
3494                         ddb->y_plane[pipe][id].start = start;
3495                         ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3496                 }
3497
3498                 start += y_plane_blocks;
3499         }
3500
3501         return 0;
3502 }
3503
3504 /*
3505  * The max latency should be 257 (max the punit can code is 255 and we add 2us
3506  * for the read latency) and cpp should always be <= 8, so that
3507  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3508  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3509 */
3510 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
3511 {
3512         uint32_t wm_intermediate_val, ret;
3513
3514         if (latency == 0)
3515                 return UINT_MAX;
3516
3517         wm_intermediate_val = latency * pixel_rate * cpp / 512;
3518         ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3519
3520         return ret;
3521 }
3522
3523 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3524                                uint32_t latency, uint32_t plane_blocks_per_line)
3525 {
3526         uint32_t ret;
3527         uint32_t wm_intermediate_val;
3528
3529         if (latency == 0)
3530                 return UINT_MAX;
3531
3532         wm_intermediate_val = latency * pixel_rate;
3533         ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3534                                 plane_blocks_per_line;
3535
3536         return ret;
3537 }
3538
3539 static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3540                                               struct intel_plane_state *pstate)
3541 {
3542         uint64_t adjusted_pixel_rate;
3543         uint64_t downscale_amount;
3544         uint64_t pixel_rate;
3545
3546         /* Shouldn't reach here on disabled planes... */
3547         if (WARN_ON(!pstate->base.visible))
3548                 return 0;
3549
3550         /*
3551          * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3552          * with additional adjustments for plane-specific scaling.
3553          */
3554         adjusted_pixel_rate = ilk_pipe_pixel_rate(cstate);
3555         downscale_amount = skl_plane_downscale_amount(pstate);
3556
3557         pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3558         WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3559
3560         return pixel_rate;
3561 }
3562
3563 static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3564                                 struct intel_crtc_state *cstate,
3565                                 struct intel_plane_state *intel_pstate,
3566                                 uint16_t ddb_allocation,
3567                                 int level,
3568                                 uint16_t *out_blocks, /* out */
3569                                 uint8_t *out_lines, /* out */
3570                                 bool *enabled /* out */)
3571 {
3572         struct drm_plane_state *pstate = &intel_pstate->base;
3573         struct drm_framebuffer *fb = pstate->fb;
3574         uint32_t latency = dev_priv->wm.skl_latency[level];
3575         uint32_t method1, method2;
3576         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3577         uint32_t res_blocks, res_lines;
3578         uint32_t selected_result;
3579         uint8_t cpp;
3580         uint32_t width = 0, height = 0;
3581         uint32_t plane_pixel_rate;
3582         uint32_t y_tile_minimum, y_min_scanlines;
3583         struct intel_atomic_state *state =
3584                 to_intel_atomic_state(cstate->base.state);
3585         bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
3586
3587         if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
3588                 *enabled = false;
3589                 return 0;
3590         }
3591
3592         if (apply_memory_bw_wa && fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3593                 latency += 15;
3594
3595         width = drm_rect_width(&intel_pstate->base.src) >> 16;
3596         height = drm_rect_height(&intel_pstate->base.src) >> 16;
3597
3598         if (drm_rotation_90_or_270(pstate->rotation))
3599                 swap(width, height);
3600
3601         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3602         plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3603
3604         if (drm_rotation_90_or_270(pstate->rotation)) {
3605                 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3606                         drm_format_plane_cpp(fb->pixel_format, 1) :
3607                         drm_format_plane_cpp(fb->pixel_format, 0);
3608
3609                 switch (cpp) {
3610                 case 1:
3611                         y_min_scanlines = 16;
3612                         break;
3613                 case 2:
3614                         y_min_scanlines = 8;
3615                         break;
3616                 case 4:
3617                         y_min_scanlines = 4;
3618                         break;
3619                 default:
3620                         MISSING_CASE(cpp);
3621                         return -EINVAL;
3622                 }
3623         } else {
3624                 y_min_scanlines = 4;
3625         }
3626
3627         plane_bytes_per_line = width * cpp;
3628         if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3629             fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3630                 plane_blocks_per_line =
3631                       DIV_ROUND_UP(plane_bytes_per_line * y_min_scanlines, 512);
3632                 plane_blocks_per_line /= y_min_scanlines;
3633         } else if (fb->modifier[0] == DRM_FORMAT_MOD_NONE) {
3634                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512)
3635                                         + 1;
3636         } else {
3637                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3638         }
3639
3640         method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3641         method2 = skl_wm_method2(plane_pixel_rate,
3642                                  cstate->base.adjusted_mode.crtc_htotal,
3643                                  latency,
3644                                  plane_blocks_per_line);
3645
3646         y_tile_minimum = plane_blocks_per_line * y_min_scanlines;
3647         if (apply_memory_bw_wa)
3648                 y_tile_minimum *= 2;
3649
3650         if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3651             fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3652                 selected_result = max(method2, y_tile_minimum);
3653         } else {
3654                 if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) &&
3655                     (plane_bytes_per_line / 512 < 1))
3656                         selected_result = method2;
3657                 else if ((ddb_allocation / plane_blocks_per_line) >= 1)
3658                         selected_result = min(method1, method2);
3659                 else
3660                         selected_result = method1;
3661         }
3662
3663         res_blocks = selected_result + 1;
3664         res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3665
3666         if (level >= 1 && level <= 7) {
3667                 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3668                     fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3669                         res_blocks += y_tile_minimum;
3670                         res_lines += y_min_scanlines;
3671                 } else {
3672                         res_blocks++;
3673                 }
3674         }
3675
3676         if (res_blocks >= ddb_allocation || res_lines > 31) {
3677                 *enabled = false;
3678
3679                 /*
3680                  * If there are no valid level 0 watermarks, then we can't
3681                  * support this display configuration.
3682                  */
3683                 if (level) {
3684                         return 0;
3685                 } else {
3686                         DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3687                         DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3688                                       to_intel_crtc(cstate->base.crtc)->pipe,
3689                                       skl_wm_plane_id(to_intel_plane(pstate->plane)),
3690                                       res_blocks, ddb_allocation, res_lines);
3691
3692                         return -EINVAL;
3693                 }
3694         }
3695
3696         *out_blocks = res_blocks;
3697         *out_lines = res_lines;
3698         *enabled = true;
3699
3700         return 0;
3701 }
3702
3703 static int
3704 skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3705                      struct skl_ddb_allocation *ddb,
3706                      struct intel_crtc_state *cstate,
3707                      struct intel_plane *intel_plane,
3708                      int level,
3709                      struct skl_wm_level *result)
3710 {
3711         struct drm_atomic_state *state = cstate->base.state;
3712         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3713         struct drm_plane *plane = &intel_plane->base;
3714         struct intel_plane_state *intel_pstate = NULL;
3715         uint16_t ddb_blocks;
3716         enum pipe pipe = intel_crtc->pipe;
3717         int ret;
3718         int i = skl_wm_plane_id(intel_plane);
3719
3720         if (state)
3721                 intel_pstate =
3722                         intel_atomic_get_existing_plane_state(state,
3723                                                               intel_plane);
3724
3725         /*
3726          * Note: If we start supporting multiple pending atomic commits against
3727          * the same planes/CRTC's in the future, plane->state will no longer be
3728          * the correct pre-state to use for the calculations here and we'll
3729          * need to change where we get the 'unchanged' plane data from.
3730          *
3731          * For now this is fine because we only allow one queued commit against
3732          * a CRTC.  Even if the plane isn't modified by this transaction and we
3733          * don't have a plane lock, we still have the CRTC's lock, so we know
3734          * that no other transactions are racing with us to update it.
3735          */
3736         if (!intel_pstate)
3737                 intel_pstate = to_intel_plane_state(plane->state);
3738
3739         WARN_ON(!intel_pstate->base.fb);
3740
3741         ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3742
3743         ret = skl_compute_plane_wm(dev_priv,
3744                                    cstate,
3745                                    intel_pstate,
3746                                    ddb_blocks,
3747                                    level,
3748                                    &result->plane_res_b,
3749                                    &result->plane_res_l,
3750                                    &result->plane_en);
3751         if (ret)
3752                 return ret;
3753
3754         return 0;
3755 }
3756
3757 static uint32_t
3758 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3759 {
3760         uint32_t pixel_rate;
3761
3762         if (!cstate->base.active)
3763                 return 0;
3764
3765         pixel_rate = ilk_pipe_pixel_rate(cstate);
3766
3767         if (WARN_ON(pixel_rate == 0))
3768                 return 0;
3769
3770         return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3771                             pixel_rate);
3772 }
3773
3774 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3775                                       struct skl_wm_level *trans_wm /* out */)
3776 {
3777         if (!cstate->base.active)
3778                 return;
3779
3780         /* Until we know more, just disable transition WMs */
3781         trans_wm->plane_en = false;
3782 }
3783
3784 static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3785                              struct skl_ddb_allocation *ddb,
3786                              struct skl_pipe_wm *pipe_wm)
3787 {
3788         struct drm_device *dev = cstate->base.crtc->dev;
3789         const struct drm_i915_private *dev_priv = to_i915(dev);
3790         struct intel_plane *intel_plane;
3791         struct skl_plane_wm *wm;
3792         int level, max_level = ilk_wm_max_level(dev_priv);
3793         int ret;
3794
3795         /*
3796          * We'll only calculate watermarks for planes that are actually
3797          * enabled, so make sure all other planes are set as disabled.
3798          */
3799         memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
3800
3801         for_each_intel_plane_mask(&dev_priv->drm,
3802                                   intel_plane,
3803                                   cstate->base.plane_mask) {
3804                 wm = &pipe_wm->planes[skl_wm_plane_id(intel_plane)];
3805
3806                 for (level = 0; level <= max_level; level++) {
3807                         ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3808                                                    intel_plane, level,
3809                                                    &wm->wm[level]);
3810                         if (ret)
3811                                 return ret;
3812                 }
3813                 skl_compute_transition_wm(cstate, &wm->trans_wm);
3814         }
3815         pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3816
3817         return 0;
3818 }
3819
3820 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3821                                 i915_reg_t reg,
3822                                 const struct skl_ddb_entry *entry)
3823 {
3824         if (entry->end)
3825                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3826         else
3827                 I915_WRITE(reg, 0);
3828 }
3829
3830 static void skl_write_wm_level(struct drm_i915_private *dev_priv,
3831                                i915_reg_t reg,
3832                                const struct skl_wm_level *level)
3833 {
3834         uint32_t val = 0;
3835
3836         if (level->plane_en) {
3837                 val |= PLANE_WM_EN;
3838                 val |= level->plane_res_b;
3839                 val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
3840         }
3841
3842         I915_WRITE(reg, val);
3843 }
3844
3845 void skl_write_plane_wm(struct intel_crtc *intel_crtc,
3846                         const struct skl_plane_wm *wm,
3847                         const struct skl_ddb_allocation *ddb,
3848                         int plane)
3849 {
3850         struct drm_crtc *crtc = &intel_crtc->base;
3851         struct drm_device *dev = crtc->dev;
3852         struct drm_i915_private *dev_priv = to_i915(dev);
3853         int level, max_level = ilk_wm_max_level(dev_priv);
3854         enum pipe pipe = intel_crtc->pipe;
3855
3856         for (level = 0; level <= max_level; level++) {
3857                 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane, level),
3858                                    &wm->wm[level]);
3859         }
3860         skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane),
3861                            &wm->trans_wm);
3862
3863         skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane),
3864                             &ddb->plane[pipe][plane]);
3865         skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane),
3866                             &ddb->y_plane[pipe][plane]);
3867 }
3868
3869 void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
3870                          const struct skl_plane_wm *wm,
3871                          const struct skl_ddb_allocation *ddb)
3872 {
3873         struct drm_crtc *crtc = &intel_crtc->base;
3874         struct drm_device *dev = crtc->dev;
3875         struct drm_i915_private *dev_priv = to_i915(dev);
3876         int level, max_level = ilk_wm_max_level(dev_priv);
3877         enum pipe pipe = intel_crtc->pipe;
3878
3879         for (level = 0; level <= max_level; level++) {
3880                 skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
3881                                    &wm->wm[level]);
3882         }
3883         skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
3884
3885         skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3886                             &ddb->plane[pipe][PLANE_CURSOR]);
3887 }
3888
3889 bool skl_wm_level_equals(const struct skl_wm_level *l1,
3890                          const struct skl_wm_level *l2)
3891 {
3892         if (l1->plane_en != l2->plane_en)
3893                 return false;
3894
3895         /* If both planes aren't enabled, the rest shouldn't matter */
3896         if (!l1->plane_en)
3897                 return true;
3898
3899         return (l1->plane_res_l == l2->plane_res_l &&
3900                 l1->plane_res_b == l2->plane_res_b);
3901 }
3902
3903 static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
3904                                            const struct skl_ddb_entry *b)
3905 {
3906         return a->start < b->end && b->start < a->end;
3907 }
3908
3909 bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state,
3910                                  struct intel_crtc *intel_crtc)
3911 {
3912         struct drm_crtc *other_crtc;
3913         struct drm_crtc_state *other_cstate;
3914         struct intel_crtc *other_intel_crtc;
3915         const struct skl_ddb_entry *ddb =
3916                 &to_intel_crtc_state(intel_crtc->base.state)->wm.skl.ddb;
3917         int i;
3918
3919         for_each_crtc_in_state(state, other_crtc, other_cstate, i) {
3920                 other_intel_crtc = to_intel_crtc(other_crtc);
3921
3922                 if (other_intel_crtc == intel_crtc)
3923                         continue;
3924
3925                 if (skl_ddb_entries_overlap(ddb, &other_intel_crtc->hw_ddb))
3926                         return true;
3927         }
3928
3929         return false;
3930 }
3931
3932 static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
3933                               struct skl_ddb_allocation *ddb, /* out */
3934                               struct skl_pipe_wm *pipe_wm, /* out */
3935                               bool *changed /* out */)
3936 {
3937         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->crtc);
3938         struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
3939         int ret;
3940
3941         ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3942         if (ret)
3943                 return ret;
3944
3945         if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
3946                 *changed = false;
3947         else
3948                 *changed = true;
3949
3950         return 0;
3951 }
3952
3953 static uint32_t
3954 pipes_modified(struct drm_atomic_state *state)
3955 {
3956         struct drm_crtc *crtc;
3957         struct drm_crtc_state *cstate;
3958         uint32_t i, ret = 0;
3959
3960         for_each_crtc_in_state(state, crtc, cstate, i)
3961                 ret |= drm_crtc_mask(crtc);
3962
3963         return ret;
3964 }
3965
3966 static int
3967 skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
3968 {
3969         struct drm_atomic_state *state = cstate->base.state;
3970         struct drm_device *dev = state->dev;
3971         struct drm_crtc *crtc = cstate->base.crtc;
3972         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3973         struct drm_i915_private *dev_priv = to_i915(dev);
3974         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3975         struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
3976         struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3977         struct drm_plane_state *plane_state;
3978         struct drm_plane *plane;
3979         enum pipe pipe = intel_crtc->pipe;
3980         int id;
3981
3982         WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
3983
3984         drm_for_each_plane_mask(plane, dev, crtc->state->plane_mask) {
3985                 id = skl_wm_plane_id(to_intel_plane(plane));
3986
3987                 if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][id],
3988                                         &new_ddb->plane[pipe][id]) &&
3989                     skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][id],
3990                                         &new_ddb->y_plane[pipe][id]))
3991                         continue;
3992
3993                 plane_state = drm_atomic_get_plane_state(state, plane);
3994                 if (IS_ERR(plane_state))
3995                         return PTR_ERR(plane_state);
3996         }
3997
3998         return 0;
3999 }
4000
4001 static int
4002 skl_compute_ddb(struct drm_atomic_state *state)
4003 {
4004         struct drm_device *dev = state->dev;
4005         struct drm_i915_private *dev_priv = to_i915(dev);
4006         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4007         struct intel_crtc *intel_crtc;
4008         struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
4009         uint32_t realloc_pipes = pipes_modified(state);
4010         int ret;
4011
4012         /*
4013          * If this is our first atomic update following hardware readout,
4014          * we can't trust the DDB that the BIOS programmed for us.  Let's
4015          * pretend that all pipes switched active status so that we'll
4016          * ensure a full DDB recompute.
4017          */
4018         if (dev_priv->wm.distrust_bios_wm) {
4019                 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
4020                                        state->acquire_ctx);
4021                 if (ret)
4022                         return ret;
4023
4024                 intel_state->active_pipe_changes = ~0;
4025
4026                 /*
4027                  * We usually only initialize intel_state->active_crtcs if we
4028                  * we're doing a modeset; make sure this field is always
4029                  * initialized during the sanitization process that happens
4030                  * on the first commit too.
4031                  */
4032                 if (!intel_state->modeset)
4033                         intel_state->active_crtcs = dev_priv->active_crtcs;
4034         }
4035
4036         /*
4037          * If the modeset changes which CRTC's are active, we need to
4038          * recompute the DDB allocation for *all* active pipes, even
4039          * those that weren't otherwise being modified in any way by this
4040          * atomic commit.  Due to the shrinking of the per-pipe allocations
4041          * when new active CRTC's are added, it's possible for a pipe that
4042          * we were already using and aren't changing at all here to suddenly
4043          * become invalid if its DDB needs exceeds its new allocation.
4044          *
4045          * Note that if we wind up doing a full DDB recompute, we can't let
4046          * any other display updates race with this transaction, so we need
4047          * to grab the lock on *all* CRTC's.
4048          */
4049         if (intel_state->active_pipe_changes) {
4050                 realloc_pipes = ~0;
4051                 intel_state->wm_results.dirty_pipes = ~0;
4052         }
4053
4054         /*
4055          * We're not recomputing for the pipes not included in the commit, so
4056          * make sure we start with the current state.
4057          */
4058         memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
4059
4060         for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4061                 struct intel_crtc_state *cstate;
4062
4063                 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4064                 if (IS_ERR(cstate))
4065                         return PTR_ERR(cstate);
4066
4067                 ret = skl_allocate_pipe_ddb(cstate, ddb);
4068                 if (ret)
4069                         return ret;
4070
4071                 ret = skl_ddb_add_affected_planes(cstate);
4072                 if (ret)
4073                         return ret;
4074         }
4075
4076         return 0;
4077 }
4078
4079 static void
4080 skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4081                      struct skl_wm_values *src,
4082                      enum pipe pipe)
4083 {
4084         memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4085                sizeof(dst->ddb.y_plane[pipe]));
4086         memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4087                sizeof(dst->ddb.plane[pipe]));
4088 }
4089
4090 static void
4091 skl_print_wm_changes(const struct drm_atomic_state *state)
4092 {
4093         const struct drm_device *dev = state->dev;
4094         const struct drm_i915_private *dev_priv = to_i915(dev);
4095         const struct intel_atomic_state *intel_state =
4096                 to_intel_atomic_state(state);
4097         const struct drm_crtc *crtc;
4098         const struct drm_crtc_state *cstate;
4099         const struct drm_plane *plane;
4100         const struct intel_plane *intel_plane;
4101         const struct drm_plane_state *pstate;
4102         const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
4103         const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
4104         enum pipe pipe;
4105         int id;
4106         int i, j;
4107
4108         for_each_crtc_in_state(state, crtc, cstate, i) {
4109                 pipe = to_intel_crtc(crtc)->pipe;
4110
4111                 for_each_plane_in_state(state, plane, pstate, j) {
4112                         const struct skl_ddb_entry *old, *new;
4113
4114                         intel_plane = to_intel_plane(plane);
4115                         id = skl_wm_plane_id(intel_plane);
4116                         old = &old_ddb->plane[pipe][id];
4117                         new = &new_ddb->plane[pipe][id];
4118
4119                         if (intel_plane->pipe != pipe)
4120                                 continue;
4121
4122                         if (skl_ddb_entry_equal(old, new))
4123                                 continue;
4124
4125                         if (id != PLANE_CURSOR) {
4126                                 DRM_DEBUG_ATOMIC("[PLANE:%d:plane %d%c] ddb (%d - %d) -> (%d - %d)\n",
4127                                                  plane->base.id, id + 1,
4128                                                  pipe_name(pipe),
4129                                                  old->start, old->end,
4130                                                  new->start, new->end);
4131                         } else {
4132                                 DRM_DEBUG_ATOMIC("[PLANE:%d:cursor %c] ddb (%d - %d) -> (%d - %d)\n",
4133                                                  plane->base.id,
4134                                                  pipe_name(pipe),
4135                                                  old->start, old->end,
4136                                                  new->start, new->end);
4137                         }
4138                 }
4139         }
4140 }
4141
4142 static int
4143 skl_compute_wm(struct drm_atomic_state *state)
4144 {
4145         struct drm_crtc *crtc;
4146         struct drm_crtc_state *cstate;
4147         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4148         struct skl_wm_values *results = &intel_state->wm_results;
4149         struct skl_pipe_wm *pipe_wm;
4150         bool changed = false;
4151         int ret, i;
4152
4153         /*
4154          * If this transaction isn't actually touching any CRTC's, don't
4155          * bother with watermark calculation.  Note that if we pass this
4156          * test, we're guaranteed to hold at least one CRTC state mutex,
4157          * which means we can safely use values like dev_priv->active_crtcs
4158          * since any racing commits that want to update them would need to
4159          * hold _all_ CRTC state mutexes.
4160          */
4161         for_each_crtc_in_state(state, crtc, cstate, i)
4162                 changed = true;
4163         if (!changed)
4164                 return 0;
4165
4166         /* Clear all dirty flags */
4167         results->dirty_pipes = 0;
4168
4169         ret = skl_compute_ddb(state);
4170         if (ret)
4171                 return ret;
4172
4173         /*
4174          * Calculate WM's for all pipes that are part of this transaction.
4175          * Note that the DDB allocation above may have added more CRTC's that
4176          * weren't otherwise being modified (and set bits in dirty_pipes) if
4177          * pipe allocations had to change.
4178          *
4179          * FIXME:  Now that we're doing this in the atomic check phase, we
4180          * should allow skl_update_pipe_wm() to return failure in cases where
4181          * no suitable watermark values can be found.
4182          */
4183         for_each_crtc_in_state(state, crtc, cstate, i) {
4184                 struct intel_crtc_state *intel_cstate =
4185                         to_intel_crtc_state(cstate);
4186
4187                 pipe_wm = &intel_cstate->wm.skl.optimal;
4188                 ret = skl_update_pipe_wm(cstate, &results->ddb, pipe_wm,
4189                                          &changed);
4190                 if (ret)
4191                         return ret;
4192
4193                 if (changed)
4194                         results->dirty_pipes |= drm_crtc_mask(crtc);
4195
4196                 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4197                         /* This pipe's WM's did not change */
4198                         continue;
4199
4200                 intel_cstate->update_wm_pre = true;
4201         }
4202
4203         skl_print_wm_changes(state);
4204
4205         return 0;
4206 }
4207
4208 static void skl_update_wm(struct drm_crtc *crtc)
4209 {
4210         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4211         struct drm_device *dev = crtc->dev;
4212         struct drm_i915_private *dev_priv = to_i915(dev);
4213         struct skl_wm_values *results = &dev_priv->wm.skl_results;
4214         struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
4215         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4216         struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
4217         enum pipe pipe = intel_crtc->pipe;
4218
4219         if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4220                 return;
4221
4222         intel_crtc->wm.active.skl = *pipe_wm;
4223
4224         mutex_lock(&dev_priv->wm.wm_mutex);
4225
4226         /*
4227          * If this pipe isn't active already, we're going to be enabling it
4228          * very soon. Since it's safe to update a pipe's ddb allocation while
4229          * the pipe's shut off, just do so here. Already active pipes will have
4230          * their watermarks updated once we update their planes.
4231          */
4232         if (crtc->state->active_changed) {
4233                 int plane;
4234
4235                 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++)
4236                         skl_write_plane_wm(intel_crtc, &pipe_wm->planes[plane],
4237                                            &results->ddb, plane);
4238
4239                 skl_write_cursor_wm(intel_crtc, &pipe_wm->planes[PLANE_CURSOR],
4240                                     &results->ddb);
4241         }
4242
4243         skl_copy_wm_for_pipe(hw_vals, results, pipe);
4244
4245         intel_crtc->hw_ddb = cstate->wm.skl.ddb;
4246
4247         mutex_unlock(&dev_priv->wm.wm_mutex);
4248 }
4249
4250 static void ilk_compute_wm_config(struct drm_device *dev,
4251                                   struct intel_wm_config *config)
4252 {
4253         struct intel_crtc *crtc;
4254
4255         /* Compute the currently _active_ config */
4256         for_each_intel_crtc(dev, crtc) {
4257                 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4258
4259                 if (!wm->pipe_enabled)
4260                         continue;
4261
4262                 config->sprites_enabled |= wm->sprites_enabled;
4263                 config->sprites_scaled |= wm->sprites_scaled;
4264                 config->num_pipes_active++;
4265         }
4266 }
4267
4268 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
4269 {
4270         struct drm_device *dev = &dev_priv->drm;
4271         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
4272         struct ilk_wm_maximums max;
4273         struct intel_wm_config config = {};
4274         struct ilk_wm_values results = {};
4275         enum intel_ddb_partitioning partitioning;
4276
4277         ilk_compute_wm_config(dev, &config);
4278
4279         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4280         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
4281
4282         /* 5/6 split only in single pipe config on IVB+ */
4283         if (INTEL_INFO(dev)->gen >= 7 &&
4284             config.num_pipes_active == 1 && config.sprites_enabled) {
4285                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4286                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
4287
4288                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
4289         } else {
4290                 best_lp_wm = &lp_wm_1_2;
4291         }
4292
4293         partitioning = (best_lp_wm == &lp_wm_1_2) ?
4294                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
4295
4296         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
4297
4298         ilk_write_wm_values(dev_priv, &results);
4299 }
4300
4301 static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
4302 {
4303         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4304         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4305
4306         mutex_lock(&dev_priv->wm.wm_mutex);
4307         intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
4308         ilk_program_watermarks(dev_priv);
4309         mutex_unlock(&dev_priv->wm.wm_mutex);
4310 }
4311
4312 static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
4313 {
4314         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4315         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4316
4317         mutex_lock(&dev_priv->wm.wm_mutex);
4318         if (cstate->wm.need_postvbl_update) {
4319                 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
4320                 ilk_program_watermarks(dev_priv);
4321         }
4322         mutex_unlock(&dev_priv->wm.wm_mutex);
4323 }
4324
4325 static inline void skl_wm_level_from_reg_val(uint32_t val,
4326                                              struct skl_wm_level *level)
4327 {
4328         level->plane_en = val & PLANE_WM_EN;
4329         level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
4330         level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
4331                 PLANE_WM_LINES_MASK;
4332 }
4333
4334 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
4335                               struct skl_pipe_wm *out)
4336 {
4337         struct drm_device *dev = crtc->dev;
4338         struct drm_i915_private *dev_priv = to_i915(dev);
4339         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4340         struct intel_plane *intel_plane;
4341         struct skl_plane_wm *wm;
4342         enum pipe pipe = intel_crtc->pipe;
4343         int level, id, max_level;
4344         uint32_t val;
4345
4346         max_level = ilk_wm_max_level(dev_priv);
4347
4348         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
4349                 id = skl_wm_plane_id(intel_plane);
4350                 wm = &out->planes[id];
4351
4352                 for (level = 0; level <= max_level; level++) {
4353                         if (id != PLANE_CURSOR)
4354                                 val = I915_READ(PLANE_WM(pipe, id, level));
4355                         else
4356                                 val = I915_READ(CUR_WM(pipe, level));
4357
4358                         skl_wm_level_from_reg_val(val, &wm->wm[level]);
4359                 }
4360
4361                 if (id != PLANE_CURSOR)
4362                         val = I915_READ(PLANE_WM_TRANS(pipe, id));
4363                 else
4364                         val = I915_READ(CUR_WM_TRANS(pipe));
4365
4366                 skl_wm_level_from_reg_val(val, &wm->trans_wm);
4367         }
4368
4369         if (!intel_crtc->active)
4370                 return;
4371
4372         out->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
4373 }
4374
4375 void skl_wm_get_hw_state(struct drm_device *dev)
4376 {
4377         struct drm_i915_private *dev_priv = to_i915(dev);
4378         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
4379         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
4380         struct drm_crtc *crtc;
4381         struct intel_crtc *intel_crtc;
4382         struct intel_crtc_state *cstate;
4383
4384         skl_ddb_get_hw_state(dev_priv, ddb);
4385         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4386                 intel_crtc = to_intel_crtc(crtc);
4387                 cstate = to_intel_crtc_state(crtc->state);
4388
4389                 skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal);
4390
4391                 if (intel_crtc->active) {
4392                         hw->dirty_pipes |= drm_crtc_mask(crtc);
4393                         intel_crtc->wm.active.skl = cstate->wm.skl.optimal;
4394                 }
4395         }
4396
4397         if (dev_priv->active_crtcs) {
4398                 /* Fully recompute DDB on first atomic commit */
4399                 dev_priv->wm.distrust_bios_wm = true;
4400         } else {
4401                 /* Easy/common case; just sanitize DDB now if everything off */
4402                 memset(ddb, 0, sizeof(*ddb));
4403         }
4404 }
4405
4406 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4407 {
4408         struct drm_device *dev = crtc->dev;
4409         struct drm_i915_private *dev_priv = to_i915(dev);
4410         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4411         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4412         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4413         struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
4414         enum pipe pipe = intel_crtc->pipe;
4415         static const i915_reg_t wm0_pipe_reg[] = {
4416                 [PIPE_A] = WM0_PIPEA_ILK,
4417                 [PIPE_B] = WM0_PIPEB_ILK,
4418                 [PIPE_C] = WM0_PIPEC_IVB,
4419         };
4420
4421         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
4422         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4423                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4424
4425         memset(active, 0, sizeof(*active));
4426
4427         active->pipe_enabled = intel_crtc->active;
4428
4429         if (active->pipe_enabled) {
4430                 u32 tmp = hw->wm_pipe[pipe];
4431
4432                 /*
4433                  * For active pipes LP0 watermark is marked as
4434                  * enabled, and LP1+ watermaks as disabled since
4435                  * we can't really reverse compute them in case
4436                  * multiple pipes are active.
4437                  */
4438                 active->wm[0].enable = true;
4439                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4440                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4441                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4442                 active->linetime = hw->wm_linetime[pipe];
4443         } else {
4444                 int level, max_level = ilk_wm_max_level(dev_priv);
4445
4446                 /*
4447                  * For inactive pipes, all watermark levels
4448                  * should be marked as enabled but zeroed,
4449                  * which is what we'd compute them to.
4450                  */
4451                 for (level = 0; level <= max_level; level++)
4452                         active->wm[level].enable = true;
4453         }
4454
4455         intel_crtc->wm.active.ilk = *active;
4456 }
4457
4458 #define _FW_WM(value, plane) \
4459         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4460 #define _FW_WM_VLV(value, plane) \
4461         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4462
4463 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4464                                struct vlv_wm_values *wm)
4465 {
4466         enum pipe pipe;
4467         uint32_t tmp;
4468
4469         for_each_pipe(dev_priv, pipe) {
4470                 tmp = I915_READ(VLV_DDL(pipe));
4471
4472                 wm->ddl[pipe].primary =
4473                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4474                 wm->ddl[pipe].cursor =
4475                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4476                 wm->ddl[pipe].sprite[0] =
4477                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4478                 wm->ddl[pipe].sprite[1] =
4479                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4480         }
4481
4482         tmp = I915_READ(DSPFW1);
4483         wm->sr.plane = _FW_WM(tmp, SR);
4484         wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4485         wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4486         wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4487
4488         tmp = I915_READ(DSPFW2);
4489         wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4490         wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4491         wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4492
4493         tmp = I915_READ(DSPFW3);
4494         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4495
4496         if (IS_CHERRYVIEW(dev_priv)) {
4497                 tmp = I915_READ(DSPFW7_CHV);
4498                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4499                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4500
4501                 tmp = I915_READ(DSPFW8_CHV);
4502                 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4503                 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4504
4505                 tmp = I915_READ(DSPFW9_CHV);
4506                 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4507                 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4508
4509                 tmp = I915_READ(DSPHOWM);
4510                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4511                 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4512                 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4513                 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4514                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4515                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4516                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4517                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4518                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4519                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4520         } else {
4521                 tmp = I915_READ(DSPFW7);
4522                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4523                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4524
4525                 tmp = I915_READ(DSPHOWM);
4526                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4527                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4528                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4529                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4530                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4531                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4532                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4533         }
4534 }
4535
4536 #undef _FW_WM
4537 #undef _FW_WM_VLV
4538
4539 void vlv_wm_get_hw_state(struct drm_device *dev)
4540 {
4541         struct drm_i915_private *dev_priv = to_i915(dev);
4542         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4543         struct intel_plane *plane;
4544         enum pipe pipe;
4545         u32 val;
4546
4547         vlv_read_wm_values(dev_priv, wm);
4548
4549         for_each_intel_plane(dev, plane) {
4550                 switch (plane->base.type) {
4551                         int sprite;
4552                 case DRM_PLANE_TYPE_CURSOR:
4553                         plane->wm.fifo_size = 63;
4554                         break;
4555                 case DRM_PLANE_TYPE_PRIMARY:
4556                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4557                         break;
4558                 case DRM_PLANE_TYPE_OVERLAY:
4559                         sprite = plane->plane;
4560                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4561                         break;
4562                 }
4563         }
4564
4565         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4566         wm->level = VLV_WM_LEVEL_PM2;
4567
4568         if (IS_CHERRYVIEW(dev_priv)) {
4569                 mutex_lock(&dev_priv->rps.hw_lock);
4570
4571                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4572                 if (val & DSP_MAXFIFO_PM5_ENABLE)
4573                         wm->level = VLV_WM_LEVEL_PM5;
4574
4575                 /*
4576                  * If DDR DVFS is disabled in the BIOS, Punit
4577                  * will never ack the request. So if that happens
4578                  * assume we don't have to enable/disable DDR DVFS
4579                  * dynamically. To test that just set the REQ_ACK
4580                  * bit to poke the Punit, but don't change the
4581                  * HIGH/LOW bits so that we don't actually change
4582                  * the current state.
4583                  */
4584                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4585                 val |= FORCE_DDR_FREQ_REQ_ACK;
4586                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4587
4588                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4589                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4590                         DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4591                                       "assuming DDR DVFS is disabled\n");
4592                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4593                 } else {
4594                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4595                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4596                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4597                 }
4598
4599                 mutex_unlock(&dev_priv->rps.hw_lock);
4600         }
4601
4602         for_each_pipe(dev_priv, pipe)
4603                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4604                               pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4605                               wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4606
4607         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4608                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4609 }
4610
4611 void ilk_wm_get_hw_state(struct drm_device *dev)
4612 {
4613         struct drm_i915_private *dev_priv = to_i915(dev);
4614         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4615         struct drm_crtc *crtc;
4616
4617         for_each_crtc(dev, crtc)
4618                 ilk_pipe_wm_get_hw_state(crtc);
4619
4620         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4621         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4622         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4623
4624         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4625         if (INTEL_INFO(dev)->gen >= 7) {
4626                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4627                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4628         }
4629
4630         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4631                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4632                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4633         else if (IS_IVYBRIDGE(dev_priv))
4634                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4635                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4636
4637         hw->enable_fbc_wm =
4638                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4639 }
4640
4641 /**
4642  * intel_update_watermarks - update FIFO watermark values based on current modes
4643  *
4644  * Calculate watermark values for the various WM regs based on current mode
4645  * and plane configuration.
4646  *
4647  * There are several cases to deal with here:
4648  *   - normal (i.e. non-self-refresh)
4649  *   - self-refresh (SR) mode
4650  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4651  *   - lines are small relative to FIFO size (buffer can hold more than 2
4652  *     lines), so need to account for TLB latency
4653  *
4654  *   The normal calculation is:
4655  *     watermark = dotclock * bytes per pixel * latency
4656  *   where latency is platform & configuration dependent (we assume pessimal
4657  *   values here).
4658  *
4659  *   The SR calculation is:
4660  *     watermark = (trunc(latency/line time)+1) * surface width *
4661  *       bytes per pixel
4662  *   where
4663  *     line time = htotal / dotclock
4664  *     surface width = hdisplay for normal plane and 64 for cursor
4665  *   and latency is assumed to be high, as above.
4666  *
4667  * The final value programmed to the register should always be rounded up,
4668  * and include an extra 2 entries to account for clock crossings.
4669  *
4670  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4671  * to set the non-SR watermarks to 8.
4672  */
4673 void intel_update_watermarks(struct drm_crtc *crtc)
4674 {
4675         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4676
4677         if (dev_priv->display.update_wm)
4678                 dev_priv->display.update_wm(crtc);
4679 }
4680
4681 /*
4682  * Lock protecting IPS related data structures
4683  */
4684 DEFINE_SPINLOCK(mchdev_lock);
4685
4686 /* Global for IPS driver to get at the current i915 device. Protected by
4687  * mchdev_lock. */
4688 static struct drm_i915_private *i915_mch_dev;
4689
4690 bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
4691 {
4692         u16 rgvswctl;
4693
4694         assert_spin_locked(&mchdev_lock);
4695
4696         rgvswctl = I915_READ16(MEMSWCTL);
4697         if (rgvswctl & MEMCTL_CMD_STS) {
4698                 DRM_DEBUG("gpu busy, RCS change rejected\n");
4699                 return false; /* still busy with another command */
4700         }
4701
4702         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4703                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4704         I915_WRITE16(MEMSWCTL, rgvswctl);
4705         POSTING_READ16(MEMSWCTL);
4706
4707         rgvswctl |= MEMCTL_CMD_STS;
4708         I915_WRITE16(MEMSWCTL, rgvswctl);
4709
4710         return true;
4711 }
4712
4713 static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
4714 {
4715         u32 rgvmodectl;
4716         u8 fmax, fmin, fstart, vstart;
4717
4718         spin_lock_irq(&mchdev_lock);
4719
4720         rgvmodectl = I915_READ(MEMMODECTL);
4721
4722         /* Enable temp reporting */
4723         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4724         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4725
4726         /* 100ms RC evaluation intervals */
4727         I915_WRITE(RCUPEI, 100000);
4728         I915_WRITE(RCDNEI, 100000);
4729
4730         /* Set max/min thresholds to 90ms and 80ms respectively */
4731         I915_WRITE(RCBMAXAVG, 90000);
4732         I915_WRITE(RCBMINAVG, 80000);
4733
4734         I915_WRITE(MEMIHYST, 1);
4735
4736         /* Set up min, max, and cur for interrupt handling */
4737         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4738         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4739         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4740                 MEMMODE_FSTART_SHIFT;
4741
4742         vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4743                 PXVFREQ_PX_SHIFT;
4744
4745         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4746         dev_priv->ips.fstart = fstart;
4747
4748         dev_priv->ips.max_delay = fstart;
4749         dev_priv->ips.min_delay = fmin;
4750         dev_priv->ips.cur_delay = fstart;
4751
4752         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4753                          fmax, fmin, fstart);
4754
4755         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4756
4757         /*
4758          * Interrupts will be enabled in ironlake_irq_postinstall
4759          */
4760
4761         I915_WRITE(VIDSTART, vstart);
4762         POSTING_READ(VIDSTART);
4763
4764         rgvmodectl |= MEMMODE_SWMODE_EN;
4765         I915_WRITE(MEMMODECTL, rgvmodectl);
4766
4767         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4768                 DRM_ERROR("stuck trying to change perf mode\n");
4769         mdelay(1);
4770
4771         ironlake_set_drps(dev_priv, fstart);
4772
4773         dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4774                 I915_READ(DDREC) + I915_READ(CSIEC);
4775         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4776         dev_priv->ips.last_count2 = I915_READ(GFXEC);
4777         dev_priv->ips.last_time2 = ktime_get_raw_ns();
4778
4779         spin_unlock_irq(&mchdev_lock);
4780 }
4781
4782 static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
4783 {
4784         u16 rgvswctl;
4785
4786         spin_lock_irq(&mchdev_lock);
4787
4788         rgvswctl = I915_READ16(MEMSWCTL);
4789
4790         /* Ack interrupts, disable EFC interrupt */
4791         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4792         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4793         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4794         I915_WRITE(DEIIR, DE_PCU_EVENT);
4795         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4796
4797         /* Go back to the starting frequency */
4798         ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
4799         mdelay(1);
4800         rgvswctl |= MEMCTL_CMD_STS;
4801         I915_WRITE(MEMSWCTL, rgvswctl);
4802         mdelay(1);
4803
4804         spin_unlock_irq(&mchdev_lock);
4805 }
4806
4807 /* There's a funny hw issue where the hw returns all 0 when reading from
4808  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4809  * ourselves, instead of doing a rmw cycle (which might result in us clearing
4810  * all limits and the gpu stuck at whatever frequency it is at atm).
4811  */
4812 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4813 {
4814         u32 limits;
4815
4816         /* Only set the down limit when we've reached the lowest level to avoid
4817          * getting more interrupts, otherwise leave this clear. This prevents a
4818          * race in the hw when coming out of rc6: There's a tiny window where
4819          * the hw runs at the minimal clock before selecting the desired
4820          * frequency, if the down threshold expires in that window we will not
4821          * receive a down interrupt. */
4822         if (IS_GEN9(dev_priv)) {
4823                 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4824                 if (val <= dev_priv->rps.min_freq_softlimit)
4825                         limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4826         } else {
4827                 limits = dev_priv->rps.max_freq_softlimit << 24;
4828                 if (val <= dev_priv->rps.min_freq_softlimit)
4829                         limits |= dev_priv->rps.min_freq_softlimit << 16;
4830         }
4831
4832         return limits;
4833 }
4834
4835 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4836 {
4837         int new_power;
4838         u32 threshold_up = 0, threshold_down = 0; /* in % */
4839         u32 ei_up = 0, ei_down = 0;
4840
4841         new_power = dev_priv->rps.power;
4842         switch (dev_priv->rps.power) {
4843         case LOW_POWER:
4844                 if (val > dev_priv->rps.efficient_freq + 1 &&
4845                     val > dev_priv->rps.cur_freq)
4846                         new_power = BETWEEN;
4847                 break;
4848
4849         case BETWEEN:
4850                 if (val <= dev_priv->rps.efficient_freq &&
4851                     val < dev_priv->rps.cur_freq)
4852                         new_power = LOW_POWER;
4853                 else if (val >= dev_priv->rps.rp0_freq &&
4854                          val > dev_priv->rps.cur_freq)
4855                         new_power = HIGH_POWER;
4856                 break;
4857
4858         case HIGH_POWER:
4859                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4860                     val < dev_priv->rps.cur_freq)
4861                         new_power = BETWEEN;
4862                 break;
4863         }
4864         /* Max/min bins are special */
4865         if (val <= dev_priv->rps.min_freq_softlimit)
4866                 new_power = LOW_POWER;
4867         if (val >= dev_priv->rps.max_freq_softlimit)
4868                 new_power = HIGH_POWER;
4869         if (new_power == dev_priv->rps.power)
4870                 return;
4871
4872         /* Note the units here are not exactly 1us, but 1280ns. */
4873         switch (new_power) {
4874         case LOW_POWER:
4875                 /* Upclock if more than 95% busy over 16ms */
4876                 ei_up = 16000;
4877                 threshold_up = 95;
4878
4879                 /* Downclock if less than 85% busy over 32ms */
4880                 ei_down = 32000;
4881                 threshold_down = 85;
4882                 break;
4883
4884         case BETWEEN:
4885                 /* Upclock if more than 90% busy over 13ms */
4886                 ei_up = 13000;
4887                 threshold_up = 90;
4888
4889                 /* Downclock if less than 75% busy over 32ms */
4890                 ei_down = 32000;
4891                 threshold_down = 75;
4892                 break;
4893
4894         case HIGH_POWER:
4895                 /* Upclock if more than 85% busy over 10ms */
4896                 ei_up = 10000;
4897                 threshold_up = 85;
4898
4899                 /* Downclock if less than 60% busy over 32ms */
4900                 ei_down = 32000;
4901                 threshold_down = 60;
4902                 break;
4903         }
4904
4905         I915_WRITE(GEN6_RP_UP_EI,
4906                    GT_INTERVAL_FROM_US(dev_priv, ei_up));
4907         I915_WRITE(GEN6_RP_UP_THRESHOLD,
4908                    GT_INTERVAL_FROM_US(dev_priv,
4909                                        ei_up * threshold_up / 100));
4910
4911         I915_WRITE(GEN6_RP_DOWN_EI,
4912                    GT_INTERVAL_FROM_US(dev_priv, ei_down));
4913         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4914                    GT_INTERVAL_FROM_US(dev_priv,
4915                                        ei_down * threshold_down / 100));
4916
4917         I915_WRITE(GEN6_RP_CONTROL,
4918                    GEN6_RP_MEDIA_TURBO |
4919                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4920                    GEN6_RP_MEDIA_IS_GFX |
4921                    GEN6_RP_ENABLE |
4922                    GEN6_RP_UP_BUSY_AVG |
4923                    GEN6_RP_DOWN_IDLE_AVG);
4924
4925         dev_priv->rps.power = new_power;
4926         dev_priv->rps.up_threshold = threshold_up;
4927         dev_priv->rps.down_threshold = threshold_down;
4928         dev_priv->rps.last_adj = 0;
4929 }
4930
4931 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4932 {
4933         u32 mask = 0;
4934
4935         if (val > dev_priv->rps.min_freq_softlimit)
4936                 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4937         if (val < dev_priv->rps.max_freq_softlimit)
4938                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4939
4940         mask &= dev_priv->pm_rps_events;
4941
4942         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4943 }
4944
4945 /* gen6_set_rps is called to update the frequency request, but should also be
4946  * called when the range (min_delay and max_delay) is modified so that we can
4947  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4948 static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
4949 {
4950         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4951         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
4952                 return;
4953
4954         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4955         WARN_ON(val > dev_priv->rps.max_freq);
4956         WARN_ON(val < dev_priv->rps.min_freq);
4957
4958         /* min/max delay may still have been modified so be sure to
4959          * write the limits value.
4960          */
4961         if (val != dev_priv->rps.cur_freq) {
4962                 gen6_set_rps_thresholds(dev_priv, val);
4963
4964                 if (IS_GEN9(dev_priv))
4965                         I915_WRITE(GEN6_RPNSWREQ,
4966                                    GEN9_FREQUENCY(val));
4967                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4968                         I915_WRITE(GEN6_RPNSWREQ,
4969                                    HSW_FREQUENCY(val));
4970                 else
4971                         I915_WRITE(GEN6_RPNSWREQ,
4972                                    GEN6_FREQUENCY(val) |
4973                                    GEN6_OFFSET(0) |
4974                                    GEN6_AGGRESSIVE_TURBO);
4975         }
4976
4977         /* Make sure we continue to get interrupts
4978          * until we hit the minimum or maximum frequencies.
4979          */
4980         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4981         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4982
4983         POSTING_READ(GEN6_RPNSWREQ);
4984
4985         dev_priv->rps.cur_freq = val;
4986         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4987 }
4988
4989 static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
4990 {
4991         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4992         WARN_ON(val > dev_priv->rps.max_freq);
4993         WARN_ON(val < dev_priv->rps.min_freq);
4994
4995         if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
4996                       "Odd GPU freq value\n"))
4997                 val &= ~1;
4998
4999         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
5000
5001         if (val != dev_priv->rps.cur_freq) {
5002                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
5003                 if (!IS_CHERRYVIEW(dev_priv))
5004                         gen6_set_rps_thresholds(dev_priv, val);
5005         }
5006
5007         dev_priv->rps.cur_freq = val;
5008         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
5009 }
5010
5011 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
5012  *
5013  * * If Gfx is Idle, then
5014  * 1. Forcewake Media well.
5015  * 2. Request idle freq.
5016  * 3. Release Forcewake of Media well.
5017 */
5018 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
5019 {
5020         u32 val = dev_priv->rps.idle_freq;
5021
5022         if (dev_priv->rps.cur_freq <= val)
5023                 return;
5024
5025         /* Wake up the media well, as that takes a lot less
5026          * power than the Render well. */
5027         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
5028         valleyview_set_rps(dev_priv, val);
5029         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
5030 }
5031
5032 void gen6_rps_busy(struct drm_i915_private *dev_priv)
5033 {
5034         mutex_lock(&dev_priv->rps.hw_lock);
5035         if (dev_priv->rps.enabled) {
5036                 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
5037                         gen6_rps_reset_ei(dev_priv);
5038                 I915_WRITE(GEN6_PMINTRMSK,
5039                            gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
5040
5041                 gen6_enable_rps_interrupts(dev_priv);
5042
5043                 /* Ensure we start at the user's desired frequency */
5044                 intel_set_rps(dev_priv,
5045                               clamp(dev_priv->rps.cur_freq,
5046                                     dev_priv->rps.min_freq_softlimit,
5047                                     dev_priv->rps.max_freq_softlimit));
5048         }
5049         mutex_unlock(&dev_priv->rps.hw_lock);
5050 }
5051
5052 void gen6_rps_idle(struct drm_i915_private *dev_priv)
5053 {
5054         /* Flush our bottom-half so that it does not race with us
5055          * setting the idle frequency and so that it is bounded by
5056          * our rpm wakeref. And then disable the interrupts to stop any
5057          * futher RPS reclocking whilst we are asleep.
5058          */
5059         gen6_disable_rps_interrupts(dev_priv);
5060
5061         mutex_lock(&dev_priv->rps.hw_lock);
5062         if (dev_priv->rps.enabled) {
5063                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5064                         vlv_set_rps_idle(dev_priv);
5065                 else
5066                         gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
5067                 dev_priv->rps.last_adj = 0;
5068                 I915_WRITE(GEN6_PMINTRMSK,
5069                            gen6_sanitize_rps_pm_mask(dev_priv, ~0));
5070         }
5071         mutex_unlock(&dev_priv->rps.hw_lock);
5072
5073         spin_lock(&dev_priv->rps.client_lock);
5074         while (!list_empty(&dev_priv->rps.clients))
5075                 list_del_init(dev_priv->rps.clients.next);
5076         spin_unlock(&dev_priv->rps.client_lock);
5077 }
5078
5079 void gen6_rps_boost(struct drm_i915_private *dev_priv,
5080                     struct intel_rps_client *rps,
5081                     unsigned long submitted)
5082 {
5083         /* This is intentionally racy! We peek at the state here, then
5084          * validate inside the RPS worker.
5085          */
5086         if (!(dev_priv->gt.awake &&
5087               dev_priv->rps.enabled &&
5088               dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
5089                 return;
5090
5091         /* Force a RPS boost (and don't count it against the client) if
5092          * the GPU is severely congested.
5093          */
5094         if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
5095                 rps = NULL;
5096
5097         spin_lock(&dev_priv->rps.client_lock);
5098         if (rps == NULL || list_empty(&rps->link)) {
5099                 spin_lock_irq(&dev_priv->irq_lock);
5100                 if (dev_priv->rps.interrupts_enabled) {
5101                         dev_priv->rps.client_boost = true;
5102                         schedule_work(&dev_priv->rps.work);
5103                 }
5104                 spin_unlock_irq(&dev_priv->irq_lock);
5105
5106                 if (rps != NULL) {
5107                         list_add(&rps->link, &dev_priv->rps.clients);
5108                         rps->boosts++;
5109                 } else
5110                         dev_priv->rps.boosts++;
5111         }
5112         spin_unlock(&dev_priv->rps.client_lock);
5113 }
5114
5115 void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
5116 {
5117         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5118                 valleyview_set_rps(dev_priv, val);
5119         else
5120                 gen6_set_rps(dev_priv, val);
5121 }
5122
5123 static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
5124 {
5125         I915_WRITE(GEN6_RC_CONTROL, 0);
5126         I915_WRITE(GEN9_PG_ENABLE, 0);
5127 }
5128
5129 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
5130 {
5131         I915_WRITE(GEN6_RP_CONTROL, 0);
5132 }
5133
5134 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
5135 {
5136         I915_WRITE(GEN6_RC_CONTROL, 0);
5137         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
5138         I915_WRITE(GEN6_RP_CONTROL, 0);
5139 }
5140
5141 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
5142 {
5143         I915_WRITE(GEN6_RC_CONTROL, 0);
5144 }
5145
5146 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
5147 {
5148         /* we're doing forcewake before Disabling RC6,
5149          * This what the BIOS expects when going into suspend */
5150         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5151
5152         I915_WRITE(GEN6_RC_CONTROL, 0);
5153
5154         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5155 }
5156
5157 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
5158 {
5159         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5160                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5161                         mode = GEN6_RC_CTL_RC6_ENABLE;
5162                 else
5163                         mode = 0;
5164         }
5165         if (HAS_RC6p(dev_priv))
5166                 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5167                                  "RC6 %s RC6p %s RC6pp %s\n",
5168                                  onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5169                                  onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5170                                  onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
5171
5172         else
5173                 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5174                                  onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
5175 }
5176
5177 static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
5178 {
5179         struct i915_ggtt *ggtt = &dev_priv->ggtt;
5180         bool enable_rc6 = true;
5181         unsigned long rc6_ctx_base;
5182         u32 rc_ctl;
5183         int rc_sw_target;
5184
5185         rc_ctl = I915_READ(GEN6_RC_CONTROL);
5186         rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5187                        RC_SW_TARGET_STATE_SHIFT;
5188         DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5189                          "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5190                          onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5191                          onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5192                          rc_sw_target);
5193
5194         if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
5195                 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
5196                 enable_rc6 = false;
5197         }
5198
5199         /*
5200          * The exact context size is not known for BXT, so assume a page size
5201          * for this check.
5202          */
5203         rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
5204         if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5205               (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5206                                         ggtt->stolen_reserved_size))) {
5207                 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
5208                 enable_rc6 = false;
5209         }
5210
5211         if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5212               ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5213               ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5214               ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
5215                 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
5216                 enable_rc6 = false;
5217         }
5218
5219         if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5220             !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5221             !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5222                 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5223                 enable_rc6 = false;
5224         }
5225
5226         if (!I915_READ(GEN6_GFXPAUSE)) {
5227                 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5228                 enable_rc6 = false;
5229         }
5230
5231         if (!I915_READ(GEN8_MISC_CTRL0)) {
5232                 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
5233                 enable_rc6 = false;
5234         }
5235
5236         return enable_rc6;
5237 }
5238
5239 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
5240 {
5241         /* No RC6 before Ironlake and code is gone for ilk. */
5242         if (INTEL_INFO(dev_priv)->gen < 6)
5243                 return 0;
5244
5245         if (!enable_rc6)
5246                 return 0;
5247
5248         if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
5249                 DRM_INFO("RC6 disabled by BIOS\n");
5250                 return 0;
5251         }
5252
5253         /* Respect the kernel parameter if it is set */
5254         if (enable_rc6 >= 0) {
5255                 int mask;
5256
5257                 if (HAS_RC6p(dev_priv))
5258                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5259                                INTEL_RC6pp_ENABLE;
5260                 else
5261                         mask = INTEL_RC6_ENABLE;
5262
5263                 if ((enable_rc6 & mask) != enable_rc6)
5264                         DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5265                                          "(requested %d, valid %d)\n",
5266                                          enable_rc6 & mask, enable_rc6, mask);
5267
5268                 return enable_rc6 & mask;
5269         }
5270
5271         if (IS_IVYBRIDGE(dev_priv))
5272                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
5273
5274         return INTEL_RC6_ENABLE;
5275 }
5276
5277 static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
5278 {
5279         /* All of these values are in units of 50MHz */
5280
5281         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
5282         if (IS_BROXTON(dev_priv)) {
5283                 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
5284                 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5285                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
5286                 dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
5287         } else {
5288                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
5289                 dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
5290                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
5291                 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5292         }
5293         /* hw_max = RP0 until we check for overclocking */
5294         dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
5295
5296         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
5297         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5298             IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5299                 u32 ddcc_status = 0;
5300
5301                 if (sandybridge_pcode_read(dev_priv,
5302                                            HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5303                                            &ddcc_status) == 0)
5304                         dev_priv->rps.efficient_freq =
5305                                 clamp_t(u8,
5306                                         ((ddcc_status >> 8) & 0xff),
5307                                         dev_priv->rps.min_freq,
5308                                         dev_priv->rps.max_freq);
5309         }
5310
5311         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5312                 /* Store the frequency values in 16.66 MHZ units, which is
5313                  * the natural hardware unit for SKL
5314                  */
5315                 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5316                 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5317                 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5318                 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5319                 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5320         }
5321 }
5322
5323 static void reset_rps(struct drm_i915_private *dev_priv,
5324                       void (*set)(struct drm_i915_private *, u8))
5325 {
5326         u8 freq = dev_priv->rps.cur_freq;
5327
5328         /* force a reset */
5329         dev_priv->rps.power = -1;
5330         dev_priv->rps.cur_freq = -1;
5331
5332         set(dev_priv, freq);
5333 }
5334
5335 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
5336 static void gen9_enable_rps(struct drm_i915_private *dev_priv)
5337 {
5338         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5339
5340         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
5341         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5342                 /*
5343                  * BIOS could leave the Hw Turbo enabled, so need to explicitly
5344                  * clear out the Control register just to avoid inconsitency
5345                  * with debugfs interface, which will show  Turbo as enabled
5346                  * only and that is not expected by the User after adding the
5347                  * WaGsvDisableTurbo. Apart from this there is no problem even
5348                  * if the Turbo is left enabled in the Control register, as the
5349                  * Up/Down interrupts would remain masked.
5350                  */
5351                 gen9_disable_rps(dev_priv);
5352                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5353                 return;
5354         }
5355
5356         /* Program defaults and thresholds for RPS*/
5357         I915_WRITE(GEN6_RC_VIDEO_FREQ,
5358                 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5359
5360         /* 1 second timeout*/
5361         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5362                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5363
5364         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
5365
5366         /* Leaning on the below call to gen6_set_rps to program/setup the
5367          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5368          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
5369         reset_rps(dev_priv, gen6_set_rps);
5370
5371         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5372 }
5373
5374 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
5375 {
5376         struct intel_engine_cs *engine;
5377         enum intel_engine_id id;
5378         uint32_t rc6_mask = 0;
5379
5380         /* 1a: Software RC state - RC0 */
5381         I915_WRITE(GEN6_RC_STATE, 0);
5382
5383         /* 1b: Get forcewake during program sequence. Although the driver
5384          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5385         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5386
5387         /* 2a: Disable RC states. */
5388         I915_WRITE(GEN6_RC_CONTROL, 0);
5389
5390         /* 2b: Program RC6 thresholds.*/
5391
5392         /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
5393         if (IS_SKYLAKE(dev_priv))
5394                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5395         else
5396                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
5397         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5398         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5399         for_each_engine(engine, dev_priv, id)
5400                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5401
5402         if (HAS_GUC(dev_priv))
5403                 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5404
5405         I915_WRITE(GEN6_RC_SLEEP, 0);
5406
5407         /* 2c: Program Coarse Power Gating Policies. */
5408         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5409         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5410
5411         /* 3a: Enable RC6 */
5412         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5413                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5414         DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
5415         /* WaRsUseTimeoutMode:bxt */
5416         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5417                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
5418                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5419                            GEN7_RC_CTL_TO_MODE |
5420                            rc6_mask);
5421         } else {
5422                 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
5423                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5424                            GEN6_RC_CTL_EI_MODE(1) |
5425                            rc6_mask);
5426         }
5427
5428         /*
5429          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
5430          * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
5431          */
5432         if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
5433                 I915_WRITE(GEN9_PG_ENABLE, 0);
5434         else
5435                 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5436                                 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
5437
5438         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5439 }
5440
5441 static void gen8_enable_rps(struct drm_i915_private *dev_priv)
5442 {
5443         struct intel_engine_cs *engine;
5444         enum intel_engine_id id;
5445         uint32_t rc6_mask = 0;
5446
5447         /* 1a: Software RC state - RC0 */
5448         I915_WRITE(GEN6_RC_STATE, 0);
5449
5450         /* 1c & 1d: Get forcewake during program sequence. Although the driver
5451          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5452         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5453
5454         /* 2a: Disable RC states. */
5455         I915_WRITE(GEN6_RC_CONTROL, 0);
5456
5457         /* 2b: Program RC6 thresholds.*/
5458         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5459         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5460         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5461         for_each_engine(engine, dev_priv, id)
5462                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5463         I915_WRITE(GEN6_RC_SLEEP, 0);
5464         if (IS_BROADWELL(dev_priv))
5465                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5466         else
5467                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
5468
5469         /* 3: Enable RC6 */
5470         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5471                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5472         intel_print_rc6_info(dev_priv, rc6_mask);
5473         if (IS_BROADWELL(dev_priv))
5474                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5475                                 GEN7_RC_CTL_TO_MODE |
5476                                 rc6_mask);
5477         else
5478                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5479                                 GEN6_RC_CTL_EI_MODE(1) |
5480                                 rc6_mask);
5481
5482         /* 4 Program defaults and thresholds for RPS*/
5483         I915_WRITE(GEN6_RPNSWREQ,
5484                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5485         I915_WRITE(GEN6_RC_VIDEO_FREQ,
5486                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5487         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5488         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5489
5490         /* Docs recommend 900MHz, and 300 MHz respectively */
5491         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5492                    dev_priv->rps.max_freq_softlimit << 24 |
5493                    dev_priv->rps.min_freq_softlimit << 16);
5494
5495         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5496         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5497         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5498         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5499
5500         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5501
5502         /* 5: Enable RPS */
5503         I915_WRITE(GEN6_RP_CONTROL,
5504                    GEN6_RP_MEDIA_TURBO |
5505                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5506                    GEN6_RP_MEDIA_IS_GFX |
5507                    GEN6_RP_ENABLE |
5508                    GEN6_RP_UP_BUSY_AVG |
5509                    GEN6_RP_DOWN_IDLE_AVG);
5510
5511         /* 6: Ring frequency + overclocking (our driver does this later */
5512
5513         reset_rps(dev_priv, gen6_set_rps);
5514
5515         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5516 }
5517
5518 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
5519 {
5520         struct intel_engine_cs *engine;
5521         enum intel_engine_id id;
5522         u32 rc6vids, rc6_mask = 0;
5523         u32 gtfifodbg;
5524         int rc6_mode;
5525         int ret;
5526
5527         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5528
5529         /* Here begins a magic sequence of register writes to enable
5530          * auto-downclocking.
5531          *
5532          * Perhaps there might be some value in exposing these to
5533          * userspace...
5534          */
5535         I915_WRITE(GEN6_RC_STATE, 0);
5536
5537         /* Clear the DBG now so we don't confuse earlier errors */
5538         gtfifodbg = I915_READ(GTFIFODBG);
5539         if (gtfifodbg) {
5540                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5541                 I915_WRITE(GTFIFODBG, gtfifodbg);
5542         }
5543
5544         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5545
5546         /* disable the counters and set deterministic thresholds */
5547         I915_WRITE(GEN6_RC_CONTROL, 0);
5548
5549         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5550         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5551         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5552         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5553         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5554
5555         for_each_engine(engine, dev_priv, id)
5556                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5557
5558         I915_WRITE(GEN6_RC_SLEEP, 0);
5559         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
5560         if (IS_IVYBRIDGE(dev_priv))
5561                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5562         else
5563                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
5564         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
5565         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5566
5567         /* Check if we are enabling RC6 */
5568         rc6_mode = intel_enable_rc6();
5569         if (rc6_mode & INTEL_RC6_ENABLE)
5570                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5571
5572         /* We don't use those on Haswell */
5573         if (!IS_HASWELL(dev_priv)) {
5574                 if (rc6_mode & INTEL_RC6p_ENABLE)
5575                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5576
5577                 if (rc6_mode & INTEL_RC6pp_ENABLE)
5578                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5579         }
5580
5581         intel_print_rc6_info(dev_priv, rc6_mask);
5582
5583         I915_WRITE(GEN6_RC_CONTROL,
5584                    rc6_mask |
5585                    GEN6_RC_CTL_EI_MODE(1) |
5586                    GEN6_RC_CTL_HW_ENABLE);
5587
5588         /* Power down if completely idle for over 50ms */
5589         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5590         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5591
5592         reset_rps(dev_priv, gen6_set_rps);
5593
5594         rc6vids = 0;
5595         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5596         if (IS_GEN6(dev_priv) && ret) {
5597                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5598         } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5599                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5600                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5601                 rc6vids &= 0xffff00;
5602                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5603                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5604                 if (ret)
5605                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5606         }
5607
5608         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5609 }
5610
5611 static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
5612 {
5613         int min_freq = 15;
5614         unsigned int gpu_freq;
5615         unsigned int max_ia_freq, min_ring_freq;
5616         unsigned int max_gpu_freq, min_gpu_freq;
5617         int scaling_factor = 180;
5618         struct cpufreq_policy *policy;
5619
5620         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5621
5622         policy = cpufreq_cpu_get(0);
5623         if (policy) {
5624                 max_ia_freq = policy->cpuinfo.max_freq;
5625                 cpufreq_cpu_put(policy);
5626         } else {
5627                 /*
5628                  * Default to measured freq if none found, PCU will ensure we
5629                  * don't go over
5630                  */
5631                 max_ia_freq = tsc_khz;
5632         }
5633
5634         /* Convert from kHz to MHz */
5635         max_ia_freq /= 1000;
5636
5637         min_ring_freq = I915_READ(DCLK) & 0xf;
5638         /* convert DDR frequency from units of 266.6MHz to bandwidth */
5639         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5640
5641         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5642                 /* Convert GT frequency to 50 HZ units */
5643                 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5644                 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5645         } else {
5646                 min_gpu_freq = dev_priv->rps.min_freq;
5647                 max_gpu_freq = dev_priv->rps.max_freq;
5648         }
5649
5650         /*
5651          * For each potential GPU frequency, load a ring frequency we'd like
5652          * to use for memory access.  We do this by specifying the IA frequency
5653          * the PCU should use as a reference to determine the ring frequency.
5654          */
5655         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5656                 int diff = max_gpu_freq - gpu_freq;
5657                 unsigned int ia_freq = 0, ring_freq = 0;
5658
5659                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5660                         /*
5661                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
5662                          * No floor required for ring frequency on SKL.
5663                          */
5664                         ring_freq = gpu_freq;
5665                 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
5666                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
5667                         ring_freq = max(min_ring_freq, gpu_freq);
5668                 } else if (IS_HASWELL(dev_priv)) {
5669                         ring_freq = mult_frac(gpu_freq, 5, 4);
5670                         ring_freq = max(min_ring_freq, ring_freq);
5671                         /* leave ia_freq as the default, chosen by cpufreq */
5672                 } else {
5673                         /* On older processors, there is no separate ring
5674                          * clock domain, so in order to boost the bandwidth
5675                          * of the ring, we need to upclock the CPU (ia_freq).
5676                          *
5677                          * For GPU frequencies less than 750MHz,
5678                          * just use the lowest ring freq.
5679                          */
5680                         if (gpu_freq < min_freq)
5681                                 ia_freq = 800;
5682                         else
5683                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5684                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5685                 }
5686
5687                 sandybridge_pcode_write(dev_priv,
5688                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5689                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5690                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5691                                         gpu_freq);
5692         }
5693 }
5694
5695 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5696 {
5697         u32 val, rp0;
5698
5699         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5700
5701         switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
5702         case 8:
5703                 /* (2 * 4) config */
5704                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5705                 break;
5706         case 12:
5707                 /* (2 * 6) config */
5708                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5709                 break;
5710         case 16:
5711                 /* (2 * 8) config */
5712         default:
5713                 /* Setting (2 * 8) Min RP0 for any other combination */
5714                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5715                 break;
5716         }
5717
5718         rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5719
5720         return rp0;
5721 }
5722
5723 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5724 {
5725         u32 val, rpe;
5726
5727         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5728         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5729
5730         return rpe;
5731 }
5732
5733 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5734 {
5735         u32 val, rp1;
5736
5737         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5738         rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5739
5740         return rp1;
5741 }
5742
5743 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5744 {
5745         u32 val, rp1;
5746
5747         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5748
5749         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5750
5751         return rp1;
5752 }
5753
5754 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5755 {
5756         u32 val, rp0;
5757
5758         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5759
5760         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5761         /* Clamp to max */
5762         rp0 = min_t(u32, rp0, 0xea);
5763
5764         return rp0;
5765 }
5766
5767 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5768 {
5769         u32 val, rpe;
5770
5771         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5772         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5773         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5774         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5775
5776         return rpe;
5777 }
5778
5779 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5780 {
5781         u32 val;
5782
5783         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5784         /*
5785          * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5786          * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5787          * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5788          * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5789          * to make sure it matches what Punit accepts.
5790          */
5791         return max_t(u32, val, 0xc0);
5792 }
5793
5794 /* Check that the pctx buffer wasn't move under us. */
5795 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5796 {
5797         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5798
5799         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5800                              dev_priv->vlv_pctx->stolen->start);
5801 }
5802
5803
5804 /* Check that the pcbr address is not empty. */
5805 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5806 {
5807         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5808
5809         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5810 }
5811
5812 static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
5813 {
5814         struct i915_ggtt *ggtt = &dev_priv->ggtt;
5815         unsigned long pctx_paddr, paddr;
5816         u32 pcbr;
5817         int pctx_size = 32*1024;
5818
5819         pcbr = I915_READ(VLV_PCBR);
5820         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5821                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5822                 paddr = (dev_priv->mm.stolen_base +
5823                          (ggtt->stolen_size - pctx_size));
5824
5825                 pctx_paddr = (paddr & (~4095));
5826                 I915_WRITE(VLV_PCBR, pctx_paddr);
5827         }
5828
5829         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5830 }
5831
5832 static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
5833 {
5834         struct drm_i915_gem_object *pctx;
5835         unsigned long pctx_paddr;
5836         u32 pcbr;
5837         int pctx_size = 24*1024;
5838
5839         pcbr = I915_READ(VLV_PCBR);
5840         if (pcbr) {
5841                 /* BIOS set it up already, grab the pre-alloc'd space */
5842                 int pcbr_offset;
5843
5844                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5845                 pctx = i915_gem_object_create_stolen_for_preallocated(&dev_priv->drm,
5846                                                                       pcbr_offset,
5847                                                                       I915_GTT_OFFSET_NONE,
5848                                                                       pctx_size);
5849                 goto out;
5850         }
5851
5852         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5853
5854         /*
5855          * From the Gunit register HAS:
5856          * The Gfx driver is expected to program this register and ensure
5857          * proper allocation within Gfx stolen memory.  For example, this
5858          * register should be programmed such than the PCBR range does not
5859          * overlap with other ranges, such as the frame buffer, protected
5860          * memory, or any other relevant ranges.
5861          */
5862         pctx = i915_gem_object_create_stolen(&dev_priv->drm, pctx_size);
5863         if (!pctx) {
5864                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5865                 goto out;
5866         }
5867
5868         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5869         I915_WRITE(VLV_PCBR, pctx_paddr);
5870
5871 out:
5872         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5873         dev_priv->vlv_pctx = pctx;
5874 }
5875
5876 static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
5877 {
5878         if (WARN_ON(!dev_priv->vlv_pctx))
5879                 return;
5880
5881         i915_gem_object_put_unlocked(dev_priv->vlv_pctx);
5882         dev_priv->vlv_pctx = NULL;
5883 }
5884
5885 static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5886 {
5887         dev_priv->rps.gpll_ref_freq =
5888                 vlv_get_cck_clock(dev_priv, "GPLL ref",
5889                                   CCK_GPLL_CLOCK_CONTROL,
5890                                   dev_priv->czclk_freq);
5891
5892         DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5893                          dev_priv->rps.gpll_ref_freq);
5894 }
5895
5896 static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
5897 {
5898         u32 val;
5899
5900         valleyview_setup_pctx(dev_priv);
5901
5902         vlv_init_gpll_ref_freq(dev_priv);
5903
5904         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5905         switch ((val >> 6) & 3) {
5906         case 0:
5907         case 1:
5908                 dev_priv->mem_freq = 800;
5909                 break;
5910         case 2:
5911                 dev_priv->mem_freq = 1066;
5912                 break;
5913         case 3:
5914                 dev_priv->mem_freq = 1333;
5915                 break;
5916         }
5917         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5918
5919         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5920         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5921         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5922                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5923                          dev_priv->rps.max_freq);
5924
5925         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5926         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5927                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5928                          dev_priv->rps.efficient_freq);
5929
5930         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5931         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5932                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5933                          dev_priv->rps.rp1_freq);
5934
5935         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5936         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5937                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5938                          dev_priv->rps.min_freq);
5939 }
5940
5941 static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
5942 {
5943         u32 val;
5944
5945         cherryview_setup_pctx(dev_priv);
5946
5947         vlv_init_gpll_ref_freq(dev_priv);
5948
5949         mutex_lock(&dev_priv->sb_lock);
5950         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5951         mutex_unlock(&dev_priv->sb_lock);
5952
5953         switch ((val >> 2) & 0x7) {
5954         case 3:
5955                 dev_priv->mem_freq = 2000;
5956                 break;
5957         default:
5958                 dev_priv->mem_freq = 1600;
5959                 break;
5960         }
5961         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5962
5963         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5964         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5965         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5966                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5967                          dev_priv->rps.max_freq);
5968
5969         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5970         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5971                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5972                          dev_priv->rps.efficient_freq);
5973
5974         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5975         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5976                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5977                          dev_priv->rps.rp1_freq);
5978
5979         /* PUnit validated range is only [RPe, RP0] */
5980         dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5981         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5982                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5983                          dev_priv->rps.min_freq);
5984
5985         WARN_ONCE((dev_priv->rps.max_freq |
5986                    dev_priv->rps.efficient_freq |
5987                    dev_priv->rps.rp1_freq |
5988                    dev_priv->rps.min_freq) & 1,
5989                   "Odd GPU freq values\n");
5990 }
5991
5992 static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
5993 {
5994         valleyview_cleanup_pctx(dev_priv);
5995 }
5996
5997 static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
5998 {
5999         struct intel_engine_cs *engine;
6000         enum intel_engine_id id;
6001         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
6002
6003         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6004
6005         gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
6006                                              GT_FIFO_FREE_ENTRIES_CHV);
6007         if (gtfifodbg) {
6008                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6009                                  gtfifodbg);
6010                 I915_WRITE(GTFIFODBG, gtfifodbg);
6011         }
6012
6013         cherryview_check_pctx(dev_priv);
6014
6015         /* 1a & 1b: Get forcewake during program sequence. Although the driver
6016          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
6017         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6018
6019         /*  Disable RC states. */
6020         I915_WRITE(GEN6_RC_CONTROL, 0);
6021
6022         /* 2a: Program RC6 thresholds.*/
6023         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
6024         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6025         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6026
6027         for_each_engine(engine, dev_priv, id)
6028                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6029         I915_WRITE(GEN6_RC_SLEEP, 0);
6030
6031         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
6032         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
6033
6034         /* allows RC6 residency counter to work */
6035         I915_WRITE(VLV_COUNTER_CONTROL,
6036                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
6037                                       VLV_MEDIA_RC6_COUNT_EN |
6038                                       VLV_RENDER_RC6_COUNT_EN));
6039
6040         /* For now we assume BIOS is allocating and populating the PCBR  */
6041         pcbr = I915_READ(VLV_PCBR);
6042
6043         /* 3: Enable RC6 */
6044         if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
6045             (pcbr >> VLV_PCBR_ADDR_SHIFT))
6046                 rc6_mode = GEN7_RC_CTL_TO_MODE;
6047
6048         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6049
6050         /* 4 Program defaults and thresholds for RPS*/
6051         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6052         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6053         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6054         I915_WRITE(GEN6_RP_UP_EI, 66000);
6055         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6056
6057         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6058
6059         /* 5: Enable RPS */
6060         I915_WRITE(GEN6_RP_CONTROL,
6061                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
6062                    GEN6_RP_MEDIA_IS_GFX |
6063                    GEN6_RP_ENABLE |
6064                    GEN6_RP_UP_BUSY_AVG |
6065                    GEN6_RP_DOWN_IDLE_AVG);
6066
6067         /* Setting Fixed Bias */
6068         val = VLV_OVERRIDE_EN |
6069                   VLV_SOC_TDP_EN |
6070                   CHV_BIAS_CPU_50_SOC_50;
6071         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6072
6073         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6074
6075         /* RPS code assumes GPLL is used */
6076         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6077
6078         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6079         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6080
6081         reset_rps(dev_priv, valleyview_set_rps);
6082
6083         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6084 }
6085
6086 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
6087 {
6088         struct intel_engine_cs *engine;
6089         enum intel_engine_id id;
6090         u32 gtfifodbg, val, rc6_mode = 0;
6091
6092         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6093
6094         valleyview_check_pctx(dev_priv);
6095
6096         gtfifodbg = I915_READ(GTFIFODBG);
6097         if (gtfifodbg) {
6098                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6099                                  gtfifodbg);
6100                 I915_WRITE(GTFIFODBG, gtfifodbg);
6101         }
6102
6103         /* If VLV, Forcewake all wells, else re-direct to regular path */
6104         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6105
6106         /*  Disable RC states. */
6107         I915_WRITE(GEN6_RC_CONTROL, 0);
6108
6109         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6110         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6111         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6112         I915_WRITE(GEN6_RP_UP_EI, 66000);
6113         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6114
6115         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6116
6117         I915_WRITE(GEN6_RP_CONTROL,
6118                    GEN6_RP_MEDIA_TURBO |
6119                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
6120                    GEN6_RP_MEDIA_IS_GFX |
6121                    GEN6_RP_ENABLE |
6122                    GEN6_RP_UP_BUSY_AVG |
6123                    GEN6_RP_DOWN_IDLE_CONT);
6124
6125         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
6126         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6127         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6128
6129         for_each_engine(engine, dev_priv, id)
6130                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6131
6132         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
6133
6134         /* allows RC6 residency counter to work */
6135         I915_WRITE(VLV_COUNTER_CONTROL,
6136                    _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
6137                                       VLV_RENDER_RC0_COUNT_EN |
6138                                       VLV_MEDIA_RC6_COUNT_EN |
6139                                       VLV_RENDER_RC6_COUNT_EN));
6140
6141         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6142                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
6143
6144         intel_print_rc6_info(dev_priv, rc6_mode);
6145
6146         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6147
6148         /* Setting Fixed Bias */
6149         val = VLV_OVERRIDE_EN |
6150                   VLV_SOC_TDP_EN |
6151                   VLV_BIAS_CPU_125_SOC_875;
6152         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6153
6154         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6155
6156         /* RPS code assumes GPLL is used */
6157         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6158
6159         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6160         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6161
6162         reset_rps(dev_priv, valleyview_set_rps);
6163
6164         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6165 }
6166
6167 static unsigned long intel_pxfreq(u32 vidfreq)
6168 {
6169         unsigned long freq;
6170         int div = (vidfreq & 0x3f0000) >> 16;
6171         int post = (vidfreq & 0x3000) >> 12;
6172         int pre = (vidfreq & 0x7);
6173
6174         if (!pre)
6175                 return 0;
6176
6177         freq = ((div * 133333) / ((1<<post) * pre));
6178
6179         return freq;
6180 }
6181
6182 static const struct cparams {
6183         u16 i;
6184         u16 t;
6185         u16 m;
6186         u16 c;
6187 } cparams[] = {
6188         { 1, 1333, 301, 28664 },
6189         { 1, 1066, 294, 24460 },
6190         { 1, 800, 294, 25192 },
6191         { 0, 1333, 276, 27605 },
6192         { 0, 1066, 276, 27605 },
6193         { 0, 800, 231, 23784 },
6194 };
6195
6196 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
6197 {
6198         u64 total_count, diff, ret;
6199         u32 count1, count2, count3, m = 0, c = 0;
6200         unsigned long now = jiffies_to_msecs(jiffies), diff1;
6201         int i;
6202
6203         assert_spin_locked(&mchdev_lock);
6204
6205         diff1 = now - dev_priv->ips.last_time1;
6206
6207         /* Prevent division-by-zero if we are asking too fast.
6208          * Also, we don't get interesting results if we are polling
6209          * faster than once in 10ms, so just return the saved value
6210          * in such cases.
6211          */
6212         if (diff1 <= 10)
6213                 return dev_priv->ips.chipset_power;
6214
6215         count1 = I915_READ(DMIEC);
6216         count2 = I915_READ(DDREC);
6217         count3 = I915_READ(CSIEC);
6218
6219         total_count = count1 + count2 + count3;
6220
6221         /* FIXME: handle per-counter overflow */
6222         if (total_count < dev_priv->ips.last_count1) {
6223                 diff = ~0UL - dev_priv->ips.last_count1;
6224                 diff += total_count;
6225         } else {
6226                 diff = total_count - dev_priv->ips.last_count1;
6227         }
6228
6229         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
6230                 if (cparams[i].i == dev_priv->ips.c_m &&
6231                     cparams[i].t == dev_priv->ips.r_t) {
6232                         m = cparams[i].m;
6233                         c = cparams[i].c;
6234                         break;
6235                 }
6236         }
6237
6238         diff = div_u64(diff, diff1);
6239         ret = ((m * diff) + c);
6240         ret = div_u64(ret, 10);
6241
6242         dev_priv->ips.last_count1 = total_count;
6243         dev_priv->ips.last_time1 = now;
6244
6245         dev_priv->ips.chipset_power = ret;
6246
6247         return ret;
6248 }
6249
6250 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6251 {
6252         unsigned long val;
6253
6254         if (INTEL_INFO(dev_priv)->gen != 5)
6255                 return 0;
6256
6257         spin_lock_irq(&mchdev_lock);
6258
6259         val = __i915_chipset_val(dev_priv);
6260
6261         spin_unlock_irq(&mchdev_lock);
6262
6263         return val;
6264 }
6265
6266 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6267 {
6268         unsigned long m, x, b;
6269         u32 tsfs;
6270
6271         tsfs = I915_READ(TSFS);
6272
6273         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6274         x = I915_READ8(TR1);
6275
6276         b = tsfs & TSFS_INTR_MASK;
6277
6278         return ((m * x) / 127) - b;
6279 }
6280
6281 static int _pxvid_to_vd(u8 pxvid)
6282 {
6283         if (pxvid == 0)
6284                 return 0;
6285
6286         if (pxvid >= 8 && pxvid < 31)
6287                 pxvid = 31;
6288
6289         return (pxvid + 2) * 125;
6290 }
6291
6292 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
6293 {
6294         const int vd = _pxvid_to_vd(pxvid);
6295         const int vm = vd - 1125;
6296
6297         if (INTEL_INFO(dev_priv)->is_mobile)
6298                 return vm > 0 ? vm : 0;
6299
6300         return vd;
6301 }
6302
6303 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
6304 {
6305         u64 now, diff, diffms;
6306         u32 count;
6307
6308         assert_spin_locked(&mchdev_lock);
6309
6310         now = ktime_get_raw_ns();
6311         diffms = now - dev_priv->ips.last_time2;
6312         do_div(diffms, NSEC_PER_MSEC);
6313
6314         /* Don't divide by 0 */
6315         if (!diffms)
6316                 return;
6317
6318         count = I915_READ(GFXEC);
6319
6320         if (count < dev_priv->ips.last_count2) {
6321                 diff = ~0UL - dev_priv->ips.last_count2;
6322                 diff += count;
6323         } else {
6324                 diff = count - dev_priv->ips.last_count2;
6325         }
6326
6327         dev_priv->ips.last_count2 = count;
6328         dev_priv->ips.last_time2 = now;
6329
6330         /* More magic constants... */
6331         diff = diff * 1181;
6332         diff = div_u64(diff, diffms * 10);
6333         dev_priv->ips.gfx_power = diff;
6334 }
6335
6336 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6337 {
6338         if (INTEL_INFO(dev_priv)->gen != 5)
6339                 return;
6340
6341         spin_lock_irq(&mchdev_lock);
6342
6343         __i915_update_gfx_val(dev_priv);
6344
6345         spin_unlock_irq(&mchdev_lock);
6346 }
6347
6348 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
6349 {
6350         unsigned long t, corr, state1, corr2, state2;
6351         u32 pxvid, ext_v;
6352
6353         assert_spin_locked(&mchdev_lock);
6354
6355         pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
6356         pxvid = (pxvid >> 24) & 0x7f;
6357         ext_v = pvid_to_extvid(dev_priv, pxvid);
6358
6359         state1 = ext_v;
6360
6361         t = i915_mch_val(dev_priv);
6362
6363         /* Revel in the empirically derived constants */
6364
6365         /* Correction factor in 1/100000 units */
6366         if (t > 80)
6367                 corr = ((t * 2349) + 135940);
6368         else if (t >= 50)
6369                 corr = ((t * 964) + 29317);
6370         else /* < 50 */
6371                 corr = ((t * 301) + 1004);
6372
6373         corr = corr * ((150142 * state1) / 10000 - 78642);
6374         corr /= 100000;
6375         corr2 = (corr * dev_priv->ips.corr);
6376
6377         state2 = (corr2 * state1) / 10000;
6378         state2 /= 100; /* convert to mW */
6379
6380         __i915_update_gfx_val(dev_priv);
6381
6382         return dev_priv->ips.gfx_power + state2;
6383 }
6384
6385 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6386 {
6387         unsigned long val;
6388
6389         if (INTEL_INFO(dev_priv)->gen != 5)
6390                 return 0;
6391
6392         spin_lock_irq(&mchdev_lock);
6393
6394         val = __i915_gfx_val(dev_priv);
6395
6396         spin_unlock_irq(&mchdev_lock);
6397
6398         return val;
6399 }
6400
6401 /**
6402  * i915_read_mch_val - return value for IPS use
6403  *
6404  * Calculate and return a value for the IPS driver to use when deciding whether
6405  * we have thermal and power headroom to increase CPU or GPU power budget.
6406  */
6407 unsigned long i915_read_mch_val(void)
6408 {
6409         struct drm_i915_private *dev_priv;
6410         unsigned long chipset_val, graphics_val, ret = 0;
6411
6412         spin_lock_irq(&mchdev_lock);
6413         if (!i915_mch_dev)
6414                 goto out_unlock;
6415         dev_priv = i915_mch_dev;
6416
6417         chipset_val = __i915_chipset_val(dev_priv);
6418         graphics_val = __i915_gfx_val(dev_priv);
6419
6420         ret = chipset_val + graphics_val;
6421
6422 out_unlock:
6423         spin_unlock_irq(&mchdev_lock);
6424
6425         return ret;
6426 }
6427 EXPORT_SYMBOL_GPL(i915_read_mch_val);
6428
6429 /**
6430  * i915_gpu_raise - raise GPU frequency limit
6431  *
6432  * Raise the limit; IPS indicates we have thermal headroom.
6433  */
6434 bool i915_gpu_raise(void)
6435 {
6436         struct drm_i915_private *dev_priv;
6437         bool ret = true;
6438
6439         spin_lock_irq(&mchdev_lock);
6440         if (!i915_mch_dev) {
6441                 ret = false;
6442                 goto out_unlock;
6443         }
6444         dev_priv = i915_mch_dev;
6445
6446         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6447                 dev_priv->ips.max_delay--;
6448
6449 out_unlock:
6450         spin_unlock_irq(&mchdev_lock);
6451
6452         return ret;
6453 }
6454 EXPORT_SYMBOL_GPL(i915_gpu_raise);
6455
6456 /**
6457  * i915_gpu_lower - lower GPU frequency limit
6458  *
6459  * IPS indicates we're close to a thermal limit, so throttle back the GPU
6460  * frequency maximum.
6461  */
6462 bool i915_gpu_lower(void)
6463 {
6464         struct drm_i915_private *dev_priv;
6465         bool ret = true;
6466
6467         spin_lock_irq(&mchdev_lock);
6468         if (!i915_mch_dev) {
6469                 ret = false;
6470                 goto out_unlock;
6471         }
6472         dev_priv = i915_mch_dev;
6473
6474         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6475                 dev_priv->ips.max_delay++;
6476
6477 out_unlock:
6478         spin_unlock_irq(&mchdev_lock);
6479
6480         return ret;
6481 }
6482 EXPORT_SYMBOL_GPL(i915_gpu_lower);
6483
6484 /**
6485  * i915_gpu_busy - indicate GPU business to IPS
6486  *
6487  * Tell the IPS driver whether or not the GPU is busy.
6488  */
6489 bool i915_gpu_busy(void)
6490 {
6491         bool ret = false;
6492
6493         spin_lock_irq(&mchdev_lock);
6494         if (i915_mch_dev)
6495                 ret = i915_mch_dev->gt.awake;
6496         spin_unlock_irq(&mchdev_lock);
6497
6498         return ret;
6499 }
6500 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6501
6502 /**
6503  * i915_gpu_turbo_disable - disable graphics turbo
6504  *
6505  * Disable graphics turbo by resetting the max frequency and setting the
6506  * current frequency to the default.
6507  */
6508 bool i915_gpu_turbo_disable(void)
6509 {
6510         struct drm_i915_private *dev_priv;
6511         bool ret = true;
6512
6513         spin_lock_irq(&mchdev_lock);
6514         if (!i915_mch_dev) {
6515                 ret = false;
6516                 goto out_unlock;
6517         }
6518         dev_priv = i915_mch_dev;
6519
6520         dev_priv->ips.max_delay = dev_priv->ips.fstart;
6521
6522         if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
6523                 ret = false;
6524
6525 out_unlock:
6526         spin_unlock_irq(&mchdev_lock);
6527
6528         return ret;
6529 }
6530 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6531
6532 /**
6533  * Tells the intel_ips driver that the i915 driver is now loaded, if
6534  * IPS got loaded first.
6535  *
6536  * This awkward dance is so that neither module has to depend on the
6537  * other in order for IPS to do the appropriate communication of
6538  * GPU turbo limits to i915.
6539  */
6540 static void
6541 ips_ping_for_i915_load(void)
6542 {
6543         void (*link)(void);
6544
6545         link = symbol_get(ips_link_to_i915_driver);
6546         if (link) {
6547                 link();
6548                 symbol_put(ips_link_to_i915_driver);
6549         }
6550 }
6551
6552 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6553 {
6554         /* We only register the i915 ips part with intel-ips once everything is
6555          * set up, to avoid intel-ips sneaking in and reading bogus values. */
6556         spin_lock_irq(&mchdev_lock);
6557         i915_mch_dev = dev_priv;
6558         spin_unlock_irq(&mchdev_lock);
6559
6560         ips_ping_for_i915_load();
6561 }
6562
6563 void intel_gpu_ips_teardown(void)
6564 {
6565         spin_lock_irq(&mchdev_lock);
6566         i915_mch_dev = NULL;
6567         spin_unlock_irq(&mchdev_lock);
6568 }
6569
6570 static void intel_init_emon(struct drm_i915_private *dev_priv)
6571 {
6572         u32 lcfuse;
6573         u8 pxw[16];
6574         int i;
6575
6576         /* Disable to program */
6577         I915_WRITE(ECR, 0);
6578         POSTING_READ(ECR);
6579
6580         /* Program energy weights for various events */
6581         I915_WRITE(SDEW, 0x15040d00);
6582         I915_WRITE(CSIEW0, 0x007f0000);
6583         I915_WRITE(CSIEW1, 0x1e220004);
6584         I915_WRITE(CSIEW2, 0x04000004);
6585
6586         for (i = 0; i < 5; i++)
6587                 I915_WRITE(PEW(i), 0);
6588         for (i = 0; i < 3; i++)
6589                 I915_WRITE(DEW(i), 0);
6590
6591         /* Program P-state weights to account for frequency power adjustment */
6592         for (i = 0; i < 16; i++) {
6593                 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6594                 unsigned long freq = intel_pxfreq(pxvidfreq);
6595                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6596                         PXVFREQ_PX_SHIFT;
6597                 unsigned long val;
6598
6599                 val = vid * vid;
6600                 val *= (freq / 1000);
6601                 val *= 255;
6602                 val /= (127*127*900);
6603                 if (val > 0xff)
6604                         DRM_ERROR("bad pxval: %ld\n", val);
6605                 pxw[i] = val;
6606         }
6607         /* Render standby states get 0 weight */
6608         pxw[14] = 0;
6609         pxw[15] = 0;
6610
6611         for (i = 0; i < 4; i++) {
6612                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6613                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6614                 I915_WRITE(PXW(i), val);
6615         }
6616
6617         /* Adjust magic regs to magic values (more experimental results) */
6618         I915_WRITE(OGW0, 0);
6619         I915_WRITE(OGW1, 0);
6620         I915_WRITE(EG0, 0x00007f00);
6621         I915_WRITE(EG1, 0x0000000e);
6622         I915_WRITE(EG2, 0x000e0000);
6623         I915_WRITE(EG3, 0x68000300);
6624         I915_WRITE(EG4, 0x42000000);
6625         I915_WRITE(EG5, 0x00140031);
6626         I915_WRITE(EG6, 0);
6627         I915_WRITE(EG7, 0);
6628
6629         for (i = 0; i < 8; i++)
6630                 I915_WRITE(PXWL(i), 0);
6631
6632         /* Enable PMON + select events */
6633         I915_WRITE(ECR, 0x80000019);
6634
6635         lcfuse = I915_READ(LCFUSE02);
6636
6637         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6638 }
6639
6640 void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
6641 {
6642         /*
6643          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6644          * requirement.
6645          */
6646         if (!i915.enable_rc6) {
6647                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6648                 intel_runtime_pm_get(dev_priv);
6649         }
6650
6651         mutex_lock(&dev_priv->drm.struct_mutex);
6652         mutex_lock(&dev_priv->rps.hw_lock);
6653
6654         /* Initialize RPS limits (for userspace) */
6655         if (IS_CHERRYVIEW(dev_priv))
6656                 cherryview_init_gt_powersave(dev_priv);
6657         else if (IS_VALLEYVIEW(dev_priv))
6658                 valleyview_init_gt_powersave(dev_priv);
6659         else if (INTEL_GEN(dev_priv) >= 6)
6660                 gen6_init_rps_frequencies(dev_priv);
6661
6662         /* Derive initial user preferences/limits from the hardware limits */
6663         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6664         dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6665
6666         dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6667         dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6668
6669         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6670                 dev_priv->rps.min_freq_softlimit =
6671                         max_t(int,
6672                               dev_priv->rps.efficient_freq,
6673                               intel_freq_opcode(dev_priv, 450));
6674
6675         /* After setting max-softlimit, find the overclock max freq */
6676         if (IS_GEN6(dev_priv) ||
6677             IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6678                 u32 params = 0;
6679
6680                 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
6681                 if (params & BIT(31)) { /* OC supported */
6682                         DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6683                                          (dev_priv->rps.max_freq & 0xff) * 50,
6684                                          (params & 0xff) * 50);
6685                         dev_priv->rps.max_freq = params & 0xff;
6686                 }
6687         }
6688
6689         /* Finally allow us to boost to max by default */
6690         dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6691
6692         mutex_unlock(&dev_priv->rps.hw_lock);
6693         mutex_unlock(&dev_priv->drm.struct_mutex);
6694
6695         intel_autoenable_gt_powersave(dev_priv);
6696 }
6697
6698 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
6699 {
6700         if (IS_VALLEYVIEW(dev_priv))
6701                 valleyview_cleanup_gt_powersave(dev_priv);
6702
6703         if (!i915.enable_rc6)
6704                 intel_runtime_pm_put(dev_priv);
6705 }
6706
6707 /**
6708  * intel_suspend_gt_powersave - suspend PM work and helper threads
6709  * @dev_priv: i915 device
6710  *
6711  * We don't want to disable RC6 or other features here, we just want
6712  * to make sure any work we've queued has finished and won't bother
6713  * us while we're suspended.
6714  */
6715 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6716 {
6717         if (INTEL_GEN(dev_priv) < 6)
6718                 return;
6719
6720         if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
6721                 intel_runtime_pm_put(dev_priv);
6722
6723         /* gen6_rps_idle() will be called later to disable interrupts */
6724 }
6725
6726 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
6727 {
6728         dev_priv->rps.enabled = true; /* force disabling */
6729         intel_disable_gt_powersave(dev_priv);
6730
6731         gen6_reset_rps_interrupts(dev_priv);
6732 }
6733
6734 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
6735 {
6736         if (!READ_ONCE(dev_priv->rps.enabled))
6737                 return;
6738
6739         mutex_lock(&dev_priv->rps.hw_lock);
6740
6741         if (INTEL_GEN(dev_priv) >= 9) {
6742                 gen9_disable_rc6(dev_priv);
6743                 gen9_disable_rps(dev_priv);
6744         } else if (IS_CHERRYVIEW(dev_priv)) {
6745                 cherryview_disable_rps(dev_priv);
6746         } else if (IS_VALLEYVIEW(dev_priv)) {
6747                 valleyview_disable_rps(dev_priv);
6748         } else if (INTEL_GEN(dev_priv) >= 6) {
6749                 gen6_disable_rps(dev_priv);
6750         }  else if (IS_IRONLAKE_M(dev_priv)) {
6751                 ironlake_disable_drps(dev_priv);
6752         }
6753
6754         dev_priv->rps.enabled = false;
6755         mutex_unlock(&dev_priv->rps.hw_lock);
6756 }
6757
6758 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
6759 {
6760         /* We shouldn't be disabling as we submit, so this should be less
6761          * racy than it appears!
6762          */
6763         if (READ_ONCE(dev_priv->rps.enabled))
6764                 return;
6765
6766         /* Powersaving is controlled by the host when inside a VM */
6767         if (intel_vgpu_active(dev_priv))
6768                 return;
6769
6770         mutex_lock(&dev_priv->rps.hw_lock);
6771
6772         if (IS_CHERRYVIEW(dev_priv)) {
6773                 cherryview_enable_rps(dev_priv);
6774         } else if (IS_VALLEYVIEW(dev_priv)) {
6775                 valleyview_enable_rps(dev_priv);
6776         } else if (INTEL_GEN(dev_priv) >= 9) {
6777                 gen9_enable_rc6(dev_priv);
6778                 gen9_enable_rps(dev_priv);
6779                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
6780                         gen6_update_ring_freq(dev_priv);
6781         } else if (IS_BROADWELL(dev_priv)) {
6782                 gen8_enable_rps(dev_priv);
6783                 gen6_update_ring_freq(dev_priv);
6784         } else if (INTEL_GEN(dev_priv) >= 6) {
6785                 gen6_enable_rps(dev_priv);
6786                 gen6_update_ring_freq(dev_priv);
6787         } else if (IS_IRONLAKE_M(dev_priv)) {
6788                 ironlake_enable_drps(dev_priv);
6789                 intel_init_emon(dev_priv);
6790         }
6791
6792         WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6793         WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6794
6795         WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6796         WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6797
6798         dev_priv->rps.enabled = true;
6799         mutex_unlock(&dev_priv->rps.hw_lock);
6800 }
6801
6802 static void __intel_autoenable_gt_powersave(struct work_struct *work)
6803 {
6804         struct drm_i915_private *dev_priv =
6805                 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
6806         struct intel_engine_cs *rcs;
6807         struct drm_i915_gem_request *req;
6808
6809         if (READ_ONCE(dev_priv->rps.enabled))
6810                 goto out;
6811
6812         rcs = dev_priv->engine[RCS];
6813         if (rcs->last_context)
6814                 goto out;
6815
6816         if (!rcs->init_context)
6817                 goto out;
6818
6819         mutex_lock(&dev_priv->drm.struct_mutex);
6820
6821         req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
6822         if (IS_ERR(req))
6823                 goto unlock;
6824
6825         if (!i915.enable_execlists && i915_switch_context(req) == 0)
6826                 rcs->init_context(req);
6827
6828         /* Mark the device busy, calling intel_enable_gt_powersave() */
6829         i915_add_request_no_flush(req);
6830
6831 unlock:
6832         mutex_unlock(&dev_priv->drm.struct_mutex);
6833 out:
6834         intel_runtime_pm_put(dev_priv);
6835 }
6836
6837 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
6838 {
6839         if (READ_ONCE(dev_priv->rps.enabled))
6840                 return;
6841
6842         if (IS_IRONLAKE_M(dev_priv)) {
6843                 ironlake_enable_drps(dev_priv);
6844                 intel_init_emon(dev_priv);
6845         } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6846                 /*
6847                  * PCU communication is slow and this doesn't need to be
6848                  * done at any specific time, so do this out of our fast path
6849                  * to make resume and init faster.
6850                  *
6851                  * We depend on the HW RC6 power context save/restore
6852                  * mechanism when entering D3 through runtime PM suspend. So
6853                  * disable RPM until RPS/RC6 is properly setup. We can only
6854                  * get here via the driver load/system resume/runtime resume
6855                  * paths, so the _noresume version is enough (and in case of
6856                  * runtime resume it's necessary).
6857                  */
6858                 if (queue_delayed_work(dev_priv->wq,
6859                                        &dev_priv->rps.autoenable_work,
6860                                        round_jiffies_up_relative(HZ)))
6861                         intel_runtime_pm_get_noresume(dev_priv);
6862         }
6863 }
6864
6865 static void ibx_init_clock_gating(struct drm_device *dev)
6866 {
6867         struct drm_i915_private *dev_priv = to_i915(dev);
6868
6869         /*
6870          * On Ibex Peak and Cougar Point, we need to disable clock
6871          * gating for the panel power sequencer or it will fail to
6872          * start up when no ports are active.
6873          */
6874         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6875 }
6876
6877 static void g4x_disable_trickle_feed(struct drm_device *dev)
6878 {
6879         struct drm_i915_private *dev_priv = to_i915(dev);
6880         enum pipe pipe;
6881
6882         for_each_pipe(dev_priv, pipe) {
6883                 I915_WRITE(DSPCNTR(pipe),
6884                            I915_READ(DSPCNTR(pipe)) |
6885                            DISPPLANE_TRICKLE_FEED_DISABLE);
6886
6887                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6888                 POSTING_READ(DSPSURF(pipe));
6889         }
6890 }
6891
6892 static void ilk_init_lp_watermarks(struct drm_device *dev)
6893 {
6894         struct drm_i915_private *dev_priv = to_i915(dev);
6895
6896         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6897         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6898         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6899
6900         /*
6901          * Don't touch WM1S_LP_EN here.
6902          * Doing so could cause underruns.
6903          */
6904 }
6905
6906 static void ironlake_init_clock_gating(struct drm_device *dev)
6907 {
6908         struct drm_i915_private *dev_priv = to_i915(dev);
6909         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6910
6911         /*
6912          * Required for FBC
6913          * WaFbcDisableDpfcClockGating:ilk
6914          */
6915         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6916                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6917                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6918
6919         I915_WRITE(PCH_3DCGDIS0,
6920                    MARIUNIT_CLOCK_GATE_DISABLE |
6921                    SVSMUNIT_CLOCK_GATE_DISABLE);
6922         I915_WRITE(PCH_3DCGDIS1,
6923                    VFMUNIT_CLOCK_GATE_DISABLE);
6924
6925         /*
6926          * According to the spec the following bits should be set in
6927          * order to enable memory self-refresh
6928          * The bit 22/21 of 0x42004
6929          * The bit 5 of 0x42020
6930          * The bit 15 of 0x45000
6931          */
6932         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6933                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
6934                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6935         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6936         I915_WRITE(DISP_ARB_CTL,
6937                    (I915_READ(DISP_ARB_CTL) |
6938                     DISP_FBC_WM_DIS));
6939
6940         ilk_init_lp_watermarks(dev);
6941
6942         /*
6943          * Based on the document from hardware guys the following bits
6944          * should be set unconditionally in order to enable FBC.
6945          * The bit 22 of 0x42000
6946          * The bit 22 of 0x42004
6947          * The bit 7,8,9 of 0x42020.
6948          */
6949         if (IS_IRONLAKE_M(dev_priv)) {
6950                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6951                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6952                            I915_READ(ILK_DISPLAY_CHICKEN1) |
6953                            ILK_FBCQ_DIS);
6954                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6955                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6956                            ILK_DPARB_GATE);
6957         }
6958
6959         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6960
6961         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6962                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6963                    ILK_ELPIN_409_SELECT);
6964         I915_WRITE(_3D_CHICKEN2,
6965                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6966                    _3D_CHICKEN2_WM_READ_PIPELINED);
6967
6968         /* WaDisableRenderCachePipelinedFlush:ilk */
6969         I915_WRITE(CACHE_MODE_0,
6970                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6971
6972         /* WaDisable_RenderCache_OperationalFlush:ilk */
6973         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6974
6975         g4x_disable_trickle_feed(dev);
6976
6977         ibx_init_clock_gating(dev);
6978 }
6979
6980 static void cpt_init_clock_gating(struct drm_device *dev)
6981 {
6982         struct drm_i915_private *dev_priv = to_i915(dev);
6983         int pipe;
6984         uint32_t val;
6985
6986         /*
6987          * On Ibex Peak and Cougar Point, we need to disable clock
6988          * gating for the panel power sequencer or it will fail to
6989          * start up when no ports are active.
6990          */
6991         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6992                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6993                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
6994         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6995                    DPLS_EDP_PPS_FIX_DIS);
6996         /* The below fixes the weird display corruption, a few pixels shifted
6997          * downward, on (only) LVDS of some HP laptops with IVY.
6998          */
6999         for_each_pipe(dev_priv, pipe) {
7000                 val = I915_READ(TRANS_CHICKEN2(pipe));
7001                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
7002                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
7003                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
7004                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
7005                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
7006                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
7007                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
7008                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
7009         }
7010         /* WADP0ClockGatingDisable */
7011         for_each_pipe(dev_priv, pipe) {
7012                 I915_WRITE(TRANS_CHICKEN1(pipe),
7013                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7014         }
7015 }
7016
7017 static void gen6_check_mch_setup(struct drm_device *dev)
7018 {
7019         struct drm_i915_private *dev_priv = to_i915(dev);
7020         uint32_t tmp;
7021
7022         tmp = I915_READ(MCH_SSKPD);
7023         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
7024                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
7025                               tmp);
7026 }
7027
7028 static void gen6_init_clock_gating(struct drm_device *dev)
7029 {
7030         struct drm_i915_private *dev_priv = to_i915(dev);
7031         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
7032
7033         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
7034
7035         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7036                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7037                    ILK_ELPIN_409_SELECT);
7038
7039         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
7040         I915_WRITE(_3D_CHICKEN,
7041                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
7042
7043         /* WaDisable_RenderCache_OperationalFlush:snb */
7044         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7045
7046         /*
7047          * BSpec recoomends 8x4 when MSAA is used,
7048          * however in practice 16x4 seems fastest.
7049          *
7050          * Note that PS/WM thread counts depend on the WIZ hashing
7051          * disable bit, which we don't touch here, but it's good
7052          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7053          */
7054         I915_WRITE(GEN6_GT_MODE,
7055                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7056
7057         ilk_init_lp_watermarks(dev);
7058
7059         I915_WRITE(CACHE_MODE_0,
7060                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
7061
7062         I915_WRITE(GEN6_UCGCTL1,
7063                    I915_READ(GEN6_UCGCTL1) |
7064                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
7065                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7066
7067         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7068          * gating disable must be set.  Failure to set it results in
7069          * flickering pixels due to Z write ordering failures after
7070          * some amount of runtime in the Mesa "fire" demo, and Unigine
7071          * Sanctuary and Tropics, and apparently anything else with
7072          * alpha test or pixel discard.
7073          *
7074          * According to the spec, bit 11 (RCCUNIT) must also be set,
7075          * but we didn't debug actual testcases to find it out.
7076          *
7077          * WaDisableRCCUnitClockGating:snb
7078          * WaDisableRCPBUnitClockGating:snb
7079          */
7080         I915_WRITE(GEN6_UCGCTL2,
7081                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7082                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7083
7084         /* WaStripsFansDisableFastClipPerformanceFix:snb */
7085         I915_WRITE(_3D_CHICKEN3,
7086                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
7087
7088         /*
7089          * Bspec says:
7090          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7091          * 3DSTATE_SF number of SF output attributes is more than 16."
7092          */
7093         I915_WRITE(_3D_CHICKEN3,
7094                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
7095
7096         /*
7097          * According to the spec the following bits should be
7098          * set in order to enable memory self-refresh and fbc:
7099          * The bit21 and bit22 of 0x42000
7100          * The bit21 and bit22 of 0x42004
7101          * The bit5 and bit7 of 0x42020
7102          * The bit14 of 0x70180
7103          * The bit14 of 0x71180
7104          *
7105          * WaFbcAsynchFlipDisableFbcQueue:snb
7106          */
7107         I915_WRITE(ILK_DISPLAY_CHICKEN1,
7108                    I915_READ(ILK_DISPLAY_CHICKEN1) |
7109                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7110         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7111                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7112                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7113         I915_WRITE(ILK_DSPCLK_GATE_D,
7114                    I915_READ(ILK_DSPCLK_GATE_D) |
7115                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
7116                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
7117
7118         g4x_disable_trickle_feed(dev);
7119
7120         cpt_init_clock_gating(dev);
7121
7122         gen6_check_mch_setup(dev);
7123 }
7124
7125 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
7126 {
7127         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
7128
7129         /*
7130          * WaVSThreadDispatchOverride:ivb,vlv
7131          *
7132          * This actually overrides the dispatch
7133          * mode for all thread types.
7134          */
7135         reg &= ~GEN7_FF_SCHED_MASK;
7136         reg |= GEN7_FF_TS_SCHED_HW;
7137         reg |= GEN7_FF_VS_SCHED_HW;
7138         reg |= GEN7_FF_DS_SCHED_HW;
7139
7140         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7141 }
7142
7143 static void lpt_init_clock_gating(struct drm_device *dev)
7144 {
7145         struct drm_i915_private *dev_priv = to_i915(dev);
7146
7147         /*
7148          * TODO: this bit should only be enabled when really needed, then
7149          * disabled when not needed anymore in order to save power.
7150          */
7151         if (HAS_PCH_LPT_LP(dev_priv))
7152                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7153                            I915_READ(SOUTH_DSPCLK_GATE_D) |
7154                            PCH_LP_PARTITION_LEVEL_DISABLE);
7155
7156         /* WADPOClockGatingDisable:hsw */
7157         I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7158                    I915_READ(TRANS_CHICKEN1(PIPE_A)) |
7159                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7160 }
7161
7162 static void lpt_suspend_hw(struct drm_device *dev)
7163 {
7164         struct drm_i915_private *dev_priv = to_i915(dev);
7165
7166         if (HAS_PCH_LPT_LP(dev_priv)) {
7167                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7168
7169                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7170                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7171         }
7172 }
7173
7174 static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7175                                    int general_prio_credits,
7176                                    int high_prio_credits)
7177 {
7178         u32 misccpctl;
7179
7180         /* WaTempDisableDOPClkGating:bdw */
7181         misccpctl = I915_READ(GEN7_MISCCPCTL);
7182         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7183
7184         I915_WRITE(GEN8_L3SQCREG1,
7185                    L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7186                    L3_HIGH_PRIO_CREDITS(high_prio_credits));
7187
7188         /*
7189          * Wait at least 100 clocks before re-enabling clock gating.
7190          * See the definition of L3SQCREG1 in BSpec.
7191          */
7192         POSTING_READ(GEN8_L3SQCREG1);
7193         udelay(1);
7194         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7195 }
7196
7197 static void kabylake_init_clock_gating(struct drm_device *dev)
7198 {
7199         struct drm_i915_private *dev_priv = dev->dev_private;
7200
7201         gen9_init_clock_gating(dev);
7202
7203         /* WaDisableSDEUnitClockGating:kbl */
7204         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7205                 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7206                            GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7207
7208         /* WaDisableGamClockGating:kbl */
7209         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7210                 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7211                            GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
7212
7213         /* WaFbcNukeOnHostModify:kbl */
7214         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7215                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7216 }
7217
7218 static void skylake_init_clock_gating(struct drm_device *dev)
7219 {
7220         struct drm_i915_private *dev_priv = dev->dev_private;
7221
7222         gen9_init_clock_gating(dev);
7223
7224         /* WAC6entrylatency:skl */
7225         I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7226                    FBC_LLC_FULLY_OPEN);
7227
7228         /* WaFbcNukeOnHostModify:skl */
7229         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7230                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7231 }
7232
7233 static void broadwell_init_clock_gating(struct drm_device *dev)
7234 {
7235         struct drm_i915_private *dev_priv = to_i915(dev);
7236         enum pipe pipe;
7237
7238         ilk_init_lp_watermarks(dev);
7239
7240         /* WaSwitchSolVfFArbitrationPriority:bdw */
7241         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7242
7243         /* WaPsrDPAMaskVBlankInSRD:bdw */
7244         I915_WRITE(CHICKEN_PAR1_1,
7245                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7246
7247         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
7248         for_each_pipe(dev_priv, pipe) {
7249                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
7250                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
7251                            BDW_DPRS_MASK_VBLANK_SRD);
7252         }
7253
7254         /* WaVSRefCountFullforceMissDisable:bdw */
7255         /* WaDSRefCountFullforceMissDisable:bdw */
7256         I915_WRITE(GEN7_FF_THREAD_MODE,
7257                    I915_READ(GEN7_FF_THREAD_MODE) &
7258                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7259
7260         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7261                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7262
7263         /* WaDisableSDEUnitClockGating:bdw */
7264         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7265                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7266
7267         /* WaProgramL3SqcReg1Default:bdw */
7268         gen8_set_l3sqc_credits(dev_priv, 30, 2);
7269
7270         /*
7271          * WaGttCachingOffByDefault:bdw
7272          * GTT cache may not work with big pages, so if those
7273          * are ever enabled GTT cache may need to be disabled.
7274          */
7275         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7276
7277         /* WaKVMNotificationOnConfigChange:bdw */
7278         I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7279                    | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7280
7281         lpt_init_clock_gating(dev);
7282 }
7283
7284 static void haswell_init_clock_gating(struct drm_device *dev)
7285 {
7286         struct drm_i915_private *dev_priv = to_i915(dev);
7287
7288         ilk_init_lp_watermarks(dev);
7289
7290         /* L3 caching of data atomics doesn't work -- disable it. */
7291         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7292         I915_WRITE(HSW_ROW_CHICKEN3,
7293                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7294
7295         /* This is required by WaCatErrorRejectionIssue:hsw */
7296         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7297                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7298                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7299
7300         /* WaVSRefCountFullforceMissDisable:hsw */
7301         I915_WRITE(GEN7_FF_THREAD_MODE,
7302                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
7303
7304         /* WaDisable_RenderCache_OperationalFlush:hsw */
7305         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7306
7307         /* enable HiZ Raw Stall Optimization */
7308         I915_WRITE(CACHE_MODE_0_GEN7,
7309                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7310
7311         /* WaDisable4x2SubspanOptimization:hsw */
7312         I915_WRITE(CACHE_MODE_1,
7313                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7314
7315         /*
7316          * BSpec recommends 8x4 when MSAA is used,
7317          * however in practice 16x4 seems fastest.
7318          *
7319          * Note that PS/WM thread counts depend on the WIZ hashing
7320          * disable bit, which we don't touch here, but it's good
7321          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7322          */
7323         I915_WRITE(GEN7_GT_MODE,
7324                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7325
7326         /* WaSampleCChickenBitEnable:hsw */
7327         I915_WRITE(HALF_SLICE_CHICKEN3,
7328                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7329
7330         /* WaSwitchSolVfFArbitrationPriority:hsw */
7331         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7332
7333         /* WaRsPkgCStateDisplayPMReq:hsw */
7334         I915_WRITE(CHICKEN_PAR1_1,
7335                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
7336
7337         lpt_init_clock_gating(dev);
7338 }
7339
7340 static void ivybridge_init_clock_gating(struct drm_device *dev)
7341 {
7342         struct drm_i915_private *dev_priv = to_i915(dev);
7343         uint32_t snpcr;
7344
7345         ilk_init_lp_watermarks(dev);
7346
7347         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
7348
7349         /* WaDisableEarlyCull:ivb */
7350         I915_WRITE(_3D_CHICKEN3,
7351                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7352
7353         /* WaDisableBackToBackFlipFix:ivb */
7354         I915_WRITE(IVB_CHICKEN3,
7355                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7356                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
7357
7358         /* WaDisablePSDDualDispatchEnable:ivb */
7359         if (IS_IVB_GT1(dev_priv))
7360                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7361                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7362
7363         /* WaDisable_RenderCache_OperationalFlush:ivb */
7364         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7365
7366         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
7367         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7368                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7369
7370         /* WaApplyL3ControlAndL3ChickenMode:ivb */
7371         I915_WRITE(GEN7_L3CNTLREG1,
7372                         GEN7_WA_FOR_GEN7_L3_CONTROL);
7373         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
7374                    GEN7_WA_L3_CHICKEN_MODE);
7375         if (IS_IVB_GT1(dev_priv))
7376                 I915_WRITE(GEN7_ROW_CHICKEN2,
7377                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7378         else {
7379                 /* must write both registers */
7380                 I915_WRITE(GEN7_ROW_CHICKEN2,
7381                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7382                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7383                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7384         }
7385
7386         /* WaForceL3Serialization:ivb */
7387         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7388                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7389
7390         /*
7391          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7392          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
7393          */
7394         I915_WRITE(GEN6_UCGCTL2,
7395                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7396
7397         /* This is required by WaCatErrorRejectionIssue:ivb */
7398         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7399                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7400                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7401
7402         g4x_disable_trickle_feed(dev);
7403
7404         gen7_setup_fixed_func_scheduler(dev_priv);
7405
7406         if (0) { /* causes HiZ corruption on ivb:gt1 */
7407                 /* enable HiZ Raw Stall Optimization */
7408                 I915_WRITE(CACHE_MODE_0_GEN7,
7409                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7410         }
7411
7412         /* WaDisable4x2SubspanOptimization:ivb */
7413         I915_WRITE(CACHE_MODE_1,
7414                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7415
7416         /*
7417          * BSpec recommends 8x4 when MSAA is used,
7418          * however in practice 16x4 seems fastest.
7419          *
7420          * Note that PS/WM thread counts depend on the WIZ hashing
7421          * disable bit, which we don't touch here, but it's good
7422          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7423          */
7424         I915_WRITE(GEN7_GT_MODE,
7425                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7426
7427         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7428         snpcr &= ~GEN6_MBC_SNPCR_MASK;
7429         snpcr |= GEN6_MBC_SNPCR_MED;
7430         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
7431
7432         if (!HAS_PCH_NOP(dev_priv))
7433                 cpt_init_clock_gating(dev);
7434
7435         gen6_check_mch_setup(dev);
7436 }
7437
7438 static void valleyview_init_clock_gating(struct drm_device *dev)
7439 {
7440         struct drm_i915_private *dev_priv = to_i915(dev);
7441
7442         /* WaDisableEarlyCull:vlv */
7443         I915_WRITE(_3D_CHICKEN3,
7444                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7445
7446         /* WaDisableBackToBackFlipFix:vlv */
7447         I915_WRITE(IVB_CHICKEN3,
7448                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7449                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
7450
7451         /* WaPsdDispatchEnable:vlv */
7452         /* WaDisablePSDDualDispatchEnable:vlv */
7453         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7454                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7455                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7456
7457         /* WaDisable_RenderCache_OperationalFlush:vlv */
7458         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7459
7460         /* WaForceL3Serialization:vlv */
7461         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7462                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7463
7464         /* WaDisableDopClockGating:vlv */
7465         I915_WRITE(GEN7_ROW_CHICKEN2,
7466                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7467
7468         /* This is required by WaCatErrorRejectionIssue:vlv */
7469         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7470                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7471                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7472
7473         gen7_setup_fixed_func_scheduler(dev_priv);
7474
7475         /*
7476          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7477          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
7478          */
7479         I915_WRITE(GEN6_UCGCTL2,
7480                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7481
7482         /* WaDisableL3Bank2xClockGate:vlv
7483          * Disabling L3 clock gating- MMIO 940c[25] = 1
7484          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7485         I915_WRITE(GEN7_UCGCTL4,
7486                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
7487
7488         /*
7489          * BSpec says this must be set, even though
7490          * WaDisable4x2SubspanOptimization isn't listed for VLV.
7491          */
7492         I915_WRITE(CACHE_MODE_1,
7493                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7494
7495         /*
7496          * BSpec recommends 8x4 when MSAA is used,
7497          * however in practice 16x4 seems fastest.
7498          *
7499          * Note that PS/WM thread counts depend on the WIZ hashing
7500          * disable bit, which we don't touch here, but it's good
7501          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7502          */
7503         I915_WRITE(GEN7_GT_MODE,
7504                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7505
7506         /*
7507          * WaIncreaseL3CreditsForVLVB0:vlv
7508          * This is the hardware default actually.
7509          */
7510         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7511
7512         /*
7513          * WaDisableVLVClockGating_VBIIssue:vlv
7514          * Disable clock gating on th GCFG unit to prevent a delay
7515          * in the reporting of vblank events.
7516          */
7517         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
7518 }
7519
7520 static void cherryview_init_clock_gating(struct drm_device *dev)
7521 {
7522         struct drm_i915_private *dev_priv = to_i915(dev);
7523
7524         /* WaVSRefCountFullforceMissDisable:chv */
7525         /* WaDSRefCountFullforceMissDisable:chv */
7526         I915_WRITE(GEN7_FF_THREAD_MODE,
7527                    I915_READ(GEN7_FF_THREAD_MODE) &
7528                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7529
7530         /* WaDisableSemaphoreAndSyncFlipWait:chv */
7531         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7532                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7533
7534         /* WaDisableCSUnitClockGating:chv */
7535         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7536                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7537
7538         /* WaDisableSDEUnitClockGating:chv */
7539         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7540                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7541
7542         /*
7543          * WaProgramL3SqcReg1Default:chv
7544          * See gfxspecs/Related Documents/Performance Guide/
7545          * LSQC Setting Recommendations.
7546          */
7547         gen8_set_l3sqc_credits(dev_priv, 38, 2);
7548
7549         /*
7550          * GTT cache may not work with big pages, so if those
7551          * are ever enabled GTT cache may need to be disabled.
7552          */
7553         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7554 }
7555
7556 static void g4x_init_clock_gating(struct drm_device *dev)
7557 {
7558         struct drm_i915_private *dev_priv = to_i915(dev);
7559         uint32_t dspclk_gate;
7560
7561         I915_WRITE(RENCLK_GATE_D1, 0);
7562         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7563                    GS_UNIT_CLOCK_GATE_DISABLE |
7564                    CL_UNIT_CLOCK_GATE_DISABLE);
7565         I915_WRITE(RAMCLK_GATE_D, 0);
7566         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7567                 OVRUNIT_CLOCK_GATE_DISABLE |
7568                 OVCUNIT_CLOCK_GATE_DISABLE;
7569         if (IS_GM45(dev_priv))
7570                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7571         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7572
7573         /* WaDisableRenderCachePipelinedFlush */
7574         I915_WRITE(CACHE_MODE_0,
7575                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
7576
7577         /* WaDisable_RenderCache_OperationalFlush:g4x */
7578         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7579
7580         g4x_disable_trickle_feed(dev);
7581 }
7582
7583 static void crestline_init_clock_gating(struct drm_device *dev)
7584 {
7585         struct drm_i915_private *dev_priv = to_i915(dev);
7586
7587         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7588         I915_WRITE(RENCLK_GATE_D2, 0);
7589         I915_WRITE(DSPCLK_GATE_D, 0);
7590         I915_WRITE(RAMCLK_GATE_D, 0);
7591         I915_WRITE16(DEUC, 0);
7592         I915_WRITE(MI_ARB_STATE,
7593                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7594
7595         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7596         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7597 }
7598
7599 static void broadwater_init_clock_gating(struct drm_device *dev)
7600 {
7601         struct drm_i915_private *dev_priv = to_i915(dev);
7602
7603         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7604                    I965_RCC_CLOCK_GATE_DISABLE |
7605                    I965_RCPB_CLOCK_GATE_DISABLE |
7606                    I965_ISC_CLOCK_GATE_DISABLE |
7607                    I965_FBC_CLOCK_GATE_DISABLE);
7608         I915_WRITE(RENCLK_GATE_D2, 0);
7609         I915_WRITE(MI_ARB_STATE,
7610                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7611
7612         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7613         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7614 }
7615
7616 static void gen3_init_clock_gating(struct drm_device *dev)
7617 {
7618         struct drm_i915_private *dev_priv = to_i915(dev);
7619         u32 dstate = I915_READ(D_STATE);
7620
7621         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7622                 DSTATE_DOT_CLOCK_GATING;
7623         I915_WRITE(D_STATE, dstate);
7624
7625         if (IS_PINEVIEW(dev))
7626                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7627
7628         /* IIR "flip pending" means done if this bit is set */
7629         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7630
7631         /* interrupts should cause a wake up from C3 */
7632         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7633
7634         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7635         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7636
7637         I915_WRITE(MI_ARB_STATE,
7638                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7639 }
7640
7641 static void i85x_init_clock_gating(struct drm_device *dev)
7642 {
7643         struct drm_i915_private *dev_priv = to_i915(dev);
7644
7645         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7646
7647         /* interrupts should cause a wake up from C3 */
7648         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7649                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7650
7651         I915_WRITE(MEM_MODE,
7652                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7653 }
7654
7655 static void i830_init_clock_gating(struct drm_device *dev)
7656 {
7657         struct drm_i915_private *dev_priv = to_i915(dev);
7658
7659         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7660
7661         I915_WRITE(MEM_MODE,
7662                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7663                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7664 }
7665
7666 void intel_init_clock_gating(struct drm_device *dev)
7667 {
7668         struct drm_i915_private *dev_priv = to_i915(dev);
7669
7670         dev_priv->display.init_clock_gating(dev);
7671 }
7672
7673 void intel_suspend_hw(struct drm_device *dev)
7674 {
7675         if (HAS_PCH_LPT(to_i915(dev)))
7676                 lpt_suspend_hw(dev);
7677 }
7678
7679 static void nop_init_clock_gating(struct drm_device *dev)
7680 {
7681         DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7682 }
7683
7684 /**
7685  * intel_init_clock_gating_hooks - setup the clock gating hooks
7686  * @dev_priv: device private
7687  *
7688  * Setup the hooks that configure which clocks of a given platform can be
7689  * gated and also apply various GT and display specific workarounds for these
7690  * platforms. Note that some GT specific workarounds are applied separately
7691  * when GPU contexts or batchbuffers start their execution.
7692  */
7693 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7694 {
7695         if (IS_SKYLAKE(dev_priv))
7696                 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
7697         else if (IS_KABYLAKE(dev_priv))
7698                 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
7699         else if (IS_BROXTON(dev_priv))
7700                 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7701         else if (IS_BROADWELL(dev_priv))
7702                 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7703         else if (IS_CHERRYVIEW(dev_priv))
7704                 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7705         else if (IS_HASWELL(dev_priv))
7706                 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7707         else if (IS_IVYBRIDGE(dev_priv))
7708                 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7709         else if (IS_VALLEYVIEW(dev_priv))
7710                 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7711         else if (IS_GEN6(dev_priv))
7712                 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7713         else if (IS_GEN5(dev_priv))
7714                 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7715         else if (IS_G4X(dev_priv))
7716                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7717         else if (IS_CRESTLINE(dev_priv))
7718                 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7719         else if (IS_BROADWATER(dev_priv))
7720                 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7721         else if (IS_GEN3(dev_priv))
7722                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7723         else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7724                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7725         else if (IS_GEN2(dev_priv))
7726                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7727         else {
7728                 MISSING_CASE(INTEL_DEVID(dev_priv));
7729                 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7730         }
7731 }
7732
7733 /* Set up chip specific power management-related functions */
7734 void intel_init_pm(struct drm_device *dev)
7735 {
7736         struct drm_i915_private *dev_priv = to_i915(dev);
7737
7738         intel_fbc_init(dev_priv);
7739
7740         /* For cxsr */
7741         if (IS_PINEVIEW(dev))
7742                 i915_pineview_get_mem_freq(dev);
7743         else if (IS_GEN5(dev_priv))
7744                 i915_ironlake_get_mem_freq(dev);
7745
7746         /* For FIFO watermark updates */
7747         if (INTEL_INFO(dev)->gen >= 9) {
7748                 skl_setup_wm_latency(dev);
7749                 dev_priv->display.update_wm = skl_update_wm;
7750                 dev_priv->display.compute_global_watermarks = skl_compute_wm;
7751         } else if (HAS_PCH_SPLIT(dev_priv)) {
7752                 ilk_setup_wm_latency(dev);
7753
7754                 if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
7755                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7756                     (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] &&
7757                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7758                         dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7759                         dev_priv->display.compute_intermediate_wm =
7760                                 ilk_compute_intermediate_wm;
7761                         dev_priv->display.initial_watermarks =
7762                                 ilk_initial_watermarks;
7763                         dev_priv->display.optimize_watermarks =
7764                                 ilk_optimize_watermarks;
7765                 } else {
7766                         DRM_DEBUG_KMS("Failed to read display plane latency. "
7767                                       "Disable CxSR\n");
7768                 }
7769         } else if (IS_CHERRYVIEW(dev_priv)) {
7770                 vlv_setup_wm_latency(dev);
7771                 dev_priv->display.update_wm = vlv_update_wm;
7772         } else if (IS_VALLEYVIEW(dev_priv)) {
7773                 vlv_setup_wm_latency(dev);
7774                 dev_priv->display.update_wm = vlv_update_wm;
7775         } else if (IS_PINEVIEW(dev)) {
7776                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
7777                                             dev_priv->is_ddr3,
7778                                             dev_priv->fsb_freq,
7779                                             dev_priv->mem_freq)) {
7780                         DRM_INFO("failed to find known CxSR latency "
7781                                  "(found ddr%s fsb freq %d, mem freq %d), "
7782                                  "disabling CxSR\n",
7783                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
7784                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7785                         /* Disable CxSR and never update its watermark again */
7786                         intel_set_memory_cxsr(dev_priv, false);
7787                         dev_priv->display.update_wm = NULL;
7788                 } else
7789                         dev_priv->display.update_wm = pineview_update_wm;
7790         } else if (IS_G4X(dev_priv)) {
7791                 dev_priv->display.update_wm = g4x_update_wm;
7792         } else if (IS_GEN4(dev_priv)) {
7793                 dev_priv->display.update_wm = i965_update_wm;
7794         } else if (IS_GEN3(dev_priv)) {
7795                 dev_priv->display.update_wm = i9xx_update_wm;
7796                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7797         } else if (IS_GEN2(dev_priv)) {
7798                 if (INTEL_INFO(dev)->num_pipes == 1) {
7799                         dev_priv->display.update_wm = i845_update_wm;
7800                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7801                 } else {
7802                         dev_priv->display.update_wm = i9xx_update_wm;
7803                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7804                 }
7805         } else {
7806                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7807         }
7808 }
7809
7810 static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
7811 {
7812         uint32_t flags =
7813                 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7814
7815         switch (flags) {
7816         case GEN6_PCODE_SUCCESS:
7817                 return 0;
7818         case GEN6_PCODE_UNIMPLEMENTED_CMD:
7819         case GEN6_PCODE_ILLEGAL_CMD:
7820                 return -ENXIO;
7821         case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7822         case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7823                 return -EOVERFLOW;
7824         case GEN6_PCODE_TIMEOUT:
7825                 return -ETIMEDOUT;
7826         default:
7827                 MISSING_CASE(flags)
7828                 return 0;
7829         }
7830 }
7831
7832 static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
7833 {
7834         uint32_t flags =
7835                 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7836
7837         switch (flags) {
7838         case GEN6_PCODE_SUCCESS:
7839                 return 0;
7840         case GEN6_PCODE_ILLEGAL_CMD:
7841                 return -ENXIO;
7842         case GEN7_PCODE_TIMEOUT:
7843                 return -ETIMEDOUT;
7844         case GEN7_PCODE_ILLEGAL_DATA:
7845                 return -EINVAL;
7846         case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7847                 return -EOVERFLOW;
7848         default:
7849                 MISSING_CASE(flags);
7850                 return 0;
7851         }
7852 }
7853
7854 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7855 {
7856         int status;
7857
7858         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7859
7860         /* GEN6_PCODE_* are outside of the forcewake domain, we can
7861          * use te fw I915_READ variants to reduce the amount of work
7862          * required when reading/writing.
7863          */
7864
7865         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7866                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7867                 return -EAGAIN;
7868         }
7869
7870         I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7871         I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7872         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7873
7874         if (intel_wait_for_register_fw(dev_priv,
7875                                        GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7876                                        500)) {
7877                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7878                 return -ETIMEDOUT;
7879         }
7880
7881         *val = I915_READ_FW(GEN6_PCODE_DATA);
7882         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7883
7884         if (INTEL_GEN(dev_priv) > 6)
7885                 status = gen7_check_mailbox_status(dev_priv);
7886         else
7887                 status = gen6_check_mailbox_status(dev_priv);
7888
7889         if (status) {
7890                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
7891                                  status);
7892                 return status;
7893         }
7894
7895         return 0;
7896 }
7897
7898 int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
7899                             u32 mbox, u32 val)
7900 {
7901         int status;
7902
7903         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7904
7905         /* GEN6_PCODE_* are outside of the forcewake domain, we can
7906          * use te fw I915_READ variants to reduce the amount of work
7907          * required when reading/writing.
7908          */
7909
7910         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7911                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7912                 return -EAGAIN;
7913         }
7914
7915         I915_WRITE_FW(GEN6_PCODE_DATA, val);
7916         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7917
7918         if (intel_wait_for_register_fw(dev_priv,
7919                                        GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7920                                        500)) {
7921                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7922                 return -ETIMEDOUT;
7923         }
7924
7925         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7926
7927         if (INTEL_GEN(dev_priv) > 6)
7928                 status = gen7_check_mailbox_status(dev_priv);
7929         else
7930                 status = gen6_check_mailbox_status(dev_priv);
7931
7932         if (status) {
7933                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
7934                                  status);
7935                 return status;
7936         }
7937
7938         return 0;
7939 }
7940
7941 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7942 {
7943         /*
7944          * N = val - 0xb7
7945          * Slow = Fast = GPLL ref * N
7946          */
7947         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
7948 }
7949
7950 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7951 {
7952         return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
7953 }
7954
7955 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7956 {
7957         /*
7958          * N = val / 2
7959          * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7960          */
7961         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
7962 }
7963
7964 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7965 {
7966         /* CHV needs even values */
7967         return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
7968 }
7969
7970 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7971 {
7972         if (IS_GEN9(dev_priv))
7973                 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7974                                          GEN9_FREQ_SCALER);
7975         else if (IS_CHERRYVIEW(dev_priv))
7976                 return chv_gpu_freq(dev_priv, val);
7977         else if (IS_VALLEYVIEW(dev_priv))
7978                 return byt_gpu_freq(dev_priv, val);
7979         else
7980                 return val * GT_FREQUENCY_MULTIPLIER;
7981 }
7982
7983 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7984 {
7985         if (IS_GEN9(dev_priv))
7986                 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7987                                          GT_FREQUENCY_MULTIPLIER);
7988         else if (IS_CHERRYVIEW(dev_priv))
7989                 return chv_freq_opcode(dev_priv, val);
7990         else if (IS_VALLEYVIEW(dev_priv))
7991                 return byt_freq_opcode(dev_priv, val);
7992         else
7993                 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
7994 }
7995
7996 struct request_boost {
7997         struct work_struct work;
7998         struct drm_i915_gem_request *req;
7999 };
8000
8001 static void __intel_rps_boost_work(struct work_struct *work)
8002 {
8003         struct request_boost *boost = container_of(work, struct request_boost, work);
8004         struct drm_i915_gem_request *req = boost->req;
8005
8006         if (!i915_gem_request_completed(req))
8007                 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
8008
8009         i915_gem_request_put(req);
8010         kfree(boost);
8011 }
8012
8013 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
8014 {
8015         struct request_boost *boost;
8016
8017         if (req == NULL || INTEL_GEN(req->i915) < 6)
8018                 return;
8019
8020         if (i915_gem_request_completed(req))
8021                 return;
8022
8023         boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
8024         if (boost == NULL)
8025                 return;
8026
8027         boost->req = i915_gem_request_get(req);
8028
8029         INIT_WORK(&boost->work, __intel_rps_boost_work);
8030         queue_work(req->i915->wq, &boost->work);
8031 }
8032
8033 void intel_pm_setup(struct drm_device *dev)
8034 {
8035         struct drm_i915_private *dev_priv = to_i915(dev);
8036
8037         mutex_init(&dev_priv->rps.hw_lock);
8038         spin_lock_init(&dev_priv->rps.client_lock);
8039
8040         INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
8041                           __intel_autoenable_gt_powersave);
8042         INIT_LIST_HEAD(&dev_priv->rps.clients);
8043
8044         dev_priv->pm.suspended = false;
8045         atomic_set(&dev_priv->pm.wakeref_count, 0);
8046         atomic_set(&dev_priv->pm.atomic_seq, 0);
8047 }