drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29 #include "vi.h"
  30 #include "vid.h"
  31
  32 #include "oss/oss_3_0_d.h"
  33 #include "oss/oss_3_0_sh_mask.h"
  34
  35 #include "gmc/gmc_8_1_d.h"
  36 #include "gmc/gmc_8_1_sh_mask.h"
  37
  38 #include "gca/gfx_8_0_d.h"
  39 #include "gca/gfx_8_0_enum.h"
  40 #include "gca/gfx_8_0_sh_mask.h"
  41
  42 #include "bif/bif_5_0_d.h"
  43 #include "bif/bif_5_0_sh_mask.h"
  44
  45 #include "tonga_sdma_pkt_open.h"
  46
  47 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev);
  48 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev);
  49 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  50 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev);
  51
  52 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin");
  53 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin");
  54 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin");
  55 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin");
  56
  57 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  58 {
  59         SDMA0_REGISTER_OFFSET,
  60         SDMA1_REGISTER_OFFSET
  61 };
  62
  63 static const u32 golden_settings_tonga_a11[] =
  64 {
  65         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  66         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
  67         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  68         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  69         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  70         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  71         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
  72         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  73         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  74         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  75 };
  76
  77 static const u32 tonga_mgcg_cgcg_init[] =
  78 {
  79         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
  80         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
  81 };
  82
  83 static const u32 cz_golden_settings_a11[] =
  84 {
  85         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  86         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
  87         mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
  88         mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
  89         mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
  90         mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
  91         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  92         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
  93         mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100,
  94         mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800,
  95         mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100,
  96         mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100,
  97 };
  98
  99 static const u32 cz_mgcg_cgcg_init[] =
 100 {
 101         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
 102         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
 103 };
 104
 105 /*
 106  * sDMA - System DMA
 107  * Starting with CIK, the GPU has new asynchronous
 108  * DMA engines.  These engines are used for compute
 109  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
 110  * and each one supports 1 ring buffer used for gfx
 111  * and 2 queues used for compute.
 112  *
 113  * The programming model is very similar to the CP
 114  * (ring buffer, IBs, etc.), but sDMA has it's own
 115  * packet format that is different from the PM4 format
 116  * used by the CP. sDMA supports copying data, writing
 117  * embedded data, solid fills, and a number of other
 118  * things.  It also has support for tiling/detiling of
 119  * buffers.
 120  */
 121
 122 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
 123 {
 124         switch (adev->asic_type) {
 125         case CHIP_TONGA:
 126                 amdgpu_program_register_sequence(adev,
 127                                                  tonga_mgcg_cgcg_init,
 128                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
 129                 amdgpu_program_register_sequence(adev,
 130                                                  golden_settings_tonga_a11,
 131                                                  (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
 132                 break;
 133         case CHIP_CARRIZO:
 134                 amdgpu_program_register_sequence(adev,
 135                                                  cz_mgcg_cgcg_init,
 136                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
 137                 amdgpu_program_register_sequence(adev,
 138                                                  cz_golden_settings_a11,
 139                                                  (const u32)ARRAY_SIZE(cz_golden_settings_a11));
 140                 break;
 141         default:
 142                 break;
 143         }
 144 }
 145
 146 /**
 147  * sdma_v3_0_init_microcode - load ucode images from disk
 148  *
 149  * @adev: amdgpu_device pointer
 150  *
 151  * Use the firmware interface to load the ucode images into
 152  * the driver (not loaded into hw).
 153  * Returns 0 on success, error on failure.
 154  */
 155 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
 156 {
 157         const char *chip_name;
 158         char fw_name[30];
 159         int err, i;
 160         struct amdgpu_firmware_info *info = NULL;
 161         const struct common_firmware_header *header = NULL;
 162
 163         DRM_DEBUG("\n");
 164
 165         switch (adev->asic_type) {
 166         case CHIP_TONGA:
 167                 chip_name = "tonga";
 168                 break;
 169         case CHIP_CARRIZO:
 170                 chip_name = "carrizo";
 171                 break;
 172         default: BUG();
 173         }
 174
 175         for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
 176                 if (i == 0)
 177                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 178                 else
 179                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 180                 err = request_firmware(&adev->sdma[i].fw, fw_name, adev->dev);
 181                 if (err)
 182                         goto out;
 183                 err = amdgpu_ucode_validate(adev->sdma[i].fw);
 184                 if (err)
 185                         goto out;
 186
 187                 if (adev->firmware.smu_load) {
 188                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 189                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 190                         info->fw = adev->sdma[i].fw;
 191                         header = (const struct common_firmware_header *)info->fw->data;
 192                         adev->firmware.fw_size +=
 193                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 194                 }
 195         }
 196 out:
 197         if (err) {
 198                 printk(KERN_ERR
 199                        "sdma_v3_0: Failed to load firmware \"%s\"\n",
 200                        fw_name);
 201                 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
 202                         release_firmware(adev->sdma[i].fw);
 203                         adev->sdma[i].fw = NULL;
 204                 }
 205         }
 206         return err;
 207 }
 208
 209 /**
 210  * sdma_v3_0_ring_get_rptr - get the current read pointer
 211  *
 212  * @ring: amdgpu ring pointer
 213  *
 214  * Get the current rptr from the hardware (VI+).
 215  */
 216 static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
 217 {
 218         u32 rptr;
 219
 220         /* XXX check if swapping is necessary on BE */
 221         rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2;
 222
 223         return rptr;
 224 }
 225
 226 /**
 227  * sdma_v3_0_ring_get_wptr - get the current write pointer
 228  *
 229  * @ring: amdgpu ring pointer
 230  *
 231  * Get the current wptr from the hardware (VI+).
 232  */
 233 static uint32_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
 234 {
 235         struct amdgpu_device *adev = ring->adev;
 236         u32 wptr;
 237
 238         if (ring->use_doorbell) {
 239                 /* XXX check if swapping is necessary on BE */
 240                 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
 241         } else {
 242                 int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1;
 243
 244                 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
 245         }
 246
 247         return wptr;
 248 }
 249
 250 /**
 251  * sdma_v3_0_ring_set_wptr - commit the write pointer
 252  *
 253  * @ring: amdgpu ring pointer
 254  *
 255  * Write the wptr back to the hardware (VI+).
 256  */
 257 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
 258 {
 259         struct amdgpu_device *adev = ring->adev;
 260
 261         if (ring->use_doorbell) {
 262                 /* XXX check if swapping is necessary on BE */
 263                 adev->wb.wb[ring->wptr_offs] = ring->wptr << 2;
 264                 WDOORBELL32(ring->doorbell_index, ring->wptr << 2);
 265         } else {
 266                 int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1;
 267
 268                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
 269         }
 270 }
 271
 272 /**
 273  * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine
 274  *
 275  * @ring: amdgpu ring pointer
 276  * @ib: IB object to schedule
 277  *
 278  * Schedule an IB in the DMA ring (VI).
 279  */
 280 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
 281                                    struct amdgpu_ib *ib)
 282 {
 283         u32 vmid = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf;
 284         u32 next_rptr = ring->wptr + 5;
 285
 286         while ((next_rptr & 7) != 2)
 287                 next_rptr++;
 288         next_rptr += 6;
 289
 290         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 291                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 292         amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc);
 293         amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
 294         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
 295         amdgpu_ring_write(ring, next_rptr);
 296
 297         /* IB packet must end on a 8 DW boundary */
 298         while ((ring->wptr & 7) != 2)
 299                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_NOP));
 300
 301         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 302                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
 303         /* base must be 32 byte aligned */
 304         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 305         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 306         amdgpu_ring_write(ring, ib->length_dw);
 307         amdgpu_ring_write(ring, 0);
 308         amdgpu_ring_write(ring, 0);
 309
 310 }
 311
 312 /**
 313  * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 314  *
 315  * @ring: amdgpu ring pointer
 316  *
 317  * Emit an hdp flush packet on the requested DMA ring.
 318  */
 319 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 320 {
 321         u32 ref_and_mask = 0;
 322
 323         if (ring == &ring->adev->sdma[0].ring)
 324                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
 325         else
 326                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
 327
 328         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 329                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 330                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 331         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 332         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 333         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 334         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 335         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 336                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 337 }
 338
 339 /**
 340  * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
 341  *
 342  * @ring: amdgpu ring pointer
 343  * @fence: amdgpu fence object
 344  *
 345  * Add a DMA fence packet to the ring to write
 346  * the fence seq number and DMA trap packet to generate
 347  * an interrupt if needed (VI).
 348  */
 349 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 350                                       unsigned flags)
 351 {
 352         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 353         /* write the fence */
 354         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 355         amdgpu_ring_write(ring, lower_32_bits(addr));
 356         amdgpu_ring_write(ring, upper_32_bits(addr));
 357         amdgpu_ring_write(ring, lower_32_bits(seq));
 358
 359         /* optionally write high bits as well */
 360         if (write64bit) {
 361                 addr += 4;
 362                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 363                 amdgpu_ring_write(ring, lower_32_bits(addr));
 364                 amdgpu_ring_write(ring, upper_32_bits(addr));
 365                 amdgpu_ring_write(ring, upper_32_bits(seq));
 366         }
 367
 368         /* generate an interrupt */
 369         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 370         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 371 }
 372
 373
 374 /**
 375  * sdma_v3_0_ring_emit_semaphore - emit a semaphore on the dma ring
 376  *
 377  * @ring: amdgpu_ring structure holding ring information
 378  * @semaphore: amdgpu semaphore object
 379  * @emit_wait: wait or signal semaphore
 380  *
 381  * Add a DMA semaphore packet to the ring wait on or signal
 382  * other rings (VI).
 383  */
 384 static bool sdma_v3_0_ring_emit_semaphore(struct amdgpu_ring *ring,
 385                                           struct amdgpu_semaphore *semaphore,
 386                                           bool emit_wait)
 387 {
 388         u64 addr = semaphore->gpu_addr;
 389         u32 sig = emit_wait ? 0 : 1;
 390
 391         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SEM) |
 392                           SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(sig));
 393         amdgpu_ring_write(ring, lower_32_bits(addr) & 0xfffffff8);
 394         amdgpu_ring_write(ring, upper_32_bits(addr));
 395
 396         return true;
 397 }
 398
 399 /**
 400  * sdma_v3_0_gfx_stop - stop the gfx async dma engines
 401  *
 402  * @adev: amdgpu_device pointer
 403  *
 404  * Stop the gfx async dma ring buffers (VI).
 405  */
 406 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
 407 {
 408         struct amdgpu_ring *sdma0 = &adev->sdma[0].ring;
 409         struct amdgpu_ring *sdma1 = &adev->sdma[1].ring;
 410         u32 rb_cntl, ib_cntl;
 411         int i;
 412
 413         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 414             (adev->mman.buffer_funcs_ring == sdma1))
 415                 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 416
 417         for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
 418                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 419                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 420                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 421                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 422                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 423                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 424         }
 425         sdma0->ready = false;
 426         sdma1->ready = false;
 427 }
 428
 429 /**
 430  * sdma_v3_0_rlc_stop - stop the compute async dma engines
 431  *
 432  * @adev: amdgpu_device pointer
 433  *
 434  * Stop the compute async dma queues (VI).
 435  */
 436 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev)
 437 {
 438         /* XXX todo */
 439 }
 440
 441 /**
 442  * sdma_v3_0_enable - stop the async dma engines
 443  *
 444  * @adev: amdgpu_device pointer
 445  * @enable: enable/disable the DMA MEs.
 446  *
 447  * Halt or unhalt the async dma engines (VI).
 448  */
 449 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
 450 {
 451         u32 f32_cntl;
 452         int i;
 453
 454         if (enable == false) {
 455                 sdma_v3_0_gfx_stop(adev);
 456                 sdma_v3_0_rlc_stop(adev);
 457         }
 458
 459         for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
 460                 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 461                 if (enable)
 462                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
 463                 else
 464                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
 465                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
 466         }
 467 }
 468
 469 /**
 470  * sdma_v3_0_gfx_resume - setup and start the async dma engines
 471  *
 472  * @adev: amdgpu_device pointer
 473  *
 474  * Set up the gfx DMA ring buffers and enable them (VI).
 475  * Returns 0 for success, error for failure.
 476  */
 477 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
 478 {
 479         struct amdgpu_ring *ring;
 480         u32 rb_cntl, ib_cntl;
 481         u32 rb_bufsz;
 482         u32 wb_offset;
 483         u32 doorbell;
 484         int i, j, r;
 485
 486         for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
 487                 ring = &adev->sdma[i].ring;
 488                 wb_offset = (ring->rptr_offs * 4);
 489
 490                 mutex_lock(&adev->srbm_mutex);
 491                 for (j = 0; j < 16; j++) {
 492                         vi_srbm_select(adev, 0, 0, 0, j);
 493                         /* SDMA GFX */
 494                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 495                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 496                 }
 497                 vi_srbm_select(adev, 0, 0, 0, 0);
 498                 mutex_unlock(&adev->srbm_mutex);
 499
 500                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 501
 502                 /* Set ring buffer size in dwords */
 503                 rb_bufsz = order_base_2(ring->ring_size / 4);
 504                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 505                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 506 #ifdef __BIG_ENDIAN
 507                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 508                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 509                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 510 #endif
 511                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 512
 513                 /* Initialize the ring buffer's read and write pointers */
 514                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 515                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 516
 517                 /* set the wb address whether it's enabled or not */
 518                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 519                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 520                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 521                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 522
 523                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 524
 525                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 526                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 527
 528                 ring->wptr = 0;
 529                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
 530
 531                 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
 532
 533                 if (ring->use_doorbell) {
 534                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,
 535                                                  OFFSET, ring->doorbell_index);
 536                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 537                 } else {
 538                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 539                 }
 540                 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
 541
 542                 /* enable DMA RB */
 543                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 544                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 545
 546                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 547                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 548 #ifdef __BIG_ENDIAN
 549                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 550 #endif
 551                 /* enable DMA IBs */
 552                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 553
 554                 ring->ready = true;
 555
 556                 r = amdgpu_ring_test_ring(ring);
 557                 if (r) {
 558                         ring->ready = false;
 559                         return r;
 560                 }
 561
 562                 if (adev->mman.buffer_funcs_ring == ring)
 563                         amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
 564         }
 565
 566         return 0;
 567 }
 568
 569 /**
 570  * sdma_v3_0_rlc_resume - setup and start the async dma engines
 571  *
 572  * @adev: amdgpu_device pointer
 573  *
 574  * Set up the compute DMA queues and enable them (VI).
 575  * Returns 0 for success, error for failure.
 576  */
 577 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev)
 578 {
 579         /* XXX todo */
 580         return 0;
 581 }
 582
 583 /**
 584  * sdma_v3_0_load_microcode - load the sDMA ME ucode
 585  *
 586  * @adev: amdgpu_device pointer
 587  *
 588  * Loads the sDMA0/1 ucode.
 589  * Returns 0 for success, -EINVAL if the ucode is not available.
 590  */
 591 static int sdma_v3_0_load_microcode(struct amdgpu_device *adev)
 592 {
 593         const struct sdma_firmware_header_v1_0 *hdr;
 594         const __le32 *fw_data;
 595         u32 fw_size;
 596         int i, j;
 597
 598         if (!adev->sdma[0].fw || !adev->sdma[1].fw)
 599                 return -EINVAL;
 600
 601         /* halt the MEs */
 602         sdma_v3_0_enable(adev, false);
 603
 604         for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
 605                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data;
 606                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 607                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 608                 adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 609
 610                 fw_data = (const __le32 *)
 611                         (adev->sdma[i].fw->data +
 612                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 613                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
 614                 for (j = 0; j < fw_size; j++)
 615                         WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
 616                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma[i].fw_version);
 617         }
 618
 619         return 0;
 620 }
 621
 622 /**
 623  * sdma_v3_0_start - setup and start the async dma engines
 624  *
 625  * @adev: amdgpu_device pointer
 626  *
 627  * Set up the DMA engines and enable them (VI).
 628  * Returns 0 for success, error for failure.
 629  */
 630 static int sdma_v3_0_start(struct amdgpu_device *adev)
 631 {
 632         int r;
 633
 634         if (!adev->firmware.smu_load) {
 635                 r = sdma_v3_0_load_microcode(adev);
 636                 if (r)
 637                         return r;
 638         } else {
 639                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
 640                                                 AMDGPU_UCODE_ID_SDMA0);
 641                 if (r)
 642                         return -EINVAL;
 643                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
 644                                                 AMDGPU_UCODE_ID_SDMA1);
 645                 if (r)
 646                         return -EINVAL;
 647         }
 648
 649         /* unhalt the MEs */
 650         sdma_v3_0_enable(adev, true);
 651
 652         /* start the gfx rings and rlc compute queues */
 653         r = sdma_v3_0_gfx_resume(adev);
 654         if (r)
 655                 return r;
 656         r = sdma_v3_0_rlc_resume(adev);
 657         if (r)
 658                 return r;
 659
 660         return 0;
 661 }
 662
 663 /**
 664  * sdma_v3_0_ring_test_ring - simple async dma engine test
 665  *
 666  * @ring: amdgpu_ring structure holding ring information
 667  *
 668  * Test the DMA engine by writing using it to write an
 669  * value to memory. (VI).
 670  * Returns 0 for success, error for failure.
 671  */
 672 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
 673 {
 674         struct amdgpu_device *adev = ring->adev;
 675         unsigned i;
 676         unsigned index;
 677         int r;
 678         u32 tmp;
 679         u64 gpu_addr;
 680
 681         r = amdgpu_wb_get(adev, &index);
 682         if (r) {
 683                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 684                 return r;
 685         }
 686
 687         gpu_addr = adev->wb.gpu_addr + (index * 4);
 688         tmp = 0xCAFEDEAD;
 689         adev->wb.wb[index] = cpu_to_le32(tmp);
 690
 691         r = amdgpu_ring_lock(ring, 5);
 692         if (r) {
 693                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 694                 amdgpu_wb_free(adev, index);
 695                 return r;
 696         }
 697
 698         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 699                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 700         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 701         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 702         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
 703         amdgpu_ring_write(ring, 0xDEADBEEF);
 704         amdgpu_ring_unlock_commit(ring);
 705
 706         for (i = 0; i < adev->usec_timeout; i++) {
 707                 tmp = le32_to_cpu(adev->wb.wb[index]);
 708                 if (tmp == 0xDEADBEEF)
 709                         break;
 710                 DRM_UDELAY(1);
 711         }
 712
 713         if (i < adev->usec_timeout) {
 714                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 715         } else {
 716                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 717                           ring->idx, tmp);
 718                 r = -EINVAL;
 719         }
 720         amdgpu_wb_free(adev, index);
 721
 722         return r;
 723 }
 724
 725 /**
 726  * sdma_v3_0_ring_test_ib - test an IB on the DMA engine
 727  *
 728  * @ring: amdgpu_ring structure holding ring information
 729  *
 730  * Test a simple IB in the DMA ring (VI).
 731  * Returns 0 on success, error on failure.
 732  */
 733 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring)
 734 {
 735         struct amdgpu_device *adev = ring->adev;
 736         struct amdgpu_ib ib;
 737         unsigned i;
 738         unsigned index;
 739         int r;
 740         u32 tmp = 0;
 741         u64 gpu_addr;
 742
 743         r = amdgpu_wb_get(adev, &index);
 744         if (r) {
 745                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 746                 return r;
 747         }
 748
 749         gpu_addr = adev->wb.gpu_addr + (index * 4);
 750         tmp = 0xCAFEDEAD;
 751         adev->wb.wb[index] = cpu_to_le32(tmp);
 752
 753         r = amdgpu_ib_get(ring, NULL, 256, &ib);
 754         if (r) {
 755                 amdgpu_wb_free(adev, index);
 756                 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
 757                 return r;
 758         }
 759
 760         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 761                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 762         ib.ptr[1] = lower_32_bits(gpu_addr);
 763         ib.ptr[2] = upper_32_bits(gpu_addr);
 764         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
 765         ib.ptr[4] = 0xDEADBEEF;
 766         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 767         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 768         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 769         ib.length_dw = 8;
 770
 771         r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED);
 772         if (r) {
 773                 amdgpu_ib_free(adev, &ib);
 774                 amdgpu_wb_free(adev, index);
 775                 DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r);
 776                 return r;
 777         }
 778         r = amdgpu_fence_wait(ib.fence, false);
 779         if (r) {
 780                 amdgpu_ib_free(adev, &ib);
 781                 amdgpu_wb_free(adev, index);
 782                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
 783                 return r;
 784         }
 785         for (i = 0; i < adev->usec_timeout; i++) {
 786                 tmp = le32_to_cpu(adev->wb.wb[index]);
 787                 if (tmp == 0xDEADBEEF)
 788                         break;
 789                 DRM_UDELAY(1);
 790         }
 791         if (i < adev->usec_timeout) {
 792                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
 793                          ib.fence->ring->idx, i);
 794         } else {
 795                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
 796                 r = -EINVAL;
 797         }
 798         amdgpu_ib_free(adev, &ib);
 799         amdgpu_wb_free(adev, index);
 800         return r;
 801 }
 802
 803 /**
 804  * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART
 805  *
 806  * @ib: indirect buffer to fill with commands
 807  * @pe: addr of the page entry
 808  * @src: src addr to copy from
 809  * @count: number of page entries to update
 810  *
 811  * Update PTEs by copying them from the GART using sDMA (CIK).
 812  */
 813 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
 814                                   uint64_t pe, uint64_t src,
 815                                   unsigned count)
 816 {
 817         while (count) {
 818                 unsigned bytes = count * 8;
 819                 if (bytes > 0x1FFFF8)
 820                         bytes = 0x1FFFF8;
 821
 822                 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
 823                         SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 824                 ib->ptr[ib->length_dw++] = bytes;
 825                 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 826                 ib->ptr[ib->length_dw++] = lower_32_bits(src);
 827                 ib->ptr[ib->length_dw++] = upper_32_bits(src);
 828                 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 829                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 830
 831                 pe += bytes;
 832                 src += bytes;
 833                 count -= bytes / 8;
 834         }
 835 }
 836
 837 /**
 838  * sdma_v3_0_vm_write_pte - update PTEs by writing them manually
 839  *
 840  * @ib: indirect buffer to fill with commands
 841  * @pe: addr of the page entry
 842  * @addr: dst addr to write into pe
 843  * @count: number of page entries to update
 844  * @incr: increase next addr by incr bytes
 845  * @flags: access flags
 846  *
 847  * Update PTEs by writing them manually using sDMA (CIK).
 848  */
 849 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib,
 850                                    uint64_t pe,
 851                                    uint64_t addr, unsigned count,
 852                                    uint32_t incr, uint32_t flags)
 853 {
 854         uint64_t value;
 855         unsigned ndw;
 856
 857         while (count) {
 858                 ndw = count * 2;
 859                 if (ndw > 0xFFFFE)
 860                         ndw = 0xFFFFE;
 861
 862                 /* for non-physically contiguous pages (system) */
 863                 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 864                         SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 865                 ib->ptr[ib->length_dw++] = pe;
 866                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 867                 ib->ptr[ib->length_dw++] = ndw;
 868                 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
 869                         if (flags & AMDGPU_PTE_SYSTEM) {
 870                                 value = amdgpu_vm_map_gart(ib->ring->adev, addr);
 871                                 value &= 0xFFFFFFFFFFFFF000ULL;
 872                         } else if (flags & AMDGPU_PTE_VALID) {
 873                                 value = addr;
 874                         } else {
 875                                 value = 0;
 876                         }
 877                         addr += incr;
 878                         value |= flags;
 879                         ib->ptr[ib->length_dw++] = value;
 880                         ib->ptr[ib->length_dw++] = upper_32_bits(value);
 881                 }
 882         }
 883 }
 884
 885 /**
 886  * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA
 887  *
 888  * @ib: indirect buffer to fill with commands
 889  * @pe: addr of the page entry
 890  * @addr: dst addr to write into pe
 891  * @count: number of page entries to update
 892  * @incr: increase next addr by incr bytes
 893  * @flags: access flags
 894  *
 895  * Update the page tables using sDMA (CIK).
 896  */
 897 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib,
 898                                      uint64_t pe,
 899                                      uint64_t addr, unsigned count,
 900                                      uint32_t incr, uint32_t flags)
 901 {
 902         uint64_t value;
 903         unsigned ndw;
 904
 905         while (count) {
 906                 ndw = count;
 907                 if (ndw > 0x7FFFF)
 908                         ndw = 0x7FFFF;
 909
 910                 if (flags & AMDGPU_PTE_VALID)
 911                         value = addr;
 912                 else
 913                         value = 0;
 914
 915                 /* for physically contiguous pages (vram) */
 916                 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
 917                 ib->ptr[ib->length_dw++] = pe; /* dst addr */
 918                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 919                 ib->ptr[ib->length_dw++] = flags; /* mask */
 920                 ib->ptr[ib->length_dw++] = 0;
 921                 ib->ptr[ib->length_dw++] = value; /* value */
 922                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 923                 ib->ptr[ib->length_dw++] = incr; /* increment size */
 924                 ib->ptr[ib->length_dw++] = 0;
 925                 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
 926
 927                 pe += ndw * 8;
 928                 addr += ndw * incr;
 929                 count -= ndw;
 930         }
 931 }
 932
 933 /**
 934  * sdma_v3_0_vm_pad_ib - pad the IB to the required number of dw
 935  *
 936  * @ib: indirect buffer to fill with padding
 937  *
 938  */
 939 static void sdma_v3_0_vm_pad_ib(struct amdgpu_ib *ib)
 940 {
 941         while (ib->length_dw & 0x7)
 942                 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 943 }
 944
 945 /**
 946  * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
 947  *
 948  * @ring: amdgpu_ring pointer
 949  * @vm: amdgpu_vm pointer
 950  *
 951  * Update the page table base and flush the VM TLB
 952  * using sDMA (VI).
 953  */
 954 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
 955                                          unsigned vm_id, uint64_t pd_addr)
 956 {
 957         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 958                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 959         if (vm_id < 8) {
 960                 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
 961         } else {
 962                 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
 963         }
 964         amdgpu_ring_write(ring, pd_addr >> 12);
 965
 966         /* flush TLB */
 967         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 968                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 969         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
 970         amdgpu_ring_write(ring, 1 << vm_id);
 971
 972         /* wait for flush */
 973         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 974                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
 975                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
 976         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
 977         amdgpu_ring_write(ring, 0);
 978         amdgpu_ring_write(ring, 0); /* reference */
 979         amdgpu_ring_write(ring, 0); /* mask */
 980         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 981                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 982 }
 983
 984 static int sdma_v3_0_early_init(void *handle)
 985 {
 986         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 987
 988         sdma_v3_0_set_ring_funcs(adev);
 989         sdma_v3_0_set_buffer_funcs(adev);
 990         sdma_v3_0_set_vm_pte_funcs(adev);
 991         sdma_v3_0_set_irq_funcs(adev);
 992
 993         return 0;
 994 }
 995
 996 static int sdma_v3_0_sw_init(void *handle)
 997 {
 998         struct amdgpu_ring *ring;
 999         int r;
1000         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1001
1002         /* SDMA trap event */
1003         r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq);
1004         if (r)
1005                 return r;
1006
1007         /* SDMA Privileged inst */
1008         r = amdgpu_irq_add_id(adev, 241, &adev->sdma_illegal_inst_irq);
1009         if (r)
1010                 return r;
1011
1012         /* SDMA Privileged inst */
1013         r = amdgpu_irq_add_id(adev, 247, &adev->sdma_illegal_inst_irq);
1014         if (r)
1015                 return r;
1016
1017         r = sdma_v3_0_init_microcode(adev);
1018         if (r) {
1019                 DRM_ERROR("Failed to load sdma firmware!\n");
1020                 return r;
1021         }
1022
1023         ring = &adev->sdma[0].ring;
1024         ring->ring_obj = NULL;
1025         ring->use_doorbell = true;
1026         ring->doorbell_index = AMDGPU_DOORBELL_sDMA_ENGINE0;
1027
1028         ring = &adev->sdma[1].ring;
1029         ring->ring_obj = NULL;
1030         ring->use_doorbell = true;
1031         ring->doorbell_index = AMDGPU_DOORBELL_sDMA_ENGINE1;
1032
1033         ring = &adev->sdma[0].ring;
1034         sprintf(ring->name, "sdma0");
1035         r = amdgpu_ring_init(adev, ring, 256 * 1024,
1036                              SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
1037                              &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP0,
1038                              AMDGPU_RING_TYPE_SDMA);
1039         if (r)
1040                 return r;
1041
1042         ring = &adev->sdma[1].ring;
1043         sprintf(ring->name, "sdma1");
1044         r = amdgpu_ring_init(adev, ring, 256 * 1024,
1045                              SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
1046                              &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP1,
1047                              AMDGPU_RING_TYPE_SDMA);
1048         if (r)
1049                 return r;
1050
1051         return r;
1052 }
1053
1054 static int sdma_v3_0_sw_fini(void *handle)
1055 {
1056         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1057
1058         amdgpu_ring_fini(&adev->sdma[0].ring);
1059         amdgpu_ring_fini(&adev->sdma[1].ring);
1060
1061         return 0;
1062 }
1063
1064 static int sdma_v3_0_hw_init(void *handle)
1065 {
1066         int r;
1067         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1068
1069         sdma_v3_0_init_golden_registers(adev);
1070
1071         r = sdma_v3_0_start(adev);
1072         if (r)
1073                 return r;
1074
1075         return r;
1076 }
1077
1078 static int sdma_v3_0_hw_fini(void *handle)
1079 {
1080         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1081
1082         sdma_v3_0_enable(adev, false);
1083
1084         return 0;
1085 }
1086
1087 static int sdma_v3_0_suspend(void *handle)
1088 {
1089         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1090
1091         return sdma_v3_0_hw_fini(adev);
1092 }
1093
1094 static int sdma_v3_0_resume(void *handle)
1095 {
1096         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1097
1098         return sdma_v3_0_hw_init(adev);
1099 }
1100
1101 static bool sdma_v3_0_is_idle(void *handle)
1102 {
1103         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1104         u32 tmp = RREG32(mmSRBM_STATUS2);
1105
1106         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1107                    SRBM_STATUS2__SDMA1_BUSY_MASK))
1108             return false;
1109
1110         return true;
1111 }
1112
1113 static int sdma_v3_0_wait_for_idle(void *handle)
1114 {
1115         unsigned i;
1116         u32 tmp;
1117         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1118
1119         for (i = 0; i < adev->usec_timeout; i++) {
1120                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1121                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1122
1123                 if (!tmp)
1124                         return 0;
1125                 udelay(1);
1126         }
1127         return -ETIMEDOUT;
1128 }
1129
1130 static void sdma_v3_0_print_status(void *handle)
1131 {
1132         int i, j;
1133         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1134
1135         dev_info(adev->dev, "VI SDMA registers\n");
1136         dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
1137                  RREG32(mmSRBM_STATUS2));
1138         for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
1139                 dev_info(adev->dev, "  SDMA%d_STATUS_REG=0x%08X\n",
1140                          i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
1141                 dev_info(adev->dev, "  SDMA%d_F32_CNTL=0x%08X\n",
1142                          i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
1143                 dev_info(adev->dev, "  SDMA%d_CNTL=0x%08X\n",
1144                          i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
1145                 dev_info(adev->dev, "  SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
1146                          i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
1147                 dev_info(adev->dev, "  SDMA%d_GFX_IB_CNTL=0x%08X\n",
1148                          i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
1149                 dev_info(adev->dev, "  SDMA%d_GFX_RB_CNTL=0x%08X\n",
1150                          i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
1151                 dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR=0x%08X\n",
1152                          i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
1153                 dev_info(adev->dev, "  SDMA%d_GFX_RB_WPTR=0x%08X\n",
1154                          i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
1155                 dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
1156                          i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
1157                 dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
1158                          i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
1159                 dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE=0x%08X\n",
1160                          i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
1161                 dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
1162                          i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
1163                 dev_info(adev->dev, "  SDMA%d_GFX_DOORBELL=0x%08X\n",
1164                          i, RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]));
1165                 mutex_lock(&adev->srbm_mutex);
1166                 for (j = 0; j < 16; j++) {
1167                         vi_srbm_select(adev, 0, 0, 0, j);
1168                         dev_info(adev->dev, "  VM %d:\n", j);
1169                         dev_info(adev->dev, "  SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n",
1170                                  i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
1171                         dev_info(adev->dev, "  SDMA%d_GFX_APE1_CNTL=0x%08X\n",
1172                                  i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
1173                 }
1174                 vi_srbm_select(adev, 0, 0, 0, 0);
1175                 mutex_unlock(&adev->srbm_mutex);
1176         }
1177 }
1178
1179 static int sdma_v3_0_soft_reset(void *handle)
1180 {
1181         u32 srbm_soft_reset = 0;
1182         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1183         u32 tmp = RREG32(mmSRBM_STATUS2);
1184
1185         if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1186                 /* sdma0 */
1187                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1188                 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1189                 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1190                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1191         }
1192         if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1193                 /* sdma1 */
1194                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1195                 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1196                 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1197                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1198         }
1199
1200         if (srbm_soft_reset) {
1201                 sdma_v3_0_print_status((void *)adev);
1202
1203                 tmp = RREG32(mmSRBM_SOFT_RESET);
1204                 tmp |= srbm_soft_reset;
1205                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1206                 WREG32(mmSRBM_SOFT_RESET, tmp);
1207                 tmp = RREG32(mmSRBM_SOFT_RESET);
1208
1209                 udelay(50);
1210
1211                 tmp &= ~srbm_soft_reset;
1212                 WREG32(mmSRBM_SOFT_RESET, tmp);
1213                 tmp = RREG32(mmSRBM_SOFT_RESET);
1214
1215                 /* Wait a little for things to settle down */
1216                 udelay(50);
1217
1218                 sdma_v3_0_print_status((void *)adev);
1219         }
1220
1221         return 0;
1222 }
1223
1224 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev,
1225                                         struct amdgpu_irq_src *source,
1226                                         unsigned type,
1227                                         enum amdgpu_interrupt_state state)
1228 {
1229         u32 sdma_cntl;
1230
1231         switch (type) {
1232         case AMDGPU_SDMA_IRQ_TRAP0:
1233                 switch (state) {
1234                 case AMDGPU_IRQ_STATE_DISABLE:
1235                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1236                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1237                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1238                         break;
1239                 case AMDGPU_IRQ_STATE_ENABLE:
1240                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1241                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1242                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1243                         break;
1244                 default:
1245                         break;
1246                 }
1247                 break;
1248         case AMDGPU_SDMA_IRQ_TRAP1:
1249                 switch (state) {
1250                 case AMDGPU_IRQ_STATE_DISABLE:
1251                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1252                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1253                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1254                         break;
1255                 case AMDGPU_IRQ_STATE_ENABLE:
1256                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1257                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1258                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1259                         break;
1260                 default:
1261                         break;
1262                 }
1263                 break;
1264         default:
1265                 break;
1266         }
1267         return 0;
1268 }
1269
1270 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev,
1271                                       struct amdgpu_irq_src *source,
1272                                       struct amdgpu_iv_entry *entry)
1273 {
1274         u8 instance_id, queue_id;
1275
1276         instance_id = (entry->ring_id & 0x3) >> 0;
1277         queue_id = (entry->ring_id & 0xc) >> 2;
1278         DRM_DEBUG("IH: SDMA trap\n");
1279         switch (instance_id) {
1280         case 0:
1281                 switch (queue_id) {
1282                 case 0:
1283                         amdgpu_fence_process(&adev->sdma[0].ring);
1284                         break;
1285                 case 1:
1286                         /* XXX compute */
1287                         break;
1288                 case 2:
1289                         /* XXX compute */
1290                         break;
1291                 }
1292                 break;
1293         case 1:
1294                 switch (queue_id) {
1295                 case 0:
1296                         amdgpu_fence_process(&adev->sdma[1].ring);
1297                         break;
1298                 case 1:
1299                         /* XXX compute */
1300                         break;
1301                 case 2:
1302                         /* XXX compute */
1303                         break;
1304                 }
1305                 break;
1306         }
1307         return 0;
1308 }
1309
1310 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1311                                               struct amdgpu_irq_src *source,
1312                                               struct amdgpu_iv_entry *entry)
1313 {
1314         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1315         schedule_work(&adev->reset_work);
1316         return 0;
1317 }
1318
1319 static int sdma_v3_0_set_clockgating_state(void *handle,
1320                                           enum amd_clockgating_state state)
1321 {
1322         return 0;
1323 }
1324
1325 static int sdma_v3_0_set_powergating_state(void *handle,
1326                                           enum amd_powergating_state state)
1327 {
1328         return 0;
1329 }
1330
1331 const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
1332         .early_init = sdma_v3_0_early_init,
1333         .late_init = NULL,
1334         .sw_init = sdma_v3_0_sw_init,
1335         .sw_fini = sdma_v3_0_sw_fini,
1336         .hw_init = sdma_v3_0_hw_init,
1337         .hw_fini = sdma_v3_0_hw_fini,
1338         .suspend = sdma_v3_0_suspend,
1339         .resume = sdma_v3_0_resume,
1340         .is_idle = sdma_v3_0_is_idle,
1341         .wait_for_idle = sdma_v3_0_wait_for_idle,
1342         .soft_reset = sdma_v3_0_soft_reset,
1343         .print_status = sdma_v3_0_print_status,
1344         .set_clockgating_state = sdma_v3_0_set_clockgating_state,
1345         .set_powergating_state = sdma_v3_0_set_powergating_state,
1346 };
1347
1348 /**
1349  * sdma_v3_0_ring_is_lockup - Check if the DMA engine is locked up
1350  *
1351  * @ring: amdgpu_ring structure holding ring information
1352  *
1353  * Check if the async DMA engine is locked up (VI).
1354  * Returns true if the engine appears to be locked up, false if not.
1355  */
1356 static bool sdma_v3_0_ring_is_lockup(struct amdgpu_ring *ring)
1357 {
1358
1359         if (sdma_v3_0_is_idle(ring->adev)) {
1360                 amdgpu_ring_lockup_update(ring);
1361                 return false;
1362         }
1363         return amdgpu_ring_test_lockup(ring);
1364 }
1365
1366 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
1367         .get_rptr = sdma_v3_0_ring_get_rptr,
1368         .get_wptr = sdma_v3_0_ring_get_wptr,
1369         .set_wptr = sdma_v3_0_ring_set_wptr,
1370         .parse_cs = NULL,
1371         .emit_ib = sdma_v3_0_ring_emit_ib,
1372         .emit_fence = sdma_v3_0_ring_emit_fence,
1373         .emit_semaphore = sdma_v3_0_ring_emit_semaphore,
1374         .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
1375         .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
1376         .test_ring = sdma_v3_0_ring_test_ring,
1377         .test_ib = sdma_v3_0_ring_test_ib,
1378         .is_lockup = sdma_v3_0_ring_is_lockup,
1379 };
1380
1381 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
1382 {
1383         adev->sdma[0].ring.funcs = &sdma_v3_0_ring_funcs;
1384         adev->sdma[1].ring.funcs = &sdma_v3_0_ring_funcs;
1385 }
1386
1387 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
1388         .set = sdma_v3_0_set_trap_irq_state,
1389         .process = sdma_v3_0_process_trap_irq,
1390 };
1391
1392 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = {
1393         .process = sdma_v3_0_process_illegal_inst_irq,
1394 };
1395
1396 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)
1397 {
1398         adev->sdma_trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1399         adev->sdma_trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;
1400         adev->sdma_illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;
1401 }
1402
1403 /**
1404  * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine
1405  *
1406  * @ring: amdgpu_ring structure holding ring information
1407  * @src_offset: src GPU address
1408  * @dst_offset: dst GPU address
1409  * @byte_count: number of bytes to xfer
1410  *
1411  * Copy GPU buffers using the DMA engine (VI).
1412  * Used by the amdgpu ttm implementation to move pages if
1413  * registered as the asic copy callback.
1414  */
1415 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ring *ring,
1416                                        uint64_t src_offset,
1417                                        uint64_t dst_offset,
1418                                        uint32_t byte_count)
1419 {
1420         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1421                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR));
1422         amdgpu_ring_write(ring, byte_count);
1423         amdgpu_ring_write(ring, 0); /* src/dst endian swap */
1424         amdgpu_ring_write(ring, lower_32_bits(src_offset));
1425         amdgpu_ring_write(ring, upper_32_bits(src_offset));
1426         amdgpu_ring_write(ring, lower_32_bits(dst_offset));
1427         amdgpu_ring_write(ring, upper_32_bits(dst_offset));
1428 }
1429
1430 /**
1431  * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine
1432  *
1433  * @ring: amdgpu_ring structure holding ring information
1434  * @src_data: value to write to buffer
1435  * @dst_offset: dst GPU address
1436  * @byte_count: number of bytes to xfer
1437  *
1438  * Fill GPU buffers using the DMA engine (VI).
1439  */
1440 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ring *ring,
1441                                        uint32_t src_data,
1442                                        uint64_t dst_offset,
1443                                        uint32_t byte_count)
1444 {
1445         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL));
1446         amdgpu_ring_write(ring, lower_32_bits(dst_offset));
1447         amdgpu_ring_write(ring, upper_32_bits(dst_offset));
1448         amdgpu_ring_write(ring, src_data);
1449         amdgpu_ring_write(ring, byte_count);
1450 }
1451
1452 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
1453         .copy_max_bytes = 0x1fffff,
1454         .copy_num_dw = 7,
1455         .emit_copy_buffer = sdma_v3_0_emit_copy_buffer,
1456
1457         .fill_max_bytes = 0x1fffff,
1458         .fill_num_dw = 5,
1459         .emit_fill_buffer = sdma_v3_0_emit_fill_buffer,
1460 };
1461
1462 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
1463 {
1464         if (adev->mman.buffer_funcs == NULL) {
1465                 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
1466                 adev->mman.buffer_funcs_ring = &adev->sdma[0].ring;
1467         }
1468 }
1469
1470 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
1471         .copy_pte = sdma_v3_0_vm_copy_pte,
1472         .write_pte = sdma_v3_0_vm_write_pte,
1473         .set_pte_pde = sdma_v3_0_vm_set_pte_pde,
1474         .pad_ib = sdma_v3_0_vm_pad_ib,
1475 };
1476
1477 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1478 {
1479         if (adev->vm_manager.vm_pte_funcs == NULL) {
1480                 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
1481                 adev->vm_manager.vm_pte_funcs_ring = &adev->sdma[0].ring;
1482         }
1483 }