drivers/gpu/drm/tegra/sor.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013 NVIDIA Corporation
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/debugfs.h>
   9 #include <linux/gpio.h>
  10 #include <linux/io.h>
  11 #include <linux/module.h>
  12 #include <linux/of_device.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/regulator/consumer.h>
  16 #include <linux/reset.h>
  17
  18 #include <soc/tegra/pmc.h>
  19
  20 #include <drm/drm_atomic_helper.h>
  21 #include <drm/drm_debugfs.h>
  22 #include <drm/drm_dp_helper.h>
  23 #include <drm/drm_file.h>
  24 #include <drm/drm_panel.h>
  25 #include <drm/drm_scdc_helper.h>
  26
  27 #include "dc.h"
  28 #include "dp.h"
  29 #include "drm.h"
  30 #include "hda.h"
  31 #include "sor.h"
  32 #include "trace.h"
  33
  34 #define SOR_REKEY 0x38
  35
  36 struct tegra_sor_hdmi_settings {
  37         unsigned long frequency;
  38
  39         u8 vcocap;
  40         u8 filter;
  41         u8 ichpmp;
  42         u8 loadadj;
  43         u8 tmds_termadj;
  44         u8 tx_pu_value;
  45         u8 bg_temp_coef;
  46         u8 bg_vref_level;
  47         u8 avdd10_level;
  48         u8 avdd14_level;
  49         u8 sparepll;
  50
  51         u8 drive_current[4];
  52         u8 preemphasis[4];
  53 };
  54
  55 #if 1
  56 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
  57         {
  58                 .frequency = 54000000,
  59                 .vcocap = 0x0,
  60                 .filter = 0x0,
  61                 .ichpmp = 0x1,
  62                 .loadadj = 0x3,
  63                 .tmds_termadj = 0x9,
  64                 .tx_pu_value = 0x10,
  65                 .bg_temp_coef = 0x3,
  66                 .bg_vref_level = 0x8,
  67                 .avdd10_level = 0x4,
  68                 .avdd14_level = 0x4,
  69                 .sparepll = 0x0,
  70                 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
  71                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  72         }, {
  73                 .frequency = 75000000,
  74                 .vcocap = 0x3,
  75                 .filter = 0x0,
  76                 .ichpmp = 0x1,
  77                 .loadadj = 0x3,
  78                 .tmds_termadj = 0x9,
  79                 .tx_pu_value = 0x40,
  80                 .bg_temp_coef = 0x3,
  81                 .bg_vref_level = 0x8,
  82                 .avdd10_level = 0x4,
  83                 .avdd14_level = 0x4,
  84                 .sparepll = 0x0,
  85                 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
  86                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  87         }, {
  88                 .frequency = 150000000,
  89                 .vcocap = 0x3,
  90                 .filter = 0x0,
  91                 .ichpmp = 0x1,
  92                 .loadadj = 0x3,
  93                 .tmds_termadj = 0x9,
  94                 .tx_pu_value = 0x66,
  95                 .bg_temp_coef = 0x3,
  96                 .bg_vref_level = 0x8,
  97                 .avdd10_level = 0x4,
  98                 .avdd14_level = 0x4,
  99                 .sparepll = 0x0,
 100                 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
 101                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 102         }, {
 103                 .frequency = 300000000,
 104                 .vcocap = 0x3,
 105                 .filter = 0x0,
 106                 .ichpmp = 0x1,
 107                 .loadadj = 0x3,
 108                 .tmds_termadj = 0x9,
 109                 .tx_pu_value = 0x66,
 110                 .bg_temp_coef = 0x3,
 111                 .bg_vref_level = 0xa,
 112                 .avdd10_level = 0x4,
 113                 .avdd14_level = 0x4,
 114                 .sparepll = 0x0,
 115                 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
 116                 .preemphasis = { 0x00, 0x17, 0x17, 0x17 },
 117         }, {
 118                 .frequency = 600000000,
 119                 .vcocap = 0x3,
 120                 .filter = 0x0,
 121                 .ichpmp = 0x1,
 122                 .loadadj = 0x3,
 123                 .tmds_termadj = 0x9,
 124                 .tx_pu_value = 0x66,
 125                 .bg_temp_coef = 0x3,
 126                 .bg_vref_level = 0x8,
 127                 .avdd10_level = 0x4,
 128                 .avdd14_level = 0x4,
 129                 .sparepll = 0x0,
 130                 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
 131                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 132         },
 133 };
 134 #else
 135 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
 136         {
 137                 .frequency = 75000000,
 138                 .vcocap = 0x3,
 139                 .filter = 0x0,
 140                 .ichpmp = 0x1,
 141                 .loadadj = 0x3,
 142                 .tmds_termadj = 0x9,
 143                 .tx_pu_value = 0x40,
 144                 .bg_temp_coef = 0x3,
 145                 .bg_vref_level = 0x8,
 146                 .avdd10_level = 0x4,
 147                 .avdd14_level = 0x4,
 148                 .sparepll = 0x0,
 149                 .drive_current = { 0x29, 0x29, 0x29, 0x29 },
 150                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 151         }, {
 152                 .frequency = 150000000,
 153                 .vcocap = 0x3,
 154                 .filter = 0x0,
 155                 .ichpmp = 0x1,
 156                 .loadadj = 0x3,
 157                 .tmds_termadj = 0x9,
 158                 .tx_pu_value = 0x66,
 159                 .bg_temp_coef = 0x3,
 160                 .bg_vref_level = 0x8,
 161                 .avdd10_level = 0x4,
 162                 .avdd14_level = 0x4,
 163                 .sparepll = 0x0,
 164                 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
 165                 .preemphasis = { 0x01, 0x02, 0x02, 0x02 },
 166         }, {
 167                 .frequency = 300000000,
 168                 .vcocap = 0x3,
 169                 .filter = 0x0,
 170                 .ichpmp = 0x6,
 171                 .loadadj = 0x3,
 172                 .tmds_termadj = 0x9,
 173                 .tx_pu_value = 0x66,
 174                 .bg_temp_coef = 0x3,
 175                 .bg_vref_level = 0xf,
 176                 .avdd10_level = 0x4,
 177                 .avdd14_level = 0x4,
 178                 .sparepll = 0x0,
 179                 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
 180                 .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e },
 181         }, {
 182                 .frequency = 600000000,
 183                 .vcocap = 0x3,
 184                 .filter = 0x0,
 185                 .ichpmp = 0xa,
 186                 .loadadj = 0x3,
 187                 .tmds_termadj = 0xb,
 188                 .tx_pu_value = 0x66,
 189                 .bg_temp_coef = 0x3,
 190                 .bg_vref_level = 0xe,
 191                 .avdd10_level = 0x4,
 192                 .avdd14_level = 0x4,
 193                 .sparepll = 0x0,
 194                 .drive_current = { 0x35, 0x3e, 0x3e, 0x3e },
 195                 .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f },
 196         },
 197 };
 198 #endif
 199
 200 static const struct tegra_sor_hdmi_settings tegra186_sor_hdmi_defaults[] = {
 201         {
 202                 .frequency = 54000000,
 203                 .vcocap = 0,
 204                 .filter = 5,
 205                 .ichpmp = 5,
 206                 .loadadj = 3,
 207                 .tmds_termadj = 0xf,
 208                 .tx_pu_value = 0,
 209                 .bg_temp_coef = 3,
 210                 .bg_vref_level = 8,
 211                 .avdd10_level = 4,
 212                 .avdd14_level = 4,
 213                 .sparepll = 0x54,
 214                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 215                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 216         }, {
 217                 .frequency = 75000000,
 218                 .vcocap = 1,
 219                 .filter = 5,
 220                 .ichpmp = 5,
 221                 .loadadj = 3,
 222                 .tmds_termadj = 0xf,
 223                 .tx_pu_value = 0,
 224                 .bg_temp_coef = 3,
 225                 .bg_vref_level = 8,
 226                 .avdd10_level = 4,
 227                 .avdd14_level = 4,
 228                 .sparepll = 0x44,
 229                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 230                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 231         }, {
 232                 .frequency = 150000000,
 233                 .vcocap = 3,
 234                 .filter = 5,
 235                 .ichpmp = 5,
 236                 .loadadj = 3,
 237                 .tmds_termadj = 15,
 238                 .tx_pu_value = 0x66 /* 0 */,
 239                 .bg_temp_coef = 3,
 240                 .bg_vref_level = 8,
 241                 .avdd10_level = 4,
 242                 .avdd14_level = 4,
 243                 .sparepll = 0x00, /* 0x34 */
 244                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
 245                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 246         }, {
 247                 .frequency = 300000000,
 248                 .vcocap = 3,
 249                 .filter = 5,
 250                 .ichpmp = 5,
 251                 .loadadj = 3,
 252                 .tmds_termadj = 15,
 253                 .tx_pu_value = 64,
 254                 .bg_temp_coef = 3,
 255                 .bg_vref_level = 8,
 256                 .avdd10_level = 4,
 257                 .avdd14_level = 4,
 258                 .sparepll = 0x34,
 259                 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 260                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 261         }, {
 262                 .frequency = 600000000,
 263                 .vcocap = 3,
 264                 .filter = 5,
 265                 .ichpmp = 5,
 266                 .loadadj = 3,
 267                 .tmds_termadj = 12,
 268                 .tx_pu_value = 96,
 269                 .bg_temp_coef = 3,
 270                 .bg_vref_level = 8,
 271                 .avdd10_level = 4,
 272                 .avdd14_level = 4,
 273                 .sparepll = 0x34,
 274                 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 275                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 276         }
 277 };
 278
 279 static const struct tegra_sor_hdmi_settings tegra194_sor_hdmi_defaults[] = {
 280         {
 281                 .frequency = 54000000,
 282                 .vcocap = 0,
 283                 .filter = 5,
 284                 .ichpmp = 5,
 285                 .loadadj = 3,
 286                 .tmds_termadj = 0xf,
 287                 .tx_pu_value = 0,
 288                 .bg_temp_coef = 3,
 289                 .bg_vref_level = 8,
 290                 .avdd10_level = 4,
 291                 .avdd14_level = 4,
 292                 .sparepll = 0x54,
 293                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 294                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 295         }, {
 296                 .frequency = 75000000,
 297                 .vcocap = 1,
 298                 .filter = 5,
 299                 .ichpmp = 5,
 300                 .loadadj = 3,
 301                 .tmds_termadj = 0xf,
 302                 .tx_pu_value = 0,
 303                 .bg_temp_coef = 3,
 304                 .bg_vref_level = 8,
 305                 .avdd10_level = 4,
 306                 .avdd14_level = 4,
 307                 .sparepll = 0x44,
 308                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 309                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 310         }, {
 311                 .frequency = 150000000,
 312                 .vcocap = 3,
 313                 .filter = 5,
 314                 .ichpmp = 5,
 315                 .loadadj = 3,
 316                 .tmds_termadj = 15,
 317                 .tx_pu_value = 0x66 /* 0 */,
 318                 .bg_temp_coef = 3,
 319                 .bg_vref_level = 8,
 320                 .avdd10_level = 4,
 321                 .avdd14_level = 4,
 322                 .sparepll = 0x00, /* 0x34 */
 323                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
 324                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 325         }, {
 326                 .frequency = 300000000,
 327                 .vcocap = 3,
 328                 .filter = 5,
 329                 .ichpmp = 5,
 330                 .loadadj = 3,
 331                 .tmds_termadj = 15,
 332                 .tx_pu_value = 64,
 333                 .bg_temp_coef = 3,
 334                 .bg_vref_level = 8,
 335                 .avdd10_level = 4,
 336                 .avdd14_level = 4,
 337                 .sparepll = 0x34,
 338                 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 339                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 340         }, {
 341                 .frequency = 600000000,
 342                 .vcocap = 3,
 343                 .filter = 5,
 344                 .ichpmp = 5,
 345                 .loadadj = 3,
 346                 .tmds_termadj = 12,
 347                 .tx_pu_value = 96,
 348                 .bg_temp_coef = 3,
 349                 .bg_vref_level = 8,
 350                 .avdd10_level = 4,
 351                 .avdd14_level = 4,
 352                 .sparepll = 0x34,
 353                 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 354                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 355         }
 356 };
 357
 358 struct tegra_sor_regs {
 359         unsigned int head_state0;
 360         unsigned int head_state1;
 361         unsigned int head_state2;
 362         unsigned int head_state3;
 363         unsigned int head_state4;
 364         unsigned int head_state5;
 365         unsigned int pll0;
 366         unsigned int pll1;
 367         unsigned int pll2;
 368         unsigned int pll3;
 369         unsigned int dp_padctl0;
 370         unsigned int dp_padctl2;
 371 };
 372
 373 struct tegra_sor_soc {
 374         bool supports_lvds;
 375         bool supports_hdmi;
 376         bool supports_dp;
 377         bool supports_audio;
 378         bool supports_hdcp;
 379
 380         const struct tegra_sor_regs *regs;
 381         bool has_nvdisplay;
 382
 383         const struct tegra_sor_hdmi_settings *settings;
 384         unsigned int num_settings;
 385
 386         const u8 *xbar_cfg;
 387         const u8 *lane_map;
 388
 389         const u8 (*voltage_swing)[4][4];
 390         const u8 (*pre_emphasis)[4][4];
 391         const u8 (*post_cursor)[4][4];
 392         const u8 (*tx_pu)[4][4];
 393 };
 394
 395 struct tegra_sor;
 396
 397 struct tegra_sor_ops {
 398         const char *name;
 399         int (*probe)(struct tegra_sor *sor);
 400         int (*remove)(struct tegra_sor *sor);
 401         void (*audio_enable)(struct tegra_sor *sor);
 402         void (*audio_disable)(struct tegra_sor *sor);
 403 };
 404
 405 struct tegra_sor {
 406         struct host1x_client client;
 407         struct tegra_output output;
 408         struct device *dev;
 409
 410         const struct tegra_sor_soc *soc;
 411         void __iomem *regs;
 412         unsigned int index;
 413         unsigned int irq;
 414
 415         struct reset_control *rst;
 416         struct clk *clk_parent;
 417         struct clk *clk_safe;
 418         struct clk *clk_out;
 419         struct clk *clk_pad;
 420         struct clk *clk_dp;
 421         struct clk *clk;
 422
 423         u8 xbar_cfg[5];
 424
 425         struct drm_dp_link link;
 426         struct drm_dp_aux *aux;
 427
 428         struct drm_info_list *debugfs_files;
 429
 430         const struct tegra_sor_ops *ops;
 431         enum tegra_io_pad pad;
 432
 433         /* for HDMI 2.0 */
 434         struct tegra_sor_hdmi_settings *settings;
 435         unsigned int num_settings;
 436
 437         struct regulator *avdd_io_supply;
 438         struct regulator *vdd_pll_supply;
 439         struct regulator *hdmi_supply;
 440
 441         struct delayed_work scdc;
 442         bool scdc_enabled;
 443
 444         struct tegra_hda_format format;
 445 };
 446
 447 struct tegra_sor_state {
 448         struct drm_connector_state base;
 449
 450         unsigned int link_speed;
 451         unsigned long pclk;
 452         unsigned int bpc;
 453 };
 454
 455 static inline struct tegra_sor_state *
 456 to_sor_state(struct drm_connector_state *state)
 457 {
 458         return container_of(state, struct tegra_sor_state, base);
 459 }
 460
 461 struct tegra_sor_config {
 462         u32 bits_per_pixel;
 463
 464         u32 active_polarity;
 465         u32 active_count;
 466         u32 tu_size;
 467         u32 active_frac;
 468         u32 watermark;
 469
 470         u32 hblank_symbols;
 471         u32 vblank_symbols;
 472 };
 473
 474 static inline struct tegra_sor *
 475 host1x_client_to_sor(struct host1x_client *client)
 476 {
 477         return container_of(client, struct tegra_sor, client);
 478 }
 479
 480 static inline struct tegra_sor *to_sor(struct tegra_output *output)
 481 {
 482         return container_of(output, struct tegra_sor, output);
 483 }
 484
 485 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset)
 486 {
 487         u32 value = readl(sor->regs + (offset << 2));
 488
 489         trace_sor_readl(sor->dev, offset, value);
 490
 491         return value;
 492 }
 493
 494 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value,
 495                                     unsigned int offset)
 496 {
 497         trace_sor_writel(sor->dev, offset, value);
 498         writel(value, sor->regs + (offset << 2));
 499 }
 500
 501 static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent)
 502 {
 503         int err;
 504
 505         clk_disable_unprepare(sor->clk);
 506
 507         err = clk_set_parent(sor->clk_out, parent);
 508         if (err < 0)
 509                 return err;
 510
 511         err = clk_prepare_enable(sor->clk);
 512         if (err < 0)
 513                 return err;
 514
 515         return 0;
 516 }
 517
 518 struct tegra_clk_sor_pad {
 519         struct clk_hw hw;
 520         struct tegra_sor *sor;
 521 };
 522
 523 static inline struct tegra_clk_sor_pad *to_pad(struct clk_hw *hw)
 524 {
 525         return container_of(hw, struct tegra_clk_sor_pad, hw);
 526 }
 527
 528 static const char * const tegra_clk_sor_pad_parents[2][2] = {
 529         { "pll_d_out0", "pll_dp" },
 530         { "pll_d2_out0", "pll_dp" },
 531 };
 532
 533 /*
 534  * Implementing ->set_parent() here isn't really required because the parent
 535  * will be explicitly selected in the driver code via the DP_CLK_SEL mux in
 536  * the SOR_CLK_CNTRL register. This is primarily for compatibility with the
 537  * Tegra186 and later SoC generations where the BPMP implements this clock
 538  * and doesn't expose the mux via the common clock framework.
 539  */
 540
 541 static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index)
 542 {
 543         struct tegra_clk_sor_pad *pad = to_pad(hw);
 544         struct tegra_sor *sor = pad->sor;
 545         u32 value;
 546
 547         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 548         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
 549
 550         switch (index) {
 551         case 0:
 552                 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
 553                 break;
 554
 555         case 1:
 556                 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
 557                 break;
 558         }
 559
 560         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
 561
 562         return 0;
 563 }
 564
 565 static u8 tegra_clk_sor_pad_get_parent(struct clk_hw *hw)
 566 {
 567         struct tegra_clk_sor_pad *pad = to_pad(hw);
 568         struct tegra_sor *sor = pad->sor;
 569         u8 parent = U8_MAX;
 570         u32 value;
 571
 572         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 573
 574         switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) {
 575         case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK:
 576         case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK:
 577                 parent = 0;
 578                 break;
 579
 580         case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK:
 581         case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK:
 582                 parent = 1;
 583                 break;
 584         }
 585
 586         return parent;
 587 }
 588
 589 static const struct clk_ops tegra_clk_sor_pad_ops = {
 590         .set_parent = tegra_clk_sor_pad_set_parent,
 591         .get_parent = tegra_clk_sor_pad_get_parent,
 592 };
 593
 594 static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor,
 595                                               const char *name)
 596 {
 597         struct tegra_clk_sor_pad *pad;
 598         struct clk_init_data init;
 599         struct clk *clk;
 600
 601         pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL);
 602         if (!pad)
 603                 return ERR_PTR(-ENOMEM);
 604
 605         pad->sor = sor;
 606
 607         init.name = name;
 608         init.flags = 0;
 609         init.parent_names = tegra_clk_sor_pad_parents[sor->index];
 610         init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents[sor->index]);
 611         init.ops = &tegra_clk_sor_pad_ops;
 612
 613         pad->hw.init = &init;
 614
 615         clk = devm_clk_register(sor->dev, &pad->hw);
 616
 617         return clk;
 618 }
 619
 620 static void tegra_sor_filter_rates(struct tegra_sor *sor)
 621 {
 622         struct drm_dp_link *link = &sor->link;
 623         unsigned int i;
 624
 625         /* Tegra only supports RBR, HBR and HBR2 */
 626         for (i = 0; i < link->num_rates; i++) {
 627                 switch (link->rates[i]) {
 628                 case 1620000:
 629                 case 2700000:
 630                 case 5400000:
 631                         break;
 632
 633                 default:
 634                         DRM_DEBUG_KMS("link rate %lu kHz not supported\n",
 635                                       link->rates[i]);
 636                         link->rates[i] = 0;
 637                         break;
 638                 }
 639         }
 640
 641         drm_dp_link_update_rates(link);
 642 }
 643
 644 static int tegra_sor_power_up_lanes(struct tegra_sor *sor, unsigned int lanes)
 645 {
 646         unsigned long timeout;
 647         u32 value;
 648
 649         /*
 650          * Clear or set the PD_TXD bit corresponding to each lane, depending
 651          * on whether it is used or not.
 652          */
 653         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 654
 655         if (lanes <= 2)
 656                 value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |
 657                            SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]));
 658         else
 659                 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |
 660                          SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]);
 661
 662         if (lanes <= 1)
 663                 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);
 664         else
 665                 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);
 666
 667         if (lanes == 0)
 668                 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);
 669         else
 670                 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);
 671
 672         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 673
 674         /* start lane sequencer */
 675         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
 676                 SOR_LANE_SEQ_CTL_POWER_STATE_UP;
 677         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
 678
 679         timeout = jiffies + msecs_to_jiffies(250);
 680
 681         while (time_before(jiffies, timeout)) {
 682                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
 683                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
 684                         break;
 685
 686                 usleep_range(250, 1000);
 687         }
 688
 689         if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
 690                 return -ETIMEDOUT;
 691
 692         return 0;
 693 }
 694
 695 static int tegra_sor_power_down_lanes(struct tegra_sor *sor)
 696 {
 697         unsigned long timeout;
 698         u32 value;
 699
 700         /* power down all lanes */
 701         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 702         value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
 703                    SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2);
 704         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 705
 706         /* start lane sequencer */
 707         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
 708                 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
 709         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
 710
 711         timeout = jiffies + msecs_to_jiffies(250);
 712
 713         while (time_before(jiffies, timeout)) {
 714                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
 715                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
 716                         break;
 717
 718                 usleep_range(25, 100);
 719         }
 720
 721         if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
 722                 return -ETIMEDOUT;
 723
 724         return 0;
 725 }
 726
 727 static void tegra_sor_dp_precharge(struct tegra_sor *sor, unsigned int lanes)
 728 {
 729         u32 value;
 730
 731         /* pre-charge all used lanes */
 732         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 733
 734         if (lanes <= 2)
 735                 value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |
 736                            SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]));
 737         else
 738                 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |
 739                          SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]);
 740
 741         if (lanes <= 1)
 742                 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);
 743         else
 744                 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);
 745
 746         if (lanes == 0)
 747                 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);
 748         else
 749                 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);
 750
 751         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 752
 753         usleep_range(15, 100);
 754
 755         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 756         value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
 757                    SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0);
 758         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 759 }
 760
 761 static void tegra_sor_dp_term_calibrate(struct tegra_sor *sor)
 762 {
 763         u32 mask = 0x08, adj = 0, value;
 764
 765         /* enable pad calibration logic */
 766         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 767         value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
 768         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 769
 770         value = tegra_sor_readl(sor, sor->soc->regs->pll1);
 771         value |= SOR_PLL1_TMDS_TERM;
 772         tegra_sor_writel(sor, value, sor->soc->regs->pll1);
 773
 774         while (mask) {
 775                 adj |= mask;
 776
 777                 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
 778                 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
 779                 value |= SOR_PLL1_TMDS_TERMADJ(adj);
 780                 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
 781
 782                 usleep_range(100, 200);
 783
 784                 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
 785                 if (value & SOR_PLL1_TERM_COMPOUT)
 786                         adj &= ~mask;
 787
 788                 mask >>= 1;
 789         }
 790
 791         value = tegra_sor_readl(sor, sor->soc->regs->pll1);
 792         value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
 793         value |= SOR_PLL1_TMDS_TERMADJ(adj);
 794         tegra_sor_writel(sor, value, sor->soc->regs->pll1);
 795
 796         /* disable pad calibration logic */
 797         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 798         value |= SOR_DP_PADCTL_PAD_CAL_PD;
 799         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 800 }
 801
 802 static int tegra_sor_dp_link_apply_training(struct drm_dp_link *link)
 803 {
 804         struct tegra_sor *sor = container_of(link, struct tegra_sor, link);
 805         u32 voltage_swing = 0, pre_emphasis = 0, post_cursor = 0;
 806         const struct tegra_sor_soc *soc = sor->soc;
 807         u32 pattern = 0, tx_pu = 0, value;
 808         unsigned int i;
 809
 810         for (value = 0, i = 0; i < link->lanes; i++) {
 811                 u8 vs = link->train.request.voltage_swing[i];
 812                 u8 pe = link->train.request.pre_emphasis[i];
 813                 u8 pc = link->train.request.post_cursor[i];
 814                 u8 shift = sor->soc->lane_map[i] << 3;
 815
 816                 voltage_swing |= soc->voltage_swing[pc][vs][pe] << shift;
 817                 pre_emphasis |= soc->pre_emphasis[pc][vs][pe] << shift;
 818                 post_cursor |= soc->post_cursor[pc][vs][pe] << shift;
 819
 820                 if (sor->soc->tx_pu[pc][vs][pe] > tx_pu)
 821                         tx_pu = sor->soc->tx_pu[pc][vs][pe];
 822
 823                 switch (link->train.pattern) {
 824                 case DP_TRAINING_PATTERN_DISABLE:
 825                         value = SOR_DP_TPG_SCRAMBLER_GALIOS |
 826                                 SOR_DP_TPG_PATTERN_NONE;
 827                         break;
 828
 829                 case DP_TRAINING_PATTERN_1:
 830                         value = SOR_DP_TPG_SCRAMBLER_NONE |
 831                                 SOR_DP_TPG_PATTERN_TRAIN1;
 832                         break;
 833
 834                 case DP_TRAINING_PATTERN_2:
 835                         value = SOR_DP_TPG_SCRAMBLER_NONE |
 836                                 SOR_DP_TPG_PATTERN_TRAIN2;
 837                         break;
 838
 839                 case DP_TRAINING_PATTERN_3:
 840                         value = SOR_DP_TPG_SCRAMBLER_NONE |
 841                                 SOR_DP_TPG_PATTERN_TRAIN3;
 842                         break;
 843
 844                 default:
 845                         return -EINVAL;
 846                 }
 847
 848                 if (link->caps.channel_coding)
 849                         value |= SOR_DP_TPG_CHANNEL_CODING;
 850
 851                 pattern = pattern << 8 | value;
 852         }
 853
 854         tegra_sor_writel(sor, voltage_swing, SOR_LANE_DRIVE_CURRENT0);
 855         tegra_sor_writel(sor, pre_emphasis, SOR_LANE_PREEMPHASIS0);
 856
 857         if (link->caps.tps3_supported)
 858                 tegra_sor_writel(sor, post_cursor, SOR_LANE_POSTCURSOR0);
 859
 860         tegra_sor_writel(sor, pattern, SOR_DP_TPG);
 861
 862         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 863         value &= ~SOR_DP_PADCTL_TX_PU_MASK;
 864         value |= SOR_DP_PADCTL_TX_PU_ENABLE;
 865         value |= SOR_DP_PADCTL_TX_PU(tx_pu);
 866         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 867
 868         usleep_range(20, 100);
 869
 870         return 0;
 871 }
 872
 873 static int tegra_sor_dp_link_configure(struct drm_dp_link *link)
 874 {
 875         struct tegra_sor *sor = container_of(link, struct tegra_sor, link);
 876         unsigned int rate, lanes;
 877         u32 value;
 878         int err;
 879
 880         rate = drm_dp_link_rate_to_bw_code(link->rate);
 881         lanes = link->lanes;
 882
 883         /* configure link speed and lane count */
 884         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 885         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
 886         value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
 887         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
 888
 889         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
 890         value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
 891         value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
 892
 893         if (link->caps.enhanced_framing)
 894                 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
 895
 896         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
 897
 898         usleep_range(400, 1000);
 899
 900         /* configure load pulse position adjustment */
 901         value = tegra_sor_readl(sor, sor->soc->regs->pll1);
 902         value &= ~SOR_PLL1_LOADADJ_MASK;
 903
 904         switch (rate) {
 905         case DP_LINK_BW_1_62:
 906                 value |= SOR_PLL1_LOADADJ(0x3);
 907                 break;
 908
 909         case DP_LINK_BW_2_7:
 910                 value |= SOR_PLL1_LOADADJ(0x4);
 911                 break;
 912
 913         case DP_LINK_BW_5_4:
 914                 value |= SOR_PLL1_LOADADJ(0x6);
 915                 break;
 916         }
 917
 918         tegra_sor_writel(sor, value, sor->soc->regs->pll1);
 919
 920         /* use alternate scrambler reset for eDP */
 921         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
 922
 923         if (link->edp == 0)
 924                 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
 925         else
 926                 value |= SOR_DP_SPARE_PANEL_INTERNAL;
 927
 928         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
 929
 930         err = tegra_sor_power_down_lanes(sor);
 931         if (err < 0) {
 932                 dev_err(sor->dev, "failed to power down lanes: %d\n", err);
 933                 return err;
 934         }
 935
 936         /* power up and pre-charge lanes */
 937         err = tegra_sor_power_up_lanes(sor, lanes);
 938         if (err < 0) {
 939                 dev_err(sor->dev, "failed to power up %u lane%s: %d\n",
 940                         lanes, (lanes != 1) ? "s" : "", err);
 941                 return err;
 942         }
 943
 944         tegra_sor_dp_precharge(sor, lanes);
 945
 946         return 0;
 947 }
 948
 949 static const struct drm_dp_link_ops tegra_sor_dp_link_ops = {
 950         .apply_training = tegra_sor_dp_link_apply_training,
 951         .configure = tegra_sor_dp_link_configure,
 952 };
 953
 954 static void tegra_sor_super_update(struct tegra_sor *sor)
 955 {
 956         tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
 957         tegra_sor_writel(sor, 1, SOR_SUPER_STATE0);
 958         tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
 959 }
 960
 961 static void tegra_sor_update(struct tegra_sor *sor)
 962 {
 963         tegra_sor_writel(sor, 0, SOR_STATE0);
 964         tegra_sor_writel(sor, 1, SOR_STATE0);
 965         tegra_sor_writel(sor, 0, SOR_STATE0);
 966 }
 967
 968 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout)
 969 {
 970         u32 value;
 971
 972         value = tegra_sor_readl(sor, SOR_PWM_DIV);
 973         value &= ~SOR_PWM_DIV_MASK;
 974         value |= 0x400; /* period */
 975         tegra_sor_writel(sor, value, SOR_PWM_DIV);
 976
 977         value = tegra_sor_readl(sor, SOR_PWM_CTL);
 978         value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK;
 979         value |= 0x400; /* duty cycle */
 980         value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */
 981         value |= SOR_PWM_CTL_TRIGGER;
 982         tegra_sor_writel(sor, value, SOR_PWM_CTL);
 983
 984         timeout = jiffies + msecs_to_jiffies(timeout);
 985
 986         while (time_before(jiffies, timeout)) {
 987                 value = tegra_sor_readl(sor, SOR_PWM_CTL);
 988                 if ((value & SOR_PWM_CTL_TRIGGER) == 0)
 989                         return 0;
 990
 991                 usleep_range(25, 100);
 992         }
 993
 994         return -ETIMEDOUT;
 995 }
 996
 997 static int tegra_sor_attach(struct tegra_sor *sor)
 998 {
 999         unsigned long value, timeout;
1000
1001         /* wake up in normal mode */
1002         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1003         value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE;
1004         value |= SOR_SUPER_STATE_MODE_NORMAL;
1005         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1006         tegra_sor_super_update(sor);
1007
1008         /* attach */
1009         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1010         value |= SOR_SUPER_STATE_ATTACHED;
1011         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1012         tegra_sor_super_update(sor);
1013
1014         timeout = jiffies + msecs_to_jiffies(250);
1015
1016         while (time_before(jiffies, timeout)) {
1017                 value = tegra_sor_readl(sor, SOR_TEST);
1018                 if ((value & SOR_TEST_ATTACHED) != 0)
1019                         return 0;
1020
1021                 usleep_range(25, 100);
1022         }
1023
1024         return -ETIMEDOUT;
1025 }
1026
1027 static int tegra_sor_wakeup(struct tegra_sor *sor)
1028 {
1029         unsigned long value, timeout;
1030
1031         timeout = jiffies + msecs_to_jiffies(250);
1032
1033         /* wait for head to wake up */
1034         while (time_before(jiffies, timeout)) {
1035                 value = tegra_sor_readl(sor, SOR_TEST);
1036                 value &= SOR_TEST_HEAD_MODE_MASK;
1037
1038                 if (value == SOR_TEST_HEAD_MODE_AWAKE)
1039                         return 0;
1040
1041                 usleep_range(25, 100);
1042         }
1043
1044         return -ETIMEDOUT;
1045 }
1046
1047 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout)
1048 {
1049         u32 value;
1050
1051         value = tegra_sor_readl(sor, SOR_PWR);
1052         value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU;
1053         tegra_sor_writel(sor, value, SOR_PWR);
1054
1055         timeout = jiffies + msecs_to_jiffies(timeout);
1056
1057         while (time_before(jiffies, timeout)) {
1058                 value = tegra_sor_readl(sor, SOR_PWR);
1059                 if ((value & SOR_PWR_TRIGGER) == 0)
1060                         return 0;
1061
1062                 usleep_range(25, 100);
1063         }
1064
1065         return -ETIMEDOUT;
1066 }
1067
1068 struct tegra_sor_params {
1069         /* number of link clocks per line */
1070         unsigned int num_clocks;
1071         /* ratio between input and output */
1072         u64 ratio;
1073         /* precision factor */
1074         u64 precision;
1075
1076         unsigned int active_polarity;
1077         unsigned int active_count;
1078         unsigned int active_frac;
1079         unsigned int tu_size;
1080         unsigned int error;
1081 };
1082
1083 static int tegra_sor_compute_params(struct tegra_sor *sor,
1084                                     struct tegra_sor_params *params,
1085                                     unsigned int tu_size)
1086 {
1087         u64 active_sym, active_count, frac, approx;
1088         u32 active_polarity, active_frac = 0;
1089         const u64 f = params->precision;
1090         s64 error;
1091
1092         active_sym = params->ratio * tu_size;
1093         active_count = div_u64(active_sym, f) * f;
1094         frac = active_sym - active_count;
1095
1096         /* fraction < 0.5 */
1097         if (frac >= (f / 2)) {
1098                 active_polarity = 1;
1099                 frac = f - frac;
1100         } else {
1101                 active_polarity = 0;
1102         }
1103
1104         if (frac != 0) {
1105                 frac = div_u64(f * f,  frac); /* 1/fraction */
1106                 if (frac <= (15 * f)) {
1107                         active_frac = div_u64(frac, f);
1108
1109                         /* round up */
1110                         if (active_polarity)
1111                                 active_frac++;
1112                 } else {
1113                         active_frac = active_polarity ? 1 : 15;
1114                 }
1115         }
1116
1117         if (active_frac == 1)
1118                 active_polarity = 0;
1119
1120         if (active_polarity == 1) {
1121                 if (active_frac) {
1122                         approx = active_count + (active_frac * (f - 1)) * f;
1123                         approx = div_u64(approx, active_frac * f);
1124                 } else {
1125                         approx = active_count + f;
1126                 }
1127         } else {
1128                 if (active_frac)
1129                         approx = active_count + div_u64(f, active_frac);
1130                 else
1131                         approx = active_count;
1132         }
1133
1134         error = div_s64(active_sym - approx, tu_size);
1135         error *= params->num_clocks;
1136
1137         if (error <= 0 && abs(error) < params->error) {
1138                 params->active_count = div_u64(active_count, f);
1139                 params->active_polarity = active_polarity;
1140                 params->active_frac = active_frac;
1141                 params->error = abs(error);
1142                 params->tu_size = tu_size;
1143
1144                 if (error == 0)
1145                         return true;
1146         }
1147
1148         return false;
1149 }
1150
1151 static int tegra_sor_compute_config(struct tegra_sor *sor,
1152                                     const struct drm_display_mode *mode,
1153                                     struct tegra_sor_config *config,
1154                                     struct drm_dp_link *link)
1155 {
1156         const u64 f = 100000, link_rate = link->rate * 1000;
1157         const u64 pclk = mode->clock * 1000;
1158         u64 input, output, watermark, num;
1159         struct tegra_sor_params params;
1160         u32 num_syms_per_line;
1161         unsigned int i;
1162
1163         if (!link_rate || !link->lanes || !pclk || !config->bits_per_pixel)
1164                 return -EINVAL;
1165
1166         input = pclk * config->bits_per_pixel;
1167         output = link_rate * 8 * link->lanes;
1168
1169         if (input >= output)
1170                 return -ERANGE;
1171
1172         memset(&params, 0, sizeof(params));
1173         params.ratio = div64_u64(input * f, output);
1174         params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk);
1175         params.precision = f;
1176         params.error = 64 * f;
1177         params.tu_size = 64;
1178
1179         for (i = params.tu_size; i >= 32; i--)
1180                 if (tegra_sor_compute_params(sor, &params, i))
1181                         break;
1182
1183         if (params.active_frac == 0) {
1184                 config->active_polarity = 0;
1185                 config->active_count = params.active_count;
1186
1187                 if (!params.active_polarity)
1188                         config->active_count--;
1189
1190                 config->tu_size = params.tu_size;
1191                 config->active_frac = 1;
1192         } else {
1193                 config->active_polarity = params.active_polarity;
1194                 config->active_count = params.active_count;
1195                 config->active_frac = params.active_frac;
1196                 config->tu_size = params.tu_size;
1197         }
1198
1199         dev_dbg(sor->dev,
1200                 "polarity: %d active count: %d tu size: %d active frac: %d\n",
1201                 config->active_polarity, config->active_count,
1202                 config->tu_size, config->active_frac);
1203
1204         watermark = params.ratio * config->tu_size * (f - params.ratio);
1205         watermark = div_u64(watermark, f);
1206
1207         watermark = div_u64(watermark + params.error, f);
1208         config->watermark = watermark + (config->bits_per_pixel / 8) + 2;
1209         num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) *
1210                             (link->lanes * 8);
1211
1212         if (config->watermark > 30) {
1213                 config->watermark = 30;
1214                 dev_err(sor->dev,
1215                         "unable to compute TU size, forcing watermark to %u\n",
1216                         config->watermark);
1217         } else if (config->watermark > num_syms_per_line) {
1218                 config->watermark = num_syms_per_line;
1219                 dev_err(sor->dev, "watermark too high, forcing to %u\n",
1220                         config->watermark);
1221         }
1222
1223         /* compute the number of symbols per horizontal blanking interval */
1224         num = ((mode->htotal - mode->hdisplay) - 7) * link_rate;
1225         config->hblank_symbols = div_u64(num, pclk);
1226
1227         if (link->caps.enhanced_framing)
1228                 config->hblank_symbols -= 3;
1229
1230         config->hblank_symbols -= 12 / link->lanes;
1231
1232         /* compute the number of symbols per vertical blanking interval */
1233         num = (mode->hdisplay - 25) * link_rate;
1234         config->vblank_symbols = div_u64(num, pclk);
1235         config->vblank_symbols -= 36 / link->lanes + 4;
1236
1237         dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols,
1238                 config->vblank_symbols);
1239
1240         return 0;
1241 }
1242
1243 static void tegra_sor_apply_config(struct tegra_sor *sor,
1244                                    const struct tegra_sor_config *config)
1245 {
1246         u32 value;
1247
1248         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1249         value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK;
1250         value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size);
1251         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1252
1253         value = tegra_sor_readl(sor, SOR_DP_CONFIG0);
1254         value &= ~SOR_DP_CONFIG_WATERMARK_MASK;
1255         value |= SOR_DP_CONFIG_WATERMARK(config->watermark);
1256
1257         value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK;
1258         value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count);
1259
1260         value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK;
1261         value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac);
1262
1263         if (config->active_polarity)
1264                 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1265         else
1266                 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1267
1268         value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE;
1269         value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE;
1270         tegra_sor_writel(sor, value, SOR_DP_CONFIG0);
1271
1272         value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1273         value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK;
1274         value |= config->hblank_symbols & 0xffff;
1275         tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1276
1277         value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1278         value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK;
1279         value |= config->vblank_symbols & 0xffff;
1280         tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1281 }
1282
1283 static void tegra_sor_mode_set(struct tegra_sor *sor,
1284                                const struct drm_display_mode *mode,
1285                                struct tegra_sor_state *state)
1286 {
1287         struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc);
1288         unsigned int vbe, vse, hbe, hse, vbs, hbs;
1289         u32 value;
1290
1291         value = tegra_sor_readl(sor, SOR_STATE1);
1292         value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK;
1293         value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1294         value &= ~SOR_STATE_ASY_OWNER_MASK;
1295
1296         value |= SOR_STATE_ASY_CRC_MODE_COMPLETE |
1297                  SOR_STATE_ASY_OWNER(dc->pipe + 1);
1298
1299         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1300                 value &= ~SOR_STATE_ASY_HSYNCPOL;
1301
1302         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1303                 value |= SOR_STATE_ASY_HSYNCPOL;
1304
1305         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1306                 value &= ~SOR_STATE_ASY_VSYNCPOL;
1307
1308         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1309                 value |= SOR_STATE_ASY_VSYNCPOL;
1310
1311         switch (state->bpc) {
1312         case 16:
1313                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444;
1314                 break;
1315
1316         case 12:
1317                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444;
1318                 break;
1319
1320         case 10:
1321                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444;
1322                 break;
1323
1324         case 8:
1325                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1326                 break;
1327
1328         case 6:
1329                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444;
1330                 break;
1331
1332         default:
1333                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1334                 break;
1335         }
1336
1337         tegra_sor_writel(sor, value, SOR_STATE1);
1338
1339         /*
1340          * TODO: The video timing programming below doesn't seem to match the
1341          * register definitions.
1342          */
1343
1344         value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
1345         tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe);
1346
1347         /* sync end = sync width - 1 */
1348         vse = mode->vsync_end - mode->vsync_start - 1;
1349         hse = mode->hsync_end - mode->hsync_start - 1;
1350
1351         value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
1352         tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe);
1353
1354         /* blank end = sync end + back porch */
1355         vbe = vse + (mode->vtotal - mode->vsync_end);
1356         hbe = hse + (mode->htotal - mode->hsync_end);
1357
1358         value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
1359         tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe);
1360
1361         /* blank start = blank end + active */
1362         vbs = vbe + mode->vdisplay;
1363         hbs = hbe + mode->hdisplay;
1364
1365         value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
1366         tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe);
1367
1368         /* XXX interlacing support */
1369         tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe);
1370 }
1371
1372 static int tegra_sor_detach(struct tegra_sor *sor)
1373 {
1374         unsigned long value, timeout;
1375
1376         /* switch to safe mode */
1377         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1378         value &= ~SOR_SUPER_STATE_MODE_NORMAL;
1379         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1380         tegra_sor_super_update(sor);
1381
1382         timeout = jiffies + msecs_to_jiffies(250);
1383
1384         while (time_before(jiffies, timeout)) {
1385                 value = tegra_sor_readl(sor, SOR_PWR);
1386                 if (value & SOR_PWR_MODE_SAFE)
1387                         break;
1388         }
1389
1390         if ((value & SOR_PWR_MODE_SAFE) == 0)
1391                 return -ETIMEDOUT;
1392
1393         /* go to sleep */
1394         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1395         value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK;
1396         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1397         tegra_sor_super_update(sor);
1398
1399         /* detach */
1400         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1401         value &= ~SOR_SUPER_STATE_ATTACHED;
1402         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1403         tegra_sor_super_update(sor);
1404
1405         timeout = jiffies + msecs_to_jiffies(250);
1406
1407         while (time_before(jiffies, timeout)) {
1408                 value = tegra_sor_readl(sor, SOR_TEST);
1409                 if ((value & SOR_TEST_ATTACHED) == 0)
1410                         break;
1411
1412                 usleep_range(25, 100);
1413         }
1414
1415         if ((value & SOR_TEST_ATTACHED) != 0)
1416                 return -ETIMEDOUT;
1417
1418         return 0;
1419 }
1420
1421 static int tegra_sor_power_down(struct tegra_sor *sor)
1422 {
1423         unsigned long value, timeout;
1424         int err;
1425
1426         value = tegra_sor_readl(sor, SOR_PWR);
1427         value &= ~SOR_PWR_NORMAL_STATE_PU;
1428         value |= SOR_PWR_TRIGGER;
1429         tegra_sor_writel(sor, value, SOR_PWR);
1430
1431         timeout = jiffies + msecs_to_jiffies(250);
1432
1433         while (time_before(jiffies, timeout)) {
1434                 value = tegra_sor_readl(sor, SOR_PWR);
1435                 if ((value & SOR_PWR_TRIGGER) == 0)
1436                         return 0;
1437
1438                 usleep_range(25, 100);
1439         }
1440
1441         if ((value & SOR_PWR_TRIGGER) != 0)
1442                 return -ETIMEDOUT;
1443
1444         /* switch to safe parent clock */
1445         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1446         if (err < 0) {
1447                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1448                 return err;
1449         }
1450
1451         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1452         value |= SOR_PLL2_PORT_POWERDOWN;
1453         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1454
1455         usleep_range(20, 100);
1456
1457         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1458         value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1459         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1460
1461         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1462         value |= SOR_PLL2_SEQ_PLLCAPPD;
1463         value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1464         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1465
1466         usleep_range(20, 100);
1467
1468         return 0;
1469 }
1470
1471 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout)
1472 {
1473         u32 value;
1474
1475         timeout = jiffies + msecs_to_jiffies(timeout);
1476
1477         while (time_before(jiffies, timeout)) {
1478                 value = tegra_sor_readl(sor, SOR_CRCA);
1479                 if (value & SOR_CRCA_VALID)
1480                         return 0;
1481
1482                 usleep_range(100, 200);
1483         }
1484
1485         return -ETIMEDOUT;
1486 }
1487
1488 static int tegra_sor_show_crc(struct seq_file *s, void *data)
1489 {
1490         struct drm_info_node *node = s->private;
1491         struct tegra_sor *sor = node->info_ent->data;
1492         struct drm_crtc *crtc = sor->output.encoder.crtc;
1493         struct drm_device *drm = node->minor->dev;
1494         int err = 0;
1495         u32 value;
1496
1497         drm_modeset_lock_all(drm);
1498
1499         if (!crtc || !crtc->state->active) {
1500                 err = -EBUSY;
1501                 goto unlock;
1502         }
1503
1504         value = tegra_sor_readl(sor, SOR_STATE1);
1505         value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1506         tegra_sor_writel(sor, value, SOR_STATE1);
1507
1508         value = tegra_sor_readl(sor, SOR_CRC_CNTRL);
1509         value |= SOR_CRC_CNTRL_ENABLE;
1510         tegra_sor_writel(sor, value, SOR_CRC_CNTRL);
1511
1512         value = tegra_sor_readl(sor, SOR_TEST);
1513         value &= ~SOR_TEST_CRC_POST_SERIALIZE;
1514         tegra_sor_writel(sor, value, SOR_TEST);
1515
1516         err = tegra_sor_crc_wait(sor, 100);
1517         if (err < 0)
1518                 goto unlock;
1519
1520         tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA);
1521         value = tegra_sor_readl(sor, SOR_CRCB);
1522
1523         seq_printf(s, "%08x\n", value);
1524
1525 unlock:
1526         drm_modeset_unlock_all(drm);
1527         return err;
1528 }
1529
1530 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1531
1532 static const struct debugfs_reg32 tegra_sor_regs[] = {
1533         DEBUGFS_REG32(SOR_CTXSW),
1534         DEBUGFS_REG32(SOR_SUPER_STATE0),
1535         DEBUGFS_REG32(SOR_SUPER_STATE1),
1536         DEBUGFS_REG32(SOR_STATE0),
1537         DEBUGFS_REG32(SOR_STATE1),
1538         DEBUGFS_REG32(SOR_HEAD_STATE0(0)),
1539         DEBUGFS_REG32(SOR_HEAD_STATE0(1)),
1540         DEBUGFS_REG32(SOR_HEAD_STATE1(0)),
1541         DEBUGFS_REG32(SOR_HEAD_STATE1(1)),
1542         DEBUGFS_REG32(SOR_HEAD_STATE2(0)),
1543         DEBUGFS_REG32(SOR_HEAD_STATE2(1)),
1544         DEBUGFS_REG32(SOR_HEAD_STATE3(0)),
1545         DEBUGFS_REG32(SOR_HEAD_STATE3(1)),
1546         DEBUGFS_REG32(SOR_HEAD_STATE4(0)),
1547         DEBUGFS_REG32(SOR_HEAD_STATE4(1)),
1548         DEBUGFS_REG32(SOR_HEAD_STATE5(0)),
1549         DEBUGFS_REG32(SOR_HEAD_STATE5(1)),
1550         DEBUGFS_REG32(SOR_CRC_CNTRL),
1551         DEBUGFS_REG32(SOR_DP_DEBUG_MVID),
1552         DEBUGFS_REG32(SOR_CLK_CNTRL),
1553         DEBUGFS_REG32(SOR_CAP),
1554         DEBUGFS_REG32(SOR_PWR),
1555         DEBUGFS_REG32(SOR_TEST),
1556         DEBUGFS_REG32(SOR_PLL0),
1557         DEBUGFS_REG32(SOR_PLL1),
1558         DEBUGFS_REG32(SOR_PLL2),
1559         DEBUGFS_REG32(SOR_PLL3),
1560         DEBUGFS_REG32(SOR_CSTM),
1561         DEBUGFS_REG32(SOR_LVDS),
1562         DEBUGFS_REG32(SOR_CRCA),
1563         DEBUGFS_REG32(SOR_CRCB),
1564         DEBUGFS_REG32(SOR_BLANK),
1565         DEBUGFS_REG32(SOR_SEQ_CTL),
1566         DEBUGFS_REG32(SOR_LANE_SEQ_CTL),
1567         DEBUGFS_REG32(SOR_SEQ_INST(0)),
1568         DEBUGFS_REG32(SOR_SEQ_INST(1)),
1569         DEBUGFS_REG32(SOR_SEQ_INST(2)),
1570         DEBUGFS_REG32(SOR_SEQ_INST(3)),
1571         DEBUGFS_REG32(SOR_SEQ_INST(4)),
1572         DEBUGFS_REG32(SOR_SEQ_INST(5)),
1573         DEBUGFS_REG32(SOR_SEQ_INST(6)),
1574         DEBUGFS_REG32(SOR_SEQ_INST(7)),
1575         DEBUGFS_REG32(SOR_SEQ_INST(8)),
1576         DEBUGFS_REG32(SOR_SEQ_INST(9)),
1577         DEBUGFS_REG32(SOR_SEQ_INST(10)),
1578         DEBUGFS_REG32(SOR_SEQ_INST(11)),
1579         DEBUGFS_REG32(SOR_SEQ_INST(12)),
1580         DEBUGFS_REG32(SOR_SEQ_INST(13)),
1581         DEBUGFS_REG32(SOR_SEQ_INST(14)),
1582         DEBUGFS_REG32(SOR_SEQ_INST(15)),
1583         DEBUGFS_REG32(SOR_PWM_DIV),
1584         DEBUGFS_REG32(SOR_PWM_CTL),
1585         DEBUGFS_REG32(SOR_VCRC_A0),
1586         DEBUGFS_REG32(SOR_VCRC_A1),
1587         DEBUGFS_REG32(SOR_VCRC_B0),
1588         DEBUGFS_REG32(SOR_VCRC_B1),
1589         DEBUGFS_REG32(SOR_CCRC_A0),
1590         DEBUGFS_REG32(SOR_CCRC_A1),
1591         DEBUGFS_REG32(SOR_CCRC_B0),
1592         DEBUGFS_REG32(SOR_CCRC_B1),
1593         DEBUGFS_REG32(SOR_EDATA_A0),
1594         DEBUGFS_REG32(SOR_EDATA_A1),
1595         DEBUGFS_REG32(SOR_EDATA_B0),
1596         DEBUGFS_REG32(SOR_EDATA_B1),
1597         DEBUGFS_REG32(SOR_COUNT_A0),
1598         DEBUGFS_REG32(SOR_COUNT_A1),
1599         DEBUGFS_REG32(SOR_COUNT_B0),
1600         DEBUGFS_REG32(SOR_COUNT_B1),
1601         DEBUGFS_REG32(SOR_DEBUG_A0),
1602         DEBUGFS_REG32(SOR_DEBUG_A1),
1603         DEBUGFS_REG32(SOR_DEBUG_B0),
1604         DEBUGFS_REG32(SOR_DEBUG_B1),
1605         DEBUGFS_REG32(SOR_TRIG),
1606         DEBUGFS_REG32(SOR_MSCHECK),
1607         DEBUGFS_REG32(SOR_XBAR_CTRL),
1608         DEBUGFS_REG32(SOR_XBAR_POL),
1609         DEBUGFS_REG32(SOR_DP_LINKCTL0),
1610         DEBUGFS_REG32(SOR_DP_LINKCTL1),
1611         DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT0),
1612         DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT1),
1613         DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT0),
1614         DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT1),
1615         DEBUGFS_REG32(SOR_LANE_PREEMPHASIS0),
1616         DEBUGFS_REG32(SOR_LANE_PREEMPHASIS1),
1617         DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS0),
1618         DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS1),
1619         DEBUGFS_REG32(SOR_LANE_POSTCURSOR0),
1620         DEBUGFS_REG32(SOR_LANE_POSTCURSOR1),
1621         DEBUGFS_REG32(SOR_DP_CONFIG0),
1622         DEBUGFS_REG32(SOR_DP_CONFIG1),
1623         DEBUGFS_REG32(SOR_DP_MN0),
1624         DEBUGFS_REG32(SOR_DP_MN1),
1625         DEBUGFS_REG32(SOR_DP_PADCTL0),
1626         DEBUGFS_REG32(SOR_DP_PADCTL1),
1627         DEBUGFS_REG32(SOR_DP_PADCTL2),
1628         DEBUGFS_REG32(SOR_DP_DEBUG0),
1629         DEBUGFS_REG32(SOR_DP_DEBUG1),
1630         DEBUGFS_REG32(SOR_DP_SPARE0),
1631         DEBUGFS_REG32(SOR_DP_SPARE1),
1632         DEBUGFS_REG32(SOR_DP_AUDIO_CTRL),
1633         DEBUGFS_REG32(SOR_DP_AUDIO_HBLANK_SYMBOLS),
1634         DEBUGFS_REG32(SOR_DP_AUDIO_VBLANK_SYMBOLS),
1635         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_HEADER),
1636         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK0),
1637         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK1),
1638         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK2),
1639         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK3),
1640         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK4),
1641         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK5),
1642         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK6),
1643         DEBUGFS_REG32(SOR_DP_TPG),
1644         DEBUGFS_REG32(SOR_DP_TPG_CONFIG),
1645         DEBUGFS_REG32(SOR_DP_LQ_CSTM0),
1646         DEBUGFS_REG32(SOR_DP_LQ_CSTM1),
1647         DEBUGFS_REG32(SOR_DP_LQ_CSTM2),
1648 };
1649
1650 static int tegra_sor_show_regs(struct seq_file *s, void *data)
1651 {
1652         struct drm_info_node *node = s->private;
1653         struct tegra_sor *sor = node->info_ent->data;
1654         struct drm_crtc *crtc = sor->output.encoder.crtc;
1655         struct drm_device *drm = node->minor->dev;
1656         unsigned int i;
1657         int err = 0;
1658
1659         drm_modeset_lock_all(drm);
1660
1661         if (!crtc || !crtc->state->active) {
1662                 err = -EBUSY;
1663                 goto unlock;
1664         }
1665
1666         for (i = 0; i < ARRAY_SIZE(tegra_sor_regs); i++) {
1667                 unsigned int offset = tegra_sor_regs[i].offset;
1668
1669                 seq_printf(s, "%-38s %#05x %08x\n", tegra_sor_regs[i].name,
1670                            offset, tegra_sor_readl(sor, offset));
1671         }
1672
1673 unlock:
1674         drm_modeset_unlock_all(drm);
1675         return err;
1676 }
1677
1678 static const struct drm_info_list debugfs_files[] = {
1679         { "crc", tegra_sor_show_crc, 0, NULL },
1680         { "regs", tegra_sor_show_regs, 0, NULL },
1681 };
1682
1683 static int tegra_sor_late_register(struct drm_connector *connector)
1684 {
1685         struct tegra_output *output = connector_to_output(connector);
1686         unsigned int i, count = ARRAY_SIZE(debugfs_files);
1687         struct drm_minor *minor = connector->dev->primary;
1688         struct dentry *root = connector->debugfs_entry;
1689         struct tegra_sor *sor = to_sor(output);
1690         int err;
1691
1692         sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1693                                      GFP_KERNEL);
1694         if (!sor->debugfs_files)
1695                 return -ENOMEM;
1696
1697         for (i = 0; i < count; i++)
1698                 sor->debugfs_files[i].data = sor;
1699
1700         err = drm_debugfs_create_files(sor->debugfs_files, count, root, minor);
1701         if (err < 0)
1702                 goto free;
1703
1704         return 0;
1705
1706 free:
1707         kfree(sor->debugfs_files);
1708         sor->debugfs_files = NULL;
1709
1710         return err;
1711 }
1712
1713 static void tegra_sor_early_unregister(struct drm_connector *connector)
1714 {
1715         struct tegra_output *output = connector_to_output(connector);
1716         unsigned int count = ARRAY_SIZE(debugfs_files);
1717         struct tegra_sor *sor = to_sor(output);
1718
1719         drm_debugfs_remove_files(sor->debugfs_files, count,
1720                                  connector->dev->primary);
1721         kfree(sor->debugfs_files);
1722         sor->debugfs_files = NULL;
1723 }
1724
1725 static void tegra_sor_connector_reset(struct drm_connector *connector)
1726 {
1727         struct tegra_sor_state *state;
1728
1729         state = kzalloc(sizeof(*state), GFP_KERNEL);
1730         if (!state)
1731                 return;
1732
1733         if (connector->state) {
1734                 __drm_atomic_helper_connector_destroy_state(connector->state);
1735                 kfree(connector->state);
1736         }
1737
1738         __drm_atomic_helper_connector_reset(connector, &state->base);
1739 }
1740
1741 static enum drm_connector_status
1742 tegra_sor_connector_detect(struct drm_connector *connector, bool force)
1743 {
1744         struct tegra_output *output = connector_to_output(connector);
1745         struct tegra_sor *sor = to_sor(output);
1746
1747         if (sor->aux)
1748                 return drm_dp_aux_detect(sor->aux);
1749
1750         return tegra_output_connector_detect(connector, force);
1751 }
1752
1753 static struct drm_connector_state *
1754 tegra_sor_connector_duplicate_state(struct drm_connector *connector)
1755 {
1756         struct tegra_sor_state *state = to_sor_state(connector->state);
1757         struct tegra_sor_state *copy;
1758
1759         copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
1760         if (!copy)
1761                 return NULL;
1762
1763         __drm_atomic_helper_connector_duplicate_state(connector, &copy->base);
1764
1765         return &copy->base;
1766 }
1767
1768 static const struct drm_connector_funcs tegra_sor_connector_funcs = {
1769         .reset = tegra_sor_connector_reset,
1770         .detect = tegra_sor_connector_detect,
1771         .fill_modes = drm_helper_probe_single_connector_modes,
1772         .destroy = tegra_output_connector_destroy,
1773         .atomic_duplicate_state = tegra_sor_connector_duplicate_state,
1774         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1775         .late_register = tegra_sor_late_register,
1776         .early_unregister = tegra_sor_early_unregister,
1777 };
1778
1779 static int tegra_sor_connector_get_modes(struct drm_connector *connector)
1780 {
1781         struct tegra_output *output = connector_to_output(connector);
1782         struct tegra_sor *sor = to_sor(output);
1783         int err;
1784
1785         if (sor->aux)
1786                 drm_dp_aux_enable(sor->aux);
1787
1788         err = tegra_output_connector_get_modes(connector);
1789
1790         if (sor->aux)
1791                 drm_dp_aux_disable(sor->aux);
1792
1793         return err;
1794 }
1795
1796 static enum drm_mode_status
1797 tegra_sor_connector_mode_valid(struct drm_connector *connector,
1798                                struct drm_display_mode *mode)
1799 {
1800         return MODE_OK;
1801 }
1802
1803 static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = {
1804         .get_modes = tegra_sor_connector_get_modes,
1805         .mode_valid = tegra_sor_connector_mode_valid,
1806 };
1807
1808 static const struct drm_encoder_funcs tegra_sor_encoder_funcs = {
1809         .destroy = tegra_output_encoder_destroy,
1810 };
1811
1812 static int
1813 tegra_sor_encoder_atomic_check(struct drm_encoder *encoder,
1814                                struct drm_crtc_state *crtc_state,
1815                                struct drm_connector_state *conn_state)
1816 {
1817         struct tegra_output *output = encoder_to_output(encoder);
1818         struct tegra_sor_state *state = to_sor_state(conn_state);
1819         struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1820         unsigned long pclk = crtc_state->mode.clock * 1000;
1821         struct tegra_sor *sor = to_sor(output);
1822         struct drm_display_info *info;
1823         int err;
1824
1825         info = &output->connector.display_info;
1826
1827         /*
1828          * For HBR2 modes, the SOR brick needs to use the x20 multiplier, so
1829          * the pixel clock must be corrected accordingly.
1830          */
1831         if (pclk >= 340000000) {
1832                 state->link_speed = 20;
1833                 state->pclk = pclk / 2;
1834         } else {
1835                 state->link_speed = 10;
1836                 state->pclk = pclk;
1837         }
1838
1839         err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent,
1840                                          pclk, 0);
1841         if (err < 0) {
1842                 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1843                 return err;
1844         }
1845
1846         switch (info->bpc) {
1847         case 8:
1848         case 6:
1849                 state->bpc = info->bpc;
1850                 break;
1851
1852         default:
1853                 DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc);
1854                 state->bpc = 8;
1855                 break;
1856         }
1857
1858         return 0;
1859 }
1860
1861 static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size)
1862 {
1863         u32 value = 0;
1864         size_t i;
1865
1866         for (i = size; i > 0; i--)
1867                 value = (value << 8) | ptr[i - 1];
1868
1869         return value;
1870 }
1871
1872 static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor,
1873                                           const void *data, size_t size)
1874 {
1875         const u8 *ptr = data;
1876         unsigned long offset;
1877         size_t i, j;
1878         u32 value;
1879
1880         switch (ptr[0]) {
1881         case HDMI_INFOFRAME_TYPE_AVI:
1882                 offset = SOR_HDMI_AVI_INFOFRAME_HEADER;
1883                 break;
1884
1885         case HDMI_INFOFRAME_TYPE_AUDIO:
1886                 offset = SOR_HDMI_AUDIO_INFOFRAME_HEADER;
1887                 break;
1888
1889         case HDMI_INFOFRAME_TYPE_VENDOR:
1890                 offset = SOR_HDMI_VSI_INFOFRAME_HEADER;
1891                 break;
1892
1893         default:
1894                 dev_err(sor->dev, "unsupported infoframe type: %02x\n",
1895                         ptr[0]);
1896                 return;
1897         }
1898
1899         value = INFOFRAME_HEADER_TYPE(ptr[0]) |
1900                 INFOFRAME_HEADER_VERSION(ptr[1]) |
1901                 INFOFRAME_HEADER_LEN(ptr[2]);
1902         tegra_sor_writel(sor, value, offset);
1903         offset++;
1904
1905         /*
1906          * Each subpack contains 7 bytes, divided into:
1907          * - subpack_low: bytes 0 - 3
1908          * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
1909          */
1910         for (i = 3, j = 0; i < size; i += 7, j += 8) {
1911                 size_t rem = size - i, num = min_t(size_t, rem, 4);
1912
1913                 value = tegra_sor_hdmi_subpack(&ptr[i], num);
1914                 tegra_sor_writel(sor, value, offset++);
1915
1916                 num = min_t(size_t, rem - num, 3);
1917
1918                 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num);
1919                 tegra_sor_writel(sor, value, offset++);
1920         }
1921 }
1922
1923 static int
1924 tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor,
1925                                    const struct drm_display_mode *mode)
1926 {
1927         u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
1928         struct hdmi_avi_infoframe frame;
1929         u32 value;
1930         int err;
1931
1932         /* disable AVI infoframe */
1933         value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
1934         value &= ~INFOFRAME_CTRL_SINGLE;
1935         value &= ~INFOFRAME_CTRL_OTHER;
1936         value &= ~INFOFRAME_CTRL_ENABLE;
1937         tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
1938
1939         err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
1940                                                        &sor->output.connector, mode);
1941         if (err < 0) {
1942                 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
1943                 return err;
1944         }
1945
1946         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1947         if (err < 0) {
1948                 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err);
1949                 return err;
1950         }
1951
1952         tegra_sor_hdmi_write_infopack(sor, buffer, err);
1953
1954         /* enable AVI infoframe */
1955         value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
1956         value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
1957         value |= INFOFRAME_CTRL_ENABLE;
1958         tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
1959
1960         return 0;
1961 }
1962
1963 static void tegra_sor_write_eld(struct tegra_sor *sor)
1964 {
1965         size_t length = drm_eld_size(sor->output.connector.eld), i;
1966
1967         for (i = 0; i < length; i++)
1968                 tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i],
1969                                  SOR_AUDIO_HDA_ELD_BUFWR);
1970
1971         /*
1972          * The HDA codec will always report an ELD buffer size of 96 bytes and
1973          * the HDA codec driver will check that each byte read from the buffer
1974          * is valid. Therefore every byte must be written, even if no 96 bytes
1975          * were parsed from EDID.
1976          */
1977         for (i = length; i < 96; i++)
1978                 tegra_sor_writel(sor, i << 8 | 0, SOR_AUDIO_HDA_ELD_BUFWR);
1979 }
1980
1981 static void tegra_sor_audio_prepare(struct tegra_sor *sor)
1982 {
1983         u32 value;
1984
1985         /*
1986          * Enable and unmask the HDA codec SCRATCH0 register interrupt. This
1987          * is used for interoperability between the HDA codec driver and the
1988          * HDMI/DP driver.
1989          */
1990         value = SOR_INT_CODEC_SCRATCH1 | SOR_INT_CODEC_SCRATCH0;
1991         tegra_sor_writel(sor, value, SOR_INT_ENABLE);
1992         tegra_sor_writel(sor, value, SOR_INT_MASK);
1993
1994         tegra_sor_write_eld(sor);
1995
1996         value = SOR_AUDIO_HDA_PRESENSE_ELDV | SOR_AUDIO_HDA_PRESENSE_PD;
1997         tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE);
1998 }
1999
2000 static void tegra_sor_audio_unprepare(struct tegra_sor *sor)
2001 {
2002         tegra_sor_writel(sor, 0, SOR_AUDIO_HDA_PRESENSE);
2003         tegra_sor_writel(sor, 0, SOR_INT_MASK);
2004         tegra_sor_writel(sor, 0, SOR_INT_ENABLE);
2005 }
2006
2007 static void tegra_sor_audio_enable(struct tegra_sor *sor)
2008 {
2009         u32 value;
2010
2011         value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL);
2012
2013         /* select HDA audio input */
2014         value &= ~SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_MASK);
2015         value |= SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_HDA);
2016
2017         /* inject null samples */
2018         if (sor->format.channels != 2)
2019                 value &= ~SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2020         else
2021                 value |= SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2022
2023         value |= SOR_AUDIO_CNTRL_AFIFO_FLUSH;
2024
2025         tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL);
2026
2027         /* enable advertising HBR capability */
2028         tegra_sor_writel(sor, SOR_AUDIO_SPARE_HBR_ENABLE, SOR_AUDIO_SPARE);
2029 }
2030
2031 static int tegra_sor_hdmi_enable_audio_infoframe(struct tegra_sor *sor)
2032 {
2033         u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)];
2034         struct hdmi_audio_infoframe frame;
2035         u32 value;
2036         int err;
2037
2038         err = hdmi_audio_infoframe_init(&frame);
2039         if (err < 0) {
2040                 dev_err(sor->dev, "failed to setup audio infoframe: %d\n", err);
2041                 return err;
2042         }
2043
2044         frame.channels = sor->format.channels;
2045
2046         err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
2047         if (err < 0) {
2048                 dev_err(sor->dev, "failed to pack audio infoframe: %d\n", err);
2049                 return err;
2050         }
2051
2052         tegra_sor_hdmi_write_infopack(sor, buffer, err);
2053
2054         value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2055         value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
2056         value |= INFOFRAME_CTRL_ENABLE;
2057         tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2058
2059         return 0;
2060 }
2061
2062 static void tegra_sor_hdmi_audio_enable(struct tegra_sor *sor)
2063 {
2064         u32 value;
2065
2066         tegra_sor_audio_enable(sor);
2067
2068         tegra_sor_writel(sor, 0, SOR_HDMI_ACR_CTRL);
2069
2070         value = SOR_HDMI_SPARE_ACR_PRIORITY_HIGH |
2071                 SOR_HDMI_SPARE_CTS_RESET(1) |
2072                 SOR_HDMI_SPARE_HW_CTS_ENABLE;
2073         tegra_sor_writel(sor, value, SOR_HDMI_SPARE);
2074
2075         /* enable HW CTS */
2076         value = SOR_HDMI_ACR_SUBPACK_LOW_SB1(0);
2077         tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW);
2078
2079         /* allow packet to be sent */
2080         value = SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE;
2081         tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH);
2082
2083         /* reset N counter and enable lookup */
2084         value = SOR_HDMI_AUDIO_N_RESET | SOR_HDMI_AUDIO_N_LOOKUP;
2085         tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2086
2087         value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000);
2088         tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320);
2089         tegra_sor_writel(sor, 4096, SOR_AUDIO_NVAL_0320);
2090
2091         tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0441);
2092         tegra_sor_writel(sor, 4704, SOR_AUDIO_NVAL_0441);
2093
2094         tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0882);
2095         tegra_sor_writel(sor, 9408, SOR_AUDIO_NVAL_0882);
2096
2097         tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_1764);
2098         tegra_sor_writel(sor, 18816, SOR_AUDIO_NVAL_1764);
2099
2100         value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000);
2101         tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480);
2102         tegra_sor_writel(sor, 6144, SOR_AUDIO_NVAL_0480);
2103
2104         value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000);
2105         tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960);
2106         tegra_sor_writel(sor, 12288, SOR_AUDIO_NVAL_0960);
2107
2108         value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000);
2109         tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920);
2110         tegra_sor_writel(sor, 24576, SOR_AUDIO_NVAL_1920);
2111
2112         value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N);
2113         value &= ~SOR_HDMI_AUDIO_N_RESET;
2114         tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2115
2116         tegra_sor_hdmi_enable_audio_infoframe(sor);
2117 }
2118
2119 static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor)
2120 {
2121         u32 value;
2122
2123         value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2124         value &= ~INFOFRAME_CTRL_ENABLE;
2125         tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2126 }
2127
2128 static void tegra_sor_hdmi_audio_disable(struct tegra_sor *sor)
2129 {
2130         tegra_sor_hdmi_disable_audio_infoframe(sor);
2131 }
2132
2133 static struct tegra_sor_hdmi_settings *
2134 tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency)
2135 {
2136         unsigned int i;
2137
2138         for (i = 0; i < sor->num_settings; i++)
2139                 if (frequency <= sor->settings[i].frequency)
2140                         return &sor->settings[i];
2141
2142         return NULL;
2143 }
2144
2145 static void tegra_sor_hdmi_disable_scrambling(struct tegra_sor *sor)
2146 {
2147         u32 value;
2148
2149         value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2150         value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2151         value &= ~SOR_HDMI2_CTRL_SCRAMBLE;
2152         tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2153 }
2154
2155 static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor)
2156 {
2157         struct i2c_adapter *ddc = sor->output.ddc;
2158
2159         drm_scdc_set_high_tmds_clock_ratio(ddc, false);
2160         drm_scdc_set_scrambling(ddc, false);
2161
2162         tegra_sor_hdmi_disable_scrambling(sor);
2163 }
2164
2165 static void tegra_sor_hdmi_scdc_stop(struct tegra_sor *sor)
2166 {
2167         if (sor->scdc_enabled) {
2168                 cancel_delayed_work_sync(&sor->scdc);
2169                 tegra_sor_hdmi_scdc_disable(sor);
2170         }
2171 }
2172
2173 static void tegra_sor_hdmi_enable_scrambling(struct tegra_sor *sor)
2174 {
2175         u32 value;
2176
2177         value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2178         value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2179         value |= SOR_HDMI2_CTRL_SCRAMBLE;
2180         tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2181 }
2182
2183 static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor)
2184 {
2185         struct i2c_adapter *ddc = sor->output.ddc;
2186
2187         drm_scdc_set_high_tmds_clock_ratio(ddc, true);
2188         drm_scdc_set_scrambling(ddc, true);
2189
2190         tegra_sor_hdmi_enable_scrambling(sor);
2191 }
2192
2193 static void tegra_sor_hdmi_scdc_work(struct work_struct *work)
2194 {
2195         struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work);
2196         struct i2c_adapter *ddc = sor->output.ddc;
2197
2198         if (!drm_scdc_get_scrambling_status(ddc)) {
2199                 DRM_DEBUG_KMS("SCDC not scrambled\n");
2200                 tegra_sor_hdmi_scdc_enable(sor);
2201         }
2202
2203         schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2204 }
2205
2206 static void tegra_sor_hdmi_scdc_start(struct tegra_sor *sor)
2207 {
2208         struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc;
2209         struct drm_display_mode *mode;
2210
2211         mode = &sor->output.encoder.crtc->state->adjusted_mode;
2212
2213         if (mode->clock >= 340000 && scdc->supported) {
2214                 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2215                 tegra_sor_hdmi_scdc_enable(sor);
2216                 sor->scdc_enabled = true;
2217         }
2218 }
2219
2220 static void tegra_sor_hdmi_disable(struct drm_encoder *encoder)
2221 {
2222         struct tegra_output *output = encoder_to_output(encoder);
2223         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2224         struct tegra_sor *sor = to_sor(output);
2225         u32 value;
2226         int err;
2227
2228         tegra_sor_audio_unprepare(sor);
2229         tegra_sor_hdmi_scdc_stop(sor);
2230
2231         err = tegra_sor_detach(sor);
2232         if (err < 0)
2233                 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
2234
2235         tegra_sor_writel(sor, 0, SOR_STATE1);
2236         tegra_sor_update(sor);
2237
2238         /* disable display to SOR clock */
2239         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2240
2241         if (!sor->soc->has_nvdisplay)
2242                 value &= ~SOR1_TIMING_CYA;
2243
2244         value &= ~SOR_ENABLE(sor->index);
2245
2246         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2247
2248         tegra_dc_commit(dc);
2249
2250         err = tegra_sor_power_down(sor);
2251         if (err < 0)
2252                 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
2253
2254         err = tegra_io_pad_power_disable(sor->pad);
2255         if (err < 0)
2256                 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
2257
2258         host1x_client_suspend(&sor->client);
2259 }
2260
2261 static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
2262 {
2263         struct tegra_output *output = encoder_to_output(encoder);
2264         unsigned int h_ref_to_sync = 1, pulse_start, max_ac;
2265         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2266         struct tegra_sor_hdmi_settings *settings;
2267         struct tegra_sor *sor = to_sor(output);
2268         struct tegra_sor_state *state;
2269         struct drm_display_mode *mode;
2270         unsigned long rate, pclk;
2271         unsigned int div, i;
2272         u32 value;
2273         int err;
2274
2275         state = to_sor_state(output->connector.state);
2276         mode = &encoder->crtc->state->adjusted_mode;
2277         pclk = mode->clock * 1000;
2278
2279         err = host1x_client_resume(&sor->client);
2280         if (err < 0) {
2281                 dev_err(sor->dev, "failed to resume: %d\n", err);
2282                 return;
2283         }
2284
2285         /* switch to safe parent clock */
2286         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2287         if (err < 0) {
2288                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2289                 return;
2290         }
2291
2292         div = clk_get_rate(sor->clk) / 1000000 * 4;
2293
2294         err = tegra_io_pad_power_enable(sor->pad);
2295         if (err < 0)
2296                 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err);
2297
2298         usleep_range(20, 100);
2299
2300         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2301         value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
2302         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2303
2304         usleep_range(20, 100);
2305
2306         value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2307         value &= ~SOR_PLL3_PLL_VDD_MODE_3V3;
2308         tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2309
2310         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2311         value &= ~SOR_PLL0_VCOPD;
2312         value &= ~SOR_PLL0_PWR;
2313         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2314
2315         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2316         value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
2317         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2318
2319         usleep_range(200, 400);
2320
2321         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2322         value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
2323         value &= ~SOR_PLL2_PORT_POWERDOWN;
2324         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2325
2326         usleep_range(20, 100);
2327
2328         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2329         value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
2330                  SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2;
2331         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2332
2333         while (true) {
2334                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2335                 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0)
2336                         break;
2337
2338                 usleep_range(250, 1000);
2339         }
2340
2341         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
2342                 SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5);
2343         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
2344
2345         while (true) {
2346                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2347                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
2348                         break;
2349
2350                 usleep_range(250, 1000);
2351         }
2352
2353         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
2354         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
2355         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
2356
2357         if (mode->clock < 340000) {
2358                 DRM_DEBUG_KMS("setting 2.7 GHz link speed\n");
2359                 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70;
2360         } else {
2361                 DRM_DEBUG_KMS("setting 5.4 GHz link speed\n");
2362                 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40;
2363         }
2364
2365         value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
2366         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2367
2368         /* SOR pad PLL stabilization time */
2369         usleep_range(250, 1000);
2370
2371         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
2372         value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
2373         value |= SOR_DP_LINKCTL_LANE_COUNT(4);
2374         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2375
2376         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2377         value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2378         value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
2379         value &= ~SOR_DP_SPARE_SEQ_ENABLE;
2380         value &= ~SOR_DP_SPARE_MACRO_SOR_CLK;
2381         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2382
2383         value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) |
2384                 SOR_SEQ_CTL_PD_PC(8) | SOR_SEQ_CTL_PD_PC_ALT(8);
2385         tegra_sor_writel(sor, value, SOR_SEQ_CTL);
2386
2387         value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT |
2388                 SOR_SEQ_INST_WAIT_VSYNC | SOR_SEQ_INST_WAIT(1);
2389         tegra_sor_writel(sor, value, SOR_SEQ_INST(0));
2390         tegra_sor_writel(sor, value, SOR_SEQ_INST(8));
2391
2392         if (!sor->soc->has_nvdisplay) {
2393                 /* program the reference clock */
2394                 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div);
2395                 tegra_sor_writel(sor, value, SOR_REFCLK);
2396         }
2397
2398         /* XXX not in TRM */
2399         for (value = 0, i = 0; i < 5; i++)
2400                 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) |
2401                          SOR_XBAR_CTRL_LINK1_XSEL(i, i);
2402
2403         tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
2404         tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2405
2406         /*
2407          * Switch the pad clock to the DP clock. Note that we cannot actually
2408          * do this because Tegra186 and later don't support clk_set_parent()
2409          * on the sorX_pad_clkout clocks. We already do the equivalent above
2410          * using the DP_CLK_SEL mux of the SOR_CLK_CNTRL register.
2411          */
2412 #if 0
2413         err = clk_set_parent(sor->clk_pad, sor->clk_dp);
2414         if (err < 0) {
2415                 dev_err(sor->dev, "failed to select pad parent clock: %d\n",
2416                         err);
2417                 return;
2418         }
2419 #endif
2420
2421         /* switch the SOR clock to the pad clock */
2422         err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
2423         if (err < 0) {
2424                 dev_err(sor->dev, "failed to select SOR parent clock: %d\n",
2425                         err);
2426                 return;
2427         }
2428
2429         /* switch the output clock to the parent pixel clock */
2430         err = clk_set_parent(sor->clk, sor->clk_parent);
2431         if (err < 0) {
2432                 dev_err(sor->dev, "failed to select output parent clock: %d\n",
2433                         err);
2434                 return;
2435         }
2436
2437         /* adjust clock rate for HDMI 2.0 modes */
2438         rate = clk_get_rate(sor->clk_parent);
2439
2440         if (mode->clock >= 340000)
2441                 rate /= 2;
2442
2443         DRM_DEBUG_KMS("setting clock to %lu Hz, mode: %lu Hz\n", rate, pclk);
2444
2445         clk_set_rate(sor->clk, rate);
2446
2447         if (!sor->soc->has_nvdisplay) {
2448                 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
2449
2450                 /* XXX is this the proper check? */
2451                 if (mode->clock < 75000)
2452                         value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED;
2453
2454                 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL);
2455         }
2456
2457         max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32;
2458
2459         value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) |
2460                 SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY);
2461         tegra_sor_writel(sor, value, SOR_HDMI_CTRL);
2462
2463         if (!dc->soc->has_nvdisplay) {
2464                 /* H_PULSE2 setup */
2465                 pulse_start = h_ref_to_sync +
2466                               (mode->hsync_end - mode->hsync_start) +
2467                               (mode->htotal - mode->hsync_end) - 10;
2468
2469                 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE |
2470                         PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL;
2471                 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
2472
2473                 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start);
2474                 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
2475
2476                 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
2477                 value |= H_PULSE2_ENABLE;
2478                 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0);
2479         }
2480
2481         /* infoframe setup */
2482         err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode);
2483         if (err < 0)
2484                 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
2485
2486         /* XXX HDMI audio support not implemented yet */
2487         tegra_sor_hdmi_disable_audio_infoframe(sor);
2488
2489         /* use single TMDS protocol */
2490         value = tegra_sor_readl(sor, SOR_STATE1);
2491         value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2492         value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A;
2493         tegra_sor_writel(sor, value, SOR_STATE1);
2494
2495         /* power up pad calibration */
2496         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2497         value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
2498         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2499
2500         /* production settings */
2501         settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000);
2502         if (!settings) {
2503                 dev_err(sor->dev, "no settings for pixel clock %d Hz\n",
2504                         mode->clock * 1000);
2505                 return;
2506         }
2507
2508         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2509         value &= ~SOR_PLL0_ICHPMP_MASK;
2510         value &= ~SOR_PLL0_FILTER_MASK;
2511         value &= ~SOR_PLL0_VCOCAP_MASK;
2512         value |= SOR_PLL0_ICHPMP(settings->ichpmp);
2513         value |= SOR_PLL0_FILTER(settings->filter);
2514         value |= SOR_PLL0_VCOCAP(settings->vcocap);
2515         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2516
2517         /* XXX not in TRM */
2518         value = tegra_sor_readl(sor, sor->soc->regs->pll1);
2519         value &= ~SOR_PLL1_LOADADJ_MASK;
2520         value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
2521         value |= SOR_PLL1_LOADADJ(settings->loadadj);
2522         value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj);
2523         value |= SOR_PLL1_TMDS_TERM;
2524         tegra_sor_writel(sor, value, sor->soc->regs->pll1);
2525
2526         value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2527         value &= ~SOR_PLL3_BG_TEMP_COEF_MASK;
2528         value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK;
2529         value &= ~SOR_PLL3_AVDD10_LEVEL_MASK;
2530         value &= ~SOR_PLL3_AVDD14_LEVEL_MASK;
2531         value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef);
2532         value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level);
2533         value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level);
2534         value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level);
2535         tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2536
2537         value = settings->drive_current[3] << 24 |
2538                 settings->drive_current[2] << 16 |
2539                 settings->drive_current[1] <<  8 |
2540                 settings->drive_current[0] <<  0;
2541         tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
2542
2543         value = settings->preemphasis[3] << 24 |
2544                 settings->preemphasis[2] << 16 |
2545                 settings->preemphasis[1] <<  8 |
2546                 settings->preemphasis[0] <<  0;
2547         tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
2548
2549         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2550         value &= ~SOR_DP_PADCTL_TX_PU_MASK;
2551         value |= SOR_DP_PADCTL_TX_PU_ENABLE;
2552         value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value);
2553         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2554
2555         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2);
2556         value &= ~SOR_DP_PADCTL_SPAREPLL_MASK;
2557         value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll);
2558         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2);
2559
2560         /* power down pad calibration */
2561         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2562         value |= SOR_DP_PADCTL_PAD_CAL_PD;
2563         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2564
2565         if (!dc->soc->has_nvdisplay) {
2566                 /* miscellaneous display controller settings */
2567                 value = VSYNC_H_POSITION(1);
2568                 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS);
2569         }
2570
2571         value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
2572         value &= ~DITHER_CONTROL_MASK;
2573         value &= ~BASE_COLOR_SIZE_MASK;
2574
2575         switch (state->bpc) {
2576         case 6:
2577                 value |= BASE_COLOR_SIZE_666;
2578                 break;
2579
2580         case 8:
2581                 value |= BASE_COLOR_SIZE_888;
2582                 break;
2583
2584         case 10:
2585                 value |= BASE_COLOR_SIZE_101010;
2586                 break;
2587
2588         case 12:
2589                 value |= BASE_COLOR_SIZE_121212;
2590                 break;
2591
2592         default:
2593                 WARN(1, "%u bits-per-color not supported\n", state->bpc);
2594                 value |= BASE_COLOR_SIZE_888;
2595                 break;
2596         }
2597
2598         tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL);
2599
2600         /* XXX set display head owner */
2601         value = tegra_sor_readl(sor, SOR_STATE1);
2602         value &= ~SOR_STATE_ASY_OWNER_MASK;
2603         value |= SOR_STATE_ASY_OWNER(1 + dc->pipe);
2604         tegra_sor_writel(sor, value, SOR_STATE1);
2605
2606         err = tegra_sor_power_up(sor, 250);
2607         if (err < 0)
2608                 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2609
2610         /* configure dynamic range of output */
2611         value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2612         value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK;
2613         value &= ~SOR_HEAD_STATE_DYNRANGE_MASK;
2614         tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2615
2616         /* configure colorspace */
2617         value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2618         value &= ~SOR_HEAD_STATE_COLORSPACE_MASK;
2619         value |= SOR_HEAD_STATE_COLORSPACE_RGB;
2620         tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2621
2622         tegra_sor_mode_set(sor, mode, state);
2623
2624         tegra_sor_update(sor);
2625
2626         /* program preamble timing in SOR (XXX) */
2627         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2628         value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2629         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2630
2631         err = tegra_sor_attach(sor);
2632         if (err < 0)
2633                 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2634
2635         /* enable display to SOR clock and generate HDMI preamble */
2636         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2637
2638         if (!sor->soc->has_nvdisplay)
2639                 value |= SOR1_TIMING_CYA;
2640
2641         value |= SOR_ENABLE(sor->index);
2642
2643         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2644
2645         if (dc->soc->has_nvdisplay) {
2646                 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2647                 value &= ~PROTOCOL_MASK;
2648                 value |= PROTOCOL_SINGLE_TMDS_A;
2649                 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2650         }
2651
2652         tegra_dc_commit(dc);
2653
2654         err = tegra_sor_wakeup(sor);
2655         if (err < 0)
2656                 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2657
2658         tegra_sor_hdmi_scdc_start(sor);
2659         tegra_sor_audio_prepare(sor);
2660 }
2661
2662 static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = {
2663         .disable = tegra_sor_hdmi_disable,
2664         .enable = tegra_sor_hdmi_enable,
2665         .atomic_check = tegra_sor_encoder_atomic_check,
2666 };
2667
2668 static void tegra_sor_dp_disable(struct drm_encoder *encoder)
2669 {
2670         struct tegra_output *output = encoder_to_output(encoder);
2671         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2672         struct tegra_sor *sor = to_sor(output);
2673         u32 value;
2674         int err;
2675
2676         if (output->panel)
2677                 drm_panel_disable(output->panel);
2678
2679         /*
2680          * Do not attempt to power down a DP link if we're not connected since
2681          * the AUX transactions would just be timing out.
2682          */
2683         if (output->connector.status != connector_status_disconnected) {
2684                 err = drm_dp_link_power_down(sor->aux, &sor->link);
2685                 if (err < 0)
2686                         dev_err(sor->dev, "failed to power down link: %d\n",
2687                                 err);
2688         }
2689
2690         err = tegra_sor_detach(sor);
2691         if (err < 0)
2692                 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
2693
2694         tegra_sor_writel(sor, 0, SOR_STATE1);
2695         tegra_sor_update(sor);
2696
2697         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2698         value &= ~SOR_ENABLE(sor->index);
2699         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2700         tegra_dc_commit(dc);
2701
2702         value = tegra_sor_readl(sor, SOR_STATE1);
2703         value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2704         value &= ~SOR_STATE_ASY_SUBOWNER_MASK;
2705         value &= ~SOR_STATE_ASY_OWNER_MASK;
2706         tegra_sor_writel(sor, value, SOR_STATE1);
2707         tegra_sor_update(sor);
2708
2709         /* switch to safe parent clock */
2710         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2711         if (err < 0)
2712                 dev_err(sor->dev, "failed to set safe clock: %d\n", err);
2713
2714         err = tegra_sor_power_down(sor);
2715         if (err < 0)
2716                 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
2717
2718         err = tegra_io_pad_power_disable(sor->pad);
2719         if (err < 0)
2720                 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
2721
2722         err = drm_dp_aux_disable(sor->aux);
2723         if (err < 0)
2724                 dev_err(sor->dev, "failed disable DPAUX: %d\n", err);
2725
2726         if (output->panel)
2727                 drm_panel_unprepare(output->panel);
2728
2729         host1x_client_suspend(&sor->client);
2730 }
2731
2732 static void tegra_sor_dp_enable(struct drm_encoder *encoder)
2733 {
2734         struct tegra_output *output = encoder_to_output(encoder);
2735         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2736         struct tegra_sor *sor = to_sor(output);
2737         struct tegra_sor_config config;
2738         struct tegra_sor_state *state;
2739         struct drm_display_mode *mode;
2740         struct drm_display_info *info;
2741         unsigned int i;
2742         u32 value;
2743         int err;
2744
2745         state = to_sor_state(output->connector.state);
2746         mode = &encoder->crtc->state->adjusted_mode;
2747         info = &output->connector.display_info;
2748
2749         err = host1x_client_resume(&sor->client);
2750         if (err < 0) {
2751                 dev_err(sor->dev, "failed to resume: %d\n", err);
2752                 return;
2753         }
2754
2755         /* switch to safe parent clock */
2756         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2757         if (err < 0)
2758                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2759
2760         err = tegra_io_pad_power_enable(sor->pad);
2761         if (err < 0)
2762                 dev_err(sor->dev, "failed to power on LVDS rail: %d\n", err);
2763
2764         usleep_range(20, 100);
2765
2766         err = drm_dp_aux_enable(sor->aux);
2767         if (err < 0)
2768                 dev_err(sor->dev, "failed to enable DPAUX: %d\n", err);
2769
2770         err = drm_dp_link_probe(sor->aux, &sor->link);
2771         if (err < 0)
2772                 dev_err(sor->dev, "failed to probe DP link: %d\n", err);
2773
2774         tegra_sor_filter_rates(sor);
2775
2776         err = drm_dp_link_choose(&sor->link, mode, info);
2777         if (err < 0)
2778                 dev_err(sor->dev, "failed to choose link: %d\n", err);
2779
2780         if (output->panel)
2781                 drm_panel_prepare(output->panel);
2782
2783         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2784         value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
2785         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2786
2787         usleep_range(20, 40);
2788
2789         value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2790         value |= SOR_PLL3_PLL_VDD_MODE_3V3;
2791         tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2792
2793         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2794         value &= ~(SOR_PLL0_VCOPD | SOR_PLL0_PWR);
2795         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2796
2797         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2798         value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
2799         value |= SOR_PLL2_SEQ_PLLCAPPD;
2800         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2801
2802         usleep_range(200, 400);
2803
2804         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2805         value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
2806         value &= ~SOR_PLL2_PORT_POWERDOWN;
2807         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2808
2809         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
2810         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
2811
2812         if (output->panel)
2813                 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
2814         else
2815                 value |= SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK;
2816
2817         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2818
2819         usleep_range(200, 400);
2820
2821         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2822         /* XXX not in TRM */
2823         if (output->panel)
2824                 value |= SOR_DP_SPARE_PANEL_INTERNAL;
2825         else
2826                 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
2827
2828         value |= SOR_DP_SPARE_SEQ_ENABLE;
2829         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2830
2831         /* XXX not in TRM */
2832         tegra_sor_writel(sor, 0, SOR_LVDS);
2833
2834         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2835         value &= ~SOR_PLL0_ICHPMP_MASK;
2836         value &= ~SOR_PLL0_VCOCAP_MASK;
2837         value |= SOR_PLL0_ICHPMP(0x1);
2838         value |= SOR_PLL0_VCOCAP(0x3);
2839         value |= SOR_PLL0_RESISTOR_EXT;
2840         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2841
2842         /* XXX not in TRM */
2843         for (value = 0, i = 0; i < 5; i++)
2844                 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) |
2845                          SOR_XBAR_CTRL_LINK1_XSEL(i, i);
2846
2847         tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
2848         tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2849
2850         /*
2851          * Switch the pad clock to the DP clock. Note that we cannot actually
2852          * do this because Tegra186 and later don't support clk_set_parent()
2853          * on the sorX_pad_clkout clocks. We already do the equivalent above
2854          * using the DP_CLK_SEL mux of the SOR_CLK_CNTRL register.
2855          */
2856 #if 0
2857         err = clk_set_parent(sor->clk_pad, sor->clk_parent);
2858         if (err < 0) {
2859                 dev_err(sor->dev, "failed to select pad parent clock: %d\n",
2860                         err);
2861                 return;
2862         }
2863 #endif
2864
2865         /* switch the SOR clock to the pad clock */
2866         err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
2867         if (err < 0) {
2868                 dev_err(sor->dev, "failed to select SOR parent clock: %d\n",
2869                         err);
2870                 return;
2871         }
2872
2873         /* switch the output clock to the parent pixel clock */
2874         err = clk_set_parent(sor->clk, sor->clk_parent);
2875         if (err < 0) {
2876                 dev_err(sor->dev, "failed to select output parent clock: %d\n",
2877                         err);
2878                 return;
2879         }
2880
2881         /* use DP-A protocol */
2882         value = tegra_sor_readl(sor, SOR_STATE1);
2883         value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2884         value |= SOR_STATE_ASY_PROTOCOL_DP_A;
2885         tegra_sor_writel(sor, value, SOR_STATE1);
2886
2887         /* enable port */
2888         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
2889         value |= SOR_DP_LINKCTL_ENABLE;
2890         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2891
2892         tegra_sor_dp_term_calibrate(sor);
2893
2894         err = drm_dp_link_train(&sor->link);
2895         if (err < 0)
2896                 dev_err(sor->dev, "link training failed: %d\n", err);
2897         else
2898                 dev_dbg(sor->dev, "link training succeeded\n");
2899
2900         err = drm_dp_link_power_up(sor->aux, &sor->link);
2901         if (err < 0)
2902                 dev_err(sor->dev, "failed to power up DP link: %d\n", err);
2903
2904         /* compute configuration */
2905         memset(&config, 0, sizeof(config));
2906         config.bits_per_pixel = state->bpc * 3;
2907
2908         err = tegra_sor_compute_config(sor, mode, &config, &sor->link);
2909         if (err < 0)
2910                 dev_err(sor->dev, "failed to compute configuration: %d\n", err);
2911
2912         tegra_sor_apply_config(sor, &config);
2913         tegra_sor_mode_set(sor, mode, state);
2914
2915         if (output->panel) {
2916                 /* CSTM (LVDS, link A/B, upper) */
2917                 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |
2918                         SOR_CSTM_UPPER;
2919                 tegra_sor_writel(sor, value, SOR_CSTM);
2920
2921                 /* PWM setup */
2922                 err = tegra_sor_setup_pwm(sor, 250);
2923                 if (err < 0)
2924                         dev_err(sor->dev, "failed to setup PWM: %d\n", err);
2925         }
2926
2927         tegra_sor_update(sor);
2928
2929         err = tegra_sor_power_up(sor, 250);
2930         if (err < 0)
2931                 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2932
2933         /* attach and wake up */
2934         err = tegra_sor_attach(sor);
2935         if (err < 0)
2936                 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2937
2938         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2939         value |= SOR_ENABLE(sor->index);
2940         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2941
2942         tegra_dc_commit(dc);
2943
2944         err = tegra_sor_wakeup(sor);
2945         if (err < 0)
2946                 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2947
2948         if (output->panel)
2949                 drm_panel_enable(output->panel);
2950 }
2951
2952 static const struct drm_encoder_helper_funcs tegra_sor_dp_helpers = {
2953         .disable = tegra_sor_dp_disable,
2954         .enable = tegra_sor_dp_enable,
2955         .atomic_check = tegra_sor_encoder_atomic_check,
2956 };
2957
2958 static int tegra_sor_hdmi_probe(struct tegra_sor *sor)
2959 {
2960         int err;
2961
2962         sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io");
2963         if (IS_ERR(sor->avdd_io_supply)) {
2964                 dev_err(sor->dev, "cannot get AVDD I/O supply: %ld\n",
2965                         PTR_ERR(sor->avdd_io_supply));
2966                 return PTR_ERR(sor->avdd_io_supply);
2967         }
2968
2969         err = regulator_enable(sor->avdd_io_supply);
2970         if (err < 0) {
2971                 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n",
2972                         err);
2973                 return err;
2974         }
2975
2976         sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-pll");
2977         if (IS_ERR(sor->vdd_pll_supply)) {
2978                 dev_err(sor->dev, "cannot get VDD PLL supply: %ld\n",
2979                         PTR_ERR(sor->vdd_pll_supply));
2980                 return PTR_ERR(sor->vdd_pll_supply);
2981         }
2982
2983         err = regulator_enable(sor->vdd_pll_supply);
2984         if (err < 0) {
2985                 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n",
2986                         err);
2987                 return err;
2988         }
2989
2990         sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi");
2991         if (IS_ERR(sor->hdmi_supply)) {
2992                 dev_err(sor->dev, "cannot get HDMI supply: %ld\n",
2993                         PTR_ERR(sor->hdmi_supply));
2994                 return PTR_ERR(sor->hdmi_supply);
2995         }
2996
2997         err = regulator_enable(sor->hdmi_supply);
2998         if (err < 0) {
2999                 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err);
3000                 return err;
3001         }
3002
3003         INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work);
3004
3005         return 0;
3006 }
3007
3008 static int tegra_sor_hdmi_remove(struct tegra_sor *sor)
3009 {
3010         regulator_disable(sor->hdmi_supply);
3011         regulator_disable(sor->vdd_pll_supply);
3012         regulator_disable(sor->avdd_io_supply);
3013
3014         return 0;
3015 }
3016
3017 static const struct tegra_sor_ops tegra_sor_hdmi_ops = {
3018         .name = "HDMI",
3019         .probe = tegra_sor_hdmi_probe,
3020         .remove = tegra_sor_hdmi_remove,
3021         .audio_enable = tegra_sor_hdmi_audio_enable,
3022         .audio_disable = tegra_sor_hdmi_audio_disable,
3023 };
3024
3025 static int tegra_sor_dp_probe(struct tegra_sor *sor)
3026 {
3027         int err;
3028
3029         sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp");
3030         if (IS_ERR(sor->avdd_io_supply))
3031                 return PTR_ERR(sor->avdd_io_supply);
3032
3033         err = regulator_enable(sor->avdd_io_supply);
3034         if (err < 0)
3035                 return err;
3036
3037         sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll");
3038         if (IS_ERR(sor->vdd_pll_supply))
3039                 return PTR_ERR(sor->vdd_pll_supply);
3040
3041         err = regulator_enable(sor->vdd_pll_supply);
3042         if (err < 0)
3043                 return err;
3044
3045         return 0;
3046 }
3047
3048 static int tegra_sor_dp_remove(struct tegra_sor *sor)
3049 {
3050         regulator_disable(sor->vdd_pll_supply);
3051         regulator_disable(sor->avdd_io_supply);
3052
3053         return 0;
3054 }
3055
3056 static const struct tegra_sor_ops tegra_sor_dp_ops = {
3057         .name = "DP",
3058         .probe = tegra_sor_dp_probe,
3059         .remove = tegra_sor_dp_remove,
3060 };
3061
3062 static int tegra_sor_init(struct host1x_client *client)
3063 {
3064         struct drm_device *drm = dev_get_drvdata(client->host);
3065         const struct drm_encoder_helper_funcs *helpers = NULL;
3066         struct tegra_sor *sor = host1x_client_to_sor(client);
3067         int connector = DRM_MODE_CONNECTOR_Unknown;
3068         int encoder = DRM_MODE_ENCODER_NONE;
3069         int err;
3070
3071         if (!sor->aux) {
3072                 if (sor->ops == &tegra_sor_hdmi_ops) {
3073                         connector = DRM_MODE_CONNECTOR_HDMIA;
3074                         encoder = DRM_MODE_ENCODER_TMDS;
3075                         helpers = &tegra_sor_hdmi_helpers;
3076                 } else if (sor->soc->supports_lvds) {
3077                         connector = DRM_MODE_CONNECTOR_LVDS;
3078                         encoder = DRM_MODE_ENCODER_LVDS;
3079                 }
3080         } else {
3081                 if (sor->output.panel) {
3082                         connector = DRM_MODE_CONNECTOR_eDP;
3083                         encoder = DRM_MODE_ENCODER_TMDS;
3084                         helpers = &tegra_sor_dp_helpers;
3085                 } else {
3086                         connector = DRM_MODE_CONNECTOR_DisplayPort;
3087                         encoder = DRM_MODE_ENCODER_TMDS;
3088                         helpers = &tegra_sor_dp_helpers;
3089                 }
3090
3091                 sor->link.ops = &tegra_sor_dp_link_ops;
3092                 sor->link.aux = sor->aux;
3093         }
3094
3095         sor->output.dev = sor->dev;
3096
3097         drm_connector_init_with_ddc(drm, &sor->output.connector,
3098                                     &tegra_sor_connector_funcs,
3099                                     connector,
3100                                     sor->output.ddc);
3101         drm_connector_helper_add(&sor->output.connector,
3102                                  &tegra_sor_connector_helper_funcs);
3103         sor->output.connector.dpms = DRM_MODE_DPMS_OFF;
3104
3105         drm_encoder_init(drm, &sor->output.encoder, &tegra_sor_encoder_funcs,
3106                          encoder, NULL);
3107         drm_encoder_helper_add(&sor->output.encoder, helpers);
3108
3109         drm_connector_attach_encoder(&sor->output.connector,
3110                                           &sor->output.encoder);
3111         drm_connector_register(&sor->output.connector);
3112
3113         err = tegra_output_init(drm, &sor->output);
3114         if (err < 0) {
3115                 dev_err(client->dev, "failed to initialize output: %d\n", err);
3116                 return err;
3117         }
3118
3119         tegra_output_find_possible_crtcs(&sor->output, drm);
3120
3121         if (sor->aux) {
3122                 err = drm_dp_aux_attach(sor->aux, &sor->output);
3123                 if (err < 0) {
3124                         dev_err(sor->dev, "failed to attach DP: %d\n", err);
3125                         return err;
3126                 }
3127         }
3128
3129         /*
3130          * XXX: Remove this reset once proper hand-over from firmware to
3131          * kernel is possible.
3132          */
3133         if (sor->rst) {
3134                 err = reset_control_acquire(sor->rst);
3135                 if (err < 0) {
3136                         dev_err(sor->dev, "failed to acquire SOR reset: %d\n",
3137                                 err);
3138                         return err;
3139                 }
3140
3141                 err = reset_control_assert(sor->rst);
3142                 if (err < 0) {
3143                         dev_err(sor->dev, "failed to assert SOR reset: %d\n",
3144                                 err);
3145                         return err;
3146                 }
3147         }
3148
3149         err = clk_prepare_enable(sor->clk);
3150         if (err < 0) {
3151                 dev_err(sor->dev, "failed to enable clock: %d\n", err);
3152                 return err;
3153         }
3154
3155         usleep_range(1000, 3000);
3156
3157         if (sor->rst) {
3158                 err = reset_control_deassert(sor->rst);
3159                 if (err < 0) {
3160                         dev_err(sor->dev, "failed to deassert SOR reset: %d\n",
3161                                 err);
3162                         return err;
3163                 }
3164
3165                 reset_control_release(sor->rst);
3166         }
3167
3168         err = clk_prepare_enable(sor->clk_safe);
3169         if (err < 0)
3170                 return err;
3171
3172         err = clk_prepare_enable(sor->clk_dp);
3173         if (err < 0)
3174                 return err;
3175
3176         return 0;
3177 }
3178
3179 static int tegra_sor_exit(struct host1x_client *client)
3180 {
3181         struct tegra_sor *sor = host1x_client_to_sor(client);
3182         int err;
3183
3184         tegra_output_exit(&sor->output);
3185
3186         if (sor->aux) {
3187                 err = drm_dp_aux_detach(sor->aux);
3188                 if (err < 0) {
3189                         dev_err(sor->dev, "failed to detach DP: %d\n", err);
3190                         return err;
3191                 }
3192         }
3193
3194         clk_disable_unprepare(sor->clk_safe);
3195         clk_disable_unprepare(sor->clk_dp);
3196         clk_disable_unprepare(sor->clk);
3197
3198         return 0;
3199 }
3200
3201 static int tegra_sor_runtime_suspend(struct host1x_client *client)
3202 {
3203         struct tegra_sor *sor = host1x_client_to_sor(client);
3204         struct device *dev = client->dev;
3205         int err;
3206
3207         if (sor->rst) {
3208                 err = reset_control_assert(sor->rst);
3209                 if (err < 0) {
3210                         dev_err(dev, "failed to assert reset: %d\n", err);
3211                         return err;
3212                 }
3213
3214                 reset_control_release(sor->rst);
3215         }
3216
3217         usleep_range(1000, 2000);
3218
3219         clk_disable_unprepare(sor->clk);
3220         pm_runtime_put_sync(dev);
3221
3222         return 0;
3223 }
3224
3225 static int tegra_sor_runtime_resume(struct host1x_client *client)
3226 {
3227         struct tegra_sor *sor = host1x_client_to_sor(client);
3228         struct device *dev = client->dev;
3229         int err;
3230
3231         err = pm_runtime_get_sync(dev);
3232         if (err < 0) {
3233                 dev_err(dev, "failed to get runtime PM: %d\n", err);
3234                 return err;
3235         }
3236
3237         err = clk_prepare_enable(sor->clk);
3238         if (err < 0) {
3239                 dev_err(dev, "failed to enable clock: %d\n", err);
3240                 goto put_rpm;
3241         }
3242
3243         usleep_range(1000, 2000);
3244
3245         if (sor->rst) {
3246                 err = reset_control_acquire(sor->rst);
3247                 if (err < 0) {
3248                         dev_err(dev, "failed to acquire reset: %d\n", err);
3249                         goto disable_clk;
3250                 }
3251
3252                 err = reset_control_deassert(sor->rst);
3253                 if (err < 0) {
3254                         dev_err(dev, "failed to deassert reset: %d\n", err);
3255                         goto release_reset;
3256                 }
3257         }
3258
3259         return 0;
3260
3261 release_reset:
3262         reset_control_release(sor->rst);
3263 disable_clk:
3264         clk_disable_unprepare(sor->clk);
3265 put_rpm:
3266         pm_runtime_put_sync(dev);
3267         return err;
3268 }
3269
3270 static const struct host1x_client_ops sor_client_ops = {
3271         .init = tegra_sor_init,
3272         .exit = tegra_sor_exit,
3273         .suspend = tegra_sor_runtime_suspend,
3274         .resume = tegra_sor_runtime_resume,
3275 };
3276
3277 static const u8 tegra124_sor_xbar_cfg[5] = {
3278         0, 1, 2, 3, 4
3279 };
3280
3281 static const struct tegra_sor_regs tegra124_sor_regs = {
3282         .head_state0 = 0x05,
3283         .head_state1 = 0x07,
3284         .head_state2 = 0x09,
3285         .head_state3 = 0x0b,
3286         .head_state4 = 0x0d,
3287         .head_state5 = 0x0f,
3288         .pll0 = 0x17,
3289         .pll1 = 0x18,
3290         .pll2 = 0x19,
3291         .pll3 = 0x1a,
3292         .dp_padctl0 = 0x5c,
3293         .dp_padctl2 = 0x73,
3294 };
3295
3296 /* Tegra124 and Tegra132 have lanes 0 and 2 swapped. */
3297 static const u8 tegra124_sor_lane_map[4] = {
3298         2, 1, 0, 3,
3299 };
3300
3301 static const u8 tegra124_sor_voltage_swing[4][4][4] = {
3302         {
3303                 { 0x13, 0x19, 0x1e, 0x28 },
3304                 { 0x1e, 0x25, 0x2d, },
3305                 { 0x28, 0x32, },
3306                 { 0x3c, },
3307         }, {
3308                 { 0x12, 0x17, 0x1b, 0x25 },
3309                 { 0x1c, 0x23, 0x2a, },
3310                 { 0x25, 0x2f, },
3311                 { 0x39, }
3312         }, {
3313                 { 0x12, 0x16, 0x1a, 0x22 },
3314                 { 0x1b, 0x20, 0x27, },
3315                 { 0x24, 0x2d, },
3316                 { 0x36, },
3317         }, {
3318                 { 0x11, 0x14, 0x17, 0x1f },
3319                 { 0x19, 0x1e, 0x24, },
3320                 { 0x22, 0x2a, },
3321                 { 0x32, },
3322         },
3323 };
3324
3325 static const u8 tegra124_sor_pre_emphasis[4][4][4] = {
3326         {
3327                 { 0x00, 0x09, 0x13, 0x25 },
3328                 { 0x00, 0x0f, 0x1e, },
3329                 { 0x00, 0x14, },
3330                 { 0x00, },
3331         }, {
3332                 { 0x00, 0x0a, 0x14, 0x28 },
3333                 { 0x00, 0x0f, 0x1e, },
3334                 { 0x00, 0x14, },
3335                 { 0x00 },
3336         }, {
3337                 { 0x00, 0x0a, 0x14, 0x28 },
3338                 { 0x00, 0x0f, 0x1e, },
3339                 { 0x00, 0x14, },
3340                 { 0x00, },
3341         }, {
3342                 { 0x00, 0x0a, 0x14, 0x28 },
3343                 { 0x00, 0x0f, 0x1e, },
3344                 { 0x00, 0x14, },
3345                 { 0x00, },
3346         },
3347 };
3348
3349 static const u8 tegra124_sor_post_cursor[4][4][4] = {
3350         {
3351                 { 0x00, 0x00, 0x00, 0x00 },
3352                 { 0x00, 0x00, 0x00, },
3353                 { 0x00, 0x00, },
3354                 { 0x00, },
3355         }, {
3356                 { 0x02, 0x02, 0x04, 0x05 },
3357                 { 0x02, 0x04, 0x05, },
3358                 { 0x04, 0x05, },
3359                 { 0x05, },
3360         }, {
3361                 { 0x04, 0x05, 0x08, 0x0b },
3362                 { 0x05, 0x09, 0x0b, },
3363                 { 0x08, 0x0a, },
3364                 { 0x0b, },
3365         }, {
3366                 { 0x05, 0x09, 0x0b, 0x12 },
3367                 { 0x09, 0x0d, 0x12, },
3368                 { 0x0b, 0x0f, },
3369                 { 0x12, },
3370         },
3371 };
3372
3373 static const u8 tegra124_sor_tx_pu[4][4][4] = {
3374         {
3375                 { 0x20, 0x30, 0x40, 0x60 },
3376                 { 0x30, 0x40, 0x60, },
3377                 { 0x40, 0x60, },
3378                 { 0x60, },
3379         }, {
3380                 { 0x20, 0x20, 0x30, 0x50 },
3381                 { 0x30, 0x40, 0x50, },
3382                 { 0x40, 0x50, },
3383                 { 0x60, },
3384         }, {
3385                 { 0x20, 0x20, 0x30, 0x40, },
3386                 { 0x30, 0x30, 0x40, },
3387                 { 0x40, 0x50, },
3388                 { 0x60, },
3389         }, {
3390                 { 0x20, 0x20, 0x20, 0x40, },
3391                 { 0x30, 0x30, 0x40, },
3392                 { 0x40, 0x40, },
3393                 { 0x60, },
3394         },
3395 };
3396
3397 static const struct tegra_sor_soc tegra124_sor = {
3398         .supports_lvds = true,
3399         .supports_hdmi = false,
3400         .supports_dp = true,
3401         .supports_audio = false,
3402         .supports_hdcp = false,
3403         .regs = &tegra124_sor_regs,
3404         .has_nvdisplay = false,
3405         .xbar_cfg = tegra124_sor_xbar_cfg,
3406         .lane_map = tegra124_sor_lane_map,
3407         .voltage_swing = tegra124_sor_voltage_swing,
3408         .pre_emphasis = tegra124_sor_pre_emphasis,
3409         .post_cursor = tegra124_sor_post_cursor,
3410         .tx_pu = tegra124_sor_tx_pu,
3411 };
3412
3413 static const u8 tegra132_sor_pre_emphasis[4][4][4] = {
3414         {
3415                 { 0x00, 0x08, 0x12, 0x24 },
3416                 { 0x01, 0x0e, 0x1d, },
3417                 { 0x01, 0x13, },
3418                 { 0x00, },
3419         }, {
3420                 { 0x00, 0x08, 0x12, 0x24 },
3421                 { 0x00, 0x0e, 0x1d, },
3422                 { 0x00, 0x13, },
3423                 { 0x00 },
3424         }, {
3425                 { 0x00, 0x08, 0x12, 0x24 },
3426                 { 0x00, 0x0e, 0x1d, },
3427                 { 0x00, 0x13, },
3428                 { 0x00, },
3429         }, {
3430                 { 0x00, 0x08, 0x12, 0x24 },
3431                 { 0x00, 0x0e, 0x1d, },
3432                 { 0x00, 0x13, },
3433                 { 0x00, },
3434         },
3435 };
3436
3437 static const struct tegra_sor_soc tegra132_sor = {
3438         .supports_lvds = true,
3439         .supports_hdmi = false,
3440         .supports_dp = true,
3441         .supports_audio = false,
3442         .supports_hdcp = false,
3443         .regs = &tegra124_sor_regs,
3444         .has_nvdisplay = false,
3445         .xbar_cfg = tegra124_sor_xbar_cfg,
3446         .lane_map = tegra124_sor_lane_map,
3447         .voltage_swing = tegra124_sor_voltage_swing,
3448         .pre_emphasis = tegra132_sor_pre_emphasis,
3449         .post_cursor = tegra124_sor_post_cursor,
3450         .tx_pu = tegra124_sor_tx_pu,
3451 };
3452
3453 static const struct tegra_sor_regs tegra210_sor_regs = {
3454         .head_state0 = 0x05,
3455         .head_state1 = 0x07,
3456         .head_state2 = 0x09,
3457         .head_state3 = 0x0b,
3458         .head_state4 = 0x0d,
3459         .head_state5 = 0x0f,
3460         .pll0 = 0x17,
3461         .pll1 = 0x18,
3462         .pll2 = 0x19,
3463         .pll3 = 0x1a,
3464         .dp_padctl0 = 0x5c,
3465         .dp_padctl2 = 0x73,
3466 };
3467
3468 static const u8 tegra210_sor_xbar_cfg[5] = {
3469         2, 1, 0, 3, 4
3470 };
3471
3472 static const u8 tegra210_sor_lane_map[4] = {
3473         0, 1, 2, 3,
3474 };
3475
3476 static const struct tegra_sor_soc tegra210_sor = {
3477         .supports_lvds = false,
3478         .supports_hdmi = false,
3479         .supports_dp = true,
3480         .supports_audio = false,
3481         .supports_hdcp = false,
3482
3483         .regs = &tegra210_sor_regs,
3484         .has_nvdisplay = false,
3485
3486         .xbar_cfg = tegra210_sor_xbar_cfg,
3487         .lane_map = tegra210_sor_lane_map,
3488         .voltage_swing = tegra124_sor_voltage_swing,
3489         .pre_emphasis = tegra124_sor_pre_emphasis,
3490         .post_cursor = tegra124_sor_post_cursor,
3491         .tx_pu = tegra124_sor_tx_pu,
3492 };
3493
3494 static const struct tegra_sor_soc tegra210_sor1 = {
3495         .supports_lvds = false,
3496         .supports_hdmi = true,
3497         .supports_dp = true,
3498         .supports_audio = true,
3499         .supports_hdcp = true,
3500
3501         .regs = &tegra210_sor_regs,
3502         .has_nvdisplay = false,
3503
3504         .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults),
3505         .settings = tegra210_sor_hdmi_defaults,
3506         .xbar_cfg = tegra210_sor_xbar_cfg,
3507         .lane_map = tegra210_sor_lane_map,
3508         .voltage_swing = tegra124_sor_voltage_swing,
3509         .pre_emphasis = tegra124_sor_pre_emphasis,
3510         .post_cursor = tegra124_sor_post_cursor,
3511         .tx_pu = tegra124_sor_tx_pu,
3512 };
3513
3514 static const struct tegra_sor_regs tegra186_sor_regs = {
3515         .head_state0 = 0x151,
3516         .head_state1 = 0x154,
3517         .head_state2 = 0x157,
3518         .head_state3 = 0x15a,
3519         .head_state4 = 0x15d,
3520         .head_state5 = 0x160,
3521         .pll0 = 0x163,
3522         .pll1 = 0x164,
3523         .pll2 = 0x165,
3524         .pll3 = 0x166,
3525         .dp_padctl0 = 0x168,
3526         .dp_padctl2 = 0x16a,
3527 };
3528
3529 static const u8 tegra186_sor_voltage_swing[4][4][4] = {
3530         {
3531                 { 0x13, 0x19, 0x1e, 0x28 },
3532                 { 0x1e, 0x25, 0x2d, },
3533                 { 0x28, 0x32, },
3534                 { 0x39, },
3535         }, {
3536                 { 0x12, 0x16, 0x1b, 0x25 },
3537                 { 0x1c, 0x23, 0x2a, },
3538                 { 0x25, 0x2f, },
3539                 { 0x37, }
3540         }, {
3541                 { 0x12, 0x16, 0x1a, 0x22 },
3542                 { 0x1b, 0x20, 0x27, },
3543                 { 0x24, 0x2d, },
3544                 { 0x35, },
3545         }, {
3546                 { 0x11, 0x14, 0x17, 0x1f },
3547                 { 0x19, 0x1e, 0x24, },
3548                 { 0x22, 0x2a, },
3549                 { 0x32, },
3550         },
3551 };
3552
3553 static const u8 tegra186_sor_pre_emphasis[4][4][4] = {
3554         {
3555                 { 0x00, 0x08, 0x12, 0x24 },
3556                 { 0x01, 0x0e, 0x1d, },
3557                 { 0x01, 0x13, },
3558                 { 0x00, },
3559         }, {
3560                 { 0x00, 0x08, 0x12, 0x24 },
3561                 { 0x00, 0x0e, 0x1d, },
3562                 { 0x00, 0x13, },
3563                 { 0x00 },
3564         }, {
3565                 { 0x00, 0x08, 0x14, 0x24 },
3566                 { 0x00, 0x0e, 0x1d, },
3567                 { 0x00, 0x13, },
3568                 { 0x00, },
3569         }, {
3570                 { 0x00, 0x08, 0x12, 0x24 },
3571                 { 0x00, 0x0e, 0x1d, },
3572                 { 0x00, 0x13, },
3573                 { 0x00, },
3574         },
3575 };
3576
3577 static const struct tegra_sor_soc tegra186_sor = {
3578         .supports_lvds = false,
3579         .supports_hdmi = true,
3580         .supports_dp = true,
3581         .supports_audio = true,
3582         .supports_hdcp = true,
3583
3584         .regs = &tegra186_sor_regs,
3585         .has_nvdisplay = true,
3586
3587         .num_settings = ARRAY_SIZE(tegra186_sor_hdmi_defaults),
3588         .settings = tegra186_sor_hdmi_defaults,
3589         .xbar_cfg = tegra124_sor_xbar_cfg,
3590         .lane_map = tegra124_sor_lane_map,
3591         .voltage_swing = tegra186_sor_voltage_swing,
3592         .pre_emphasis = tegra186_sor_pre_emphasis,
3593         .post_cursor = tegra124_sor_post_cursor,
3594         .tx_pu = tegra124_sor_tx_pu,
3595 };
3596
3597 static const struct tegra_sor_regs tegra194_sor_regs = {
3598         .head_state0 = 0x151,
3599         .head_state1 = 0x155,
3600         .head_state2 = 0x159,
3601         .head_state3 = 0x15d,
3602         .head_state4 = 0x161,
3603         .head_state5 = 0x165,
3604         .pll0 = 0x169,
3605         .pll1 = 0x16a,
3606         .pll2 = 0x16b,
3607         .pll3 = 0x16c,
3608         .dp_padctl0 = 0x16e,
3609         .dp_padctl2 = 0x16f,
3610 };
3611
3612 static const struct tegra_sor_soc tegra194_sor = {
3613         .supports_lvds = false,
3614         .supports_hdmi = true,
3615         .supports_dp = true,
3616         .supports_audio = true,
3617         .supports_hdcp = true,
3618
3619         .regs = &tegra194_sor_regs,
3620         .has_nvdisplay = true,
3621
3622         .num_settings = ARRAY_SIZE(tegra194_sor_hdmi_defaults),
3623         .settings = tegra194_sor_hdmi_defaults,
3624
3625         .xbar_cfg = tegra210_sor_xbar_cfg,
3626         .lane_map = tegra124_sor_lane_map,
3627         .voltage_swing = tegra186_sor_voltage_swing,
3628         .pre_emphasis = tegra186_sor_pre_emphasis,
3629         .post_cursor = tegra124_sor_post_cursor,
3630         .tx_pu = tegra124_sor_tx_pu,
3631 };
3632
3633 static const struct of_device_id tegra_sor_of_match[] = {
3634         { .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor },
3635         { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor },
3636         { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 },
3637         { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor },
3638         { .compatible = "nvidia,tegra132-sor", .data = &tegra132_sor },
3639         { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor },
3640         { },
3641 };
3642 MODULE_DEVICE_TABLE(of, tegra_sor_of_match);
3643
3644 static int tegra_sor_parse_dt(struct tegra_sor *sor)
3645 {
3646         struct device_node *np = sor->dev->of_node;
3647         u32 xbar_cfg[5];
3648         unsigned int i;
3649         u32 value;
3650         int err;
3651
3652         if (sor->soc->has_nvdisplay) {
3653                 err = of_property_read_u32(np, "nvidia,interface", &value);
3654                 if (err < 0)
3655                         return err;
3656
3657                 sor->index = value;
3658
3659                 /*
3660                  * override the default that we already set for Tegra210 and
3661                  * earlier
3662                  */
3663                 sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index;
3664         } else {
3665                 if (!sor->soc->supports_audio)
3666                         sor->index = 0;
3667                 else
3668                         sor->index = 1;
3669         }
3670
3671         err = of_property_read_u32_array(np, "nvidia,xbar-cfg", xbar_cfg, 5);
3672         if (err < 0) {
3673                 /* fall back to default per-SoC XBAR configuration */
3674                 for (i = 0; i < 5; i++)
3675                         sor->xbar_cfg[i] = sor->soc->xbar_cfg[i];
3676         } else {
3677                 /* copy cells to SOR XBAR configuration */
3678                 for (i = 0; i < 5; i++)
3679                         sor->xbar_cfg[i] = xbar_cfg[i];
3680         }
3681
3682         return 0;
3683 }
3684
3685 static irqreturn_t tegra_sor_irq(int irq, void *data)
3686 {
3687         struct tegra_sor *sor = data;
3688         u32 value;
3689
3690         value = tegra_sor_readl(sor, SOR_INT_STATUS);
3691         tegra_sor_writel(sor, value, SOR_INT_STATUS);
3692
3693         if (value & SOR_INT_CODEC_SCRATCH0) {
3694                 value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0);
3695
3696                 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
3697                         unsigned int format;
3698
3699                         format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;
3700
3701                         tegra_hda_parse_format(format, &sor->format);
3702
3703                         if (sor->ops->audio_enable)
3704                                 sor->ops->audio_enable(sor);
3705                 } else {
3706                         if (sor->ops->audio_disable)
3707                                 sor->ops->audio_disable(sor);
3708                 }
3709         }
3710
3711         return IRQ_HANDLED;
3712 }
3713
3714 static int tegra_sor_probe(struct platform_device *pdev)
3715 {
3716         struct device_node *np;
3717         struct tegra_sor *sor;
3718         struct resource *regs;
3719         int err;
3720
3721         sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL);
3722         if (!sor)
3723                 return -ENOMEM;
3724
3725         sor->soc = of_device_get_match_data(&pdev->dev);
3726         sor->output.dev = sor->dev = &pdev->dev;
3727
3728         sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings,
3729                                      sor->soc->num_settings *
3730                                         sizeof(*sor->settings),
3731                                      GFP_KERNEL);
3732         if (!sor->settings)
3733                 return -ENOMEM;
3734
3735         sor->num_settings = sor->soc->num_settings;
3736
3737         np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0);
3738         if (np) {
3739                 sor->aux = drm_dp_aux_find_by_of_node(np);
3740                 of_node_put(np);
3741
3742                 if (!sor->aux)
3743                         return -EPROBE_DEFER;
3744
3745                 sor->output.ddc = &sor->aux->ddc;
3746         }
3747
3748         if (!sor->aux) {
3749                 if (sor->soc->supports_hdmi) {
3750                         sor->ops = &tegra_sor_hdmi_ops;
3751                         sor->pad = TEGRA_IO_PAD_HDMI;
3752                 } else if (sor->soc->supports_lvds) {
3753                         dev_err(&pdev->dev, "LVDS not supported yet\n");
3754                         return -ENODEV;
3755                 } else {
3756                         dev_err(&pdev->dev, "unknown (non-DP) support\n");
3757                         return -ENODEV;
3758                 }
3759         } else {
3760                 np = of_parse_phandle(pdev->dev.of_node, "nvidia,panel", 0);
3761                 /*
3762                  * No need to keep this around since we only use it as a check
3763                  * to see if a panel is connected (eDP) or not (DP).
3764                  */
3765                 of_node_put(np);
3766
3767                 sor->ops = &tegra_sor_dp_ops;
3768                 sor->pad = TEGRA_IO_PAD_LVDS;
3769         }
3770
3771         err = tegra_sor_parse_dt(sor);
3772         if (err < 0)
3773                 return err;
3774
3775         err = tegra_output_probe(&sor->output);
3776         if (err < 0) {
3777                 dev_err(&pdev->dev, "failed to probe output: %d\n", err);
3778                 return err;
3779         }
3780
3781         if (sor->ops && sor->ops->probe) {
3782                 err = sor->ops->probe(sor);
3783                 if (err < 0) {
3784                         dev_err(&pdev->dev, "failed to probe %s: %d\n",
3785                                 sor->ops->name, err);
3786                         goto output;
3787                 }
3788         }
3789
3790         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3791         sor->regs = devm_ioremap_resource(&pdev->dev, regs);
3792         if (IS_ERR(sor->regs)) {
3793                 err = PTR_ERR(sor->regs);
3794                 goto remove;
3795         }
3796
3797         err = platform_get_irq(pdev, 0);
3798         if (err < 0) {
3799                 dev_err(&pdev->dev, "failed to get IRQ: %d\n", err);
3800                 goto remove;
3801         }
3802
3803         sor->irq = err;
3804
3805         err = devm_request_irq(sor->dev, sor->irq, tegra_sor_irq, 0,
3806                                dev_name(sor->dev), sor);
3807         if (err < 0) {
3808                 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
3809                 goto remove;
3810         }
3811
3812         sor->rst = devm_reset_control_get_exclusive_released(&pdev->dev, "sor");
3813         if (IS_ERR(sor->rst)) {
3814                 err = PTR_ERR(sor->rst);
3815
3816                 if (err != -EBUSY || WARN_ON(!pdev->dev.pm_domain)) {
3817                         dev_err(&pdev->dev, "failed to get reset control: %d\n",
3818                                 err);
3819                         goto remove;
3820                 }
3821
3822                 /*
3823                  * At this point, the reset control is most likely being used
3824                  * by the generic power domain implementation. With any luck
3825                  * the power domain will have taken care of resetting the SOR
3826                  * and we don't have to do anything.
3827                  */
3828                 sor->rst = NULL;
3829         }
3830
3831         sor->clk = devm_clk_get(&pdev->dev, NULL);
3832         if (IS_ERR(sor->clk)) {
3833                 err = PTR_ERR(sor->clk);
3834                 dev_err(&pdev->dev, "failed to get module clock: %d\n", err);
3835                 goto remove;
3836         }
3837
3838         if (sor->soc->supports_hdmi || sor->soc->supports_dp) {
3839                 struct device_node *np = pdev->dev.of_node;
3840                 const char *name;
3841
3842                 /*
3843                  * For backwards compatibility with Tegra210 device trees,
3844                  * fall back to the old clock name "source" if the new "out"
3845                  * clock is not available.
3846                  */
3847                 if (of_property_match_string(np, "clock-names", "out") < 0)
3848                         name = "source";
3849                 else
3850                         name = "out";
3851
3852                 sor->clk_out = devm_clk_get(&pdev->dev, name);
3853                 if (IS_ERR(sor->clk_out)) {
3854                         err = PTR_ERR(sor->clk_out);
3855                         dev_err(sor->dev, "failed to get %s clock: %d\n",
3856                                 name, err);
3857                         goto remove;
3858                 }
3859         } else {
3860                 /* fall back to the module clock on SOR0 (eDP/LVDS only) */
3861                 sor->clk_out = sor->clk;
3862         }
3863
3864         sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
3865         if (IS_ERR(sor->clk_parent)) {
3866                 err = PTR_ERR(sor->clk_parent);
3867                 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err);
3868                 goto remove;
3869         }
3870
3871         sor->clk_safe = devm_clk_get(&pdev->dev, "safe");
3872         if (IS_ERR(sor->clk_safe)) {
3873                 err = PTR_ERR(sor->clk_safe);
3874                 dev_err(&pdev->dev, "failed to get safe clock: %d\n", err);
3875                 goto remove;
3876         }
3877
3878         sor->clk_dp = devm_clk_get(&pdev->dev, "dp");
3879         if (IS_ERR(sor->clk_dp)) {
3880                 err = PTR_ERR(sor->clk_dp);
3881                 dev_err(&pdev->dev, "failed to get DP clock: %d\n", err);
3882                 goto remove;
3883         }
3884
3885         /*
3886          * Starting with Tegra186, the BPMP provides an implementation for
3887          * the pad output clock, so we have to look it up from device tree.
3888          */
3889         sor->clk_pad = devm_clk_get(&pdev->dev, "pad");
3890         if (IS_ERR(sor->clk_pad)) {
3891                 if (sor->clk_pad != ERR_PTR(-ENOENT)) {
3892                         err = PTR_ERR(sor->clk_pad);
3893                         goto remove;
3894                 }
3895
3896                 /*
3897                  * If the pad output clock is not available, then we assume
3898                  * we're on Tegra210 or earlier and have to provide our own
3899                  * implementation.
3900                  */
3901                 sor->clk_pad = NULL;
3902         }
3903
3904         /*
3905          * The bootloader may have set up the SOR such that it's module clock
3906          * is sourced by one of the display PLLs. However, that doesn't work
3907          * without properly having set up other bits of the SOR.
3908          */
3909         err = clk_set_parent(sor->clk_out, sor->clk_safe);
3910         if (err < 0) {
3911                 dev_err(&pdev->dev, "failed to use safe clock: %d\n", err);
3912                 goto remove;
3913         }
3914
3915         platform_set_drvdata(pdev, sor);
3916         pm_runtime_enable(&pdev->dev);
3917
3918         INIT_LIST_HEAD(&sor->client.list);
3919         sor->client.ops = &sor_client_ops;
3920         sor->client.dev = &pdev->dev;
3921
3922         err = host1x_client_register(&sor->client);
3923         if (err < 0) {
3924                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
3925                         err);
3926                 goto rpm_disable;
3927         }
3928
3929         /*
3930          * On Tegra210 and earlier, provide our own implementation for the
3931          * pad output clock.
3932          */
3933         if (!sor->clk_pad) {
3934                 char *name;
3935
3936                 name = devm_kasprintf(sor->dev, GFP_KERNEL, "sor%u_pad_clkout",
3937                                       sor->index);
3938                 if (!name) {
3939                         err = -ENOMEM;
3940                         goto unregister;
3941                 }
3942
3943                 err = host1x_client_resume(&sor->client);
3944                 if (err < 0) {
3945                         dev_err(sor->dev, "failed to resume: %d\n", err);
3946                         goto unregister;
3947                 }
3948
3949                 sor->clk_pad = tegra_clk_sor_pad_register(sor, name);
3950                 host1x_client_suspend(&sor->client);
3951         }
3952
3953         if (IS_ERR(sor->clk_pad)) {
3954                 err = PTR_ERR(sor->clk_pad);
3955                 dev_err(sor->dev, "failed to register SOR pad clock: %d\n",
3956                         err);
3957                 goto unregister;
3958         }
3959
3960         return 0;
3961
3962 unregister:
3963         host1x_client_unregister(&sor->client);
3964 rpm_disable:
3965         pm_runtime_disable(&pdev->dev);
3966 remove:
3967         if (sor->ops && sor->ops->remove)
3968                 sor->ops->remove(sor);
3969 output:
3970         tegra_output_remove(&sor->output);
3971         return err;
3972 }
3973
3974 static int tegra_sor_remove(struct platform_device *pdev)
3975 {
3976         struct tegra_sor *sor = platform_get_drvdata(pdev);
3977         int err;
3978
3979         err = host1x_client_unregister(&sor->client);
3980         if (err < 0) {
3981                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
3982                         err);
3983                 return err;
3984         }
3985
3986         pm_runtime_disable(&pdev->dev);
3987
3988         if (sor->ops && sor->ops->remove) {
3989                 err = sor->ops->remove(sor);
3990                 if (err < 0)
3991                         dev_err(&pdev->dev, "failed to remove SOR: %d\n", err);
3992         }
3993
3994         tegra_output_remove(&sor->output);
3995
3996         return 0;
3997 }
3998
3999 static int __maybe_unused tegra_sor_suspend(struct device *dev)
4000 {
4001         struct tegra_sor *sor = dev_get_drvdata(dev);
4002         int err;
4003
4004         err = tegra_output_suspend(&sor->output);
4005         if (err < 0) {
4006                 dev_err(dev, "failed to suspend output: %d\n", err);
4007                 return err;
4008         }
4009
4010         if (sor->hdmi_supply) {
4011                 err = regulator_disable(sor->hdmi_supply);
4012                 if (err < 0) {
4013                         tegra_output_resume(&sor->output);
4014                         return err;
4015                 }
4016         }
4017
4018         return 0;
4019 }
4020
4021 static int __maybe_unused tegra_sor_resume(struct device *dev)
4022 {
4023         struct tegra_sor *sor = dev_get_drvdata(dev);
4024         int err;
4025
4026         if (sor->hdmi_supply) {
4027                 err = regulator_enable(sor->hdmi_supply);
4028                 if (err < 0)
4029                         return err;
4030         }
4031
4032         err = tegra_output_resume(&sor->output);
4033         if (err < 0) {
4034                 dev_err(dev, "failed to resume output: %d\n", err);
4035
4036                 if (sor->hdmi_supply)
4037                         regulator_disable(sor->hdmi_supply);
4038
4039                 return err;
4040         }
4041
4042         return 0;
4043 }
4044
4045 static const struct dev_pm_ops tegra_sor_pm_ops = {
4046         SET_SYSTEM_SLEEP_PM_OPS(tegra_sor_suspend, tegra_sor_resume)
4047 };
4048
4049 struct platform_driver tegra_sor_driver = {
4050         .driver = {
4051                 .name = "tegra-sor",
4052                 .of_match_table = tegra_sor_of_match,
4053                 .pm = &tegra_sor_pm_ops,
4054         },
4055         .probe = tegra_sor_probe,
4056         .remove = tegra_sor_remove,
4057 };