drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

   1 /*
   2  * Copyright 2008 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jerome Glisse <[email protected]>
  26  */
  27 #include <linux/pagemap.h>
  28 #include <linux/sync_file.h>
  29 #include <drm/drmP.h>
  30 #include <drm/amdgpu_drm.h>
  31 #include <drm/drm_syncobj.h>
  32 #include "amdgpu.h"
  33 #include "amdgpu_trace.h"
  34
  35 static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
  36                                       struct drm_amdgpu_cs_chunk_fence *data,
  37                                       uint32_t *offset)
  38 {
  39         struct drm_gem_object *gobj;
  40         unsigned long size;
  41
  42         gobj = drm_gem_object_lookup(p->filp, data->handle);
  43         if (gobj == NULL)
  44                 return -EINVAL;
  45
  46         p->uf_entry.robj = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
  47         p->uf_entry.priority = 0;
  48         p->uf_entry.tv.bo = &p->uf_entry.robj->tbo;
  49         p->uf_entry.tv.shared = true;
  50         p->uf_entry.user_pages = NULL;
  51
  52         size = amdgpu_bo_size(p->uf_entry.robj);
  53         if (size != PAGE_SIZE || (data->offset + 8) > size)
  54                 return -EINVAL;
  55
  56         *offset = data->offset;
  57
  58         drm_gem_object_put_unlocked(gobj);
  59
  60         if (amdgpu_ttm_tt_get_usermm(p->uf_entry.robj->tbo.ttm)) {
  61                 amdgpu_bo_unref(&p->uf_entry.robj);
  62                 return -EINVAL;
  63         }
  64
  65         return 0;
  66 }
  67
  68 static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
  69 {
  70         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
  71         struct amdgpu_vm *vm = &fpriv->vm;
  72         union drm_amdgpu_cs *cs = data;
  73         uint64_t *chunk_array_user;
  74         uint64_t *chunk_array;
  75         unsigned size, num_ibs = 0;
  76         uint32_t uf_offset = 0;
  77         int i;
  78         int ret;
  79
  80         if (cs->in.num_chunks == 0)
  81                 return 0;
  82
  83         chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
  84         if (!chunk_array)
  85                 return -ENOMEM;
  86
  87         p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
  88         if (!p->ctx) {
  89                 ret = -EINVAL;
  90                 goto free_chunk;
  91         }
  92
  93         /* skip guilty context job */
  94         if (atomic_read(&p->ctx->guilty) == 1) {
  95                 ret = -ECANCELED;
  96                 goto free_chunk;
  97         }
  98
  99         mutex_lock(&p->ctx->lock);
 100
 101         /* get chunks */
 102         chunk_array_user = u64_to_user_ptr(cs->in.chunks);
 103         if (copy_from_user(chunk_array, chunk_array_user,
 104                            sizeof(uint64_t)*cs->in.num_chunks)) {
 105                 ret = -EFAULT;
 106                 goto free_chunk;
 107         }
 108
 109         p->nchunks = cs->in.num_chunks;
 110         p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
 111                             GFP_KERNEL);
 112         if (!p->chunks) {
 113                 ret = -ENOMEM;
 114                 goto free_chunk;
 115         }
 116
 117         for (i = 0; i < p->nchunks; i++) {
 118                 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
 119                 struct drm_amdgpu_cs_chunk user_chunk;
 120                 uint32_t __user *cdata;
 121
 122                 chunk_ptr = u64_to_user_ptr(chunk_array[i]);
 123                 if (copy_from_user(&user_chunk, chunk_ptr,
 124                                        sizeof(struct drm_amdgpu_cs_chunk))) {
 125                         ret = -EFAULT;
 126                         i--;
 127                         goto free_partial_kdata;
 128                 }
 129                 p->chunks[i].chunk_id = user_chunk.chunk_id;
 130                 p->chunks[i].length_dw = user_chunk.length_dw;
 131
 132                 size = p->chunks[i].length_dw;
 133                 cdata = u64_to_user_ptr(user_chunk.chunk_data);
 134
 135                 p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
 136                 if (p->chunks[i].kdata == NULL) {
 137                         ret = -ENOMEM;
 138                         i--;
 139                         goto free_partial_kdata;
 140                 }
 141                 size *= sizeof(uint32_t);
 142                 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
 143                         ret = -EFAULT;
 144                         goto free_partial_kdata;
 145                 }
 146
 147                 switch (p->chunks[i].chunk_id) {
 148                 case AMDGPU_CHUNK_ID_IB:
 149                         ++num_ibs;
 150                         break;
 151
 152                 case AMDGPU_CHUNK_ID_FENCE:
 153                         size = sizeof(struct drm_amdgpu_cs_chunk_fence);
 154                         if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
 155                                 ret = -EINVAL;
 156                                 goto free_partial_kdata;
 157                         }
 158
 159                         ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata,
 160                                                          &uf_offset);
 161                         if (ret)
 162                                 goto free_partial_kdata;
 163
 164                         break;
 165
 166                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
 167                 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
 168                 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
 169                         break;
 170
 171                 default:
 172                         ret = -EINVAL;
 173                         goto free_partial_kdata;
 174                 }
 175         }
 176
 177         ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm);
 178         if (ret)
 179                 goto free_all_kdata;
 180
 181         if (p->ctx->vram_lost_counter != p->job->vram_lost_counter) {
 182                 ret = -ECANCELED;
 183                 goto free_all_kdata;
 184         }
 185
 186         if (p->uf_entry.robj)
 187                 p->job->uf_addr = uf_offset;
 188         kfree(chunk_array);
 189         return 0;
 190
 191 free_all_kdata:
 192         i = p->nchunks - 1;
 193 free_partial_kdata:
 194         for (; i >= 0; i--)
 195                 kvfree(p->chunks[i].kdata);
 196         kfree(p->chunks);
 197         p->chunks = NULL;
 198         p->nchunks = 0;
 199 free_chunk:
 200         kfree(chunk_array);
 201
 202         return ret;
 203 }
 204
 205 /* Convert microseconds to bytes. */
 206 static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)
 207 {
 208         if (us <= 0 || !adev->mm_stats.log2_max_MBps)
 209                 return 0;
 210
 211         /* Since accum_us is incremented by a million per second, just
 212          * multiply it by the number of MB/s to get the number of bytes.
 213          */
 214         return us << adev->mm_stats.log2_max_MBps;
 215 }
 216
 217 static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)
 218 {
 219         if (!adev->mm_stats.log2_max_MBps)
 220                 return 0;
 221
 222         return bytes >> adev->mm_stats.log2_max_MBps;
 223 }
 224
 225 /* Returns how many bytes TTM can move right now. If no bytes can be moved,
 226  * it returns 0. If it returns non-zero, it's OK to move at least one buffer,
 227  * which means it can go over the threshold once. If that happens, the driver
 228  * will be in debt and no other buffer migrations can be done until that debt
 229  * is repaid.
 230  *
 231  * This approach allows moving a buffer of any size (it's important to allow
 232  * that).
 233  *
 234  * The currency is simply time in microseconds and it increases as the clock
 235  * ticks. The accumulated microseconds (us) are converted to bytes and
 236  * returned.
 237  */
 238 static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
 239                                               u64 *max_bytes,
 240                                               u64 *max_vis_bytes)
 241 {
 242         s64 time_us, increment_us;
 243         u64 free_vram, total_vram, used_vram;
 244
 245         /* Allow a maximum of 200 accumulated ms. This is basically per-IB
 246          * throttling.
 247          *
 248          * It means that in order to get full max MBps, at least 5 IBs per
 249          * second must be submitted and not more than 200ms apart from each
 250          * other.
 251          */
 252         const s64 us_upper_bound = 200000;
 253
 254         if (!adev->mm_stats.log2_max_MBps) {
 255                 *max_bytes = 0;
 256                 *max_vis_bytes = 0;
 257                 return;
 258         }
 259
 260         total_vram = adev->gmc.real_vram_size - adev->vram_pin_size;
 261         used_vram = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 262         free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
 263
 264         spin_lock(&adev->mm_stats.lock);
 265
 266         /* Increase the amount of accumulated us. */
 267         time_us = ktime_to_us(ktime_get());
 268         increment_us = time_us - adev->mm_stats.last_update_us;
 269         adev->mm_stats.last_update_us = time_us;
 270         adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,
 271                                       us_upper_bound);
 272
 273         /* This prevents the short period of low performance when the VRAM
 274          * usage is low and the driver is in debt or doesn't have enough
 275          * accumulated us to fill VRAM quickly.
 276          *
 277          * The situation can occur in these cases:
 278          * - a lot of VRAM is freed by userspace
 279          * - the presence of a big buffer causes a lot of evictions
 280          *   (solution: split buffers into smaller ones)
 281          *
 282          * If 128 MB or 1/8th of VRAM is free, start filling it now by setting
 283          * accum_us to a positive number.
 284          */
 285         if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) {
 286                 s64 min_us;
 287
 288                 /* Be more aggresive on dGPUs. Try to fill a portion of free
 289                  * VRAM now.
 290                  */
 291                 if (!(adev->flags & AMD_IS_APU))
 292                         min_us = bytes_to_us(adev, free_vram / 4);
 293                 else
 294                         min_us = 0; /* Reset accum_us on APUs. */
 295
 296                 adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us);
 297         }
 298
 299         /* This is set to 0 if the driver is in debt to disallow (optional)
 300          * buffer moves.
 301          */
 302         *max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);
 303
 304         /* Do the same for visible VRAM if half of it is free */
 305         if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size) {
 306                 u64 total_vis_vram = adev->gmc.visible_vram_size;
 307                 u64 used_vis_vram =
 308                         amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 309
 310                 if (used_vis_vram < total_vis_vram) {
 311                         u64 free_vis_vram = total_vis_vram - used_vis_vram;
 312                         adev->mm_stats.accum_us_vis = min(adev->mm_stats.accum_us_vis +
 313                                                           increment_us, us_upper_bound);
 314
 315                         if (free_vis_vram >= total_vis_vram / 2)
 316                                 adev->mm_stats.accum_us_vis =
 317                                         max(bytes_to_us(adev, free_vis_vram / 2),
 318                                             adev->mm_stats.accum_us_vis);
 319                 }
 320
 321                 *max_vis_bytes = us_to_bytes(adev, adev->mm_stats.accum_us_vis);
 322         } else {
 323                 *max_vis_bytes = 0;
 324         }
 325
 326         spin_unlock(&adev->mm_stats.lock);
 327 }
 328
 329 /* Report how many bytes have really been moved for the last command
 330  * submission. This can result in a debt that can stop buffer migrations
 331  * temporarily.
 332  */
 333 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
 334                                   u64 num_vis_bytes)
 335 {
 336         spin_lock(&adev->mm_stats.lock);
 337         adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
 338         adev->mm_stats.accum_us_vis -= bytes_to_us(adev, num_vis_bytes);
 339         spin_unlock(&adev->mm_stats.lock);
 340 }
 341
 342 static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p,
 343                                  struct amdgpu_bo *bo)
 344 {
 345         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 346         struct ttm_operation_ctx ctx = {
 347                 .interruptible = true,
 348                 .no_wait_gpu = false,
 349                 .resv = bo->tbo.resv,
 350                 .flags = 0
 351         };
 352         uint32_t domain;
 353         int r;
 354
 355         if (bo->pin_count)
 356                 return 0;
 357
 358         /* Don't move this buffer if we have depleted our allowance
 359          * to move it. Don't move anything if the threshold is zero.
 360          */
 361         if (p->bytes_moved < p->bytes_moved_threshold) {
 362                 if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
 363                     (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
 364                         /* And don't move a CPU_ACCESS_REQUIRED BO to limited
 365                          * visible VRAM if we've depleted our allowance to do
 366                          * that.
 367                          */
 368                         if (p->bytes_moved_vis < p->bytes_moved_vis_threshold)
 369                                 domain = bo->preferred_domains;
 370                         else
 371                                 domain = bo->allowed_domains;
 372                 } else {
 373                         domain = bo->preferred_domains;
 374                 }
 375         } else {
 376                 domain = bo->allowed_domains;
 377         }
 378
 379 retry:
 380         amdgpu_ttm_placement_from_domain(bo, domain);
 381         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 382
 383         p->bytes_moved += ctx.bytes_moved;
 384         if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
 385             amdgpu_bo_in_cpu_visible_vram(bo))
 386                 p->bytes_moved_vis += ctx.bytes_moved;
 387
 388         if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains &&
 389             !(bo->flags & AMDGPU_GEM_CREATE_NO_FALLBACK)) {
 390                 domain = bo->allowed_domains;
 391                 goto retry;
 392         }
 393
 394         return r;
 395 }
 396
 397 /* Last resort, try to evict something from the current working set */
 398 static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p,
 399                                 struct amdgpu_bo *validated)
 400 {
 401         uint32_t domain = validated->allowed_domains;
 402         struct ttm_operation_ctx ctx = { true, false };
 403         int r;
 404
 405         if (!p->evictable)
 406                 return false;
 407
 408         for (;&p->evictable->tv.head != &p->validated;
 409              p->evictable = list_prev_entry(p->evictable, tv.head)) {
 410
 411                 struct amdgpu_bo_list_entry *candidate = p->evictable;
 412                 struct amdgpu_bo *bo = candidate->robj;
 413                 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 414                 bool update_bytes_moved_vis;
 415                 uint32_t other;
 416
 417                 /* If we reached our current BO we can forget it */
 418                 if (candidate->robj == validated)
 419                         break;
 420
 421                 /* We can't move pinned BOs here */
 422                 if (bo->pin_count)
 423                         continue;
 424
 425                 other = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 426
 427                 /* Check if this BO is in one of the domains we need space for */
 428                 if (!(other & domain))
 429                         continue;
 430
 431                 /* Check if we can move this BO somewhere else */
 432                 other = bo->allowed_domains & ~domain;
 433                 if (!other)
 434                         continue;
 435
 436                 /* Good we can try to move this BO somewhere else */
 437                 update_bytes_moved_vis =
 438                         adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
 439                         amdgpu_bo_in_cpu_visible_vram(bo);
 440                 amdgpu_ttm_placement_from_domain(bo, other);
 441                 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 442                 p->bytes_moved += ctx.bytes_moved;
 443                 if (update_bytes_moved_vis)
 444                         p->bytes_moved_vis += ctx.bytes_moved;
 445
 446                 if (unlikely(r))
 447                         break;
 448
 449                 p->evictable = list_prev_entry(p->evictable, tv.head);
 450                 list_move(&candidate->tv.head, &p->validated);
 451
 452                 return true;
 453         }
 454
 455         return false;
 456 }
 457
 458 static int amdgpu_cs_validate(void *param, struct amdgpu_bo *bo)
 459 {
 460         struct amdgpu_cs_parser *p = param;
 461         int r;
 462
 463         do {
 464                 r = amdgpu_cs_bo_validate(p, bo);
 465         } while (r == -ENOMEM && amdgpu_cs_try_evict(p, bo));
 466         if (r)
 467                 return r;
 468
 469         if (bo->shadow)
 470                 r = amdgpu_cs_bo_validate(p, bo->shadow);
 471
 472         return r;
 473 }
 474
 475 static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
 476                             struct list_head *validated)
 477 {
 478         struct ttm_operation_ctx ctx = { true, false };
 479         struct amdgpu_bo_list_entry *lobj;
 480         int r;
 481
 482         list_for_each_entry(lobj, validated, tv.head) {
 483                 struct amdgpu_bo *bo = lobj->robj;
 484                 bool binding_userptr = false;
 485                 struct mm_struct *usermm;
 486
 487                 usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
 488                 if (usermm && usermm != current->mm)
 489                         return -EPERM;
 490
 491                 /* Check if we have user pages and nobody bound the BO already */
 492                 if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) &&
 493                     lobj->user_pages) {
 494                         amdgpu_ttm_placement_from_domain(bo,
 495                                                          AMDGPU_GEM_DOMAIN_CPU);
 496                         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 497                         if (r)
 498                                 return r;
 499                         amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
 500                                                      lobj->user_pages);
 501                         binding_userptr = true;
 502                 }
 503
 504                 if (p->evictable == lobj)
 505                         p->evictable = NULL;
 506
 507                 r = amdgpu_cs_validate(p, bo);
 508                 if (r)
 509                         return r;
 510
 511                 if (binding_userptr) {
 512                         kvfree(lobj->user_pages);
 513                         lobj->user_pages = NULL;
 514                 }
 515         }
 516         return 0;
 517 }
 518
 519 static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
 520                                 union drm_amdgpu_cs *cs)
 521 {
 522         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 523         struct amdgpu_bo_list_entry *e;
 524         struct list_head duplicates;
 525         unsigned i, tries = 10;
 526         int r;
 527
 528         INIT_LIST_HEAD(&p->validated);
 529
 530         p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
 531         if (p->bo_list) {
 532                 amdgpu_bo_list_get_list(p->bo_list, &p->validated);
 533                 if (p->bo_list->first_userptr != p->bo_list->num_entries)
 534                         p->mn = amdgpu_mn_get(p->adev);
 535         }
 536
 537         INIT_LIST_HEAD(&duplicates);
 538         amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
 539
 540         if (p->uf_entry.robj && !p->uf_entry.robj->parent)
 541                 list_add(&p->uf_entry.tv.head, &p->validated);
 542
 543         while (1) {
 544                 struct list_head need_pages;
 545                 unsigned i;
 546
 547                 r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
 548                                            &duplicates);
 549                 if (unlikely(r != 0)) {
 550                         if (r != -ERESTARTSYS)
 551                                 DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
 552                         goto error_free_pages;
 553                 }
 554
 555                 /* Without a BO list we don't have userptr BOs */
 556                 if (!p->bo_list)
 557                         break;
 558
 559                 INIT_LIST_HEAD(&need_pages);
 560                 for (i = p->bo_list->first_userptr;
 561                      i < p->bo_list->num_entries; ++i) {
 562                         struct amdgpu_bo *bo;
 563
 564                         e = &p->bo_list->array[i];
 565                         bo = e->robj;
 566
 567                         if (amdgpu_ttm_tt_userptr_invalidated(bo->tbo.ttm,
 568                                  &e->user_invalidated) && e->user_pages) {
 569
 570                                 /* We acquired a page array, but somebody
 571                                  * invalidated it. Free it and try again
 572                                  */
 573                                 release_pages(e->user_pages,
 574                                               bo->tbo.ttm->num_pages);
 575                                 kvfree(e->user_pages);
 576                                 e->user_pages = NULL;
 577                         }
 578
 579                         if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) &&
 580                             !e->user_pages) {
 581                                 list_del(&e->tv.head);
 582                                 list_add(&e->tv.head, &need_pages);
 583
 584                                 amdgpu_bo_unreserve(e->robj);
 585                         }
 586                 }
 587
 588                 if (list_empty(&need_pages))
 589                         break;
 590
 591                 /* Unreserve everything again. */
 592                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 593
 594                 /* We tried too many times, just abort */
 595                 if (!--tries) {
 596                         r = -EDEADLK;
 597                         DRM_ERROR("deadlock in %s\n", __func__);
 598                         goto error_free_pages;
 599                 }
 600
 601                 /* Fill the page arrays for all userptrs. */
 602                 list_for_each_entry(e, &need_pages, tv.head) {
 603                         struct ttm_tt *ttm = e->robj->tbo.ttm;
 604
 605                         e->user_pages = kvmalloc_array(ttm->num_pages,
 606                                                          sizeof(struct page*),
 607                                                          GFP_KERNEL | __GFP_ZERO);
 608                         if (!e->user_pages) {
 609                                 r = -ENOMEM;
 610                                 DRM_ERROR("calloc failure in %s\n", __func__);
 611                                 goto error_free_pages;
 612                         }
 613
 614                         r = amdgpu_ttm_tt_get_user_pages(ttm, e->user_pages);
 615                         if (r) {
 616                                 DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n");
 617                                 kvfree(e->user_pages);
 618                                 e->user_pages = NULL;
 619                                 goto error_free_pages;
 620                         }
 621                 }
 622
 623                 /* And try again. */
 624                 list_splice(&need_pages, &p->validated);
 625         }
 626
 627         amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold,
 628                                           &p->bytes_moved_vis_threshold);
 629         p->bytes_moved = 0;
 630         p->bytes_moved_vis = 0;
 631         p->evictable = list_last_entry(&p->validated,
 632                                        struct amdgpu_bo_list_entry,
 633                                        tv.head);
 634
 635         r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm,
 636                                       amdgpu_cs_validate, p);
 637         if (r) {
 638                 DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
 639                 goto error_validate;
 640         }
 641
 642         r = amdgpu_cs_list_validate(p, &duplicates);
 643         if (r) {
 644                 DRM_ERROR("amdgpu_cs_list_validate(duplicates) failed.\n");
 645                 goto error_validate;
 646         }
 647
 648         r = amdgpu_cs_list_validate(p, &p->validated);
 649         if (r) {
 650                 DRM_ERROR("amdgpu_cs_list_validate(validated) failed.\n");
 651                 goto error_validate;
 652         }
 653
 654         amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved,
 655                                      p->bytes_moved_vis);
 656         if (p->bo_list) {
 657                 struct amdgpu_bo *gds = p->bo_list->gds_obj;
 658                 struct amdgpu_bo *gws = p->bo_list->gws_obj;
 659                 struct amdgpu_bo *oa = p->bo_list->oa_obj;
 660                 struct amdgpu_vm *vm = &fpriv->vm;
 661                 unsigned i;
 662
 663                 for (i = 0; i < p->bo_list->num_entries; i++) {
 664                         struct amdgpu_bo *bo = p->bo_list->array[i].robj;
 665
 666                         p->bo_list->array[i].bo_va = amdgpu_vm_bo_find(vm, bo);
 667                 }
 668
 669                 if (gds) {
 670                         p->job->gds_base = amdgpu_bo_gpu_offset(gds);
 671                         p->job->gds_size = amdgpu_bo_size(gds);
 672                 }
 673                 if (gws) {
 674                         p->job->gws_base = amdgpu_bo_gpu_offset(gws);
 675                         p->job->gws_size = amdgpu_bo_size(gws);
 676                 }
 677                 if (oa) {
 678                         p->job->oa_base = amdgpu_bo_gpu_offset(oa);
 679                         p->job->oa_size = amdgpu_bo_size(oa);
 680                 }
 681         }
 682
 683         if (!r && p->uf_entry.robj) {
 684                 struct amdgpu_bo *uf = p->uf_entry.robj;
 685
 686                 r = amdgpu_ttm_alloc_gart(&uf->tbo);
 687                 p->job->uf_addr += amdgpu_bo_gpu_offset(uf);
 688         }
 689
 690 error_validate:
 691         if (r)
 692                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 693
 694 error_free_pages:
 695
 696         if (p->bo_list) {
 697                 for (i = p->bo_list->first_userptr;
 698                      i < p->bo_list->num_entries; ++i) {
 699                         e = &p->bo_list->array[i];
 700
 701                         if (!e->user_pages)
 702                                 continue;
 703
 704                         release_pages(e->user_pages,
 705                                       e->robj->tbo.ttm->num_pages);
 706                         kvfree(e->user_pages);
 707                 }
 708         }
 709
 710         return r;
 711 }
 712
 713 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
 714 {
 715         struct amdgpu_bo_list_entry *e;
 716         int r;
 717
 718         list_for_each_entry(e, &p->validated, tv.head) {
 719                 struct reservation_object *resv = e->robj->tbo.resv;
 720                 r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp,
 721                                      amdgpu_bo_explicit_sync(e->robj));
 722
 723                 if (r)
 724                         return r;
 725         }
 726         return 0;
 727 }
 728
 729 /**
 730  * cs_parser_fini() - clean parser states
 731  * @parser:     parser structure holding parsing context.
 732  * @error:      error number
 733  *
 734  * If error is set than unvalidate buffer, otherwise just free memory
 735  * used by parsing context.
 736  **/
 737 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error,
 738                                   bool backoff)
 739 {
 740         unsigned i;
 741
 742         if (error && backoff)
 743                 ttm_eu_backoff_reservation(&parser->ticket,
 744                                            &parser->validated);
 745
 746         for (i = 0; i < parser->num_post_dep_syncobjs; i++)
 747                 drm_syncobj_put(parser->post_dep_syncobjs[i]);
 748         kfree(parser->post_dep_syncobjs);
 749
 750         dma_fence_put(parser->fence);
 751
 752         if (parser->ctx) {
 753                 mutex_unlock(&parser->ctx->lock);
 754                 amdgpu_ctx_put(parser->ctx);
 755         }
 756         if (parser->bo_list)
 757                 amdgpu_bo_list_put(parser->bo_list);
 758
 759         for (i = 0; i < parser->nchunks; i++)
 760                 kvfree(parser->chunks[i].kdata);
 761         kfree(parser->chunks);
 762         if (parser->job)
 763                 amdgpu_job_free(parser->job);
 764         amdgpu_bo_unref(&parser->uf_entry.robj);
 765 }
 766
 767 static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p)
 768 {
 769         struct amdgpu_device *adev = p->adev;
 770         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 771         struct amdgpu_vm *vm = &fpriv->vm;
 772         struct amdgpu_bo_va *bo_va;
 773         struct amdgpu_bo *bo;
 774         int i, r;
 775
 776         r = amdgpu_vm_clear_freed(adev, vm, NULL);
 777         if (r)
 778                 return r;
 779
 780         r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false);
 781         if (r)
 782                 return r;
 783
 784         r = amdgpu_sync_fence(adev, &p->job->sync,
 785                               fpriv->prt_va->last_pt_update, false);
 786         if (r)
 787                 return r;
 788
 789         if (amdgpu_sriov_vf(adev)) {
 790                 struct dma_fence *f;
 791
 792                 bo_va = fpriv->csa_va;
 793                 BUG_ON(!bo_va);
 794                 r = amdgpu_vm_bo_update(adev, bo_va, false);
 795                 if (r)
 796                         return r;
 797
 798                 f = bo_va->last_pt_update;
 799                 r = amdgpu_sync_fence(adev, &p->job->sync, f, false);
 800                 if (r)
 801                         return r;
 802         }
 803
 804         if (p->bo_list) {
 805                 for (i = 0; i < p->bo_list->num_entries; i++) {
 806                         struct dma_fence *f;
 807
 808                         /* ignore duplicates */
 809                         bo = p->bo_list->array[i].robj;
 810                         if (!bo)
 811                                 continue;
 812
 813                         bo_va = p->bo_list->array[i].bo_va;
 814                         if (bo_va == NULL)
 815                                 continue;
 816
 817                         r = amdgpu_vm_bo_update(adev, bo_va, false);
 818                         if (r)
 819                                 return r;
 820
 821                         f = bo_va->last_pt_update;
 822                         r = amdgpu_sync_fence(adev, &p->job->sync, f, false);
 823                         if (r)
 824                                 return r;
 825                 }
 826
 827         }
 828
 829         r = amdgpu_vm_handle_moved(adev, vm);
 830         if (r)
 831                 return r;
 832
 833         r = amdgpu_vm_update_directories(adev, vm);
 834         if (r)
 835                 return r;
 836
 837         r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_update, false);
 838         if (r)
 839                 return r;
 840
 841         if (amdgpu_vm_debug && p->bo_list) {
 842                 /* Invalidate all BOs to test for userspace bugs */
 843                 for (i = 0; i < p->bo_list->num_entries; i++) {
 844                         /* ignore duplicates */
 845                         bo = p->bo_list->array[i].robj;
 846                         if (!bo)
 847                                 continue;
 848
 849                         amdgpu_vm_bo_invalidate(adev, bo, false);
 850                 }
 851         }
 852
 853         return r;
 854 }
 855
 856 static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
 857                                  struct amdgpu_cs_parser *p)
 858 {
 859         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 860         struct amdgpu_vm *vm = &fpriv->vm;
 861         struct amdgpu_ring *ring = p->job->ring;
 862         int r;
 863
 864         /* Only for UVD/VCE VM emulation */
 865         if (p->job->ring->funcs->parse_cs) {
 866                 unsigned i, j;
 867
 868                 for (i = 0, j = 0; i < p->nchunks && j < p->job->num_ibs; i++) {
 869                         struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 870                         struct amdgpu_bo_va_mapping *m;
 871                         struct amdgpu_bo *aobj = NULL;
 872                         struct amdgpu_cs_chunk *chunk;
 873                         uint64_t offset, va_start;
 874                         struct amdgpu_ib *ib;
 875                         uint8_t *kptr;
 876
 877                         chunk = &p->chunks[i];
 878                         ib = &p->job->ibs[j];
 879                         chunk_ib = chunk->kdata;
 880
 881                         if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 882                                 continue;
 883
 884                         va_start = chunk_ib->va_start & AMDGPU_VA_HOLE_MASK;
 885                         r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m);
 886                         if (r) {
 887                                 DRM_ERROR("IB va_start is invalid\n");
 888                                 return r;
 889                         }
 890
 891                         if ((va_start + chunk_ib->ib_bytes) >
 892                             (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 893                                 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
 894                                 return -EINVAL;
 895                         }
 896
 897                         /* the IB should be reserved at this point */
 898                         r = amdgpu_bo_kmap(aobj, (void **)&kptr);
 899                         if (r) {
 900                                 return r;
 901                         }
 902
 903                         offset = m->start * AMDGPU_GPU_PAGE_SIZE;
 904                         kptr += va_start - offset;
 905
 906                         memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
 907                         amdgpu_bo_kunmap(aobj);
 908
 909                         r = amdgpu_ring_parse_cs(ring, p, j);
 910                         if (r)
 911                                 return r;
 912
 913                         j++;
 914                 }
 915         }
 916
 917         if (p->job->vm) {
 918                 p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->root.base.bo);
 919
 920                 r = amdgpu_bo_vm_update_pte(p);
 921                 if (r)
 922                         return r;
 923         }
 924
 925         return amdgpu_cs_sync_rings(p);
 926 }
 927
 928 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
 929                              struct amdgpu_cs_parser *parser)
 930 {
 931         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 932         struct amdgpu_vm *vm = &fpriv->vm;
 933         int i, j;
 934         int r, ce_preempt = 0, de_preempt = 0;
 935
 936         for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) {
 937                 struct amdgpu_cs_chunk *chunk;
 938                 struct amdgpu_ib *ib;
 939                 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 940                 struct amdgpu_ring *ring;
 941
 942                 chunk = &parser->chunks[i];
 943                 ib = &parser->job->ibs[j];
 944                 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
 945
 946                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 947                         continue;
 948
 949                 if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX && amdgpu_sriov_vf(adev)) {
 950                         if (chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
 951                                 if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
 952                                         ce_preempt++;
 953                                 else
 954                                         de_preempt++;
 955                         }
 956
 957                         /* each GFX command submit allows 0 or 1 IB preemptible for CE & DE */
 958                         if (ce_preempt > 1 || de_preempt > 1)
 959                                 return -EINVAL;
 960                 }
 961
 962                 r = amdgpu_queue_mgr_map(adev, &parser->ctx->queue_mgr, chunk_ib->ip_type,
 963                                          chunk_ib->ip_instance, chunk_ib->ring, &ring);
 964                 if (r)
 965                         return r;
 966
 967                 if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE) {
 968                         parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT;
 969                         if (!parser->ctx->preamble_presented) {
 970                                 parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;
 971                                 parser->ctx->preamble_presented = true;
 972                         }
 973                 }
 974
 975                 if (parser->job->ring && parser->job->ring != ring)
 976                         return -EINVAL;
 977
 978                 parser->job->ring = ring;
 979
 980                 r =  amdgpu_ib_get(adev, vm,
 981                                         ring->funcs->parse_cs ? chunk_ib->ib_bytes : 0,
 982                                         ib);
 983                 if (r) {
 984                         DRM_ERROR("Failed to get ib !\n");
 985                         return r;
 986                 }
 987
 988                 ib->gpu_addr = chunk_ib->va_start;
 989                 ib->length_dw = chunk_ib->ib_bytes / 4;
 990                 ib->flags = chunk_ib->flags;
 991
 992                 j++;
 993         }
 994
 995         /* UVD & VCE fw doesn't support user fences */
 996         if (parser->job->uf_addr && (
 997             parser->job->ring->funcs->type == AMDGPU_RING_TYPE_UVD ||
 998             parser->job->ring->funcs->type == AMDGPU_RING_TYPE_VCE))
 999                 return -EINVAL;
1000
1001         return amdgpu_ctx_wait_prev_fence(parser->ctx, parser->job->ring->idx);
1002 }
1003
1004 static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,
1005                                        struct amdgpu_cs_chunk *chunk)
1006 {
1007         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1008         unsigned num_deps;
1009         int i, r;
1010         struct drm_amdgpu_cs_chunk_dep *deps;
1011
1012         deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
1013         num_deps = chunk->length_dw * 4 /
1014                 sizeof(struct drm_amdgpu_cs_chunk_dep);
1015
1016         for (i = 0; i < num_deps; ++i) {
1017                 struct amdgpu_ring *ring;
1018                 struct amdgpu_ctx *ctx;
1019                 struct dma_fence *fence;
1020
1021                 ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
1022                 if (ctx == NULL)
1023                         return -EINVAL;
1024
1025                 r = amdgpu_queue_mgr_map(p->adev, &ctx->queue_mgr,
1026                                          deps[i].ip_type,
1027                                          deps[i].ip_instance,
1028                                          deps[i].ring, &ring);
1029                 if (r) {
1030                         amdgpu_ctx_put(ctx);
1031                         return r;
1032                 }
1033
1034                 fence = amdgpu_ctx_get_fence(ctx, ring,
1035                                              deps[i].handle);
1036                 if (IS_ERR(fence)) {
1037                         r = PTR_ERR(fence);
1038                         amdgpu_ctx_put(ctx);
1039                         return r;
1040                 } else if (fence) {
1041                         r = amdgpu_sync_fence(p->adev, &p->job->sync, fence,
1042                                         true);
1043                         dma_fence_put(fence);
1044                         amdgpu_ctx_put(ctx);
1045                         if (r)
1046                                 return r;
1047                 }
1048         }
1049         return 0;
1050 }
1051
1052 static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,
1053                                                  uint32_t handle)
1054 {
1055         int r;
1056         struct dma_fence *fence;
1057         r = drm_syncobj_find_fence(p->filp, handle, &fence);
1058         if (r)
1059                 return r;
1060
1061         r = amdgpu_sync_fence(p->adev, &p->job->sync, fence, true);
1062         dma_fence_put(fence);
1063
1064         return r;
1065 }
1066
1067 static int amdgpu_cs_process_syncobj_in_dep(struct amdgpu_cs_parser *p,
1068                                             struct amdgpu_cs_chunk *chunk)
1069 {
1070         unsigned num_deps;
1071         int i, r;
1072         struct drm_amdgpu_cs_chunk_sem *deps;
1073
1074         deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1075         num_deps = chunk->length_dw * 4 /
1076                 sizeof(struct drm_amdgpu_cs_chunk_sem);
1077
1078         for (i = 0; i < num_deps; ++i) {
1079                 r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle);
1080                 if (r)
1081                         return r;
1082         }
1083         return 0;
1084 }
1085
1086 static int amdgpu_cs_process_syncobj_out_dep(struct amdgpu_cs_parser *p,
1087                                              struct amdgpu_cs_chunk *chunk)
1088 {
1089         unsigned num_deps;
1090         int i;
1091         struct drm_amdgpu_cs_chunk_sem *deps;
1092         deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1093         num_deps = chunk->length_dw * 4 /
1094                 sizeof(struct drm_amdgpu_cs_chunk_sem);
1095
1096         p->post_dep_syncobjs = kmalloc_array(num_deps,
1097                                              sizeof(struct drm_syncobj *),
1098                                              GFP_KERNEL);
1099         p->num_post_dep_syncobjs = 0;
1100
1101         if (!p->post_dep_syncobjs)
1102                 return -ENOMEM;
1103
1104         for (i = 0; i < num_deps; ++i) {
1105                 p->post_dep_syncobjs[i] = drm_syncobj_find(p->filp, deps[i].handle);
1106                 if (!p->post_dep_syncobjs[i])
1107                         return -EINVAL;
1108                 p->num_post_dep_syncobjs++;
1109         }
1110         return 0;
1111 }
1112
1113 static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
1114                                   struct amdgpu_cs_parser *p)
1115 {
1116         int i, r;
1117
1118         for (i = 0; i < p->nchunks; ++i) {
1119                 struct amdgpu_cs_chunk *chunk;
1120
1121                 chunk = &p->chunks[i];
1122
1123                 if (chunk->chunk_id == AMDGPU_CHUNK_ID_DEPENDENCIES) {
1124                         r = amdgpu_cs_process_fence_dep(p, chunk);
1125                         if (r)
1126                                 return r;
1127                 } else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_IN) {
1128                         r = amdgpu_cs_process_syncobj_in_dep(p, chunk);
1129                         if (r)
1130                                 return r;
1131                 } else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_OUT) {
1132                         r = amdgpu_cs_process_syncobj_out_dep(p, chunk);
1133                         if (r)
1134                                 return r;
1135                 }
1136         }
1137
1138         return 0;
1139 }
1140
1141 static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p)
1142 {
1143         int i;
1144
1145         for (i = 0; i < p->num_post_dep_syncobjs; ++i)
1146                 drm_syncobj_replace_fence(p->post_dep_syncobjs[i], p->fence);
1147 }
1148
1149 static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
1150                             union drm_amdgpu_cs *cs)
1151 {
1152         struct amdgpu_ring *ring = p->job->ring;
1153         struct drm_sched_entity *entity = &p->ctx->rings[ring->idx].entity;
1154         struct amdgpu_job *job;
1155         unsigned i;
1156         uint64_t seq;
1157
1158         int r;
1159
1160         amdgpu_mn_lock(p->mn);
1161         if (p->bo_list) {
1162                 for (i = p->bo_list->first_userptr;
1163                      i < p->bo_list->num_entries; ++i) {
1164                         struct amdgpu_bo *bo = p->bo_list->array[i].robj;
1165
1166                         if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm)) {
1167                                 amdgpu_mn_unlock(p->mn);
1168                                 return -ERESTARTSYS;
1169                         }
1170                 }
1171         }
1172
1173         job = p->job;
1174         p->job = NULL;
1175
1176         r = drm_sched_job_init(&job->base, &ring->sched, entity, p->filp);
1177         if (r) {
1178                 amdgpu_job_free(job);
1179                 amdgpu_mn_unlock(p->mn);
1180                 return r;
1181         }
1182
1183         job->owner = p->filp;
1184         job->fence_ctx = entity->fence_context;
1185         p->fence = dma_fence_get(&job->base.s_fence->finished);
1186
1187         r = amdgpu_ctx_add_fence(p->ctx, ring, p->fence, &seq);
1188         if (r) {
1189                 dma_fence_put(p->fence);
1190                 dma_fence_put(&job->base.s_fence->finished);
1191                 amdgpu_job_free(job);
1192                 amdgpu_mn_unlock(p->mn);
1193                 return r;
1194         }
1195
1196         amdgpu_cs_post_dependencies(p);
1197
1198         cs->out.handle = seq;
1199         job->uf_sequence = seq;
1200
1201         amdgpu_job_free_resources(job);
1202         amdgpu_ring_priority_get(job->ring, job->base.s_priority);
1203
1204         trace_amdgpu_cs_ioctl(job);
1205         drm_sched_entity_push_job(&job->base, entity);
1206
1207         ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence);
1208         amdgpu_mn_unlock(p->mn);
1209
1210         return 0;
1211 }
1212
1213 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
1214 {
1215         struct amdgpu_device *adev = dev->dev_private;
1216         union drm_amdgpu_cs *cs = data;
1217         struct amdgpu_cs_parser parser = {};
1218         bool reserved_buffers = false;
1219         int i, r;
1220
1221         if (!adev->accel_working)
1222                 return -EBUSY;
1223
1224         parser.adev = adev;
1225         parser.filp = filp;
1226
1227         r = amdgpu_cs_parser_init(&parser, data);
1228         if (r) {
1229                 DRM_ERROR("Failed to initialize parser !\n");
1230                 goto out;
1231         }
1232
1233         r = amdgpu_cs_ib_fill(adev, &parser);
1234         if (r)
1235                 goto out;
1236
1237         r = amdgpu_cs_parser_bos(&parser, data);
1238         if (r) {
1239                 if (r == -ENOMEM)
1240                         DRM_ERROR("Not enough memory for command submission!\n");
1241                 else if (r != -ERESTARTSYS)
1242                         DRM_ERROR("Failed to process the buffer list %d!\n", r);
1243                 goto out;
1244         }
1245
1246         reserved_buffers = true;
1247
1248         r = amdgpu_cs_dependencies(adev, &parser);
1249         if (r) {
1250                 DRM_ERROR("Failed in the dependencies handling %d!\n", r);
1251                 goto out;
1252         }
1253
1254         for (i = 0; i < parser.job->num_ibs; i++)
1255                 trace_amdgpu_cs(&parser, i);
1256
1257         r = amdgpu_cs_ib_vm_chunk(adev, &parser);
1258         if (r)
1259                 goto out;
1260
1261         r = amdgpu_cs_submit(&parser, cs);
1262
1263 out:
1264         amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
1265         return r;
1266 }
1267
1268 /**
1269  * amdgpu_cs_wait_ioctl - wait for a command submission to finish
1270  *
1271  * @dev: drm device
1272  * @data: data from userspace
1273  * @filp: file private
1274  *
1275  * Wait for the command submission identified by handle to finish.
1276  */
1277 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
1278                          struct drm_file *filp)
1279 {
1280         union drm_amdgpu_wait_cs *wait = data;
1281         struct amdgpu_device *adev = dev->dev_private;
1282         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
1283         struct amdgpu_ring *ring = NULL;
1284         struct amdgpu_ctx *ctx;
1285         struct dma_fence *fence;
1286         long r;
1287
1288         ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
1289         if (ctx == NULL)
1290                 return -EINVAL;
1291
1292         r = amdgpu_queue_mgr_map(adev, &ctx->queue_mgr,
1293                                  wait->in.ip_type, wait->in.ip_instance,
1294                                  wait->in.ring, &ring);
1295         if (r) {
1296                 amdgpu_ctx_put(ctx);
1297                 return r;
1298         }
1299
1300         fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle);
1301         if (IS_ERR(fence))
1302                 r = PTR_ERR(fence);
1303         else if (fence) {
1304                 r = dma_fence_wait_timeout(fence, true, timeout);
1305                 if (r > 0 && fence->error)
1306                         r = fence->error;
1307                 dma_fence_put(fence);
1308         } else
1309                 r = 1;
1310
1311         amdgpu_ctx_put(ctx);
1312         if (r < 0)
1313                 return r;
1314
1315         memset(wait, 0, sizeof(*wait));
1316         wait->out.status = (r == 0);
1317
1318         return 0;
1319 }
1320
1321 /**
1322  * amdgpu_cs_get_fence - helper to get fence from drm_amdgpu_fence
1323  *
1324  * @adev: amdgpu device
1325  * @filp: file private
1326  * @user: drm_amdgpu_fence copied from user space
1327  */
1328 static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev,
1329                                              struct drm_file *filp,
1330                                              struct drm_amdgpu_fence *user)
1331 {
1332         struct amdgpu_ring *ring;
1333         struct amdgpu_ctx *ctx;
1334         struct dma_fence *fence;
1335         int r;
1336
1337         ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id);
1338         if (ctx == NULL)
1339                 return ERR_PTR(-EINVAL);
1340
1341         r = amdgpu_queue_mgr_map(adev, &ctx->queue_mgr, user->ip_type,
1342                                  user->ip_instance, user->ring, &ring);
1343         if (r) {
1344                 amdgpu_ctx_put(ctx);
1345                 return ERR_PTR(r);
1346         }
1347
1348         fence = amdgpu_ctx_get_fence(ctx, ring, user->seq_no);
1349         amdgpu_ctx_put(ctx);
1350
1351         return fence;
1352 }
1353
1354 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
1355                                     struct drm_file *filp)
1356 {
1357         struct amdgpu_device *adev = dev->dev_private;
1358         union drm_amdgpu_fence_to_handle *info = data;
1359         struct dma_fence *fence;
1360         struct drm_syncobj *syncobj;
1361         struct sync_file *sync_file;
1362         int fd, r;
1363
1364         fence = amdgpu_cs_get_fence(adev, filp, &info->in.fence);
1365         if (IS_ERR(fence))
1366                 return PTR_ERR(fence);
1367
1368         switch (info->in.what) {
1369         case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
1370                 r = drm_syncobj_create(&syncobj, 0, fence);
1371                 dma_fence_put(fence);
1372                 if (r)
1373                         return r;
1374                 r = drm_syncobj_get_handle(filp, syncobj, &info->out.handle);
1375                 drm_syncobj_put(syncobj);
1376                 return r;
1377
1378         case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD:
1379                 r = drm_syncobj_create(&syncobj, 0, fence);
1380                 dma_fence_put(fence);
1381                 if (r)
1382                         return r;
1383                 r = drm_syncobj_get_fd(syncobj, (int*)&info->out.handle);
1384                 drm_syncobj_put(syncobj);
1385                 return r;
1386
1387         case AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD:
1388                 fd = get_unused_fd_flags(O_CLOEXEC);
1389                 if (fd < 0) {
1390                         dma_fence_put(fence);
1391                         return fd;
1392                 }
1393
1394                 sync_file = sync_file_create(fence);
1395                 dma_fence_put(fence);
1396                 if (!sync_file) {
1397                         put_unused_fd(fd);
1398                         return -ENOMEM;
1399                 }
1400
1401                 fd_install(fd, sync_file->file);
1402                 info->out.handle = fd;
1403                 return 0;
1404
1405         default:
1406                 return -EINVAL;
1407         }
1408 }
1409
1410 /**
1411  * amdgpu_cs_wait_all_fence - wait on all fences to signal
1412  *
1413  * @adev: amdgpu device
1414  * @filp: file private
1415  * @wait: wait parameters
1416  * @fences: array of drm_amdgpu_fence
1417  */
1418 static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
1419                                      struct drm_file *filp,
1420                                      union drm_amdgpu_wait_fences *wait,
1421                                      struct drm_amdgpu_fence *fences)
1422 {
1423         uint32_t fence_count = wait->in.fence_count;
1424         unsigned int i;
1425         long r = 1;
1426
1427         for (i = 0; i < fence_count; i++) {
1428                 struct dma_fence *fence;
1429                 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1430
1431                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1432                 if (IS_ERR(fence))
1433                         return PTR_ERR(fence);
1434                 else if (!fence)
1435                         continue;
1436
1437                 r = dma_fence_wait_timeout(fence, true, timeout);
1438                 dma_fence_put(fence);
1439                 if (r < 0)
1440                         return r;
1441
1442                 if (r == 0)
1443                         break;
1444
1445                 if (fence->error)
1446                         return fence->error;
1447         }
1448
1449         memset(wait, 0, sizeof(*wait));
1450         wait->out.status = (r > 0);
1451
1452         return 0;
1453 }
1454
1455 /**
1456  * amdgpu_cs_wait_any_fence - wait on any fence to signal
1457  *
1458  * @adev: amdgpu device
1459  * @filp: file private
1460  * @wait: wait parameters
1461  * @fences: array of drm_amdgpu_fence
1462  */
1463 static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev,
1464                                     struct drm_file *filp,
1465                                     union drm_amdgpu_wait_fences *wait,
1466                                     struct drm_amdgpu_fence *fences)
1467 {
1468         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1469         uint32_t fence_count = wait->in.fence_count;
1470         uint32_t first = ~0;
1471         struct dma_fence **array;
1472         unsigned int i;
1473         long r;
1474
1475         /* Prepare the fence array */
1476         array = kcalloc(fence_count, sizeof(struct dma_fence *), GFP_KERNEL);
1477
1478         if (array == NULL)
1479                 return -ENOMEM;
1480
1481         for (i = 0; i < fence_count; i++) {
1482                 struct dma_fence *fence;
1483
1484                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1485                 if (IS_ERR(fence)) {
1486                         r = PTR_ERR(fence);
1487                         goto err_free_fence_array;
1488                 } else if (fence) {
1489                         array[i] = fence;
1490                 } else { /* NULL, the fence has been already signaled */
1491                         r = 1;
1492                         first = i;
1493                         goto out;
1494                 }
1495         }
1496
1497         r = dma_fence_wait_any_timeout(array, fence_count, true, timeout,
1498                                        &first);
1499         if (r < 0)
1500                 goto err_free_fence_array;
1501
1502 out:
1503         memset(wait, 0, sizeof(*wait));
1504         wait->out.status = (r > 0);
1505         wait->out.first_signaled = first;
1506
1507         if (first < fence_count && array[first])
1508                 r = array[first]->error;
1509         else
1510                 r = 0;
1511
1512 err_free_fence_array:
1513         for (i = 0; i < fence_count; i++)
1514                 dma_fence_put(array[i]);
1515         kfree(array);
1516
1517         return r;
1518 }
1519
1520 /**
1521  * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to finish
1522  *
1523  * @dev: drm device
1524  * @data: data from userspace
1525  * @filp: file private
1526  */
1527 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1528                                 struct drm_file *filp)
1529 {
1530         struct amdgpu_device *adev = dev->dev_private;
1531         union drm_amdgpu_wait_fences *wait = data;
1532         uint32_t fence_count = wait->in.fence_count;
1533         struct drm_amdgpu_fence *fences_user;
1534         struct drm_amdgpu_fence *fences;
1535         int r;
1536
1537         /* Get the fences from userspace */
1538         fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence),
1539                         GFP_KERNEL);
1540         if (fences == NULL)
1541                 return -ENOMEM;
1542
1543         fences_user = u64_to_user_ptr(wait->in.fences);
1544         if (copy_from_user(fences, fences_user,
1545                 sizeof(struct drm_amdgpu_fence) * fence_count)) {
1546                 r = -EFAULT;
1547                 goto err_free_fences;
1548         }
1549
1550         if (wait->in.wait_all)
1551                 r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences);
1552         else
1553                 r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences);
1554
1555 err_free_fences:
1556         kfree(fences);
1557
1558         return r;
1559 }
1560
1561 /**
1562  * amdgpu_cs_find_bo_va - find bo_va for VM address
1563  *
1564  * @parser: command submission parser context
1565  * @addr: VM address
1566  * @bo: resulting BO of the mapping found
1567  *
1568  * Search the buffer objects in the command submission context for a certain
1569  * virtual memory address. Returns allocation structure when found, NULL
1570  * otherwise.
1571  */
1572 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1573                            uint64_t addr, struct amdgpu_bo **bo,
1574                            struct amdgpu_bo_va_mapping **map)
1575 {
1576         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
1577         struct ttm_operation_ctx ctx = { false, false };
1578         struct amdgpu_vm *vm = &fpriv->vm;
1579         struct amdgpu_bo_va_mapping *mapping;
1580         int r;
1581
1582         addr /= AMDGPU_GPU_PAGE_SIZE;
1583
1584         mapping = amdgpu_vm_bo_lookup_mapping(vm, addr);
1585         if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo)
1586                 return -EINVAL;
1587
1588         *bo = mapping->bo_va->base.bo;
1589         *map = mapping;
1590
1591         /* Double check that the BO is reserved by this CS */
1592         if (READ_ONCE((*bo)->tbo.resv->lock.ctx) != &parser->ticket)
1593                 return -EINVAL;
1594
1595         if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {
1596                 (*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1597                 amdgpu_ttm_placement_from_domain(*bo, (*bo)->allowed_domains);
1598                 r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, &ctx);
1599                 if (r)
1600                         return r;
1601         }
1602
1603         return amdgpu_ttm_alloc_gart(&(*bo)->tbo);
1604 }