drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <linux/list.h>
  33 #include <linux/slab.h>
  34 #include <drm/drmP.h>
  35 #include <drm/amdgpu_drm.h>
  36 #include <drm/drm_cache.h>
  37 #include "amdgpu.h"
  38 #include "amdgpu_trace.h"
  39
  40
  41
  42 static u64 amdgpu_get_vis_part_size(struct amdgpu_device *adev,
  43                                                 struct ttm_mem_reg *mem)
  44 {
  45         if (mem->start << PAGE_SHIFT >= adev->mc.visible_vram_size)
  46                 return 0;
  47
  48         return ((mem->start << PAGE_SHIFT) + mem->size) >
  49                 adev->mc.visible_vram_size ?
  50                 adev->mc.visible_vram_size - (mem->start << PAGE_SHIFT) :
  51                 mem->size;
  52 }
  53
  54 static void amdgpu_update_memory_usage(struct amdgpu_device *adev,
  55                        struct ttm_mem_reg *old_mem,
  56                        struct ttm_mem_reg *new_mem)
  57 {
  58         u64 vis_size;
  59         if (!adev)
  60                 return;
  61
  62         if (new_mem) {
  63                 switch (new_mem->mem_type) {
  64                 case TTM_PL_TT:
  65                         atomic64_add(new_mem->size, &adev->gtt_usage);
  66                         break;
  67                 case TTM_PL_VRAM:
  68                         atomic64_add(new_mem->size, &adev->vram_usage);
  69                         vis_size = amdgpu_get_vis_part_size(adev, new_mem);
  70                         atomic64_add(vis_size, &adev->vram_vis_usage);
  71                         break;
  72                 }
  73         }
  74
  75         if (old_mem) {
  76                 switch (old_mem->mem_type) {
  77                 case TTM_PL_TT:
  78                         atomic64_sub(old_mem->size, &adev->gtt_usage);
  79                         break;
  80                 case TTM_PL_VRAM:
  81                         atomic64_sub(old_mem->size, &adev->vram_usage);
  82                         vis_size = amdgpu_get_vis_part_size(adev, old_mem);
  83                         atomic64_sub(vis_size, &adev->vram_vis_usage);
  84                         break;
  85                 }
  86         }
  87 }
  88
  89 static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  90 {
  91         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
  92         struct amdgpu_bo *bo;
  93
  94         bo = container_of(tbo, struct amdgpu_bo, tbo);
  95
  96         amdgpu_bo_kunmap(bo);
  97         amdgpu_update_memory_usage(adev, &bo->tbo.mem, NULL);
  98
  99         drm_gem_object_release(&bo->gem_base);
 100         amdgpu_bo_unref(&bo->parent);
 101         if (!list_empty(&bo->shadow_list)) {
 102                 mutex_lock(&adev->shadow_list_lock);
 103                 list_del_init(&bo->shadow_list);
 104                 mutex_unlock(&adev->shadow_list_lock);
 105         }
 106         kfree(bo->metadata);
 107         kfree(bo);
 108 }
 109
 110 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
 111 {
 112         if (bo->destroy == &amdgpu_ttm_bo_destroy)
 113                 return true;
 114         return false;
 115 }
 116
 117 static void amdgpu_ttm_placement_init(struct amdgpu_device *adev,
 118                                       struct ttm_placement *placement,
 119                                       struct ttm_place *places,
 120                                       u32 domain, u64 flags)
 121 {
 122         u32 c = 0;
 123
 124         if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
 125                 unsigned visible_pfn = adev->mc.visible_vram_size >> PAGE_SHIFT;
 126
 127                 places[c].fpfn = 0;
 128                 places[c].lpfn = 0;
 129                 places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
 130                         TTM_PL_FLAG_VRAM;
 131
 132                 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
 133                         places[c].lpfn = visible_pfn;
 134                 else
 135                         places[c].flags |= TTM_PL_FLAG_TOPDOWN;
 136
 137                 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
 138                         places[c].flags |= TTM_PL_FLAG_CONTIGUOUS;
 139                 c++;
 140         }
 141
 142         if (domain & AMDGPU_GEM_DOMAIN_GTT) {
 143                 places[c].fpfn = 0;
 144                 places[c].lpfn = 0;
 145                 places[c].flags = TTM_PL_FLAG_TT;
 146                 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 147                         places[c].flags |= TTM_PL_FLAG_WC |
 148                                 TTM_PL_FLAG_UNCACHED;
 149                 else
 150                         places[c].flags |= TTM_PL_FLAG_CACHED;
 151                 c++;
 152         }
 153
 154         if (domain & AMDGPU_GEM_DOMAIN_CPU) {
 155                 places[c].fpfn = 0;
 156                 places[c].lpfn = 0;
 157                 places[c].flags = TTM_PL_FLAG_SYSTEM;
 158                 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 159                         places[c].flags |= TTM_PL_FLAG_WC |
 160                                 TTM_PL_FLAG_UNCACHED;
 161                 else
 162                         places[c].flags |= TTM_PL_FLAG_CACHED;
 163                 c++;
 164         }
 165
 166         if (domain & AMDGPU_GEM_DOMAIN_GDS) {
 167                 places[c].fpfn = 0;
 168                 places[c].lpfn = 0;
 169                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GDS;
 170                 c++;
 171         }
 172
 173         if (domain & AMDGPU_GEM_DOMAIN_GWS) {
 174                 places[c].fpfn = 0;
 175                 places[c].lpfn = 0;
 176                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GWS;
 177                 c++;
 178         }
 179
 180         if (domain & AMDGPU_GEM_DOMAIN_OA) {
 181                 places[c].fpfn = 0;
 182                 places[c].lpfn = 0;
 183                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_OA;
 184                 c++;
 185         }
 186
 187         if (!c) {
 188                 places[c].fpfn = 0;
 189                 places[c].lpfn = 0;
 190                 places[c].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
 191                 c++;
 192         }
 193
 194         placement->num_placement = c;
 195         placement->placement = places;
 196
 197         placement->num_busy_placement = c;
 198         placement->busy_placement = places;
 199 }
 200
 201 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
 202 {
 203         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
 204
 205         amdgpu_ttm_placement_init(adev, &abo->placement, abo->placements,
 206                                   domain, abo->flags);
 207 }
 208
 209 static void amdgpu_fill_placement_to_bo(struct amdgpu_bo *bo,
 210                                         struct ttm_placement *placement)
 211 {
 212         BUG_ON(placement->num_placement > (AMDGPU_GEM_DOMAIN_MAX + 1));
 213
 214         memcpy(bo->placements, placement->placement,
 215                placement->num_placement * sizeof(struct ttm_place));
 216         bo->placement.num_placement = placement->num_placement;
 217         bo->placement.num_busy_placement = placement->num_busy_placement;
 218         bo->placement.placement = bo->placements;
 219         bo->placement.busy_placement = bo->placements;
 220 }
 221
 222 /**
 223  * amdgpu_bo_create_kernel - create BO for kernel use
 224  *
 225  * @adev: amdgpu device object
 226  * @size: size for the new BO
 227  * @align: alignment for the new BO
 228  * @domain: where to place it
 229  * @bo_ptr: resulting BO
 230  * @gpu_addr: GPU addr of the pinned BO
 231  * @cpu_addr: optional CPU address mapping
 232  *
 233  * Allocates and pins a BO for kernel internal use.
 234  *
 235  * Returns 0 on success, negative error code otherwise.
 236  */
 237 int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
 238                             unsigned long size, int align,
 239                             u32 domain, struct amdgpu_bo **bo_ptr,
 240                             u64 *gpu_addr, void **cpu_addr)
 241 {
 242         bool free = false;
 243         int r;
 244
 245         if (!*bo_ptr) {
 246                 r = amdgpu_bo_create(adev, size, align, true, domain,
 247                                      AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
 248                                      AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
 249                                      NULL, NULL, bo_ptr);
 250                 if (r) {
 251                         dev_err(adev->dev, "(%d) failed to allocate kernel bo\n",
 252                                 r);
 253                         return r;
 254                 }
 255                 free = true;
 256         }
 257
 258         r = amdgpu_bo_reserve(*bo_ptr, false);
 259         if (r) {
 260                 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r);
 261                 goto error_free;
 262         }
 263
 264         r = amdgpu_bo_pin(*bo_ptr, domain, gpu_addr);
 265         if (r) {
 266                 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r);
 267                 goto error_unreserve;
 268         }
 269
 270         if (cpu_addr) {
 271                 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
 272                 if (r) {
 273                         dev_err(adev->dev, "(%d) kernel bo map failed\n", r);
 274                         goto error_unreserve;
 275                 }
 276         }
 277
 278         amdgpu_bo_unreserve(*bo_ptr);
 279
 280         return 0;
 281
 282 error_unreserve:
 283         amdgpu_bo_unreserve(*bo_ptr);
 284
 285 error_free:
 286         if (free)
 287                 amdgpu_bo_unref(bo_ptr);
 288
 289         return r;
 290 }
 291
 292 /**
 293  * amdgpu_bo_free_kernel - free BO for kernel use
 294  *
 295  * @bo: amdgpu BO to free
 296  *
 297  * unmaps and unpin a BO for kernel internal use.
 298  */
 299 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
 300                            void **cpu_addr)
 301 {
 302         if (*bo == NULL)
 303                 return;
 304
 305         if (likely(amdgpu_bo_reserve(*bo, true) == 0)) {
 306                 if (cpu_addr)
 307                         amdgpu_bo_kunmap(*bo);
 308
 309                 amdgpu_bo_unpin(*bo);
 310                 amdgpu_bo_unreserve(*bo);
 311         }
 312         amdgpu_bo_unref(bo);
 313
 314         if (gpu_addr)
 315                 *gpu_addr = 0;
 316
 317         if (cpu_addr)
 318                 *cpu_addr = NULL;
 319 }
 320
 321 int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
 322                                 unsigned long size, int byte_align,
 323                                 bool kernel, u32 domain, u64 flags,
 324                                 struct sg_table *sg,
 325                                 struct ttm_placement *placement,
 326                                 struct reservation_object *resv,
 327                                 struct amdgpu_bo **bo_ptr)
 328 {
 329         struct amdgpu_bo *bo;
 330         enum ttm_bo_type type;
 331         unsigned long page_align;
 332         u64 initial_bytes_moved, bytes_moved;
 333         size_t acc_size;
 334         int r;
 335
 336         page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
 337         size = ALIGN(size, PAGE_SIZE);
 338
 339         if (kernel) {
 340                 type = ttm_bo_type_kernel;
 341         } else if (sg) {
 342                 type = ttm_bo_type_sg;
 343         } else {
 344                 type = ttm_bo_type_device;
 345         }
 346         *bo_ptr = NULL;
 347
 348         acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
 349                                        sizeof(struct amdgpu_bo));
 350
 351         bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL);
 352         if (bo == NULL)
 353                 return -ENOMEM;
 354         r = drm_gem_object_init(adev->ddev, &bo->gem_base, size);
 355         if (unlikely(r)) {
 356                 kfree(bo);
 357                 return r;
 358         }
 359         INIT_LIST_HEAD(&bo->shadow_list);
 360         INIT_LIST_HEAD(&bo->va);
 361         bo->prefered_domains = domain & (AMDGPU_GEM_DOMAIN_VRAM |
 362                                          AMDGPU_GEM_DOMAIN_GTT |
 363                                          AMDGPU_GEM_DOMAIN_CPU |
 364                                          AMDGPU_GEM_DOMAIN_GDS |
 365                                          AMDGPU_GEM_DOMAIN_GWS |
 366                                          AMDGPU_GEM_DOMAIN_OA);
 367         bo->allowed_domains = bo->prefered_domains;
 368         if (!kernel && bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
 369                 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
 370
 371         bo->flags = flags;
 372
 373 #ifdef CONFIG_X86_32
 374         /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
 375          * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
 376          */
 377         bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 378 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
 379         /* Don't try to enable write-combining when it can't work, or things
 380          * may be slow
 381          * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
 382          */
 383
 384 #ifndef CONFIG_COMPILE_TEST
 385 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
 386          thanks to write-combining
 387 #endif
 388
 389         if (bo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 390                 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
 391                               "better performance thanks to write-combining\n");
 392         bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 393 #else
 394         /* For architectures that don't support WC memory,
 395          * mask out the WC flag from the BO
 396          */
 397         if (!drm_arch_can_wc_memory())
 398                 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 399 #endif
 400
 401         amdgpu_fill_placement_to_bo(bo, placement);
 402         /* Kernel allocation are uninterruptible */
 403
 404         initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
 405         r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, type,
 406                                  &bo->placement, page_align, !kernel, NULL,
 407                                  acc_size, sg, resv, &amdgpu_ttm_bo_destroy);
 408         bytes_moved = atomic64_read(&adev->num_bytes_moved) -
 409                       initial_bytes_moved;
 410         if (adev->mc.visible_vram_size < adev->mc.real_vram_size &&
 411             bo->tbo.mem.mem_type == TTM_PL_VRAM &&
 412             bo->tbo.mem.start < adev->mc.visible_vram_size >> PAGE_SHIFT)
 413                 amdgpu_cs_report_moved_bytes(adev, bytes_moved, bytes_moved);
 414         else
 415                 amdgpu_cs_report_moved_bytes(adev, bytes_moved, 0);
 416
 417         if (unlikely(r != 0))
 418                 return r;
 419
 420         if (kernel)
 421                 bo->tbo.priority = 1;
 422
 423         if (flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
 424             bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) {
 425                 struct dma_fence *fence;
 426
 427                 r = amdgpu_fill_buffer(bo, 0, bo->tbo.resv, &fence);
 428                 if (unlikely(r))
 429                         goto fail_unreserve;
 430
 431                 amdgpu_bo_fence(bo, fence, false);
 432                 dma_fence_put(bo->tbo.moving);
 433                 bo->tbo.moving = dma_fence_get(fence);
 434                 dma_fence_put(fence);
 435         }
 436         if (!resv)
 437                 amdgpu_bo_unreserve(bo);
 438         *bo_ptr = bo;
 439
 440         trace_amdgpu_bo_create(bo);
 441
 442         /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */
 443         if (type == ttm_bo_type_device)
 444                 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 445
 446         return 0;
 447
 448 fail_unreserve:
 449         if (!resv)
 450                 ww_mutex_unlock(&bo->tbo.resv->lock);
 451         amdgpu_bo_unref(&bo);
 452         return r;
 453 }
 454
 455 static int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
 456                                    unsigned long size, int byte_align,
 457                                    struct amdgpu_bo *bo)
 458 {
 459         struct ttm_placement placement = {0};
 460         struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
 461         int r;
 462
 463         if (bo->shadow)
 464                 return 0;
 465
 466         bo->flags |= AMDGPU_GEM_CREATE_SHADOW;
 467         memset(&placements, 0,
 468                (AMDGPU_GEM_DOMAIN_MAX + 1) * sizeof(struct ttm_place));
 469
 470         amdgpu_ttm_placement_init(adev, &placement,
 471                                   placements, AMDGPU_GEM_DOMAIN_GTT,
 472                                   AMDGPU_GEM_CREATE_CPU_GTT_USWC);
 473
 474         r = amdgpu_bo_create_restricted(adev, size, byte_align, true,
 475                                         AMDGPU_GEM_DOMAIN_GTT,
 476                                         AMDGPU_GEM_CREATE_CPU_GTT_USWC,
 477                                         NULL, &placement,
 478                                         bo->tbo.resv,
 479                                         &bo->shadow);
 480         if (!r) {
 481                 bo->shadow->parent = amdgpu_bo_ref(bo);
 482                 mutex_lock(&adev->shadow_list_lock);
 483                 list_add_tail(&bo->shadow_list, &adev->shadow_list);
 484                 mutex_unlock(&adev->shadow_list_lock);
 485         }
 486
 487         return r;
 488 }
 489
 490 int amdgpu_bo_create(struct amdgpu_device *adev,
 491                      unsigned long size, int byte_align,
 492                      bool kernel, u32 domain, u64 flags,
 493                      struct sg_table *sg,
 494                      struct reservation_object *resv,
 495                      struct amdgpu_bo **bo_ptr)
 496 {
 497         struct ttm_placement placement = {0};
 498         struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
 499         int r;
 500
 501         memset(&placements, 0,
 502                (AMDGPU_GEM_DOMAIN_MAX + 1) * sizeof(struct ttm_place));
 503
 504         amdgpu_ttm_placement_init(adev, &placement,
 505                                   placements, domain, flags);
 506
 507         r = amdgpu_bo_create_restricted(adev, size, byte_align, kernel,
 508                                         domain, flags, sg, &placement,
 509                                         resv, bo_ptr);
 510         if (r)
 511                 return r;
 512
 513         if (amdgpu_need_backup(adev) && (flags & AMDGPU_GEM_CREATE_SHADOW)) {
 514                 if (!resv) {
 515                         r = ww_mutex_lock(&(*bo_ptr)->tbo.resv->lock, NULL);
 516                         WARN_ON(r != 0);
 517                 }
 518
 519                 r = amdgpu_bo_create_shadow(adev, size, byte_align, (*bo_ptr));
 520
 521                 if (!resv)
 522                         ww_mutex_unlock(&(*bo_ptr)->tbo.resv->lock);
 523
 524                 if (r)
 525                         amdgpu_bo_unref(bo_ptr);
 526         }
 527
 528         return r;
 529 }
 530
 531 int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev,
 532                                struct amdgpu_ring *ring,
 533                                struct amdgpu_bo *bo,
 534                                struct reservation_object *resv,
 535                                struct dma_fence **fence,
 536                                bool direct)
 537
 538 {
 539         struct amdgpu_bo *shadow = bo->shadow;
 540         uint64_t bo_addr, shadow_addr;
 541         int r;
 542
 543         if (!shadow)
 544                 return -EINVAL;
 545
 546         bo_addr = amdgpu_bo_gpu_offset(bo);
 547         shadow_addr = amdgpu_bo_gpu_offset(bo->shadow);
 548
 549         r = reservation_object_reserve_shared(bo->tbo.resv);
 550         if (r)
 551                 goto err;
 552
 553         r = amdgpu_copy_buffer(ring, bo_addr, shadow_addr,
 554                                amdgpu_bo_size(bo), resv, fence,
 555                                direct, false);
 556         if (!r)
 557                 amdgpu_bo_fence(bo, *fence, true);
 558
 559 err:
 560         return r;
 561 }
 562
 563 int amdgpu_bo_validate(struct amdgpu_bo *bo)
 564 {
 565         uint32_t domain;
 566         int r;
 567
 568         if (bo->pin_count)
 569                 return 0;
 570
 571         domain = bo->prefered_domains;
 572
 573 retry:
 574         amdgpu_ttm_placement_from_domain(bo, domain);
 575         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 576         if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
 577                 domain = bo->allowed_domains;
 578                 goto retry;
 579         }
 580
 581         return r;
 582 }
 583
 584 int amdgpu_bo_restore_from_shadow(struct amdgpu_device *adev,
 585                                   struct amdgpu_ring *ring,
 586                                   struct amdgpu_bo *bo,
 587                                   struct reservation_object *resv,
 588                                   struct dma_fence **fence,
 589                                   bool direct)
 590
 591 {
 592         struct amdgpu_bo *shadow = bo->shadow;
 593         uint64_t bo_addr, shadow_addr;
 594         int r;
 595
 596         if (!shadow)
 597                 return -EINVAL;
 598
 599         bo_addr = amdgpu_bo_gpu_offset(bo);
 600         shadow_addr = amdgpu_bo_gpu_offset(bo->shadow);
 601
 602         r = reservation_object_reserve_shared(bo->tbo.resv);
 603         if (r)
 604                 goto err;
 605
 606         r = amdgpu_copy_buffer(ring, shadow_addr, bo_addr,
 607                                amdgpu_bo_size(bo), resv, fence,
 608                                direct, false);
 609         if (!r)
 610                 amdgpu_bo_fence(bo, *fence, true);
 611
 612 err:
 613         return r;
 614 }
 615
 616 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
 617 {
 618         void *kptr;
 619         long r;
 620
 621         if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 622                 return -EPERM;
 623
 624         kptr = amdgpu_bo_kptr(bo);
 625         if (kptr) {
 626                 if (ptr)
 627                         *ptr = kptr;
 628                 return 0;
 629         }
 630
 631         r = reservation_object_wait_timeout_rcu(bo->tbo.resv, false, false,
 632                                                 MAX_SCHEDULE_TIMEOUT);
 633         if (r < 0)
 634                 return r;
 635
 636         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
 637         if (r)
 638                 return r;
 639
 640         if (ptr)
 641                 *ptr = amdgpu_bo_kptr(bo);
 642
 643         return 0;
 644 }
 645
 646 void *amdgpu_bo_kptr(struct amdgpu_bo *bo)
 647 {
 648         bool is_iomem;
 649
 650         return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
 651 }
 652
 653 void amdgpu_bo_kunmap(struct amdgpu_bo *bo)
 654 {
 655         if (bo->kmap.bo)
 656                 ttm_bo_kunmap(&bo->kmap);
 657 }
 658
 659 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)
 660 {
 661         if (bo == NULL)
 662                 return NULL;
 663
 664         ttm_bo_reference(&bo->tbo);
 665         return bo;
 666 }
 667
 668 void amdgpu_bo_unref(struct amdgpu_bo **bo)
 669 {
 670         struct ttm_buffer_object *tbo;
 671
 672         if ((*bo) == NULL)
 673                 return;
 674
 675         tbo = &((*bo)->tbo);
 676         ttm_bo_unref(&tbo);
 677         if (tbo == NULL)
 678                 *bo = NULL;
 679 }
 680
 681 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
 682                              u64 min_offset, u64 max_offset,
 683                              u64 *gpu_addr)
 684 {
 685         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 686         int r, i;
 687         unsigned fpfn, lpfn;
 688
 689         if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
 690                 return -EPERM;
 691
 692         if (WARN_ON_ONCE(min_offset > max_offset))
 693                 return -EINVAL;
 694
 695         /* A shared bo cannot be migrated to VRAM */
 696         if (bo->prime_shared_count && (domain == AMDGPU_GEM_DOMAIN_VRAM))
 697                 return -EINVAL;
 698
 699         if (bo->pin_count) {
 700                 uint32_t mem_type = bo->tbo.mem.mem_type;
 701
 702                 if (domain != amdgpu_mem_type_to_domain(mem_type))
 703                         return -EINVAL;
 704
 705                 bo->pin_count++;
 706                 if (gpu_addr)
 707                         *gpu_addr = amdgpu_bo_gpu_offset(bo);
 708
 709                 if (max_offset != 0) {
 710                         u64 domain_start = bo->tbo.bdev->man[mem_type].gpu_offset;
 711                         WARN_ON_ONCE(max_offset <
 712                                      (amdgpu_bo_gpu_offset(bo) - domain_start));
 713                 }
 714
 715                 return 0;
 716         }
 717
 718         bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
 719         amdgpu_ttm_placement_from_domain(bo, domain);
 720         for (i = 0; i < bo->placement.num_placement; i++) {
 721                 /* force to pin into visible video ram */
 722                 if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
 723                     !(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) &&
 724                     (!max_offset || max_offset >
 725                      adev->mc.visible_vram_size)) {
 726                         if (WARN_ON_ONCE(min_offset >
 727                                          adev->mc.visible_vram_size))
 728                                 return -EINVAL;
 729                         fpfn = min_offset >> PAGE_SHIFT;
 730                         lpfn = adev->mc.visible_vram_size >> PAGE_SHIFT;
 731                 } else {
 732                         fpfn = min_offset >> PAGE_SHIFT;
 733                         lpfn = max_offset >> PAGE_SHIFT;
 734                 }
 735                 if (fpfn > bo->placements[i].fpfn)
 736                         bo->placements[i].fpfn = fpfn;
 737                 if (!bo->placements[i].lpfn ||
 738                     (lpfn && lpfn < bo->placements[i].lpfn))
 739                         bo->placements[i].lpfn = lpfn;
 740                 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
 741         }
 742
 743         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 744         if (unlikely(r)) {
 745                 dev_err(adev->dev, "%p pin failed\n", bo);
 746                 goto error;
 747         }
 748
 749         bo->pin_count = 1;
 750         if (gpu_addr != NULL) {
 751                 r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem);
 752                 if (unlikely(r)) {
 753                         dev_err(adev->dev, "%p bind failed\n", bo);
 754                         goto error;
 755                 }
 756                 *gpu_addr = amdgpu_bo_gpu_offset(bo);
 757         }
 758         if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
 759                 adev->vram_pin_size += amdgpu_bo_size(bo);
 760                 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 761                         adev->invisible_pin_size += amdgpu_bo_size(bo);
 762         } else if (domain == AMDGPU_GEM_DOMAIN_GTT) {
 763                 adev->gart_pin_size += amdgpu_bo_size(bo);
 764         }
 765
 766 error:
 767         return r;
 768 }
 769
 770 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr)
 771 {
 772         return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr);
 773 }
 774
 775 int amdgpu_bo_unpin(struct amdgpu_bo *bo)
 776 {
 777         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 778         int r, i;
 779
 780         if (!bo->pin_count) {
 781                 dev_warn(adev->dev, "%p unpin not necessary\n", bo);
 782                 return 0;
 783         }
 784         bo->pin_count--;
 785         if (bo->pin_count)
 786                 return 0;
 787         for (i = 0; i < bo->placement.num_placement; i++) {
 788                 bo->placements[i].lpfn = 0;
 789                 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
 790         }
 791         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 792         if (unlikely(r)) {
 793                 dev_err(adev->dev, "%p validate failed for unpin\n", bo);
 794                 goto error;
 795         }
 796
 797         if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
 798                 adev->vram_pin_size -= amdgpu_bo_size(bo);
 799                 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 800                         adev->invisible_pin_size -= amdgpu_bo_size(bo);
 801         } else if (bo->tbo.mem.mem_type == TTM_PL_TT) {
 802                 adev->gart_pin_size -= amdgpu_bo_size(bo);
 803         }
 804
 805 error:
 806         return r;
 807 }
 808
 809 int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
 810 {
 811         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
 812         if (0 && (adev->flags & AMD_IS_APU)) {
 813                 /* Useless to evict on IGP chips */
 814                 return 0;
 815         }
 816         return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM);
 817 }
 818
 819 static const char *amdgpu_vram_names[] = {
 820         "UNKNOWN",
 821         "GDDR1",
 822         "DDR2",
 823         "GDDR3",
 824         "GDDR4",
 825         "GDDR5",
 826         "HBM",
 827         "DDR3"
 828 };
 829
 830 int amdgpu_bo_init(struct amdgpu_device *adev)
 831 {
 832         /* reserve PAT memory space to WC for VRAM */
 833         arch_io_reserve_memtype_wc(adev->mc.aper_base,
 834                                    adev->mc.aper_size);
 835
 836         /* Add an MTRR for the VRAM */
 837         adev->mc.vram_mtrr = arch_phys_wc_add(adev->mc.aper_base,
 838                                               adev->mc.aper_size);
 839         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
 840                 adev->mc.mc_vram_size >> 20,
 841                 (unsigned long long)adev->mc.aper_size >> 20);
 842         DRM_INFO("RAM width %dbits %s\n",
 843                  adev->mc.vram_width, amdgpu_vram_names[adev->mc.vram_type]);
 844         return amdgpu_ttm_init(adev);
 845 }
 846
 847 void amdgpu_bo_fini(struct amdgpu_device *adev)
 848 {
 849         amdgpu_ttm_fini(adev);
 850         arch_phys_wc_del(adev->mc.vram_mtrr);
 851         arch_io_free_memtype_wc(adev->mc.aper_base, adev->mc.aper_size);
 852 }
 853
 854 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
 855                              struct vm_area_struct *vma)
 856 {
 857         return ttm_fbdev_mmap(vma, &bo->tbo);
 858 }
 859
 860 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
 861 {
 862         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 863
 864         if (adev->family <= AMDGPU_FAMILY_CZ &&
 865             AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
 866                 return -EINVAL;
 867
 868         bo->tiling_flags = tiling_flags;
 869         return 0;
 870 }
 871
 872 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
 873 {
 874         lockdep_assert_held(&bo->tbo.resv->lock.base);
 875
 876         if (tiling_flags)
 877                 *tiling_flags = bo->tiling_flags;
 878 }
 879
 880 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
 881                             uint32_t metadata_size, uint64_t flags)
 882 {
 883         void *buffer;
 884
 885         if (!metadata_size) {
 886                 if (bo->metadata_size) {
 887                         kfree(bo->metadata);
 888                         bo->metadata = NULL;
 889                         bo->metadata_size = 0;
 890                 }
 891                 return 0;
 892         }
 893
 894         if (metadata == NULL)
 895                 return -EINVAL;
 896
 897         buffer = kmemdup(metadata, metadata_size, GFP_KERNEL);
 898         if (buffer == NULL)
 899                 return -ENOMEM;
 900
 901         kfree(bo->metadata);
 902         bo->metadata_flags = flags;
 903         bo->metadata = buffer;
 904         bo->metadata_size = metadata_size;
 905
 906         return 0;
 907 }
 908
 909 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
 910                            size_t buffer_size, uint32_t *metadata_size,
 911                            uint64_t *flags)
 912 {
 913         if (!buffer && !metadata_size)
 914                 return -EINVAL;
 915
 916         if (buffer) {
 917                 if (buffer_size < bo->metadata_size)
 918                         return -EINVAL;
 919
 920                 if (bo->metadata_size)
 921                         memcpy(buffer, bo->metadata, bo->metadata_size);
 922         }
 923
 924         if (metadata_size)
 925                 *metadata_size = bo->metadata_size;
 926         if (flags)
 927                 *flags = bo->metadata_flags;
 928
 929         return 0;
 930 }
 931
 932 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
 933                            bool evict,
 934                            struct ttm_mem_reg *new_mem)
 935 {
 936         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 937         struct amdgpu_bo *abo;
 938         struct ttm_mem_reg *old_mem = &bo->mem;
 939
 940         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
 941                 return;
 942
 943         abo = container_of(bo, struct amdgpu_bo, tbo);
 944         amdgpu_vm_bo_invalidate(adev, abo);
 945
 946         amdgpu_bo_kunmap(abo);
 947
 948         /* remember the eviction */
 949         if (evict)
 950                 atomic64_inc(&adev->num_evictions);
 951
 952         /* update statistics */
 953         if (!new_mem)
 954                 return;
 955
 956         /* move_notify is called before move happens */
 957         amdgpu_update_memory_usage(adev, &bo->mem, new_mem);
 958
 959         trace_amdgpu_ttm_bo_move(abo, new_mem->mem_type, old_mem->mem_type);
 960 }
 961
 962 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 963 {
 964         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 965         struct amdgpu_bo *abo;
 966         unsigned long offset, size;
 967         int r;
 968
 969         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
 970                 return 0;
 971
 972         abo = container_of(bo, struct amdgpu_bo, tbo);
 973
 974         /* Remember that this BO was accessed by the CPU */
 975         abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 976
 977         if (bo->mem.mem_type != TTM_PL_VRAM)
 978                 return 0;
 979
 980         size = bo->mem.num_pages << PAGE_SHIFT;
 981         offset = bo->mem.start << PAGE_SHIFT;
 982         if ((offset + size) <= adev->mc.visible_vram_size)
 983                 return 0;
 984
 985         /* Can't move a pinned BO to visible VRAM */
 986         if (abo->pin_count > 0)
 987                 return -EINVAL;
 988
 989         /* hurrah the memory is not visible ! */
 990         atomic64_inc(&adev->num_vram_cpu_page_faults);
 991         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 992                                          AMDGPU_GEM_DOMAIN_GTT);
 993
 994         /* Avoid costly evictions; only set GTT as a busy placement */
 995         abo->placement.num_busy_placement = 1;
 996         abo->placement.busy_placement = &abo->placements[1];
 997
 998         r = ttm_bo_validate(bo, &abo->placement, false, false);
 999         if (unlikely(r != 0))
1000                 return r;
1001
1002         offset = bo->mem.start << PAGE_SHIFT;
1003         /* this should never happen */
1004         if (bo->mem.mem_type == TTM_PL_VRAM &&
1005             (offset + size) > adev->mc.visible_vram_size)
1006                 return -EINVAL;
1007
1008         return 0;
1009 }
1010
1011 /**
1012  * amdgpu_bo_fence - add fence to buffer object
1013  *
1014  * @bo: buffer object in question
1015  * @fence: fence to add
1016  * @shared: true if fence should be added shared
1017  *
1018  */
1019 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
1020                      bool shared)
1021 {
1022         struct reservation_object *resv = bo->tbo.resv;
1023
1024         if (shared)
1025                 reservation_object_add_shared_fence(resv, fence);
1026         else
1027                 reservation_object_add_excl_fence(resv, fence);
1028 }
1029
1030 /**
1031  * amdgpu_bo_gpu_offset - return GPU offset of bo
1032  * @bo: amdgpu object for which we query the offset
1033  *
1034  * Returns current GPU offset of the object.
1035  *
1036  * Note: object should either be pinned or reserved when calling this
1037  * function, it might be useful to add check for this for debugging.
1038  */
1039 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
1040 {
1041         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM);
1042         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_TT &&
1043                      !amdgpu_ttm_is_bound(bo->tbo.ttm));
1044         WARN_ON_ONCE(!ww_mutex_is_locked(&bo->tbo.resv->lock) &&
1045                      !bo->pin_count);
1046         WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET);
1047         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM &&
1048                      !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS));
1049
1050         return bo->tbo.offset;
1051 }