drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/debugfs.h>
  25 #include <linux/list.h>
  26 #include <linux/module.h>
  27 #include <linux/uaccess.h>
  28 #include <linux/reboot.h>
  29 #include <linux/syscalls.h>
  30
  31 #include "amdgpu.h"
  32 #include "amdgpu_ras.h"
  33 #include "amdgpu_atomfirmware.h"
  34 #include "amdgpu_xgmi.h"
  35 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
  36
  37 static const char *RAS_FS_NAME = "ras";
  38
  39 const char *ras_error_string[] = {
  40         "none",
  41         "parity",
  42         "single_correctable",
  43         "multi_uncorrectable",
  44         "poison",
  45 };
  46
  47 const char *ras_block_string[] = {
  48         "umc",
  49         "sdma",
  50         "gfx",
  51         "mmhub",
  52         "athub",
  53         "pcie_bif",
  54         "hdp",
  55         "xgmi_wafl",
  56         "df",
  57         "smn",
  58         "sem",
  59         "mp0",
  60         "mp1",
  61         "fuse",
  62 };
  63
  64 #define ras_err_str(i) (ras_error_string[ffs(i)])
  65 #define ras_block_str(i) (ras_block_string[i])
  66
  67 #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
  68
  69 /* inject address is 52 bits */
  70 #define RAS_UMC_INJECT_ADDR_LIMIT       (0x1ULL << 52)
  71
  72 /* typical ECC bad page rate(1 bad page per 100MB VRAM) */
  73 #define RAS_BAD_PAGE_RATE               (100 * 1024 * 1024ULL)
  74
  75 enum amdgpu_ras_retire_page_reservation {
  76         AMDGPU_RAS_RETIRE_PAGE_RESERVED,
  77         AMDGPU_RAS_RETIRE_PAGE_PENDING,
  78         AMDGPU_RAS_RETIRE_PAGE_FAULT,
  79 };
  80
  81 atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
  82
  83 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
  84                                 uint64_t addr);
  85 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
  86                                 uint64_t addr);
  87
  88 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
  89 {
  90         if (adev && amdgpu_ras_get_context(adev))
  91                 amdgpu_ras_get_context(adev)->error_query_ready = ready;
  92 }
  93
  94 static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
  95 {
  96         if (adev && amdgpu_ras_get_context(adev))
  97                 return amdgpu_ras_get_context(adev)->error_query_ready;
  98
  99         return false;
 100 }
 101
 102 static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
 103                                         size_t size, loff_t *pos)
 104 {
 105         struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
 106         struct ras_query_if info = {
 107                 .head = obj->head,
 108         };
 109         ssize_t s;
 110         char val[128];
 111
 112         if (amdgpu_ras_query_error_status(obj->adev, &info))
 113                 return -EINVAL;
 114
 115         s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
 116                         "ue", info.ue_count,
 117                         "ce", info.ce_count);
 118         if (*pos >= s)
 119                 return 0;
 120
 121         s -= *pos;
 122         s = min_t(u64, s, size);
 123
 124
 125         if (copy_to_user(buf, &val[*pos], s))
 126                 return -EINVAL;
 127
 128         *pos += s;
 129
 130         return s;
 131 }
 132
 133 static const struct file_operations amdgpu_ras_debugfs_ops = {
 134         .owner = THIS_MODULE,
 135         .read = amdgpu_ras_debugfs_read,
 136         .write = NULL,
 137         .llseek = default_llseek
 138 };
 139
 140 static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
 141 {
 142         int i;
 143
 144         for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
 145                 *block_id = i;
 146                 if (strcmp(name, ras_block_str(i)) == 0)
 147                         return 0;
 148         }
 149         return -EINVAL;
 150 }
 151
 152 static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
 153                 const char __user *buf, size_t size,
 154                 loff_t *pos, struct ras_debug_if *data)
 155 {
 156         ssize_t s = min_t(u64, 64, size);
 157         char str[65];
 158         char block_name[33];
 159         char err[9] = "ue";
 160         int op = -1;
 161         int block_id;
 162         uint32_t sub_block;
 163         u64 address, value;
 164
 165         if (*pos)
 166                 return -EINVAL;
 167         *pos = size;
 168
 169         memset(str, 0, sizeof(str));
 170         memset(data, 0, sizeof(*data));
 171
 172         if (copy_from_user(str, buf, s))
 173                 return -EINVAL;
 174
 175         if (sscanf(str, "disable %32s", block_name) == 1)
 176                 op = 0;
 177         else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
 178                 op = 1;
 179         else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
 180                 op = 2;
 181         else if (str[0] && str[1] && str[2] && str[3])
 182                 /* ascii string, but commands are not matched. */
 183                 return -EINVAL;
 184
 185         if (op != -1) {
 186                 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
 187                         return -EINVAL;
 188
 189                 data->head.block = block_id;
 190                 /* only ue and ce errors are supported */
 191                 if (!memcmp("ue", err, 2))
 192                         data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 193                 else if (!memcmp("ce", err, 2))
 194                         data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
 195                 else
 196                         return -EINVAL;
 197
 198                 data->op = op;
 199
 200                 if (op == 2) {
 201                         if (sscanf(str, "%*s %*s %*s %u %llu %llu",
 202                                                 &sub_block, &address, &value) != 3)
 203                                 if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
 204                                                         &sub_block, &address, &value) != 3)
 205                                         return -EINVAL;
 206                         data->head.sub_block_index = sub_block;
 207                         data->inject.address = address;
 208                         data->inject.value = value;
 209                 }
 210         } else {
 211                 if (size < sizeof(*data))
 212                         return -EINVAL;
 213
 214                 if (copy_from_user(data, buf, sizeof(*data)))
 215                         return -EINVAL;
 216         }
 217
 218         return 0;
 219 }
 220
 221 /**
 222  * DOC: AMDGPU RAS debugfs control interface
 223  *
 224  * It accepts struct ras_debug_if who has two members.
 225  *
 226  * First member: ras_debug_if::head or ras_debug_if::inject.
 227  *
 228  * head is used to indicate which IP block will be under control.
 229  *
 230  * head has four members, they are block, type, sub_block_index, name.
 231  * block: which IP will be under control.
 232  * type: what kind of error will be enabled/disabled/injected.
 233  * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
 234  * name: the name of IP.
 235  *
 236  * inject has two more members than head, they are address, value.
 237  * As their names indicate, inject operation will write the
 238  * value to the address.
 239  *
 240  * The second member: struct ras_debug_if::op.
 241  * It has three kinds of operations.
 242  *
 243  * - 0: disable RAS on the block. Take ::head as its data.
 244  * - 1: enable RAS on the block. Take ::head as its data.
 245  * - 2: inject errors on the block. Take ::inject as its data.
 246  *
 247  * How to use the interface?
 248  *
 249  * Programs
 250  *
 251  * Copy the struct ras_debug_if in your codes and initialize it.
 252  * Write the struct to the control node.
 253  *
 254  * Shells
 255  *
 256  * .. code-block:: bash
 257  *
 258  *      echo op block [error [sub_block address value]] > .../ras/ras_ctrl
 259  *
 260  * Parameters:
 261  *
 262  * op: disable, enable, inject
 263  *      disable: only block is needed
 264  *      enable: block and error are needed
 265  *      inject: error, address, value are needed
 266  * block: umc, sdma, gfx, .........
 267  *      see ras_block_string[] for details
 268  * error: ue, ce
 269  *      ue: multi_uncorrectable
 270  *      ce: single_correctable
 271  * sub_block:
 272  *      sub block index, pass 0 if there is no sub block
 273  *
 274  * here are some examples for bash commands:
 275  *
 276  * .. code-block:: bash
 277  *
 278  *      echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 279  *      echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 280  *      echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
 281  *
 282  * How to check the result?
 283  *
 284  * For disable/enable, please check ras features at
 285  * /sys/class/drm/card[0/1/2...]/device/ras/features
 286  *
 287  * For inject, please check corresponding err count at
 288  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
 289  *
 290  * .. note::
 291  *      Operations are only allowed on blocks which are supported.
 292  *      Please check ras mask at /sys/module/amdgpu/parameters/ras_mask
 293  *      to see which blocks support RAS on a particular asic.
 294  *
 295  */
 296 static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *buf,
 297                 size_t size, loff_t *pos)
 298 {
 299         struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
 300         struct ras_debug_if data;
 301         int ret = 0;
 302
 303         if (!amdgpu_ras_get_error_query_ready(adev)) {
 304                 dev_warn(adev->dev, "RAS WARN: error injection "
 305                                 "currently inaccessible\n");
 306                 return size;
 307         }
 308
 309         ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
 310         if (ret)
 311                 return -EINVAL;
 312
 313         if (!amdgpu_ras_is_supported(adev, data.head.block))
 314                 return -EINVAL;
 315
 316         switch (data.op) {
 317         case 0:
 318                 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
 319                 break;
 320         case 1:
 321                 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
 322                 break;
 323         case 2:
 324                 if ((data.inject.address >= adev->gmc.mc_vram_size) ||
 325                     (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 326                         dev_warn(adev->dev, "RAS WARN: input address "
 327                                         "0x%llx is invalid.",
 328                                         data.inject.address);
 329                         ret = -EINVAL;
 330                         break;
 331                 }
 332
 333                 /* umc ce/ue error injection for a bad page is not allowed */
 334                 if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
 335                     amdgpu_ras_check_bad_page(adev, data.inject.address)) {
 336                         dev_warn(adev->dev, "RAS WARN: 0x%llx has been marked "
 337                                         "as bad before error injection!\n",
 338                                         data.inject.address);
 339                         break;
 340                 }
 341
 342                 /* data.inject.address is offset instead of absolute gpu address */
 343                 ret = amdgpu_ras_error_inject(adev, &data.inject);
 344                 break;
 345         default:
 346                 ret = -EINVAL;
 347                 break;
 348         }
 349
 350         if (ret)
 351                 return -EINVAL;
 352
 353         return size;
 354 }
 355
 356 /**
 357  * DOC: AMDGPU RAS debugfs EEPROM table reset interface
 358  *
 359  * Some boards contain an EEPROM which is used to persistently store a list of
 360  * bad pages which experiences ECC errors in vram.  This interface provides
 361  * a way to reset the EEPROM, e.g., after testing error injection.
 362  *
 363  * Usage:
 364  *
 365  * .. code-block:: bash
 366  *
 367  *      echo 1 > ../ras/ras_eeprom_reset
 368  *
 369  * will reset EEPROM table to 0 entries.
 370  *
 371  */
 372 static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, const char __user *buf,
 373                 size_t size, loff_t *pos)
 374 {
 375         struct amdgpu_device *adev =
 376                 (struct amdgpu_device *)file_inode(f)->i_private;
 377         int ret;
 378
 379         ret = amdgpu_ras_eeprom_reset_table(
 380                         &(amdgpu_ras_get_context(adev)->eeprom_control));
 381
 382         if (ret == 1) {
 383                 amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS;
 384                 return size;
 385         } else {
 386                 return -EIO;
 387         }
 388 }
 389
 390 static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
 391         .owner = THIS_MODULE,
 392         .read = NULL,
 393         .write = amdgpu_ras_debugfs_ctrl_write,
 394         .llseek = default_llseek
 395 };
 396
 397 static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
 398         .owner = THIS_MODULE,
 399         .read = NULL,
 400         .write = amdgpu_ras_debugfs_eeprom_write,
 401         .llseek = default_llseek
 402 };
 403
 404 /**
 405  * DOC: AMDGPU RAS sysfs Error Count Interface
 406  *
 407  * It allows the user to read the error count for each IP block on the gpu through
 408  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
 409  *
 410  * It outputs the multiple lines which report the uncorrected (ue) and corrected
 411  * (ce) error counts.
 412  *
 413  * The format of one line is below,
 414  *
 415  * [ce|ue]: count
 416  *
 417  * Example:
 418  *
 419  * .. code-block:: bash
 420  *
 421  *      ue: 0
 422  *      ce: 1
 423  *
 424  */
 425 static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
 426                 struct device_attribute *attr, char *buf)
 427 {
 428         struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
 429         struct ras_query_if info = {
 430                 .head = obj->head,
 431         };
 432
 433         if (!amdgpu_ras_get_error_query_ready(obj->adev))
 434                 return sysfs_emit(buf, "Query currently inaccessible\n");
 435
 436         if (amdgpu_ras_query_error_status(obj->adev, &info))
 437                 return -EINVAL;
 438
 439         return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count,
 440                           "ce", info.ce_count);
 441 }
 442
 443 /* obj begin */
 444
 445 #define get_obj(obj) do { (obj)->use++; } while (0)
 446 #define alive_obj(obj) ((obj)->use)
 447
 448 static inline void put_obj(struct ras_manager *obj)
 449 {
 450         if (obj && (--obj->use == 0))
 451                 list_del(&obj->node);
 452         if (obj && (obj->use < 0))
 453                 DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name);
 454 }
 455
 456 /* make one obj and return it. */
 457 static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
 458                 struct ras_common_if *head)
 459 {
 460         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 461         struct ras_manager *obj;
 462
 463         if (!adev->ras_features || !con)
 464                 return NULL;
 465
 466         if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 467                 return NULL;
 468
 469         obj = &con->objs[head->block];
 470         /* already exist. return obj? */
 471         if (alive_obj(obj))
 472                 return NULL;
 473
 474         obj->head = *head;
 475         obj->adev = adev;
 476         list_add(&obj->node, &con->head);
 477         get_obj(obj);
 478
 479         return obj;
 480 }
 481
 482 /* return an obj equal to head, or the first when head is NULL */
 483 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 484                 struct ras_common_if *head)
 485 {
 486         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 487         struct ras_manager *obj;
 488         int i;
 489
 490         if (!adev->ras_features || !con)
 491                 return NULL;
 492
 493         if (head) {
 494                 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 495                         return NULL;
 496
 497                 obj = &con->objs[head->block];
 498
 499                 if (alive_obj(obj)) {
 500                         WARN_ON(head->block != obj->head.block);
 501                         return obj;
 502                 }
 503         } else {
 504                 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
 505                         obj = &con->objs[i];
 506                         if (alive_obj(obj)) {
 507                                 WARN_ON(i != obj->head.block);
 508                                 return obj;
 509                         }
 510                 }
 511         }
 512
 513         return NULL;
 514 }
 515 /* obj end */
 516
 517 static void amdgpu_ras_parse_status_code(struct amdgpu_device *adev,
 518                                          const char* invoke_type,
 519                                          const char* block_name,
 520                                          enum ta_ras_status ret)
 521 {
 522         switch (ret) {
 523         case TA_RAS_STATUS__SUCCESS:
 524                 return;
 525         case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE:
 526                 dev_warn(adev->dev,
 527                         "RAS WARN: %s %s currently unavailable\n",
 528                         invoke_type,
 529                         block_name);
 530                 break;
 531         default:
 532                 dev_err(adev->dev,
 533                         "RAS ERROR: %s %s error failed ret 0x%X\n",
 534                         invoke_type,
 535                         block_name,
 536                         ret);
 537         }
 538 }
 539
 540 /* feature ctl begin */
 541 static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
 542                 struct ras_common_if *head)
 543 {
 544         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 545
 546         return con->hw_supported & BIT(head->block);
 547 }
 548
 549 static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
 550                 struct ras_common_if *head)
 551 {
 552         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 553
 554         return con->features & BIT(head->block);
 555 }
 556
 557 /*
 558  * if obj is not created, then create one.
 559  * set feature enable flag.
 560  */
 561 static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 562                 struct ras_common_if *head, int enable)
 563 {
 564         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 565         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
 566
 567         /* If hardware does not support ras, then do not create obj.
 568          * But if hardware support ras, we can create the obj.
 569          * Ras framework checks con->hw_supported to see if it need do
 570          * corresponding initialization.
 571          * IP checks con->support to see if it need disable ras.
 572          */
 573         if (!amdgpu_ras_is_feature_allowed(adev, head))
 574                 return 0;
 575         if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head)))
 576                 return 0;
 577
 578         if (enable) {
 579                 if (!obj) {
 580                         obj = amdgpu_ras_create_obj(adev, head);
 581                         if (!obj)
 582                                 return -EINVAL;
 583                 } else {
 584                         /* In case we create obj somewhere else */
 585                         get_obj(obj);
 586                 }
 587                 con->features |= BIT(head->block);
 588         } else {
 589                 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
 590                         /* skip clean gfx ras context feature for VEGA20 Gaming.
 591                          * will clean later
 592                          */
 593                         if (!(!adev->ras_features && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)))
 594                                 con->features &= ~BIT(head->block);
 595                         put_obj(obj);
 596                 }
 597         }
 598
 599         return 0;
 600 }
 601
 602 /* wrapper of psp_ras_enable_features */
 603 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 604                 struct ras_common_if *head, bool enable)
 605 {
 606         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 607         union ta_ras_cmd_input *info;
 608         int ret;
 609
 610         if (!con)
 611                 return -EINVAL;
 612
 613         info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL);
 614         if (!info)
 615                 return -ENOMEM;
 616
 617         if (!enable) {
 618                 info->disable_features = (struct ta_ras_disable_features_input) {
 619                         .block_id =  amdgpu_ras_block_to_ta(head->block),
 620                         .error_type = amdgpu_ras_error_to_ta(head->type),
 621                 };
 622         } else {
 623                 info->enable_features = (struct ta_ras_enable_features_input) {
 624                         .block_id =  amdgpu_ras_block_to_ta(head->block),
 625                         .error_type = amdgpu_ras_error_to_ta(head->type),
 626                 };
 627         }
 628
 629         /* Do not enable if it is not allowed. */
 630         WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head));
 631         /* Are we alerady in that state we are going to set? */
 632         if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) {
 633                 ret = 0;
 634                 goto out;
 635         }
 636
 637         if (!amdgpu_ras_intr_triggered()) {
 638                 ret = psp_ras_enable_features(&adev->psp, info, enable);
 639                 if (ret) {
 640                         amdgpu_ras_parse_status_code(adev,
 641                                                      enable ? "enable":"disable",
 642                                                      ras_block_str(head->block),
 643                                                     (enum ta_ras_status)ret);
 644                         if (ret == TA_RAS_STATUS__RESET_NEEDED)
 645                                 ret = -EAGAIN;
 646                         else
 647                                 ret = -EINVAL;
 648
 649                         goto out;
 650                 }
 651         }
 652
 653         /* setup the obj */
 654         __amdgpu_ras_feature_enable(adev, head, enable);
 655         ret = 0;
 656 out:
 657         kfree(info);
 658         return ret;
 659 }
 660
 661 /* Only used in device probe stage and called only once. */
 662 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
 663                 struct ras_common_if *head, bool enable)
 664 {
 665         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 666         int ret;
 667
 668         if (!con)
 669                 return -EINVAL;
 670
 671         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
 672                 if (enable) {
 673                         /* There is no harm to issue a ras TA cmd regardless of
 674                          * the currecnt ras state.
 675                          * If current state == target state, it will do nothing
 676                          * But sometimes it requests driver to reset and repost
 677                          * with error code -EAGAIN.
 678                          */
 679                         ret = amdgpu_ras_feature_enable(adev, head, 1);
 680                         /* With old ras TA, we might fail to enable ras.
 681                          * Log it and just setup the object.
 682                          * TODO need remove this WA in the future.
 683                          */
 684                         if (ret == -EINVAL) {
 685                                 ret = __amdgpu_ras_feature_enable(adev, head, 1);
 686                                 if (!ret)
 687                                         dev_info(adev->dev,
 688                                                 "RAS INFO: %s setup object\n",
 689                                                 ras_block_str(head->block));
 690                         }
 691                 } else {
 692                         /* setup the object then issue a ras TA disable cmd.*/
 693                         ret = __amdgpu_ras_feature_enable(adev, head, 1);
 694                         if (ret)
 695                                 return ret;
 696
 697                         /* gfx block ras dsiable cmd must send to ras-ta */
 698                         if (head->block == AMDGPU_RAS_BLOCK__GFX)
 699                                 con->features |= BIT(head->block);
 700
 701                         ret = amdgpu_ras_feature_enable(adev, head, 0);
 702                 }
 703         } else
 704                 ret = amdgpu_ras_feature_enable(adev, head, enable);
 705
 706         return ret;
 707 }
 708
 709 static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
 710                 bool bypass)
 711 {
 712         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 713         struct ras_manager *obj, *tmp;
 714
 715         list_for_each_entry_safe(obj, tmp, &con->head, node) {
 716                 /* bypass psp.
 717                  * aka just release the obj and corresponding flags
 718                  */
 719                 if (bypass) {
 720                         if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
 721                                 break;
 722                 } else {
 723                         if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
 724                                 break;
 725                 }
 726         }
 727
 728         return con->features;
 729 }
 730
 731 static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
 732                 bool bypass)
 733 {
 734         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 735         int ras_block_count = AMDGPU_RAS_BLOCK_COUNT;
 736         int i;
 737         const enum amdgpu_ras_error_type default_ras_type =
 738                 AMDGPU_RAS_ERROR__NONE;
 739
 740         for (i = 0; i < ras_block_count; i++) {
 741                 struct ras_common_if head = {
 742                         .block = i,
 743                         .type = default_ras_type,
 744                         .sub_block_index = 0,
 745                 };
 746                 strcpy(head.name, ras_block_str(i));
 747                 if (bypass) {
 748                         /*
 749                          * bypass psp. vbios enable ras for us.
 750                          * so just create the obj
 751                          */
 752                         if (__amdgpu_ras_feature_enable(adev, &head, 1))
 753                                 break;
 754                 } else {
 755                         if (amdgpu_ras_feature_enable(adev, &head, 1))
 756                                 break;
 757                 }
 758         }
 759
 760         return con->features;
 761 }
 762 /* feature ctl end */
 763
 764 /* query/inject/cure begin */
 765 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
 766         struct ras_query_if *info)
 767 {
 768         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
 769         struct ras_err_data err_data = {0, 0, 0, NULL};
 770         int i;
 771
 772         if (!obj)
 773                 return -EINVAL;
 774
 775         switch (info->head.block) {
 776         case AMDGPU_RAS_BLOCK__UMC:
 777                 if (adev->umc.funcs->query_ras_error_count)
 778                         adev->umc.funcs->query_ras_error_count(adev, &err_data);
 779                 /* umc query_ras_error_address is also responsible for clearing
 780                  * error status
 781                  */
 782                 if (adev->umc.funcs->query_ras_error_address)
 783                         adev->umc.funcs->query_ras_error_address(adev, &err_data);
 784                 break;
 785         case AMDGPU_RAS_BLOCK__SDMA:
 786                 if (adev->sdma.funcs->query_ras_error_count) {
 787                         for (i = 0; i < adev->sdma.num_instances; i++)
 788                                 adev->sdma.funcs->query_ras_error_count(adev, i,
 789                                                                         &err_data);
 790                 }
 791                 break;
 792         case AMDGPU_RAS_BLOCK__GFX:
 793                 if (adev->gfx.funcs->query_ras_error_count)
 794                         adev->gfx.funcs->query_ras_error_count(adev, &err_data);
 795
 796                 if (adev->gfx.funcs->query_ras_error_status)
 797                         adev->gfx.funcs->query_ras_error_status(adev);
 798                 break;
 799         case AMDGPU_RAS_BLOCK__MMHUB:
 800                 if (adev->mmhub.funcs->query_ras_error_count)
 801                         adev->mmhub.funcs->query_ras_error_count(adev, &err_data);
 802
 803                 if (adev->mmhub.funcs->query_ras_error_status)
 804                         adev->mmhub.funcs->query_ras_error_status(adev);
 805                 break;
 806         case AMDGPU_RAS_BLOCK__PCIE_BIF:
 807                 if (adev->nbio.ras_funcs &&
 808                     adev->nbio.ras_funcs->query_ras_error_count)
 809                         adev->nbio.ras_funcs->query_ras_error_count(adev, &err_data);
 810                 break;
 811         case AMDGPU_RAS_BLOCK__XGMI_WAFL:
 812                 if (adev->gmc.xgmi.ras_funcs &&
 813                     adev->gmc.xgmi.ras_funcs->query_ras_error_count)
 814                         adev->gmc.xgmi.ras_funcs->query_ras_error_count(adev, &err_data);
 815                 break;
 816         default:
 817                 break;
 818         }
 819
 820         obj->err_data.ue_count += err_data.ue_count;
 821         obj->err_data.ce_count += err_data.ce_count;
 822
 823         info->ue_count = obj->err_data.ue_count;
 824         info->ce_count = obj->err_data.ce_count;
 825
 826         if (err_data.ce_count) {
 827                 dev_info(adev->dev, "%ld correctable hardware errors "
 828                                         "detected in %s block, no user "
 829                                         "action is needed.\n",
 830                                         obj->err_data.ce_count,
 831                                         ras_block_str(info->head.block));
 832         }
 833         if (err_data.ue_count) {
 834                 dev_info(adev->dev, "%ld uncorrectable hardware errors "
 835                                         "detected in %s block\n",
 836                                         obj->err_data.ue_count,
 837                                         ras_block_str(info->head.block));
 838         }
 839
 840         return 0;
 841 }
 842
 843 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
 844                 enum amdgpu_ras_block block)
 845 {
 846         if (!amdgpu_ras_is_supported(adev, block))
 847                 return -EINVAL;
 848
 849         switch (block) {
 850         case AMDGPU_RAS_BLOCK__GFX:
 851                 if (adev->gfx.funcs->reset_ras_error_count)
 852                         adev->gfx.funcs->reset_ras_error_count(adev);
 853
 854                 if (adev->gfx.funcs->reset_ras_error_status)
 855                         adev->gfx.funcs->reset_ras_error_status(adev);
 856                 break;
 857         case AMDGPU_RAS_BLOCK__MMHUB:
 858                 if (adev->mmhub.funcs->reset_ras_error_count)
 859                         adev->mmhub.funcs->reset_ras_error_count(adev);
 860                 break;
 861         case AMDGPU_RAS_BLOCK__SDMA:
 862                 if (adev->sdma.funcs->reset_ras_error_count)
 863                         adev->sdma.funcs->reset_ras_error_count(adev);
 864                 break;
 865         default:
 866                 break;
 867         }
 868
 869         return 0;
 870 }
 871
 872 /* Trigger XGMI/WAFL error */
 873 static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev,
 874                                  struct ta_ras_trigger_error_input *block_info)
 875 {
 876         int ret;
 877
 878         if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
 879                 dev_warn(adev->dev, "Failed to disallow df cstate");
 880
 881         if (amdgpu_dpm_allow_xgmi_power_down(adev, false))
 882                 dev_warn(adev->dev, "Failed to disallow XGMI power down");
 883
 884         ret = psp_ras_trigger_error(&adev->psp, block_info);
 885
 886         if (amdgpu_ras_intr_triggered())
 887                 return ret;
 888
 889         if (amdgpu_dpm_allow_xgmi_power_down(adev, true))
 890                 dev_warn(adev->dev, "Failed to allow XGMI power down");
 891
 892         if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW))
 893                 dev_warn(adev->dev, "Failed to allow df cstate");
 894
 895         return ret;
 896 }
 897
 898 /* wrapper of psp_ras_trigger_error */
 899 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
 900                 struct ras_inject_if *info)
 901 {
 902         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
 903         struct ta_ras_trigger_error_input block_info = {
 904                 .block_id =  amdgpu_ras_block_to_ta(info->head.block),
 905                 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
 906                 .sub_block_index = info->head.sub_block_index,
 907                 .address = info->address,
 908                 .value = info->value,
 909         };
 910         int ret = 0;
 911
 912         if (!obj)
 913                 return -EINVAL;
 914
 915         /* Calculate XGMI relative offset */
 916         if (adev->gmc.xgmi.num_physical_nodes > 1) {
 917                 block_info.address =
 918                         amdgpu_xgmi_get_relative_phy_addr(adev,
 919                                                           block_info.address);
 920         }
 921
 922         switch (info->head.block) {
 923         case AMDGPU_RAS_BLOCK__GFX:
 924                 if (adev->gfx.funcs->ras_error_inject)
 925                         ret = adev->gfx.funcs->ras_error_inject(adev, info);
 926                 else
 927                         ret = -EINVAL;
 928                 break;
 929         case AMDGPU_RAS_BLOCK__UMC:
 930         case AMDGPU_RAS_BLOCK__SDMA:
 931         case AMDGPU_RAS_BLOCK__MMHUB:
 932         case AMDGPU_RAS_BLOCK__PCIE_BIF:
 933                 ret = psp_ras_trigger_error(&adev->psp, &block_info);
 934                 break;
 935         case AMDGPU_RAS_BLOCK__XGMI_WAFL:
 936                 ret = amdgpu_ras_error_inject_xgmi(adev, &block_info);
 937                 break;
 938         default:
 939                 dev_info(adev->dev, "%s error injection is not supported yet\n",
 940                          ras_block_str(info->head.block));
 941                 ret = -EINVAL;
 942         }
 943
 944         amdgpu_ras_parse_status_code(adev,
 945                                      "inject",
 946                                      ras_block_str(info->head.block),
 947                                      (enum ta_ras_status)ret);
 948
 949         return ret;
 950 }
 951
 952 /* get the total error counts on all IPs */
 953 unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev,
 954                 bool is_ce)
 955 {
 956         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 957         struct ras_manager *obj;
 958         struct ras_err_data data = {0, 0};
 959
 960         if (!adev->ras_features || !con)
 961                 return 0;
 962
 963         list_for_each_entry(obj, &con->head, node) {
 964                 struct ras_query_if info = {
 965                         .head = obj->head,
 966                 };
 967
 968                 if (amdgpu_ras_query_error_status(adev, &info))
 969                         return 0;
 970
 971                 data.ce_count += info.ce_count;
 972                 data.ue_count += info.ue_count;
 973         }
 974
 975         return is_ce ? data.ce_count : data.ue_count;
 976 }
 977 /* query/inject/cure end */
 978
 979
 980 /* sysfs begin */
 981
 982 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
 983                 struct ras_badpage **bps, unsigned int *count);
 984
 985 static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
 986 {
 987         switch (flags) {
 988         case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
 989                 return "R";
 990         case AMDGPU_RAS_RETIRE_PAGE_PENDING:
 991                 return "P";
 992         case AMDGPU_RAS_RETIRE_PAGE_FAULT:
 993         default:
 994                 return "F";
 995         }
 996 }
 997
 998 /**
 999  * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
1000  *
1001  * It allows user to read the bad pages of vram on the gpu through
1002  * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
1003  *
1004  * It outputs multiple lines, and each line stands for one gpu page.
1005  *
1006  * The format of one line is below,
1007  * gpu pfn : gpu page size : flags
1008  *
1009  * gpu pfn and gpu page size are printed in hex format.
1010  * flags can be one of below character,
1011  *
1012  * R: reserved, this gpu page is reserved and not able to use.
1013  *
1014  * P: pending for reserve, this gpu page is marked as bad, will be reserved
1015  * in next window of page_reserve.
1016  *
1017  * F: unable to reserve. this gpu page can't be reserved due to some reasons.
1018  *
1019  * Examples:
1020  *
1021  * .. code-block:: bash
1022  *
1023  *      0x00000001 : 0x00001000 : R
1024  *      0x00000002 : 0x00001000 : P
1025  *
1026  */
1027
1028 static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
1029                 struct kobject *kobj, struct bin_attribute *attr,
1030                 char *buf, loff_t ppos, size_t count)
1031 {
1032         struct amdgpu_ras *con =
1033                 container_of(attr, struct amdgpu_ras, badpages_attr);
1034         struct amdgpu_device *adev = con->adev;
1035         const unsigned int element_size =
1036                 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
1037         unsigned int start = div64_ul(ppos + element_size - 1, element_size);
1038         unsigned int end = div64_ul(ppos + count - 1, element_size);
1039         ssize_t s = 0;
1040         struct ras_badpage *bps = NULL;
1041         unsigned int bps_count = 0;
1042
1043         memset(buf, 0, count);
1044
1045         if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
1046                 return 0;
1047
1048         for (; start < end && start < bps_count; start++)
1049                 s += scnprintf(&buf[s], element_size + 1,
1050                                 "0x%08x : 0x%08x : %1s\n",
1051                                 bps[start].bp,
1052                                 bps[start].size,
1053                                 amdgpu_ras_badpage_flags_str(bps[start].flags));
1054
1055         kfree(bps);
1056
1057         return s;
1058 }
1059
1060 static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
1061                 struct device_attribute *attr, char *buf)
1062 {
1063         struct amdgpu_ras *con =
1064                 container_of(attr, struct amdgpu_ras, features_attr);
1065
1066         return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features);
1067 }
1068
1069 static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev)
1070 {
1071         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1072
1073         sysfs_remove_file_from_group(&adev->dev->kobj,
1074                                 &con->badpages_attr.attr,
1075                                 RAS_FS_NAME);
1076 }
1077
1078 static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev)
1079 {
1080         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1081         struct attribute *attrs[] = {
1082                 &con->features_attr.attr,
1083                 NULL
1084         };
1085         struct attribute_group group = {
1086                 .name = RAS_FS_NAME,
1087                 .attrs = attrs,
1088         };
1089
1090         sysfs_remove_group(&adev->dev->kobj, &group);
1091
1092         return 0;
1093 }
1094
1095 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
1096                 struct ras_fs_if *head)
1097 {
1098         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1099
1100         if (!obj || obj->attr_inuse)
1101                 return -EINVAL;
1102
1103         get_obj(obj);
1104
1105         memcpy(obj->fs_data.sysfs_name,
1106                         head->sysfs_name,
1107                         sizeof(obj->fs_data.sysfs_name));
1108
1109         obj->sysfs_attr = (struct device_attribute){
1110                 .attr = {
1111                         .name = obj->fs_data.sysfs_name,
1112                         .mode = S_IRUGO,
1113                 },
1114                         .show = amdgpu_ras_sysfs_read,
1115         };
1116         sysfs_attr_init(&obj->sysfs_attr.attr);
1117
1118         if (sysfs_add_file_to_group(&adev->dev->kobj,
1119                                 &obj->sysfs_attr.attr,
1120                                 RAS_FS_NAME)) {
1121                 put_obj(obj);
1122                 return -EINVAL;
1123         }
1124
1125         obj->attr_inuse = 1;
1126
1127         return 0;
1128 }
1129
1130 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
1131                 struct ras_common_if *head)
1132 {
1133         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1134
1135         if (!obj || !obj->attr_inuse)
1136                 return -EINVAL;
1137
1138         sysfs_remove_file_from_group(&adev->dev->kobj,
1139                                 &obj->sysfs_attr.attr,
1140                                 RAS_FS_NAME);
1141         obj->attr_inuse = 0;
1142         put_obj(obj);
1143
1144         return 0;
1145 }
1146
1147 static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
1148 {
1149         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1150         struct ras_manager *obj, *tmp;
1151
1152         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1153                 amdgpu_ras_sysfs_remove(adev, &obj->head);
1154         }
1155
1156         if (amdgpu_bad_page_threshold != 0)
1157                 amdgpu_ras_sysfs_remove_bad_page_node(adev);
1158
1159         amdgpu_ras_sysfs_remove_feature_node(adev);
1160
1161         return 0;
1162 }
1163 /* sysfs end */
1164
1165 /**
1166  * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
1167  *
1168  * Normally when there is an uncorrectable error, the driver will reset
1169  * the GPU to recover.  However, in the event of an unrecoverable error,
1170  * the driver provides an interface to reboot the system automatically
1171  * in that event.
1172  *
1173  * The following file in debugfs provides that interface:
1174  * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
1175  *
1176  * Usage:
1177  *
1178  * .. code-block:: bash
1179  *
1180  *      echo true > .../ras/auto_reboot
1181  *
1182  */
1183 /* debugfs begin */
1184 static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
1185 {
1186         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1187         struct dentry *dir;
1188         struct drm_minor *minor = adev_to_drm(adev)->primary;
1189
1190         dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root);
1191         debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev,
1192                             &amdgpu_ras_debugfs_ctrl_ops);
1193         debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev,
1194                             &amdgpu_ras_debugfs_eeprom_ops);
1195
1196         /*
1197          * After one uncorrectable error happens, usually GPU recovery will
1198          * be scheduled. But due to the known problem in GPU recovery failing
1199          * to bring GPU back, below interface provides one direct way to
1200          * user to reboot system automatically in such case within
1201          * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
1202          * will never be called.
1203          */
1204         debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot);
1205
1206         /*
1207          * User could set this not to clean up hardware's error count register
1208          * of RAS IPs during ras recovery.
1209          */
1210         debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir,
1211                             &con->disable_ras_err_cnt_harvest);
1212         return dir;
1213 }
1214
1215 static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
1216                                       struct ras_fs_if *head,
1217                                       struct dentry *dir)
1218 {
1219         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1220
1221         if (!obj || !dir)
1222                 return;
1223
1224         get_obj(obj);
1225
1226         memcpy(obj->fs_data.debugfs_name,
1227                         head->debugfs_name,
1228                         sizeof(obj->fs_data.debugfs_name));
1229
1230         debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir,
1231                             obj, &amdgpu_ras_debugfs_ops);
1232 }
1233
1234 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
1235 {
1236         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1237         struct dentry *dir;
1238         struct ras_manager *obj;
1239         struct ras_fs_if fs_info;
1240
1241         /*
1242          * it won't be called in resume path, no need to check
1243          * suspend and gpu reset status
1244          */
1245         if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con)
1246                 return;
1247
1248         dir = amdgpu_ras_debugfs_create_ctrl_node(adev);
1249
1250         list_for_each_entry(obj, &con->head, node) {
1251                 if (amdgpu_ras_is_supported(adev, obj->head.block) &&
1252                         (obj->attr_inuse == 1)) {
1253                         sprintf(fs_info.debugfs_name, "%s_err_inject",
1254                                         ras_block_str(obj->head.block));
1255                         fs_info.head = obj->head;
1256                         amdgpu_ras_debugfs_create(adev, &fs_info, dir);
1257                 }
1258         }
1259 }
1260
1261 /* debugfs end */
1262
1263 /* ras fs */
1264 static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,
1265                 amdgpu_ras_sysfs_badpages_read, NULL, 0);
1266 static DEVICE_ATTR(features, S_IRUGO,
1267                 amdgpu_ras_sysfs_features_read, NULL);
1268 static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
1269 {
1270         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1271         struct attribute_group group = {
1272                 .name = RAS_FS_NAME,
1273         };
1274         struct attribute *attrs[] = {
1275                 &con->features_attr.attr,
1276                 NULL
1277         };
1278         struct bin_attribute *bin_attrs[] = {
1279                 NULL,
1280                 NULL,
1281         };
1282         int r;
1283
1284         /* add features entry */
1285         con->features_attr = dev_attr_features;
1286         group.attrs = attrs;
1287         sysfs_attr_init(attrs[0]);
1288
1289         if (amdgpu_bad_page_threshold != 0) {
1290                 /* add bad_page_features entry */
1291                 bin_attr_gpu_vram_bad_pages.private = NULL;
1292                 con->badpages_attr = bin_attr_gpu_vram_bad_pages;
1293                 bin_attrs[0] = &con->badpages_attr;
1294                 group.bin_attrs = bin_attrs;
1295                 sysfs_bin_attr_init(bin_attrs[0]);
1296         }
1297
1298         r = sysfs_create_group(&adev->dev->kobj, &group);
1299         if (r)
1300                 dev_err(adev->dev, "Failed to create RAS sysfs group!");
1301
1302         return 0;
1303 }
1304
1305 static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
1306 {
1307         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1308         struct ras_manager *con_obj, *ip_obj, *tmp;
1309
1310         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1311                 list_for_each_entry_safe(con_obj, tmp, &con->head, node) {
1312                         ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head);
1313                         if (ip_obj)
1314                                 put_obj(ip_obj);
1315                 }
1316         }
1317
1318         amdgpu_ras_sysfs_remove_all(adev);
1319         return 0;
1320 }
1321 /* ras fs end */
1322
1323 /* ih begin */
1324 static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
1325 {
1326         struct ras_ih_data *data = &obj->ih_data;
1327         struct amdgpu_iv_entry entry;
1328         int ret;
1329         struct ras_err_data err_data = {0, 0, 0, NULL};
1330
1331         while (data->rptr != data->wptr) {
1332                 rmb();
1333                 memcpy(&entry, &data->ring[data->rptr],
1334                                 data->element_size);
1335
1336                 wmb();
1337                 data->rptr = (data->aligned_element_size +
1338                                 data->rptr) % data->ring_size;
1339
1340                 /* Let IP handle its data, maybe we need get the output
1341                  * from the callback to udpate the error type/count, etc
1342                  */
1343                 if (data->cb) {
1344                         ret = data->cb(obj->adev, &err_data, &entry);
1345                         /* ue will trigger an interrupt, and in that case
1346                          * we need do a reset to recovery the whole system.
1347                          * But leave IP do that recovery, here we just dispatch
1348                          * the error.
1349                          */
1350                         if (ret == AMDGPU_RAS_SUCCESS) {
1351                                 /* these counts could be left as 0 if
1352                                  * some blocks do not count error number
1353                                  */
1354                                 obj->err_data.ue_count += err_data.ue_count;
1355                                 obj->err_data.ce_count += err_data.ce_count;
1356                         }
1357                 }
1358         }
1359 }
1360
1361 static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
1362 {
1363         struct ras_ih_data *data =
1364                 container_of(work, struct ras_ih_data, ih_work);
1365         struct ras_manager *obj =
1366                 container_of(data, struct ras_manager, ih_data);
1367
1368         amdgpu_ras_interrupt_handler(obj);
1369 }
1370
1371 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
1372                 struct ras_dispatch_if *info)
1373 {
1374         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1375         struct ras_ih_data *data = &obj->ih_data;
1376
1377         if (!obj)
1378                 return -EINVAL;
1379
1380         if (data->inuse == 0)
1381                 return 0;
1382
1383         /* Might be overflow... */
1384         memcpy(&data->ring[data->wptr], info->entry,
1385                         data->element_size);
1386
1387         wmb();
1388         data->wptr = (data->aligned_element_size +
1389                         data->wptr) % data->ring_size;
1390
1391         schedule_work(&data->ih_work);
1392
1393         return 0;
1394 }
1395
1396 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
1397                 struct ras_ih_if *info)
1398 {
1399         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1400         struct ras_ih_data *data;
1401
1402         if (!obj)
1403                 return -EINVAL;
1404
1405         data = &obj->ih_data;
1406         if (data->inuse == 0)
1407                 return 0;
1408
1409         cancel_work_sync(&data->ih_work);
1410
1411         kfree(data->ring);
1412         memset(data, 0, sizeof(*data));
1413         put_obj(obj);
1414
1415         return 0;
1416 }
1417
1418 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
1419                 struct ras_ih_if *info)
1420 {
1421         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1422         struct ras_ih_data *data;
1423
1424         if (!obj) {
1425                 /* in case we registe the IH before enable ras feature */
1426                 obj = amdgpu_ras_create_obj(adev, &info->head);
1427                 if (!obj)
1428                         return -EINVAL;
1429         } else
1430                 get_obj(obj);
1431
1432         data = &obj->ih_data;
1433         /* add the callback.etc */
1434         *data = (struct ras_ih_data) {
1435                 .inuse = 0,
1436                 .cb = info->cb,
1437                 .element_size = sizeof(struct amdgpu_iv_entry),
1438                 .rptr = 0,
1439                 .wptr = 0,
1440         };
1441
1442         INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
1443
1444         data->aligned_element_size = ALIGN(data->element_size, 8);
1445         /* the ring can store 64 iv entries. */
1446         data->ring_size = 64 * data->aligned_element_size;
1447         data->ring = kmalloc(data->ring_size, GFP_KERNEL);
1448         if (!data->ring) {
1449                 put_obj(obj);
1450                 return -ENOMEM;
1451         }
1452
1453         /* IH is ready */
1454         data->inuse = 1;
1455
1456         return 0;
1457 }
1458
1459 static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
1460 {
1461         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1462         struct ras_manager *obj, *tmp;
1463
1464         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1465                 struct ras_ih_if info = {
1466                         .head = obj->head,
1467                 };
1468                 amdgpu_ras_interrupt_remove_handler(adev, &info);
1469         }
1470
1471         return 0;
1472 }
1473 /* ih end */
1474
1475 /* traversal all IPs except NBIO to query error counter */
1476 static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
1477 {
1478         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1479         struct ras_manager *obj;
1480
1481         if (!adev->ras_features || !con)
1482                 return;
1483
1484         list_for_each_entry(obj, &con->head, node) {
1485                 struct ras_query_if info = {
1486                         .head = obj->head,
1487                 };
1488
1489                 /*
1490                  * PCIE_BIF IP has one different isr by ras controller
1491                  * interrupt, the specific ras counter query will be
1492                  * done in that isr. So skip such block from common
1493                  * sync flood interrupt isr calling.
1494                  */
1495                 if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF)
1496                         continue;
1497
1498                 amdgpu_ras_query_error_status(adev, &info);
1499         }
1500 }
1501
1502 /* Parse RdRspStatus and WrRspStatus */
1503 static void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
1504                                           struct ras_query_if *info)
1505 {
1506         /*
1507          * Only two block need to query read/write
1508          * RspStatus at current state
1509          */
1510         switch (info->head.block) {
1511         case AMDGPU_RAS_BLOCK__GFX:
1512                 if (adev->gfx.funcs->query_ras_error_status)
1513                         adev->gfx.funcs->query_ras_error_status(adev);
1514                 break;
1515         case AMDGPU_RAS_BLOCK__MMHUB:
1516                 if (adev->mmhub.funcs->query_ras_error_status)
1517                         adev->mmhub.funcs->query_ras_error_status(adev);
1518                 break;
1519         default:
1520                 break;
1521         }
1522 }
1523
1524 static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
1525 {
1526         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1527         struct ras_manager *obj;
1528
1529         if (!adev->ras_features || !con)
1530                 return;
1531
1532         list_for_each_entry(obj, &con->head, node) {
1533                 struct ras_query_if info = {
1534                         .head = obj->head,
1535                 };
1536
1537                 amdgpu_ras_error_status_query(adev, &info);
1538         }
1539 }
1540
1541 /* recovery begin */
1542
1543 /* return 0 on success.
1544  * caller need free bps.
1545  */
1546 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1547                 struct ras_badpage **bps, unsigned int *count)
1548 {
1549         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1550         struct ras_err_handler_data *data;
1551         int i = 0;
1552         int ret = 0, status;
1553
1554         if (!con || !con->eh_data || !bps || !count)
1555                 return -EINVAL;
1556
1557         mutex_lock(&con->recovery_lock);
1558         data = con->eh_data;
1559         if (!data || data->count == 0) {
1560                 *bps = NULL;
1561                 ret = -EINVAL;
1562                 goto out;
1563         }
1564
1565         *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);
1566         if (!*bps) {
1567                 ret = -ENOMEM;
1568                 goto out;
1569         }
1570
1571         for (; i < data->count; i++) {
1572                 (*bps)[i] = (struct ras_badpage){
1573                         .bp = data->bps[i].retired_page,
1574                         .size = AMDGPU_GPU_PAGE_SIZE,
1575                         .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
1576                 };
1577                 status = amdgpu_vram_mgr_query_page_status(
1578                                 ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),
1579                                 data->bps[i].retired_page);
1580                 if (status == -EBUSY)
1581                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
1582                 else if (status == -ENOENT)
1583                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
1584         }
1585
1586         *count = data->count;
1587 out:
1588         mutex_unlock(&con->recovery_lock);
1589         return ret;
1590 }
1591
1592 static void amdgpu_ras_do_recovery(struct work_struct *work)
1593 {
1594         struct amdgpu_ras *ras =
1595                 container_of(work, struct amdgpu_ras, recovery_work);
1596         struct amdgpu_device *remote_adev = NULL;
1597         struct amdgpu_device *adev = ras->adev;
1598         struct list_head device_list, *device_list_handle =  NULL;
1599
1600         if (!ras->disable_ras_err_cnt_harvest) {
1601                 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
1602
1603                 /* Build list of devices to query RAS related errors */
1604                 if  (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
1605                         device_list_handle = &hive->device_list;
1606                 } else {
1607                         INIT_LIST_HEAD(&device_list);
1608                         list_add_tail(&adev->gmc.xgmi.head, &device_list);
1609                         device_list_handle = &device_list;
1610                 }
1611
1612                 list_for_each_entry(remote_adev,
1613                                 device_list_handle, gmc.xgmi.head) {
1614                         amdgpu_ras_query_err_status(remote_adev);
1615                         amdgpu_ras_log_on_err_counter(remote_adev);
1616                 }
1617
1618                 amdgpu_put_xgmi_hive(hive);
1619         }
1620
1621         if (amdgpu_device_should_recover_gpu(ras->adev))
1622                 amdgpu_device_gpu_recover(ras->adev, NULL);
1623         atomic_set(&ras->in_recovery, 0);
1624 }
1625
1626 /* alloc/realloc bps array */
1627 static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
1628                 struct ras_err_handler_data *data, int pages)
1629 {
1630         unsigned int old_space = data->count + data->space_left;
1631         unsigned int new_space = old_space + pages;
1632         unsigned int align_space = ALIGN(new_space, 512);
1633         void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
1634
1635         if (!bps) {
1636                 kfree(bps);
1637                 return -ENOMEM;
1638         }
1639
1640         if (data->bps) {
1641                 memcpy(bps, data->bps,
1642                                 data->count * sizeof(*data->bps));
1643                 kfree(data->bps);
1644         }
1645
1646         data->bps = bps;
1647         data->space_left += align_space - old_space;
1648         return 0;
1649 }
1650
1651 /* it deal with vram only. */
1652 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
1653                 struct eeprom_table_record *bps, int pages)
1654 {
1655         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1656         struct ras_err_handler_data *data;
1657         int ret = 0;
1658         uint32_t i;
1659
1660         if (!con || !con->eh_data || !bps || pages <= 0)
1661                 return 0;
1662
1663         mutex_lock(&con->recovery_lock);
1664         data = con->eh_data;
1665         if (!data)
1666                 goto out;
1667
1668         for (i = 0; i < pages; i++) {
1669                 if (amdgpu_ras_check_bad_page_unlock(con,
1670                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
1671                         continue;
1672
1673                 if (!data->space_left &&
1674                         amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
1675                         ret = -ENOMEM;
1676                         goto out;
1677                 }
1678
1679                 amdgpu_vram_mgr_reserve_range(
1680                         ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),
1681                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT,
1682                         AMDGPU_GPU_PAGE_SIZE);
1683
1684                 memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps));
1685                 data->count++;
1686                 data->space_left--;
1687         }
1688 out:
1689         mutex_unlock(&con->recovery_lock);
1690
1691         return ret;
1692 }
1693
1694 /*
1695  * write error record array to eeprom, the function should be
1696  * protected by recovery_lock
1697  */
1698 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
1699 {
1700         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1701         struct ras_err_handler_data *data;
1702         struct amdgpu_ras_eeprom_control *control;
1703         int save_count;
1704
1705         if (!con || !con->eh_data)
1706                 return 0;
1707
1708         control = &con->eeprom_control;
1709         data = con->eh_data;
1710         save_count = data->count - control->num_recs;
1711         /* only new entries are saved */
1712         if (save_count > 0) {
1713                 if (amdgpu_ras_eeprom_process_recods(control,
1714                                                         &data->bps[control->num_recs],
1715                                                         true,
1716                                                         save_count)) {
1717                         dev_err(adev->dev, "Failed to save EEPROM table data!");
1718                         return -EIO;
1719                 }
1720
1721                 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
1722         }
1723
1724         return 0;
1725 }
1726
1727 /*
1728  * read error record array in eeprom and reserve enough space for
1729  * storing new bad pages
1730  */
1731 static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
1732 {
1733         struct amdgpu_ras_eeprom_control *control =
1734                                         &adev->psp.ras.ras->eeprom_control;
1735         struct eeprom_table_record *bps = NULL;
1736         int ret = 0;
1737
1738         /* no bad page record, skip eeprom access */
1739         if (!control->num_recs || (amdgpu_bad_page_threshold == 0))
1740                 return ret;
1741
1742         bps = kcalloc(control->num_recs, sizeof(*bps), GFP_KERNEL);
1743         if (!bps)
1744                 return -ENOMEM;
1745
1746         if (amdgpu_ras_eeprom_process_recods(control, bps, false,
1747                 control->num_recs)) {
1748                 dev_err(adev->dev, "Failed to load EEPROM table records!");
1749                 ret = -EIO;
1750                 goto out;
1751         }
1752
1753         ret = amdgpu_ras_add_bad_pages(adev, bps, control->num_recs);
1754
1755 out:
1756         kfree(bps);
1757         return ret;
1758 }
1759
1760 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
1761                                 uint64_t addr)
1762 {
1763         struct ras_err_handler_data *data = con->eh_data;
1764         int i;
1765
1766         addr >>= AMDGPU_GPU_PAGE_SHIFT;
1767         for (i = 0; i < data->count; i++)
1768                 if (addr == data->bps[i].retired_page)
1769                         return true;
1770
1771         return false;
1772 }
1773
1774 /*
1775  * check if an address belongs to bad page
1776  *
1777  * Note: this check is only for umc block
1778  */
1779 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
1780                                 uint64_t addr)
1781 {
1782         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1783         bool ret = false;
1784
1785         if (!con || !con->eh_data)
1786                 return ret;
1787
1788         mutex_lock(&con->recovery_lock);
1789         ret = amdgpu_ras_check_bad_page_unlock(con, addr);
1790         mutex_unlock(&con->recovery_lock);
1791         return ret;
1792 }
1793
1794 static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev,
1795                                         uint32_t max_length)
1796 {
1797         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1798         int tmp_threshold = amdgpu_bad_page_threshold;
1799         u64 val;
1800
1801         /*
1802          * Justification of value bad_page_cnt_threshold in ras structure
1803          *
1804          * Generally, -1 <= amdgpu_bad_page_threshold <= max record length
1805          * in eeprom, and introduce two scenarios accordingly.
1806          *
1807          * Bad page retirement enablement:
1808          *    - If amdgpu_bad_page_threshold = -1,
1809          *      bad_page_cnt_threshold = typical value by formula.
1810          *
1811          *    - When the value from user is 0 < amdgpu_bad_page_threshold <
1812          *      max record length in eeprom, use it directly.
1813          *
1814          * Bad page retirement disablement:
1815          *    - If amdgpu_bad_page_threshold = 0, bad page retirement
1816          *      functionality is disabled, and bad_page_cnt_threshold will
1817          *      take no effect.
1818          */
1819
1820         if (tmp_threshold < -1)
1821                 tmp_threshold = -1;
1822         else if (tmp_threshold > max_length)
1823                 tmp_threshold = max_length;
1824
1825         if (tmp_threshold == -1) {
1826                 val = adev->gmc.mc_vram_size;
1827                 do_div(val, RAS_BAD_PAGE_RATE);
1828                 con->bad_page_cnt_threshold = min(lower_32_bits(val),
1829                                                 max_length);
1830         } else {
1831                 con->bad_page_cnt_threshold = tmp_threshold;
1832         }
1833 }
1834
1835 int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
1836 {
1837         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1838         struct ras_err_handler_data **data;
1839         uint32_t max_eeprom_records_len = 0;
1840         bool exc_err_limit = false;
1841         int ret;
1842
1843         if (adev->ras_features && con)
1844                 data = &con->eh_data;
1845         else
1846                 return 0;
1847
1848         *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO);
1849         if (!*data) {
1850                 ret = -ENOMEM;
1851                 goto out;
1852         }
1853
1854         mutex_init(&con->recovery_lock);
1855         INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
1856         atomic_set(&con->in_recovery, 0);
1857         con->adev = adev;
1858
1859         max_eeprom_records_len = amdgpu_ras_eeprom_get_record_max_length();
1860         amdgpu_ras_validate_threshold(adev, max_eeprom_records_len);
1861
1862         /* Todo: During test the SMU might fail to read the eeprom through I2C
1863          * when the GPU is pending on XGMI reset during probe time
1864          * (Mostly after second bus reset), skip it now
1865          */
1866         if (adev->gmc.xgmi.pending_reset)
1867                 return 0;
1868         ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);
1869         /*
1870          * This calling fails when exc_err_limit is true or
1871          * ret != 0.
1872          */
1873         if (exc_err_limit || ret)
1874                 goto free;
1875
1876         if (con->eeprom_control.num_recs) {
1877                 ret = amdgpu_ras_load_bad_pages(adev);
1878                 if (ret)
1879                         goto free;
1880         }
1881
1882         return 0;
1883
1884 free:
1885         kfree((*data)->bps);
1886         kfree(*data);
1887         con->eh_data = NULL;
1888 out:
1889         dev_warn(adev->dev, "Failed to initialize ras recovery!\n");
1890
1891         /*
1892          * Except error threshold exceeding case, other failure cases in this
1893          * function would not fail amdgpu driver init.
1894          */
1895         if (!exc_err_limit)
1896                 ret = 0;
1897         else
1898                 ret = -EINVAL;
1899
1900         return ret;
1901 }
1902
1903 static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
1904 {
1905         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1906         struct ras_err_handler_data *data = con->eh_data;
1907
1908         /* recovery_init failed to init it, fini is useless */
1909         if (!data)
1910                 return 0;
1911
1912         cancel_work_sync(&con->recovery_work);
1913
1914         mutex_lock(&con->recovery_lock);
1915         con->eh_data = NULL;
1916         kfree(data->bps);
1917         kfree(data);
1918         mutex_unlock(&con->recovery_lock);
1919
1920         return 0;
1921 }
1922 /* recovery end */
1923
1924 /* return 0 if ras will reset gpu and repost.*/
1925 int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev,
1926                 unsigned int block)
1927 {
1928         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1929
1930         if (!ras)
1931                 return -EINVAL;
1932
1933         ras->flags |= AMDGPU_RAS_FLAG_INIT_NEED_RESET;
1934         return 0;
1935 }
1936
1937 static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
1938 {
1939         return adev->asic_type == CHIP_VEGA10 ||
1940                 adev->asic_type == CHIP_VEGA20 ||
1941                 adev->asic_type == CHIP_ARCTURUS ||
1942                 adev->asic_type == CHIP_ALDEBARAN ||
1943                 adev->asic_type == CHIP_SIENNA_CICHLID;
1944 }
1945
1946 /*
1947  * check hardware's ras ability which will be saved in hw_supported.
1948  * if hardware does not support ras, we can skip some ras initializtion and
1949  * forbid some ras operations from IP.
1950  * if software itself, say boot parameter, limit the ras ability. We still
1951  * need allow IP do some limited operations, like disable. In such case,
1952  * we have to initialize ras as normal. but need check if operation is
1953  * allowed or not in each function.
1954  */
1955 static void amdgpu_ras_check_supported(struct amdgpu_device *adev,
1956                 uint32_t *hw_supported, uint32_t *supported)
1957 {
1958         *hw_supported = 0;
1959         *supported = 0;
1960
1961         if (amdgpu_sriov_vf(adev) || !adev->is_atom_fw ||
1962             !amdgpu_ras_asic_supported(adev))
1963                 return;
1964
1965         if (!adev->gmc.xgmi.connected_to_cpu) {
1966                 if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
1967                         dev_info(adev->dev, "MEM ECC is active.\n");
1968                         *hw_supported |= (1 << AMDGPU_RAS_BLOCK__UMC |
1969                                         1 << AMDGPU_RAS_BLOCK__DF);
1970                 } else {
1971                         dev_info(adev->dev, "MEM ECC is not presented.\n");
1972                 }
1973
1974                 if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
1975                         dev_info(adev->dev, "SRAM ECC is active.\n");
1976                         *hw_supported |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
1977                                         1 << AMDGPU_RAS_BLOCK__DF);
1978                 } else {
1979                         dev_info(adev->dev, "SRAM ECC is not presented.\n");
1980                 }
1981         } else {
1982                 /* driver only manages a few IP blocks RAS feature
1983                  * when GPU is connected cpu through XGMI */
1984                 *hw_supported |= (1 << AMDGPU_RAS_BLOCK__GFX |
1985                                 1 << AMDGPU_RAS_BLOCK__SDMA |
1986                                 1 << AMDGPU_RAS_BLOCK__MMHUB);
1987         }
1988
1989         /* hw_supported needs to be aligned with RAS block mask. */
1990         *hw_supported &= AMDGPU_RAS_BLOCK_MASK;
1991
1992         *supported = amdgpu_ras_enable == 0 ?
1993                         0 : *hw_supported & amdgpu_ras_mask;
1994         adev->ras_features = *supported;
1995 }
1996
1997 int amdgpu_ras_init(struct amdgpu_device *adev)
1998 {
1999         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2000         int r;
2001
2002         if (con)
2003                 return 0;
2004
2005         con = kmalloc(sizeof(struct amdgpu_ras) +
2006                         sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT,
2007                         GFP_KERNEL|__GFP_ZERO);
2008         if (!con)
2009                 return -ENOMEM;
2010
2011         con->objs = (struct ras_manager *)(con + 1);
2012
2013         amdgpu_ras_set_context(adev, con);
2014
2015         amdgpu_ras_check_supported(adev, &con->hw_supported,
2016                         &con->supported);
2017         if (!con->hw_supported || (adev->asic_type == CHIP_VEGA10)) {
2018                 /* set gfx block ras context feature for VEGA20 Gaming
2019                  * send ras disable cmd to ras ta during ras late init.
2020                  */
2021                 if (!adev->ras_features && adev->asic_type == CHIP_VEGA20) {
2022                         con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);
2023
2024                         return 0;
2025                 }
2026
2027                 r = 0;
2028                 goto release_con;
2029         }
2030
2031         con->features = 0;
2032         INIT_LIST_HEAD(&con->head);
2033         /* Might need get this flag from vbios. */
2034         con->flags = RAS_DEFAULT_FLAGS;
2035
2036         /* initialize nbio ras function ahead of any other
2037          * ras functions so hardware fatal error interrupt
2038          * can be enabled as early as possible */
2039         switch (adev->asic_type) {
2040         case CHIP_VEGA20:
2041         case CHIP_ARCTURUS:
2042         case CHIP_ALDEBARAN:
2043                 if (!adev->gmc.xgmi.connected_to_cpu)
2044                         adev->nbio.ras_funcs = &nbio_v7_4_ras_funcs;
2045                 break;
2046         default:
2047                 /* nbio ras is not available */
2048                 break;
2049         }
2050
2051         if (adev->nbio.ras_funcs &&
2052             adev->nbio.ras_funcs->init_ras_controller_interrupt) {
2053                 r = adev->nbio.ras_funcs->init_ras_controller_interrupt(adev);
2054                 if (r)
2055                         goto release_con;
2056         }
2057
2058         if (adev->nbio.ras_funcs &&
2059             adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt) {
2060                 r = adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt(adev);
2061                 if (r)
2062                         goto release_con;
2063         }
2064
2065         if (amdgpu_ras_fs_init(adev)) {
2066                 r = -EINVAL;
2067                 goto release_con;
2068         }
2069
2070         dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
2071                         "hardware ability[%x] ras_mask[%x]\n",
2072                         con->hw_supported, con->supported);
2073         return 0;
2074 release_con:
2075         amdgpu_ras_set_context(adev, NULL);
2076         kfree(con);
2077
2078         return r;
2079 }
2080
2081 /* helper function to handle common stuff in ip late init phase */
2082 int amdgpu_ras_late_init(struct amdgpu_device *adev,
2083                          struct ras_common_if *ras_block,
2084                          struct ras_fs_if *fs_info,
2085                          struct ras_ih_if *ih_info)
2086 {
2087         int r;
2088
2089         /* disable RAS feature per IP block if it is not supported */
2090         if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
2091                 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
2092                 return 0;
2093         }
2094
2095         r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
2096         if (r) {
2097                 if (r == -EAGAIN) {
2098                         /* request gpu reset. will run again */
2099                         amdgpu_ras_request_reset_on_boot(adev,
2100                                         ras_block->block);
2101                         return 0;
2102                 } else if (adev->in_suspend || amdgpu_in_reset(adev)) {
2103                         /* in resume phase, if fail to enable ras,
2104                          * clean up all ras fs nodes, and disable ras */
2105                         goto cleanup;
2106                 } else
2107                         return r;
2108         }
2109
2110         /* in resume phase, no need to create ras fs node */
2111         if (adev->in_suspend || amdgpu_in_reset(adev))
2112                 return 0;
2113
2114         if (ih_info->cb) {
2115                 r = amdgpu_ras_interrupt_add_handler(adev, ih_info);
2116                 if (r)
2117                         goto interrupt;
2118         }
2119
2120         r = amdgpu_ras_sysfs_create(adev, fs_info);
2121         if (r)
2122                 goto sysfs;
2123
2124         return 0;
2125 cleanup:
2126         amdgpu_ras_sysfs_remove(adev, ras_block);
2127 sysfs:
2128         if (ih_info->cb)
2129                 amdgpu_ras_interrupt_remove_handler(adev, ih_info);
2130 interrupt:
2131         amdgpu_ras_feature_enable(adev, ras_block, 0);
2132         return r;
2133 }
2134
2135 /* helper function to remove ras fs node and interrupt handler */
2136 void amdgpu_ras_late_fini(struct amdgpu_device *adev,
2137                           struct ras_common_if *ras_block,
2138                           struct ras_ih_if *ih_info)
2139 {
2140         if (!ras_block || !ih_info)
2141                 return;
2142
2143         amdgpu_ras_sysfs_remove(adev, ras_block);
2144         if (ih_info->cb)
2145                 amdgpu_ras_interrupt_remove_handler(adev, ih_info);
2146         amdgpu_ras_feature_enable(adev, ras_block, 0);
2147 }
2148
2149 /* do some init work after IP late init as dependence.
2150  * and it runs in resume/gpu reset/booting up cases.
2151  */
2152 void amdgpu_ras_resume(struct amdgpu_device *adev)
2153 {
2154         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2155         struct ras_manager *obj, *tmp;
2156
2157         if (!adev->ras_features || !con) {
2158                 /* clean ras context for VEGA20 Gaming after send ras disable cmd */
2159                 amdgpu_release_ras_context(adev);
2160
2161                 return;
2162         }
2163
2164         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
2165                 /* Set up all other IPs which are not implemented. There is a
2166                  * tricky thing that IP's actual ras error type should be
2167                  * MULTI_UNCORRECTABLE, but as driver does not handle it, so
2168                  * ERROR_NONE make sense anyway.
2169                  */
2170                 amdgpu_ras_enable_all_features(adev, 1);
2171
2172                 /* We enable ras on all hw_supported block, but as boot
2173                  * parameter might disable some of them and one or more IP has
2174                  * not implemented yet. So we disable them on behalf.
2175                  */
2176                 list_for_each_entry_safe(obj, tmp, &con->head, node) {
2177                         if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
2178                                 amdgpu_ras_feature_enable(adev, &obj->head, 0);
2179                                 /* there should be no any reference. */
2180                                 WARN_ON(alive_obj(obj));
2181                         }
2182                 }
2183         }
2184
2185         if (con->flags & AMDGPU_RAS_FLAG_INIT_NEED_RESET) {
2186                 con->flags &= ~AMDGPU_RAS_FLAG_INIT_NEED_RESET;
2187                 /* setup ras obj state as disabled.
2188                  * for init_by_vbios case.
2189                  * if we want to enable ras, just enable it in a normal way.
2190                  * If we want do disable it, need setup ras obj as enabled,
2191                  * then issue another TA disable cmd.
2192                  * See feature_enable_on_boot
2193                  */
2194                 amdgpu_ras_disable_all_features(adev, 1);
2195                 amdgpu_ras_reset_gpu(adev);
2196         }
2197 }
2198
2199 void amdgpu_ras_suspend(struct amdgpu_device *adev)
2200 {
2201         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2202
2203         if (!adev->ras_features || !con)
2204                 return;
2205
2206         amdgpu_ras_disable_all_features(adev, 0);
2207         /* Make sure all ras objects are disabled. */
2208         if (con->features)
2209                 amdgpu_ras_disable_all_features(adev, 1);
2210 }
2211
2212 /* do some fini work before IP fini as dependence */
2213 int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
2214 {
2215         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2216
2217         if (!adev->ras_features || !con)
2218                 return 0;
2219
2220         /* Need disable ras on all IPs here before ip [hw/sw]fini */
2221         amdgpu_ras_disable_all_features(adev, 0);
2222         amdgpu_ras_recovery_fini(adev);
2223         return 0;
2224 }
2225
2226 int amdgpu_ras_fini(struct amdgpu_device *adev)
2227 {
2228         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2229
2230         if (!adev->ras_features || !con)
2231                 return 0;
2232
2233         amdgpu_ras_fs_fini(adev);
2234         amdgpu_ras_interrupt_remove_all(adev);
2235
2236         WARN(con->features, "Feature mask is not cleared");
2237
2238         if (con->features)
2239                 amdgpu_ras_disable_all_features(adev, 1);
2240
2241         amdgpu_ras_set_context(adev, NULL);
2242         kfree(con);
2243
2244         return 0;
2245 }
2246
2247 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
2248 {
2249         uint32_t hw_supported, supported;
2250
2251         amdgpu_ras_check_supported(adev, &hw_supported, &supported);
2252         if (!hw_supported)
2253                 return;
2254
2255         if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
2256                 dev_info(adev->dev, "uncorrectable hardware error"
2257                         "(ERREVENT_ATHUB_INTERRUPT) detected!\n");
2258
2259                 amdgpu_ras_reset_gpu(adev);
2260         }
2261 }
2262
2263 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
2264 {
2265         if (adev->asic_type == CHIP_VEGA20 &&
2266             adev->pm.fw_version <= 0x283400) {
2267                 return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) &&
2268                                 amdgpu_ras_intr_triggered();
2269         }
2270
2271         return false;
2272 }
2273
2274 void amdgpu_release_ras_context(struct amdgpu_device *adev)
2275 {
2276         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2277
2278         if (!con)
2279                 return;
2280
2281         if (!adev->ras_features && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {
2282                 con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX);
2283                 amdgpu_ras_set_context(adev, NULL);
2284                 kfree(con);
2285         }
2286 }