drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29
  30 #include "amdgpu.h"
  31 #include "amdgpu_gfx.h"
  32 #include "vi.h"
  33 #include "vi_structs.h"
  34 #include "vid.h"
  35 #include "amdgpu_ucode.h"
  36 #include "amdgpu_atombios.h"
  37 #include "atombios_i2c.h"
  38 #include "clearstate_vi.h"
  39
  40 #include "gmc/gmc_8_2_d.h"
  41 #include "gmc/gmc_8_2_sh_mask.h"
  42
  43 #include "oss/oss_3_0_d.h"
  44 #include "oss/oss_3_0_sh_mask.h"
  45
  46 #include "bif/bif_5_0_d.h"
  47 #include "bif/bif_5_0_sh_mask.h"
  48 #include "gca/gfx_8_0_d.h"
  49 #include "gca/gfx_8_0_enum.h"
  50 #include "gca/gfx_8_0_sh_mask.h"
  51
  52 #include "dce/dce_10_0_d.h"
  53 #include "dce/dce_10_0_sh_mask.h"
  54
  55 #include "smu/smu_7_1_3_d.h"
  56
  57 #include "ivsrcid/ivsrcid_vislands30.h"
  58
  59 #define GFX8_NUM_GFX_RINGS     1
  60 #define GFX8_MEC_HPD_SIZE 4096
  61
  62 #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
  63 #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
  64 #define POLARIS11_GB_ADDR_CONFIG_GOLDEN 0x22011002
  65 #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
  66
  67 #define ARRAY_MODE(x)                                   ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
  68 #define PIPE_CONFIG(x)                                  ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
  69 #define TILE_SPLIT(x)                                   ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
  70 #define MICRO_TILE_MODE_NEW(x)                          ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT)
  71 #define SAMPLE_SPLIT(x)                                 ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
  72 #define BANK_WIDTH(x)                                   ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT)
  73 #define BANK_HEIGHT(x)                                  ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT)
  74 #define MACRO_TILE_ASPECT(x)                            ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT)
  75 #define NUM_BANKS(x)                                    ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT)
  76
  77 #define RLC_CGTT_MGCG_OVERRIDE__CPF_MASK            0x00000001L
  78 #define RLC_CGTT_MGCG_OVERRIDE__RLC_MASK            0x00000002L
  79 #define RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK           0x00000004L
  80 #define RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK           0x00000008L
  81 #define RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK           0x00000010L
  82 #define RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK           0x00000020L
  83
  84 /* BPM SERDES CMD */
  85 #define SET_BPM_SERDES_CMD    1
  86 #define CLE_BPM_SERDES_CMD    0
  87
  88 /* BPM Register Address*/
  89 enum {
  90         BPM_REG_CGLS_EN = 0,        /* Enable/Disable CGLS */
  91         BPM_REG_CGLS_ON,            /* ON/OFF CGLS: shall be controlled by RLC FW */
  92         BPM_REG_CGCG_OVERRIDE,      /* Set/Clear CGCG Override */
  93         BPM_REG_MGCG_OVERRIDE,      /* Set/Clear MGCG Override */
  94         BPM_REG_FGCG_OVERRIDE,      /* Set/Clear FGCG Override */
  95         BPM_REG_FGCG_MAX
  96 };
  97
  98 #define RLC_FormatDirectRegListLength        14
  99
 100 MODULE_FIRMWARE("amdgpu/carrizo_ce.bin");
 101 MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin");
 102 MODULE_FIRMWARE("amdgpu/carrizo_me.bin");
 103 MODULE_FIRMWARE("amdgpu/carrizo_mec.bin");
 104 MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin");
 105 MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin");
 106
 107 MODULE_FIRMWARE("amdgpu/stoney_ce.bin");
 108 MODULE_FIRMWARE("amdgpu/stoney_pfp.bin");
 109 MODULE_FIRMWARE("amdgpu/stoney_me.bin");
 110 MODULE_FIRMWARE("amdgpu/stoney_mec.bin");
 111 MODULE_FIRMWARE("amdgpu/stoney_rlc.bin");
 112
 113 MODULE_FIRMWARE("amdgpu/tonga_ce.bin");
 114 MODULE_FIRMWARE("amdgpu/tonga_pfp.bin");
 115 MODULE_FIRMWARE("amdgpu/tonga_me.bin");
 116 MODULE_FIRMWARE("amdgpu/tonga_mec.bin");
 117 MODULE_FIRMWARE("amdgpu/tonga_mec2.bin");
 118 MODULE_FIRMWARE("amdgpu/tonga_rlc.bin");
 119
 120 MODULE_FIRMWARE("amdgpu/topaz_ce.bin");
 121 MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
 122 MODULE_FIRMWARE("amdgpu/topaz_me.bin");
 123 MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
 124 MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");
 125
 126 MODULE_FIRMWARE("amdgpu/fiji_ce.bin");
 127 MODULE_FIRMWARE("amdgpu/fiji_pfp.bin");
 128 MODULE_FIRMWARE("amdgpu/fiji_me.bin");
 129 MODULE_FIRMWARE("amdgpu/fiji_mec.bin");
 130 MODULE_FIRMWARE("amdgpu/fiji_mec2.bin");
 131 MODULE_FIRMWARE("amdgpu/fiji_rlc.bin");
 132
 133 MODULE_FIRMWARE("amdgpu/polaris10_ce.bin");
 134 MODULE_FIRMWARE("amdgpu/polaris10_ce_2.bin");
 135 MODULE_FIRMWARE("amdgpu/polaris10_pfp.bin");
 136 MODULE_FIRMWARE("amdgpu/polaris10_pfp_2.bin");
 137 MODULE_FIRMWARE("amdgpu/polaris10_me.bin");
 138 MODULE_FIRMWARE("amdgpu/polaris10_me_2.bin");
 139 MODULE_FIRMWARE("amdgpu/polaris10_mec.bin");
 140 MODULE_FIRMWARE("amdgpu/polaris10_mec_2.bin");
 141 MODULE_FIRMWARE("amdgpu/polaris10_mec2.bin");
 142 MODULE_FIRMWARE("amdgpu/polaris10_mec2_2.bin");
 143 MODULE_FIRMWARE("amdgpu/polaris10_rlc.bin");
 144
 145 MODULE_FIRMWARE("amdgpu/polaris11_ce.bin");
 146 MODULE_FIRMWARE("amdgpu/polaris11_ce_2.bin");
 147 MODULE_FIRMWARE("amdgpu/polaris11_pfp.bin");
 148 MODULE_FIRMWARE("amdgpu/polaris11_pfp_2.bin");
 149 MODULE_FIRMWARE("amdgpu/polaris11_me.bin");
 150 MODULE_FIRMWARE("amdgpu/polaris11_me_2.bin");
 151 MODULE_FIRMWARE("amdgpu/polaris11_mec.bin");
 152 MODULE_FIRMWARE("amdgpu/polaris11_mec_2.bin");
 153 MODULE_FIRMWARE("amdgpu/polaris11_mec2.bin");
 154 MODULE_FIRMWARE("amdgpu/polaris11_mec2_2.bin");
 155 MODULE_FIRMWARE("amdgpu/polaris11_rlc.bin");
 156
 157 MODULE_FIRMWARE("amdgpu/polaris12_ce.bin");
 158 MODULE_FIRMWARE("amdgpu/polaris12_ce_2.bin");
 159 MODULE_FIRMWARE("amdgpu/polaris12_pfp.bin");
 160 MODULE_FIRMWARE("amdgpu/polaris12_pfp_2.bin");
 161 MODULE_FIRMWARE("amdgpu/polaris12_me.bin");
 162 MODULE_FIRMWARE("amdgpu/polaris12_me_2.bin");
 163 MODULE_FIRMWARE("amdgpu/polaris12_mec.bin");
 164 MODULE_FIRMWARE("amdgpu/polaris12_mec_2.bin");
 165 MODULE_FIRMWARE("amdgpu/polaris12_mec2.bin");
 166 MODULE_FIRMWARE("amdgpu/polaris12_mec2_2.bin");
 167 MODULE_FIRMWARE("amdgpu/polaris12_rlc.bin");
 168
 169 MODULE_FIRMWARE("amdgpu/vegam_ce.bin");
 170 MODULE_FIRMWARE("amdgpu/vegam_pfp.bin");
 171 MODULE_FIRMWARE("amdgpu/vegam_me.bin");
 172 MODULE_FIRMWARE("amdgpu/vegam_mec.bin");
 173 MODULE_FIRMWARE("amdgpu/vegam_mec2.bin");
 174 MODULE_FIRMWARE("amdgpu/vegam_rlc.bin");
 175
 176 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
 177 {
 178         {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
 179         {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
 180         {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
 181         {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
 182         {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
 183         {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
 184         {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
 185         {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
 186         {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
 187         {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
 188         {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
 189         {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
 190         {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
 191         {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
 192         {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
 193         {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
 194 };
 195
 196 static const u32 golden_settings_tonga_a11[] =
 197 {
 198         mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
 199         mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
 200         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 201         mmGB_GPU_ID, 0x0000000f, 0x00000000,
 202         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
 203         mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
 204         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 205         mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
 206         mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
 207         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 208         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
 209         mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
 210         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
 211         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
 212         mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
 213         mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
 214 };
 215
 216 static const u32 tonga_golden_common_all[] =
 217 {
 218         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 219         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
 220         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
 221         mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
 222         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 223         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 224         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
 225         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
 226 };
 227
 228 static const u32 tonga_mgcg_cgcg_init[] =
 229 {
 230         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
 231         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 232         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 233         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 234         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
 235         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
 236         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
 237         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 238         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 239         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 240         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 241         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 242         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 243         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 244         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 245         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 246         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 247         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 248         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 249         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 250         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 251         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 252         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
 253         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 254         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 255         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 256         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 257         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 258         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 259         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 260         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 261         mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 262         mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 263         mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 264         mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 265         mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 266         mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 267         mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 268         mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
 269         mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 270         mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 271         mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 272         mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 273         mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
 274         mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 275         mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 276         mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 277         mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 278         mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
 279         mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 280         mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 281         mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 282         mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 283         mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 284         mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 285         mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 286         mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 287         mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 288         mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
 289         mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 290         mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 291         mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 292         mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 293         mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
 294         mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 295         mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 296         mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 297         mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 298         mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
 299         mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 300         mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 301         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 302         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 303         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
 304         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
 305 };
 306
 307 static const u32 golden_settings_vegam_a11[] =
 308 {
 309         mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208,
 310         mmCB_HW_CONTROL_2, 0x0f000000, 0x0d000000,
 311         mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
 312         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 313         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
 314         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 315         mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x3a00161a,
 316         mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002e,
 317         mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
 318         mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
 319         mmSQ_CONFIG, 0x07f80000, 0x01180000,
 320         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 321         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
 322         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
 323         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
 324         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x32761054,
 325         mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
 326 };
 327
 328 static const u32 vegam_golden_common_all[] =
 329 {
 330         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 331         mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
 332         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 333         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 334         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
 335         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
 336 };
 337
 338 static const u32 golden_settings_polaris11_a11[] =
 339 {
 340         mmCB_HW_CONTROL, 0x0000f3cf, 0x00007208,
 341         mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
 342         mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
 343         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 344         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
 345         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 346         mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
 347         mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
 348         mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
 349         mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
 350         mmSQ_CONFIG, 0x07f80000, 0x01180000,
 351         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 352         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
 353         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3,
 354         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
 355         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210,
 356         mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
 357 };
 358
 359 static const u32 polaris11_golden_common_all[] =
 360 {
 361         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 362         mmGB_ADDR_CONFIG, 0xffffffff, 0x22011002,
 363         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 364         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 365         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
 366         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
 367 };
 368
 369 static const u32 golden_settings_polaris10_a11[] =
 370 {
 371         mmATC_MISC_CG, 0x000c0fc0, 0x000c0200,
 372         mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208,
 373         mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
 374         mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
 375         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 376         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
 377         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 378         mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
 379         mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002a,
 380         mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
 381         mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
 382         mmSQ_CONFIG, 0x07f80000, 0x07180000,
 383         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 384         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
 385         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
 386         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
 387         mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
 388 };
 389
 390 static const u32 polaris10_golden_common_all[] =
 391 {
 392         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 393         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
 394         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
 395         mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
 396         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 397         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 398         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
 399         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
 400 };
 401
 402 static const u32 fiji_golden_common_all[] =
 403 {
 404         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 405         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a,
 406         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,
 407         mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
 408         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 409         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 410         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
 411         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
 412         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 413         mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009,
 414 };
 415
 416 static const u32 golden_settings_fiji_a10[] =
 417 {
 418         mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
 419         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 420         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
 421         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 422         mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
 423         mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
 424         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 425         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
 426         mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
 427         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff,
 428         mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
 429 };
 430
 431 static const u32 fiji_mgcg_cgcg_init[] =
 432 {
 433         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
 434         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 435         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 436         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 437         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
 438         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
 439         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
 440         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 441         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 442         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 443         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 444         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 445         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 446         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 447         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 448         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 449         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 450         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 451         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 452         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 453         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 454         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 455         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
 456         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 457         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 458         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 459         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 460         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 461         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 462         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 463         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 464         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 465         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 466         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
 467         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
 468 };
 469
 470 static const u32 golden_settings_iceland_a11[] =
 471 {
 472         mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
 473         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 474         mmDB_DEBUG3, 0xc0000000, 0xc0000000,
 475         mmGB_GPU_ID, 0x0000000f, 0x00000000,
 476         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
 477         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 478         mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
 479         mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
 480         mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
 481         mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
 482         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 483         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
 484         mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
 485         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
 486         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
 487         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
 488 };
 489
 490 static const u32 iceland_golden_common_all[] =
 491 {
 492         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 493         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
 494         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
 495         mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
 496         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 497         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 498         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
 499         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
 500 };
 501
 502 static const u32 iceland_mgcg_cgcg_init[] =
 503 {
 504         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
 505         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 506         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 507         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 508         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
 509         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
 510         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
 511         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 512         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 513         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 514         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 515         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 516         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 517         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 518         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 519         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 520         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 521         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 522         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 523         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 524         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 525         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 526         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
 527         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 528         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 529         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 530         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 531         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 532         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 533         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 534         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 535         mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 536         mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 537         mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
 538         mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 539         mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 540         mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 541         mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 542         mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
 543         mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 544         mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 545         mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 546         mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 547         mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
 548         mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 549         mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 550         mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 551         mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 552         mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
 553         mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 554         mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 555         mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 556         mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 557         mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
 558         mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 559         mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 560         mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 561         mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 562         mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
 563         mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 564         mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 565         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 566         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 567         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
 568 };
 569
 570 static const u32 cz_golden_settings_a11[] =
 571 {
 572         mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
 573         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 574         mmGB_GPU_ID, 0x0000000f, 0x00000000,
 575         mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
 576         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 577         mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
 578         mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
 579         mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
 580         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
 581         mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
 582         mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
 583         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
 584 };
 585
 586 static const u32 cz_golden_common_all[] =
 587 {
 588         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 589         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
 590         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
 591         mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
 592         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 593         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 594         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
 595         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
 596 };
 597
 598 static const u32 cz_mgcg_cgcg_init[] =
 599 {
 600         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
 601         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 602         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 603         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 604         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
 605         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
 606         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
 607         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 608         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 609         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 610         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 611         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 612         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 613         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 614         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 615         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 616         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 617         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 618         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 619         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 620         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 621         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 622         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
 623         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 624         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 625         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 626         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 627         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 628         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 629         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 630         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 631         mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 632         mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 633         mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 634         mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 635         mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 636         mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 637         mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 638         mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
 639         mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 640         mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 641         mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 642         mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 643         mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
 644         mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 645         mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 646         mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 647         mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 648         mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
 649         mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 650         mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 651         mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 652         mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 653         mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 654         mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 655         mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 656         mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 657         mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 658         mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
 659         mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 660         mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 661         mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 662         mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 663         mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
 664         mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 665         mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 666         mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 667         mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 668         mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
 669         mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 670         mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 671         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 672         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 673         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
 674         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
 675 };
 676
 677 static const u32 stoney_golden_settings_a11[] =
 678 {
 679         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 680         mmGB_GPU_ID, 0x0000000f, 0x00000000,
 681         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
 682         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 683         mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
 684         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 685         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
 686         mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
 687         mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f1,
 688         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x10101010,
 689 };
 690
 691 static const u32 stoney_golden_common_all[] =
 692 {
 693         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 694         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000000,
 695         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
 696         mmGB_ADDR_CONFIG, 0xffffffff, 0x12010001,
 697         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 698         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 699         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
 700         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
 701 };
 702
 703 static const u32 stoney_mgcg_cgcg_init[] =
 704 {
 705         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 706         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
 707         mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
 708         mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
 709         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
 710 };
 711
 712
 713 static const char * const sq_edc_source_names[] = {
 714         "SQ_EDC_INFO_SOURCE_INVALID: No EDC error has occurred",
 715         "SQ_EDC_INFO_SOURCE_INST: EDC source is Instruction Fetch",
 716         "SQ_EDC_INFO_SOURCE_SGPR: EDC source is SGPR or SQC data return",
 717         "SQ_EDC_INFO_SOURCE_VGPR: EDC source is VGPR",
 718         "SQ_EDC_INFO_SOURCE_LDS: EDC source is LDS",
 719         "SQ_EDC_INFO_SOURCE_GDS: EDC source is GDS",
 720         "SQ_EDC_INFO_SOURCE_TA: EDC source is TA",
 721 };
 722
 723 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
 724 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
 725 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
 726 static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev);
 727 static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev);
 728 static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev);
 729 static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring);
 730 static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring);
 731
 732 static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
 733 {
 734         switch (adev->asic_type) {
 735         case CHIP_TOPAZ:
 736                 amdgpu_device_program_register_sequence(adev,
 737                                                         iceland_mgcg_cgcg_init,
 738                                                         ARRAY_SIZE(iceland_mgcg_cgcg_init));
 739                 amdgpu_device_program_register_sequence(adev,
 740                                                         golden_settings_iceland_a11,
 741                                                         ARRAY_SIZE(golden_settings_iceland_a11));
 742                 amdgpu_device_program_register_sequence(adev,
 743                                                         iceland_golden_common_all,
 744                                                         ARRAY_SIZE(iceland_golden_common_all));
 745                 break;
 746         case CHIP_FIJI:
 747                 amdgpu_device_program_register_sequence(adev,
 748                                                         fiji_mgcg_cgcg_init,
 749                                                         ARRAY_SIZE(fiji_mgcg_cgcg_init));
 750                 amdgpu_device_program_register_sequence(adev,
 751                                                         golden_settings_fiji_a10,
 752                                                         ARRAY_SIZE(golden_settings_fiji_a10));
 753                 amdgpu_device_program_register_sequence(adev,
 754                                                         fiji_golden_common_all,
 755                                                         ARRAY_SIZE(fiji_golden_common_all));
 756                 break;
 757
 758         case CHIP_TONGA:
 759                 amdgpu_device_program_register_sequence(adev,
 760                                                         tonga_mgcg_cgcg_init,
 761                                                         ARRAY_SIZE(tonga_mgcg_cgcg_init));
 762                 amdgpu_device_program_register_sequence(adev,
 763                                                         golden_settings_tonga_a11,
 764                                                         ARRAY_SIZE(golden_settings_tonga_a11));
 765                 amdgpu_device_program_register_sequence(adev,
 766                                                         tonga_golden_common_all,
 767                                                         ARRAY_SIZE(tonga_golden_common_all));
 768                 break;
 769         case CHIP_VEGAM:
 770                 amdgpu_device_program_register_sequence(adev,
 771                                                         golden_settings_vegam_a11,
 772                                                         ARRAY_SIZE(golden_settings_vegam_a11));
 773                 amdgpu_device_program_register_sequence(adev,
 774                                                         vegam_golden_common_all,
 775                                                         ARRAY_SIZE(vegam_golden_common_all));
 776                 break;
 777         case CHIP_POLARIS11:
 778         case CHIP_POLARIS12:
 779                 amdgpu_device_program_register_sequence(adev,
 780                                                         golden_settings_polaris11_a11,
 781                                                         ARRAY_SIZE(golden_settings_polaris11_a11));
 782                 amdgpu_device_program_register_sequence(adev,
 783                                                         polaris11_golden_common_all,
 784                                                         ARRAY_SIZE(polaris11_golden_common_all));
 785                 break;
 786         case CHIP_POLARIS10:
 787                 amdgpu_device_program_register_sequence(adev,
 788                                                         golden_settings_polaris10_a11,
 789                                                         ARRAY_SIZE(golden_settings_polaris10_a11));
 790                 amdgpu_device_program_register_sequence(adev,
 791                                                         polaris10_golden_common_all,
 792                                                         ARRAY_SIZE(polaris10_golden_common_all));
 793                 WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C);
 794                 if (adev->pdev->revision == 0xc7 &&
 795                     ((adev->pdev->subsystem_device == 0xb37 && adev->pdev->subsystem_vendor == 0x1002) ||
 796                      (adev->pdev->subsystem_device == 0x4a8 && adev->pdev->subsystem_vendor == 0x1043) ||
 797                      (adev->pdev->subsystem_device == 0x9480 && adev->pdev->subsystem_vendor == 0x1682))) {
 798                         amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1E, 0xDD);
 799                         amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1F, 0xD0);
 800                 }
 801                 break;
 802         case CHIP_CARRIZO:
 803                 amdgpu_device_program_register_sequence(adev,
 804                                                         cz_mgcg_cgcg_init,
 805                                                         ARRAY_SIZE(cz_mgcg_cgcg_init));
 806                 amdgpu_device_program_register_sequence(adev,
 807                                                         cz_golden_settings_a11,
 808                                                         ARRAY_SIZE(cz_golden_settings_a11));
 809                 amdgpu_device_program_register_sequence(adev,
 810                                                         cz_golden_common_all,
 811                                                         ARRAY_SIZE(cz_golden_common_all));
 812                 break;
 813         case CHIP_STONEY:
 814                 amdgpu_device_program_register_sequence(adev,
 815                                                         stoney_mgcg_cgcg_init,
 816                                                         ARRAY_SIZE(stoney_mgcg_cgcg_init));
 817                 amdgpu_device_program_register_sequence(adev,
 818                                                         stoney_golden_settings_a11,
 819                                                         ARRAY_SIZE(stoney_golden_settings_a11));
 820                 amdgpu_device_program_register_sequence(adev,
 821                                                         stoney_golden_common_all,
 822                                                         ARRAY_SIZE(stoney_golden_common_all));
 823                 break;
 824         default:
 825                 break;
 826         }
 827 }
 828
 829 static void gfx_v8_0_scratch_init(struct amdgpu_device *adev)
 830 {
 831         adev->gfx.scratch.num_reg = 8;
 832         adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
 833         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
 834 }
 835
 836 static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
 837 {
 838         struct amdgpu_device *adev = ring->adev;
 839         uint32_t scratch;
 840         uint32_t tmp = 0;
 841         unsigned i;
 842         int r;
 843
 844         r = amdgpu_gfx_scratch_get(adev, &scratch);
 845         if (r)
 846                 return r;
 847
 848         WREG32(scratch, 0xCAFEDEAD);
 849         r = amdgpu_ring_alloc(ring, 3);
 850         if (r)
 851                 goto error_free_scratch;
 852
 853         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 854         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
 855         amdgpu_ring_write(ring, 0xDEADBEEF);
 856         amdgpu_ring_commit(ring);
 857
 858         for (i = 0; i < adev->usec_timeout; i++) {
 859                 tmp = RREG32(scratch);
 860                 if (tmp == 0xDEADBEEF)
 861                         break;
 862                 udelay(1);
 863         }
 864
 865         if (i >= adev->usec_timeout)
 866                 r = -ETIMEDOUT;
 867
 868 error_free_scratch:
 869         amdgpu_gfx_scratch_free(adev, scratch);
 870         return r;
 871 }
 872
 873 static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 874 {
 875         struct amdgpu_device *adev = ring->adev;
 876         struct amdgpu_ib ib;
 877         struct dma_fence *f = NULL;
 878
 879         unsigned int index;
 880         uint64_t gpu_addr;
 881         uint32_t tmp;
 882         long r;
 883
 884         r = amdgpu_device_wb_get(adev, &index);
 885         if (r)
 886                 return r;
 887
 888         gpu_addr = adev->wb.gpu_addr + (index * 4);
 889         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
 890         memset(&ib, 0, sizeof(ib));
 891         r = amdgpu_ib_get(adev, NULL, 16, &ib);
 892         if (r)
 893                 goto err1;
 894
 895         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
 896         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
 897         ib.ptr[2] = lower_32_bits(gpu_addr);
 898         ib.ptr[3] = upper_32_bits(gpu_addr);
 899         ib.ptr[4] = 0xDEADBEEF;
 900         ib.length_dw = 5;
 901
 902         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 903         if (r)
 904                 goto err2;
 905
 906         r = dma_fence_wait_timeout(f, false, timeout);
 907         if (r == 0) {
 908                 r = -ETIMEDOUT;
 909                 goto err2;
 910         } else if (r < 0) {
 911                 goto err2;
 912         }
 913
 914         tmp = adev->wb.wb[index];
 915         if (tmp == 0xDEADBEEF)
 916                 r = 0;
 917         else
 918                 r = -EINVAL;
 919
 920 err2:
 921         amdgpu_ib_free(adev, &ib, NULL);
 922         dma_fence_put(f);
 923 err1:
 924         amdgpu_device_wb_free(adev, index);
 925         return r;
 926 }
 927
 928
 929 static void gfx_v8_0_free_microcode(struct amdgpu_device *adev)
 930 {
 931         release_firmware(adev->gfx.pfp_fw);
 932         adev->gfx.pfp_fw = NULL;
 933         release_firmware(adev->gfx.me_fw);
 934         adev->gfx.me_fw = NULL;
 935         release_firmware(adev->gfx.ce_fw);
 936         adev->gfx.ce_fw = NULL;
 937         release_firmware(adev->gfx.rlc_fw);
 938         adev->gfx.rlc_fw = NULL;
 939         release_firmware(adev->gfx.mec_fw);
 940         adev->gfx.mec_fw = NULL;
 941         if ((adev->asic_type != CHIP_STONEY) &&
 942             (adev->asic_type != CHIP_TOPAZ))
 943                 release_firmware(adev->gfx.mec2_fw);
 944         adev->gfx.mec2_fw = NULL;
 945
 946         kfree(adev->gfx.rlc.register_list_format);
 947 }
 948
 949 static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
 950 {
 951         const char *chip_name;
 952         char fw_name[30];
 953         int err;
 954         struct amdgpu_firmware_info *info = NULL;
 955         const struct common_firmware_header *header = NULL;
 956         const struct gfx_firmware_header_v1_0 *cp_hdr;
 957         const struct rlc_firmware_header_v2_0 *rlc_hdr;
 958         unsigned int *tmp = NULL, i;
 959
 960         DRM_DEBUG("\n");
 961
 962         switch (adev->asic_type) {
 963         case CHIP_TOPAZ:
 964                 chip_name = "topaz";
 965                 break;
 966         case CHIP_TONGA:
 967                 chip_name = "tonga";
 968                 break;
 969         case CHIP_CARRIZO:
 970                 chip_name = "carrizo";
 971                 break;
 972         case CHIP_FIJI:
 973                 chip_name = "fiji";
 974                 break;
 975         case CHIP_STONEY:
 976                 chip_name = "stoney";
 977                 break;
 978         case CHIP_POLARIS10:
 979                 chip_name = "polaris10";
 980                 break;
 981         case CHIP_POLARIS11:
 982                 chip_name = "polaris11";
 983                 break;
 984         case CHIP_POLARIS12:
 985                 chip_name = "polaris12";
 986                 break;
 987         case CHIP_VEGAM:
 988                 chip_name = "vegam";
 989                 break;
 990         default:
 991                 BUG();
 992         }
 993
 994         if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
 995                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp_2.bin", chip_name);
 996                 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 997                 if (err == -ENOENT) {
 998                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
 999                         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
1000                 }
1001         } else {
1002                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
1003                 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
1004         }
1005         if (err)
1006                 goto out;
1007         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
1008         if (err)
1009                 goto out;
1010         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
1011         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1012         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1013
1014         if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1015                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me_2.bin", chip_name);
1016                 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
1017                 if (err == -ENOENT) {
1018                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
1019                         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
1020                 }
1021         } else {
1022                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
1023                 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
1024         }
1025         if (err)
1026                 goto out;
1027         err = amdgpu_ucode_validate(adev->gfx.me_fw);
1028         if (err)
1029                 goto out;
1030         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1031         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1032
1033         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1034
1035         if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1036                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce_2.bin", chip_name);
1037                 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
1038                 if (err == -ENOENT) {
1039                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
1040                         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
1041                 }
1042         } else {
1043                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
1044                 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
1045         }
1046         if (err)
1047                 goto out;
1048         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
1049         if (err)
1050                 goto out;
1051         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1052         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1053         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1054
1055         /*
1056          * Support for MCBP/Virtualization in combination with chained IBs is
1057          * formal released on feature version #46
1058          */
1059         if (adev->gfx.ce_feature_version >= 46 &&
1060             adev->gfx.pfp_feature_version >= 46) {
1061                 adev->virt.chained_ib_support = true;
1062                 DRM_INFO("Chained IB support enabled!\n");
1063         } else
1064                 adev->virt.chained_ib_support = false;
1065
1066         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
1067         err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
1068         if (err)
1069                 goto out;
1070         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
1071         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1072         adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
1073         adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
1074
1075         adev->gfx.rlc.save_and_restore_offset =
1076                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
1077         adev->gfx.rlc.clear_state_descriptor_offset =
1078                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
1079         adev->gfx.rlc.avail_scratch_ram_locations =
1080                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
1081         adev->gfx.rlc.reg_restore_list_size =
1082                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
1083         adev->gfx.rlc.reg_list_format_start =
1084                         le32_to_cpu(rlc_hdr->reg_list_format_start);
1085         adev->gfx.rlc.reg_list_format_separate_start =
1086                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
1087         adev->gfx.rlc.starting_offsets_start =
1088                         le32_to_cpu(rlc_hdr->starting_offsets_start);
1089         adev->gfx.rlc.reg_list_format_size_bytes =
1090                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
1091         adev->gfx.rlc.reg_list_size_bytes =
1092                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
1093
1094         adev->gfx.rlc.register_list_format =
1095                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
1096                                         adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
1097
1098         if (!adev->gfx.rlc.register_list_format) {
1099                 err = -ENOMEM;
1100                 goto out;
1101         }
1102
1103         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
1104                         le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
1105         for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++)
1106                 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
1107
1108         adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
1109
1110         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
1111                         le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
1112         for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++)
1113                 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
1114
1115         if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1116                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec_2.bin", chip_name);
1117                 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
1118                 if (err == -ENOENT) {
1119                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
1120                         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
1121                 }
1122         } else {
1123                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
1124                 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
1125         }
1126         if (err)
1127                 goto out;
1128         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
1129         if (err)
1130                 goto out;
1131         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1132         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1133         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1134
1135         if ((adev->asic_type != CHIP_STONEY) &&
1136             (adev->asic_type != CHIP_TOPAZ)) {
1137                 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1138                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2_2.bin", chip_name);
1139                         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
1140                         if (err == -ENOENT) {
1141                                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
1142                                 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
1143                         }
1144                 } else {
1145                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
1146                         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
1147                 }
1148                 if (!err) {
1149                         err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
1150                         if (err)
1151                                 goto out;
1152                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1153                                 adev->gfx.mec2_fw->data;
1154                         adev->gfx.mec2_fw_version =
1155                                 le32_to_cpu(cp_hdr->header.ucode_version);
1156                         adev->gfx.mec2_feature_version =
1157                                 le32_to_cpu(cp_hdr->ucode_feature_version);
1158                 } else {
1159                         err = 0;
1160                         adev->gfx.mec2_fw = NULL;
1161                 }
1162         }
1163
1164         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
1165         info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
1166         info->fw = adev->gfx.pfp_fw;
1167         header = (const struct common_firmware_header *)info->fw->data;
1168         adev->firmware.fw_size +=
1169                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1170
1171         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
1172         info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
1173         info->fw = adev->gfx.me_fw;
1174         header = (const struct common_firmware_header *)info->fw->data;
1175         adev->firmware.fw_size +=
1176                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1177
1178         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
1179         info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
1180         info->fw = adev->gfx.ce_fw;
1181         header = (const struct common_firmware_header *)info->fw->data;
1182         adev->firmware.fw_size +=
1183                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1184
1185         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
1186         info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
1187         info->fw = adev->gfx.rlc_fw;
1188         header = (const struct common_firmware_header *)info->fw->data;
1189         adev->firmware.fw_size +=
1190                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1191
1192         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
1193         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
1194         info->fw = adev->gfx.mec_fw;
1195         header = (const struct common_firmware_header *)info->fw->data;
1196         adev->firmware.fw_size +=
1197                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1198
1199         /* we need account JT in */
1200         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1201         adev->firmware.fw_size +=
1202                 ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
1203
1204         if (amdgpu_sriov_vf(adev)) {
1205                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_STORAGE];
1206                 info->ucode_id = AMDGPU_UCODE_ID_STORAGE;
1207                 info->fw = adev->gfx.mec_fw;
1208                 adev->firmware.fw_size +=
1209                         ALIGN(le32_to_cpu(64 * PAGE_SIZE), PAGE_SIZE);
1210         }
1211
1212         if (adev->gfx.mec2_fw) {
1213                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
1214                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
1215                 info->fw = adev->gfx.mec2_fw;
1216                 header = (const struct common_firmware_header *)info->fw->data;
1217                 adev->firmware.fw_size +=
1218                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1219         }
1220
1221 out:
1222         if (err) {
1223                 dev_err(adev->dev,
1224                         "gfx8: Failed to load firmware \"%s\"\n",
1225                         fw_name);
1226                 release_firmware(adev->gfx.pfp_fw);
1227                 adev->gfx.pfp_fw = NULL;
1228                 release_firmware(adev->gfx.me_fw);
1229                 adev->gfx.me_fw = NULL;
1230                 release_firmware(adev->gfx.ce_fw);
1231                 adev->gfx.ce_fw = NULL;
1232                 release_firmware(adev->gfx.rlc_fw);
1233                 adev->gfx.rlc_fw = NULL;
1234                 release_firmware(adev->gfx.mec_fw);
1235                 adev->gfx.mec_fw = NULL;
1236                 release_firmware(adev->gfx.mec2_fw);
1237                 adev->gfx.mec2_fw = NULL;
1238         }
1239         return err;
1240 }
1241
1242 static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev,
1243                                     volatile u32 *buffer)
1244 {
1245         u32 count = 0, i;
1246         const struct cs_section_def *sect = NULL;
1247         const struct cs_extent_def *ext = NULL;
1248
1249         if (adev->gfx.rlc.cs_data == NULL)
1250                 return;
1251         if (buffer == NULL)
1252                 return;
1253
1254         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1255         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1256
1257         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
1258         buffer[count++] = cpu_to_le32(0x80000000);
1259         buffer[count++] = cpu_to_le32(0x80000000);
1260
1261         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
1262                 for (ext = sect->section; ext->extent != NULL; ++ext) {
1263                         if (sect->id == SECT_CONTEXT) {
1264                                 buffer[count++] =
1265                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
1266                                 buffer[count++] = cpu_to_le32(ext->reg_index -
1267                                                 PACKET3_SET_CONTEXT_REG_START);
1268                                 for (i = 0; i < ext->reg_count; i++)
1269                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
1270                         } else {
1271                                 return;
1272                         }
1273                 }
1274         }
1275
1276         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
1277         buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG -
1278                         PACKET3_SET_CONTEXT_REG_START);
1279         buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config);
1280         buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1);
1281
1282         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1283         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
1284
1285         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
1286         buffer[count++] = cpu_to_le32(0);
1287 }
1288
1289 static int gfx_v8_0_cp_jump_table_num(struct amdgpu_device *adev)
1290 {
1291         if (adev->asic_type == CHIP_CARRIZO)
1292                 return 5;
1293         else
1294                 return 4;
1295 }
1296
1297 static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
1298 {
1299         const struct cs_section_def *cs_data;
1300         int r;
1301
1302         adev->gfx.rlc.cs_data = vi_cs_data;
1303
1304         cs_data = adev->gfx.rlc.cs_data;
1305
1306         if (cs_data) {
1307                 /* init clear state block */
1308                 r = amdgpu_gfx_rlc_init_csb(adev);
1309                 if (r)
1310                         return r;
1311         }
1312
1313         if ((adev->asic_type == CHIP_CARRIZO) ||
1314             (adev->asic_type == CHIP_STONEY)) {
1315                 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
1316                 r = amdgpu_gfx_rlc_init_cpt(adev);
1317                 if (r)
1318                         return r;
1319         }
1320
1321         return 0;
1322 }
1323
1324 static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
1325 {
1326         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
1327 }
1328
1329 static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
1330 {
1331         int r;
1332         u32 *hpd;
1333         size_t mec_hpd_size;
1334
1335         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1336
1337         /* take ownership of the relevant compute queues */
1338         amdgpu_gfx_compute_queue_acquire(adev);
1339
1340         mec_hpd_size = adev->gfx.num_compute_rings * GFX8_MEC_HPD_SIZE;
1341
1342         r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
1343                                       AMDGPU_GEM_DOMAIN_VRAM,
1344                                       &adev->gfx.mec.hpd_eop_obj,
1345                                       &adev->gfx.mec.hpd_eop_gpu_addr,
1346                                       (void **)&hpd);
1347         if (r) {
1348                 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1349                 return r;
1350         }
1351
1352         memset(hpd, 0, mec_hpd_size);
1353
1354         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1355         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1356
1357         return 0;
1358 }
1359
1360 static const u32 vgpr_init_compute_shader[] =
1361 {
1362         0x7e000209, 0x7e020208,
1363         0x7e040207, 0x7e060206,
1364         0x7e080205, 0x7e0a0204,
1365         0x7e0c0203, 0x7e0e0202,
1366         0x7e100201, 0x7e120200,
1367         0x7e140209, 0x7e160208,
1368         0x7e180207, 0x7e1a0206,
1369         0x7e1c0205, 0x7e1e0204,
1370         0x7e200203, 0x7e220202,
1371         0x7e240201, 0x7e260200,
1372         0x7e280209, 0x7e2a0208,
1373         0x7e2c0207, 0x7e2e0206,
1374         0x7e300205, 0x7e320204,
1375         0x7e340203, 0x7e360202,
1376         0x7e380201, 0x7e3a0200,
1377         0x7e3c0209, 0x7e3e0208,
1378         0x7e400207, 0x7e420206,
1379         0x7e440205, 0x7e460204,
1380         0x7e480203, 0x7e4a0202,
1381         0x7e4c0201, 0x7e4e0200,
1382         0x7e500209, 0x7e520208,
1383         0x7e540207, 0x7e560206,
1384         0x7e580205, 0x7e5a0204,
1385         0x7e5c0203, 0x7e5e0202,
1386         0x7e600201, 0x7e620200,
1387         0x7e640209, 0x7e660208,
1388         0x7e680207, 0x7e6a0206,
1389         0x7e6c0205, 0x7e6e0204,
1390         0x7e700203, 0x7e720202,
1391         0x7e740201, 0x7e760200,
1392         0x7e780209, 0x7e7a0208,
1393         0x7e7c0207, 0x7e7e0206,
1394         0xbf8a0000, 0xbf810000,
1395 };
1396
1397 static const u32 sgpr_init_compute_shader[] =
1398 {
1399         0xbe8a0100, 0xbe8c0102,
1400         0xbe8e0104, 0xbe900106,
1401         0xbe920108, 0xbe940100,
1402         0xbe960102, 0xbe980104,
1403         0xbe9a0106, 0xbe9c0108,
1404         0xbe9e0100, 0xbea00102,
1405         0xbea20104, 0xbea40106,
1406         0xbea60108, 0xbea80100,
1407         0xbeaa0102, 0xbeac0104,
1408         0xbeae0106, 0xbeb00108,
1409         0xbeb20100, 0xbeb40102,
1410         0xbeb60104, 0xbeb80106,
1411         0xbeba0108, 0xbebc0100,
1412         0xbebe0102, 0xbec00104,
1413         0xbec20106, 0xbec40108,
1414         0xbec60100, 0xbec80102,
1415         0xbee60004, 0xbee70005,
1416         0xbeea0006, 0xbeeb0007,
1417         0xbee80008, 0xbee90009,
1418         0xbefc0000, 0xbf8a0000,
1419         0xbf810000, 0x00000000,
1420 };
1421
1422 static const u32 vgpr_init_regs[] =
1423 {
1424         mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xffffffff,
1425         mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */
1426         mmCOMPUTE_NUM_THREAD_X, 256*4,
1427         mmCOMPUTE_NUM_THREAD_Y, 1,
1428         mmCOMPUTE_NUM_THREAD_Z, 1,
1429         mmCOMPUTE_PGM_RSRC1, 0x100004f, /* VGPRS=15 (64 logical VGPRs), SGPRS=1 (16 SGPRs), BULKY=1 */
1430         mmCOMPUTE_PGM_RSRC2, 20,
1431         mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1432         mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1433         mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1434         mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1435         mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1436         mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1437         mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1438         mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1439         mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1440         mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1441 };
1442
1443 static const u32 sgpr1_init_regs[] =
1444 {
1445         mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0x0f,
1446         mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */
1447         mmCOMPUTE_NUM_THREAD_X, 256*5,
1448         mmCOMPUTE_NUM_THREAD_Y, 1,
1449         mmCOMPUTE_NUM_THREAD_Z, 1,
1450         mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
1451         mmCOMPUTE_PGM_RSRC2, 20,
1452         mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1453         mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1454         mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1455         mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1456         mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1457         mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1458         mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1459         mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1460         mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1461         mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1462 };
1463
1464 static const u32 sgpr2_init_regs[] =
1465 {
1466         mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xf0,
1467         mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,
1468         mmCOMPUTE_NUM_THREAD_X, 256*5,
1469         mmCOMPUTE_NUM_THREAD_Y, 1,
1470         mmCOMPUTE_NUM_THREAD_Z, 1,
1471         mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
1472         mmCOMPUTE_PGM_RSRC2, 20,
1473         mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1474         mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1475         mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1476         mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1477         mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1478         mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1479         mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1480         mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1481         mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1482         mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1483 };
1484
1485 static const u32 sec_ded_counter_registers[] =
1486 {
1487         mmCPC_EDC_ATC_CNT,
1488         mmCPC_EDC_SCRATCH_CNT,
1489         mmCPC_EDC_UCODE_CNT,
1490         mmCPF_EDC_ATC_CNT,
1491         mmCPF_EDC_ROQ_CNT,
1492         mmCPF_EDC_TAG_CNT,
1493         mmCPG_EDC_ATC_CNT,
1494         mmCPG_EDC_DMA_CNT,
1495         mmCPG_EDC_TAG_CNT,
1496         mmDC_EDC_CSINVOC_CNT,
1497         mmDC_EDC_RESTORE_CNT,
1498         mmDC_EDC_STATE_CNT,
1499         mmGDS_EDC_CNT,
1500         mmGDS_EDC_GRBM_CNT,
1501         mmGDS_EDC_OA_DED,
1502         mmSPI_EDC_CNT,
1503         mmSQC_ATC_EDC_GATCL1_CNT,
1504         mmSQC_EDC_CNT,
1505         mmSQ_EDC_DED_CNT,
1506         mmSQ_EDC_INFO,
1507         mmSQ_EDC_SEC_CNT,
1508         mmTCC_EDC_CNT,
1509         mmTCP_ATC_EDC_GATCL1_CNT,
1510         mmTCP_EDC_CNT,
1511         mmTD_EDC_CNT
1512 };
1513
1514 static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
1515 {
1516         struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
1517         struct amdgpu_ib ib;
1518         struct dma_fence *f = NULL;
1519         int r, i;
1520         u32 tmp;
1521         unsigned total_size, vgpr_offset, sgpr_offset;
1522         u64 gpu_addr;
1523
1524         /* only supported on CZ */
1525         if (adev->asic_type != CHIP_CARRIZO)
1526                 return 0;
1527
1528         /* bail if the compute ring is not ready */
1529         if (!ring->sched.ready)
1530                 return 0;
1531
1532         tmp = RREG32(mmGB_EDC_MODE);
1533         WREG32(mmGB_EDC_MODE, 0);
1534
1535         total_size =
1536                 (((ARRAY_SIZE(vgpr_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1537         total_size +=
1538                 (((ARRAY_SIZE(sgpr1_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1539         total_size +=
1540                 (((ARRAY_SIZE(sgpr2_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1541         total_size = ALIGN(total_size, 256);
1542         vgpr_offset = total_size;
1543         total_size += ALIGN(sizeof(vgpr_init_compute_shader), 256);
1544         sgpr_offset = total_size;
1545         total_size += sizeof(sgpr_init_compute_shader);
1546
1547         /* allocate an indirect buffer to put the commands in */
1548         memset(&ib, 0, sizeof(ib));
1549         r = amdgpu_ib_get(adev, NULL, total_size, &ib);
1550         if (r) {
1551                 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
1552                 return r;
1553         }
1554
1555         /* load the compute shaders */
1556         for (i = 0; i < ARRAY_SIZE(vgpr_init_compute_shader); i++)
1557                 ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_compute_shader[i];
1558
1559         for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++)
1560                 ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i];
1561
1562         /* init the ib length to 0 */
1563         ib.length_dw = 0;
1564
1565         /* VGPR */
1566         /* write the register state for the compute dispatch */
1567         for (i = 0; i < ARRAY_SIZE(vgpr_init_regs); i += 2) {
1568                 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1569                 ib.ptr[ib.length_dw++] = vgpr_init_regs[i] - PACKET3_SET_SH_REG_START;
1570                 ib.ptr[ib.length_dw++] = vgpr_init_regs[i + 1];
1571         }
1572         /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1573         gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8;
1574         ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1575         ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1576         ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1577         ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1578
1579         /* write dispatch packet */
1580         ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1581         ib.ptr[ib.length_dw++] = 8; /* x */
1582         ib.ptr[ib.length_dw++] = 1; /* y */
1583         ib.ptr[ib.length_dw++] = 1; /* z */
1584         ib.ptr[ib.length_dw++] =
1585                 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1586
1587         /* write CS partial flush packet */
1588         ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1589         ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1590
1591         /* SGPR1 */
1592         /* write the register state for the compute dispatch */
1593         for (i = 0; i < ARRAY_SIZE(sgpr1_init_regs); i += 2) {
1594                 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1595                 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i] - PACKET3_SET_SH_REG_START;
1596                 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i + 1];
1597         }
1598         /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1599         gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
1600         ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1601         ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1602         ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1603         ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1604
1605         /* write dispatch packet */
1606         ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1607         ib.ptr[ib.length_dw++] = 8; /* x */
1608         ib.ptr[ib.length_dw++] = 1; /* y */
1609         ib.ptr[ib.length_dw++] = 1; /* z */
1610         ib.ptr[ib.length_dw++] =
1611                 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1612
1613         /* write CS partial flush packet */
1614         ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1615         ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1616
1617         /* SGPR2 */
1618         /* write the register state for the compute dispatch */
1619         for (i = 0; i < ARRAY_SIZE(sgpr2_init_regs); i += 2) {
1620                 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1621                 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i] - PACKET3_SET_SH_REG_START;
1622                 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i + 1];
1623         }
1624         /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1625         gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
1626         ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1627         ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1628         ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1629         ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1630
1631         /* write dispatch packet */
1632         ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1633         ib.ptr[ib.length_dw++] = 8; /* x */
1634         ib.ptr[ib.length_dw++] = 1; /* y */
1635         ib.ptr[ib.length_dw++] = 1; /* z */
1636         ib.ptr[ib.length_dw++] =
1637                 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1638
1639         /* write CS partial flush packet */
1640         ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1641         ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1642
1643         /* shedule the ib on the ring */
1644         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1645         if (r) {
1646                 DRM_ERROR("amdgpu: ib submit failed (%d).\n", r);
1647                 goto fail;
1648         }
1649
1650         /* wait for the GPU to finish processing the IB */
1651         r = dma_fence_wait(f, false);
1652         if (r) {
1653                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
1654                 goto fail;
1655         }
1656
1657         tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2);
1658         tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1);
1659         WREG32(mmGB_EDC_MODE, tmp);
1660
1661         tmp = RREG32(mmCC_GC_EDC_CONFIG);
1662         tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1;
1663         WREG32(mmCC_GC_EDC_CONFIG, tmp);
1664
1665
1666         /* read back registers to clear the counters */
1667         for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++)
1668                 RREG32(sec_ded_counter_registers[i]);
1669
1670 fail:
1671         amdgpu_ib_free(adev, &ib, NULL);
1672         dma_fence_put(f);
1673
1674         return r;
1675 }
1676
1677 static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
1678 {
1679         u32 gb_addr_config;
1680         u32 mc_shared_chmap, mc_arb_ramcfg;
1681         u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
1682         u32 tmp;
1683         int ret;
1684
1685         switch (adev->asic_type) {
1686         case CHIP_TOPAZ:
1687                 adev->gfx.config.max_shader_engines = 1;
1688                 adev->gfx.config.max_tile_pipes = 2;
1689                 adev->gfx.config.max_cu_per_sh = 6;
1690                 adev->gfx.config.max_sh_per_se = 1;
1691                 adev->gfx.config.max_backends_per_se = 2;
1692                 adev->gfx.config.max_texture_channel_caches = 2;
1693                 adev->gfx.config.max_gprs = 256;
1694                 adev->gfx.config.max_gs_threads = 32;
1695                 adev->gfx.config.max_hw_contexts = 8;
1696
1697                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1698                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1699                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1700                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1701                 gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
1702                 break;
1703         case CHIP_FIJI:
1704                 adev->gfx.config.max_shader_engines = 4;
1705                 adev->gfx.config.max_tile_pipes = 16;
1706                 adev->gfx.config.max_cu_per_sh = 16;
1707                 adev->gfx.config.max_sh_per_se = 1;
1708                 adev->gfx.config.max_backends_per_se = 4;
1709                 adev->gfx.config.max_texture_channel_caches = 16;
1710                 adev->gfx.config.max_gprs = 256;
1711                 adev->gfx.config.max_gs_threads = 32;
1712                 adev->gfx.config.max_hw_contexts = 8;
1713
1714                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1715                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1716                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1717                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1718                 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1719                 break;
1720         case CHIP_POLARIS11:
1721         case CHIP_POLARIS12:
1722                 ret = amdgpu_atombios_get_gfx_info(adev);
1723                 if (ret)
1724                         return ret;
1725                 adev->gfx.config.max_gprs = 256;
1726                 adev->gfx.config.max_gs_threads = 32;
1727                 adev->gfx.config.max_hw_contexts = 8;
1728
1729                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1730                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1731                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1732                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1733                 gb_addr_config = POLARIS11_GB_ADDR_CONFIG_GOLDEN;
1734                 break;
1735         case CHIP_POLARIS10:
1736         case CHIP_VEGAM:
1737                 ret = amdgpu_atombios_get_gfx_info(adev);
1738                 if (ret)
1739                         return ret;
1740                 adev->gfx.config.max_gprs = 256;
1741                 adev->gfx.config.max_gs_threads = 32;
1742                 adev->gfx.config.max_hw_contexts = 8;
1743
1744                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1745                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1746                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1747                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1748                 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1749                 break;
1750         case CHIP_TONGA:
1751                 adev->gfx.config.max_shader_engines = 4;
1752                 adev->gfx.config.max_tile_pipes = 8;
1753                 adev->gfx.config.max_cu_per_sh = 8;
1754                 adev->gfx.config.max_sh_per_se = 1;
1755                 adev->gfx.config.max_backends_per_se = 2;
1756                 adev->gfx.config.max_texture_channel_caches = 8;
1757                 adev->gfx.config.max_gprs = 256;
1758                 adev->gfx.config.max_gs_threads = 32;
1759                 adev->gfx.config.max_hw_contexts = 8;
1760
1761                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1762                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1763                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1764                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1765                 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1766                 break;
1767         case CHIP_CARRIZO:
1768                 adev->gfx.config.max_shader_engines = 1;
1769                 adev->gfx.config.max_tile_pipes = 2;
1770                 adev->gfx.config.max_sh_per_se = 1;
1771                 adev->gfx.config.max_backends_per_se = 2;
1772                 adev->gfx.config.max_cu_per_sh = 8;
1773                 adev->gfx.config.max_texture_channel_caches = 2;
1774                 adev->gfx.config.max_gprs = 256;
1775                 adev->gfx.config.max_gs_threads = 32;
1776                 adev->gfx.config.max_hw_contexts = 8;
1777
1778                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1779                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1780                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1781                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1782                 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1783                 break;
1784         case CHIP_STONEY:
1785                 adev->gfx.config.max_shader_engines = 1;
1786                 adev->gfx.config.max_tile_pipes = 2;
1787                 adev->gfx.config.max_sh_per_se = 1;
1788                 adev->gfx.config.max_backends_per_se = 1;
1789                 adev->gfx.config.max_cu_per_sh = 3;
1790                 adev->gfx.config.max_texture_channel_caches = 2;
1791                 adev->gfx.config.max_gprs = 256;
1792                 adev->gfx.config.max_gs_threads = 16;
1793                 adev->gfx.config.max_hw_contexts = 8;
1794
1795                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1796                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1797                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1798                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1799                 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1800                 break;
1801         default:
1802                 adev->gfx.config.max_shader_engines = 2;
1803                 adev->gfx.config.max_tile_pipes = 4;
1804                 adev->gfx.config.max_cu_per_sh = 2;
1805                 adev->gfx.config.max_sh_per_se = 1;
1806                 adev->gfx.config.max_backends_per_se = 2;
1807                 adev->gfx.config.max_texture_channel_caches = 4;
1808                 adev->gfx.config.max_gprs = 256;
1809                 adev->gfx.config.max_gs_threads = 32;
1810                 adev->gfx.config.max_hw_contexts = 8;
1811
1812                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1813                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1814                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1815                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1816                 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1817                 break;
1818         }
1819
1820         mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
1821         adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1822         mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
1823
1824         adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1825         adev->gfx.config.mem_max_burst_length_bytes = 256;
1826         if (adev->flags & AMD_IS_APU) {
1827                 /* Get memory bank mapping mode. */
1828                 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
1829                 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1830                 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1831
1832                 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
1833                 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1834                 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1835
1836                 /* Validate settings in case only one DIMM installed. */
1837                 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
1838                         dimm00_addr_map = 0;
1839                 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
1840                         dimm01_addr_map = 0;
1841                 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
1842                         dimm10_addr_map = 0;
1843                 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
1844                         dimm11_addr_map = 0;
1845
1846                 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
1847                 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
1848                 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
1849                         adev->gfx.config.mem_row_size_in_kb = 2;
1850                 else
1851                         adev->gfx.config.mem_row_size_in_kb = 1;
1852         } else {
1853                 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
1854                 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1855                 if (adev->gfx.config.mem_row_size_in_kb > 4)
1856                         adev->gfx.config.mem_row_size_in_kb = 4;
1857         }
1858
1859         adev->gfx.config.shader_engine_tile_size = 32;
1860         adev->gfx.config.num_gpus = 1;
1861         adev->gfx.config.multi_gpu_tile_size = 64;
1862
1863         /* fix up row size */
1864         switch (adev->gfx.config.mem_row_size_in_kb) {
1865         case 1:
1866         default:
1867                 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
1868                 break;
1869         case 2:
1870                 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
1871                 break;
1872         case 4:
1873                 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
1874                 break;
1875         }
1876         adev->gfx.config.gb_addr_config = gb_addr_config;
1877
1878         return 0;
1879 }
1880
1881 static int gfx_v8_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1882                                         int mec, int pipe, int queue)
1883 {
1884         int r;
1885         unsigned irq_type;
1886         struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1887
1888         ring = &adev->gfx.compute_ring[ring_id];
1889
1890         /* mec0 is me1 */
1891         ring->me = mec + 1;
1892         ring->pipe = pipe;
1893         ring->queue = queue;
1894
1895         ring->ring_obj = NULL;
1896         ring->use_doorbell = true;
1897         ring->doorbell_index = adev->doorbell_index.mec_ring0 + ring_id;
1898         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1899                                 + (ring_id * GFX8_MEC_HPD_SIZE);
1900         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1901
1902         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1903                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1904                 + ring->pipe;
1905
1906         /* type-2 packets are deprecated on MEC, use type-3 instead */
1907         r = amdgpu_ring_init(adev, ring, 1024,
1908                         &adev->gfx.eop_irq, irq_type);
1909         if (r)
1910                 return r;
1911
1912
1913         return 0;
1914 }
1915
1916 static void gfx_v8_0_sq_irq_work_func(struct work_struct *work);
1917
1918 static int gfx_v8_0_sw_init(void *handle)
1919 {
1920         int i, j, k, r, ring_id;
1921         struct amdgpu_ring *ring;
1922         struct amdgpu_kiq *kiq;
1923         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1924
1925         switch (adev->asic_type) {
1926         case CHIP_TONGA:
1927         case CHIP_CARRIZO:
1928         case CHIP_FIJI:
1929         case CHIP_POLARIS10:
1930         case CHIP_POLARIS11:
1931         case CHIP_POLARIS12:
1932         case CHIP_VEGAM:
1933                 adev->gfx.mec.num_mec = 2;
1934                 break;
1935         case CHIP_TOPAZ:
1936         case CHIP_STONEY:
1937         default:
1938                 adev->gfx.mec.num_mec = 1;
1939                 break;
1940         }
1941
1942         adev->gfx.mec.num_pipe_per_mec = 4;
1943         adev->gfx.mec.num_queue_per_pipe = 8;
1944
1945         /* EOP Event */
1946         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_END_OF_PIPE, &adev->gfx.eop_irq);
1947         if (r)
1948                 return r;
1949
1950         /* Privileged reg */
1951         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_REG_FAULT,
1952                               &adev->gfx.priv_reg_irq);
1953         if (r)
1954                 return r;
1955
1956         /* Privileged inst */
1957         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_INSTR_FAULT,
1958                               &adev->gfx.priv_inst_irq);
1959         if (r)
1960                 return r;
1961
1962         /* Add CP EDC/ECC irq  */
1963         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_ECC_ERROR,
1964                               &adev->gfx.cp_ecc_error_irq);
1965         if (r)
1966                 return r;
1967
1968         /* SQ interrupts. */
1969         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SQ_INTERRUPT_MSG,
1970                               &adev->gfx.sq_irq);
1971         if (r) {
1972                 DRM_ERROR("amdgpu_irq_add() for SQ failed: %d\n", r);
1973                 return r;
1974         }
1975
1976         INIT_WORK(&adev->gfx.sq_work.work, gfx_v8_0_sq_irq_work_func);
1977
1978         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1979
1980         gfx_v8_0_scratch_init(adev);
1981
1982         r = gfx_v8_0_init_microcode(adev);
1983         if (r) {
1984                 DRM_ERROR("Failed to load gfx firmware!\n");
1985                 return r;
1986         }
1987
1988         r = adev->gfx.rlc.funcs->init(adev);
1989         if (r) {
1990                 DRM_ERROR("Failed to init rlc BOs!\n");
1991                 return r;
1992         }
1993
1994         r = gfx_v8_0_mec_init(adev);
1995         if (r) {
1996                 DRM_ERROR("Failed to init MEC BOs!\n");
1997                 return r;
1998         }
1999
2000         /* set up the gfx ring */
2001         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
2002                 ring = &adev->gfx.gfx_ring[i];
2003                 ring->ring_obj = NULL;
2004                 sprintf(ring->name, "gfx");
2005                 /* no gfx doorbells on iceland */
2006                 if (adev->asic_type != CHIP_TOPAZ) {
2007                         ring->use_doorbell = true;
2008                         ring->doorbell_index = adev->doorbell_index.gfx_ring0;
2009                 }
2010
2011                 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq,
2012                                      AMDGPU_CP_IRQ_GFX_EOP);
2013                 if (r)
2014                         return r;
2015         }
2016
2017
2018         /* set up the compute queues - allocate horizontally across pipes */
2019         ring_id = 0;
2020         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
2021                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
2022                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
2023                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
2024                                         continue;
2025
2026                                 r = gfx_v8_0_compute_ring_init(adev,
2027                                                                 ring_id,
2028                                                                 i, k, j);
2029                                 if (r)
2030                                         return r;
2031
2032                                 ring_id++;
2033                         }
2034                 }
2035         }
2036
2037         r = amdgpu_gfx_kiq_init(adev, GFX8_MEC_HPD_SIZE);
2038         if (r) {
2039                 DRM_ERROR("Failed to init KIQ BOs!\n");
2040                 return r;
2041         }
2042
2043         kiq = &adev->gfx.kiq;
2044         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
2045         if (r)
2046                 return r;
2047
2048         /* create MQD for all compute queues as well as KIQ for SRIOV case */
2049         r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct vi_mqd_allocation));
2050         if (r)
2051                 return r;
2052
2053         adev->gfx.ce_ram_size = 0x8000;
2054
2055         r = gfx_v8_0_gpu_early_init(adev);
2056         if (r)
2057                 return r;
2058
2059         return 0;
2060 }
2061
2062 static int gfx_v8_0_sw_fini(void *handle)
2063 {
2064         int i;
2065         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2066
2067         amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
2068         amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
2069         amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
2070
2071         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2072                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
2073         for (i = 0; i < adev->gfx.num_compute_rings; i++)
2074                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
2075
2076         amdgpu_gfx_compute_mqd_sw_fini(adev);
2077         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
2078         amdgpu_gfx_kiq_fini(adev);
2079
2080         gfx_v8_0_mec_fini(adev);
2081         amdgpu_gfx_rlc_fini(adev);
2082         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
2083                                 &adev->gfx.rlc.clear_state_gpu_addr,
2084                                 (void **)&adev->gfx.rlc.cs_ptr);
2085         if ((adev->asic_type == CHIP_CARRIZO) ||
2086             (adev->asic_type == CHIP_STONEY)) {
2087                 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
2088                                 &adev->gfx.rlc.cp_table_gpu_addr,
2089                                 (void **)&adev->gfx.rlc.cp_table_ptr);
2090         }
2091         gfx_v8_0_free_microcode(adev);
2092
2093         return 0;
2094 }
2095
2096 static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
2097 {
2098         uint32_t *modearray, *mod2array;
2099         const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);
2100         const u32 num_secondary_tile_mode_states = ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
2101         u32 reg_offset;
2102
2103         modearray = adev->gfx.config.tile_mode_array;
2104         mod2array = adev->gfx.config.macrotile_mode_array;
2105
2106         for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2107                 modearray[reg_offset] = 0;
2108
2109         for (reg_offset = 0; reg_offset <  num_secondary_tile_mode_states; reg_offset++)
2110                 mod2array[reg_offset] = 0;
2111
2112         switch (adev->asic_type) {
2113         case CHIP_TOPAZ:
2114                 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2115                                 PIPE_CONFIG(ADDR_SURF_P2) |
2116                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2117                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2118                 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2119                                 PIPE_CONFIG(ADDR_SURF_P2) |
2120                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2121                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2122                 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2123                                 PIPE_CONFIG(ADDR_SURF_P2) |
2124                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2125                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2126                 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2127                                 PIPE_CONFIG(ADDR_SURF_P2) |
2128                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2129                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2130                 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2131                                 PIPE_CONFIG(ADDR_SURF_P2) |
2132                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2133                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2134                 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2135                                 PIPE_CONFIG(ADDR_SURF_P2) |
2136                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2137                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2138                 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2139                                 PIPE_CONFIG(ADDR_SURF_P2) |
2140                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2141                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2142                 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2143                                 PIPE_CONFIG(ADDR_SURF_P2));
2144                 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2145                                 PIPE_CONFIG(ADDR_SURF_P2) |
2146                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2147                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2148                 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2149                                  PIPE_CONFIG(ADDR_SURF_P2) |
2150                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2151                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2152                 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2153                                  PIPE_CONFIG(ADDR_SURF_P2) |
2154                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2155                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2156                 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2157                                  PIPE_CONFIG(ADDR_SURF_P2) |
2158                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2159                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2160                 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2161                                  PIPE_CONFIG(ADDR_SURF_P2) |
2162                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2163                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2164                 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2165                                  PIPE_CONFIG(ADDR_SURF_P2) |
2166                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2167                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2168                 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2169                                  PIPE_CONFIG(ADDR_SURF_P2) |
2170                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2171                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2172                 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2173                                  PIPE_CONFIG(ADDR_SURF_P2) |
2174                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2175                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2176                 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2177                                  PIPE_CONFIG(ADDR_SURF_P2) |
2178                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2179                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2180                 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2181                                  PIPE_CONFIG(ADDR_SURF_P2) |
2182                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2183                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2184                 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2185                                  PIPE_CONFIG(ADDR_SURF_P2) |
2186                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2187                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2188                 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2189                                  PIPE_CONFIG(ADDR_SURF_P2) |
2190                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2191                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2192                 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2193                                  PIPE_CONFIG(ADDR_SURF_P2) |
2194                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2195                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2196                 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2197                                  PIPE_CONFIG(ADDR_SURF_P2) |
2198                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2199                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2200                 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2201                                  PIPE_CONFIG(ADDR_SURF_P2) |
2202                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2203                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2204                 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2205                                  PIPE_CONFIG(ADDR_SURF_P2) |
2206                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2207                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2208                 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2209                                  PIPE_CONFIG(ADDR_SURF_P2) |
2210                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2211                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2212                 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2213                                  PIPE_CONFIG(ADDR_SURF_P2) |
2214                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2215                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2216
2217                 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2218                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2219                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2220                                 NUM_BANKS(ADDR_SURF_8_BANK));
2221                 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2222                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2223                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2224                                 NUM_BANKS(ADDR_SURF_8_BANK));
2225                 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2226                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2227                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2228                                 NUM_BANKS(ADDR_SURF_8_BANK));
2229                 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2230                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2231                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2232                                 NUM_BANKS(ADDR_SURF_8_BANK));
2233                 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2234                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2235                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2236                                 NUM_BANKS(ADDR_SURF_8_BANK));
2237                 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2238                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2239                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2240                                 NUM_BANKS(ADDR_SURF_8_BANK));
2241                 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2242                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2243                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2244                                 NUM_BANKS(ADDR_SURF_8_BANK));
2245                 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2246                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2247                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2248                                 NUM_BANKS(ADDR_SURF_16_BANK));
2249                 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2250                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2251                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2252                                 NUM_BANKS(ADDR_SURF_16_BANK));
2253                 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2254                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2255                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2256                                  NUM_BANKS(ADDR_SURF_16_BANK));
2257                 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2258                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2259                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2260                                  NUM_BANKS(ADDR_SURF_16_BANK));
2261                 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2262                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2263                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2264                                  NUM_BANKS(ADDR_SURF_16_BANK));
2265                 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2266                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2267                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2268                                  NUM_BANKS(ADDR_SURF_16_BANK));
2269                 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2270                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2271                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2272                                  NUM_BANKS(ADDR_SURF_8_BANK));
2273
2274                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2275                         if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
2276                             reg_offset != 23)
2277                                 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2278
2279                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2280                         if (reg_offset != 7)
2281                                 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2282
2283                 break;
2284         case CHIP_FIJI:
2285         case CHIP_VEGAM:
2286                 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2287                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2288                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2289                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2290                 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2291                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2292                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2293                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2294                 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2295                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2296                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2297                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2298                 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2299                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2300                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2301                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2302                 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2303                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2304                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2305                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2306                 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2307                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2308                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2309                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2310                 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2311                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2312                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2313                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2314                 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2315                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2316                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2317                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2318                 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2319                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
2320                 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2321                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2322                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2323                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2324                 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2325                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2326                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2327                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2328                 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2329                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2330                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2331                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2332                 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2333                                  PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2334                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2335                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2336                 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2337                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2338                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2339                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2340                 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2341                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2342                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2343                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2344                 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2345                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2346                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2347                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2348                 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2349                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2350                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2351                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2352                 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2353                                  PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2354                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2355                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2356                 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2357                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2358                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2359                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2360                 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2361                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2362                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2363                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2364                 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2365                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2366                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2367                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2368                 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2369                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2370                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2371                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2372                 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2373                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2374                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2375                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2376                 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2377                                  PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2378                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2379                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2380                 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2381                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2382                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2383                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2384                 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2385                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2386                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2387                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2388                 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2389                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2390                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2391                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2392                 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2393                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2394                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2395                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2396                 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2397                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2398                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2399                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2400                 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2401                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2402                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2403                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2404                 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2405                                  PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2406                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2407                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2408
2409                 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2410                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2411                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2412                                 NUM_BANKS(ADDR_SURF_8_BANK));
2413                 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2414                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2415                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2416                                 NUM_BANKS(ADDR_SURF_8_BANK));
2417                 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2418                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2419                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2420                                 NUM_BANKS(ADDR_SURF_8_BANK));
2421                 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2422                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2423                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2424                                 NUM_BANKS(ADDR_SURF_8_BANK));
2425                 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2426                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2427                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2428                                 NUM_BANKS(ADDR_SURF_8_BANK));
2429                 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2430                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2431                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2432                                 NUM_BANKS(ADDR_SURF_8_BANK));
2433                 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2434                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2435                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2436                                 NUM_BANKS(ADDR_SURF_8_BANK));
2437                 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2438                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2439                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2440                                 NUM_BANKS(ADDR_SURF_8_BANK));
2441                 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2442                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2443                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2444                                 NUM_BANKS(ADDR_SURF_8_BANK));
2445                 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2446                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2447                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2448                                  NUM_BANKS(ADDR_SURF_8_BANK));
2449                 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2450                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2451                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2452                                  NUM_BANKS(ADDR_SURF_8_BANK));
2453                 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2454                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2455                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2456                                  NUM_BANKS(ADDR_SURF_8_BANK));
2457                 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2458                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2459                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2460                                  NUM_BANKS(ADDR_SURF_8_BANK));
2461                 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2462                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2463                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2464                                  NUM_BANKS(ADDR_SURF_4_BANK));
2465
2466                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2467                         WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2468
2469                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2470                         if (reg_offset != 7)
2471                                 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2472
2473                 break;
2474         case CHIP_TONGA:
2475                 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2476                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2477                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2478                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2479                 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2480                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2481                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2482                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2483                 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2484                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2485                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2486                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2487                 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2488                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2489                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2490                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2491                 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2492                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2493                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2494                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2495                 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2496                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2497                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2498                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2499                 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2500                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2501                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2502                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2503                 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2504                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2505                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2506                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2507                 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2508                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2509                 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2510                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2511                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2512                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2513                 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2514                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2515                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2516                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2517                 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2518                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2519                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2520                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2521                 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2522                                  PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2523                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2524                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2525                 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2526                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2527                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2528                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2529                 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2530                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2531                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2532                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2533                 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2534                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2535                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2536                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2537                 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2538                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2539                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2540                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2541                 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2542                                  PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2543                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2544                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2545                 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2546                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2547                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2548                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2549                 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2550                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2551                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2552                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2553                 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2554                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2555                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2556                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2557                 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2558                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2559                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2560                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2561                 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2562                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2563                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2564                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2565                 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2566                                  PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2567                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2568                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2569                 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2570                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2571                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2572                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2573                 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2574                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2575                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2576                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2577                 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2578                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2579                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2580                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2581                 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2582                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2583                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2584                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2585                 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2586                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2587                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2588                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2589                 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2590                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2591                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2592                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2593                 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2594                                  PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2595                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2596                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2597
2598                 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2599                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2600                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2601                                 NUM_BANKS(ADDR_SURF_16_BANK));
2602                 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2603                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2604                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2605                                 NUM_BANKS(ADDR_SURF_16_BANK));
2606                 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2607                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2608                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2609                                 NUM_BANKS(ADDR_SURF_16_BANK));
2610                 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2611                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2612                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2613                                 NUM_BANKS(ADDR_SURF_16_BANK));
2614                 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2615                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2616                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2617                                 NUM_BANKS(ADDR_SURF_16_BANK));
2618                 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2619                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2620                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2621                                 NUM_BANKS(ADDR_SURF_16_BANK));
2622                 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2623                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2624                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2625                                 NUM_BANKS(ADDR_SURF_16_BANK));
2626                 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2627                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2628                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2629                                 NUM_BANKS(ADDR_SURF_16_BANK));
2630                 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2631                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2632                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2633                                 NUM_BANKS(ADDR_SURF_16_BANK));
2634                 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2635                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2636                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2637                                  NUM_BANKS(ADDR_SURF_16_BANK));
2638                 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2639                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2640                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2641                                  NUM_BANKS(ADDR_SURF_16_BANK));
2642                 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2643                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2644                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2645                                  NUM_BANKS(ADDR_SURF_8_BANK));
2646                 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2647                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2648                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2649                                  NUM_BANKS(ADDR_SURF_4_BANK));
2650                 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2651                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2652                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2653                                  NUM_BANKS(ADDR_SURF_4_BANK));
2654
2655                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2656                         WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2657
2658                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2659                         if (reg_offset != 7)
2660                                 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2661
2662                 break;
2663         case CHIP_POLARIS11:
2664         case CHIP_POLARIS12:
2665                 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2666                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2667                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2668                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2669                 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2670                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2671                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2672                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2673                 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2674                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2675                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2676                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2677                 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2678                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2679                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2680                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2681                 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2682                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2683                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2684                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2685                 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2686                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2687                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2688                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2689                 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2690                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2691                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2692                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2693                 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2694                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2695                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2696                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2697                 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2698                                 PIPE_CONFIG(ADDR_SURF_P4_16x16));
2699                 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2700                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2701                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2702                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2703                 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2704                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2705                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2706                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2707                 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2708                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2709                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2710                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2711                 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2712                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2713                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2714                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2715                 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2716                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2717                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2718                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2719                 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2720                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2721                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2722                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2723                 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2724                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2725                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2726                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2727                 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2728                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2729                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2730                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2731                 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2732                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2733                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2734                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2735                 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2736                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2737                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2738                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2739                 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2740                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2741                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2742                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2743                 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2744                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2745                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2746                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2747                 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2748                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2749                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2750                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2751                 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2752                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2753                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2754                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2755                 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2756                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2757                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2758                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2759                 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2760                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2761                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2762                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2763                 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2764                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2765                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2766                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2767                 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2768                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2769                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2770                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2771                 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2772                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2773                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2774                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2775                 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2776                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2777                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2778                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2779                 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2780                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2781                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2782                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2783                 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2784                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2785                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2786                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2787
2788                 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2789                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2790                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2791                                 NUM_BANKS(ADDR_SURF_16_BANK));
2792
2793                 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2794                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2795                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2796                                 NUM_BANKS(ADDR_SURF_16_BANK));
2797
2798                 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2799                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2800                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2801                                 NUM_BANKS(ADDR_SURF_16_BANK));
2802
2803                 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2804                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2805                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2806                                 NUM_BANKS(ADDR_SURF_16_BANK));
2807
2808                 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2809                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2810                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2811                                 NUM_BANKS(ADDR_SURF_16_BANK));
2812
2813                 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2814                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2815                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2816                                 NUM_BANKS(ADDR_SURF_16_BANK));
2817
2818                 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2819                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2820                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2821                                 NUM_BANKS(ADDR_SURF_16_BANK));
2822
2823                 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2824                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2825                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2826                                 NUM_BANKS(ADDR_SURF_16_BANK));
2827
2828                 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2829                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2830                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2831                                 NUM_BANKS(ADDR_SURF_16_BANK));
2832
2833                 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2834                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2835                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2836                                 NUM_BANKS(ADDR_SURF_16_BANK));
2837
2838                 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2839                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2840                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2841                                 NUM_BANKS(ADDR_SURF_16_BANK));
2842
2843                 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2844                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2845                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2846                                 NUM_BANKS(ADDR_SURF_16_BANK));
2847
2848                 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2849                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2850                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2851                                 NUM_BANKS(ADDR_SURF_8_BANK));
2852
2853                 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2854                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2855                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2856                                 NUM_BANKS(ADDR_SURF_4_BANK));
2857
2858                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2859                         WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2860
2861                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2862                         if (reg_offset != 7)
2863                                 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2864
2865                 break;
2866         case CHIP_POLARIS10:
2867                 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2868                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2869                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2870                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2871                 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2872                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2873                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2874                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2875                 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2876                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2877                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2878                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2879                 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2880                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2881                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2882                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2883                 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2884                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2885                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2886                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2887                 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2888                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2889                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2890                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2891                 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2892                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2893                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2894                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2895                 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2896                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2897                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2898                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2899                 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2900                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2901                 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2902                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2903                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2904                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2905                 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2906                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2907                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2908                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2909                 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2910                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2911                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2912                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2913                 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2914                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2915                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2916                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2917                 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2918                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2919                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2920                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2921                 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2922                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2923                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2924                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2925                 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2926                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2927                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2928                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2929                 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2930                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2931                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2932                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2933                 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2934                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2935                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2936                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2937                 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2938                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2939                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2940                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2941                 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2942                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2943                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2944                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2945                 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2946                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2947                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2948                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2949                 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2950                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2951                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2952                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2953                 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2954                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2955                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2956                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2957                 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2958                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2959                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2960                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2961                 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2962                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2963                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2964                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2965                 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2966                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2967                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2968                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2969                 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2970                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2971                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2972                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2973                 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2974                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2975                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2976                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2977                 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2978                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2979                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2980                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2981                 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2982                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2983                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2984                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2985                 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2986                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2987                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2988                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2989
2990                 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2991                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2992                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2993                                 NUM_BANKS(ADDR_SURF_16_BANK));
2994
2995                 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2996                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2997                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2998                                 NUM_BANKS(ADDR_SURF_16_BANK));
2999
3000                 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3001                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3002                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3003                                 NUM_BANKS(ADDR_SURF_16_BANK));
3004
3005                 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3006                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3007                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3008                                 NUM_BANKS(ADDR_SURF_16_BANK));
3009
3010                 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3011                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3012                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3013                                 NUM_BANKS(ADDR_SURF_16_BANK));
3014
3015                 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3016                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3017                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3018                                 NUM_BANKS(ADDR_SURF_16_BANK));
3019
3020                 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3021                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3022                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3023                                 NUM_BANKS(ADDR_SURF_16_BANK));
3024
3025                 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3026                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3027                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3028                                 NUM_BANKS(ADDR_SURF_16_BANK));
3029
3030                 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3031                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3032                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3033                                 NUM_BANKS(ADDR_SURF_16_BANK));
3034
3035                 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3036                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3037                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3038                                 NUM_BANKS(ADDR_SURF_16_BANK));
3039
3040                 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3041                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3042                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3043                                 NUM_BANKS(ADDR_SURF_16_BANK));
3044
3045                 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3046                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3047                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3048                                 NUM_BANKS(ADDR_SURF_8_BANK));
3049
3050                 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3051                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3052                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3053                                 NUM_BANKS(ADDR_SURF_4_BANK));
3054
3055                 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3056                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3057                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3058                                 NUM_BANKS(ADDR_SURF_4_BANK));
3059
3060                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3061                         WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3062
3063                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3064                         if (reg_offset != 7)
3065                                 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3066
3067                 break;
3068         case CHIP_STONEY:
3069                 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3070                                 PIPE_CONFIG(ADDR_SURF_P2) |
3071                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
3072                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3073                 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3074                                 PIPE_CONFIG(ADDR_SURF_P2) |
3075                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
3076                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3077                 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3078                                 PIPE_CONFIG(ADDR_SURF_P2) |
3079                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
3080                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3081                 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3082                                 PIPE_CONFIG(ADDR_SURF_P2) |
3083                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
3084                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3085                 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3086                                 PIPE_CONFIG(ADDR_SURF_P2) |
3087                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3088                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3089                 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3090                                 PIPE_CONFIG(ADDR_SURF_P2) |
3091                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3092                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3093                 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3094                                 PIPE_CONFIG(ADDR_SURF_P2) |
3095                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3096                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3097                 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
3098                                 PIPE_CONFIG(ADDR_SURF_P2));
3099                 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3100                                 PIPE_CONFIG(ADDR_SURF_P2) |
3101                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3102                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3103                 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3104                                  PIPE_CONFIG(ADDR_SURF_P2) |
3105                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3106                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3107                 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3108                                  PIPE_CONFIG(ADDR_SURF_P2) |
3109                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3110                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3111                 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3112                                  PIPE_CONFIG(ADDR_SURF_P2) |
3113                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3114                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3115                 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3116                                  PIPE_CONFIG(ADDR_SURF_P2) |
3117                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3118                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3119                 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
3120                                  PIPE_CONFIG(ADDR_SURF_P2) |
3121                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3122                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3123                 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3124                                  PIPE_CONFIG(ADDR_SURF_P2) |
3125                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3126                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3127                 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3128                                  PIPE_CONFIG(ADDR_SURF_P2) |
3129                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3130                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3131                 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3132                                  PIPE_CONFIG(ADDR_SURF_P2) |
3133                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3134                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3135                 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3136                                  PIPE_CONFIG(ADDR_SURF_P2) |
3137                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3138                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3139                 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
3140                                  PIPE_CONFIG(ADDR_SURF_P2) |
3141                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3142                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3143                 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
3144                                  PIPE_CONFIG(ADDR_SURF_P2) |
3145                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3146                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3147                 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3148                                  PIPE_CONFIG(ADDR_SURF_P2) |
3149                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3150                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3151                 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
3152                                  PIPE_CONFIG(ADDR_SURF_P2) |
3153                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3154                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3155                 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
3156                                  PIPE_CONFIG(ADDR_SURF_P2) |
3157                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3158                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3159                 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3160                                  PIPE_CONFIG(ADDR_SURF_P2) |
3161                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3162                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3163                 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3164                                  PIPE_CONFIG(ADDR_SURF_P2) |
3165                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3166                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3167                 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3168                                  PIPE_CONFIG(ADDR_SURF_P2) |
3169                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3170                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3171
3172                 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3173                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3174                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3175                                 NUM_BANKS(ADDR_SURF_8_BANK));
3176                 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3177                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3178                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3179                                 NUM_BANKS(ADDR_SURF_8_BANK));
3180                 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3181                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3182                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3183                                 NUM_BANKS(ADDR_SURF_8_BANK));
3184                 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3185                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3186                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3187                                 NUM_BANKS(ADDR_SURF_8_BANK));
3188                 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3189                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3190                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3191                                 NUM_BANKS(ADDR_SURF_8_BANK));
3192                 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3193                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3194                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3195                                 NUM_BANKS(ADDR_SURF_8_BANK));
3196                 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3197                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3198                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3199                                 NUM_BANKS(ADDR_SURF_8_BANK));
3200                 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3201                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3202                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3203                                 NUM_BANKS(ADDR_SURF_16_BANK));
3204                 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3205                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3206                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3207                                 NUM_BANKS(ADDR_SURF_16_BANK));
3208                 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3209                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3210                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3211                                  NUM_BANKS(ADDR_SURF_16_BANK));
3212                 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3213                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3214                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3215                                  NUM_BANKS(ADDR_SURF_16_BANK));
3216                 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3217                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3218                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3219                                  NUM_BANKS(ADDR_SURF_16_BANK));
3220                 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3221                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3222                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3223                                  NUM_BANKS(ADDR_SURF_16_BANK));
3224                 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3225                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3226                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3227                                  NUM_BANKS(ADDR_SURF_8_BANK));
3228
3229                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3230                         if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
3231                             reg_offset != 23)
3232                                 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3233
3234                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3235                         if (reg_offset != 7)
3236                                 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3237
3238                 break;
3239         default:
3240                 dev_warn(adev->dev,
3241                          "Unknown chip type (%d) in function gfx_v8_0_tiling_mode_table_init() falling through to CHIP_CARRIZO\n",
3242                          adev->asic_type);
3243                 /* fall through */
3244
3245         case CHIP_CARRIZO:
3246                 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3247                                 PIPE_CONFIG(ADDR_SURF_P2) |
3248                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
3249                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3250                 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3251                                 PIPE_CONFIG(ADDR_SURF_P2) |
3252                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
3253                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3254                 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3255                                 PIPE_CONFIG(ADDR_SURF_P2) |
3256                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
3257                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3258                 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3259                                 PIPE_CONFIG(ADDR_SURF_P2) |
3260                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
3261                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3262                 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3263                                 PIPE_CONFIG(ADDR_SURF_P2) |
3264                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3265                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3266                 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3267                                 PIPE_CONFIG(ADDR_SURF_P2) |
3268                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3269                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3270                 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3271                                 PIPE_CONFIG(ADDR_SURF_P2) |
3272                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3273                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3274                 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
3275                                 PIPE_CONFIG(ADDR_SURF_P2));
3276                 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3277                                 PIPE_CONFIG(ADDR_SURF_P2) |
3278                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3279                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3280                 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3281                                  PIPE_CONFIG(ADDR_SURF_P2) |
3282                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3283                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3284                 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3285                                  PIPE_CONFIG(ADDR_SURF_P2) |
3286                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3287                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3288                 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3289                                  PIPE_CONFIG(ADDR_SURF_P2) |
3290                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3291                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3292                 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3293                                  PIPE_CONFIG(ADDR_SURF_P2) |
3294                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3295                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3296                 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
3297                                  PIPE_CONFIG(ADDR_SURF_P2) |
3298                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3299                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3300                 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3301                                  PIPE_CONFIG(ADDR_SURF_P2) |
3302                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3303                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3304                 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3305                                  PIPE_CONFIG(ADDR_SURF_P2) |
3306                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3307                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3308                 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3309                                  PIPE_CONFIG(ADDR_SURF_P2) |
3310                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3311                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3312                 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3313                                  PIPE_CONFIG(ADDR_SURF_P2) |
3314                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3315                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3316                 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
3317                                  PIPE_CONFIG(ADDR_SURF_P2) |
3318                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3319                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3320                 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
3321                                  PIPE_CONFIG(ADDR_SURF_P2) |
3322                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3323                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3324                 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3325                                  PIPE_CONFIG(ADDR_SURF_P2) |
3326                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3327                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3328                 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
3329                                  PIPE_CONFIG(ADDR_SURF_P2) |
3330                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3331                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3332                 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
3333                                  PIPE_CONFIG(ADDR_SURF_P2) |
3334                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3335                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3336                 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3337                                  PIPE_CONFIG(ADDR_SURF_P2) |
3338                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3339                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3340                 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3341                                  PIPE_CONFIG(ADDR_SURF_P2) |
3342                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3343                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3344                 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3345                                  PIPE_CONFIG(ADDR_SURF_P2) |
3346                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3347                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3348
3349                 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3350                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3351                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3352                                 NUM_BANKS(ADDR_SURF_8_BANK));
3353                 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3354                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3355                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3356                                 NUM_BANKS(ADDR_SURF_8_BANK));
3357                 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3358                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3359                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3360                                 NUM_BANKS(ADDR_SURF_8_BANK));
3361                 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3362                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3363                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3364                                 NUM_BANKS(ADDR_SURF_8_BANK));
3365                 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3366                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3367                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3368                                 NUM_BANKS(ADDR_SURF_8_BANK));
3369                 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3370                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3371                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3372                                 NUM_BANKS(ADDR_SURF_8_BANK));
3373                 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3374                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3375                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3376                                 NUM_BANKS(ADDR_SURF_8_BANK));
3377                 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3378                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3379                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3380                                 NUM_BANKS(ADDR_SURF_16_BANK));
3381                 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3382                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3383                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3384                                 NUM_BANKS(ADDR_SURF_16_BANK));
3385                 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3386                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3387                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3388                                  NUM_BANKS(ADDR_SURF_16_BANK));
3389                 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3390                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3391                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3392                                  NUM_BANKS(ADDR_SURF_16_BANK));
3393                 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3394                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3395                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3396                                  NUM_BANKS(ADDR_SURF_16_BANK));
3397                 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3398                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3399                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3400                                  NUM_BANKS(ADDR_SURF_16_BANK));
3401                 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3402                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3403                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3404                                  NUM_BANKS(ADDR_SURF_8_BANK));
3405
3406                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3407                         if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
3408                             reg_offset != 23)
3409                                 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3410
3411                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3412                         if (reg_offset != 7)
3413                                 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3414
3415                 break;
3416         }
3417 }
3418
3419 static void gfx_v8_0_select_se_sh(struct amdgpu_device *adev,
3420                                   u32 se_num, u32 sh_num, u32 instance)
3421 {
3422         u32 data;
3423
3424         if (instance == 0xffffffff)
3425                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
3426         else
3427                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
3428
3429         if (se_num == 0xffffffff)
3430                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
3431         else
3432                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
3433
3434         if (sh_num == 0xffffffff)
3435                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
3436         else
3437                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
3438
3439         WREG32(mmGRBM_GFX_INDEX, data);
3440 }
3441
3442 static void gfx_v8_0_select_me_pipe_q(struct amdgpu_device *adev,
3443                                   u32 me, u32 pipe, u32 q)
3444 {
3445         vi_srbm_select(adev, me, pipe, q, 0);
3446 }
3447
3448 static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev)
3449 {
3450         u32 data, mask;
3451
3452         data =  RREG32(mmCC_RB_BACKEND_DISABLE) |
3453                 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
3454
3455         data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE);
3456
3457         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
3458                                          adev->gfx.config.max_sh_per_se);
3459
3460         return (~data) & mask;
3461 }
3462
3463 static void
3464 gfx_v8_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1)
3465 {
3466         switch (adev->asic_type) {
3467         case CHIP_FIJI:
3468         case CHIP_VEGAM:
3469                 *rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) |
3470                           RB_XSEL2(1) | PKR_MAP(2) |
3471                           PKR_XSEL(1) | PKR_YSEL(1) |
3472                           SE_MAP(2) | SE_XSEL(2) | SE_YSEL(3);
3473                 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) |
3474                            SE_PAIR_YSEL(2);
3475                 break;
3476         case CHIP_TONGA:
3477         case CHIP_POLARIS10:
3478                 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
3479                           SE_XSEL(1) | SE_YSEL(1);
3480                 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(2) |
3481                            SE_PAIR_YSEL(2);
3482                 break;
3483         case CHIP_TOPAZ:
3484         case CHIP_CARRIZO:
3485                 *rconf |= RB_MAP_PKR0(2);
3486                 *rconf1 |= 0x0;
3487                 break;
3488         case CHIP_POLARIS11:
3489         case CHIP_POLARIS12:
3490                 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
3491                           SE_XSEL(1) | SE_YSEL(1);
3492                 *rconf1 |= 0x0;
3493                 break;
3494         case CHIP_STONEY:
3495                 *rconf |= 0x0;
3496                 *rconf1 |= 0x0;
3497                 break;
3498         default:
3499                 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
3500                 break;
3501         }
3502 }
3503
3504 static void
3505 gfx_v8_0_write_harvested_raster_configs(struct amdgpu_device *adev,
3506                                         u32 raster_config, u32 raster_config_1,
3507                                         unsigned rb_mask, unsigned num_rb)
3508 {
3509         unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
3510         unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
3511         unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
3512         unsigned rb_per_se = num_rb / num_se;
3513         unsigned se_mask[4];
3514         unsigned se;
3515
3516         se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
3517         se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
3518         se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
3519         se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
3520
3521         WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
3522         WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
3523         WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
3524
3525         if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3526                              (!se_mask[2] && !se_mask[3]))) {
3527                 raster_config_1 &= ~SE_PAIR_MAP_MASK;
3528
3529                 if (!se_mask[0] && !se_mask[1]) {
3530                         raster_config_1 |=
3531                                 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3);
3532                 } else {
3533                         raster_config_1 |=
3534                                 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0);
3535                 }
3536         }
3537
3538         for (se = 0; se < num_se; se++) {
3539                 unsigned raster_config_se = raster_config;
3540                 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3541                 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3542                 int idx = (se / 2) * 2;
3543
3544                 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3545                         raster_config_se &= ~SE_MAP_MASK;
3546
3547                         if (!se_mask[idx]) {
3548                                 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3);
3549                         } else {
3550                                 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0);
3551                         }
3552                 }
3553
3554                 pkr0_mask &= rb_mask;
3555                 pkr1_mask &= rb_mask;
3556                 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3557                         raster_config_se &= ~PKR_MAP_MASK;
3558
3559                         if (!pkr0_mask) {
3560                                 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3);
3561                         } else {
3562                                 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0);
3563                         }
3564                 }
3565
3566                 if (rb_per_se >= 2) {
3567                         unsigned rb0_mask = 1 << (se * rb_per_se);
3568                         unsigned rb1_mask = rb0_mask << 1;
3569
3570                         rb0_mask &= rb_mask;
3571                         rb1_mask &= rb_mask;
3572                         if (!rb0_mask || !rb1_mask) {
3573                                 raster_config_se &= ~RB_MAP_PKR0_MASK;
3574
3575                                 if (!rb0_mask) {
3576                                         raster_config_se |=
3577                                                 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3);
3578                                 } else {
3579                                         raster_config_se |=
3580                                                 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0);
3581                                 }
3582                         }
3583
3584                         if (rb_per_se > 2) {
3585                                 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3586                                 rb1_mask = rb0_mask << 1;
3587                                 rb0_mask &= rb_mask;
3588                                 rb1_mask &= rb_mask;
3589                                 if (!rb0_mask || !rb1_mask) {
3590                                         raster_config_se &= ~RB_MAP_PKR1_MASK;
3591
3592                                         if (!rb0_mask) {
3593                                                 raster_config_se |=
3594                                                         RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3);
3595                                         } else {
3596                                                 raster_config_se |=
3597                                                         RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0);
3598                                         }
3599                                 }
3600                         }
3601                 }
3602
3603                 /* GRBM_GFX_INDEX has a different offset on VI */
3604                 gfx_v8_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
3605                 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
3606                 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
3607         }
3608
3609         /* GRBM_GFX_INDEX has a different offset on VI */
3610         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3611 }
3612
3613 static void gfx_v8_0_setup_rb(struct amdgpu_device *adev)
3614 {
3615         int i, j;
3616         u32 data;
3617         u32 raster_config = 0, raster_config_1 = 0;
3618         u32 active_rbs = 0;
3619         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
3620                                         adev->gfx.config.max_sh_per_se;
3621         unsigned num_rb_pipes;
3622
3623         mutex_lock(&adev->grbm_idx_mutex);
3624         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3625                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3626                         gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff);
3627                         data = gfx_v8_0_get_rb_active_bitmap(adev);
3628                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
3629                                                rb_bitmap_width_per_sh);
3630                 }
3631         }
3632         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3633
3634         adev->gfx.config.backend_enable_mask = active_rbs;
3635         adev->gfx.config.num_rbs = hweight32(active_rbs);
3636
3637         num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
3638                              adev->gfx.config.max_shader_engines, 16);
3639
3640         gfx_v8_0_raster_config(adev, &raster_config, &raster_config_1);
3641
3642         if (!adev->gfx.config.backend_enable_mask ||
3643                         adev->gfx.config.num_rbs >= num_rb_pipes) {
3644                 WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
3645                 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
3646         } else {
3647                 gfx_v8_0_write_harvested_raster_configs(adev, raster_config, raster_config_1,
3648                                                         adev->gfx.config.backend_enable_mask,
3649                                                         num_rb_pipes);
3650         }
3651
3652         /* cache the values for userspace */
3653         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3654                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3655                         gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff);
3656                         adev->gfx.config.rb_config[i][j].rb_backend_disable =
3657                                 RREG32(mmCC_RB_BACKEND_DISABLE);
3658                         adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
3659                                 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
3660                         adev->gfx.config.rb_config[i][j].raster_config =
3661                                 RREG32(mmPA_SC_RASTER_CONFIG);
3662                         adev->gfx.config.rb_config[i][j].raster_config_1 =
3663                                 RREG32(mmPA_SC_RASTER_CONFIG_1);
3664                 }
3665         }
3666         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3667         mutex_unlock(&adev->grbm_idx_mutex);
3668 }
3669
3670 /**
3671  * gfx_v8_0_init_compute_vmid - gart enable
3672  *
3673  * @adev: amdgpu_device pointer
3674  *
3675  * Initialize compute vmid sh_mem registers
3676  *
3677  */
3678 #define DEFAULT_SH_MEM_BASES    (0x6000)
3679 #define FIRST_COMPUTE_VMID      (8)
3680 #define LAST_COMPUTE_VMID       (16)
3681 static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
3682 {
3683         int i;
3684         uint32_t sh_mem_config;
3685         uint32_t sh_mem_bases;
3686
3687         /*
3688          * Configure apertures:
3689          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
3690          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
3691          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
3692          */
3693         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
3694
3695         sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 <<
3696                         SH_MEM_CONFIG__ADDRESS_MODE__SHIFT |
3697                         SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
3698                         SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
3699                         MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
3700                         SH_MEM_CONFIG__PRIVATE_ATC_MASK;
3701
3702         mutex_lock(&adev->srbm_mutex);
3703         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
3704                 vi_srbm_select(adev, 0, 0, 0, i);
3705                 /* CP and shaders */
3706                 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
3707                 WREG32(mmSH_MEM_APE1_BASE, 1);
3708                 WREG32(mmSH_MEM_APE1_LIMIT, 0);
3709                 WREG32(mmSH_MEM_BASES, sh_mem_bases);
3710         }
3711         vi_srbm_select(adev, 0, 0, 0, 0);
3712         mutex_unlock(&adev->srbm_mutex);
3713 }
3714
3715 static void gfx_v8_0_config_init(struct amdgpu_device *adev)
3716 {
3717         switch (adev->asic_type) {
3718         default:
3719                 adev->gfx.config.double_offchip_lds_buf = 1;
3720                 break;
3721         case CHIP_CARRIZO:
3722         case CHIP_STONEY:
3723                 adev->gfx.config.double_offchip_lds_buf = 0;
3724                 break;
3725         }
3726 }
3727
3728 static void gfx_v8_0_constants_init(struct amdgpu_device *adev)
3729 {
3730         u32 tmp, sh_static_mem_cfg;
3731         int i;
3732
3733         WREG32_FIELD(GRBM_CNTL, READ_TIMEOUT, 0xFF);
3734         WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
3735         WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
3736         WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
3737
3738         gfx_v8_0_tiling_mode_table_init(adev);
3739         gfx_v8_0_setup_rb(adev);
3740         gfx_v8_0_get_cu_info(adev);
3741         gfx_v8_0_config_init(adev);
3742
3743         /* XXX SH_MEM regs */
3744         /* where to put LDS, scratch, GPUVM in FSA64 space */
3745         sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG,
3746                                    SWIZZLE_ENABLE, 1);
3747         sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
3748                                    ELEMENT_SIZE, 1);
3749         sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
3750                                    INDEX_STRIDE, 3);
3751         WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg);
3752
3753         mutex_lock(&adev->srbm_mutex);
3754         for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) {
3755                 vi_srbm_select(adev, 0, 0, 0, i);
3756                 /* CP and shaders */
3757                 if (i == 0) {
3758                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
3759                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
3760                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
3761                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
3762                         WREG32(mmSH_MEM_CONFIG, tmp);
3763                         WREG32(mmSH_MEM_BASES, 0);
3764                 } else {
3765                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
3766                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
3767                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
3768                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
3769                         WREG32(mmSH_MEM_CONFIG, tmp);
3770                         tmp = adev->gmc.shared_aperture_start >> 48;
3771                         WREG32(mmSH_MEM_BASES, tmp);
3772                 }
3773
3774                 WREG32(mmSH_MEM_APE1_BASE, 1);
3775                 WREG32(mmSH_MEM_APE1_LIMIT, 0);
3776         }
3777         vi_srbm_select(adev, 0, 0, 0, 0);
3778         mutex_unlock(&adev->srbm_mutex);
3779
3780         gfx_v8_0_init_compute_vmid(adev);
3781
3782         mutex_lock(&adev->grbm_idx_mutex);
3783         /*
3784          * making sure that the following register writes will be broadcasted
3785          * to all the shaders
3786          */
3787         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3788
3789         WREG32(mmPA_SC_FIFO_SIZE,
3790                    (adev->gfx.config.sc_prim_fifo_size_frontend <<
3791                         PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
3792                    (adev->gfx.config.sc_prim_fifo_size_backend <<
3793                         PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
3794                    (adev->gfx.config.sc_hiz_tile_fifo_size <<
3795                         PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
3796                    (adev->gfx.config.sc_earlyz_tile_fifo_size <<
3797                         PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
3798
3799         tmp = RREG32(mmSPI_ARB_PRIORITY);
3800         tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2);
3801         tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2);
3802         tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2);
3803         tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2);
3804         WREG32(mmSPI_ARB_PRIORITY, tmp);
3805
3806         mutex_unlock(&adev->grbm_idx_mutex);
3807
3808 }
3809
3810 static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3811 {
3812         u32 i, j, k;
3813         u32 mask;
3814
3815         mutex_lock(&adev->grbm_idx_mutex);
3816         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3817                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3818                         gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff);
3819                         for (k = 0; k < adev->usec_timeout; k++) {
3820                                 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3821                                         break;
3822                                 udelay(1);
3823                         }
3824                         if (k == adev->usec_timeout) {
3825                                 gfx_v8_0_select_se_sh(adev, 0xffffffff,
3826                                                       0xffffffff, 0xffffffff);
3827                                 mutex_unlock(&adev->grbm_idx_mutex);
3828                                 DRM_INFO("Timeout wait for RLC serdes %u,%u\n",
3829                                          i, j);
3830                                 return;
3831                         }
3832                 }
3833         }
3834         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3835         mutex_unlock(&adev->grbm_idx_mutex);
3836
3837         mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3838                 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3839                 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3840                 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3841         for (k = 0; k < adev->usec_timeout; k++) {
3842                 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3843                         break;
3844                 udelay(1);
3845         }
3846 }
3847
3848 static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
3849                                                bool enable)
3850 {
3851         u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
3852
3853         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
3854         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
3855         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
3856         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
3857
3858         WREG32(mmCP_INT_CNTL_RING0, tmp);
3859 }
3860
3861 static void gfx_v8_0_init_csb(struct amdgpu_device *adev)
3862 {
3863         /* csib */
3864         WREG32(mmRLC_CSIB_ADDR_HI,
3865                         adev->gfx.rlc.clear_state_gpu_addr >> 32);
3866         WREG32(mmRLC_CSIB_ADDR_LO,
3867                         adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
3868         WREG32(mmRLC_CSIB_LENGTH,
3869                         adev->gfx.rlc.clear_state_size);
3870 }
3871
3872 static void gfx_v8_0_parse_ind_reg_list(int *register_list_format,
3873                                 int ind_offset,
3874                                 int list_size,
3875                                 int *unique_indices,
3876                                 int *indices_count,
3877                                 int max_indices,
3878                                 int *ind_start_offsets,
3879                                 int *offset_count,
3880                                 int max_offset)
3881 {
3882         int indices;
3883         bool new_entry = true;
3884
3885         for (; ind_offset < list_size; ind_offset++) {
3886
3887                 if (new_entry) {
3888                         new_entry = false;
3889                         ind_start_offsets[*offset_count] = ind_offset;
3890                         *offset_count = *offset_count + 1;
3891                         BUG_ON(*offset_count >= max_offset);
3892                 }
3893
3894                 if (register_list_format[ind_offset] == 0xFFFFFFFF) {
3895                         new_entry = true;
3896                         continue;
3897                 }
3898
3899                 ind_offset += 2;
3900
3901                 /* look for the matching indice */
3902                 for (indices = 0;
3903                         indices < *indices_count;
3904                         indices++) {
3905                         if (unique_indices[indices] ==
3906                                 register_list_format[ind_offset])
3907                                 break;
3908                 }
3909
3910                 if (indices >= *indices_count) {
3911                         unique_indices[*indices_count] =
3912                                 register_list_format[ind_offset];
3913                         indices = *indices_count;
3914                         *indices_count = *indices_count + 1;
3915                         BUG_ON(*indices_count >= max_indices);
3916                 }
3917
3918                 register_list_format[ind_offset] = indices;
3919         }
3920 }
3921
3922 static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev)
3923 {
3924         int i, temp, data;
3925         int unique_indices[] = {0, 0, 0, 0, 0, 0, 0, 0};
3926         int indices_count = 0;
3927         int indirect_start_offsets[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
3928         int offset_count = 0;
3929
3930         int list_size;
3931         unsigned int *register_list_format =
3932                 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
3933         if (!register_list_format)
3934                 return -ENOMEM;
3935         memcpy(register_list_format, adev->gfx.rlc.register_list_format,
3936                         adev->gfx.rlc.reg_list_format_size_bytes);
3937
3938         gfx_v8_0_parse_ind_reg_list(register_list_format,
3939                                 RLC_FormatDirectRegListLength,
3940                                 adev->gfx.rlc.reg_list_format_size_bytes >> 2,
3941                                 unique_indices,
3942                                 &indices_count,
3943                                 ARRAY_SIZE(unique_indices),
3944                                 indirect_start_offsets,
3945                                 &offset_count,
3946                                 ARRAY_SIZE(indirect_start_offsets));
3947
3948         /* save and restore list */
3949         WREG32_FIELD(RLC_SRM_CNTL, AUTO_INCR_ADDR, 1);
3950
3951         WREG32(mmRLC_SRM_ARAM_ADDR, 0);
3952         for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
3953                 WREG32(mmRLC_SRM_ARAM_DATA, adev->gfx.rlc.register_restore[i]);
3954
3955         /* indirect list */
3956         WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_list_format_start);
3957         for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++)
3958                 WREG32(mmRLC_GPM_SCRATCH_DATA, register_list_format[i]);
3959
3960         list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
3961         list_size = list_size >> 1;
3962         WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_restore_list_size);
3963         WREG32(mmRLC_GPM_SCRATCH_DATA, list_size);
3964
3965         /* starting offsets starts */
3966         WREG32(mmRLC_GPM_SCRATCH_ADDR,
3967                 adev->gfx.rlc.starting_offsets_start);
3968         for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)
3969                 WREG32(mmRLC_GPM_SCRATCH_DATA,
3970                                 indirect_start_offsets[i]);
3971
3972         /* unique indices */
3973         temp = mmRLC_SRM_INDEX_CNTL_ADDR_0;
3974         data = mmRLC_SRM_INDEX_CNTL_DATA_0;
3975         for (i = 0; i < ARRAY_SIZE(unique_indices); i++) {
3976                 if (unique_indices[i] != 0) {
3977                         WREG32(temp + i, unique_indices[i] & 0x3FFFF);
3978                         WREG32(data + i, unique_indices[i] >> 20);
3979                 }
3980         }
3981         kfree(register_list_format);
3982
3983         return 0;
3984 }
3985
3986 static void gfx_v8_0_enable_save_restore_machine(struct amdgpu_device *adev)
3987 {
3988         WREG32_FIELD(RLC_SRM_CNTL, SRM_ENABLE, 1);
3989 }
3990
3991 static void gfx_v8_0_init_power_gating(struct amdgpu_device *adev)
3992 {
3993         uint32_t data;
3994
3995         WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60);
3996
3997         data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10);
3998         data = REG_SET_FIELD(data, RLC_PG_DELAY, POWER_DOWN_DELAY, 0x10);
3999         data = REG_SET_FIELD(data, RLC_PG_DELAY, CMD_PROPAGATE_DELAY, 0x10);
4000         data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY, 0x10);
4001         WREG32(mmRLC_PG_DELAY, data);
4002
4003         WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3);
4004         WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0);
4005
4006 }
4007
4008 static void cz_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
4009                                                 bool enable)
4010 {
4011         WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PU_ENABLE, enable ? 1 : 0);
4012 }
4013
4014 static void cz_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
4015                                                   bool enable)
4016 {
4017         WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PD_ENABLE, enable ? 1 : 0);
4018 }
4019
4020 static void cz_enable_cp_power_gating(struct amdgpu_device *adev, bool enable)
4021 {
4022         WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1);
4023 }
4024
4025 static void gfx_v8_0_init_pg(struct amdgpu_device *adev)
4026 {
4027         if ((adev->asic_type == CHIP_CARRIZO) ||
4028             (adev->asic_type == CHIP_STONEY)) {
4029                 gfx_v8_0_init_csb(adev);
4030                 gfx_v8_0_init_save_restore_list(adev);
4031                 gfx_v8_0_enable_save_restore_machine(adev);
4032                 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
4033                 gfx_v8_0_init_power_gating(adev);
4034                 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
4035         } else if ((adev->asic_type == CHIP_POLARIS11) ||
4036                    (adev->asic_type == CHIP_POLARIS12) ||
4037                    (adev->asic_type == CHIP_VEGAM)) {
4038                 gfx_v8_0_init_csb(adev);
4039                 gfx_v8_0_init_save_restore_list(adev);
4040                 gfx_v8_0_enable_save_restore_machine(adev);
4041                 gfx_v8_0_init_power_gating(adev);
4042         }
4043
4044 }
4045
4046 static void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
4047 {
4048         WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 0);
4049
4050         gfx_v8_0_enable_gui_idle_interrupt(adev, false);
4051         gfx_v8_0_wait_for_rlc_serdes(adev);
4052 }
4053
4054 static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev)
4055 {
4056         WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4057         udelay(50);
4058
4059         WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
4060         udelay(50);
4061 }
4062
4063 static void gfx_v8_0_rlc_start(struct amdgpu_device *adev)
4064 {
4065         WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 1);
4066
4067         /* carrizo do enable cp interrupt after cp inited */
4068         if (!(adev->flags & AMD_IS_APU))
4069                 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
4070
4071         udelay(50);
4072 }
4073
4074 static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
4075 {
4076         if (amdgpu_sriov_vf(adev)) {
4077                 gfx_v8_0_init_csb(adev);
4078                 return 0;
4079         }
4080
4081         adev->gfx.rlc.funcs->stop(adev);
4082         adev->gfx.rlc.funcs->reset(adev);
4083         gfx_v8_0_init_pg(adev);
4084         adev->gfx.rlc.funcs->start(adev);
4085
4086         return 0;
4087 }
4088
4089 static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
4090 {
4091         int i;
4092         u32 tmp = RREG32(mmCP_ME_CNTL);
4093
4094         if (enable) {
4095                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
4096                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
4097                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
4098         } else {
4099                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
4100                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
4101                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
4102                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4103                         adev->gfx.gfx_ring[i].sched.ready = false;
4104         }
4105         WREG32(mmCP_ME_CNTL, tmp);
4106         udelay(50);
4107 }
4108
4109 static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev)
4110 {
4111         u32 count = 0;
4112         const struct cs_section_def *sect = NULL;
4113         const struct cs_extent_def *ext = NULL;
4114
4115         /* begin clear state */
4116         count += 2;
4117         /* context control state */
4118         count += 3;
4119
4120         for (sect = vi_cs_data; sect->section != NULL; ++sect) {
4121                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4122                         if (sect->id == SECT_CONTEXT)
4123                                 count += 2 + ext->reg_count;
4124                         else
4125                                 return 0;
4126                 }
4127         }
4128         /* pa_sc_raster_config/pa_sc_raster_config1 */
4129         count += 4;
4130         /* end clear state */
4131         count += 2;
4132         /* clear state */
4133         count += 2;
4134
4135         return count;
4136 }
4137
4138 static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
4139 {
4140         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
4141         const struct cs_section_def *sect = NULL;
4142         const struct cs_extent_def *ext = NULL;
4143         int r, i;
4144
4145         /* init the CP */
4146         WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
4147         WREG32(mmCP_ENDIAN_SWAP, 0);
4148         WREG32(mmCP_DEVICE_ID, 1);
4149
4150         gfx_v8_0_cp_gfx_enable(adev, true);
4151
4152         r = amdgpu_ring_alloc(ring, gfx_v8_0_get_csb_size(adev) + 4);
4153         if (r) {
4154                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
4155                 return r;
4156         }
4157
4158         /* clear state buffer */
4159         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4160         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4161
4162         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4163         amdgpu_ring_write(ring, 0x80000000);
4164         amdgpu_ring_write(ring, 0x80000000);
4165
4166         for (sect = vi_cs_data; sect->section != NULL; ++sect) {
4167                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4168                         if (sect->id == SECT_CONTEXT) {
4169                                 amdgpu_ring_write(ring,
4170                                        PACKET3(PACKET3_SET_CONTEXT_REG,
4171                                                ext->reg_count));
4172                                 amdgpu_ring_write(ring,
4173                                        ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
4174                                 for (i = 0; i < ext->reg_count; i++)
4175                                         amdgpu_ring_write(ring, ext->extent[i]);
4176                         }
4177                 }
4178         }
4179
4180         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
4181         amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
4182         amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config);
4183         amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1);
4184
4185         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4186         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
4187
4188         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
4189         amdgpu_ring_write(ring, 0);
4190
4191         /* init the CE partitions */
4192         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
4193         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
4194         amdgpu_ring_write(ring, 0x8000);
4195         amdgpu_ring_write(ring, 0x8000);
4196
4197         amdgpu_ring_commit(ring);
4198
4199         return 0;
4200 }
4201 static void gfx_v8_0_set_cpg_door_bell(struct amdgpu_device *adev, struct amdgpu_ring *ring)
4202 {
4203         u32 tmp;
4204         /* no gfx doorbells on iceland */
4205         if (adev->asic_type == CHIP_TOPAZ)
4206                 return;
4207
4208         tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
4209
4210         if (ring->use_doorbell) {
4211                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4212                                 DOORBELL_OFFSET, ring->doorbell_index);
4213                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4214                                                 DOORBELL_HIT, 0);
4215                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4216                                             DOORBELL_EN, 1);
4217         } else {
4218                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
4219         }
4220
4221         WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
4222
4223         if (adev->flags & AMD_IS_APU)
4224                 return;
4225
4226         tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
4227                                         DOORBELL_RANGE_LOWER,
4228                                         adev->doorbell_index.gfx_ring0);
4229         WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
4230
4231         WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
4232                 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
4233 }
4234
4235 static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
4236 {
4237         struct amdgpu_ring *ring;
4238         u32 tmp;
4239         u32 rb_bufsz;
4240         u64 rb_addr, rptr_addr, wptr_gpu_addr;
4241
4242         /* Set the write pointer delay */
4243         WREG32(mmCP_RB_WPTR_DELAY, 0);
4244
4245         /* set the RB to use vmid 0 */
4246         WREG32(mmCP_RB_VMID, 0);
4247
4248         /* Set ring buffer size */
4249         ring = &adev->gfx.gfx_ring[0];
4250         rb_bufsz = order_base_2(ring->ring_size / 8);
4251         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
4252         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
4253         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);
4254         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);
4255 #ifdef __BIG_ENDIAN
4256         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
4257 #endif
4258         WREG32(mmCP_RB0_CNTL, tmp);
4259
4260         /* Initialize the ring buffer's read and write pointers */
4261         WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
4262         ring->wptr = 0;
4263         WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
4264
4265         /* set the wb address wether it's enabled or not */
4266         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
4267         WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
4268         WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
4269
4270         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
4271         WREG32(mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
4272         WREG32(mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
4273         mdelay(1);
4274         WREG32(mmCP_RB0_CNTL, tmp);
4275
4276         rb_addr = ring->gpu_addr >> 8;
4277         WREG32(mmCP_RB0_BASE, rb_addr);
4278         WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
4279
4280         gfx_v8_0_set_cpg_door_bell(adev, ring);
4281         /* start the ring */
4282         amdgpu_ring_clear_ring(ring);
4283         gfx_v8_0_cp_gfx_start(adev);
4284         ring->sched.ready = true;
4285
4286         return 0;
4287 }
4288
4289 static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
4290 {
4291         int i;
4292
4293         if (enable) {
4294                 WREG32(mmCP_MEC_CNTL, 0);
4295         } else {
4296                 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
4297                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4298                         adev->gfx.compute_ring[i].sched.ready = false;
4299                 adev->gfx.kiq.ring.sched.ready = false;
4300         }
4301         udelay(50);
4302 }
4303
4304 /* KIQ functions */
4305 static void gfx_v8_0_kiq_setting(struct amdgpu_ring *ring)
4306 {
4307         uint32_t tmp;
4308         struct amdgpu_device *adev = ring->adev;
4309
4310         /* tell RLC which is KIQ queue */
4311         tmp = RREG32(mmRLC_CP_SCHEDULERS);
4312         tmp &= 0xffffff00;
4313         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
4314         WREG32(mmRLC_CP_SCHEDULERS, tmp);
4315         tmp |= 0x80;
4316         WREG32(mmRLC_CP_SCHEDULERS, tmp);
4317 }
4318
4319 static int gfx_v8_0_kiq_kcq_enable(struct amdgpu_device *adev)
4320 {
4321         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
4322         uint64_t queue_mask = 0;
4323         int r, i;
4324
4325         for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
4326                 if (!test_bit(i, adev->gfx.mec.queue_bitmap))
4327                         continue;
4328
4329                 /* This situation may be hit in the future if a new HW
4330                  * generation exposes more than 64 queues. If so, the
4331                  * definition of queue_mask needs updating */
4332                 if (WARN_ON(i >= (sizeof(queue_mask)*8))) {
4333                         DRM_ERROR("Invalid KCQ enabled: %d\n", i);
4334                         break;
4335                 }
4336
4337                 queue_mask |= (1ull << i);
4338         }
4339
4340         r = amdgpu_ring_alloc(kiq_ring, (8 * adev->gfx.num_compute_rings) + 8);
4341         if (r) {
4342                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
4343                 return r;
4344         }
4345         /* set resources */
4346         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
4347         amdgpu_ring_write(kiq_ring, 0); /* vmid_mask:0 queue_type:0 (KIQ) */
4348         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
4349         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
4350         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
4351         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
4352         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
4353         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
4354         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4355                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
4356                 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
4357                 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
4358
4359                 /* map queues */
4360                 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
4361                 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
4362                 amdgpu_ring_write(kiq_ring,
4363                                   PACKET3_MAP_QUEUES_NUM_QUEUES(1));
4364                 amdgpu_ring_write(kiq_ring,
4365                                   PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index) |
4366                                   PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
4367                                   PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
4368                                   PACKET3_MAP_QUEUES_ME(ring->me == 1 ? 0 : 1)); /* doorbell */
4369                 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
4370                 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
4371                 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
4372                 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
4373         }
4374
4375         amdgpu_ring_commit(kiq_ring);
4376
4377         return 0;
4378 }
4379
4380 static int gfx_v8_0_deactivate_hqd(struct amdgpu_device *adev, u32 req)
4381 {
4382         int i, r = 0;
4383
4384         if (RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK) {
4385                 WREG32_FIELD(CP_HQD_DEQUEUE_REQUEST, DEQUEUE_REQ, req);
4386                 for (i = 0; i < adev->usec_timeout; i++) {
4387                         if (!(RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK))
4388                                 break;
4389                         udelay(1);
4390                 }
4391                 if (i == adev->usec_timeout)
4392                         r = -ETIMEDOUT;
4393         }
4394         WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0);
4395         WREG32(mmCP_HQD_PQ_RPTR, 0);
4396         WREG32(mmCP_HQD_PQ_WPTR, 0);
4397
4398         return r;
4399 }
4400
4401 static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
4402 {
4403         struct amdgpu_device *adev = ring->adev;
4404         struct vi_mqd *mqd = ring->mqd_ptr;
4405         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
4406         uint32_t tmp;
4407
4408         mqd->header = 0xC0310800;
4409         mqd->compute_pipelinestat_enable = 0x00000001;
4410         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
4411         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
4412         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
4413         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
4414         mqd->compute_misc_reserved = 0x00000003;
4415         mqd->dynamic_cu_mask_addr_lo = lower_32_bits(ring->mqd_gpu_addr
4416                                                      + offsetof(struct vi_mqd_allocation, dynamic_cu_mask));
4417         mqd->dynamic_cu_mask_addr_hi = upper_32_bits(ring->mqd_gpu_addr
4418                                                      + offsetof(struct vi_mqd_allocation, dynamic_cu_mask));
4419         eop_base_addr = ring->eop_gpu_addr >> 8;
4420         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
4421         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
4422
4423         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
4424         tmp = RREG32(mmCP_HQD_EOP_CONTROL);
4425         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
4426                         (order_base_2(GFX8_MEC_HPD_SIZE / 4) - 1));
4427
4428         mqd->cp_hqd_eop_control = tmp;
4429
4430         /* enable doorbell? */
4431         tmp = REG_SET_FIELD(RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL),
4432                             CP_HQD_PQ_DOORBELL_CONTROL,
4433                             DOORBELL_EN,
4434                             ring->use_doorbell ? 1 : 0);
4435
4436         mqd->cp_hqd_pq_doorbell_control = tmp;
4437
4438         /* set the pointer to the MQD */
4439         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
4440         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
4441
4442         /* set MQD vmid to 0 */
4443         tmp = RREG32(mmCP_MQD_CONTROL);
4444         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
4445         mqd->cp_mqd_control = tmp;
4446
4447         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
4448         hqd_gpu_addr = ring->gpu_addr >> 8;
4449         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
4450         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
4451
4452         /* set up the HQD, this is similar to CP_RB0_CNTL */
4453         tmp = RREG32(mmCP_HQD_PQ_CONTROL);
4454         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
4455                             (order_base_2(ring->ring_size / 4) - 1));
4456         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
4457                         ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
4458 #ifdef __BIG_ENDIAN
4459         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
4460 #endif
4461         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
4462         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
4463         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
4464         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
4465         mqd->cp_hqd_pq_control = tmp;
4466
4467         /* set the wb address whether it's enabled or not */
4468         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
4469         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
4470         mqd->cp_hqd_pq_rptr_report_addr_hi =
4471                 upper_32_bits(wb_gpu_addr) & 0xffff;
4472
4473         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
4474         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
4475         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
4476         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
4477
4478         tmp = 0;
4479         /* enable the doorbell if requested */
4480         if (ring->use_doorbell) {
4481                 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
4482                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4483                                 DOORBELL_OFFSET, ring->doorbell_index);
4484
4485                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4486                                          DOORBELL_EN, 1);
4487                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4488                                          DOORBELL_SOURCE, 0);
4489                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4490                                          DOORBELL_HIT, 0);
4491         }
4492
4493         mqd->cp_hqd_pq_doorbell_control = tmp;
4494
4495         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
4496         ring->wptr = 0;
4497         mqd->cp_hqd_pq_wptr = ring->wptr;
4498         mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
4499
4500         /* set the vmid for the queue */
4501         mqd->cp_hqd_vmid = 0;
4502
4503         tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
4504         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
4505         mqd->cp_hqd_persistent_state = tmp;
4506
4507         /* set MTYPE */
4508         tmp = RREG32(mmCP_HQD_IB_CONTROL);
4509         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
4510         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MTYPE, 3);
4511         mqd->cp_hqd_ib_control = tmp;
4512
4513         tmp = RREG32(mmCP_HQD_IQ_TIMER);
4514         tmp = REG_SET_FIELD(tmp, CP_HQD_IQ_TIMER, MTYPE, 3);
4515         mqd->cp_hqd_iq_timer = tmp;
4516
4517         tmp = RREG32(mmCP_HQD_CTX_SAVE_CONTROL);
4518         tmp = REG_SET_FIELD(tmp, CP_HQD_CTX_SAVE_CONTROL, MTYPE, 3);
4519         mqd->cp_hqd_ctx_save_control = tmp;
4520
4521         /* defaults */
4522         mqd->cp_hqd_eop_rptr = RREG32(mmCP_HQD_EOP_RPTR);
4523         mqd->cp_hqd_eop_wptr = RREG32(mmCP_HQD_EOP_WPTR);
4524         mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY);
4525         mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY);
4526         mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
4527         mqd->cp_hqd_ctx_save_base_addr_lo = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_LO);
4528         mqd->cp_hqd_ctx_save_base_addr_hi = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_HI);
4529         mqd->cp_hqd_cntl_stack_offset = RREG32(mmCP_HQD_CNTL_STACK_OFFSET);
4530         mqd->cp_hqd_cntl_stack_size = RREG32(mmCP_HQD_CNTL_STACK_SIZE);
4531         mqd->cp_hqd_wg_state_offset = RREG32(mmCP_HQD_WG_STATE_OFFSET);
4532         mqd->cp_hqd_ctx_save_size = RREG32(mmCP_HQD_CTX_SAVE_SIZE);
4533         mqd->cp_hqd_eop_done_events = RREG32(mmCP_HQD_EOP_EVENTS);
4534         mqd->cp_hqd_error = RREG32(mmCP_HQD_ERROR);
4535         mqd->cp_hqd_eop_wptr_mem = RREG32(mmCP_HQD_EOP_WPTR_MEM);
4536         mqd->cp_hqd_eop_dones = RREG32(mmCP_HQD_EOP_DONES);
4537
4538         /* activate the queue */
4539         mqd->cp_hqd_active = 1;
4540
4541         return 0;
4542 }
4543
4544 int gfx_v8_0_mqd_commit(struct amdgpu_device *adev,
4545                         struct vi_mqd *mqd)
4546 {
4547         uint32_t mqd_reg;
4548         uint32_t *mqd_data;
4549
4550         /* HQD registers extend from mmCP_MQD_BASE_ADDR to mmCP_HQD_ERROR */
4551         mqd_data = &mqd->cp_mqd_base_addr_lo;
4552
4553         /* disable wptr polling */
4554         WREG32_FIELD(CP_PQ_WPTR_POLL_CNTL, EN, 0);
4555
4556         /* program all HQD registers */
4557         for (mqd_reg = mmCP_HQD_VMID; mqd_reg <= mmCP_HQD_EOP_CONTROL; mqd_reg++)
4558                 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
4559
4560         /* Tonga errata: EOP RPTR/WPTR should be left unmodified.
4561          * This is safe since EOP RPTR==WPTR for any inactive HQD
4562          * on ASICs that do not support context-save.
4563          * EOP writes/reads can start anywhere in the ring.
4564          */
4565         if (adev->asic_type != CHIP_TONGA) {
4566                 WREG32(mmCP_HQD_EOP_RPTR, mqd->cp_hqd_eop_rptr);
4567                 WREG32(mmCP_HQD_EOP_WPTR, mqd->cp_hqd_eop_wptr);
4568                 WREG32(mmCP_HQD_EOP_WPTR_MEM, mqd->cp_hqd_eop_wptr_mem);
4569         }
4570
4571         for (mqd_reg = mmCP_HQD_EOP_EVENTS; mqd_reg <= mmCP_HQD_ERROR; mqd_reg++)
4572                 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
4573
4574         /* activate the HQD */
4575         for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++)
4576                 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
4577
4578         return 0;
4579 }
4580
4581 static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring)
4582 {
4583         struct amdgpu_device *adev = ring->adev;
4584         struct vi_mqd *mqd = ring->mqd_ptr;
4585         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
4586
4587         gfx_v8_0_kiq_setting(ring);
4588
4589         if (adev->in_gpu_reset) { /* for GPU_RESET case */
4590                 /* reset MQD to a clean status */
4591                 if (adev->gfx.mec.mqd_backup[mqd_idx])
4592                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation));
4593
4594                 /* reset ring buffer */
4595                 ring->wptr = 0;
4596                 amdgpu_ring_clear_ring(ring);
4597                 mutex_lock(&adev->srbm_mutex);
4598                 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4599                 gfx_v8_0_mqd_commit(adev, mqd);
4600                 vi_srbm_select(adev, 0, 0, 0, 0);
4601                 mutex_unlock(&adev->srbm_mutex);
4602         } else {
4603                 memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));
4604                 ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
4605                 ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
4606                 mutex_lock(&adev->srbm_mutex);
4607                 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4608                 gfx_v8_0_mqd_init(ring);
4609                 gfx_v8_0_mqd_commit(adev, mqd);
4610                 vi_srbm_select(adev, 0, 0, 0, 0);
4611                 mutex_unlock(&adev->srbm_mutex);
4612
4613                 if (adev->gfx.mec.mqd_backup[mqd_idx])
4614                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation));
4615         }
4616
4617         return 0;
4618 }
4619
4620 static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring)
4621 {
4622         struct amdgpu_device *adev = ring->adev;
4623         struct vi_mqd *mqd = ring->mqd_ptr;
4624         int mqd_idx = ring - &adev->gfx.compute_ring[0];
4625
4626         if (!adev->in_gpu_reset && !adev->in_suspend) {
4627                 memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));
4628                 ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
4629                 ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
4630                 mutex_lock(&adev->srbm_mutex);
4631                 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4632                 gfx_v8_0_mqd_init(ring);
4633                 vi_srbm_select(adev, 0, 0, 0, 0);
4634                 mutex_unlock(&adev->srbm_mutex);
4635
4636                 if (adev->gfx.mec.mqd_backup[mqd_idx])
4637                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation));
4638         } else if (adev->in_gpu_reset) { /* for GPU_RESET case */
4639                 /* reset MQD to a clean status */
4640                 if (adev->gfx.mec.mqd_backup[mqd_idx])
4641                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation));
4642                 /* reset ring buffer */
4643                 ring->wptr = 0;
4644                 amdgpu_ring_clear_ring(ring);
4645         } else {
4646                 amdgpu_ring_clear_ring(ring);
4647         }
4648         return 0;
4649 }
4650
4651 static void gfx_v8_0_set_mec_doorbell_range(struct amdgpu_device *adev)
4652 {
4653         if (adev->asic_type > CHIP_TONGA) {
4654                 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, adev->doorbell_index.kiq << 2);
4655                 WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, adev->doorbell_index.mec_ring7 << 2);
4656         }
4657         /* enable doorbells */
4658         WREG32_FIELD(CP_PQ_STATUS, DOORBELL_ENABLE, 1);
4659 }
4660
4661 static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev)
4662 {
4663         struct amdgpu_ring *ring;
4664         int r;
4665
4666         ring = &adev->gfx.kiq.ring;
4667
4668         r = amdgpu_bo_reserve(ring->mqd_obj, false);
4669         if (unlikely(r != 0))
4670                 return r;
4671
4672         r = amdgpu_bo_kmap(ring->mqd_obj, &ring->mqd_ptr);
4673         if (unlikely(r != 0))
4674                 return r;
4675
4676         gfx_v8_0_kiq_init_queue(ring);
4677         amdgpu_bo_kunmap(ring->mqd_obj);
4678         ring->mqd_ptr = NULL;
4679         amdgpu_bo_unreserve(ring->mqd_obj);
4680         ring->sched.ready = true;
4681         return 0;
4682 }
4683
4684 static int gfx_v8_0_kcq_resume(struct amdgpu_device *adev)
4685 {
4686         struct amdgpu_ring *ring = NULL;
4687         int r = 0, i;
4688
4689         gfx_v8_0_cp_compute_enable(adev, true);
4690
4691         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4692                 ring = &adev->gfx.compute_ring[i];
4693
4694                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
4695                 if (unlikely(r != 0))
4696                         goto done;
4697                 r = amdgpu_bo_kmap(ring->mqd_obj, &ring->mqd_ptr);
4698                 if (!r) {
4699                         r = gfx_v8_0_kcq_init_queue(ring);
4700                         amdgpu_bo_kunmap(ring->mqd_obj);
4701                         ring->mqd_ptr = NULL;
4702                 }
4703                 amdgpu_bo_unreserve(ring->mqd_obj);
4704                 if (r)
4705                         goto done;
4706         }
4707
4708         gfx_v8_0_set_mec_doorbell_range(adev);
4709
4710         r = gfx_v8_0_kiq_kcq_enable(adev);
4711         if (r)
4712                 goto done;
4713
4714 done:
4715         return r;
4716 }
4717
4718 static int gfx_v8_0_cp_test_all_rings(struct amdgpu_device *adev)
4719 {
4720         int r, i;
4721         struct amdgpu_ring *ring;
4722
4723         /* collect all the ring_tests here, gfx, kiq, compute */
4724         ring = &adev->gfx.gfx_ring[0];
4725         r = amdgpu_ring_test_helper(ring);
4726         if (r)
4727                 return r;
4728
4729         ring = &adev->gfx.kiq.ring;
4730         r = amdgpu_ring_test_helper(ring);
4731         if (r)
4732                 return r;
4733
4734         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4735                 ring = &adev->gfx.compute_ring[i];
4736                 amdgpu_ring_test_helper(ring);
4737         }
4738
4739         return 0;
4740 }
4741
4742 static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
4743 {
4744         int r;
4745
4746         if (!(adev->flags & AMD_IS_APU))
4747                 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
4748
4749         r = gfx_v8_0_kiq_resume(adev);
4750         if (r)
4751                 return r;
4752
4753         r = gfx_v8_0_cp_gfx_resume(adev);
4754         if (r)
4755                 return r;
4756
4757         r = gfx_v8_0_kcq_resume(adev);
4758         if (r)
4759                 return r;
4760
4761         r = gfx_v8_0_cp_test_all_rings(adev);
4762         if (r)
4763                 return r;
4764
4765         gfx_v8_0_enable_gui_idle_interrupt(adev, true);
4766
4767         return 0;
4768 }
4769
4770 static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable)
4771 {
4772         gfx_v8_0_cp_gfx_enable(adev, enable);
4773         gfx_v8_0_cp_compute_enable(adev, enable);
4774 }
4775
4776 static int gfx_v8_0_hw_init(void *handle)
4777 {
4778         int r;
4779         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4780
4781         gfx_v8_0_init_golden_registers(adev);
4782         gfx_v8_0_constants_init(adev);
4783
4784         r = adev->gfx.rlc.funcs->resume(adev);
4785         if (r)
4786                 return r;
4787
4788         r = gfx_v8_0_cp_resume(adev);
4789
4790         return r;
4791 }
4792
4793 static int gfx_v8_0_kcq_disable(struct amdgpu_device *adev)
4794 {
4795         int r, i;
4796         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
4797
4798         r = amdgpu_ring_alloc(kiq_ring, 6 * adev->gfx.num_compute_rings);
4799         if (r)
4800                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
4801
4802         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4803                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
4804
4805                 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
4806                 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
4807                                                 PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */
4808                                                 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
4809                                                 PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) |
4810                                                 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
4811                 amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
4812                 amdgpu_ring_write(kiq_ring, 0);
4813                 amdgpu_ring_write(kiq_ring, 0);
4814                 amdgpu_ring_write(kiq_ring, 0);
4815         }
4816         r = amdgpu_ring_test_helper(kiq_ring);
4817         if (r)
4818                 DRM_ERROR("KCQ disable failed\n");
4819
4820         return r;
4821 }
4822
4823 static bool gfx_v8_0_is_idle(void *handle)
4824 {
4825         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4826
4827         if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE)
4828                 || RREG32(mmGRBM_STATUS2) != 0x8)
4829                 return false;
4830         else
4831                 return true;
4832 }
4833
4834 static bool gfx_v8_0_rlc_is_idle(void *handle)
4835 {
4836         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4837
4838         if (RREG32(mmGRBM_STATUS2) != 0x8)
4839                 return false;
4840         else
4841                 return true;
4842 }
4843
4844 static int gfx_v8_0_wait_for_rlc_idle(void *handle)
4845 {
4846         unsigned int i;
4847         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4848
4849         for (i = 0; i < adev->usec_timeout; i++) {
4850                 if (gfx_v8_0_rlc_is_idle(handle))
4851                         return 0;
4852
4853                 udelay(1);
4854         }
4855         return -ETIMEDOUT;
4856 }
4857
4858 static int gfx_v8_0_wait_for_idle(void *handle)
4859 {
4860         unsigned int i;
4861         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4862
4863         for (i = 0; i < adev->usec_timeout; i++) {
4864                 if (gfx_v8_0_is_idle(handle))
4865                         return 0;
4866
4867                 udelay(1);
4868         }
4869         return -ETIMEDOUT;
4870 }
4871
4872 static int gfx_v8_0_hw_fini(void *handle)
4873 {
4874         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4875
4876         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4877         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
4878
4879         amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0);
4880
4881         amdgpu_irq_put(adev, &adev->gfx.sq_irq, 0);
4882
4883         /* disable KCQ to avoid CPC touch memory not valid anymore */
4884         gfx_v8_0_kcq_disable(adev);
4885
4886         if (amdgpu_sriov_vf(adev)) {
4887                 pr_debug("For SRIOV client, shouldn't do anything.\n");
4888                 return 0;
4889         }
4890         amdgpu_gfx_rlc_enter_safe_mode(adev);
4891         if (!gfx_v8_0_wait_for_idle(adev))
4892                 gfx_v8_0_cp_enable(adev, false);
4893         else
4894                 pr_err("cp is busy, skip halt cp\n");
4895         if (!gfx_v8_0_wait_for_rlc_idle(adev))
4896                 adev->gfx.rlc.funcs->stop(adev);
4897         else
4898                 pr_err("rlc is busy, skip halt rlc\n");
4899         amdgpu_gfx_rlc_exit_safe_mode(adev);
4900         return 0;
4901 }
4902
4903 static int gfx_v8_0_suspend(void *handle)
4904 {
4905         return gfx_v8_0_hw_fini(handle);
4906 }
4907
4908 static int gfx_v8_0_resume(void *handle)
4909 {
4910         return gfx_v8_0_hw_init(handle);
4911 }
4912
4913 static bool gfx_v8_0_check_soft_reset(void *handle)
4914 {
4915         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4916         u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4917         u32 tmp;
4918
4919         /* GRBM_STATUS */
4920         tmp = RREG32(mmGRBM_STATUS);
4921         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
4922                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
4923                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
4924                    GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
4925                    GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
4926                    GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK |
4927                    GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
4928                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4929                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
4930                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4931                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
4932                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
4933                                                 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
4934         }
4935
4936         /* GRBM_STATUS2 */
4937         tmp = RREG32(mmGRBM_STATUS2);
4938         if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
4939                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4940                                                 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4941
4942         if (REG_GET_FIELD(tmp, GRBM_STATUS2, CPF_BUSY) ||
4943             REG_GET_FIELD(tmp, GRBM_STATUS2, CPC_BUSY) ||
4944             REG_GET_FIELD(tmp, GRBM_STATUS2, CPG_BUSY)) {
4945                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4946                                                 SOFT_RESET_CPF, 1);
4947                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4948                                                 SOFT_RESET_CPC, 1);
4949                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4950                                                 SOFT_RESET_CPG, 1);
4951                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
4952                                                 SOFT_RESET_GRBM, 1);
4953         }
4954
4955         /* SRBM_STATUS */
4956         tmp = RREG32(mmSRBM_STATUS);
4957         if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING))
4958                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
4959                                                 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
4960         if (REG_GET_FIELD(tmp, SRBM_STATUS, SEM_BUSY))
4961                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
4962                                                 SRBM_SOFT_RESET, SOFT_RESET_SEM, 1);
4963
4964         if (grbm_soft_reset || srbm_soft_reset) {
4965                 adev->gfx.grbm_soft_reset = grbm_soft_reset;
4966                 adev->gfx.srbm_soft_reset = srbm_soft_reset;
4967                 return true;
4968         } else {
4969                 adev->gfx.grbm_soft_reset = 0;
4970                 adev->gfx.srbm_soft_reset = 0;
4971                 return false;
4972         }
4973 }
4974
4975 static int gfx_v8_0_pre_soft_reset(void *handle)
4976 {
4977         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4978         u32 grbm_soft_reset = 0;
4979
4980         if ((!adev->gfx.grbm_soft_reset) &&
4981             (!adev->gfx.srbm_soft_reset))
4982                 return 0;
4983
4984         grbm_soft_reset = adev->gfx.grbm_soft_reset;
4985
4986         /* stop the rlc */
4987         adev->gfx.rlc.funcs->stop(adev);
4988
4989         if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
4990             REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX))
4991                 /* Disable GFX parsing/prefetching */
4992                 gfx_v8_0_cp_gfx_enable(adev, false);
4993
4994         if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
4995             REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPF) ||
4996             REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPC) ||
4997             REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPG)) {
4998                 int i;
4999
5000                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5001                         struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
5002
5003                         mutex_lock(&adev->srbm_mutex);
5004                         vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
5005                         gfx_v8_0_deactivate_hqd(adev, 2);
5006                         vi_srbm_select(adev, 0, 0, 0, 0);
5007                         mutex_unlock(&adev->srbm_mutex);
5008                 }
5009                 /* Disable MEC parsing/prefetching */
5010                 gfx_v8_0_cp_compute_enable(adev, false);
5011         }
5012
5013        return 0;
5014 }
5015
5016 static int gfx_v8_0_soft_reset(void *handle)
5017 {
5018         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5019         u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
5020         u32 tmp;
5021
5022         if ((!adev->gfx.grbm_soft_reset) &&
5023             (!adev->gfx.srbm_soft_reset))
5024                 return 0;
5025
5026         grbm_soft_reset = adev->gfx.grbm_soft_reset;
5027         srbm_soft_reset = adev->gfx.srbm_soft_reset;
5028
5029         if (grbm_soft_reset || srbm_soft_reset) {
5030                 tmp = RREG32(mmGMCON_DEBUG);
5031                 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 1);
5032                 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 1);
5033                 WREG32(mmGMCON_DEBUG, tmp);
5034                 udelay(50);
5035         }
5036
5037         if (grbm_soft_reset) {
5038                 tmp = RREG32(mmGRBM_SOFT_RESET);
5039                 tmp |= grbm_soft_reset;
5040                 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
5041                 WREG32(mmGRBM_SOFT_RESET, tmp);
5042                 tmp = RREG32(mmGRBM_SOFT_RESET);
5043
5044                 udelay(50);
5045
5046                 tmp &= ~grbm_soft_reset;
5047                 WREG32(mmGRBM_SOFT_RESET, tmp);
5048                 tmp = RREG32(mmGRBM_SOFT_RESET);
5049         }
5050
5051         if (srbm_soft_reset) {
5052                 tmp = RREG32(mmSRBM_SOFT_RESET);
5053                 tmp |= srbm_soft_reset;
5054                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
5055                 WREG32(mmSRBM_SOFT_RESET, tmp);
5056                 tmp = RREG32(mmSRBM_SOFT_RESET);
5057
5058                 udelay(50);
5059
5060                 tmp &= ~srbm_soft_reset;
5061                 WREG32(mmSRBM_SOFT_RESET, tmp);
5062                 tmp = RREG32(mmSRBM_SOFT_RESET);
5063         }
5064
5065         if (grbm_soft_reset || srbm_soft_reset) {
5066                 tmp = RREG32(mmGMCON_DEBUG);
5067                 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 0);
5068                 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 0);
5069                 WREG32(mmGMCON_DEBUG, tmp);
5070         }
5071
5072         /* Wait a little for things to settle down */
5073         udelay(50);
5074
5075         return 0;
5076 }
5077
5078 static int gfx_v8_0_post_soft_reset(void *handle)
5079 {
5080         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5081         u32 grbm_soft_reset = 0;
5082
5083         if ((!adev->gfx.grbm_soft_reset) &&
5084             (!adev->gfx.srbm_soft_reset))
5085                 return 0;
5086
5087         grbm_soft_reset = adev->gfx.grbm_soft_reset;
5088
5089         if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
5090             REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPF) ||
5091             REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPC) ||
5092             REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPG)) {
5093                 int i;
5094
5095                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5096                         struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
5097
5098                         mutex_lock(&adev->srbm_mutex);
5099                         vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
5100                         gfx_v8_0_deactivate_hqd(adev, 2);
5101                         vi_srbm_select(adev, 0, 0, 0, 0);
5102                         mutex_unlock(&adev->srbm_mutex);
5103                 }
5104                 gfx_v8_0_kiq_resume(adev);
5105                 gfx_v8_0_kcq_resume(adev);
5106         }
5107
5108         if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
5109             REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX))
5110                 gfx_v8_0_cp_gfx_resume(adev);
5111
5112         gfx_v8_0_cp_test_all_rings(adev);
5113
5114         adev->gfx.rlc.funcs->start(adev);
5115
5116         return 0;
5117 }
5118
5119 /**
5120  * gfx_v8_0_get_gpu_clock_counter - return GPU clock counter snapshot
5121  *
5122  * @adev: amdgpu_device pointer
5123  *
5124  * Fetches a GPU clock counter snapshot.
5125  * Returns the 64 bit clock counter snapshot.
5126  */
5127 static uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev)
5128 {
5129         uint64_t clock;
5130
5131         mutex_lock(&adev->gfx.gpu_clock_mutex);
5132         WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
5133         clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
5134                 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
5135         mutex_unlock(&adev->gfx.gpu_clock_mutex);
5136         return clock;
5137 }
5138
5139 static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
5140                                           uint32_t vmid,
5141                                           uint32_t gds_base, uint32_t gds_size,
5142                                           uint32_t gws_base, uint32_t gws_size,
5143                                           uint32_t oa_base, uint32_t oa_size)
5144 {
5145         /* GDS Base */
5146         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5147         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5148                                 WRITE_DATA_DST_SEL(0)));
5149         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
5150         amdgpu_ring_write(ring, 0);
5151         amdgpu_ring_write(ring, gds_base);
5152
5153         /* GDS Size */
5154         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5155         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5156                                 WRITE_DATA_DST_SEL(0)));
5157         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
5158         amdgpu_ring_write(ring, 0);
5159         amdgpu_ring_write(ring, gds_size);
5160
5161         /* GWS */
5162         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5163         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5164                                 WRITE_DATA_DST_SEL(0)));
5165         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
5166         amdgpu_ring_write(ring, 0);
5167         amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
5168
5169         /* OA */
5170         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5171         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5172                                 WRITE_DATA_DST_SEL(0)));
5173         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
5174         amdgpu_ring_write(ring, 0);
5175         amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
5176 }
5177
5178 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
5179 {
5180         WREG32(mmSQ_IND_INDEX,
5181                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
5182                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
5183                 (address << SQ_IND_INDEX__INDEX__SHIFT) |
5184                 (SQ_IND_INDEX__FORCE_READ_MASK));
5185         return RREG32(mmSQ_IND_DATA);
5186 }
5187
5188 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
5189                            uint32_t wave, uint32_t thread,
5190                            uint32_t regno, uint32_t num, uint32_t *out)
5191 {
5192         WREG32(mmSQ_IND_INDEX,
5193                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
5194                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
5195                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
5196                 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
5197                 (SQ_IND_INDEX__FORCE_READ_MASK) |
5198                 (SQ_IND_INDEX__AUTO_INCR_MASK));
5199         while (num--)
5200                 *(out++) = RREG32(mmSQ_IND_DATA);
5201 }
5202
5203 static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
5204 {
5205         /* type 0 wave data */
5206         dst[(*no_fields)++] = 0;
5207         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
5208         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
5209         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
5210         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
5211         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
5212         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
5213         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
5214         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
5215         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
5216         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
5217         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
5218         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
5219         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
5220         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
5221         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
5222         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
5223         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
5224         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
5225 }
5226
5227 static void gfx_v8_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
5228                                      uint32_t wave, uint32_t start,
5229                                      uint32_t size, uint32_t *dst)
5230 {
5231         wave_read_regs(
5232                 adev, simd, wave, 0,
5233                 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
5234 }
5235
5236
5237 static const struct amdgpu_gfx_funcs gfx_v8_0_gfx_funcs = {
5238         .get_gpu_clock_counter = &gfx_v8_0_get_gpu_clock_counter,
5239         .select_se_sh = &gfx_v8_0_select_se_sh,
5240         .read_wave_data = &gfx_v8_0_read_wave_data,
5241         .read_wave_sgprs = &gfx_v8_0_read_wave_sgprs,
5242         .select_me_pipe_q = &gfx_v8_0_select_me_pipe_q
5243 };
5244
5245 static int gfx_v8_0_early_init(void *handle)
5246 {
5247         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5248
5249         adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS;
5250         adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
5251         adev->gfx.funcs = &gfx_v8_0_gfx_funcs;
5252         gfx_v8_0_set_ring_funcs(adev);
5253         gfx_v8_0_set_irq_funcs(adev);
5254         gfx_v8_0_set_gds_init(adev);
5255         gfx_v8_0_set_rlc_funcs(adev);
5256
5257         return 0;
5258 }
5259
5260 static int gfx_v8_0_late_init(void *handle)
5261 {
5262         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5263         int r;
5264
5265         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
5266         if (r)
5267                 return r;
5268
5269         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
5270         if (r)
5271                 return r;
5272
5273         /* requires IBs so do in late init after IB pool is initialized */
5274         r = gfx_v8_0_do_edc_gpr_workarounds(adev);
5275         if (r)
5276                 return r;
5277
5278         r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
5279         if (r) {
5280                 DRM_ERROR("amdgpu_irq_get() failed to get IRQ for EDC, r: %d.\n", r);
5281                 return r;
5282         }
5283
5284         r = amdgpu_irq_get(adev, &adev->gfx.sq_irq, 0);
5285         if (r) {
5286                 DRM_ERROR(
5287                         "amdgpu_irq_get() failed to get IRQ for SQ, r: %d.\n",
5288                         r);
5289                 return r;
5290         }
5291
5292         return 0;
5293 }
5294
5295 static void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
5296                                                        bool enable)
5297 {
5298         if (((adev->asic_type == CHIP_POLARIS11) ||
5299             (adev->asic_type == CHIP_POLARIS12) ||
5300             (adev->asic_type == CHIP_VEGAM)) &&
5301             adev->powerplay.pp_funcs->set_powergating_by_smu)
5302                 /* Send msg to SMU via Powerplay */
5303                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, enable);
5304
5305         WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0);
5306 }
5307
5308 static void gfx_v8_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
5309                                                         bool enable)
5310 {
5311         WREG32_FIELD(RLC_PG_CNTL, DYN_PER_CU_PG_ENABLE, enable ? 1 : 0);
5312 }
5313
5314 static void polaris11_enable_gfx_quick_mg_power_gating(struct amdgpu_device *adev,
5315                 bool enable)
5316 {
5317         WREG32_FIELD(RLC_PG_CNTL, QUICK_PG_ENABLE, enable ? 1 : 0);
5318 }
5319
5320 static void cz_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
5321                                           bool enable)
5322 {
5323         WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, enable ? 1 : 0);
5324 }
5325
5326 static void cz_enable_gfx_pipeline_power_gating(struct amdgpu_device *adev,
5327                                                 bool enable)
5328 {
5329         WREG32_FIELD(RLC_PG_CNTL, GFX_PIPELINE_PG_ENABLE, enable ? 1 : 0);
5330
5331         /* Read any GFX register to wake up GFX. */
5332         if (!enable)
5333                 RREG32(mmDB_RENDER_CONTROL);
5334 }
5335
5336 static void cz_update_gfx_cg_power_gating(struct amdgpu_device *adev,
5337                                           bool enable)
5338 {
5339         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
5340                 cz_enable_gfx_cg_power_gating(adev, true);
5341                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
5342                         cz_enable_gfx_pipeline_power_gating(adev, true);
5343         } else {
5344                 cz_enable_gfx_cg_power_gating(adev, false);
5345                 cz_enable_gfx_pipeline_power_gating(adev, false);
5346         }
5347 }
5348
5349 static int gfx_v8_0_set_powergating_state(void *handle,
5350                                           enum amd_powergating_state state)
5351 {
5352         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5353         bool enable = (state == AMD_PG_STATE_GATE);
5354
5355         if (amdgpu_sriov_vf(adev))
5356                 return 0;
5357
5358         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_SMG |
5359                                 AMD_PG_SUPPORT_RLC_SMU_HS |
5360                                 AMD_PG_SUPPORT_CP |
5361                                 AMD_PG_SUPPORT_GFX_DMG))
5362                 amdgpu_gfx_rlc_enter_safe_mode(adev);
5363         switch (adev->asic_type) {
5364         case CHIP_CARRIZO:
5365         case CHIP_STONEY:
5366
5367                 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
5368                         cz_enable_sck_slow_down_on_power_up(adev, true);
5369                         cz_enable_sck_slow_down_on_power_down(adev, true);
5370                 } else {
5371                         cz_enable_sck_slow_down_on_power_up(adev, false);
5372                         cz_enable_sck_slow_down_on_power_down(adev, false);
5373                 }
5374                 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
5375                         cz_enable_cp_power_gating(adev, true);
5376                 else
5377                         cz_enable_cp_power_gating(adev, false);
5378
5379                 cz_update_gfx_cg_power_gating(adev, enable);
5380
5381                 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
5382                         gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true);
5383                 else
5384                         gfx_v8_0_enable_gfx_static_mg_power_gating(adev, false);
5385
5386                 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
5387                         gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, true);
5388                 else
5389                         gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, false);
5390                 break;
5391         case CHIP_POLARIS11:
5392         case CHIP_POLARIS12:
5393         case CHIP_VEGAM:
5394                 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
5395                         gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true);
5396                 else
5397                         gfx_v8_0_enable_gfx_static_mg_power_gating(adev, false);
5398
5399                 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
5400                         gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, true);
5401                 else
5402                         gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, false);
5403
5404                 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_QUICK_MG) && enable)
5405                         polaris11_enable_gfx_quick_mg_power_gating(adev, true);
5406                 else
5407                         polaris11_enable_gfx_quick_mg_power_gating(adev, false);
5408                 break;
5409         default:
5410                 break;
5411         }
5412         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_SMG |
5413                                 AMD_PG_SUPPORT_RLC_SMU_HS |
5414                                 AMD_PG_SUPPORT_CP |
5415                                 AMD_PG_SUPPORT_GFX_DMG))
5416                 amdgpu_gfx_rlc_exit_safe_mode(adev);
5417         return 0;
5418 }
5419
5420 static void gfx_v8_0_get_clockgating_state(void *handle, u32 *flags)
5421 {
5422         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5423         int data;
5424
5425         if (amdgpu_sriov_vf(adev))
5426                 *flags = 0;
5427
5428         /* AMD_CG_SUPPORT_GFX_MGCG */
5429         data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5430         if (!(data & RLC_CGTT_MGCG_OVERRIDE__CPF_MASK))
5431                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
5432
5433         /* AMD_CG_SUPPORT_GFX_CGLG */
5434         data = RREG32(mmRLC_CGCG_CGLS_CTRL);
5435         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
5436                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
5437
5438         /* AMD_CG_SUPPORT_GFX_CGLS */
5439         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
5440                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
5441
5442         /* AMD_CG_SUPPORT_GFX_CGTS */
5443         data = RREG32(mmCGTS_SM_CTRL_REG);
5444         if (!(data & CGTS_SM_CTRL_REG__OVERRIDE_MASK))
5445                 *flags |= AMD_CG_SUPPORT_GFX_CGTS;
5446
5447         /* AMD_CG_SUPPORT_GFX_CGTS_LS */
5448         if (!(data & CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK))
5449                 *flags |= AMD_CG_SUPPORT_GFX_CGTS_LS;
5450
5451         /* AMD_CG_SUPPORT_GFX_RLC_LS */
5452         data = RREG32(mmRLC_MEM_SLP_CNTL);
5453         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
5454                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
5455
5456         /* AMD_CG_SUPPORT_GFX_CP_LS */
5457         data = RREG32(mmCP_MEM_SLP_CNTL);
5458         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
5459                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
5460 }
5461
5462 static void gfx_v8_0_send_serdes_cmd(struct amdgpu_device *adev,
5463                                      uint32_t reg_addr, uint32_t cmd)
5464 {
5465         uint32_t data;
5466
5467         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5468
5469         WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
5470         WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
5471
5472         data = RREG32(mmRLC_SERDES_WR_CTRL);
5473         if (adev->asic_type == CHIP_STONEY)
5474                 data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
5475                           RLC_SERDES_WR_CTRL__READ_COMMAND_MASK |
5476                           RLC_SERDES_WR_CTRL__P1_SELECT_MASK |
5477                           RLC_SERDES_WR_CTRL__P2_SELECT_MASK |
5478                           RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK |
5479                           RLC_SERDES_WR_CTRL__POWER_DOWN_MASK |
5480                           RLC_SERDES_WR_CTRL__POWER_UP_MASK |
5481                           RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK |
5482                           RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK);
5483         else
5484                 data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
5485                           RLC_SERDES_WR_CTRL__READ_COMMAND_MASK |
5486                           RLC_SERDES_WR_CTRL__P1_SELECT_MASK |
5487                           RLC_SERDES_WR_CTRL__P2_SELECT_MASK |
5488                           RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK |
5489                           RLC_SERDES_WR_CTRL__POWER_DOWN_MASK |
5490                           RLC_SERDES_WR_CTRL__POWER_UP_MASK |
5491                           RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK |
5492                           RLC_SERDES_WR_CTRL__BPM_DATA_MASK |
5493                           RLC_SERDES_WR_CTRL__REG_ADDR_MASK |
5494                           RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK);
5495         data |= (RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK |
5496                  (cmd << RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT) |
5497                  (reg_addr << RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT) |
5498                  (0xff << RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT));
5499
5500         WREG32(mmRLC_SERDES_WR_CTRL, data);
5501 }
5502
5503 #define MSG_ENTER_RLC_SAFE_MODE     1
5504 #define MSG_EXIT_RLC_SAFE_MODE      0
5505 #define RLC_GPR_REG2__REQ_MASK 0x00000001
5506 #define RLC_GPR_REG2__REQ__SHIFT 0
5507 #define RLC_GPR_REG2__MESSAGE__SHIFT 0x00000001
5508 #define RLC_GPR_REG2__MESSAGE_MASK 0x0000001e
5509
5510 static bool gfx_v8_0_is_rlc_enabled(struct amdgpu_device *adev)
5511 {
5512         uint32_t rlc_setting;
5513
5514         rlc_setting = RREG32(mmRLC_CNTL);
5515         if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
5516                 return false;
5517
5518         return true;
5519 }
5520
5521 static void gfx_v8_0_set_safe_mode(struct amdgpu_device *adev)
5522 {
5523         uint32_t data;
5524         unsigned i;
5525         data = RREG32(mmRLC_CNTL);
5526         data |= RLC_SAFE_MODE__CMD_MASK;
5527         data &= ~RLC_SAFE_MODE__MESSAGE_MASK;
5528         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
5529         WREG32(mmRLC_SAFE_MODE, data);
5530
5531         /* wait for RLC_SAFE_MODE */
5532         for (i = 0; i < adev->usec_timeout; i++) {
5533                 if ((RREG32(mmRLC_GPM_STAT) &
5534                      (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
5535                       RLC_GPM_STAT__GFX_POWER_STATUS_MASK)) ==
5536                     (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
5537                      RLC_GPM_STAT__GFX_POWER_STATUS_MASK))
5538                         break;
5539                 udelay(1);
5540         }
5541         for (i = 0; i < adev->usec_timeout; i++) {
5542                 if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
5543                         break;
5544                 udelay(1);
5545         }
5546 }
5547
5548 static void gfx_v8_0_unset_safe_mode(struct amdgpu_device *adev)
5549 {
5550         uint32_t data;
5551         unsigned i;
5552
5553         data = RREG32(mmRLC_CNTL);
5554         data |= RLC_SAFE_MODE__CMD_MASK;
5555         data &= ~RLC_SAFE_MODE__MESSAGE_MASK;
5556         WREG32(mmRLC_SAFE_MODE, data);
5557
5558         for (i = 0; i < adev->usec_timeout; i++) {
5559                 if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
5560                         break;
5561                 udelay(1);
5562         }
5563 }
5564
5565 static const struct amdgpu_rlc_funcs iceland_rlc_funcs = {
5566         .is_rlc_enabled = gfx_v8_0_is_rlc_enabled,
5567         .set_safe_mode = gfx_v8_0_set_safe_mode,
5568         .unset_safe_mode = gfx_v8_0_unset_safe_mode,
5569         .init = gfx_v8_0_rlc_init,
5570         .get_csb_size = gfx_v8_0_get_csb_size,
5571         .get_csb_buffer = gfx_v8_0_get_csb_buffer,
5572         .get_cp_table_num = gfx_v8_0_cp_jump_table_num,
5573         .resume = gfx_v8_0_rlc_resume,
5574         .stop = gfx_v8_0_rlc_stop,
5575         .reset = gfx_v8_0_rlc_reset,
5576         .start = gfx_v8_0_rlc_start
5577 };
5578
5579 static void gfx_v8_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
5580                                                       bool enable)
5581 {
5582         uint32_t temp, data;
5583
5584         amdgpu_gfx_rlc_enter_safe_mode(adev);
5585
5586         /* It is disabled by HW by default */
5587         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
5588                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
5589                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS)
5590                                 /* 1 - RLC memory Light sleep */
5591                                 WREG32_FIELD(RLC_MEM_SLP_CNTL, RLC_MEM_LS_EN, 1);
5592
5593                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS)
5594                                 WREG32_FIELD(CP_MEM_SLP_CNTL, CP_MEM_LS_EN, 1);
5595                 }
5596
5597                 /* 3 - RLC_CGTT_MGCG_OVERRIDE */
5598                 temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5599                 if (adev->flags & AMD_IS_APU)
5600                         data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
5601                                   RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
5602                                   RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK);
5603                 else
5604                         data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
5605                                   RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
5606                                   RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK |
5607                                   RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK);
5608
5609                 if (temp != data)
5610                         WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
5611
5612                 /* 4 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5613                 gfx_v8_0_wait_for_rlc_serdes(adev);
5614
5615                 /* 5 - clear mgcg override */
5616                 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
5617
5618                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
5619                         /* 6 - Enable CGTS(Tree Shade) MGCG /MGLS */
5620                         temp = data = RREG32(mmCGTS_SM_CTRL_REG);
5621                         data &= ~(CGTS_SM_CTRL_REG__SM_MODE_MASK);
5622                         data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
5623                         data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
5624                         data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
5625                         if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
5626                             (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
5627                                 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
5628                         data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
5629                         data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
5630                         if (temp != data)
5631                                 WREG32(mmCGTS_SM_CTRL_REG, data);
5632                 }
5633                 udelay(50);
5634
5635                 /* 7 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5636                 gfx_v8_0_wait_for_rlc_serdes(adev);
5637         } else {
5638                 /* 1 - MGCG_OVERRIDE[0] for CP and MGCG_OVERRIDE[1] for RLC */
5639                 temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5640                 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
5641                                 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
5642                                 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK |
5643                                 RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK);
5644                 if (temp != data)
5645                         WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
5646
5647                 /* 2 - disable MGLS in RLC */
5648                 data = RREG32(mmRLC_MEM_SLP_CNTL);
5649                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
5650                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
5651                         WREG32(mmRLC_MEM_SLP_CNTL, data);
5652                 }
5653
5654                 /* 3 - disable MGLS in CP */
5655                 data = RREG32(mmCP_MEM_SLP_CNTL);
5656                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
5657                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
5658                         WREG32(mmCP_MEM_SLP_CNTL, data);
5659                 }
5660
5661                 /* 4 - Disable CGTS(Tree Shade) MGCG and MGLS */
5662                 temp = data = RREG32(mmCGTS_SM_CTRL_REG);
5663                 data |= (CGTS_SM_CTRL_REG__OVERRIDE_MASK |
5664                                 CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK);
5665                 if (temp != data)
5666                         WREG32(mmCGTS_SM_CTRL_REG, data);
5667
5668                 /* 5 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5669                 gfx_v8_0_wait_for_rlc_serdes(adev);
5670
5671                 /* 6 - set mgcg override */
5672                 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, SET_BPM_SERDES_CMD);
5673
5674                 udelay(50);
5675
5676                 /* 7- wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5677                 gfx_v8_0_wait_for_rlc_serdes(adev);
5678         }
5679
5680         amdgpu_gfx_rlc_exit_safe_mode(adev);
5681 }
5682
5683 static void gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
5684                                                       bool enable)
5685 {
5686         uint32_t temp, temp1, data, data1;
5687
5688         temp = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
5689
5690         amdgpu_gfx_rlc_enter_safe_mode(adev);
5691
5692         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
5693                 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5694                 data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK;
5695                 if (temp1 != data1)
5696                         WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
5697
5698                 /* : wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5699                 gfx_v8_0_wait_for_rlc_serdes(adev);
5700
5701                 /* 2 - clear cgcg override */
5702                 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
5703
5704                 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5705                 gfx_v8_0_wait_for_rlc_serdes(adev);
5706
5707                 /* 3 - write cmd to set CGLS */
5708                 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, SET_BPM_SERDES_CMD);
5709
5710                 /* 4 - enable cgcg */
5711                 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
5712
5713                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
5714                         /* enable cgls*/
5715                         data |= RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
5716
5717                         temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5718                         data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK;
5719
5720                         if (temp1 != data1)
5721                                 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
5722                 } else {
5723                         data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
5724                 }
5725
5726                 if (temp != data)
5727                         WREG32(mmRLC_CGCG_CGLS_CTRL, data);
5728
5729                 /* 5 enable cntx_empty_int_enable/cntx_busy_int_enable/
5730                  * Cmp_busy/GFX_Idle interrupts
5731                  */
5732                 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
5733         } else {
5734                 /* disable cntx_empty_int_enable & GFX Idle interrupt */
5735                 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
5736
5737                 /* TEST CGCG */
5738                 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5739                 data1 |= (RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK |
5740                                 RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK);
5741                 if (temp1 != data1)
5742                         WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
5743
5744                 /* read gfx register to wake up cgcg */
5745                 RREG32(mmCB_CGTT_SCLK_CTRL);
5746                 RREG32(mmCB_CGTT_SCLK_CTRL);
5747                 RREG32(mmCB_CGTT_SCLK_CTRL);
5748                 RREG32(mmCB_CGTT_SCLK_CTRL);
5749
5750                 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5751                 gfx_v8_0_wait_for_rlc_serdes(adev);
5752
5753                 /* write cmd to Set CGCG Overrride */
5754                 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, SET_BPM_SERDES_CMD);
5755
5756                 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5757                 gfx_v8_0_wait_for_rlc_serdes(adev);
5758
5759                 /* write cmd to Clear CGLS */
5760                 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, CLE_BPM_SERDES_CMD);
5761
5762                 /* disable cgcg, cgls should be disabled too. */
5763                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK |
5764                           RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
5765                 if (temp != data)
5766                         WREG32(mmRLC_CGCG_CGLS_CTRL, data);
5767                 /* enable interrupts again for PG */
5768                 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
5769         }
5770
5771         gfx_v8_0_wait_for_rlc_serdes(adev);
5772
5773         amdgpu_gfx_rlc_exit_safe_mode(adev);
5774 }
5775 static int gfx_v8_0_update_gfx_clock_gating(struct amdgpu_device *adev,
5776                                             bool enable)
5777 {
5778         if (enable) {
5779                 /* CGCG/CGLS should be enabled after MGCG/MGLS/TS(CG/LS)
5780                  * ===  MGCG + MGLS + TS(CG/LS) ===
5781                  */
5782                 gfx_v8_0_update_medium_grain_clock_gating(adev, enable);
5783                 gfx_v8_0_update_coarse_grain_clock_gating(adev, enable);
5784         } else {
5785                 /* CGCG/CGLS should be disabled before MGCG/MGLS/TS(CG/LS)
5786                  * ===  CGCG + CGLS ===
5787                  */
5788                 gfx_v8_0_update_coarse_grain_clock_gating(adev, enable);
5789                 gfx_v8_0_update_medium_grain_clock_gating(adev, enable);
5790         }
5791         return 0;
5792 }
5793
5794 static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev,
5795                                           enum amd_clockgating_state state)
5796 {
5797         uint32_t msg_id, pp_state = 0;
5798         uint32_t pp_support_state = 0;
5799
5800         if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
5801                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
5802                         pp_support_state = PP_STATE_SUPPORT_LS;
5803                         pp_state = PP_STATE_LS;
5804                 }
5805                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
5806                         pp_support_state |= PP_STATE_SUPPORT_CG;
5807                         pp_state |= PP_STATE_CG;
5808                 }
5809                 if (state == AMD_CG_STATE_UNGATE)
5810                         pp_state = 0;
5811
5812                 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5813                                 PP_BLOCK_GFX_CG,
5814                                 pp_support_state,
5815                                 pp_state);
5816                 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
5817                         amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5818         }
5819
5820         if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
5821                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
5822                         pp_support_state = PP_STATE_SUPPORT_LS;
5823                         pp_state = PP_STATE_LS;
5824                 }
5825
5826                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
5827                         pp_support_state |= PP_STATE_SUPPORT_CG;
5828                         pp_state |= PP_STATE_CG;
5829                 }
5830
5831                 if (state == AMD_CG_STATE_UNGATE)
5832                         pp_state = 0;
5833
5834                 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5835                                 PP_BLOCK_GFX_MG,
5836                                 pp_support_state,
5837                                 pp_state);
5838                 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
5839                         amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5840         }
5841
5842         return 0;
5843 }
5844
5845 static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
5846                                           enum amd_clockgating_state state)
5847 {
5848
5849         uint32_t msg_id, pp_state = 0;
5850         uint32_t pp_support_state = 0;
5851
5852         if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
5853                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
5854                         pp_support_state = PP_STATE_SUPPORT_LS;
5855                         pp_state = PP_STATE_LS;
5856                 }
5857                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
5858                         pp_support_state |= PP_STATE_SUPPORT_CG;
5859                         pp_state |= PP_STATE_CG;
5860                 }
5861                 if (state == AMD_CG_STATE_UNGATE)
5862                         pp_state = 0;
5863
5864                 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5865                                 PP_BLOCK_GFX_CG,
5866                                 pp_support_state,
5867                                 pp_state);
5868                 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
5869                         amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5870         }
5871
5872         if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)) {
5873                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) {
5874                         pp_support_state = PP_STATE_SUPPORT_LS;
5875                         pp_state = PP_STATE_LS;
5876                 }
5877                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) {
5878                         pp_support_state |= PP_STATE_SUPPORT_CG;
5879                         pp_state |= PP_STATE_CG;
5880                 }
5881                 if (state == AMD_CG_STATE_UNGATE)
5882                         pp_state = 0;
5883
5884                 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5885                                 PP_BLOCK_GFX_3D,
5886                                 pp_support_state,
5887                                 pp_state);
5888                 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
5889                         amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5890         }
5891
5892         if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
5893                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
5894                         pp_support_state = PP_STATE_SUPPORT_LS;
5895                         pp_state = PP_STATE_LS;
5896                 }
5897
5898                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
5899                         pp_support_state |= PP_STATE_SUPPORT_CG;
5900                         pp_state |= PP_STATE_CG;
5901                 }
5902
5903                 if (state == AMD_CG_STATE_UNGATE)
5904                         pp_state = 0;
5905
5906                 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5907                                 PP_BLOCK_GFX_MG,
5908                                 pp_support_state,
5909                                 pp_state);
5910                 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
5911                         amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5912         }
5913
5914         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
5915                 pp_support_state = PP_STATE_SUPPORT_LS;
5916
5917                 if (state == AMD_CG_STATE_UNGATE)
5918                         pp_state = 0;
5919                 else
5920                         pp_state = PP_STATE_LS;
5921
5922                 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5923                                 PP_BLOCK_GFX_RLC,
5924                                 pp_support_state,
5925                                 pp_state);
5926                 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
5927                         amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5928         }
5929
5930         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
5931                 pp_support_state = PP_STATE_SUPPORT_LS;
5932
5933                 if (state == AMD_CG_STATE_UNGATE)
5934                         pp_state = 0;
5935                 else
5936                         pp_state = PP_STATE_LS;
5937                 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5938                         PP_BLOCK_GFX_CP,
5939                         pp_support_state,
5940                         pp_state);
5941                 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
5942                         amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5943         }
5944
5945         return 0;
5946 }
5947
5948 static int gfx_v8_0_set_clockgating_state(void *handle,
5949                                           enum amd_clockgating_state state)
5950 {
5951         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5952
5953         if (amdgpu_sriov_vf(adev))
5954                 return 0;
5955
5956         switch (adev->asic_type) {
5957         case CHIP_FIJI:
5958         case CHIP_CARRIZO:
5959         case CHIP_STONEY:
5960                 gfx_v8_0_update_gfx_clock_gating(adev,
5961                                                  state == AMD_CG_STATE_GATE);
5962                 break;
5963         case CHIP_TONGA:
5964                 gfx_v8_0_tonga_update_gfx_clock_gating(adev, state);
5965                 break;
5966         case CHIP_POLARIS10:
5967         case CHIP_POLARIS11:
5968         case CHIP_POLARIS12:
5969         case CHIP_VEGAM:
5970                 gfx_v8_0_polaris_update_gfx_clock_gating(adev, state);
5971                 break;
5972         default:
5973                 break;
5974         }
5975         return 0;
5976 }
5977
5978 static u64 gfx_v8_0_ring_get_rptr(struct amdgpu_ring *ring)
5979 {
5980         return ring->adev->wb.wb[ring->rptr_offs];
5981 }
5982
5983 static u64 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
5984 {
5985         struct amdgpu_device *adev = ring->adev;
5986
5987         if (ring->use_doorbell)
5988                 /* XXX check if swapping is necessary on BE */
5989                 return ring->adev->wb.wb[ring->wptr_offs];
5990         else
5991                 return RREG32(mmCP_RB0_WPTR);
5992 }
5993
5994 static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
5995 {
5996         struct amdgpu_device *adev = ring->adev;
5997
5998         if (ring->use_doorbell) {
5999                 /* XXX check if swapping is necessary on BE */
6000                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
6001                 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
6002         } else {
6003                 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6004                 (void)RREG32(mmCP_RB0_WPTR);
6005         }
6006 }
6007
6008 static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
6009 {
6010         u32 ref_and_mask, reg_mem_engine;
6011
6012         if ((ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) ||
6013             (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)) {
6014                 switch (ring->me) {
6015                 case 1:
6016                         ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
6017                         break;
6018                 case 2:
6019                         ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
6020                         break;
6021                 default:
6022                         return;
6023                 }
6024                 reg_mem_engine = 0;
6025         } else {
6026                 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
6027                 reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */
6028         }
6029
6030         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
6031         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
6032                                  WAIT_REG_MEM_FUNCTION(3) |  /* == */
6033                                  reg_mem_engine));
6034         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
6035         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
6036         amdgpu_ring_write(ring, ref_and_mask);
6037         amdgpu_ring_write(ring, ref_and_mask);
6038         amdgpu_ring_write(ring, 0x20); /* poll interval */
6039 }
6040
6041 static void gfx_v8_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
6042 {
6043         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
6044         amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) |
6045                 EVENT_INDEX(4));
6046
6047         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
6048         amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
6049                 EVENT_INDEX(0));
6050 }
6051
6052 static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
6053                                         struct amdgpu_job *job,
6054                                         struct amdgpu_ib *ib,
6055                                         uint32_t flags)
6056 {
6057         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
6058         u32 header, control = 0;
6059
6060         if (ib->flags & AMDGPU_IB_FLAG_CE)
6061                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
6062         else
6063                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
6064
6065         control |= ib->length_dw | (vmid << 24);
6066
6067         if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
6068                 control |= INDIRECT_BUFFER_PRE_ENB(1);
6069
6070                 if (!(ib->flags & AMDGPU_IB_FLAG_CE))
6071                         gfx_v8_0_ring_emit_de_meta(ring);
6072         }
6073
6074         amdgpu_ring_write(ring, header);
6075         amdgpu_ring_write(ring,
6076 #ifdef __BIG_ENDIAN
6077                           (2 << 0) |
6078 #endif
6079                           (ib->gpu_addr & 0xFFFFFFFC));
6080         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
6081         amdgpu_ring_write(ring, control);
6082 }
6083
6084 static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
6085                                           struct amdgpu_job *job,
6086                                           struct amdgpu_ib *ib,
6087                                           uint32_t flags)
6088 {
6089         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
6090         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
6091
6092         /* Currently, there is a high possibility to get wave ID mismatch
6093          * between ME and GDS, leading to a hw deadlock, because ME generates
6094          * different wave IDs than the GDS expects. This situation happens
6095          * randomly when at least 5 compute pipes use GDS ordered append.
6096          * The wave IDs generated by ME are also wrong after suspend/resume.
6097          * Those are probably bugs somewhere else in the kernel driver.
6098          *
6099          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
6100          * GDS to 0 for this ring (me/pipe).
6101          */
6102         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
6103                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
6104                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID - PACKET3_SET_CONFIG_REG_START);
6105                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
6106         }
6107
6108         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
6109         amdgpu_ring_write(ring,
6110 #ifdef __BIG_ENDIAN
6111                                 (2 << 0) |
6112 #endif
6113                                 (ib->gpu_addr & 0xFFFFFFFC));
6114         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
6115         amdgpu_ring_write(ring, control);
6116 }
6117
6118 static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
6119                                          u64 seq, unsigned flags)
6120 {
6121         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
6122         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
6123
6124         /* EVENT_WRITE_EOP - flush caches, send int */
6125         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
6126         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
6127                                  EOP_TC_ACTION_EN |
6128                                  EOP_TC_WB_ACTION_EN |
6129                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
6130                                  EVENT_INDEX(5)));
6131         amdgpu_ring_write(ring, addr & 0xfffffffc);
6132         amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
6133                           DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
6134         amdgpu_ring_write(ring, lower_32_bits(seq));
6135         amdgpu_ring_write(ring, upper_32_bits(seq));
6136
6137 }
6138
6139 static void gfx_v8_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
6140 {
6141         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
6142         uint32_t seq = ring->fence_drv.sync_seq;
6143         uint64_t addr = ring->fence_drv.gpu_addr;
6144
6145         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
6146         amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
6147                                  WAIT_REG_MEM_FUNCTION(3) | /* equal */
6148                                  WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
6149         amdgpu_ring_write(ring, addr & 0xfffffffc);
6150         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
6151         amdgpu_ring_write(ring, seq);
6152         amdgpu_ring_write(ring, 0xffffffff);
6153         amdgpu_ring_write(ring, 4); /* poll interval */
6154 }
6155
6156 static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
6157                                         unsigned vmid, uint64_t pd_addr)
6158 {
6159         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
6160
6161         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
6162
6163         /* wait for the invalidate to complete */
6164         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
6165         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
6166                                  WAIT_REG_MEM_FUNCTION(0) |  /* always */
6167                                  WAIT_REG_MEM_ENGINE(0))); /* me */
6168         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
6169         amdgpu_ring_write(ring, 0);
6170         amdgpu_ring_write(ring, 0); /* ref */
6171         amdgpu_ring_write(ring, 0); /* mask */
6172         amdgpu_ring_write(ring, 0x20); /* poll interval */
6173
6174         /* compute doesn't have PFP */
6175         if (usepfp) {
6176                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
6177                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
6178                 amdgpu_ring_write(ring, 0x0);
6179         }
6180 }
6181
6182 static u64 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
6183 {
6184         return ring->adev->wb.wb[ring->wptr_offs];
6185 }
6186
6187 static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
6188 {
6189         struct amdgpu_device *adev = ring->adev;
6190
6191         /* XXX check if swapping is necessary on BE */
6192         adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
6193         WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
6194 }
6195
6196 static void gfx_v8_0_ring_set_pipe_percent(struct amdgpu_ring *ring,
6197                                            bool acquire)
6198 {
6199         struct amdgpu_device *adev = ring->adev;
6200         int pipe_num, tmp, reg;
6201         int pipe_percent = acquire ? SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK : 0x1;
6202
6203         pipe_num = ring->me * adev->gfx.mec.num_pipe_per_mec + ring->pipe;
6204
6205         /* first me only has 2 entries, GFX and HP3D */
6206         if (ring->me > 0)
6207                 pipe_num -= 2;
6208
6209         reg = mmSPI_WCL_PIPE_PERCENT_GFX + pipe_num;
6210         tmp = RREG32(reg);
6211         tmp = REG_SET_FIELD(tmp, SPI_WCL_PIPE_PERCENT_GFX, VALUE, pipe_percent);
6212         WREG32(reg, tmp);
6213 }
6214
6215 static void gfx_v8_0_pipe_reserve_resources(struct amdgpu_device *adev,
6216                                             struct amdgpu_ring *ring,
6217                                             bool acquire)
6218 {
6219         int i, pipe;
6220         bool reserve;
6221         struct amdgpu_ring *iring;
6222
6223         mutex_lock(&adev->gfx.pipe_reserve_mutex);
6224         pipe = amdgpu_gfx_queue_to_bit(adev, ring->me, ring->pipe, 0);
6225         if (acquire)
6226                 set_bit(pipe, adev->gfx.pipe_reserve_bitmap);
6227         else
6228                 clear_bit(pipe, adev->gfx.pipe_reserve_bitmap);
6229
6230         if (!bitmap_weight(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES)) {
6231                 /* Clear all reservations - everyone reacquires all resources */
6232                 for (i = 0; i < adev->gfx.num_gfx_rings; ++i)
6233                         gfx_v8_0_ring_set_pipe_percent(&adev->gfx.gfx_ring[i],
6234                                                        true);
6235
6236                 for (i = 0; i < adev->gfx.num_compute_rings; ++i)
6237                         gfx_v8_0_ring_set_pipe_percent(&adev->gfx.compute_ring[i],
6238                                                        true);
6239         } else {
6240                 /* Lower all pipes without a current reservation */
6241                 for (i = 0; i < adev->gfx.num_gfx_rings; ++i) {
6242                         iring = &adev->gfx.gfx_ring[i];
6243                         pipe = amdgpu_gfx_queue_to_bit(adev,
6244                                                        iring->me,
6245                                                        iring->pipe,
6246                                                        0);
6247                         reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
6248                         gfx_v8_0_ring_set_pipe_percent(iring, reserve);
6249                 }
6250
6251                 for (i = 0; i < adev->gfx.num_compute_rings; ++i) {
6252                         iring = &adev->gfx.compute_ring[i];
6253                         pipe = amdgpu_gfx_queue_to_bit(adev,
6254                                                        iring->me,
6255                                                        iring->pipe,
6256                                                        0);
6257                         reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
6258                         gfx_v8_0_ring_set_pipe_percent(iring, reserve);
6259                 }
6260         }
6261
6262         mutex_unlock(&adev->gfx.pipe_reserve_mutex);
6263 }
6264
6265 static void gfx_v8_0_hqd_set_priority(struct amdgpu_device *adev,
6266                                       struct amdgpu_ring *ring,
6267                                       bool acquire)
6268 {
6269         uint32_t pipe_priority = acquire ? 0x2 : 0x0;
6270         uint32_t queue_priority = acquire ? 0xf : 0x0;
6271
6272         mutex_lock(&adev->srbm_mutex);
6273         vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6274
6275         WREG32(mmCP_HQD_PIPE_PRIORITY, pipe_priority);
6276         WREG32(mmCP_HQD_QUEUE_PRIORITY, queue_priority);
6277
6278         vi_srbm_select(adev, 0, 0, 0, 0);
6279         mutex_unlock(&adev->srbm_mutex);
6280 }
6281 static void gfx_v8_0_ring_set_priority_compute(struct amdgpu_ring *ring,
6282                                                enum drm_sched_priority priority)
6283 {
6284         struct amdgpu_device *adev = ring->adev;
6285         bool acquire = priority == DRM_SCHED_PRIORITY_HIGH_HW;
6286
6287         if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE)
6288                 return;
6289
6290         gfx_v8_0_hqd_set_priority(adev, ring, acquire);
6291         gfx_v8_0_pipe_reserve_resources(adev, ring, acquire);
6292 }
6293
6294 static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
6295                                              u64 addr, u64 seq,
6296                                              unsigned flags)
6297 {
6298         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
6299         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
6300
6301         /* RELEASE_MEM - flush caches, send int */
6302         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
6303         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
6304                                  EOP_TC_ACTION_EN |
6305                                  EOP_TC_WB_ACTION_EN |
6306                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
6307                                  EVENT_INDEX(5)));
6308         amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
6309         amdgpu_ring_write(ring, addr & 0xfffffffc);
6310         amdgpu_ring_write(ring, upper_32_bits(addr));
6311         amdgpu_ring_write(ring, lower_32_bits(seq));
6312         amdgpu_ring_write(ring, upper_32_bits(seq));
6313 }
6314
6315 static void gfx_v8_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
6316                                          u64 seq, unsigned int flags)
6317 {
6318         /* we only allocate 32bit for each seq wb address */
6319         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
6320
6321         /* write fence seq to the "addr" */
6322         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
6323         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
6324                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
6325         amdgpu_ring_write(ring, lower_32_bits(addr));
6326         amdgpu_ring_write(ring, upper_32_bits(addr));
6327         amdgpu_ring_write(ring, lower_32_bits(seq));
6328
6329         if (flags & AMDGPU_FENCE_FLAG_INT) {
6330                 /* set register to trigger INT */
6331                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
6332                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
6333                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
6334                 amdgpu_ring_write(ring, mmCPC_INT_STATUS);
6335                 amdgpu_ring_write(ring, 0);
6336                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
6337         }
6338 }
6339
6340 static void gfx_v8_ring_emit_sb(struct amdgpu_ring *ring)
6341 {
6342         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
6343         amdgpu_ring_write(ring, 0);
6344 }
6345
6346 static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
6347 {
6348         uint32_t dw2 = 0;
6349
6350         if (amdgpu_sriov_vf(ring->adev))
6351                 gfx_v8_0_ring_emit_ce_meta(ring);
6352
6353         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
6354         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
6355                 gfx_v8_0_ring_emit_vgt_flush(ring);
6356                 /* set load_global_config & load_global_uconfig */
6357                 dw2 |= 0x8001;
6358                 /* set load_cs_sh_regs */
6359                 dw2 |= 0x01000000;
6360                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
6361                 dw2 |= 0x10002;
6362
6363                 /* set load_ce_ram if preamble presented */
6364                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
6365                         dw2 |= 0x10000000;
6366         } else {
6367                 /* still load_ce_ram if this is the first time preamble presented
6368                  * although there is no context switch happens.
6369                  */
6370                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
6371                         dw2 |= 0x10000000;
6372         }
6373
6374         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
6375         amdgpu_ring_write(ring, dw2);
6376         amdgpu_ring_write(ring, 0);
6377 }
6378
6379 static unsigned gfx_v8_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
6380 {
6381         unsigned ret;
6382
6383         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
6384         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
6385         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
6386         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
6387         ret = ring->wptr & ring->buf_mask;
6388         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
6389         return ret;
6390 }
6391
6392 static void gfx_v8_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
6393 {
6394         unsigned cur;
6395
6396         BUG_ON(offset > ring->buf_mask);
6397         BUG_ON(ring->ring[offset] != 0x55aa55aa);
6398
6399         cur = (ring->wptr & ring->buf_mask) - 1;
6400         if (likely(cur > offset))
6401                 ring->ring[offset] = cur - offset;
6402         else
6403                 ring->ring[offset] = (ring->ring_size >> 2) - offset + cur;
6404 }
6405
6406 static void gfx_v8_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
6407 {
6408         struct amdgpu_device *adev = ring->adev;
6409
6410         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
6411         amdgpu_ring_write(ring, 0 |     /* src: register*/
6412                                 (5 << 8) |      /* dst: memory */
6413                                 (1 << 20));     /* write confirm */
6414         amdgpu_ring_write(ring, reg);
6415         amdgpu_ring_write(ring, 0);
6416         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
6417                                 adev->virt.reg_val_offs * 4));
6418         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
6419                                 adev->virt.reg_val_offs * 4));
6420 }
6421
6422 static void gfx_v8_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
6423                                   uint32_t val)
6424 {
6425         uint32_t cmd;
6426
6427         switch (ring->funcs->type) {
6428         case AMDGPU_RING_TYPE_GFX:
6429                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
6430                 break;
6431         case AMDGPU_RING_TYPE_KIQ:
6432                 cmd = 1 << 16; /* no inc addr */
6433                 break;
6434         default:
6435                 cmd = WR_CONFIRM;
6436                 break;
6437         }
6438
6439         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
6440         amdgpu_ring_write(ring, cmd);
6441         amdgpu_ring_write(ring, reg);
6442         amdgpu_ring_write(ring, 0);
6443         amdgpu_ring_write(ring, val);
6444 }
6445
6446 static void gfx_v8_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid)
6447 {
6448         struct amdgpu_device *adev = ring->adev;
6449         uint32_t value = 0;
6450
6451         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
6452         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
6453         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
6454         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
6455         WREG32(mmSQ_CMD, value);
6456 }
6457
6458 static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
6459                                                  enum amdgpu_interrupt_state state)
6460 {
6461         WREG32_FIELD(CP_INT_CNTL_RING0, TIME_STAMP_INT_ENABLE,
6462                      state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
6463 }
6464
6465 static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
6466                                                      int me, int pipe,
6467                                                      enum amdgpu_interrupt_state state)
6468 {
6469         u32 mec_int_cntl, mec_int_cntl_reg;
6470
6471         /*
6472          * amdgpu controls only the first MEC. That's why this function only
6473          * handles the setting of interrupts for this specific MEC. All other
6474          * pipes' interrupts are set by amdkfd.
6475          */
6476
6477         if (me == 1) {
6478                 switch (pipe) {
6479                 case 0:
6480                         mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
6481                         break;
6482                 case 1:
6483                         mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL;
6484                         break;
6485                 case 2:
6486                         mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL;
6487                         break;
6488                 case 3:
6489                         mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL;
6490                         break;
6491                 default:
6492                         DRM_DEBUG("invalid pipe %d\n", pipe);
6493                         return;
6494                 }
6495         } else {
6496                 DRM_DEBUG("invalid me %d\n", me);
6497                 return;
6498         }
6499
6500         switch (state) {
6501         case AMDGPU_IRQ_STATE_DISABLE:
6502                 mec_int_cntl = RREG32(mec_int_cntl_reg);
6503                 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
6504                 WREG32(mec_int_cntl_reg, mec_int_cntl);
6505                 break;
6506         case AMDGPU_IRQ_STATE_ENABLE:
6507                 mec_int_cntl = RREG32(mec_int_cntl_reg);
6508                 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
6509                 WREG32(mec_int_cntl_reg, mec_int_cntl);
6510                 break;
6511         default:
6512                 break;
6513         }
6514 }
6515
6516 static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
6517                                              struct amdgpu_irq_src *source,
6518                                              unsigned type,
6519                                              enum amdgpu_interrupt_state state)
6520 {
6521         WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_REG_INT_ENABLE,
6522                      state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
6523
6524         return 0;
6525 }
6526
6527 static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
6528                                               struct amdgpu_irq_src *source,
6529                                               unsigned type,
6530                                               enum amdgpu_interrupt_state state)
6531 {
6532         WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_INSTR_INT_ENABLE,
6533                      state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
6534
6535         return 0;
6536 }
6537
6538 static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev,
6539                                             struct amdgpu_irq_src *src,
6540                                             unsigned type,
6541                                             enum amdgpu_interrupt_state state)
6542 {
6543         switch (type) {
6544         case AMDGPU_CP_IRQ_GFX_EOP:
6545                 gfx_v8_0_set_gfx_eop_interrupt_state(adev, state);
6546                 break;
6547         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
6548                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
6549                 break;
6550         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
6551                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
6552                 break;
6553         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
6554                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
6555                 break;
6556         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
6557                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
6558                 break;
6559         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
6560                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
6561                 break;
6562         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
6563                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
6564                 break;
6565         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
6566                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
6567                 break;
6568         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
6569                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
6570                 break;
6571         default:
6572                 break;
6573         }
6574         return 0;
6575 }
6576
6577 static int gfx_v8_0_set_cp_ecc_int_state(struct amdgpu_device *adev,
6578                                          struct amdgpu_irq_src *source,
6579                                          unsigned int type,
6580                                          enum amdgpu_interrupt_state state)
6581 {
6582         int enable_flag;
6583
6584         switch (state) {
6585         case AMDGPU_IRQ_STATE_DISABLE:
6586                 enable_flag = 0;
6587                 break;
6588
6589         case AMDGPU_IRQ_STATE_ENABLE:
6590                 enable_flag = 1;
6591                 break;
6592
6593         default:
6594                 return -EINVAL;
6595         }
6596
6597         WREG32_FIELD(CP_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, enable_flag);
6598         WREG32_FIELD(CP_INT_CNTL_RING0, CP_ECC_ERROR_INT_ENABLE, enable_flag);
6599         WREG32_FIELD(CP_INT_CNTL_RING1, CP_ECC_ERROR_INT_ENABLE, enable_flag);
6600         WREG32_FIELD(CP_INT_CNTL_RING2, CP_ECC_ERROR_INT_ENABLE, enable_flag);
6601         WREG32_FIELD(CPC_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, enable_flag);
6602         WREG32_FIELD(CP_ME1_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6603                      enable_flag);
6604         WREG32_FIELD(CP_ME1_PIPE1_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6605                      enable_flag);
6606         WREG32_FIELD(CP_ME1_PIPE2_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6607                      enable_flag);
6608         WREG32_FIELD(CP_ME1_PIPE3_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6609                      enable_flag);
6610         WREG32_FIELD(CP_ME2_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6611                      enable_flag);
6612         WREG32_FIELD(CP_ME2_PIPE1_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6613                      enable_flag);
6614         WREG32_FIELD(CP_ME2_PIPE2_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6615                      enable_flag);
6616         WREG32_FIELD(CP_ME2_PIPE3_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6617                      enable_flag);
6618
6619         return 0;
6620 }
6621
6622 static int gfx_v8_0_set_sq_int_state(struct amdgpu_device *adev,
6623                                      struct amdgpu_irq_src *source,
6624                                      unsigned int type,
6625                                      enum amdgpu_interrupt_state state)
6626 {
6627         int enable_flag;
6628
6629         switch (state) {
6630         case AMDGPU_IRQ_STATE_DISABLE:
6631                 enable_flag = 1;
6632                 break;
6633
6634         case AMDGPU_IRQ_STATE_ENABLE:
6635                 enable_flag = 0;
6636                 break;
6637
6638         default:
6639                 return -EINVAL;
6640         }
6641
6642         WREG32_FIELD(SQ_INTERRUPT_MSG_CTRL, STALL,
6643                      enable_flag);
6644
6645         return 0;
6646 }
6647
6648 static int gfx_v8_0_eop_irq(struct amdgpu_device *adev,
6649                             struct amdgpu_irq_src *source,
6650                             struct amdgpu_iv_entry *entry)
6651 {
6652         int i;
6653         u8 me_id, pipe_id, queue_id;
6654         struct amdgpu_ring *ring;
6655
6656         DRM_DEBUG("IH: CP EOP\n");
6657         me_id = (entry->ring_id & 0x0c) >> 2;
6658         pipe_id = (entry->ring_id & 0x03) >> 0;
6659         queue_id = (entry->ring_id & 0x70) >> 4;
6660
6661         switch (me_id) {
6662         case 0:
6663                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
6664                 break;
6665         case 1:
6666         case 2:
6667                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6668                         ring = &adev->gfx.compute_ring[i];
6669                         /* Per-queue interrupt is supported for MEC starting from VI.
6670                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
6671                           */
6672                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
6673                                 amdgpu_fence_process(ring);
6674                 }
6675                 break;
6676         }
6677         return 0;
6678 }
6679
6680 static void gfx_v8_0_fault(struct amdgpu_device *adev,
6681                            struct amdgpu_iv_entry *entry)
6682 {
6683         u8 me_id, pipe_id, queue_id;
6684         struct amdgpu_ring *ring;
6685         int i;
6686
6687         me_id = (entry->ring_id & 0x0c) >> 2;
6688         pipe_id = (entry->ring_id & 0x03) >> 0;
6689         queue_id = (entry->ring_id & 0x70) >> 4;
6690
6691         switch (me_id) {
6692         case 0:
6693                 drm_sched_fault(&adev->gfx.gfx_ring[0].sched);
6694                 break;
6695         case 1:
6696         case 2:
6697                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6698                         ring = &adev->gfx.compute_ring[i];
6699                         if (ring->me == me_id && ring->pipe == pipe_id &&
6700                             ring->queue == queue_id)
6701                                 drm_sched_fault(&ring->sched);
6702                 }
6703                 break;
6704         }
6705 }
6706
6707 static int gfx_v8_0_priv_reg_irq(struct amdgpu_device *adev,
6708                                  struct amdgpu_irq_src *source,
6709                                  struct amdgpu_iv_entry *entry)
6710 {
6711         DRM_ERROR("Illegal register access in command stream\n");
6712         gfx_v8_0_fault(adev, entry);
6713         return 0;
6714 }
6715
6716 static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev,
6717                                   struct amdgpu_irq_src *source,
6718                                   struct amdgpu_iv_entry *entry)
6719 {
6720         DRM_ERROR("Illegal instruction in command stream\n");
6721         gfx_v8_0_fault(adev, entry);
6722         return 0;
6723 }
6724
6725 static int gfx_v8_0_cp_ecc_error_irq(struct amdgpu_device *adev,
6726                                      struct amdgpu_irq_src *source,
6727                                      struct amdgpu_iv_entry *entry)
6728 {
6729         DRM_ERROR("CP EDC/ECC error detected.");
6730         return 0;
6731 }
6732
6733 static void gfx_v8_0_parse_sq_irq(struct amdgpu_device *adev, unsigned ih_data)
6734 {
6735         u32 enc, se_id, sh_id, cu_id;
6736         char type[20];
6737         int sq_edc_source = -1;
6738
6739         enc = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, ENCODING);
6740         se_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, SE_ID);
6741
6742         switch (enc) {
6743                 case 0:
6744                         DRM_INFO("SQ general purpose intr detected:"
6745                                         "se_id %d, immed_overflow %d, host_reg_overflow %d,"
6746                                         "host_cmd_overflow %d, cmd_timestamp %d,"
6747                                         "reg_timestamp %d, thread_trace_buff_full %d,"
6748                                         "wlt %d, thread_trace %d.\n",
6749                                         se_id,
6750                                         REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, IMMED_OVERFLOW),
6751                                         REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, HOST_REG_OVERFLOW),
6752                                         REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, HOST_CMD_OVERFLOW),
6753                                         REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, CMD_TIMESTAMP),
6754                                         REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, REG_TIMESTAMP),
6755                                         REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, THREAD_TRACE_BUF_FULL),
6756                                         REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, WLT),
6757                                         REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, THREAD_TRACE)
6758                                         );
6759                         break;
6760                 case 1:
6761                 case 2:
6762
6763                         cu_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, CU_ID);
6764                         sh_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, SH_ID);
6765
6766                         /*
6767                          * This function can be called either directly from ISR
6768                          * or from BH in which case we can access SQ_EDC_INFO
6769                          * instance
6770                          */
6771                         if (in_task()) {
6772                                 mutex_lock(&adev->grbm_idx_mutex);
6773                                 gfx_v8_0_select_se_sh(adev, se_id, sh_id, cu_id);
6774
6775                                 sq_edc_source = REG_GET_FIELD(RREG32(mmSQ_EDC_INFO), SQ_EDC_INFO, SOURCE);
6776
6777                                 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
6778                                 mutex_unlock(&adev->grbm_idx_mutex);
6779                         }
6780
6781                         if (enc == 1)
6782                                 sprintf(type, "instruction intr");
6783                         else
6784                                 sprintf(type, "EDC/ECC error");
6785
6786                         DRM_INFO(
6787                                 "SQ %s detected: "
6788                                         "se_id %d, sh_id %d, cu_id %d, simd_id %d, wave_id %d, vm_id %d "
6789                                         "trap %s, sq_ed_info.source %s.\n",
6790                                         type, se_id, sh_id, cu_id,
6791                                         REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, SIMD_ID),
6792                                         REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, WAVE_ID),
6793                                         REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, VM_ID),
6794                                         REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, PRIV) ? "true" : "false",
6795                                         (sq_edc_source != -1) ? sq_edc_source_names[sq_edc_source] : "unavailable"
6796                                 );
6797                         break;
6798                 default:
6799                         DRM_ERROR("SQ invalid encoding type\n.");
6800         }
6801 }
6802
6803 static void gfx_v8_0_sq_irq_work_func(struct work_struct *work)
6804 {
6805
6806         struct amdgpu_device *adev = container_of(work, struct amdgpu_device, gfx.sq_work.work);
6807         struct sq_work *sq_work = container_of(work, struct sq_work, work);
6808
6809         gfx_v8_0_parse_sq_irq(adev, sq_work->ih_data);
6810 }
6811
6812 static int gfx_v8_0_sq_irq(struct amdgpu_device *adev,
6813                            struct amdgpu_irq_src *source,
6814                            struct amdgpu_iv_entry *entry)
6815 {
6816         unsigned ih_data = entry->src_data[0];
6817
6818         /*
6819          * Try to submit work so SQ_EDC_INFO can be accessed from
6820          * BH. If previous work submission hasn't finished yet
6821          * just print whatever info is possible directly from the ISR.
6822          */
6823         if (work_pending(&adev->gfx.sq_work.work)) {
6824                 gfx_v8_0_parse_sq_irq(adev, ih_data);
6825         } else {
6826                 adev->gfx.sq_work.ih_data = ih_data;
6827                 schedule_work(&adev->gfx.sq_work.work);
6828         }
6829
6830         return 0;
6831 }
6832
6833 static const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
6834         .name = "gfx_v8_0",
6835         .early_init = gfx_v8_0_early_init,
6836         .late_init = gfx_v8_0_late_init,
6837         .sw_init = gfx_v8_0_sw_init,
6838         .sw_fini = gfx_v8_0_sw_fini,
6839         .hw_init = gfx_v8_0_hw_init,
6840         .hw_fini = gfx_v8_0_hw_fini,
6841         .suspend = gfx_v8_0_suspend,
6842         .resume = gfx_v8_0_resume,
6843         .is_idle = gfx_v8_0_is_idle,
6844         .wait_for_idle = gfx_v8_0_wait_for_idle,
6845         .check_soft_reset = gfx_v8_0_check_soft_reset,
6846         .pre_soft_reset = gfx_v8_0_pre_soft_reset,
6847         .soft_reset = gfx_v8_0_soft_reset,
6848         .post_soft_reset = gfx_v8_0_post_soft_reset,
6849         .set_clockgating_state = gfx_v8_0_set_clockgating_state,
6850         .set_powergating_state = gfx_v8_0_set_powergating_state,
6851         .get_clockgating_state = gfx_v8_0_get_clockgating_state,
6852 };
6853
6854 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
6855         .type = AMDGPU_RING_TYPE_GFX,
6856         .align_mask = 0xff,
6857         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6858         .support_64bit_ptrs = false,
6859         .get_rptr = gfx_v8_0_ring_get_rptr,
6860         .get_wptr = gfx_v8_0_ring_get_wptr_gfx,
6861         .set_wptr = gfx_v8_0_ring_set_wptr_gfx,
6862         .emit_frame_size = /* maximum 215dw if count 16 IBs in */
6863                 5 +  /* COND_EXEC */
6864                 7 +  /* PIPELINE_SYNC */
6865                 VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 9 + /* VM_FLUSH */
6866                 8 +  /* FENCE for VM_FLUSH */
6867                 20 + /* GDS switch */
6868                 4 + /* double SWITCH_BUFFER,
6869                        the first COND_EXEC jump to the place just
6870                            prior to this double SWITCH_BUFFER  */
6871                 5 + /* COND_EXEC */
6872                 7 +      /*     HDP_flush */
6873                 4 +      /*     VGT_flush */
6874                 14 + /* CE_META */
6875                 31 + /* DE_META */
6876                 3 + /* CNTX_CTRL */
6877                 5 + /* HDP_INVL */
6878                 8 + 8 + /* FENCE x2 */
6879                 2, /* SWITCH_BUFFER */
6880         .emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_gfx */
6881         .emit_ib = gfx_v8_0_ring_emit_ib_gfx,
6882         .emit_fence = gfx_v8_0_ring_emit_fence_gfx,
6883         .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
6884         .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
6885         .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
6886         .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
6887         .test_ring = gfx_v8_0_ring_test_ring,
6888         .test_ib = gfx_v8_0_ring_test_ib,
6889         .insert_nop = amdgpu_ring_insert_nop,
6890         .pad_ib = amdgpu_ring_generic_pad_ib,
6891         .emit_switch_buffer = gfx_v8_ring_emit_sb,
6892         .emit_cntxcntl = gfx_v8_ring_emit_cntxcntl,
6893         .init_cond_exec = gfx_v8_0_ring_emit_init_cond_exec,
6894         .patch_cond_exec = gfx_v8_0_ring_emit_patch_cond_exec,
6895         .emit_wreg = gfx_v8_0_ring_emit_wreg,
6896         .soft_recovery = gfx_v8_0_ring_soft_recovery,
6897 };
6898
6899 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
6900         .type = AMDGPU_RING_TYPE_COMPUTE,
6901         .align_mask = 0xff,
6902         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6903         .support_64bit_ptrs = false,
6904         .get_rptr = gfx_v8_0_ring_get_rptr,
6905         .get_wptr = gfx_v8_0_ring_get_wptr_compute,
6906         .set_wptr = gfx_v8_0_ring_set_wptr_compute,
6907         .emit_frame_size =
6908                 20 + /* gfx_v8_0_ring_emit_gds_switch */
6909                 7 + /* gfx_v8_0_ring_emit_hdp_flush */
6910                 5 + /* hdp_invalidate */
6911                 7 + /* gfx_v8_0_ring_emit_pipeline_sync */
6912                 VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v8_0_ring_emit_vm_flush */
6913                 7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_compute x3 for user fence, vm fence */
6914         .emit_ib_size = 7, /* gfx_v8_0_ring_emit_ib_compute */
6915         .emit_ib = gfx_v8_0_ring_emit_ib_compute,
6916         .emit_fence = gfx_v8_0_ring_emit_fence_compute,
6917         .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
6918         .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
6919         .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
6920         .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
6921         .test_ring = gfx_v8_0_ring_test_ring,
6922         .test_ib = gfx_v8_0_ring_test_ib,
6923         .insert_nop = amdgpu_ring_insert_nop,
6924         .pad_ib = amdgpu_ring_generic_pad_ib,
6925         .set_priority = gfx_v8_0_ring_set_priority_compute,
6926         .emit_wreg = gfx_v8_0_ring_emit_wreg,
6927 };
6928
6929 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_kiq = {
6930         .type = AMDGPU_RING_TYPE_KIQ,
6931         .align_mask = 0xff,
6932         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6933         .support_64bit_ptrs = false,
6934         .get_rptr = gfx_v8_0_ring_get_rptr,
6935         .get_wptr = gfx_v8_0_ring_get_wptr_compute,
6936         .set_wptr = gfx_v8_0_ring_set_wptr_compute,
6937         .emit_frame_size =
6938                 20 + /* gfx_v8_0_ring_emit_gds_switch */
6939                 7 + /* gfx_v8_0_ring_emit_hdp_flush */
6940                 5 + /* hdp_invalidate */
6941                 7 + /* gfx_v8_0_ring_emit_pipeline_sync */
6942                 17 + /* gfx_v8_0_ring_emit_vm_flush */
6943                 7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_kiq x3 for user fence, vm fence */
6944         .emit_ib_size = 7, /* gfx_v8_0_ring_emit_ib_compute */
6945         .emit_fence = gfx_v8_0_ring_emit_fence_kiq,
6946         .test_ring = gfx_v8_0_ring_test_ring,
6947         .insert_nop = amdgpu_ring_insert_nop,
6948         .pad_ib = amdgpu_ring_generic_pad_ib,
6949         .emit_rreg = gfx_v8_0_ring_emit_rreg,
6950         .emit_wreg = gfx_v8_0_ring_emit_wreg,
6951 };
6952
6953 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev)
6954 {
6955         int i;
6956
6957         adev->gfx.kiq.ring.funcs = &gfx_v8_0_ring_funcs_kiq;
6958
6959         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6960                 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx;
6961
6962         for (i = 0; i < adev->gfx.num_compute_rings; i++)
6963                 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute;
6964 }
6965
6966 static const struct amdgpu_irq_src_funcs gfx_v8_0_eop_irq_funcs = {
6967         .set = gfx_v8_0_set_eop_interrupt_state,
6968         .process = gfx_v8_0_eop_irq,
6969 };
6970
6971 static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_reg_irq_funcs = {
6972         .set = gfx_v8_0_set_priv_reg_fault_state,
6973         .process = gfx_v8_0_priv_reg_irq,
6974 };
6975
6976 static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_inst_irq_funcs = {
6977         .set = gfx_v8_0_set_priv_inst_fault_state,
6978         .process = gfx_v8_0_priv_inst_irq,
6979 };
6980
6981 static const struct amdgpu_irq_src_funcs gfx_v8_0_cp_ecc_error_irq_funcs = {
6982         .set = gfx_v8_0_set_cp_ecc_int_state,
6983         .process = gfx_v8_0_cp_ecc_error_irq,
6984 };
6985
6986 static const struct amdgpu_irq_src_funcs gfx_v8_0_sq_irq_funcs = {
6987         .set = gfx_v8_0_set_sq_int_state,
6988         .process = gfx_v8_0_sq_irq,
6989 };
6990
6991 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev)
6992 {
6993         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
6994         adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs;
6995
6996         adev->gfx.priv_reg_irq.num_types = 1;
6997         adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs;
6998
6999         adev->gfx.priv_inst_irq.num_types = 1;
7000         adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs;
7001
7002         adev->gfx.cp_ecc_error_irq.num_types = 1;
7003         adev->gfx.cp_ecc_error_irq.funcs = &gfx_v8_0_cp_ecc_error_irq_funcs;
7004
7005         adev->gfx.sq_irq.num_types = 1;
7006         adev->gfx.sq_irq.funcs = &gfx_v8_0_sq_irq_funcs;
7007 }
7008
7009 static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev)
7010 {
7011         adev->gfx.rlc.funcs = &iceland_rlc_funcs;
7012 }
7013
7014 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev)
7015 {
7016         /* init asci gds info */
7017         adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
7018         adev->gds.gws.total_size = 64;
7019         adev->gds.oa.total_size = 16;
7020         adev->gds.gds_compute_max_wave_id = RREG32(mmGDS_COMPUTE_MAX_WAVE_ID);
7021
7022         if (adev->gds.mem.total_size == 64 * 1024) {
7023                 adev->gds.mem.gfx_partition_size = 4096;
7024                 adev->gds.mem.cs_partition_size = 4096;
7025
7026                 adev->gds.gws.gfx_partition_size = 4;
7027                 adev->gds.gws.cs_partition_size = 4;
7028
7029                 adev->gds.oa.gfx_partition_size = 4;
7030                 adev->gds.oa.cs_partition_size = 1;
7031         } else {
7032                 adev->gds.mem.gfx_partition_size = 1024;
7033                 adev->gds.mem.cs_partition_size = 1024;
7034
7035                 adev->gds.gws.gfx_partition_size = 16;
7036                 adev->gds.gws.cs_partition_size = 16;
7037
7038                 adev->gds.oa.gfx_partition_size = 4;
7039                 adev->gds.oa.cs_partition_size = 4;
7040         }
7041 }
7042
7043 static void gfx_v8_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
7044                                                  u32 bitmap)
7045 {
7046         u32 data;
7047
7048         if (!bitmap)
7049                 return;
7050
7051         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
7052         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
7053
7054         WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
7055 }
7056
7057 static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev)
7058 {
7059         u32 data, mask;
7060
7061         data =  RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |
7062                 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
7063
7064         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
7065
7066         return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask;
7067 }
7068
7069 static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev)
7070 {
7071         int i, j, k, counter, active_cu_number = 0;
7072         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
7073         struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
7074         unsigned disable_masks[4 * 2];
7075         u32 ao_cu_num;
7076
7077         memset(cu_info, 0, sizeof(*cu_info));
7078
7079         if (adev->flags & AMD_IS_APU)
7080                 ao_cu_num = 2;
7081         else
7082                 ao_cu_num = adev->gfx.config.max_cu_per_sh;
7083
7084         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
7085
7086         mutex_lock(&adev->grbm_idx_mutex);
7087         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
7088                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
7089                         mask = 1;
7090                         ao_bitmap = 0;
7091                         counter = 0;
7092                         gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff);
7093                         if (i < 4 && j < 2)
7094                                 gfx_v8_0_set_user_cu_inactive_bitmap(
7095                                         adev, disable_masks[i * 2 + j]);
7096                         bitmap = gfx_v8_0_get_cu_active_bitmap(adev);
7097                         cu_info->bitmap[i][j] = bitmap;
7098
7099                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
7100                                 if (bitmap & mask) {
7101                                         if (counter < ao_cu_num)
7102                                                 ao_bitmap |= mask;
7103                                         counter ++;
7104                                 }
7105                                 mask <<= 1;
7106                         }
7107                         active_cu_number += counter;
7108                         if (i < 2 && j < 2)
7109                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
7110                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
7111                 }
7112         }
7113         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
7114         mutex_unlock(&adev->grbm_idx_mutex);
7115
7116         cu_info->number = active_cu_number;
7117         cu_info->ao_cu_mask = ao_cu_mask;
7118         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
7119         cu_info->max_waves_per_simd = 10;
7120         cu_info->max_scratch_slots_per_cu = 32;
7121         cu_info->wave_front_size = 64;
7122         cu_info->lds_size = 64;
7123 }
7124
7125 const struct amdgpu_ip_block_version gfx_v8_0_ip_block =
7126 {
7127         .type = AMD_IP_BLOCK_TYPE_GFX,
7128         .major = 8,
7129         .minor = 0,
7130         .rev = 0,
7131         .funcs = &gfx_v8_0_ip_funcs,
7132 };
7133
7134 const struct amdgpu_ip_block_version gfx_v8_1_ip_block =
7135 {
7136         .type = AMD_IP_BLOCK_TYPE_GFX,
7137         .major = 8,
7138         .minor = 1,
7139         .rev = 0,
7140         .funcs = &gfx_v8_0_ip_funcs,
7141 };
7142
7143 static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
7144 {
7145         uint64_t ce_payload_addr;
7146         int cnt_ce;
7147         union {
7148                 struct vi_ce_ib_state regular;
7149                 struct vi_ce_ib_state_chained_ib chained;
7150         } ce_payload = {};
7151
7152         if (ring->adev->virt.chained_ib_support) {
7153                 ce_payload_addr = amdgpu_csa_vaddr(ring->adev) +
7154                         offsetof(struct vi_gfx_meta_data_chained_ib, ce_payload);
7155                 cnt_ce = (sizeof(ce_payload.chained) >> 2) + 4 - 2;
7156         } else {
7157                 ce_payload_addr = amdgpu_csa_vaddr(ring->adev) +
7158                         offsetof(struct vi_gfx_meta_data, ce_payload);
7159                 cnt_ce = (sizeof(ce_payload.regular) >> 2) + 4 - 2;
7160         }
7161
7162         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt_ce));
7163         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
7164                                 WRITE_DATA_DST_SEL(8) |
7165                                 WR_CONFIRM) |
7166                                 WRITE_DATA_CACHE_POLICY(0));
7167         amdgpu_ring_write(ring, lower_32_bits(ce_payload_addr));
7168         amdgpu_ring_write(ring, upper_32_bits(ce_payload_addr));
7169         amdgpu_ring_write_multiple(ring, (void *)&ce_payload, cnt_ce - 2);
7170 }
7171
7172 static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring)
7173 {
7174         uint64_t de_payload_addr, gds_addr, csa_addr;
7175         int cnt_de;
7176         union {
7177                 struct vi_de_ib_state regular;
7178                 struct vi_de_ib_state_chained_ib chained;
7179         } de_payload = {};
7180
7181         csa_addr = amdgpu_csa_vaddr(ring->adev);
7182         gds_addr = csa_addr + 4096;
7183         if (ring->adev->virt.chained_ib_support) {
7184                 de_payload.chained.gds_backup_addrlo = lower_32_bits(gds_addr);
7185                 de_payload.chained.gds_backup_addrhi = upper_32_bits(gds_addr);
7186                 de_payload_addr = csa_addr + offsetof(struct vi_gfx_meta_data_chained_ib, de_payload);
7187                 cnt_de = (sizeof(de_payload.chained) >> 2) + 4 - 2;
7188         } else {
7189                 de_payload.regular.gds_backup_addrlo = lower_32_bits(gds_addr);
7190                 de_payload.regular.gds_backup_addrhi = upper_32_bits(gds_addr);
7191                 de_payload_addr = csa_addr + offsetof(struct vi_gfx_meta_data, de_payload);
7192                 cnt_de = (sizeof(de_payload.regular) >> 2) + 4 - 2;
7193         }
7194
7195         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt_de));
7196         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
7197                                 WRITE_DATA_DST_SEL(8) |
7198                                 WR_CONFIRM) |
7199                                 WRITE_DATA_CACHE_POLICY(0));
7200         amdgpu_ring_write(ring, lower_32_bits(de_payload_addr));
7201         amdgpu_ring_write(ring, upper_32_bits(de_payload_addr));
7202         amdgpu_ring_write_multiple(ring, (void *)&de_payload, cnt_de - 2);
7203 }