drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_vcn.h"
  28 #include "amdgpu_pm.h"
  29 #include "soc15.h"
  30 #include "soc15d.h"
  31 #include "vcn_v2_0.h"
  32 #include "mmsch_v1_0.h"
  33
  34 #include "vcn/vcn_2_5_offset.h"
  35 #include "vcn/vcn_2_5_sh_mask.h"
  36 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
  37
  38 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET                        0x27
  39 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET                    0x0f
  40 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET                  0x10
  41 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET                  0x11
  42 #define mmUVD_NO_OP_INTERNAL_OFFSET                             0x29
  43 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET                       0x66
  44 #define mmUVD_SCRATCH9_INTERNAL_OFFSET                          0xc01d
  45
  46 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET                   0x431
  47 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET          0x3b4
  48 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET         0x3b5
  49 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET                       0x25c
  50
  51 #define VCN25_MAX_HW_INSTANCES_ARCTURUS                 2
  52
  53 static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
  54 static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev);
  55 static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev);
  56 static int vcn_v2_5_set_powergating_state(void *handle,
  57                                 enum amd_powergating_state state);
  58 static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
  59                                 int inst_idx, struct dpg_pause_state *new_state);
  60 static int vcn_v2_5_sriov_start(struct amdgpu_device *adev);
  61
  62 static int amdgpu_ih_clientid_vcns[] = {
  63         SOC15_IH_CLIENTID_VCN,
  64         SOC15_IH_CLIENTID_VCN1
  65 };
  66
  67 /**
  68  * vcn_v2_5_early_init - set function pointers
  69  *
  70  * @handle: amdgpu_device pointer
  71  *
  72  * Set ring and irq function pointers
  73  */
  74 static int vcn_v2_5_early_init(void *handle)
  75 {
  76         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  77         if (adev->asic_type == CHIP_ARCTURUS) {
  78                 u32 harvest;
  79                 int i;
  80
  81                 adev->vcn.num_vcn_inst = VCN25_MAX_HW_INSTANCES_ARCTURUS;
  82                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
  83                         harvest = RREG32_SOC15(UVD, i, mmCC_UVD_HARVESTING);
  84                         if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
  85                                 adev->vcn.harvest_config |= 1 << i;
  86                 }
  87
  88                 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 |
  89                                                  AMDGPU_VCN_HARVEST_VCN1))
  90                         /* both instances are harvested, disable the block */
  91                         return -ENOENT;
  92         } else
  93                 adev->vcn.num_vcn_inst = 1;
  94
  95         if (amdgpu_sriov_vf(adev)) {
  96                 adev->vcn.num_vcn_inst = 2;
  97                 adev->vcn.harvest_config = 0;
  98                 adev->vcn.num_enc_rings = 1;
  99         } else {
 100                 adev->vcn.num_enc_rings = 2;
 101         }
 102
 103         vcn_v2_5_set_dec_ring_funcs(adev);
 104         vcn_v2_5_set_enc_ring_funcs(adev);
 105         vcn_v2_5_set_irq_funcs(adev);
 106
 107         return 0;
 108 }
 109
 110 /**
 111  * vcn_v2_5_sw_init - sw init for VCN block
 112  *
 113  * @handle: amdgpu_device pointer
 114  *
 115  * Load firmware and sw initialization
 116  */
 117 static int vcn_v2_5_sw_init(void *handle)
 118 {
 119         struct amdgpu_ring *ring;
 120         int i, j, r;
 121         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 122
 123         for (j = 0; j < adev->vcn.num_vcn_inst; j++) {
 124                 if (adev->vcn.harvest_config & (1 << j))
 125                         continue;
 126                 /* VCN DEC TRAP */
 127                 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
 128                                 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[j].irq);
 129                 if (r)
 130                         return r;
 131
 132                 /* VCN ENC TRAP */
 133                 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 134                         r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
 135                                 i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[j].irq);
 136                         if (r)
 137                                 return r;
 138                 }
 139         }
 140
 141         r = amdgpu_vcn_sw_init(adev);
 142         if (r)
 143                 return r;
 144
 145         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 146                 const struct common_firmware_header *hdr;
 147                 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
 148                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
 149                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
 150                 adev->firmware.fw_size +=
 151                         ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
 152
 153                 if (adev->vcn.num_vcn_inst == VCN25_MAX_HW_INSTANCES_ARCTURUS) {
 154                         adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].ucode_id = AMDGPU_UCODE_ID_VCN1;
 155                         adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].fw = adev->vcn.fw;
 156                         adev->firmware.fw_size +=
 157                                 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
 158                 }
 159                 DRM_INFO("PSP loading VCN firmware\n");
 160         }
 161
 162         r = amdgpu_vcn_resume(adev);
 163         if (r)
 164                 return r;
 165
 166         for (j = 0; j < adev->vcn.num_vcn_inst; j++) {
 167                 if (adev->vcn.harvest_config & (1 << j))
 168                         continue;
 169                 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
 170                 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
 171                 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
 172                 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
 173                 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
 174                 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
 175
 176                 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
 177                 adev->vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(UVD, j, mmUVD_SCRATCH9);
 178                 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
 179                 adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(UVD, j, mmUVD_GPCOM_VCPU_DATA0);
 180                 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
 181                 adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(UVD, j, mmUVD_GPCOM_VCPU_DATA1);
 182                 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
 183                 adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(UVD, j, mmUVD_GPCOM_VCPU_CMD);
 184                 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
 185                 adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(UVD, j, mmUVD_NO_OP);
 186
 187                 ring = &adev->vcn.inst[j].ring_dec;
 188                 ring->use_doorbell = true;
 189
 190                 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
 191                                 (amdgpu_sriov_vf(adev) ? 2*j : 8*j);
 192                 sprintf(ring->name, "vcn_dec_%d", j);
 193                 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq, 0);
 194                 if (r)
 195                         return r;
 196
 197                 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 198                         ring = &adev->vcn.inst[j].ring_enc[i];
 199                         ring->use_doorbell = true;
 200
 201                         ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
 202                                         (amdgpu_sriov_vf(adev) ? (1 + i + 2*j) : (2 + i + 8*j));
 203
 204                         sprintf(ring->name, "vcn_enc_%d.%d", j, i);
 205                         r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq, 0);
 206                         if (r)
 207                                 return r;
 208                 }
 209         }
 210
 211         if (amdgpu_sriov_vf(adev)) {
 212                 r = amdgpu_virt_alloc_mm_table(adev);
 213                 if (r)
 214                         return r;
 215         }
 216
 217         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
 218                 adev->vcn.pause_dpg_mode = vcn_v2_5_pause_dpg_mode;
 219
 220         return 0;
 221 }
 222
 223 /**
 224  * vcn_v2_5_sw_fini - sw fini for VCN block
 225  *
 226  * @handle: amdgpu_device pointer
 227  *
 228  * VCN suspend and free up sw allocation
 229  */
 230 static int vcn_v2_5_sw_fini(void *handle)
 231 {
 232         int r;
 233         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 234
 235         if (amdgpu_sriov_vf(adev))
 236                 amdgpu_virt_free_mm_table(adev);
 237
 238         r = amdgpu_vcn_suspend(adev);
 239         if (r)
 240                 return r;
 241
 242         r = amdgpu_vcn_sw_fini(adev);
 243
 244         return r;
 245 }
 246
 247 /**
 248  * vcn_v2_5_hw_init - start and test VCN block
 249  *
 250  * @handle: amdgpu_device pointer
 251  *
 252  * Initialize the hardware, boot up the VCPU and do some testing
 253  */
 254 static int vcn_v2_5_hw_init(void *handle)
 255 {
 256         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 257         struct amdgpu_ring *ring;
 258         int i, j, r = 0;
 259
 260         if (amdgpu_sriov_vf(adev))
 261                 r = vcn_v2_5_sriov_start(adev);
 262
 263         for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
 264                 if (adev->vcn.harvest_config & (1 << j))
 265                         continue;
 266
 267                 if (amdgpu_sriov_vf(adev)) {
 268                         adev->vcn.inst[j].ring_enc[0].sched.ready = true;
 269                         adev->vcn.inst[j].ring_enc[1].sched.ready = false;
 270                         adev->vcn.inst[j].ring_enc[2].sched.ready = false;
 271                         adev->vcn.inst[j].ring_dec.sched.ready = true;
 272                 } else {
 273
 274                         ring = &adev->vcn.inst[j].ring_dec;
 275
 276                         adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
 277                                                      ring->doorbell_index, j);
 278
 279                         r = amdgpu_ring_test_helper(ring);
 280                         if (r)
 281                                 goto done;
 282
 283                         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 284                                 ring = &adev->vcn.inst[j].ring_enc[i];
 285                                 r = amdgpu_ring_test_helper(ring);
 286                                 if (r)
 287                                         goto done;
 288                         }
 289                 }
 290         }
 291
 292 done:
 293         if (!r)
 294                 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
 295                         (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
 296
 297         return r;
 298 }
 299
 300 /**
 301  * vcn_v2_5_hw_fini - stop the hardware block
 302  *
 303  * @handle: amdgpu_device pointer
 304  *
 305  * Stop the VCN block, mark ring as not ready any more
 306  */
 307 static int vcn_v2_5_hw_fini(void *handle)
 308 {
 309         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 310         struct amdgpu_ring *ring;
 311         int i, j;
 312
 313         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 314                 if (adev->vcn.harvest_config & (1 << i))
 315                         continue;
 316                 ring = &adev->vcn.inst[i].ring_dec;
 317
 318                 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
 319                     (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
 320                      RREG32_SOC15(VCN, i, mmUVD_STATUS)))
 321                         vcn_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
 322
 323                 ring->sched.ready = false;
 324
 325                 for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
 326                         ring = &adev->vcn.inst[i].ring_enc[j];
 327                         ring->sched.ready = false;
 328                 }
 329         }
 330
 331         return 0;
 332 }
 333
 334 /**
 335  * vcn_v2_5_suspend - suspend VCN block
 336  *
 337  * @handle: amdgpu_device pointer
 338  *
 339  * HW fini and suspend VCN block
 340  */
 341 static int vcn_v2_5_suspend(void *handle)
 342 {
 343         int r;
 344         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 345
 346         r = vcn_v2_5_hw_fini(adev);
 347         if (r)
 348                 return r;
 349
 350         r = amdgpu_vcn_suspend(adev);
 351
 352         return r;
 353 }
 354
 355 /**
 356  * vcn_v2_5_resume - resume VCN block
 357  *
 358  * @handle: amdgpu_device pointer
 359  *
 360  * Resume firmware and hw init VCN block
 361  */
 362 static int vcn_v2_5_resume(void *handle)
 363 {
 364         int r;
 365         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 366
 367         r = amdgpu_vcn_resume(adev);
 368         if (r)
 369                 return r;
 370
 371         r = vcn_v2_5_hw_init(adev);
 372
 373         return r;
 374 }
 375
 376 /**
 377  * vcn_v2_5_mc_resume - memory controller programming
 378  *
 379  * @adev: amdgpu_device pointer
 380  *
 381  * Let the VCN memory controller know it's offsets
 382  */
 383 static void vcn_v2_5_mc_resume(struct amdgpu_device *adev)
 384 {
 385         uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
 386         uint32_t offset;
 387         int i;
 388
 389         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 390                 if (adev->vcn.harvest_config & (1 << i))
 391                         continue;
 392                 /* cache window 0: fw */
 393                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 394                         WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 395                                 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo));
 396                         WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 397                                 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi));
 398                         WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0);
 399                         offset = 0;
 400                 } else {
 401                         WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 402                                 lower_32_bits(adev->vcn.inst[i].gpu_addr));
 403                         WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 404                                 upper_32_bits(adev->vcn.inst[i].gpu_addr));
 405                         offset = size;
 406                         WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0,
 407                                 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 408                 }
 409                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size);
 410
 411                 /* cache window 1: stack */
 412                 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 413                         lower_32_bits(adev->vcn.inst[i].gpu_addr + offset));
 414                 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 415                         upper_32_bits(adev->vcn.inst[i].gpu_addr + offset));
 416                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET1, 0);
 417                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
 418
 419                 /* cache window 2: context */
 420                 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 421                         lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 422                 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 423                         upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 424                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET2, 0);
 425                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
 426         }
 427 }
 428
 429 static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
 430 {
 431         uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
 432         uint32_t offset;
 433
 434         /* cache window 0: fw */
 435         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 436                 if (!indirect) {
 437                         WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 438                                 UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 439                                 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);
 440                         WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 441                                 UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 442                                 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);
 443                         WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 444                                 UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
 445                 } else {
 446                         WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 447                                 UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
 448                         WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 449                                 UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
 450                         WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 451                                 UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
 452                 }
 453                 offset = 0;
 454         } else {
 455                 WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 456                         UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 457                         lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
 458                 WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 459                         UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 460                         upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
 461                 offset = size;
 462                 WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 463                         UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET0),
 464                         AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
 465         }
 466
 467         if (!indirect)
 468                 WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 469                         UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
 470         else
 471                 WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 472                         UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
 473
 474         /* cache window 1: stack */
 475         if (!indirect) {
 476                 WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 477                         UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
 478                         lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
 479                 WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 480                         UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
 481                         upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
 482                 WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 483                         UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
 484         } else {
 485                 WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 486                         UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
 487                 WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 488                         UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
 489                 WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 490                         UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
 491         }
 492         WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 493                 UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
 494
 495         /* cache window 2: context */
 496         WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 497                 UVD, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
 498                 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
 499         WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 500                 UVD, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
 501                 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
 502         WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 503                 UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
 504         WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 505                 UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
 506
 507         /* non-cache window */
 508         WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 509                 UVD, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
 510         WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 511                 UVD, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
 512         WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 513                 UVD, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
 514         WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 515                 UVD, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
 516
 517         /* VCN global tiling registers */
 518         WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 519                 UVD, inst_idx, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
 520 }
 521
 522 /**
 523  * vcn_v2_5_disable_clock_gating - disable VCN clock gating
 524  *
 525  * @adev: amdgpu_device pointer
 526  *
 527  * Disable clock gating for VCN block
 528  */
 529 static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev)
 530 {
 531         uint32_t data;
 532         int ret = 0;
 533         int i;
 534
 535         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 536                 if (adev->vcn.harvest_config & (1 << i))
 537                         continue;
 538                 /* UVD disable CGC */
 539                 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
 540                 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 541                         data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 542                 else
 543                         data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 544                 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 545                 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 546                 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
 547
 548                 data = RREG32_SOC15(VCN, i, mmUVD_CGC_GATE);
 549                 data &= ~(UVD_CGC_GATE__SYS_MASK
 550                         | UVD_CGC_GATE__UDEC_MASK
 551                         | UVD_CGC_GATE__MPEG2_MASK
 552                         | UVD_CGC_GATE__REGS_MASK
 553                         | UVD_CGC_GATE__RBC_MASK
 554                         | UVD_CGC_GATE__LMI_MC_MASK
 555                         | UVD_CGC_GATE__LMI_UMC_MASK
 556                         | UVD_CGC_GATE__IDCT_MASK
 557                         | UVD_CGC_GATE__MPRD_MASK
 558                         | UVD_CGC_GATE__MPC_MASK
 559                         | UVD_CGC_GATE__LBSI_MASK
 560                         | UVD_CGC_GATE__LRBBM_MASK
 561                         | UVD_CGC_GATE__UDEC_RE_MASK
 562                         | UVD_CGC_GATE__UDEC_CM_MASK
 563                         | UVD_CGC_GATE__UDEC_IT_MASK
 564                         | UVD_CGC_GATE__UDEC_DB_MASK
 565                         | UVD_CGC_GATE__UDEC_MP_MASK
 566                         | UVD_CGC_GATE__WCB_MASK
 567                         | UVD_CGC_GATE__VCPU_MASK
 568                         | UVD_CGC_GATE__MMSCH_MASK);
 569
 570                 WREG32_SOC15(VCN, i, mmUVD_CGC_GATE, data);
 571
 572                 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0,  0xFFFFFFFF, ret);
 573
 574                 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
 575                 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 576                         | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 577                         | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 578                         | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 579                         | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 580                         | UVD_CGC_CTRL__SYS_MODE_MASK
 581                         | UVD_CGC_CTRL__UDEC_MODE_MASK
 582                         | UVD_CGC_CTRL__MPEG2_MODE_MASK
 583                         | UVD_CGC_CTRL__REGS_MODE_MASK
 584                         | UVD_CGC_CTRL__RBC_MODE_MASK
 585                         | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 586                         | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 587                         | UVD_CGC_CTRL__IDCT_MODE_MASK
 588                         | UVD_CGC_CTRL__MPRD_MODE_MASK
 589                         | UVD_CGC_CTRL__MPC_MODE_MASK
 590                         | UVD_CGC_CTRL__LBSI_MODE_MASK
 591                         | UVD_CGC_CTRL__LRBBM_MODE_MASK
 592                         | UVD_CGC_CTRL__WCB_MODE_MASK
 593                         | UVD_CGC_CTRL__VCPU_MODE_MASK
 594                         | UVD_CGC_CTRL__MMSCH_MODE_MASK);
 595                 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
 596
 597                 /* turn on */
 598                 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE);
 599                 data |= (UVD_SUVD_CGC_GATE__SRE_MASK
 600                         | UVD_SUVD_CGC_GATE__SIT_MASK
 601                         | UVD_SUVD_CGC_GATE__SMP_MASK
 602                         | UVD_SUVD_CGC_GATE__SCM_MASK
 603                         | UVD_SUVD_CGC_GATE__SDB_MASK
 604                         | UVD_SUVD_CGC_GATE__SRE_H264_MASK
 605                         | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
 606                         | UVD_SUVD_CGC_GATE__SIT_H264_MASK
 607                         | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
 608                         | UVD_SUVD_CGC_GATE__SCM_H264_MASK
 609                         | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
 610                         | UVD_SUVD_CGC_GATE__SDB_H264_MASK
 611                         | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
 612                         | UVD_SUVD_CGC_GATE__SCLR_MASK
 613                         | UVD_SUVD_CGC_GATE__UVD_SC_MASK
 614                         | UVD_SUVD_CGC_GATE__ENT_MASK
 615                         | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
 616                         | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
 617                         | UVD_SUVD_CGC_GATE__SITE_MASK
 618                         | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
 619                         | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
 620                         | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
 621                         | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
 622                         | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
 623                 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE, data);
 624
 625                 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL);
 626                 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 627                         | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 628                         | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 629                         | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 630                         | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 631                         | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 632                         | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 633                         | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 634                         | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 635                         | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 636                 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data);
 637         }
 638 }
 639
 640 static void vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device *adev,
 641                 uint8_t sram_sel, int inst_idx, uint8_t indirect)
 642 {
 643         uint32_t reg_data = 0;
 644
 645         /* enable sw clock gating control */
 646         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 647                 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 648         else
 649                 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 650         reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 651         reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 652         reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
 653                  UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
 654                  UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
 655                  UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
 656                  UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
 657                  UVD_CGC_CTRL__SYS_MODE_MASK |
 658                  UVD_CGC_CTRL__UDEC_MODE_MASK |
 659                  UVD_CGC_CTRL__MPEG2_MODE_MASK |
 660                  UVD_CGC_CTRL__REGS_MODE_MASK |
 661                  UVD_CGC_CTRL__RBC_MODE_MASK |
 662                  UVD_CGC_CTRL__LMI_MC_MODE_MASK |
 663                  UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
 664                  UVD_CGC_CTRL__IDCT_MODE_MASK |
 665                  UVD_CGC_CTRL__MPRD_MODE_MASK |
 666                  UVD_CGC_CTRL__MPC_MODE_MASK |
 667                  UVD_CGC_CTRL__LBSI_MODE_MASK |
 668                  UVD_CGC_CTRL__LRBBM_MODE_MASK |
 669                  UVD_CGC_CTRL__WCB_MODE_MASK |
 670                  UVD_CGC_CTRL__VCPU_MODE_MASK |
 671                  UVD_CGC_CTRL__MMSCH_MODE_MASK);
 672         WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 673                 UVD, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
 674
 675         /* turn off clock gating */
 676         WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 677                 UVD, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect);
 678
 679         /* turn on SUVD clock gating */
 680         WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 681                 UVD, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
 682
 683         /* turn on sw mode in UVD_SUVD_CGC_CTRL */
 684         WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 685                 UVD, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
 686 }
 687
 688 /**
 689  * vcn_v2_5_enable_clock_gating - enable VCN clock gating
 690  *
 691  * @adev: amdgpu_device pointer
 692  *
 693  * Enable clock gating for VCN block
 694  */
 695 static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev)
 696 {
 697         uint32_t data = 0;
 698         int i;
 699
 700         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 701                 if (adev->vcn.harvest_config & (1 << i))
 702                         continue;
 703                 /* enable UVD CGC */
 704                 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
 705                 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 706                         data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 707                 else
 708                         data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 709                 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 710                 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 711                 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
 712
 713                 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
 714                 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 715                         | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 716                         | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 717                         | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 718                         | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 719                         | UVD_CGC_CTRL__SYS_MODE_MASK
 720                         | UVD_CGC_CTRL__UDEC_MODE_MASK
 721                         | UVD_CGC_CTRL__MPEG2_MODE_MASK
 722                         | UVD_CGC_CTRL__REGS_MODE_MASK
 723                         | UVD_CGC_CTRL__RBC_MODE_MASK
 724                         | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 725                         | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 726                         | UVD_CGC_CTRL__IDCT_MODE_MASK
 727                         | UVD_CGC_CTRL__MPRD_MODE_MASK
 728                         | UVD_CGC_CTRL__MPC_MODE_MASK
 729                         | UVD_CGC_CTRL__LBSI_MODE_MASK
 730                         | UVD_CGC_CTRL__LRBBM_MODE_MASK
 731                         | UVD_CGC_CTRL__WCB_MODE_MASK
 732                         | UVD_CGC_CTRL__VCPU_MODE_MASK);
 733                 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
 734
 735                 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL);
 736                 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 737                         | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 738                         | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 739                         | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 740                         | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 741                         | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 742                         | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 743                         | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 744                         | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 745                         | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 746                 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data);
 747         }
 748 }
 749
 750 static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
 751 {
 752         struct amdgpu_ring *ring;
 753         uint32_t rb_bufsz, tmp;
 754
 755         /* disable register anti-hang mechanism */
 756         WREG32_P(SOC15_REG_OFFSET(UVD, inst_idx, mmUVD_POWER_STATUS), 1,
 757                 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
 758         /* enable dynamic power gating mode */
 759         tmp = RREG32_SOC15(UVD, inst_idx, mmUVD_POWER_STATUS);
 760         tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
 761         tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
 762         WREG32_SOC15(UVD, inst_idx, mmUVD_POWER_STATUS, tmp);
 763
 764         if (indirect)
 765                 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t*)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
 766
 767         /* enable clock gating */
 768         vcn_v2_5_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);
 769
 770         /* enable VCPU clock */
 771         tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
 772         tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
 773         tmp |= UVD_VCPU_CNTL__BLK_RST_MASK;
 774         WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 775                 UVD, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
 776
 777         /* disable master interupt */
 778         WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 779                 UVD, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect);
 780
 781         /* setup mmUVD_LMI_CTRL */
 782         tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 783                 UVD_LMI_CTRL__REQ_MODE_MASK |
 784                 UVD_LMI_CTRL__CRC_RESET_MASK |
 785                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
 786                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 787                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 788                 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 789                 0x00100000L);
 790         WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 791                 UVD, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect);
 792
 793         WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 794                 UVD, inst_idx, mmUVD_MPC_CNTL),
 795                 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
 796
 797         WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 798                 UVD, inst_idx, mmUVD_MPC_SET_MUXA0),
 799                 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
 800                  (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
 801                  (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
 802                  (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
 803
 804         WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 805                 UVD, inst_idx, mmUVD_MPC_SET_MUXB0),
 806                 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
 807                  (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
 808                  (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
 809                  (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
 810
 811         WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 812                 UVD, inst_idx, mmUVD_MPC_SET_MUX),
 813                 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
 814                  (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
 815                  (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
 816
 817         vcn_v2_5_mc_resume_dpg_mode(adev, inst_idx, indirect);
 818
 819         WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 820                 UVD, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
 821         WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 822                 UVD, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
 823
 824         /* enable LMI MC and UMC channels */
 825         WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 826                 UVD, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect);
 827
 828         /* unblock VCPU register access */
 829         WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 830                 UVD, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect);
 831
 832         tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
 833         tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
 834         WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 835                 UVD, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
 836
 837         /* enable master interrupt */
 838         WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
 839                 UVD, inst_idx, mmUVD_MASTINT_EN),
 840                 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
 841
 842         if (indirect)
 843                 psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr,
 844                                     (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -
 845                                                (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr));
 846
 847         ring = &adev->vcn.inst[inst_idx].ring_dec;
 848         /* force RBC into idle state */
 849         rb_bufsz = order_base_2(ring->ring_size);
 850         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
 851         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
 852         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 853         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
 854         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
 855         WREG32_SOC15(UVD, inst_idx, mmUVD_RBC_RB_CNTL, tmp);
 856
 857         /* set the write pointer delay */
 858         WREG32_SOC15(UVD, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0);
 859
 860         /* set the wb address */
 861         WREG32_SOC15(UVD, inst_idx, mmUVD_RBC_RB_RPTR_ADDR,
 862                 (upper_32_bits(ring->gpu_addr) >> 2));
 863
 864         /* programm the RB_BASE for ring buffer */
 865         WREG32_SOC15(UVD, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
 866                 lower_32_bits(ring->gpu_addr));
 867         WREG32_SOC15(UVD, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
 868                 upper_32_bits(ring->gpu_addr));
 869
 870         /* Initialize the ring buffer's read and write pointers */
 871         WREG32_SOC15(UVD, inst_idx, mmUVD_RBC_RB_RPTR, 0);
 872
 873         WREG32_SOC15(UVD, inst_idx, mmUVD_SCRATCH2, 0);
 874
 875         ring->wptr = RREG32_SOC15(UVD, inst_idx, mmUVD_RBC_RB_RPTR);
 876         WREG32_SOC15(UVD, inst_idx, mmUVD_RBC_RB_WPTR,
 877                 lower_32_bits(ring->wptr));
 878
 879         return 0;
 880 }
 881
 882 static int vcn_v2_5_start(struct amdgpu_device *adev)
 883 {
 884         struct amdgpu_ring *ring;
 885         uint32_t rb_bufsz, tmp;
 886         int i, j, k, r;
 887
 888         if (adev->pm.dpm_enabled)
 889                 amdgpu_dpm_enable_uvd(adev, true);
 890
 891         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 892                 if (adev->vcn.harvest_config & (1 << i))
 893                         continue;
 894                 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
 895                         return vcn_v2_5_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
 896
 897                 /* disable register anti-hang mechanism */
 898                 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_POWER_STATUS), 0,
 899                         ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
 900
 901                 /* set uvd status busy */
 902                 tmp = RREG32_SOC15(UVD, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
 903                 WREG32_SOC15(UVD, i, mmUVD_STATUS, tmp);
 904         }
 905
 906         /*SW clock gating */
 907         vcn_v2_5_disable_clock_gating(adev);
 908
 909         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 910                 if (adev->vcn.harvest_config & (1 << i))
 911                         continue;
 912                 /* enable VCPU clock */
 913                 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),
 914                         UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
 915
 916                 /* disable master interrupt */
 917                 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), 0,
 918                         ~UVD_MASTINT_EN__VCPU_EN_MASK);
 919
 920                 /* setup mmUVD_LMI_CTRL */
 921                 tmp = RREG32_SOC15(UVD, i, mmUVD_LMI_CTRL);
 922                 tmp &= ~0xff;
 923                 WREG32_SOC15(UVD, i, mmUVD_LMI_CTRL, tmp | 0x8|
 924                         UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 925                         UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
 926                         UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 927                         UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
 928
 929                 /* setup mmUVD_MPC_CNTL */
 930                 tmp = RREG32_SOC15(UVD, i, mmUVD_MPC_CNTL);
 931                 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
 932                 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
 933                 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp);
 934
 935                 /* setup UVD_MPC_SET_MUXA0 */
 936                 WREG32_SOC15(UVD, i, mmUVD_MPC_SET_MUXA0,
 937                         ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
 938                         (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
 939                         (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
 940                         (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
 941
 942                 /* setup UVD_MPC_SET_MUXB0 */
 943                 WREG32_SOC15(UVD, i, mmUVD_MPC_SET_MUXB0,
 944                         ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
 945                         (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
 946                         (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
 947                         (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
 948
 949                 /* setup mmUVD_MPC_SET_MUX */
 950                 WREG32_SOC15(UVD, i, mmUVD_MPC_SET_MUX,
 951                         ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
 952                         (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
 953                         (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
 954         }
 955
 956         vcn_v2_5_mc_resume(adev);
 957
 958         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 959                 if (adev->vcn.harvest_config & (1 << i))
 960                         continue;
 961                 /* VCN global tiling registers */
 962                 WREG32_SOC15(UVD, i, mmUVD_GFX8_ADDR_CONFIG,
 963                         adev->gfx.config.gb_addr_config);
 964                 WREG32_SOC15(UVD, i, mmUVD_GFX8_ADDR_CONFIG,
 965                         adev->gfx.config.gb_addr_config);
 966
 967                 /* enable LMI MC and UMC channels */
 968                 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0,
 969                         ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 970
 971                 /* unblock VCPU register access */
 972                 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_ARB_CTRL), 0,
 973                         ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
 974
 975                 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 0,
 976                         ~UVD_VCPU_CNTL__BLK_RST_MASK);
 977
 978                 for (k = 0; k < 10; ++k) {
 979                         uint32_t status;
 980
 981                         for (j = 0; j < 100; ++j) {
 982                                 status = RREG32_SOC15(UVD, i, mmUVD_STATUS);
 983                                 if (status & 2)
 984                                         break;
 985                                 if (amdgpu_emu_mode == 1)
 986                                         msleep(500);
 987                                 else
 988                                         mdelay(10);
 989                         }
 990                         r = 0;
 991                         if (status & 2)
 992                                 break;
 993
 994                         DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
 995                         WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),
 996                                 UVD_VCPU_CNTL__BLK_RST_MASK,
 997                                 ~UVD_VCPU_CNTL__BLK_RST_MASK);
 998                         mdelay(10);
 999                         WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 0,
1000                                 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1001
1002                         mdelay(10);
1003                         r = -1;
1004                 }
1005
1006                 if (r) {
1007                         DRM_ERROR("VCN decode not responding, giving up!!!\n");
1008                         return r;
1009                 }
1010
1011                 /* enable master interrupt */
1012                 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),
1013                         UVD_MASTINT_EN__VCPU_EN_MASK,
1014                         ~UVD_MASTINT_EN__VCPU_EN_MASK);
1015
1016                 /* clear the busy bit of VCN_STATUS */
1017                 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0,
1018                         ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1019
1020                 WREG32_SOC15(UVD, i, mmUVD_LMI_RBC_RB_VMID, 0);
1021
1022                 ring = &adev->vcn.inst[i].ring_dec;
1023                 /* force RBC into idle state */
1024                 rb_bufsz = order_base_2(ring->ring_size);
1025                 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1026                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1027                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1028                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1029                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1030                 WREG32_SOC15(UVD, i, mmUVD_RBC_RB_CNTL, tmp);
1031
1032                 /* programm the RB_BASE for ring buffer */
1033                 WREG32_SOC15(UVD, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1034                         lower_32_bits(ring->gpu_addr));
1035                 WREG32_SOC15(UVD, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1036                         upper_32_bits(ring->gpu_addr));
1037
1038                 /* Initialize the ring buffer's read and write pointers */
1039                 WREG32_SOC15(UVD, i, mmUVD_RBC_RB_RPTR, 0);
1040
1041                 ring->wptr = RREG32_SOC15(UVD, i, mmUVD_RBC_RB_RPTR);
1042                 WREG32_SOC15(UVD, i, mmUVD_RBC_RB_WPTR,
1043                                 lower_32_bits(ring->wptr));
1044                 ring = &adev->vcn.inst[i].ring_enc[0];
1045                 WREG32_SOC15(UVD, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1046                 WREG32_SOC15(UVD, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1047                 WREG32_SOC15(UVD, i, mmUVD_RB_BASE_LO, ring->gpu_addr);
1048                 WREG32_SOC15(UVD, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1049                 WREG32_SOC15(UVD, i, mmUVD_RB_SIZE, ring->ring_size / 4);
1050
1051                 ring = &adev->vcn.inst[i].ring_enc[1];
1052                 WREG32_SOC15(UVD, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1053                 WREG32_SOC15(UVD, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1054                 WREG32_SOC15(UVD, i, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1055                 WREG32_SOC15(UVD, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1056                 WREG32_SOC15(UVD, i, mmUVD_RB_SIZE2, ring->ring_size / 4);
1057         }
1058
1059         return 0;
1060 }
1061
1062 static int vcn_v2_5_mmsch_start(struct amdgpu_device *adev,
1063                                 struct amdgpu_mm_table *table)
1064 {
1065         uint32_t data = 0, loop = 0, size = 0;
1066         uint64_t addr = table->gpu_addr;
1067         struct mmsch_v1_1_init_header *header = NULL;;
1068
1069         header = (struct mmsch_v1_1_init_header *)table->cpu_addr;
1070         size = header->total_size;
1071
1072         /*
1073          * 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of
1074          *  memory descriptor location
1075          */
1076         WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));
1077         WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));
1078
1079         /* 2, update vmid of descriptor */
1080         data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID);
1081         data &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
1082         /* use domain0 for MM scheduler */
1083         data |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
1084         WREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID, data);
1085
1086         /* 3, notify mmsch about the size of this descriptor */
1087         WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_SIZE, size);
1088
1089         /* 4, set resp to zero */
1090         WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP, 0);
1091
1092         /*
1093          * 5, kick off the initialization and wait until
1094          * VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero
1095          */
1096         WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001);
1097
1098         data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP);
1099         loop = 10;
1100         while ((data & 0x10000002) != 0x10000002) {
1101                 udelay(100);
1102                 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP);
1103                 loop--;
1104                 if (!loop)
1105                         break;
1106         }
1107
1108         if (!loop) {
1109                 dev_err(adev->dev,
1110                         "failed to init MMSCH, mmMMSCH_VF_MAILBOX_RESP = %x\n",
1111                         data);
1112                 return -EBUSY;
1113         }
1114
1115         return 0;
1116 }
1117
1118 static int vcn_v2_5_sriov_start(struct amdgpu_device *adev)
1119 {
1120         struct amdgpu_ring *ring;
1121         uint32_t offset, size, tmp, i, rb_bufsz;
1122         uint32_t table_size = 0;
1123         struct mmsch_v1_0_cmd_direct_write direct_wt = { { 0 } };
1124         struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { { 0 } };
1125         struct mmsch_v1_0_cmd_direct_polling direct_poll = { { 0 } };
1126         struct mmsch_v1_0_cmd_end end = { { 0 } };
1127         uint32_t *init_table = adev->virt.mm_table.cpu_addr;
1128         struct mmsch_v1_1_init_header *header = (struct mmsch_v1_1_init_header *)init_table;
1129
1130         direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE;
1131         direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
1132         direct_poll.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_POLLING;
1133         end.cmd_header.command_type = MMSCH_COMMAND__END;
1134
1135         header->version = MMSCH_VERSION;
1136         header->total_size = sizeof(struct mmsch_v1_1_init_header) >> 2;
1137         init_table += header->total_size;
1138
1139         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1140                 header->eng[i].table_offset = header->total_size;
1141                 header->eng[i].init_status = 0;
1142                 header->eng[i].table_size = 0;
1143
1144                 table_size = 0;
1145
1146                 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(
1147                         SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
1148                         ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);
1149
1150                 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
1151                 /* mc resume*/
1152                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1153                         MMSCH_V1_0_INSERT_DIRECT_WT(
1154                                 SOC15_REG_OFFSET(UVD, i,
1155                                         mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1156                                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo);
1157                         MMSCH_V1_0_INSERT_DIRECT_WT(
1158                                 SOC15_REG_OFFSET(UVD, i,
1159                                         mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1160                                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi);
1161                         offset = 0;
1162                         MMSCH_V1_0_INSERT_DIRECT_WT(
1163                                 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0), 0);
1164                 } else {
1165                         MMSCH_V1_0_INSERT_DIRECT_WT(
1166                                 SOC15_REG_OFFSET(UVD, i,
1167                                         mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1168                                 lower_32_bits(adev->vcn.inst[i].gpu_addr));
1169                         MMSCH_V1_0_INSERT_DIRECT_WT(
1170                                 SOC15_REG_OFFSET(UVD, i,
1171                                         mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1172                                 upper_32_bits(adev->vcn.inst[i].gpu_addr));
1173                         offset = size;
1174                         MMSCH_V1_0_INSERT_DIRECT_WT(
1175                                 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0),
1176                                 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
1177                 }
1178
1179                 MMSCH_V1_0_INSERT_DIRECT_WT(
1180                         SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0),
1181                         size);
1182                 MMSCH_V1_0_INSERT_DIRECT_WT(
1183                         SOC15_REG_OFFSET(UVD, i,
1184                                 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
1185                         lower_32_bits(adev->vcn.inst[i].gpu_addr + offset));
1186                 MMSCH_V1_0_INSERT_DIRECT_WT(
1187                         SOC15_REG_OFFSET(UVD, i,
1188                                 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
1189                         upper_32_bits(adev->vcn.inst[i].gpu_addr + offset));
1190                 MMSCH_V1_0_INSERT_DIRECT_WT(
1191                         SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1),
1192                         0);
1193                 MMSCH_V1_0_INSERT_DIRECT_WT(
1194                         SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1),
1195                         AMDGPU_VCN_STACK_SIZE);
1196                 MMSCH_V1_0_INSERT_DIRECT_WT(
1197                         SOC15_REG_OFFSET(UVD, i,
1198                                 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
1199                         lower_32_bits(adev->vcn.inst[i].gpu_addr + offset +
1200                                 AMDGPU_VCN_STACK_SIZE));
1201                 MMSCH_V1_0_INSERT_DIRECT_WT(
1202                         SOC15_REG_OFFSET(UVD, i,
1203                                 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
1204                         upper_32_bits(adev->vcn.inst[i].gpu_addr + offset +
1205                                 AMDGPU_VCN_STACK_SIZE));
1206                 MMSCH_V1_0_INSERT_DIRECT_WT(
1207                         SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2),
1208                         0);
1209                 MMSCH_V1_0_INSERT_DIRECT_WT(
1210                         SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2),
1211                         AMDGPU_VCN_CONTEXT_SIZE);
1212
1213                 ring = &adev->vcn.inst[i].ring_enc[0];
1214                 ring->wptr = 0;
1215
1216                 MMSCH_V1_0_INSERT_DIRECT_WT(
1217                         SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO),
1218                         lower_32_bits(ring->gpu_addr));
1219                 MMSCH_V1_0_INSERT_DIRECT_WT(
1220                         SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI),
1221                         upper_32_bits(ring->gpu_addr));
1222                 MMSCH_V1_0_INSERT_DIRECT_WT(
1223                         SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE),
1224                         ring->ring_size / 4);
1225
1226                 ring = &adev->vcn.inst[i].ring_dec;
1227                 ring->wptr = 0;
1228                 MMSCH_V1_0_INSERT_DIRECT_WT(
1229                         SOC15_REG_OFFSET(UVD, i,
1230                                 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),
1231                         lower_32_bits(ring->gpu_addr));
1232                 MMSCH_V1_0_INSERT_DIRECT_WT(
1233                         SOC15_REG_OFFSET(UVD, i,
1234                                 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),
1235                         upper_32_bits(ring->gpu_addr));
1236
1237                 /* force RBC into idle state */
1238                 rb_bufsz = order_base_2(ring->ring_size);
1239                 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1240                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1241                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1242                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1243                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1244                 MMSCH_V1_0_INSERT_DIRECT_WT(
1245                         SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp);
1246
1247                 /* add end packet */
1248                 memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end));
1249                 table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4;
1250                 init_table += sizeof(struct mmsch_v1_0_cmd_end) / 4;
1251
1252                 /* refine header */
1253                 header->eng[i].table_size = table_size;
1254                 header->total_size += table_size;
1255         }
1256
1257         return vcn_v2_5_mmsch_start(adev, &adev->virt.mm_table);
1258 }
1259
1260 static int vcn_v2_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
1261 {
1262         int ret_code = 0;
1263         uint32_t tmp;
1264
1265         /* Wait for power status to be 1 */
1266         SOC15_WAIT_ON_RREG(UVD, inst_idx, mmUVD_POWER_STATUS, 1,
1267                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1268
1269         /* wait for read ptr to be equal to write ptr */
1270         tmp = RREG32_SOC15(UVD, inst_idx, mmUVD_RB_WPTR);
1271         SOC15_WAIT_ON_RREG(UVD, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
1272
1273         tmp = RREG32_SOC15(UVD, inst_idx, mmUVD_RB_WPTR2);
1274         SOC15_WAIT_ON_RREG(UVD, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF, ret_code);
1275
1276         tmp = RREG32_SOC15(UVD, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1277         SOC15_WAIT_ON_RREG(UVD, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
1278
1279         SOC15_WAIT_ON_RREG(UVD, inst_idx, mmUVD_POWER_STATUS, 1,
1280                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1281
1282         /* disable dynamic power gating mode */
1283         WREG32_P(SOC15_REG_OFFSET(UVD, inst_idx, mmUVD_POWER_STATUS), 0,
1284                         ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1285
1286         return 0;
1287 }
1288
1289 static int vcn_v2_5_stop(struct amdgpu_device *adev)
1290 {
1291         uint32_t tmp;
1292         int i, r = 0;
1293
1294         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1295                 if (adev->vcn.harvest_config & (1 << i))
1296                         continue;
1297
1298                 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1299                         r = vcn_v2_5_stop_dpg_mode(adev, i);
1300                         goto power_off;
1301                 }
1302
1303                 /* wait for vcn idle */
1304                 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r);
1305                 if (r)
1306                         return r;
1307
1308                 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1309                         UVD_LMI_STATUS__READ_CLEAN_MASK |
1310                         UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1311                         UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1312                 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp, r);
1313                 if (r)
1314                         return r;
1315
1316                 /* block LMI UMC channel */
1317                 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2);
1318                 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
1319                 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp);
1320
1321                 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
1322                         UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1323                 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp, r);
1324                 if (r)
1325                         return r;
1326
1327                 /* block VCPU register access */
1328                 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_ARB_CTRL),
1329                         UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
1330                         ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1331
1332                 /* reset VCPU */
1333                 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),
1334                         UVD_VCPU_CNTL__BLK_RST_MASK,
1335                         ~UVD_VCPU_CNTL__BLK_RST_MASK);
1336
1337                 /* disable VCPU clock */
1338                 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 0,
1339                         ~(UVD_VCPU_CNTL__CLK_EN_MASK));
1340
1341                 /* clear status */
1342                 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0);
1343
1344                 vcn_v2_5_enable_clock_gating(adev);
1345
1346                 /* enable register anti-hang mechanism */
1347                 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_POWER_STATUS),
1348                         UVD_POWER_STATUS__UVD_POWER_STATUS_MASK,
1349                         ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1350         }
1351
1352 power_off:
1353         if (adev->pm.dpm_enabled)
1354                 amdgpu_dpm_enable_uvd(adev, false);
1355
1356         return 0;
1357 }
1358
1359 static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
1360                                 int inst_idx, struct dpg_pause_state *new_state)
1361 {
1362         struct amdgpu_ring *ring;
1363         uint32_t reg_data = 0;
1364         int ret_code;
1365
1366         /* pause/unpause if state is changed */
1367         if (adev->vcn.pause_state.fw_based != new_state->fw_based) {
1368                 DRM_DEBUG("dpg pause state changed %d -> %d",
1369                         adev->vcn.pause_state.fw_based, new_state->fw_based);
1370                 reg_data = RREG32_SOC15(UVD, inst_idx, mmUVD_DPG_PAUSE) &
1371                         (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1372
1373                 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1374                         ret_code = 0;
1375                         SOC15_WAIT_ON_RREG(UVD, inst_idx, mmUVD_POWER_STATUS, 0x1,
1376                                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1377
1378                         if (!ret_code) {
1379                                 /* pause DPG */
1380                                 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1381                                 WREG32_SOC15(UVD, inst_idx, mmUVD_DPG_PAUSE, reg_data);
1382
1383                                 /* wait for ACK */
1384                                 SOC15_WAIT_ON_RREG(UVD, inst_idx, mmUVD_DPG_PAUSE,
1385                                            UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1386                                            UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code);
1387
1388                                 /* Restore */
1389                                 ring = &adev->vcn.inst[inst_idx].ring_enc[0];
1390                                 WREG32_SOC15(UVD, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr);
1391                                 WREG32_SOC15(UVD, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1392                                 WREG32_SOC15(UVD, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4);
1393                                 WREG32_SOC15(UVD, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1394                                 WREG32_SOC15(UVD, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1395
1396                                 ring = &adev->vcn.inst[inst_idx].ring_enc[1];
1397                                 WREG32_SOC15(UVD, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1398                                 WREG32_SOC15(UVD, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1399                                 WREG32_SOC15(UVD, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4);
1400                                 WREG32_SOC15(UVD, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1401                                 WREG32_SOC15(UVD, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1402
1403                                 WREG32_SOC15(UVD, inst_idx, mmUVD_RBC_RB_WPTR,
1404                                            RREG32_SOC15(UVD, inst_idx, mmUVD_SCRATCH2) & 0x7FFFFFFF);
1405
1406                                 SOC15_WAIT_ON_RREG(UVD, inst_idx, mmUVD_POWER_STATUS,
1407                                            0x0, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1408                         }
1409                 } else {
1410                         /* unpause dpg, no need to wait */
1411                         reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1412                         WREG32_SOC15(UVD, inst_idx, mmUVD_DPG_PAUSE, reg_data);
1413                 }
1414                 adev->vcn.pause_state.fw_based = new_state->fw_based;
1415         }
1416
1417         return 0;
1418 }
1419
1420 /**
1421  * vcn_v2_5_dec_ring_get_rptr - get read pointer
1422  *
1423  * @ring: amdgpu_ring pointer
1424  *
1425  * Returns the current hardware read pointer
1426  */
1427 static uint64_t vcn_v2_5_dec_ring_get_rptr(struct amdgpu_ring *ring)
1428 {
1429         struct amdgpu_device *adev = ring->adev;
1430
1431         return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR);
1432 }
1433
1434 /**
1435  * vcn_v2_5_dec_ring_get_wptr - get write pointer
1436  *
1437  * @ring: amdgpu_ring pointer
1438  *
1439  * Returns the current hardware write pointer
1440  */
1441 static uint64_t vcn_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring)
1442 {
1443         struct amdgpu_device *adev = ring->adev;
1444
1445         if (ring->use_doorbell)
1446                 return adev->wb.wb[ring->wptr_offs];
1447         else
1448                 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR);
1449 }
1450
1451 /**
1452  * vcn_v2_5_dec_ring_set_wptr - set write pointer
1453  *
1454  * @ring: amdgpu_ring pointer
1455  *
1456  * Commits the write pointer to the hardware
1457  */
1458 static void vcn_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring)
1459 {
1460         struct amdgpu_device *adev = ring->adev;
1461
1462         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1463                 WREG32_SOC15(UVD, ring->me, mmUVD_SCRATCH2,
1464                         lower_32_bits(ring->wptr) | 0x80000000);
1465
1466         if (ring->use_doorbell) {
1467                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1468                 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1469         } else {
1470                 WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1471         }
1472 }
1473
1474 static const struct amdgpu_ring_funcs vcn_v2_5_dec_ring_vm_funcs = {
1475         .type = AMDGPU_RING_TYPE_VCN_DEC,
1476         .align_mask = 0xf,
1477         .vmhub = AMDGPU_MMHUB_1,
1478         .get_rptr = vcn_v2_5_dec_ring_get_rptr,
1479         .get_wptr = vcn_v2_5_dec_ring_get_wptr,
1480         .set_wptr = vcn_v2_5_dec_ring_set_wptr,
1481         .emit_frame_size =
1482                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1483                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
1484                 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */
1485                 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */
1486                 6,
1487         .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */
1488         .emit_ib = vcn_v2_0_dec_ring_emit_ib,
1489         .emit_fence = vcn_v2_0_dec_ring_emit_fence,
1490         .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
1491         .test_ring = amdgpu_vcn_dec_ring_test_ring,
1492         .test_ib = amdgpu_vcn_dec_ring_test_ib,
1493         .insert_nop = vcn_v2_0_dec_ring_insert_nop,
1494         .insert_start = vcn_v2_0_dec_ring_insert_start,
1495         .insert_end = vcn_v2_0_dec_ring_insert_end,
1496         .pad_ib = amdgpu_ring_generic_pad_ib,
1497         .begin_use = amdgpu_vcn_ring_begin_use,
1498         .end_use = amdgpu_vcn_ring_end_use,
1499         .emit_wreg = vcn_v2_0_dec_ring_emit_wreg,
1500         .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,
1501         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1502 };
1503
1504 /**
1505  * vcn_v2_5_enc_ring_get_rptr - get enc read pointer
1506  *
1507  * @ring: amdgpu_ring pointer
1508  *
1509  * Returns the current hardware enc read pointer
1510  */
1511 static uint64_t vcn_v2_5_enc_ring_get_rptr(struct amdgpu_ring *ring)
1512 {
1513         struct amdgpu_device *adev = ring->adev;
1514
1515         if (ring == &adev->vcn.inst[ring->me].ring_enc[0])
1516                 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR);
1517         else
1518                 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2);
1519 }
1520
1521 /**
1522  * vcn_v2_5_enc_ring_get_wptr - get enc write pointer
1523  *
1524  * @ring: amdgpu_ring pointer
1525  *
1526  * Returns the current hardware enc write pointer
1527  */
1528 static uint64_t vcn_v2_5_enc_ring_get_wptr(struct amdgpu_ring *ring)
1529 {
1530         struct amdgpu_device *adev = ring->adev;
1531
1532         if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
1533                 if (ring->use_doorbell)
1534                         return adev->wb.wb[ring->wptr_offs];
1535                 else
1536                         return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR);
1537         } else {
1538                 if (ring->use_doorbell)
1539                         return adev->wb.wb[ring->wptr_offs];
1540                 else
1541                         return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2);
1542         }
1543 }
1544
1545 /**
1546  * vcn_v2_5_enc_ring_set_wptr - set enc write pointer
1547  *
1548  * @ring: amdgpu_ring pointer
1549  *
1550  * Commits the enc write pointer to the hardware
1551  */
1552 static void vcn_v2_5_enc_ring_set_wptr(struct amdgpu_ring *ring)
1553 {
1554         struct amdgpu_device *adev = ring->adev;
1555
1556         if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
1557                 if (ring->use_doorbell) {
1558                         adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1559                         WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1560                 } else {
1561                         WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1562                 }
1563         } else {
1564                 if (ring->use_doorbell) {
1565                         adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1566                         WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1567                 } else {
1568                         WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1569                 }
1570         }
1571 }
1572
1573 static const struct amdgpu_ring_funcs vcn_v2_5_enc_ring_vm_funcs = {
1574         .type = AMDGPU_RING_TYPE_VCN_ENC,
1575         .align_mask = 0x3f,
1576         .nop = VCN_ENC_CMD_NO_OP,
1577         .vmhub = AMDGPU_MMHUB_1,
1578         .get_rptr = vcn_v2_5_enc_ring_get_rptr,
1579         .get_wptr = vcn_v2_5_enc_ring_get_wptr,
1580         .set_wptr = vcn_v2_5_enc_ring_set_wptr,
1581         .emit_frame_size =
1582                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1583                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1584                 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
1585                 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
1586                 1, /* vcn_v2_0_enc_ring_insert_end */
1587         .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
1588         .emit_ib = vcn_v2_0_enc_ring_emit_ib,
1589         .emit_fence = vcn_v2_0_enc_ring_emit_fence,
1590         .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
1591         .test_ring = amdgpu_vcn_enc_ring_test_ring,
1592         .test_ib = amdgpu_vcn_enc_ring_test_ib,
1593         .insert_nop = amdgpu_ring_insert_nop,
1594         .insert_end = vcn_v2_0_enc_ring_insert_end,
1595         .pad_ib = amdgpu_ring_generic_pad_ib,
1596         .begin_use = amdgpu_vcn_ring_begin_use,
1597         .end_use = amdgpu_vcn_ring_end_use,
1598         .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
1599         .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
1600         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1601 };
1602
1603 static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
1604 {
1605         int i;
1606
1607         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1608                 if (adev->vcn.harvest_config & (1 << i))
1609                         continue;
1610                 adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs;
1611                 adev->vcn.inst[i].ring_dec.me = i;
1612                 DRM_INFO("VCN(%d) decode is enabled in VM mode\n", i);
1613         }
1614 }
1615
1616 static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev)
1617 {
1618         int i, j;
1619
1620         for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
1621                 if (adev->vcn.harvest_config & (1 << j))
1622                         continue;
1623                 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
1624                         adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs;
1625                         adev->vcn.inst[j].ring_enc[i].me = j;
1626                 }
1627                 DRM_INFO("VCN(%d) encode is enabled in VM mode\n", j);
1628         }
1629 }
1630
1631 static bool vcn_v2_5_is_idle(void *handle)
1632 {
1633         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1634         int i, ret = 1;
1635
1636         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1637                 if (adev->vcn.harvest_config & (1 << i))
1638                         continue;
1639                 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE);
1640         }
1641
1642         return ret;
1643 }
1644
1645 static int vcn_v2_5_wait_for_idle(void *handle)
1646 {
1647         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1648         int i, ret = 0;
1649
1650         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1651                 if (adev->vcn.harvest_config & (1 << i))
1652                         continue;
1653                 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE,
1654                         UVD_STATUS__IDLE, ret);
1655                 if (ret)
1656                         return ret;
1657         }
1658
1659         return ret;
1660 }
1661
1662 static int vcn_v2_5_set_clockgating_state(void *handle,
1663                                           enum amd_clockgating_state state)
1664 {
1665         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1666         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1667
1668         if (amdgpu_sriov_vf(adev))
1669                 return 0;
1670
1671         if (enable) {
1672                 if (vcn_v2_5_is_idle(handle))
1673                         return -EBUSY;
1674                 vcn_v2_5_enable_clock_gating(adev);
1675         } else {
1676                 vcn_v2_5_disable_clock_gating(adev);
1677         }
1678
1679         return 0;
1680 }
1681
1682 static int vcn_v2_5_set_powergating_state(void *handle,
1683                                           enum amd_powergating_state state)
1684 {
1685         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1686         int ret;
1687
1688         if (amdgpu_sriov_vf(adev))
1689                 return 0;
1690
1691         if(state == adev->vcn.cur_state)
1692                 return 0;
1693
1694         if (state == AMD_PG_STATE_GATE)
1695                 ret = vcn_v2_5_stop(adev);
1696         else
1697                 ret = vcn_v2_5_start(adev);
1698
1699         if(!ret)
1700                 adev->vcn.cur_state = state;
1701
1702         return ret;
1703 }
1704
1705 static int vcn_v2_5_set_interrupt_state(struct amdgpu_device *adev,
1706                                         struct amdgpu_irq_src *source,
1707                                         unsigned type,
1708                                         enum amdgpu_interrupt_state state)
1709 {
1710         return 0;
1711 }
1712
1713 static int vcn_v2_5_process_interrupt(struct amdgpu_device *adev,
1714                                       struct amdgpu_irq_src *source,
1715                                       struct amdgpu_iv_entry *entry)
1716 {
1717         uint32_t ip_instance;
1718
1719         switch (entry->client_id) {
1720         case SOC15_IH_CLIENTID_VCN:
1721                 ip_instance = 0;
1722                 break;
1723         case SOC15_IH_CLIENTID_VCN1:
1724                 ip_instance = 1;
1725                 break;
1726         default:
1727                 DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
1728                 return 0;
1729         }
1730
1731         DRM_DEBUG("IH: VCN TRAP\n");
1732
1733         switch (entry->src_id) {
1734         case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT:
1735                 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec);
1736                 break;
1737         case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
1738                 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);
1739                 break;
1740         case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:
1741                 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]);
1742                 break;
1743         default:
1744                 DRM_ERROR("Unhandled interrupt: %d %d\n",
1745                           entry->src_id, entry->src_data[0]);
1746                 break;
1747         }
1748
1749         return 0;
1750 }
1751
1752 static const struct amdgpu_irq_src_funcs vcn_v2_5_irq_funcs = {
1753         .set = vcn_v2_5_set_interrupt_state,
1754         .process = vcn_v2_5_process_interrupt,
1755 };
1756
1757 static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev)
1758 {
1759         int i;
1760
1761         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1762                 if (adev->vcn.harvest_config & (1 << i))
1763                         continue;
1764                 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1;
1765                 adev->vcn.inst[i].irq.funcs = &vcn_v2_5_irq_funcs;
1766         }
1767 }
1768
1769 static const struct amd_ip_funcs vcn_v2_5_ip_funcs = {
1770         .name = "vcn_v2_5",
1771         .early_init = vcn_v2_5_early_init,
1772         .late_init = NULL,
1773         .sw_init = vcn_v2_5_sw_init,
1774         .sw_fini = vcn_v2_5_sw_fini,
1775         .hw_init = vcn_v2_5_hw_init,
1776         .hw_fini = vcn_v2_5_hw_fini,
1777         .suspend = vcn_v2_5_suspend,
1778         .resume = vcn_v2_5_resume,
1779         .is_idle = vcn_v2_5_is_idle,
1780         .wait_for_idle = vcn_v2_5_wait_for_idle,
1781         .check_soft_reset = NULL,
1782         .pre_soft_reset = NULL,
1783         .soft_reset = NULL,
1784         .post_soft_reset = NULL,
1785         .set_clockgating_state = vcn_v2_5_set_clockgating_state,
1786         .set_powergating_state = vcn_v2_5_set_powergating_state,
1787 };
1788
1789 const struct amdgpu_ip_block_version vcn_v2_5_ip_block =
1790 {
1791                 .type = AMD_IP_BLOCK_TYPE_VCN,
1792                 .major = 2,
1793                 .minor = 5,
1794                 .rev = 0,
1795                 .funcs = &vcn_v2_5_ip_funcs,
1796 };