drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <drm/drmP.h>
  25 #include "amdgpu.h"
  26 #include "cikd.h"
  27 #include "cik.h"
  28 #include "gmc_v7_0.h"
  29 #include "amdgpu_ucode.h"
  30
  31 #include "bif/bif_4_1_d.h"
  32 #include "bif/bif_4_1_sh_mask.h"
  33
  34 #include "gmc/gmc_7_1_d.h"
  35 #include "gmc/gmc_7_1_sh_mask.h"
  36
  37 #include "oss/oss_2_0_d.h"
  38 #include "oss/oss_2_0_sh_mask.h"
  39
  40 #include "dce/dce_8_0_d.h"
  41 #include "dce/dce_8_0_sh_mask.h"
  42
  43 #include "amdgpu_atombios.h"
  44
  45 static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev);
  46 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);
  47 static int gmc_v7_0_wait_for_idle(void *handle);
  48
  49 MODULE_FIRMWARE("radeon/bonaire_mc.bin");
  50 MODULE_FIRMWARE("radeon/hawaii_mc.bin");
  51 MODULE_FIRMWARE("amdgpu/topaz_mc.bin");
  52
  53 static const u32 golden_settings_iceland_a11[] =
  54 {
  55         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  56         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  57         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  58         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  59 };
  60
  61 static const u32 iceland_mgcg_cgcg_init[] =
  62 {
  63         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  64 };
  65
  66 static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev)
  67 {
  68         switch (adev->asic_type) {
  69         case CHIP_TOPAZ:
  70                 amdgpu_program_register_sequence(adev,
  71                                                  iceland_mgcg_cgcg_init,
  72                                                  (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
  73                 amdgpu_program_register_sequence(adev,
  74                                                  golden_settings_iceland_a11,
  75                                                  (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
  76                 break;
  77         default:
  78                 break;
  79         }
  80 }
  81
  82 static void gmc_v7_0_mc_stop(struct amdgpu_device *adev)
  83 {
  84         u32 blackout;
  85
  86         gmc_v7_0_wait_for_idle((void *)adev);
  87
  88         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
  89         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
  90                 /* Block CPU access */
  91                 WREG32(mmBIF_FB_EN, 0);
  92                 /* blackout the MC */
  93                 blackout = REG_SET_FIELD(blackout,
  94                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
  95                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
  96         }
  97         /* wait for the MC to settle */
  98         udelay(100);
  99 }
 100
 101 static void gmc_v7_0_mc_resume(struct amdgpu_device *adev)
 102 {
 103         u32 tmp;
 104
 105         /* unblackout the MC */
 106         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 107         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 108         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 109         /* allow CPU access */
 110         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 111         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 112         WREG32(mmBIF_FB_EN, tmp);
 113 }
 114
 115 /**
 116  * gmc_v7_0_init_microcode - load ucode images from disk
 117  *
 118  * @adev: amdgpu_device pointer
 119  *
 120  * Use the firmware interface to load the ucode images into
 121  * the driver (not loaded into hw).
 122  * Returns 0 on success, error on failure.
 123  */
 124 static int gmc_v7_0_init_microcode(struct amdgpu_device *adev)
 125 {
 126         const char *chip_name;
 127         char fw_name[30];
 128         int err;
 129
 130         DRM_DEBUG("\n");
 131
 132         switch (adev->asic_type) {
 133         case CHIP_BONAIRE:
 134                 chip_name = "bonaire";
 135                 break;
 136         case CHIP_HAWAII:
 137                 chip_name = "hawaii";
 138                 break;
 139         case CHIP_TOPAZ:
 140                 chip_name = "topaz";
 141                 break;
 142         case CHIP_KAVERI:
 143         case CHIP_KABINI:
 144         case CHIP_MULLINS:
 145                 return 0;
 146         default: BUG();
 147         }
 148
 149         if (adev->asic_type == CHIP_TOPAZ)
 150                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
 151         else
 152                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
 153
 154         err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
 155         if (err)
 156                 goto out;
 157         err = amdgpu_ucode_validate(adev->mc.fw);
 158
 159 out:
 160         if (err) {
 161                 pr_err("cik_mc: Failed to load firmware \"%s\"\n", fw_name);
 162                 release_firmware(adev->mc.fw);
 163                 adev->mc.fw = NULL;
 164         }
 165         return err;
 166 }
 167
 168 /**
 169  * gmc_v7_0_mc_load_microcode - load MC ucode into the hw
 170  *
 171  * @adev: amdgpu_device pointer
 172  *
 173  * Load the GDDR MC ucode into the hw (CIK).
 174  * Returns 0 on success, error on failure.
 175  */
 176 static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev)
 177 {
 178         const struct mc_firmware_header_v1_0 *hdr;
 179         const __le32 *fw_data = NULL;
 180         const __le32 *io_mc_regs = NULL;
 181         u32 running;
 182         int i, ucode_size, regs_size;
 183
 184         if (!adev->mc.fw)
 185                 return -EINVAL;
 186
 187         hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 188         amdgpu_ucode_print_mc_hdr(&hdr->header);
 189
 190         adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 191         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 192         io_mc_regs = (const __le32 *)
 193                 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 194         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 195         fw_data = (const __le32 *)
 196                 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 197
 198         running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
 199
 200         if (running == 0) {
 201                 /* reset the engine and set to writable */
 202                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 203                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 204
 205                 /* load mc io regs */
 206                 for (i = 0; i < regs_size; i++) {
 207                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 208                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 209                 }
 210                 /* load the MC ucode */
 211                 for (i = 0; i < ucode_size; i++)
 212                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 213
 214                 /* put the engine back into the active state */
 215                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 216                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 217                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 218
 219                 /* wait for training to complete */
 220                 for (i = 0; i < adev->usec_timeout; i++) {
 221                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 222                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
 223                                 break;
 224                         udelay(1);
 225                 }
 226                 for (i = 0; i < adev->usec_timeout; i++) {
 227                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 228                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
 229                                 break;
 230                         udelay(1);
 231                 }
 232         }
 233
 234         return 0;
 235 }
 236
 237 static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev,
 238                                        struct amdgpu_mc *mc)
 239 {
 240         u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
 241         base <<= 24;
 242
 243         if (mc->mc_vram_size > 0xFFC0000000ULL) {
 244                 /* leave room for at least 1024M GTT */
 245                 dev_warn(adev->dev, "limiting VRAM\n");
 246                 mc->real_vram_size = 0xFFC0000000ULL;
 247                 mc->mc_vram_size = 0xFFC0000000ULL;
 248         }
 249         amdgpu_vram_location(adev, &adev->mc, base);
 250         amdgpu_gart_location(adev, mc);
 251 }
 252
 253 /**
 254  * gmc_v7_0_mc_program - program the GPU memory controller
 255  *
 256  * @adev: amdgpu_device pointer
 257  *
 258  * Set the location of vram, gart, and AGP in the GPU's
 259  * physical address space (CIK).
 260  */
 261 static void gmc_v7_0_mc_program(struct amdgpu_device *adev)
 262 {
 263         u32 tmp;
 264         int i, j;
 265
 266         /* Initialize HDP */
 267         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 268                 WREG32((0xb05 + j), 0x00000000);
 269                 WREG32((0xb06 + j), 0x00000000);
 270                 WREG32((0xb07 + j), 0x00000000);
 271                 WREG32((0xb08 + j), 0x00000000);
 272                 WREG32((0xb09 + j), 0x00000000);
 273         }
 274         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 275
 276         if (gmc_v7_0_wait_for_idle((void *)adev)) {
 277                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 278         }
 279         if (adev->mode_info.num_crtc) {
 280                 /* Lockout access through VGA aperture*/
 281                 tmp = RREG32(mmVGA_HDP_CONTROL);
 282                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 283                 WREG32(mmVGA_HDP_CONTROL, tmp);
 284
 285                 /* disable VGA render */
 286                 tmp = RREG32(mmVGA_RENDER_CONTROL);
 287                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 288                 WREG32(mmVGA_RENDER_CONTROL, tmp);
 289         }
 290         /* Update configuration */
 291         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 292                adev->mc.vram_start >> 12);
 293         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 294                adev->mc.vram_end >> 12);
 295         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 296                adev->vram_scratch.gpu_addr >> 12);
 297         WREG32(mmMC_VM_AGP_BASE, 0);
 298         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 299         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 300         if (gmc_v7_0_wait_for_idle((void *)adev)) {
 301                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 302         }
 303
 304         WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
 305
 306         tmp = RREG32(mmHDP_MISC_CNTL);
 307         tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
 308         WREG32(mmHDP_MISC_CNTL, tmp);
 309
 310         tmp = RREG32(mmHDP_HOST_PATH_CNTL);
 311         WREG32(mmHDP_HOST_PATH_CNTL, tmp);
 312 }
 313
 314 /**
 315  * gmc_v7_0_mc_init - initialize the memory controller driver params
 316  *
 317  * @adev: amdgpu_device pointer
 318  *
 319  * Look up the amount of vram, vram width, and decide how to place
 320  * vram and gart within the GPU's physical address space (CIK).
 321  * Returns 0 for success.
 322  */
 323 static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
 324 {
 325         adev->mc.vram_width = amdgpu_atombios_get_vram_width(adev);
 326         if (!adev->mc.vram_width) {
 327                 u32 tmp;
 328                 int chansize, numchan;
 329
 330                 /* Get VRAM informations */
 331                 tmp = RREG32(mmMC_ARB_RAMCFG);
 332                 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
 333                         chansize = 64;
 334                 } else {
 335                         chansize = 32;
 336                 }
 337                 tmp = RREG32(mmMC_SHARED_CHMAP);
 338                 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 339                 case 0:
 340                 default:
 341                         numchan = 1;
 342                         break;
 343                 case 1:
 344                         numchan = 2;
 345                         break;
 346                 case 2:
 347                         numchan = 4;
 348                         break;
 349                 case 3:
 350                         numchan = 8;
 351                         break;
 352                 case 4:
 353                         numchan = 3;
 354                         break;
 355                 case 5:
 356                         numchan = 6;
 357                         break;
 358                 case 6:
 359                         numchan = 10;
 360                         break;
 361                 case 7:
 362                         numchan = 12;
 363                         break;
 364                 case 8:
 365                         numchan = 16;
 366                         break;
 367                 }
 368                 adev->mc.vram_width = numchan * chansize;
 369         }
 370         /* Could aper size report 0 ? */
 371         adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
 372         adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
 373         /* size in MB on si */
 374         adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 375         adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 376
 377 #ifdef CONFIG_X86_64
 378         if (adev->flags & AMD_IS_APU) {
 379                 adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
 380                 adev->mc.aper_size = adev->mc.real_vram_size;
 381         }
 382 #endif
 383
 384         /* In case the PCI BAR is larger than the actual amount of vram */
 385         adev->mc.visible_vram_size = adev->mc.aper_size;
 386         if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
 387                 adev->mc.visible_vram_size = adev->mc.real_vram_size;
 388
 389         amdgpu_gart_set_defaults(adev);
 390         gmc_v7_0_vram_gtt_location(adev, &adev->mc);
 391
 392         return 0;
 393 }
 394
 395 /*
 396  * GART
 397  * VMID 0 is the physical GPU addresses as used by the kernel.
 398  * VMIDs 1-15 are used for userspace clients and are handled
 399  * by the amdgpu vm/hsa code.
 400  */
 401
 402 /**
 403  * gmc_v7_0_gart_flush_gpu_tlb - gart tlb flush callback
 404  *
 405  * @adev: amdgpu_device pointer
 406  * @vmid: vm instance to flush
 407  *
 408  * Flush the TLB for the requested page table (CIK).
 409  */
 410 static void gmc_v7_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
 411                                         uint32_t vmid)
 412 {
 413         /* flush hdp cache */
 414         WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
 415
 416         /* bits 0-15 are the VM contexts0-15 */
 417         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 418 }
 419
 420 /**
 421  * gmc_v7_0_gart_set_pte_pde - update the page tables using MMIO
 422  *
 423  * @adev: amdgpu_device pointer
 424  * @cpu_pt_addr: cpu address of the page table
 425  * @gpu_page_idx: entry in the page table to update
 426  * @addr: dst addr to write into pte/pde
 427  * @flags: access flags
 428  *
 429  * Update the page tables using the CPU.
 430  */
 431 static int gmc_v7_0_gart_set_pte_pde(struct amdgpu_device *adev,
 432                                      void *cpu_pt_addr,
 433                                      uint32_t gpu_page_idx,
 434                                      uint64_t addr,
 435                                      uint64_t flags)
 436 {
 437         void __iomem *ptr = (void *)cpu_pt_addr;
 438         uint64_t value;
 439
 440         value = addr & 0xFFFFFFFFFFFFF000ULL;
 441         value |= flags;
 442         writeq(value, ptr + (gpu_page_idx * 8));
 443
 444         return 0;
 445 }
 446
 447 static uint64_t gmc_v7_0_get_vm_pte_flags(struct amdgpu_device *adev,
 448                                           uint32_t flags)
 449 {
 450         uint64_t pte_flag = 0;
 451
 452         if (flags & AMDGPU_VM_PAGE_READABLE)
 453                 pte_flag |= AMDGPU_PTE_READABLE;
 454         if (flags & AMDGPU_VM_PAGE_WRITEABLE)
 455                 pte_flag |= AMDGPU_PTE_WRITEABLE;
 456         if (flags & AMDGPU_VM_PAGE_PRT)
 457                 pte_flag |= AMDGPU_PTE_PRT;
 458
 459         return pte_flag;
 460 }
 461
 462 static uint64_t gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, uint64_t addr)
 463 {
 464         BUG_ON(addr & 0xFFFFFF0000000FFFULL);
 465         return addr;
 466 }
 467
 468 /**
 469  * gmc_v8_0_set_fault_enable_default - update VM fault handling
 470  *
 471  * @adev: amdgpu_device pointer
 472  * @value: true redirects VM faults to the default page
 473  */
 474 static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev,
 475                                               bool value)
 476 {
 477         u32 tmp;
 478
 479         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 480         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 481                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 482         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 483                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 484         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 485                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 486         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 487                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 488         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 489                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 490         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 491                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 492         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 493 }
 494
 495 /**
 496  * gmc_v7_0_set_prt - set PRT VM fault
 497  *
 498  * @adev: amdgpu_device pointer
 499  * @enable: enable/disable VM fault handling for PRT
 500  */
 501 static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable)
 502 {
 503         uint32_t tmp;
 504
 505         if (enable && !adev->mc.prt_warning) {
 506                 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
 507                 adev->mc.prt_warning = true;
 508         }
 509
 510         tmp = RREG32(mmVM_PRT_CNTL);
 511         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 512                             CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 513         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 514                             CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 515         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 516                             TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 517         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 518                             TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 519         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 520                             L2_CACHE_STORE_INVALID_ENTRIES, enable);
 521         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 522                             L1_TLB_STORE_INVALID_ENTRIES, enable);
 523         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 524                             MASK_PDE0_FAULT, enable);
 525         WREG32(mmVM_PRT_CNTL, tmp);
 526
 527         if (enable) {
 528                 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
 529                 uint32_t high = adev->vm_manager.max_pfn;
 530
 531                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
 532                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
 533                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
 534                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
 535                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
 536                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
 537                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
 538                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
 539         } else {
 540                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
 541                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
 542                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
 543                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
 544                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
 545                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
 546                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
 547                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
 548         }
 549 }
 550
 551 /**
 552  * gmc_v7_0_gart_enable - gart enable
 553  *
 554  * @adev: amdgpu_device pointer
 555  *
 556  * This sets up the TLBs, programs the page tables for VMID0,
 557  * sets up the hw for VMIDs 1-15 which are allocated on
 558  * demand, and sets up the global locations for the LDS, GDS,
 559  * and GPUVM for FSA64 clients (CIK).
 560  * Returns 0 for success, errors for failure.
 561  */
 562 static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
 563 {
 564         int r, i;
 565         u32 tmp, field;
 566
 567         if (adev->gart.robj == NULL) {
 568                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 569                 return -EINVAL;
 570         }
 571         r = amdgpu_gart_table_vram_pin(adev);
 572         if (r)
 573                 return r;
 574         /* Setup TLB control */
 575         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 576         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 577         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
 578         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 579         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
 580         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 581         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 582         /* Setup L2 cache */
 583         tmp = RREG32(mmVM_L2_CNTL);
 584         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 585         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 586         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
 587         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
 588         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
 589         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 590         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 591         WREG32(mmVM_L2_CNTL, tmp);
 592         tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 593         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 594         WREG32(mmVM_L2_CNTL2, tmp);
 595
 596         field = adev->vm_manager.fragment_size;
 597         tmp = RREG32(mmVM_L2_CNTL3);
 598         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
 599         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
 600         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
 601         WREG32(mmVM_L2_CNTL3, tmp);
 602         /* setup context0 */
 603         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gart_start >> 12);
 604         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gart_end >> 12);
 605         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
 606         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 607                         (u32)(adev->dummy_page.addr >> 12));
 608         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 609         tmp = RREG32(mmVM_CONTEXT0_CNTL);
 610         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 611         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 612         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 613         WREG32(mmVM_CONTEXT0_CNTL, tmp);
 614
 615         WREG32(0x575, 0);
 616         WREG32(0x576, 0);
 617         WREG32(0x577, 0);
 618
 619         /* empty context1-15 */
 620         /* FIXME start with 4G, once using 2 level pt switch to full
 621          * vm size space
 622          */
 623         /* set vm size, must be a multiple of 4 */
 624         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 625         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 626         for (i = 1; i < 16; i++) {
 627                 if (i < 8)
 628                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 629                                adev->gart.table_addr >> 12);
 630                 else
 631                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 632                                adev->gart.table_addr >> 12);
 633         }
 634
 635         /* enable context1-15 */
 636         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 637                (u32)(adev->dummy_page.addr >> 12));
 638         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 639         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 640         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 641         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
 642         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
 643                             adev->vm_manager.block_size - 9);
 644         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 645         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 646                 gmc_v7_0_set_fault_enable_default(adev, false);
 647         else
 648                 gmc_v7_0_set_fault_enable_default(adev, true);
 649
 650         if (adev->asic_type == CHIP_KAVERI) {
 651                 tmp = RREG32(mmCHUB_CONTROL);
 652                 tmp &= ~BYPASS_VM;
 653                 WREG32(mmCHUB_CONTROL, tmp);
 654         }
 655
 656         gmc_v7_0_gart_flush_gpu_tlb(adev, 0);
 657         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 658                  (unsigned)(adev->mc.gart_size >> 20),
 659                  (unsigned long long)adev->gart.table_addr);
 660         adev->gart.ready = true;
 661         return 0;
 662 }
 663
 664 static int gmc_v7_0_gart_init(struct amdgpu_device *adev)
 665 {
 666         int r;
 667
 668         if (adev->gart.robj) {
 669                 WARN(1, "R600 PCIE GART already initialized\n");
 670                 return 0;
 671         }
 672         /* Initialize common gart structure */
 673         r = amdgpu_gart_init(adev);
 674         if (r)
 675                 return r;
 676         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 677         adev->gart.gart_pte_flags = 0;
 678         return amdgpu_gart_table_vram_alloc(adev);
 679 }
 680
 681 /**
 682  * gmc_v7_0_gart_disable - gart disable
 683  *
 684  * @adev: amdgpu_device pointer
 685  *
 686  * This disables all VM page table (CIK).
 687  */
 688 static void gmc_v7_0_gart_disable(struct amdgpu_device *adev)
 689 {
 690         u32 tmp;
 691
 692         /* Disable all tables */
 693         WREG32(mmVM_CONTEXT0_CNTL, 0);
 694         WREG32(mmVM_CONTEXT1_CNTL, 0);
 695         /* Setup TLB control */
 696         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 697         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 698         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
 699         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
 700         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 701         /* Setup L2 cache */
 702         tmp = RREG32(mmVM_L2_CNTL);
 703         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 704         WREG32(mmVM_L2_CNTL, tmp);
 705         WREG32(mmVM_L2_CNTL2, 0);
 706         amdgpu_gart_table_vram_unpin(adev);
 707 }
 708
 709 /**
 710  * gmc_v7_0_gart_fini - vm fini callback
 711  *
 712  * @adev: amdgpu_device pointer
 713  *
 714  * Tears down the driver GART/VM setup (CIK).
 715  */
 716 static void gmc_v7_0_gart_fini(struct amdgpu_device *adev)
 717 {
 718         amdgpu_gart_table_vram_free(adev);
 719         amdgpu_gart_fini(adev);
 720 }
 721
 722 /**
 723  * gmc_v7_0_vm_decode_fault - print human readable fault info
 724  *
 725  * @adev: amdgpu_device pointer
 726  * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
 727  * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
 728  *
 729  * Print human readable fault information (CIK).
 730  */
 731 static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev,
 732                                      u32 status, u32 addr, u32 mc_client)
 733 {
 734         u32 mc_id;
 735         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 736         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 737                                         PROTECTIONS);
 738         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 739                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 740
 741         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 742                               MEMORY_CLIENT_ID);
 743
 744         dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 745                protections, vmid, addr,
 746                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 747                              MEMORY_CLIENT_RW) ?
 748                "write" : "read", block, mc_client, mc_id);
 749 }
 750
 751
 752 static const u32 mc_cg_registers[] = {
 753         mmMC_HUB_MISC_HUB_CG,
 754         mmMC_HUB_MISC_SIP_CG,
 755         mmMC_HUB_MISC_VM_CG,
 756         mmMC_XPB_CLK_GAT,
 757         mmATC_MISC_CG,
 758         mmMC_CITF_MISC_WR_CG,
 759         mmMC_CITF_MISC_RD_CG,
 760         mmMC_CITF_MISC_VM_CG,
 761         mmVM_L2_CG,
 762 };
 763
 764 static const u32 mc_cg_ls_en[] = {
 765         MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
 766         MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
 767         MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 768         MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
 769         ATC_MISC_CG__MEM_LS_ENABLE_MASK,
 770         MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
 771         MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
 772         MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 773         VM_L2_CG__MEM_LS_ENABLE_MASK,
 774 };
 775
 776 static const u32 mc_cg_en[] = {
 777         MC_HUB_MISC_HUB_CG__ENABLE_MASK,
 778         MC_HUB_MISC_SIP_CG__ENABLE_MASK,
 779         MC_HUB_MISC_VM_CG__ENABLE_MASK,
 780         MC_XPB_CLK_GAT__ENABLE_MASK,
 781         ATC_MISC_CG__ENABLE_MASK,
 782         MC_CITF_MISC_WR_CG__ENABLE_MASK,
 783         MC_CITF_MISC_RD_CG__ENABLE_MASK,
 784         MC_CITF_MISC_VM_CG__ENABLE_MASK,
 785         VM_L2_CG__ENABLE_MASK,
 786 };
 787
 788 static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev,
 789                                   bool enable)
 790 {
 791         int i;
 792         u32 orig, data;
 793
 794         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 795                 orig = data = RREG32(mc_cg_registers[i]);
 796                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
 797                         data |= mc_cg_ls_en[i];
 798                 else
 799                         data &= ~mc_cg_ls_en[i];
 800                 if (data != orig)
 801                         WREG32(mc_cg_registers[i], data);
 802         }
 803 }
 804
 805 static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev,
 806                                     bool enable)
 807 {
 808         int i;
 809         u32 orig, data;
 810
 811         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 812                 orig = data = RREG32(mc_cg_registers[i]);
 813                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
 814                         data |= mc_cg_en[i];
 815                 else
 816                         data &= ~mc_cg_en[i];
 817                 if (data != orig)
 818                         WREG32(mc_cg_registers[i], data);
 819         }
 820 }
 821
 822 static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev,
 823                                      bool enable)
 824 {
 825         u32 orig, data;
 826
 827         orig = data = RREG32_PCIE(ixPCIE_CNTL2);
 828
 829         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
 830                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
 831                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
 832                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
 833                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
 834         } else {
 835                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
 836                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
 837                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
 838                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
 839         }
 840
 841         if (orig != data)
 842                 WREG32_PCIE(ixPCIE_CNTL2, data);
 843 }
 844
 845 static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev,
 846                                      bool enable)
 847 {
 848         u32 orig, data;
 849
 850         orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
 851
 852         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
 853                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
 854         else
 855                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
 856
 857         if (orig != data)
 858                 WREG32(mmHDP_HOST_PATH_CNTL, data);
 859 }
 860
 861 static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev,
 862                                    bool enable)
 863 {
 864         u32 orig, data;
 865
 866         orig = data = RREG32(mmHDP_MEM_POWER_LS);
 867
 868         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
 869                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
 870         else
 871                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
 872
 873         if (orig != data)
 874                 WREG32(mmHDP_MEM_POWER_LS, data);
 875 }
 876
 877 static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type)
 878 {
 879         switch (mc_seq_vram_type) {
 880         case MC_SEQ_MISC0__MT__GDDR1:
 881                 return AMDGPU_VRAM_TYPE_GDDR1;
 882         case MC_SEQ_MISC0__MT__DDR2:
 883                 return AMDGPU_VRAM_TYPE_DDR2;
 884         case MC_SEQ_MISC0__MT__GDDR3:
 885                 return AMDGPU_VRAM_TYPE_GDDR3;
 886         case MC_SEQ_MISC0__MT__GDDR4:
 887                 return AMDGPU_VRAM_TYPE_GDDR4;
 888         case MC_SEQ_MISC0__MT__GDDR5:
 889                 return AMDGPU_VRAM_TYPE_GDDR5;
 890         case MC_SEQ_MISC0__MT__HBM:
 891                 return AMDGPU_VRAM_TYPE_HBM;
 892         case MC_SEQ_MISC0__MT__DDR3:
 893                 return AMDGPU_VRAM_TYPE_DDR3;
 894         default:
 895                 return AMDGPU_VRAM_TYPE_UNKNOWN;
 896         }
 897 }
 898
 899 static int gmc_v7_0_early_init(void *handle)
 900 {
 901         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 902
 903         gmc_v7_0_set_gart_funcs(adev);
 904         gmc_v7_0_set_irq_funcs(adev);
 905
 906         adev->mc.shared_aperture_start = 0x2000000000000000ULL;
 907         adev->mc.shared_aperture_end =
 908                 adev->mc.shared_aperture_start + (4ULL << 30) - 1;
 909         adev->mc.private_aperture_start =
 910                 adev->mc.shared_aperture_end + 1;
 911         adev->mc.private_aperture_end =
 912                 adev->mc.private_aperture_start + (4ULL << 30) - 1;
 913
 914         return 0;
 915 }
 916
 917 static int gmc_v7_0_late_init(void *handle)
 918 {
 919         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 920
 921         if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
 922                 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
 923         else
 924                 return 0;
 925 }
 926
 927 static int gmc_v7_0_sw_init(void *handle)
 928 {
 929         int r;
 930         int dma_bits;
 931         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 932
 933         if (adev->flags & AMD_IS_APU) {
 934                 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 935         } else {
 936                 u32 tmp = RREG32(mmMC_SEQ_MISC0);
 937                 tmp &= MC_SEQ_MISC0__MT__MASK;
 938                 adev->mc.vram_type = gmc_v7_0_convert_vram_type(tmp);
 939         }
 940
 941         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->mc.vm_fault);
 942         if (r)
 943                 return r;
 944
 945         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->mc.vm_fault);
 946         if (r)
 947                 return r;
 948
 949         /* Adjust VM size here.
 950          * Currently set to 4GB ((1 << 20) 4k pages).
 951          * Max GPUVM size for cayman and SI is 40 bits.
 952          */
 953         amdgpu_vm_adjust_size(adev, 64, 4);
 954         adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
 955
 956         /* Set the internal MC address mask
 957          * This is the max address of the GPU's
 958          * internal address space.
 959          */
 960         adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
 961
 962         adev->mc.stolen_size = 256 * 1024;
 963
 964         /* set DMA mask + need_dma32 flags.
 965          * PCIE - can handle 40-bits.
 966          * IGP - can handle 40-bits
 967          * PCI - dma32 for legacy pci gart, 40 bits on newer asics
 968          */
 969         adev->need_dma32 = false;
 970         dma_bits = adev->need_dma32 ? 32 : 40;
 971         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 972         if (r) {
 973                 adev->need_dma32 = true;
 974                 dma_bits = 32;
 975                 pr_warn("amdgpu: No suitable DMA available\n");
 976         }
 977         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 978         if (r) {
 979                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
 980                 pr_warn("amdgpu: No coherent DMA available\n");
 981         }
 982
 983         r = gmc_v7_0_init_microcode(adev);
 984         if (r) {
 985                 DRM_ERROR("Failed to load mc firmware!\n");
 986                 return r;
 987         }
 988
 989         r = gmc_v7_0_mc_init(adev);
 990         if (r)
 991                 return r;
 992
 993         /* Memory manager */
 994         r = amdgpu_bo_init(adev);
 995         if (r)
 996                 return r;
 997
 998         r = gmc_v7_0_gart_init(adev);
 999         if (r)
1000                 return r;
1001
1002         /*
1003          * number of VMs
1004          * VMID 0 is reserved for System
1005          * amdgpu graphics/compute will use VMIDs 1-7
1006          * amdkfd will use VMIDs 8-15
1007          */
1008         adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
1009         adev->vm_manager.num_level = 1;
1010         amdgpu_vm_manager_init(adev);
1011
1012         /* base offset of vram pages */
1013         if (adev->flags & AMD_IS_APU) {
1014                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
1015
1016                 tmp <<= 22;
1017                 adev->vm_manager.vram_base_offset = tmp;
1018         } else {
1019                 adev->vm_manager.vram_base_offset = 0;
1020         }
1021
1022         return 0;
1023 }
1024
1025 static int gmc_v7_0_sw_fini(void *handle)
1026 {
1027         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1028
1029         amdgpu_vm_manager_fini(adev);
1030         gmc_v7_0_gart_fini(adev);
1031         amdgpu_gem_force_release(adev);
1032         amdgpu_bo_fini(adev);
1033
1034         return 0;
1035 }
1036
1037 static int gmc_v7_0_hw_init(void *handle)
1038 {
1039         int r;
1040         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1041
1042         gmc_v7_0_init_golden_registers(adev);
1043
1044         gmc_v7_0_mc_program(adev);
1045
1046         if (!(adev->flags & AMD_IS_APU)) {
1047                 r = gmc_v7_0_mc_load_microcode(adev);
1048                 if (r) {
1049                         DRM_ERROR("Failed to load MC firmware!\n");
1050                         return r;
1051                 }
1052         }
1053
1054         r = gmc_v7_0_gart_enable(adev);
1055         if (r)
1056                 return r;
1057
1058         return r;
1059 }
1060
1061 static int gmc_v7_0_hw_fini(void *handle)
1062 {
1063         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1064
1065         amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
1066         gmc_v7_0_gart_disable(adev);
1067
1068         return 0;
1069 }
1070
1071 static int gmc_v7_0_suspend(void *handle)
1072 {
1073         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1074
1075         gmc_v7_0_hw_fini(adev);
1076
1077         return 0;
1078 }
1079
1080 static int gmc_v7_0_resume(void *handle)
1081 {
1082         int r;
1083         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1084
1085         r = gmc_v7_0_hw_init(adev);
1086         if (r)
1087                 return r;
1088
1089         amdgpu_vm_reset_all_ids(adev);
1090
1091         return 0;
1092 }
1093
1094 static bool gmc_v7_0_is_idle(void *handle)
1095 {
1096         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1097         u32 tmp = RREG32(mmSRBM_STATUS);
1098
1099         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1100                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1101                 return false;
1102
1103         return true;
1104 }
1105
1106 static int gmc_v7_0_wait_for_idle(void *handle)
1107 {
1108         unsigned i;
1109         u32 tmp;
1110         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1111
1112         for (i = 0; i < adev->usec_timeout; i++) {
1113                 /* read MC_STATUS */
1114                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1115                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1116                                                SRBM_STATUS__MCC_BUSY_MASK |
1117                                                SRBM_STATUS__MCD_BUSY_MASK |
1118                                                SRBM_STATUS__VMC_BUSY_MASK);
1119                 if (!tmp)
1120                         return 0;
1121                 udelay(1);
1122         }
1123         return -ETIMEDOUT;
1124
1125 }
1126
1127 static int gmc_v7_0_soft_reset(void *handle)
1128 {
1129         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1130         u32 srbm_soft_reset = 0;
1131         u32 tmp = RREG32(mmSRBM_STATUS);
1132
1133         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1134                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1135                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1136
1137         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1138                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1139                 if (!(adev->flags & AMD_IS_APU))
1140                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1141                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1142         }
1143
1144         if (srbm_soft_reset) {
1145                 gmc_v7_0_mc_stop(adev);
1146                 if (gmc_v7_0_wait_for_idle((void *)adev)) {
1147                         dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1148                 }
1149
1150
1151                 tmp = RREG32(mmSRBM_SOFT_RESET);
1152                 tmp |= srbm_soft_reset;
1153                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1154                 WREG32(mmSRBM_SOFT_RESET, tmp);
1155                 tmp = RREG32(mmSRBM_SOFT_RESET);
1156
1157                 udelay(50);
1158
1159                 tmp &= ~srbm_soft_reset;
1160                 WREG32(mmSRBM_SOFT_RESET, tmp);
1161                 tmp = RREG32(mmSRBM_SOFT_RESET);
1162
1163                 /* Wait a little for things to settle down */
1164                 udelay(50);
1165
1166                 gmc_v7_0_mc_resume(adev);
1167                 udelay(50);
1168         }
1169
1170         return 0;
1171 }
1172
1173 static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1174                                              struct amdgpu_irq_src *src,
1175                                              unsigned type,
1176                                              enum amdgpu_interrupt_state state)
1177 {
1178         u32 tmp;
1179         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1180                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1181                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1182                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1183                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1184                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1185
1186         switch (state) {
1187         case AMDGPU_IRQ_STATE_DISABLE:
1188                 /* system context */
1189                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1190                 tmp &= ~bits;
1191                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1192                 /* VMs */
1193                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1194                 tmp &= ~bits;
1195                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1196                 break;
1197         case AMDGPU_IRQ_STATE_ENABLE:
1198                 /* system context */
1199                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1200                 tmp |= bits;
1201                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1202                 /* VMs */
1203                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1204                 tmp |= bits;
1205                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1206                 break;
1207         default:
1208                 break;
1209         }
1210
1211         return 0;
1212 }
1213
1214 static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev,
1215                                       struct amdgpu_irq_src *source,
1216                                       struct amdgpu_iv_entry *entry)
1217 {
1218         u32 addr, status, mc_client;
1219
1220         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1221         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1222         mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1223         /* reset addr and status */
1224         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1225
1226         if (!addr && !status)
1227                 return 0;
1228
1229         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1230                 gmc_v7_0_set_fault_enable_default(adev, false);
1231
1232         if (printk_ratelimit()) {
1233                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1234                         entry->src_id, entry->src_data[0]);
1235                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1236                         addr);
1237                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1238                         status);
1239                 gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client);
1240         }
1241
1242         return 0;
1243 }
1244
1245 static int gmc_v7_0_set_clockgating_state(void *handle,
1246                                           enum amd_clockgating_state state)
1247 {
1248         bool gate = false;
1249         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1250
1251         if (state == AMD_CG_STATE_GATE)
1252                 gate = true;
1253
1254         if (!(adev->flags & AMD_IS_APU)) {
1255                 gmc_v7_0_enable_mc_mgcg(adev, gate);
1256                 gmc_v7_0_enable_mc_ls(adev, gate);
1257         }
1258         gmc_v7_0_enable_bif_mgls(adev, gate);
1259         gmc_v7_0_enable_hdp_mgcg(adev, gate);
1260         gmc_v7_0_enable_hdp_ls(adev, gate);
1261
1262         return 0;
1263 }
1264
1265 static int gmc_v7_0_set_powergating_state(void *handle,
1266                                           enum amd_powergating_state state)
1267 {
1268         return 0;
1269 }
1270
1271 static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
1272         .name = "gmc_v7_0",
1273         .early_init = gmc_v7_0_early_init,
1274         .late_init = gmc_v7_0_late_init,
1275         .sw_init = gmc_v7_0_sw_init,
1276         .sw_fini = gmc_v7_0_sw_fini,
1277         .hw_init = gmc_v7_0_hw_init,
1278         .hw_fini = gmc_v7_0_hw_fini,
1279         .suspend = gmc_v7_0_suspend,
1280         .resume = gmc_v7_0_resume,
1281         .is_idle = gmc_v7_0_is_idle,
1282         .wait_for_idle = gmc_v7_0_wait_for_idle,
1283         .soft_reset = gmc_v7_0_soft_reset,
1284         .set_clockgating_state = gmc_v7_0_set_clockgating_state,
1285         .set_powergating_state = gmc_v7_0_set_powergating_state,
1286 };
1287
1288 static const struct amdgpu_gart_funcs gmc_v7_0_gart_funcs = {
1289         .flush_gpu_tlb = gmc_v7_0_gart_flush_gpu_tlb,
1290         .set_pte_pde = gmc_v7_0_gart_set_pte_pde,
1291         .set_prt = gmc_v7_0_set_prt,
1292         .get_vm_pte_flags = gmc_v7_0_get_vm_pte_flags,
1293         .get_vm_pde = gmc_v7_0_get_vm_pde
1294 };
1295
1296 static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = {
1297         .set = gmc_v7_0_vm_fault_interrupt_state,
1298         .process = gmc_v7_0_process_interrupt,
1299 };
1300
1301 static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev)
1302 {
1303         if (adev->gart.gart_funcs == NULL)
1304                 adev->gart.gart_funcs = &gmc_v7_0_gart_funcs;
1305 }
1306
1307 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1308 {
1309         adev->mc.vm_fault.num_types = 1;
1310         adev->mc.vm_fault.funcs = &gmc_v7_0_irq_funcs;
1311 }
1312
1313 const struct amdgpu_ip_block_version gmc_v7_0_ip_block =
1314 {
1315         .type = AMD_IP_BLOCK_TYPE_GMC,
1316         .major = 7,
1317         .minor = 0,
1318         .rev = 0,
1319         .funcs = &gmc_v7_0_ip_funcs,
1320 };
1321
1322 const struct amdgpu_ip_block_version gmc_v7_4_ip_block =
1323 {
1324         .type = AMD_IP_BLOCK_TYPE_GMC,
1325         .major = 7,
1326         .minor = 4,
1327         .rev = 0,
1328         .funcs = &gmc_v7_0_ip_funcs,
1329 };