drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

   1 /*
   2  * Copyright 2008 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jerome Glisse <[email protected]>
  26  */
  27 #include <linux/pagemap.h>
  28 #include <linux/sync_file.h>
  29 #include <drm/drmP.h>
  30 #include <drm/amdgpu_drm.h>
  31 #include <drm/drm_syncobj.h>
  32 #include "amdgpu.h"
  33 #include "amdgpu_trace.h"
  34
  35 static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
  36                                       struct drm_amdgpu_cs_chunk_fence *data,
  37                                       uint32_t *offset)
  38 {
  39         struct drm_gem_object *gobj;
  40         unsigned long size;
  41
  42         gobj = drm_gem_object_lookup(p->filp, data->handle);
  43         if (gobj == NULL)
  44                 return -EINVAL;
  45
  46         p->uf_entry.robj = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
  47         p->uf_entry.priority = 0;
  48         p->uf_entry.tv.bo = &p->uf_entry.robj->tbo;
  49         p->uf_entry.tv.shared = true;
  50         p->uf_entry.user_pages = NULL;
  51
  52         size = amdgpu_bo_size(p->uf_entry.robj);
  53         if (size != PAGE_SIZE || (data->offset + 8) > size)
  54                 return -EINVAL;
  55
  56         *offset = data->offset;
  57
  58         drm_gem_object_put_unlocked(gobj);
  59
  60         if (amdgpu_ttm_tt_get_usermm(p->uf_entry.robj->tbo.ttm)) {
  61                 amdgpu_bo_unref(&p->uf_entry.robj);
  62                 return -EINVAL;
  63         }
  64
  65         return 0;
  66 }
  67
  68 static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
  69 {
  70         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
  71         struct amdgpu_vm *vm = &fpriv->vm;
  72         union drm_amdgpu_cs *cs = data;
  73         uint64_t *chunk_array_user;
  74         uint64_t *chunk_array;
  75         unsigned size, num_ibs = 0;
  76         uint32_t uf_offset = 0;
  77         int i;
  78         int ret;
  79
  80         if (cs->in.num_chunks == 0)
  81                 return 0;
  82
  83         chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
  84         if (!chunk_array)
  85                 return -ENOMEM;
  86
  87         p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
  88         if (!p->ctx) {
  89                 ret = -EINVAL;
  90                 goto free_chunk;
  91         }
  92
  93         /* skip guilty context job */
  94         if (atomic_read(&p->ctx->guilty) == 1) {
  95                 ret = -ECANCELED;
  96                 goto free_chunk;
  97         }
  98
  99         mutex_lock(&p->ctx->lock);
 100
 101         /* get chunks */
 102         chunk_array_user = u64_to_user_ptr(cs->in.chunks);
 103         if (copy_from_user(chunk_array, chunk_array_user,
 104                            sizeof(uint64_t)*cs->in.num_chunks)) {
 105                 ret = -EFAULT;
 106                 goto free_chunk;
 107         }
 108
 109         p->nchunks = cs->in.num_chunks;
 110         p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
 111                             GFP_KERNEL);
 112         if (!p->chunks) {
 113                 ret = -ENOMEM;
 114                 goto free_chunk;
 115         }
 116
 117         for (i = 0; i < p->nchunks; i++) {
 118                 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
 119                 struct drm_amdgpu_cs_chunk user_chunk;
 120                 uint32_t __user *cdata;
 121
 122                 chunk_ptr = u64_to_user_ptr(chunk_array[i]);
 123                 if (copy_from_user(&user_chunk, chunk_ptr,
 124                                        sizeof(struct drm_amdgpu_cs_chunk))) {
 125                         ret = -EFAULT;
 126                         i--;
 127                         goto free_partial_kdata;
 128                 }
 129                 p->chunks[i].chunk_id = user_chunk.chunk_id;
 130                 p->chunks[i].length_dw = user_chunk.length_dw;
 131
 132                 size = p->chunks[i].length_dw;
 133                 cdata = u64_to_user_ptr(user_chunk.chunk_data);
 134
 135                 p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
 136                 if (p->chunks[i].kdata == NULL) {
 137                         ret = -ENOMEM;
 138                         i--;
 139                         goto free_partial_kdata;
 140                 }
 141                 size *= sizeof(uint32_t);
 142                 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
 143                         ret = -EFAULT;
 144                         goto free_partial_kdata;
 145                 }
 146
 147                 switch (p->chunks[i].chunk_id) {
 148                 case AMDGPU_CHUNK_ID_IB:
 149                         ++num_ibs;
 150                         break;
 151
 152                 case AMDGPU_CHUNK_ID_FENCE:
 153                         size = sizeof(struct drm_amdgpu_cs_chunk_fence);
 154                         if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
 155                                 ret = -EINVAL;
 156                                 goto free_partial_kdata;
 157                         }
 158
 159                         ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata,
 160                                                          &uf_offset);
 161                         if (ret)
 162                                 goto free_partial_kdata;
 163
 164                         break;
 165
 166                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
 167                 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
 168                 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
 169                         break;
 170
 171                 default:
 172                         ret = -EINVAL;
 173                         goto free_partial_kdata;
 174                 }
 175         }
 176
 177         ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm);
 178         if (ret)
 179                 goto free_all_kdata;
 180
 181         if (p->ctx->vram_lost_counter != p->job->vram_lost_counter) {
 182                 ret = -ECANCELED;
 183                 goto free_all_kdata;
 184         }
 185
 186         if (p->uf_entry.robj)
 187                 p->job->uf_addr = uf_offset;
 188         kfree(chunk_array);
 189         return 0;
 190
 191 free_all_kdata:
 192         i = p->nchunks - 1;
 193 free_partial_kdata:
 194         for (; i >= 0; i--)
 195                 kvfree(p->chunks[i].kdata);
 196         kfree(p->chunks);
 197         p->chunks = NULL;
 198         p->nchunks = 0;
 199 free_chunk:
 200         kfree(chunk_array);
 201
 202         return ret;
 203 }
 204
 205 /* Convert microseconds to bytes. */
 206 static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)
 207 {
 208         if (us <= 0 || !adev->mm_stats.log2_max_MBps)
 209                 return 0;
 210
 211         /* Since accum_us is incremented by a million per second, just
 212          * multiply it by the number of MB/s to get the number of bytes.
 213          */
 214         return us << adev->mm_stats.log2_max_MBps;
 215 }
 216
 217 static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)
 218 {
 219         if (!adev->mm_stats.log2_max_MBps)
 220                 return 0;
 221
 222         return bytes >> adev->mm_stats.log2_max_MBps;
 223 }
 224
 225 /* Returns how many bytes TTM can move right now. If no bytes can be moved,
 226  * it returns 0. If it returns non-zero, it's OK to move at least one buffer,
 227  * which means it can go over the threshold once. If that happens, the driver
 228  * will be in debt and no other buffer migrations can be done until that debt
 229  * is repaid.
 230  *
 231  * This approach allows moving a buffer of any size (it's important to allow
 232  * that).
 233  *
 234  * The currency is simply time in microseconds and it increases as the clock
 235  * ticks. The accumulated microseconds (us) are converted to bytes and
 236  * returned.
 237  */
 238 static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
 239                                               u64 *max_bytes,
 240                                               u64 *max_vis_bytes)
 241 {
 242         s64 time_us, increment_us;
 243         u64 free_vram, total_vram, used_vram;
 244
 245         /* Allow a maximum of 200 accumulated ms. This is basically per-IB
 246          * throttling.
 247          *
 248          * It means that in order to get full max MBps, at least 5 IBs per
 249          * second must be submitted and not more than 200ms apart from each
 250          * other.
 251          */
 252         const s64 us_upper_bound = 200000;
 253
 254         if (!adev->mm_stats.log2_max_MBps) {
 255                 *max_bytes = 0;
 256                 *max_vis_bytes = 0;
 257                 return;
 258         }
 259
 260         total_vram = adev->mc.real_vram_size - adev->vram_pin_size;
 261         used_vram = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 262         free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
 263
 264         spin_lock(&adev->mm_stats.lock);
 265
 266         /* Increase the amount of accumulated us. */
 267         time_us = ktime_to_us(ktime_get());
 268         increment_us = time_us - adev->mm_stats.last_update_us;
 269         adev->mm_stats.last_update_us = time_us;
 270         adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,
 271                                       us_upper_bound);
 272
 273         /* This prevents the short period of low performance when the VRAM
 274          * usage is low and the driver is in debt or doesn't have enough
 275          * accumulated us to fill VRAM quickly.
 276          *
 277          * The situation can occur in these cases:
 278          * - a lot of VRAM is freed by userspace
 279          * - the presence of a big buffer causes a lot of evictions
 280          *   (solution: split buffers into smaller ones)
 281          *
 282          * If 128 MB or 1/8th of VRAM is free, start filling it now by setting
 283          * accum_us to a positive number.
 284          */
 285         if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) {
 286                 s64 min_us;
 287
 288                 /* Be more aggresive on dGPUs. Try to fill a portion of free
 289                  * VRAM now.
 290                  */
 291                 if (!(adev->flags & AMD_IS_APU))
 292                         min_us = bytes_to_us(adev, free_vram / 4);
 293                 else
 294                         min_us = 0; /* Reset accum_us on APUs. */
 295
 296                 adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us);
 297         }
 298
 299         /* This is set to 0 if the driver is in debt to disallow (optional)
 300          * buffer moves.
 301          */
 302         *max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);
 303
 304         /* Do the same for visible VRAM if half of it is free */
 305         if (adev->mc.visible_vram_size < adev->mc.real_vram_size) {
 306                 u64 total_vis_vram = adev->mc.visible_vram_size;
 307                 u64 used_vis_vram =
 308                         amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 309
 310                 if (used_vis_vram < total_vis_vram) {
 311                         u64 free_vis_vram = total_vis_vram - used_vis_vram;
 312                         adev->mm_stats.accum_us_vis = min(adev->mm_stats.accum_us_vis +
 313                                                           increment_us, us_upper_bound);
 314
 315                         if (free_vis_vram >= total_vis_vram / 2)
 316                                 adev->mm_stats.accum_us_vis =
 317                                         max(bytes_to_us(adev, free_vis_vram / 2),
 318                                             adev->mm_stats.accum_us_vis);
 319                 }
 320
 321                 *max_vis_bytes = us_to_bytes(adev, adev->mm_stats.accum_us_vis);
 322         } else {
 323                 *max_vis_bytes = 0;
 324         }
 325
 326         spin_unlock(&adev->mm_stats.lock);
 327 }
 328
 329 /* Report how many bytes have really been moved for the last command
 330  * submission. This can result in a debt that can stop buffer migrations
 331  * temporarily.
 332  */
 333 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
 334                                   u64 num_vis_bytes)
 335 {
 336         spin_lock(&adev->mm_stats.lock);
 337         adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
 338         adev->mm_stats.accum_us_vis -= bytes_to_us(adev, num_vis_bytes);
 339         spin_unlock(&adev->mm_stats.lock);
 340 }
 341
 342 static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p,
 343                                  struct amdgpu_bo *bo)
 344 {
 345         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 346         u64 initial_bytes_moved, bytes_moved;
 347         uint32_t domain;
 348         int r;
 349
 350         if (bo->pin_count)
 351                 return 0;
 352
 353         /* Don't move this buffer if we have depleted our allowance
 354          * to move it. Don't move anything if the threshold is zero.
 355          */
 356         if (p->bytes_moved < p->bytes_moved_threshold) {
 357                 if (adev->mc.visible_vram_size < adev->mc.real_vram_size &&
 358                     (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
 359                         /* And don't move a CPU_ACCESS_REQUIRED BO to limited
 360                          * visible VRAM if we've depleted our allowance to do
 361                          * that.
 362                          */
 363                         if (p->bytes_moved_vis < p->bytes_moved_vis_threshold)
 364                                 domain = bo->preferred_domains;
 365                         else
 366                                 domain = bo->allowed_domains;
 367                 } else {
 368                         domain = bo->preferred_domains;
 369                 }
 370         } else {
 371                 domain = bo->allowed_domains;
 372         }
 373
 374 retry:
 375         amdgpu_ttm_placement_from_domain(bo, domain);
 376         initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
 377         r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 378         bytes_moved = atomic64_read(&adev->num_bytes_moved) -
 379                       initial_bytes_moved;
 380         p->bytes_moved += bytes_moved;
 381         if (adev->mc.visible_vram_size < adev->mc.real_vram_size &&
 382             bo->tbo.mem.mem_type == TTM_PL_VRAM &&
 383             bo->tbo.mem.start < adev->mc.visible_vram_size >> PAGE_SHIFT)
 384                 p->bytes_moved_vis += bytes_moved;
 385
 386         if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
 387                 domain = bo->allowed_domains;
 388                 goto retry;
 389         }
 390
 391         return r;
 392 }
 393
 394 /* Last resort, try to evict something from the current working set */
 395 static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p,
 396                                 struct amdgpu_bo *validated)
 397 {
 398         uint32_t domain = validated->allowed_domains;
 399         int r;
 400
 401         if (!p->evictable)
 402                 return false;
 403
 404         for (;&p->evictable->tv.head != &p->validated;
 405              p->evictable = list_prev_entry(p->evictable, tv.head)) {
 406
 407                 struct amdgpu_bo_list_entry *candidate = p->evictable;
 408                 struct amdgpu_bo *bo = candidate->robj;
 409                 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 410                 u64 initial_bytes_moved, bytes_moved;
 411                 bool update_bytes_moved_vis;
 412                 uint32_t other;
 413
 414                 /* If we reached our current BO we can forget it */
 415                 if (candidate->robj == validated)
 416                         break;
 417
 418                 /* We can't move pinned BOs here */
 419                 if (bo->pin_count)
 420                         continue;
 421
 422                 other = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 423
 424                 /* Check if this BO is in one of the domains we need space for */
 425                 if (!(other & domain))
 426                         continue;
 427
 428                 /* Check if we can move this BO somewhere else */
 429                 other = bo->allowed_domains & ~domain;
 430                 if (!other)
 431                         continue;
 432
 433                 /* Good we can try to move this BO somewhere else */
 434                 amdgpu_ttm_placement_from_domain(bo, other);
 435                 update_bytes_moved_vis =
 436                         adev->mc.visible_vram_size < adev->mc.real_vram_size &&
 437                         bo->tbo.mem.mem_type == TTM_PL_VRAM &&
 438                         bo->tbo.mem.start < adev->mc.visible_vram_size >> PAGE_SHIFT;
 439                 initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
 440                 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 441                 bytes_moved = atomic64_read(&adev->num_bytes_moved) -
 442                         initial_bytes_moved;
 443                 p->bytes_moved += bytes_moved;
 444                 if (update_bytes_moved_vis)
 445                         p->bytes_moved_vis += bytes_moved;
 446
 447                 if (unlikely(r))
 448                         break;
 449
 450                 p->evictable = list_prev_entry(p->evictable, tv.head);
 451                 list_move(&candidate->tv.head, &p->validated);
 452
 453                 return true;
 454         }
 455
 456         return false;
 457 }
 458
 459 static int amdgpu_cs_validate(void *param, struct amdgpu_bo *bo)
 460 {
 461         struct amdgpu_cs_parser *p = param;
 462         int r;
 463
 464         do {
 465                 r = amdgpu_cs_bo_validate(p, bo);
 466         } while (r == -ENOMEM && amdgpu_cs_try_evict(p, bo));
 467         if (r)
 468                 return r;
 469
 470         if (bo->shadow)
 471                 r = amdgpu_cs_bo_validate(p, bo->shadow);
 472
 473         return r;
 474 }
 475
 476 static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
 477                             struct list_head *validated)
 478 {
 479         struct amdgpu_bo_list_entry *lobj;
 480         int r;
 481
 482         list_for_each_entry(lobj, validated, tv.head) {
 483                 struct amdgpu_bo *bo = lobj->robj;
 484                 bool binding_userptr = false;
 485                 struct mm_struct *usermm;
 486
 487                 usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
 488                 if (usermm && usermm != current->mm)
 489                         return -EPERM;
 490
 491                 /* Check if we have user pages and nobody bound the BO already */
 492                 if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) &&
 493                     lobj->user_pages) {
 494                         amdgpu_ttm_placement_from_domain(bo,
 495                                                          AMDGPU_GEM_DOMAIN_CPU);
 496                         r = ttm_bo_validate(&bo->tbo, &bo->placement, true,
 497                                             false);
 498                         if (r)
 499                                 return r;
 500                         amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
 501                                                      lobj->user_pages);
 502                         binding_userptr = true;
 503                 }
 504
 505                 if (p->evictable == lobj)
 506                         p->evictable = NULL;
 507
 508                 r = amdgpu_cs_validate(p, bo);
 509                 if (r)
 510                         return r;
 511
 512                 if (binding_userptr) {
 513                         kvfree(lobj->user_pages);
 514                         lobj->user_pages = NULL;
 515                 }
 516         }
 517         return 0;
 518 }
 519
 520 static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
 521                                 union drm_amdgpu_cs *cs)
 522 {
 523         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 524         struct amdgpu_bo_list_entry *e;
 525         struct list_head duplicates;
 526         unsigned i, tries = 10;
 527         int r;
 528
 529         INIT_LIST_HEAD(&p->validated);
 530
 531         p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
 532         if (p->bo_list) {
 533                 amdgpu_bo_list_get_list(p->bo_list, &p->validated);
 534                 if (p->bo_list->first_userptr != p->bo_list->num_entries)
 535                         p->mn = amdgpu_mn_get(p->adev);
 536         }
 537
 538         INIT_LIST_HEAD(&duplicates);
 539         amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
 540
 541         if (p->uf_entry.robj)
 542                 list_add(&p->uf_entry.tv.head, &p->validated);
 543
 544         while (1) {
 545                 struct list_head need_pages;
 546                 unsigned i;
 547
 548                 r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
 549                                            &duplicates);
 550                 if (unlikely(r != 0)) {
 551                         if (r != -ERESTARTSYS)
 552                                 DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
 553                         goto error_free_pages;
 554                 }
 555
 556                 /* Without a BO list we don't have userptr BOs */
 557                 if (!p->bo_list)
 558                         break;
 559
 560                 INIT_LIST_HEAD(&need_pages);
 561                 for (i = p->bo_list->first_userptr;
 562                      i < p->bo_list->num_entries; ++i) {
 563                         struct amdgpu_bo *bo;
 564
 565                         e = &p->bo_list->array[i];
 566                         bo = e->robj;
 567
 568                         if (amdgpu_ttm_tt_userptr_invalidated(bo->tbo.ttm,
 569                                  &e->user_invalidated) && e->user_pages) {
 570
 571                                 /* We acquired a page array, but somebody
 572                                  * invalidated it. Free it and try again
 573                                  */
 574                                 release_pages(e->user_pages,
 575                                               bo->tbo.ttm->num_pages);
 576                                 kvfree(e->user_pages);
 577                                 e->user_pages = NULL;
 578                         }
 579
 580                         if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) &&
 581                             !e->user_pages) {
 582                                 list_del(&e->tv.head);
 583                                 list_add(&e->tv.head, &need_pages);
 584
 585                                 amdgpu_bo_unreserve(e->robj);
 586                         }
 587                 }
 588
 589                 if (list_empty(&need_pages))
 590                         break;
 591
 592                 /* Unreserve everything again. */
 593                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 594
 595                 /* We tried too many times, just abort */
 596                 if (!--tries) {
 597                         r = -EDEADLK;
 598                         DRM_ERROR("deadlock in %s\n", __func__);
 599                         goto error_free_pages;
 600                 }
 601
 602                 /* Fill the page arrays for all userptrs. */
 603                 list_for_each_entry(e, &need_pages, tv.head) {
 604                         struct ttm_tt *ttm = e->robj->tbo.ttm;
 605
 606                         e->user_pages = kvmalloc_array(ttm->num_pages,
 607                                                          sizeof(struct page*),
 608                                                          GFP_KERNEL | __GFP_ZERO);
 609                         if (!e->user_pages) {
 610                                 r = -ENOMEM;
 611                                 DRM_ERROR("calloc failure in %s\n", __func__);
 612                                 goto error_free_pages;
 613                         }
 614
 615                         r = amdgpu_ttm_tt_get_user_pages(ttm, e->user_pages);
 616                         if (r) {
 617                                 DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n");
 618                                 kvfree(e->user_pages);
 619                                 e->user_pages = NULL;
 620                                 goto error_free_pages;
 621                         }
 622                 }
 623
 624                 /* And try again. */
 625                 list_splice(&need_pages, &p->validated);
 626         }
 627
 628         amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold,
 629                                           &p->bytes_moved_vis_threshold);
 630         p->bytes_moved = 0;
 631         p->bytes_moved_vis = 0;
 632         p->evictable = list_last_entry(&p->validated,
 633                                        struct amdgpu_bo_list_entry,
 634                                        tv.head);
 635
 636         r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm,
 637                                       amdgpu_cs_validate, p);
 638         if (r) {
 639                 DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
 640                 goto error_validate;
 641         }
 642
 643         r = amdgpu_cs_list_validate(p, &duplicates);
 644         if (r) {
 645                 DRM_ERROR("amdgpu_cs_list_validate(duplicates) failed.\n");
 646                 goto error_validate;
 647         }
 648
 649         r = amdgpu_cs_list_validate(p, &p->validated);
 650         if (r) {
 651                 DRM_ERROR("amdgpu_cs_list_validate(validated) failed.\n");
 652                 goto error_validate;
 653         }
 654
 655         amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved,
 656                                      p->bytes_moved_vis);
 657         if (p->bo_list) {
 658                 struct amdgpu_bo *gds = p->bo_list->gds_obj;
 659                 struct amdgpu_bo *gws = p->bo_list->gws_obj;
 660                 struct amdgpu_bo *oa = p->bo_list->oa_obj;
 661                 struct amdgpu_vm *vm = &fpriv->vm;
 662                 unsigned i;
 663
 664                 for (i = 0; i < p->bo_list->num_entries; i++) {
 665                         struct amdgpu_bo *bo = p->bo_list->array[i].robj;
 666
 667                         p->bo_list->array[i].bo_va = amdgpu_vm_bo_find(vm, bo);
 668                 }
 669
 670                 if (gds) {
 671                         p->job->gds_base = amdgpu_bo_gpu_offset(gds);
 672                         p->job->gds_size = amdgpu_bo_size(gds);
 673                 }
 674                 if (gws) {
 675                         p->job->gws_base = amdgpu_bo_gpu_offset(gws);
 676                         p->job->gws_size = amdgpu_bo_size(gws);
 677                 }
 678                 if (oa) {
 679                         p->job->oa_base = amdgpu_bo_gpu_offset(oa);
 680                         p->job->oa_size = amdgpu_bo_size(oa);
 681                 }
 682         }
 683
 684         if (!r && p->uf_entry.robj) {
 685                 struct amdgpu_bo *uf = p->uf_entry.robj;
 686
 687                 r = amdgpu_ttm_bind(&uf->tbo);
 688                 p->job->uf_addr += amdgpu_bo_gpu_offset(uf);
 689         }
 690
 691 error_validate:
 692         if (r)
 693                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 694
 695 error_free_pages:
 696
 697         if (p->bo_list) {
 698                 for (i = p->bo_list->first_userptr;
 699                      i < p->bo_list->num_entries; ++i) {
 700                         e = &p->bo_list->array[i];
 701
 702                         if (!e->user_pages)
 703                                 continue;
 704
 705                         release_pages(e->user_pages,
 706                                       e->robj->tbo.ttm->num_pages);
 707                         kvfree(e->user_pages);
 708                 }
 709         }
 710
 711         return r;
 712 }
 713
 714 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
 715 {
 716         struct amdgpu_bo_list_entry *e;
 717         int r;
 718
 719         list_for_each_entry(e, &p->validated, tv.head) {
 720                 struct reservation_object *resv = e->robj->tbo.resv;
 721                 r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp,
 722                                      amdgpu_bo_explicit_sync(e->robj));
 723
 724                 if (r)
 725                         return r;
 726         }
 727         return 0;
 728 }
 729
 730 /**
 731  * cs_parser_fini() - clean parser states
 732  * @parser:     parser structure holding parsing context.
 733  * @error:      error number
 734  *
 735  * If error is set than unvalidate buffer, otherwise just free memory
 736  * used by parsing context.
 737  **/
 738 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error,
 739                                   bool backoff)
 740 {
 741         unsigned i;
 742
 743         if (error && backoff)
 744                 ttm_eu_backoff_reservation(&parser->ticket,
 745                                            &parser->validated);
 746
 747         for (i = 0; i < parser->num_post_dep_syncobjs; i++)
 748                 drm_syncobj_put(parser->post_dep_syncobjs[i]);
 749         kfree(parser->post_dep_syncobjs);
 750
 751         dma_fence_put(parser->fence);
 752
 753         if (parser->ctx) {
 754                 mutex_unlock(&parser->ctx->lock);
 755                 amdgpu_ctx_put(parser->ctx);
 756         }
 757         if (parser->bo_list)
 758                 amdgpu_bo_list_put(parser->bo_list);
 759
 760         for (i = 0; i < parser->nchunks; i++)
 761                 kvfree(parser->chunks[i].kdata);
 762         kfree(parser->chunks);
 763         if (parser->job)
 764                 amdgpu_job_free(parser->job);
 765         amdgpu_bo_unref(&parser->uf_entry.robj);
 766 }
 767
 768 static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p)
 769 {
 770         struct amdgpu_device *adev = p->adev;
 771         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 772         struct amdgpu_vm *vm = &fpriv->vm;
 773         struct amdgpu_bo_va *bo_va;
 774         struct amdgpu_bo *bo;
 775         int i, r;
 776
 777         r = amdgpu_vm_update_directories(adev, vm);
 778         if (r)
 779                 return r;
 780
 781         r = amdgpu_vm_clear_freed(adev, vm, NULL);
 782         if (r)
 783                 return r;
 784
 785         r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false);
 786         if (r)
 787                 return r;
 788
 789         r = amdgpu_sync_fence(adev, &p->job->sync,
 790                               fpriv->prt_va->last_pt_update);
 791         if (r)
 792                 return r;
 793
 794         if (amdgpu_sriov_vf(adev)) {
 795                 struct dma_fence *f;
 796
 797                 bo_va = fpriv->csa_va;
 798                 BUG_ON(!bo_va);
 799                 r = amdgpu_vm_bo_update(adev, bo_va, false);
 800                 if (r)
 801                         return r;
 802
 803                 f = bo_va->last_pt_update;
 804                 r = amdgpu_sync_fence(adev, &p->job->sync, f);
 805                 if (r)
 806                         return r;
 807         }
 808
 809         if (p->bo_list) {
 810                 for (i = 0; i < p->bo_list->num_entries; i++) {
 811                         struct dma_fence *f;
 812
 813                         /* ignore duplicates */
 814                         bo = p->bo_list->array[i].robj;
 815                         if (!bo)
 816                                 continue;
 817
 818                         bo_va = p->bo_list->array[i].bo_va;
 819                         if (bo_va == NULL)
 820                                 continue;
 821
 822                         r = amdgpu_vm_bo_update(adev, bo_va, false);
 823                         if (r)
 824                                 return r;
 825
 826                         f = bo_va->last_pt_update;
 827                         r = amdgpu_sync_fence(adev, &p->job->sync, f);
 828                         if (r)
 829                                 return r;
 830                 }
 831
 832         }
 833
 834         r = amdgpu_vm_handle_moved(adev, vm);
 835         if (r)
 836                 return r;
 837
 838         r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_update);
 839         if (r)
 840                 return r;
 841
 842         if (amdgpu_vm_debug && p->bo_list) {
 843                 /* Invalidate all BOs to test for userspace bugs */
 844                 for (i = 0; i < p->bo_list->num_entries; i++) {
 845                         /* ignore duplicates */
 846                         bo = p->bo_list->array[i].robj;
 847                         if (!bo)
 848                                 continue;
 849
 850                         amdgpu_vm_bo_invalidate(adev, bo, false);
 851                 }
 852         }
 853
 854         return r;
 855 }
 856
 857 static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
 858                                  struct amdgpu_cs_parser *p)
 859 {
 860         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 861         struct amdgpu_vm *vm = &fpriv->vm;
 862         struct amdgpu_ring *ring = p->job->ring;
 863         int r;
 864
 865         /* Only for UVD/VCE VM emulation */
 866         if (p->job->ring->funcs->parse_cs) {
 867                 unsigned i, j;
 868
 869                 for (i = 0, j = 0; i < p->nchunks && j < p->job->num_ibs; i++) {
 870                         struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 871                         struct amdgpu_bo_va_mapping *m;
 872                         struct amdgpu_bo *aobj = NULL;
 873                         struct amdgpu_cs_chunk *chunk;
 874                         struct amdgpu_ib *ib;
 875                         uint64_t offset;
 876                         uint8_t *kptr;
 877
 878                         chunk = &p->chunks[i];
 879                         ib = &p->job->ibs[j];
 880                         chunk_ib = chunk->kdata;
 881
 882                         if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 883                                 continue;
 884
 885                         r = amdgpu_cs_find_mapping(p, chunk_ib->va_start,
 886                                                    &aobj, &m);
 887                         if (r) {
 888                                 DRM_ERROR("IB va_start is invalid\n");
 889                                 return r;
 890                         }
 891
 892                         if ((chunk_ib->va_start + chunk_ib->ib_bytes) >
 893                             (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 894                                 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
 895                                 return -EINVAL;
 896                         }
 897
 898                         /* the IB should be reserved at this point */
 899                         r = amdgpu_bo_kmap(aobj, (void **)&kptr);
 900                         if (r) {
 901                                 return r;
 902                         }
 903
 904                         offset = m->start * AMDGPU_GPU_PAGE_SIZE;
 905                         kptr += chunk_ib->va_start - offset;
 906
 907                         memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
 908                         amdgpu_bo_kunmap(aobj);
 909
 910                         r = amdgpu_ring_parse_cs(ring, p, j);
 911                         if (r)
 912                                 return r;
 913
 914                         j++;
 915                 }
 916         }
 917
 918         if (p->job->vm) {
 919                 p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->root.base.bo);
 920
 921                 r = amdgpu_bo_vm_update_pte(p);
 922                 if (r)
 923                         return r;
 924         }
 925
 926         return amdgpu_cs_sync_rings(p);
 927 }
 928
 929 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
 930                              struct amdgpu_cs_parser *parser)
 931 {
 932         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 933         struct amdgpu_vm *vm = &fpriv->vm;
 934         int i, j;
 935         int r, ce_preempt = 0, de_preempt = 0;
 936
 937         for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) {
 938                 struct amdgpu_cs_chunk *chunk;
 939                 struct amdgpu_ib *ib;
 940                 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 941                 struct amdgpu_ring *ring;
 942
 943                 chunk = &parser->chunks[i];
 944                 ib = &parser->job->ibs[j];
 945                 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
 946
 947                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 948                         continue;
 949
 950                 if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX && amdgpu_sriov_vf(adev)) {
 951                         if (chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
 952                                 if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
 953                                         ce_preempt++;
 954                                 else
 955                                         de_preempt++;
 956                         }
 957
 958                         /* each GFX command submit allows 0 or 1 IB preemptible for CE & DE */
 959                         if (ce_preempt > 1 || de_preempt > 1)
 960                                 return -EINVAL;
 961                 }
 962
 963                 r = amdgpu_queue_mgr_map(adev, &parser->ctx->queue_mgr, chunk_ib->ip_type,
 964                                          chunk_ib->ip_instance, chunk_ib->ring, &ring);
 965                 if (r)
 966                         return r;
 967
 968                 if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE) {
 969                         parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT;
 970                         if (!parser->ctx->preamble_presented) {
 971                                 parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;
 972                                 parser->ctx->preamble_presented = true;
 973                         }
 974                 }
 975
 976                 if (parser->job->ring && parser->job->ring != ring)
 977                         return -EINVAL;
 978
 979                 parser->job->ring = ring;
 980
 981                 r =  amdgpu_ib_get(adev, vm,
 982                                         ring->funcs->parse_cs ? chunk_ib->ib_bytes : 0,
 983                                         ib);
 984                 if (r) {
 985                         DRM_ERROR("Failed to get ib !\n");
 986                         return r;
 987                 }
 988
 989                 ib->gpu_addr = chunk_ib->va_start;
 990                 ib->length_dw = chunk_ib->ib_bytes / 4;
 991                 ib->flags = chunk_ib->flags;
 992
 993                 j++;
 994         }
 995
 996         /* UVD & VCE fw doesn't support user fences */
 997         if (parser->job->uf_addr && (
 998             parser->job->ring->funcs->type == AMDGPU_RING_TYPE_UVD ||
 999             parser->job->ring->funcs->type == AMDGPU_RING_TYPE_VCE))
1000                 return -EINVAL;
1001
1002         return amdgpu_ctx_wait_prev_fence(parser->ctx, parser->job->ring->idx);
1003 }
1004
1005 static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,
1006                                        struct amdgpu_cs_chunk *chunk)
1007 {
1008         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1009         unsigned num_deps;
1010         int i, r;
1011         struct drm_amdgpu_cs_chunk_dep *deps;
1012
1013         deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
1014         num_deps = chunk->length_dw * 4 /
1015                 sizeof(struct drm_amdgpu_cs_chunk_dep);
1016
1017         for (i = 0; i < num_deps; ++i) {
1018                 struct amdgpu_ring *ring;
1019                 struct amdgpu_ctx *ctx;
1020                 struct dma_fence *fence;
1021
1022                 ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
1023                 if (ctx == NULL)
1024                         return -EINVAL;
1025
1026                 r = amdgpu_queue_mgr_map(p->adev, &ctx->queue_mgr,
1027                                          deps[i].ip_type,
1028                                          deps[i].ip_instance,
1029                                          deps[i].ring, &ring);
1030                 if (r) {
1031                         amdgpu_ctx_put(ctx);
1032                         return r;
1033                 }
1034
1035                 fence = amdgpu_ctx_get_fence(ctx, ring,
1036                                              deps[i].handle);
1037                 if (IS_ERR(fence)) {
1038                         r = PTR_ERR(fence);
1039                         amdgpu_ctx_put(ctx);
1040                         return r;
1041                 } else if (fence) {
1042                         r = amdgpu_sync_fence(p->adev, &p->job->sync,
1043                                               fence);
1044                         dma_fence_put(fence);
1045                         amdgpu_ctx_put(ctx);
1046                         if (r)
1047                                 return r;
1048                 }
1049         }
1050         return 0;
1051 }
1052
1053 static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,
1054                                                  uint32_t handle)
1055 {
1056         int r;
1057         struct dma_fence *fence;
1058         r = drm_syncobj_find_fence(p->filp, handle, &fence);
1059         if (r)
1060                 return r;
1061
1062         r = amdgpu_sync_fence(p->adev, &p->job->sync, fence);
1063         dma_fence_put(fence);
1064
1065         return r;
1066 }
1067
1068 static int amdgpu_cs_process_syncobj_in_dep(struct amdgpu_cs_parser *p,
1069                                             struct amdgpu_cs_chunk *chunk)
1070 {
1071         unsigned num_deps;
1072         int i, r;
1073         struct drm_amdgpu_cs_chunk_sem *deps;
1074
1075         deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1076         num_deps = chunk->length_dw * 4 /
1077                 sizeof(struct drm_amdgpu_cs_chunk_sem);
1078
1079         for (i = 0; i < num_deps; ++i) {
1080                 r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle);
1081                 if (r)
1082                         return r;
1083         }
1084         return 0;
1085 }
1086
1087 static int amdgpu_cs_process_syncobj_out_dep(struct amdgpu_cs_parser *p,
1088                                              struct amdgpu_cs_chunk *chunk)
1089 {
1090         unsigned num_deps;
1091         int i;
1092         struct drm_amdgpu_cs_chunk_sem *deps;
1093         deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1094         num_deps = chunk->length_dw * 4 /
1095                 sizeof(struct drm_amdgpu_cs_chunk_sem);
1096
1097         p->post_dep_syncobjs = kmalloc_array(num_deps,
1098                                              sizeof(struct drm_syncobj *),
1099                                              GFP_KERNEL);
1100         p->num_post_dep_syncobjs = 0;
1101
1102         if (!p->post_dep_syncobjs)
1103                 return -ENOMEM;
1104
1105         for (i = 0; i < num_deps; ++i) {
1106                 p->post_dep_syncobjs[i] = drm_syncobj_find(p->filp, deps[i].handle);
1107                 if (!p->post_dep_syncobjs[i])
1108                         return -EINVAL;
1109                 p->num_post_dep_syncobjs++;
1110         }
1111         return 0;
1112 }
1113
1114 static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
1115                                   struct amdgpu_cs_parser *p)
1116 {
1117         int i, r;
1118
1119         for (i = 0; i < p->nchunks; ++i) {
1120                 struct amdgpu_cs_chunk *chunk;
1121
1122                 chunk = &p->chunks[i];
1123
1124                 if (chunk->chunk_id == AMDGPU_CHUNK_ID_DEPENDENCIES) {
1125                         r = amdgpu_cs_process_fence_dep(p, chunk);
1126                         if (r)
1127                                 return r;
1128                 } else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_IN) {
1129                         r = amdgpu_cs_process_syncobj_in_dep(p, chunk);
1130                         if (r)
1131                                 return r;
1132                 } else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_OUT) {
1133                         r = amdgpu_cs_process_syncobj_out_dep(p, chunk);
1134                         if (r)
1135                                 return r;
1136                 }
1137         }
1138
1139         return 0;
1140 }
1141
1142 static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p)
1143 {
1144         int i;
1145
1146         for (i = 0; i < p->num_post_dep_syncobjs; ++i)
1147                 drm_syncobj_replace_fence(p->post_dep_syncobjs[i], p->fence);
1148 }
1149
1150 static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
1151                             union drm_amdgpu_cs *cs)
1152 {
1153         struct amdgpu_ring *ring = p->job->ring;
1154         struct amd_sched_entity *entity = &p->ctx->rings[ring->idx].entity;
1155         struct amdgpu_job *job;
1156         unsigned i;
1157         uint64_t seq;
1158
1159         int r;
1160
1161         amdgpu_mn_lock(p->mn);
1162         if (p->bo_list) {
1163                 for (i = p->bo_list->first_userptr;
1164                      i < p->bo_list->num_entries; ++i) {
1165                         struct amdgpu_bo *bo = p->bo_list->array[i].robj;
1166
1167                         if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm)) {
1168                                 amdgpu_mn_unlock(p->mn);
1169                                 return -ERESTARTSYS;
1170                         }
1171                 }
1172         }
1173
1174         job = p->job;
1175         p->job = NULL;
1176
1177         r = amd_sched_job_init(&job->base, &ring->sched, entity, p->filp);
1178         if (r) {
1179                 amdgpu_job_free(job);
1180                 amdgpu_mn_unlock(p->mn);
1181                 return r;
1182         }
1183
1184         job->owner = p->filp;
1185         job->fence_ctx = entity->fence_context;
1186         p->fence = dma_fence_get(&job->base.s_fence->finished);
1187
1188         r = amdgpu_ctx_add_fence(p->ctx, ring, p->fence, &seq);
1189         if (r) {
1190                 dma_fence_put(p->fence);
1191                 dma_fence_put(&job->base.s_fence->finished);
1192                 amdgpu_job_free(job);
1193                 amdgpu_mn_unlock(p->mn);
1194                 return r;
1195         }
1196
1197         amdgpu_cs_post_dependencies(p);
1198
1199         cs->out.handle = seq;
1200         job->uf_sequence = seq;
1201
1202         amdgpu_job_free_resources(job);
1203         amdgpu_ring_priority_get(job->ring, job->base.s_priority);
1204
1205         trace_amdgpu_cs_ioctl(job);
1206         amd_sched_entity_push_job(&job->base, entity);
1207
1208         ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence);
1209         amdgpu_mn_unlock(p->mn);
1210
1211         return 0;
1212 }
1213
1214 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
1215 {
1216         struct amdgpu_device *adev = dev->dev_private;
1217         union drm_amdgpu_cs *cs = data;
1218         struct amdgpu_cs_parser parser = {};
1219         bool reserved_buffers = false;
1220         int i, r;
1221
1222         if (!adev->accel_working)
1223                 return -EBUSY;
1224
1225         parser.adev = adev;
1226         parser.filp = filp;
1227
1228         r = amdgpu_cs_parser_init(&parser, data);
1229         if (r) {
1230                 DRM_ERROR("Failed to initialize parser !\n");
1231                 goto out;
1232         }
1233
1234         r = amdgpu_cs_ib_fill(adev, &parser);
1235         if (r)
1236                 goto out;
1237
1238         r = amdgpu_cs_parser_bos(&parser, data);
1239         if (r) {
1240                 if (r == -ENOMEM)
1241                         DRM_ERROR("Not enough memory for command submission!\n");
1242                 else if (r != -ERESTARTSYS)
1243                         DRM_ERROR("Failed to process the buffer list %d!\n", r);
1244                 goto out;
1245         }
1246
1247         reserved_buffers = true;
1248
1249         r = amdgpu_cs_dependencies(adev, &parser);
1250         if (r) {
1251                 DRM_ERROR("Failed in the dependencies handling %d!\n", r);
1252                 goto out;
1253         }
1254
1255         for (i = 0; i < parser.job->num_ibs; i++)
1256                 trace_amdgpu_cs(&parser, i);
1257
1258         r = amdgpu_cs_ib_vm_chunk(adev, &parser);
1259         if (r)
1260                 goto out;
1261
1262         r = amdgpu_cs_submit(&parser, cs);
1263
1264 out:
1265         amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
1266         return r;
1267 }
1268
1269 /**
1270  * amdgpu_cs_wait_ioctl - wait for a command submission to finish
1271  *
1272  * @dev: drm device
1273  * @data: data from userspace
1274  * @filp: file private
1275  *
1276  * Wait for the command submission identified by handle to finish.
1277  */
1278 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
1279                          struct drm_file *filp)
1280 {
1281         union drm_amdgpu_wait_cs *wait = data;
1282         struct amdgpu_device *adev = dev->dev_private;
1283         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
1284         struct amdgpu_ring *ring = NULL;
1285         struct amdgpu_ctx *ctx;
1286         struct dma_fence *fence;
1287         long r;
1288
1289         ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
1290         if (ctx == NULL)
1291                 return -EINVAL;
1292
1293         r = amdgpu_queue_mgr_map(adev, &ctx->queue_mgr,
1294                                  wait->in.ip_type, wait->in.ip_instance,
1295                                  wait->in.ring, &ring);
1296         if (r) {
1297                 amdgpu_ctx_put(ctx);
1298                 return r;
1299         }
1300
1301         fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle);
1302         if (IS_ERR(fence))
1303                 r = PTR_ERR(fence);
1304         else if (fence) {
1305                 r = dma_fence_wait_timeout(fence, true, timeout);
1306                 if (r > 0 && fence->error)
1307                         r = fence->error;
1308                 dma_fence_put(fence);
1309         } else
1310                 r = 1;
1311
1312         amdgpu_ctx_put(ctx);
1313         if (r < 0)
1314                 return r;
1315
1316         memset(wait, 0, sizeof(*wait));
1317         wait->out.status = (r == 0);
1318
1319         return 0;
1320 }
1321
1322 /**
1323  * amdgpu_cs_get_fence - helper to get fence from drm_amdgpu_fence
1324  *
1325  * @adev: amdgpu device
1326  * @filp: file private
1327  * @user: drm_amdgpu_fence copied from user space
1328  */
1329 static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev,
1330                                              struct drm_file *filp,
1331                                              struct drm_amdgpu_fence *user)
1332 {
1333         struct amdgpu_ring *ring;
1334         struct amdgpu_ctx *ctx;
1335         struct dma_fence *fence;
1336         int r;
1337
1338         ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id);
1339         if (ctx == NULL)
1340                 return ERR_PTR(-EINVAL);
1341
1342         r = amdgpu_queue_mgr_map(adev, &ctx->queue_mgr, user->ip_type,
1343                                  user->ip_instance, user->ring, &ring);
1344         if (r) {
1345                 amdgpu_ctx_put(ctx);
1346                 return ERR_PTR(r);
1347         }
1348
1349         fence = amdgpu_ctx_get_fence(ctx, ring, user->seq_no);
1350         amdgpu_ctx_put(ctx);
1351
1352         return fence;
1353 }
1354
1355 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
1356                                     struct drm_file *filp)
1357 {
1358         struct amdgpu_device *adev = dev->dev_private;
1359         union drm_amdgpu_fence_to_handle *info = data;
1360         struct dma_fence *fence;
1361         struct drm_syncobj *syncobj;
1362         struct sync_file *sync_file;
1363         int fd, r;
1364
1365         fence = amdgpu_cs_get_fence(adev, filp, &info->in.fence);
1366         if (IS_ERR(fence))
1367                 return PTR_ERR(fence);
1368
1369         switch (info->in.what) {
1370         case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
1371                 r = drm_syncobj_create(&syncobj, 0, fence);
1372                 dma_fence_put(fence);
1373                 if (r)
1374                         return r;
1375                 r = drm_syncobj_get_handle(filp, syncobj, &info->out.handle);
1376                 drm_syncobj_put(syncobj);
1377                 return r;
1378
1379         case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD:
1380                 r = drm_syncobj_create(&syncobj, 0, fence);
1381                 dma_fence_put(fence);
1382                 if (r)
1383                         return r;
1384                 r = drm_syncobj_get_fd(syncobj, (int*)&info->out.handle);
1385                 drm_syncobj_put(syncobj);
1386                 return r;
1387
1388         case AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD:
1389                 fd = get_unused_fd_flags(O_CLOEXEC);
1390                 if (fd < 0) {
1391                         dma_fence_put(fence);
1392                         return fd;
1393                 }
1394
1395                 sync_file = sync_file_create(fence);
1396                 dma_fence_put(fence);
1397                 if (!sync_file) {
1398                         put_unused_fd(fd);
1399                         return -ENOMEM;
1400                 }
1401
1402                 fd_install(fd, sync_file->file);
1403                 info->out.handle = fd;
1404                 return 0;
1405
1406         default:
1407                 return -EINVAL;
1408         }
1409 }
1410
1411 /**
1412  * amdgpu_cs_wait_all_fence - wait on all fences to signal
1413  *
1414  * @adev: amdgpu device
1415  * @filp: file private
1416  * @wait: wait parameters
1417  * @fences: array of drm_amdgpu_fence
1418  */
1419 static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
1420                                      struct drm_file *filp,
1421                                      union drm_amdgpu_wait_fences *wait,
1422                                      struct drm_amdgpu_fence *fences)
1423 {
1424         uint32_t fence_count = wait->in.fence_count;
1425         unsigned int i;
1426         long r = 1;
1427
1428         for (i = 0; i < fence_count; i++) {
1429                 struct dma_fence *fence;
1430                 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1431
1432                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1433                 if (IS_ERR(fence))
1434                         return PTR_ERR(fence);
1435                 else if (!fence)
1436                         continue;
1437
1438                 r = dma_fence_wait_timeout(fence, true, timeout);
1439                 dma_fence_put(fence);
1440                 if (r < 0)
1441                         return r;
1442
1443                 if (r == 0)
1444                         break;
1445
1446                 if (fence->error)
1447                         return fence->error;
1448         }
1449
1450         memset(wait, 0, sizeof(*wait));
1451         wait->out.status = (r > 0);
1452
1453         return 0;
1454 }
1455
1456 /**
1457  * amdgpu_cs_wait_any_fence - wait on any fence to signal
1458  *
1459  * @adev: amdgpu device
1460  * @filp: file private
1461  * @wait: wait parameters
1462  * @fences: array of drm_amdgpu_fence
1463  */
1464 static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev,
1465                                     struct drm_file *filp,
1466                                     union drm_amdgpu_wait_fences *wait,
1467                                     struct drm_amdgpu_fence *fences)
1468 {
1469         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1470         uint32_t fence_count = wait->in.fence_count;
1471         uint32_t first = ~0;
1472         struct dma_fence **array;
1473         unsigned int i;
1474         long r;
1475
1476         /* Prepare the fence array */
1477         array = kcalloc(fence_count, sizeof(struct dma_fence *), GFP_KERNEL);
1478
1479         if (array == NULL)
1480                 return -ENOMEM;
1481
1482         for (i = 0; i < fence_count; i++) {
1483                 struct dma_fence *fence;
1484
1485                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1486                 if (IS_ERR(fence)) {
1487                         r = PTR_ERR(fence);
1488                         goto err_free_fence_array;
1489                 } else if (fence) {
1490                         array[i] = fence;
1491                 } else { /* NULL, the fence has been already signaled */
1492                         r = 1;
1493                         first = i;
1494                         goto out;
1495                 }
1496         }
1497
1498         r = dma_fence_wait_any_timeout(array, fence_count, true, timeout,
1499                                        &first);
1500         if (r < 0)
1501                 goto err_free_fence_array;
1502
1503 out:
1504         memset(wait, 0, sizeof(*wait));
1505         wait->out.status = (r > 0);
1506         wait->out.first_signaled = first;
1507
1508         if (first < fence_count && array[first])
1509                 r = array[first]->error;
1510         else
1511                 r = 0;
1512
1513 err_free_fence_array:
1514         for (i = 0; i < fence_count; i++)
1515                 dma_fence_put(array[i]);
1516         kfree(array);
1517
1518         return r;
1519 }
1520
1521 /**
1522  * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to finish
1523  *
1524  * @dev: drm device
1525  * @data: data from userspace
1526  * @filp: file private
1527  */
1528 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1529                                 struct drm_file *filp)
1530 {
1531         struct amdgpu_device *adev = dev->dev_private;
1532         union drm_amdgpu_wait_fences *wait = data;
1533         uint32_t fence_count = wait->in.fence_count;
1534         struct drm_amdgpu_fence *fences_user;
1535         struct drm_amdgpu_fence *fences;
1536         int r;
1537
1538         /* Get the fences from userspace */
1539         fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence),
1540                         GFP_KERNEL);
1541         if (fences == NULL)
1542                 return -ENOMEM;
1543
1544         fences_user = u64_to_user_ptr(wait->in.fences);
1545         if (copy_from_user(fences, fences_user,
1546                 sizeof(struct drm_amdgpu_fence) * fence_count)) {
1547                 r = -EFAULT;
1548                 goto err_free_fences;
1549         }
1550
1551         if (wait->in.wait_all)
1552                 r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences);
1553         else
1554                 r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences);
1555
1556 err_free_fences:
1557         kfree(fences);
1558
1559         return r;
1560 }
1561
1562 /**
1563  * amdgpu_cs_find_bo_va - find bo_va for VM address
1564  *
1565  * @parser: command submission parser context
1566  * @addr: VM address
1567  * @bo: resulting BO of the mapping found
1568  *
1569  * Search the buffer objects in the command submission context for a certain
1570  * virtual memory address. Returns allocation structure when found, NULL
1571  * otherwise.
1572  */
1573 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1574                            uint64_t addr, struct amdgpu_bo **bo,
1575                            struct amdgpu_bo_va_mapping **map)
1576 {
1577         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
1578         struct amdgpu_vm *vm = &fpriv->vm;
1579         struct amdgpu_bo_va_mapping *mapping;
1580         int r;
1581
1582         addr /= AMDGPU_GPU_PAGE_SIZE;
1583
1584         mapping = amdgpu_vm_bo_lookup_mapping(vm, addr);
1585         if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo)
1586                 return -EINVAL;
1587
1588         *bo = mapping->bo_va->base.bo;
1589         *map = mapping;
1590
1591         /* Double check that the BO is reserved by this CS */
1592         if (READ_ONCE((*bo)->tbo.resv->lock.ctx) != &parser->ticket)
1593                 return -EINVAL;
1594
1595         if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {
1596                 (*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1597                 amdgpu_ttm_placement_from_domain(*bo, (*bo)->allowed_domains);
1598                 r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, false,
1599                                     false);
1600                 if (r)
1601                         return r;
1602         }
1603
1604         return amdgpu_ttm_bind(&(*bo)->tbo);
1605 }