drivers/gpu/drm/amd/amdgpu/soc15.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <drm/drmP.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_atombios.h"
  29 #include "amdgpu_ih.h"
  30 #include "amdgpu_uvd.h"
  31 #include "amdgpu_vce.h"
  32 #include "amdgpu_ucode.h"
  33 #include "amdgpu_psp.h"
  34 #include "atom.h"
  35 #include "amd_pcie.h"
  36
  37 #include "uvd/uvd_7_0_offset.h"
  38 #include "gc/gc_9_0_offset.h"
  39 #include "gc/gc_9_0_sh_mask.h"
  40 #include "sdma0/sdma0_4_0_offset.h"
  41 #include "sdma1/sdma1_4_0_offset.h"
  42 #include "hdp/hdp_4_0_offset.h"
  43 #include "hdp/hdp_4_0_sh_mask.h"
  44 #include "smuio/smuio_9_0_offset.h"
  45 #include "smuio/smuio_9_0_sh_mask.h"
  46 #include "nbio/nbio_7_0_default.h"
  47 #include "nbio/nbio_7_0_offset.h"
  48 #include "nbio/nbio_7_0_sh_mask.h"
  49 #include "nbio/nbio_7_0_smn.h"
  50 #include "mp/mp_9_0_offset.h"
  51
  52 #include "soc15.h"
  53 #include "soc15_common.h"
  54 #include "gfx_v9_0.h"
  55 #include "gmc_v9_0.h"
  56 #include "gfxhub_v1_0.h"
  57 #include "mmhub_v1_0.h"
  58 #include "df_v1_7.h"
  59 #include "df_v3_6.h"
  60 #include "vega10_ih.h"
  61 #include "sdma_v4_0.h"
  62 #include "uvd_v7_0.h"
  63 #include "vce_v4_0.h"
  64 #include "vcn_v1_0.h"
  65 #include "dce_virtual.h"
  66 #include "mxgpu_ai.h"
  67 #include "amdgpu_smu.h"
  68 #include "amdgpu_ras.h"
  69 #include "amdgpu_xgmi.h"
  70 #include <uapi/linux/kfd_ioctl.h>
  71
  72 #define mmMP0_MISC_CGTT_CTRL0                                                                   0x01b9
  73 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX                                                          0
  74 #define mmMP0_MISC_LIGHT_SLEEP_CTRL                                                             0x01ba
  75 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX                                                    0
  76
  77 /* for Vega20 register name change */
  78 #define mmHDP_MEM_POWER_CTRL    0x00d4
  79 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK  0x00000001L
  80 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK    0x00000002L
  81 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK   0x00010000L
  82 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK             0x00020000L
  83 #define mmHDP_MEM_POWER_CTRL_BASE_IDX   0
  84 /*
  85  * Indirect registers accessor
  86  */
  87 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
  88 {
  89         unsigned long flags, address, data;
  90         u32 r;
  91         address = adev->nbio_funcs->get_pcie_index_offset(adev);
  92         data = adev->nbio_funcs->get_pcie_data_offset(adev);
  93
  94         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  95         WREG32(address, reg);
  96         (void)RREG32(address);
  97         r = RREG32(data);
  98         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
  99         return r;
 100 }
 101
 102 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 103 {
 104         unsigned long flags, address, data;
 105
 106         address = adev->nbio_funcs->get_pcie_index_offset(adev);
 107         data = adev->nbio_funcs->get_pcie_data_offset(adev);
 108
 109         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 110         WREG32(address, reg);
 111         (void)RREG32(address);
 112         WREG32(data, v);
 113         (void)RREG32(data);
 114         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 115 }
 116
 117 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
 118 {
 119         unsigned long flags, address, data;
 120         u32 r;
 121
 122         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 123         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 124
 125         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 126         WREG32(address, ((reg) & 0x1ff));
 127         r = RREG32(data);
 128         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 129         return r;
 130 }
 131
 132 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 133 {
 134         unsigned long flags, address, data;
 135
 136         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 137         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 138
 139         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 140         WREG32(address, ((reg) & 0x1ff));
 141         WREG32(data, (v));
 142         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 143 }
 144
 145 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
 146 {
 147         unsigned long flags, address, data;
 148         u32 r;
 149
 150         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 151         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 152
 153         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 154         WREG32(address, (reg));
 155         r = RREG32(data);
 156         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 157         return r;
 158 }
 159
 160 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 161 {
 162         unsigned long flags, address, data;
 163
 164         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 165         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 166
 167         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 168         WREG32(address, (reg));
 169         WREG32(data, (v));
 170         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 171 }
 172
 173 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
 174 {
 175         unsigned long flags;
 176         u32 r;
 177
 178         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 179         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
 180         r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
 181         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 182         return r;
 183 }
 184
 185 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 186 {
 187         unsigned long flags;
 188
 189         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 190         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
 191         WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
 192         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 193 }
 194
 195 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
 196 {
 197         unsigned long flags;
 198         u32 r;
 199
 200         spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
 201         WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
 202         r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
 203         spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
 204         return r;
 205 }
 206
 207 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 208 {
 209         unsigned long flags;
 210
 211         spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
 212         WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
 213         WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
 214         spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
 215 }
 216
 217 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
 218 {
 219         return adev->nbio_funcs->get_memsize(adev);
 220 }
 221
 222 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 223 {
 224         return adev->clock.spll.reference_freq;
 225 }
 226
 227
 228 void soc15_grbm_select(struct amdgpu_device *adev,
 229                      u32 me, u32 pipe, u32 queue, u32 vmid)
 230 {
 231         u32 grbm_gfx_cntl = 0;
 232         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 233         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 234         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 235         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 236
 237         WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
 238 }
 239
 240 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
 241 {
 242         /* todo */
 243 }
 244
 245 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
 246 {
 247         /* todo */
 248         return false;
 249 }
 250
 251 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
 252                                      u8 *bios, u32 length_bytes)
 253 {
 254         u32 *dw_ptr;
 255         u32 i, length_dw;
 256
 257         if (bios == NULL)
 258                 return false;
 259         if (length_bytes == 0)
 260                 return false;
 261         /* APU vbios image is part of sbios image */
 262         if (adev->flags & AMD_IS_APU)
 263                 return false;
 264
 265         dw_ptr = (u32 *)bios;
 266         length_dw = ALIGN(length_bytes, 4) / 4;
 267
 268         /* set rom index to 0 */
 269         WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
 270         /* read out the rom data */
 271         for (i = 0; i < length_dw; i++)
 272                 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
 273
 274         return true;
 275 }
 276
 277 struct soc15_allowed_register_entry {
 278         uint32_t hwip;
 279         uint32_t inst;
 280         uint32_t seg;
 281         uint32_t reg_offset;
 282         bool grbm_indexed;
 283 };
 284
 285
 286 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
 287         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
 288         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
 289         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
 290         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
 291         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
 292         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
 293         { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
 294         { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
 295         { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
 296         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
 297         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
 298         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
 299         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
 300         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
 301         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
 302         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 303         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 304         { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
 305         { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
 306 };
 307
 308 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 309                                          u32 sh_num, u32 reg_offset)
 310 {
 311         uint32_t val;
 312
 313         mutex_lock(&adev->grbm_idx_mutex);
 314         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 315                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 316
 317         val = RREG32(reg_offset);
 318
 319         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 320                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 321         mutex_unlock(&adev->grbm_idx_mutex);
 322         return val;
 323 }
 324
 325 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
 326                                          bool indexed, u32 se_num,
 327                                          u32 sh_num, u32 reg_offset)
 328 {
 329         if (indexed) {
 330                 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
 331         } else {
 332                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
 333                         return adev->gfx.config.gb_addr_config;
 334                 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
 335                         return adev->gfx.config.db_debug2;
 336                 return RREG32(reg_offset);
 337         }
 338 }
 339
 340 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
 341                             u32 sh_num, u32 reg_offset, u32 *value)
 342 {
 343         uint32_t i;
 344         struct soc15_allowed_register_entry  *en;
 345
 346         *value = 0;
 347         for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
 348                 en = &soc15_allowed_read_registers[i];
 349                 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
 350                                         + en->reg_offset))
 351                         continue;
 352
 353                 *value = soc15_get_register_value(adev,
 354                                                   soc15_allowed_read_registers[i].grbm_indexed,
 355                                                   se_num, sh_num, reg_offset);
 356                 return 0;
 357         }
 358         return -EINVAL;
 359 }
 360
 361
 362 /**
 363  * soc15_program_register_sequence - program an array of registers.
 364  *
 365  * @adev: amdgpu_device pointer
 366  * @regs: pointer to the register array
 367  * @array_size: size of the register array
 368  *
 369  * Programs an array or registers with and and or masks.
 370  * This is a helper for setting golden registers.
 371  */
 372
 373 void soc15_program_register_sequence(struct amdgpu_device *adev,
 374                                              const struct soc15_reg_golden *regs,
 375                                              const u32 array_size)
 376 {
 377         const struct soc15_reg_golden *entry;
 378         u32 tmp, reg;
 379         int i;
 380
 381         for (i = 0; i < array_size; ++i) {
 382                 entry = &regs[i];
 383                 reg =  adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
 384
 385                 if (entry->and_mask == 0xffffffff) {
 386                         tmp = entry->or_mask;
 387                 } else {
 388                         tmp = RREG32(reg);
 389                         tmp &= ~(entry->and_mask);
 390                         tmp |= entry->or_mask;
 391                 }
 392
 393                 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
 394                         reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
 395                         reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
 396                         reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
 397                         WREG32_RLC(reg, tmp);
 398                 else
 399                         WREG32(reg, tmp);
 400
 401         }
 402
 403 }
 404
 405 static int soc15_asic_mode1_reset(struct amdgpu_device *adev)
 406 {
 407         u32 i;
 408         int ret = 0;
 409
 410         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 411
 412         dev_info(adev->dev, "GPU mode1 reset\n");
 413
 414         /* disable BM */
 415         pci_clear_master(adev->pdev);
 416
 417         pci_save_state(adev->pdev);
 418
 419         ret = psp_gpu_reset(adev);
 420         if (ret)
 421                 dev_err(adev->dev, "GPU mode1 reset failed\n");
 422
 423         pci_restore_state(adev->pdev);
 424
 425         /* wait for asic to come out of reset */
 426         for (i = 0; i < adev->usec_timeout; i++) {
 427                 u32 memsize = adev->nbio_funcs->get_memsize(adev);
 428
 429                 if (memsize != 0xffffffff)
 430                         break;
 431                 udelay(1);
 432         }
 433
 434         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 435
 436         return ret;
 437 }
 438
 439 static int soc15_asic_get_baco_capability(struct amdgpu_device *adev, bool *cap)
 440 {
 441         void *pp_handle = adev->powerplay.pp_handle;
 442         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 443
 444         if (!pp_funcs || !pp_funcs->get_asic_baco_capability) {
 445                 *cap = false;
 446                 return -ENOENT;
 447         }
 448
 449         return pp_funcs->get_asic_baco_capability(pp_handle, cap);
 450 }
 451
 452 static int soc15_asic_baco_reset(struct amdgpu_device *adev)
 453 {
 454         void *pp_handle = adev->powerplay.pp_handle;
 455         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 456
 457         if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state)
 458                 return -ENOENT;
 459
 460         /* enter BACO state */
 461         if (pp_funcs->set_asic_baco_state(pp_handle, 1))
 462                 return -EIO;
 463
 464         /* exit BACO state */
 465         if (pp_funcs->set_asic_baco_state(pp_handle, 0))
 466                 return -EIO;
 467
 468         dev_info(adev->dev, "GPU BACO reset\n");
 469
 470         adev->in_baco_reset = 1;
 471
 472         return 0;
 473 }
 474
 475 static int soc15_asic_reset(struct amdgpu_device *adev)
 476 {
 477         int ret;
 478         bool baco_reset;
 479
 480         switch (adev->asic_type) {
 481         case CHIP_VEGA10:
 482         case CHIP_VEGA12:
 483                 soc15_asic_get_baco_capability(adev, &baco_reset);
 484                 break;
 485         case CHIP_VEGA20:
 486                 if (adev->psp.sos_fw_version >= 0x80067)
 487                         soc15_asic_get_baco_capability(adev, &baco_reset);
 488                 else
 489                         baco_reset = false;
 490                 if (baco_reset) {
 491                         struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, 0);
 492                         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 493
 494                         if (hive || (ras && ras->supported))
 495                                 baco_reset = false;
 496                 }
 497                 break;
 498         default:
 499                 baco_reset = false;
 500                 break;
 501         }
 502
 503         if (baco_reset)
 504                 ret = soc15_asic_baco_reset(adev);
 505         else
 506                 ret = soc15_asic_mode1_reset(adev);
 507
 508         return ret;
 509 }
 510
 511 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
 512                         u32 cntl_reg, u32 status_reg)
 513 {
 514         return 0;
 515 }*/
 516
 517 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 518 {
 519         /*int r;
 520
 521         r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
 522         if (r)
 523                 return r;
 524
 525         r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
 526         */
 527         return 0;
 528 }
 529
 530 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 531 {
 532         /* todo */
 533
 534         return 0;
 535 }
 536
 537 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
 538 {
 539         if (pci_is_root_bus(adev->pdev->bus))
 540                 return;
 541
 542         if (amdgpu_pcie_gen2 == 0)
 543                 return;
 544
 545         if (adev->flags & AMD_IS_APU)
 546                 return;
 547
 548         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 549                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 550                 return;
 551
 552         /* todo */
 553 }
 554
 555 static void soc15_program_aspm(struct amdgpu_device *adev)
 556 {
 557
 558         if (amdgpu_aspm == 0)
 559                 return;
 560
 561         /* todo */
 562 }
 563
 564 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
 565                                            bool enable)
 566 {
 567         adev->nbio_funcs->enable_doorbell_aperture(adev, enable);
 568         adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable);
 569 }
 570
 571 static const struct amdgpu_ip_block_version vega10_common_ip_block =
 572 {
 573         .type = AMD_IP_BLOCK_TYPE_COMMON,
 574         .major = 2,
 575         .minor = 0,
 576         .rev = 0,
 577         .funcs = &soc15_common_ip_funcs,
 578 };
 579
 580 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
 581 {
 582         return adev->nbio_funcs->get_rev_id(adev);
 583 }
 584
 585 int soc15_set_ip_blocks(struct amdgpu_device *adev)
 586 {
 587         /* Set IP register base before any HW register access */
 588         switch (adev->asic_type) {
 589         case CHIP_VEGA10:
 590         case CHIP_VEGA12:
 591         case CHIP_RAVEN:
 592                 vega10_reg_base_init(adev);
 593                 break;
 594         case CHIP_VEGA20:
 595                 vega20_reg_base_init(adev);
 596                 break;
 597         default:
 598                 return -EINVAL;
 599         }
 600
 601         if (adev->asic_type == CHIP_VEGA20)
 602                 adev->gmc.xgmi.supported = true;
 603
 604         if (adev->flags & AMD_IS_APU)
 605                 adev->nbio_funcs = &nbio_v7_0_funcs;
 606         else if (adev->asic_type == CHIP_VEGA20)
 607                 adev->nbio_funcs = &nbio_v7_4_funcs;
 608         else
 609                 adev->nbio_funcs = &nbio_v6_1_funcs;
 610
 611         if (adev->asic_type == CHIP_VEGA20)
 612                 adev->df_funcs = &df_v3_6_funcs;
 613         else
 614                 adev->df_funcs = &df_v1_7_funcs;
 615
 616         adev->rev_id = soc15_get_rev_id(adev);
 617         adev->nbio_funcs->detect_hw_virt(adev);
 618
 619         if (amdgpu_sriov_vf(adev))
 620                 adev->virt.ops = &xgpu_ai_virt_ops;
 621
 622         switch (adev->asic_type) {
 623         case CHIP_VEGA10:
 624         case CHIP_VEGA12:
 625         case CHIP_VEGA20:
 626                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 627                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 628
 629                 /* For Vega10 SR-IOV, PSP need to be initialized before IH */
 630                 if (amdgpu_sriov_vf(adev)) {
 631                         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
 632                                 if (adev->asic_type == CHIP_VEGA20)
 633                                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 634                                 else
 635                                         amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
 636                         }
 637                         amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 638                 } else {
 639                         amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 640                         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
 641                                 if (adev->asic_type == CHIP_VEGA20)
 642                                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 643                                 else
 644                                         amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
 645                         }
 646                 }
 647                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 648                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 649                 if (!amdgpu_sriov_vf(adev)) {
 650                         if (is_support_sw_smu(adev))
 651                                 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 652                         else
 653                                 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
 654                 }
 655                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 656                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 657 #if defined(CONFIG_DRM_AMD_DC)
 658                 else if (amdgpu_device_has_dc_support(adev))
 659                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 660 #else
 661 #       warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
 662 #endif
 663                 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) {
 664                         amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
 665                         amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
 666                 }
 667                 break;
 668         case CHIP_RAVEN:
 669                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 670                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 671                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 672                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 673                         amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
 674                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 675                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 676                 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
 677                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 678                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 679 #if defined(CONFIG_DRM_AMD_DC)
 680                 else if (amdgpu_device_has_dc_support(adev))
 681                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 682 #else
 683 #       warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
 684 #endif
 685                 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
 686                 break;
 687         default:
 688                 return -EINVAL;
 689         }
 690
 691         return 0;
 692 }
 693
 694 static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
 695 {
 696         adev->nbio_funcs->hdp_flush(adev, ring);
 697 }
 698
 699 static void soc15_invalidate_hdp(struct amdgpu_device *adev,
 700                                  struct amdgpu_ring *ring)
 701 {
 702         if (!ring || !ring->funcs->emit_wreg)
 703                 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
 704         else
 705                 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
 706                         HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
 707 }
 708
 709 static bool soc15_need_full_reset(struct amdgpu_device *adev)
 710 {
 711         /* change this when we implement soft reset */
 712         return true;
 713 }
 714 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
 715                                  uint64_t *count1)
 716 {
 717         uint32_t perfctr = 0;
 718         uint64_t cnt0_of, cnt1_of;
 719         int tmp;
 720
 721         /* This reports 0 on APUs, so return to avoid writing/reading registers
 722          * that may or may not be different from their GPU counterparts
 723          */
 724          if (adev->flags & AMD_IS_APU)
 725                  return;
 726
 727         /* Set the 2 events that we wish to watch, defined above */
 728         /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */
 729         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
 730         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
 731
 732         /* Write to enable desired perf counters */
 733         WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
 734         /* Zero out and enable the perf counters
 735          * Write 0x5:
 736          * Bit 0 = Start all counters(1)
 737          * Bit 2 = Global counter reset enable(1)
 738          */
 739         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
 740
 741         msleep(1000);
 742
 743         /* Load the shadow and disable the perf counters
 744          * Write 0x2:
 745          * Bit 0 = Stop counters(0)
 746          * Bit 1 = Load the shadow counters(1)
 747          */
 748         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
 749
 750         /* Read register values to get any >32bit overflow */
 751         tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
 752         cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
 753         cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
 754
 755         /* Get the values and add the overflow */
 756         *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
 757         *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
 758 }
 759
 760 static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
 761 {
 762         u32 sol_reg;
 763
 764         /* Just return false for soc15 GPUs.  Reset does not seem to
 765          * be necessary.
 766          */
 767         if (!amdgpu_passthrough(adev))
 768                 return false;
 769
 770         if (adev->flags & AMD_IS_APU)
 771                 return false;
 772
 773         /* Check sOS sign of life register to confirm sys driver and sOS
 774          * are already been loaded.
 775          */
 776         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 777         if (sol_reg)
 778                 return true;
 779
 780         return false;
 781 }
 782
 783 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
 784 {
 785         uint64_t nak_r, nak_g;
 786
 787         /* Get the number of NAKs received and generated */
 788         nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
 789         nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
 790
 791         /* Add the total number of NAKs, i.e the number of replays */
 792         return (nak_r + nak_g);
 793 }
 794
 795 static const struct amdgpu_asic_funcs soc15_asic_funcs =
 796 {
 797         .read_disabled_bios = &soc15_read_disabled_bios,
 798         .read_bios_from_rom = &soc15_read_bios_from_rom,
 799         .read_register = &soc15_read_register,
 800         .reset = &soc15_asic_reset,
 801         .set_vga_state = &soc15_vga_set_state,
 802         .get_xclk = &soc15_get_xclk,
 803         .set_uvd_clocks = &soc15_set_uvd_clocks,
 804         .set_vce_clocks = &soc15_set_vce_clocks,
 805         .get_config_memsize = &soc15_get_config_memsize,
 806         .flush_hdp = &soc15_flush_hdp,
 807         .invalidate_hdp = &soc15_invalidate_hdp,
 808         .need_full_reset = &soc15_need_full_reset,
 809         .init_doorbell_index = &vega10_doorbell_index_init,
 810         .get_pcie_usage = &soc15_get_pcie_usage,
 811         .need_reset_on_init = &soc15_need_reset_on_init,
 812         .get_pcie_replay_count = &soc15_get_pcie_replay_count,
 813 };
 814
 815 static const struct amdgpu_asic_funcs vega20_asic_funcs =
 816 {
 817         .read_disabled_bios = &soc15_read_disabled_bios,
 818         .read_bios_from_rom = &soc15_read_bios_from_rom,
 819         .read_register = &soc15_read_register,
 820         .reset = &soc15_asic_reset,
 821         .set_vga_state = &soc15_vga_set_state,
 822         .get_xclk = &soc15_get_xclk,
 823         .set_uvd_clocks = &soc15_set_uvd_clocks,
 824         .set_vce_clocks = &soc15_set_vce_clocks,
 825         .get_config_memsize = &soc15_get_config_memsize,
 826         .flush_hdp = &soc15_flush_hdp,
 827         .invalidate_hdp = &soc15_invalidate_hdp,
 828         .need_full_reset = &soc15_need_full_reset,
 829         .init_doorbell_index = &vega20_doorbell_index_init,
 830         .get_pcie_usage = &soc15_get_pcie_usage,
 831         .need_reset_on_init = &soc15_need_reset_on_init,
 832         .get_pcie_replay_count = &soc15_get_pcie_replay_count,
 833 };
 834
 835 static int soc15_common_early_init(void *handle)
 836 {
 837 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
 838         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 839
 840         adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
 841         adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
 842         adev->smc_rreg = NULL;
 843         adev->smc_wreg = NULL;
 844         adev->pcie_rreg = &soc15_pcie_rreg;
 845         adev->pcie_wreg = &soc15_pcie_wreg;
 846         adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
 847         adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
 848         adev->didt_rreg = &soc15_didt_rreg;
 849         adev->didt_wreg = &soc15_didt_wreg;
 850         adev->gc_cac_rreg = &soc15_gc_cac_rreg;
 851         adev->gc_cac_wreg = &soc15_gc_cac_wreg;
 852         adev->se_cac_rreg = &soc15_se_cac_rreg;
 853         adev->se_cac_wreg = &soc15_se_cac_wreg;
 854
 855
 856         adev->external_rev_id = 0xFF;
 857         switch (adev->asic_type) {
 858         case CHIP_VEGA10:
 859                 adev->asic_funcs = &soc15_asic_funcs;
 860                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 861                         AMD_CG_SUPPORT_GFX_MGLS |
 862                         AMD_CG_SUPPORT_GFX_RLC_LS |
 863                         AMD_CG_SUPPORT_GFX_CP_LS |
 864                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 865                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 866                         AMD_CG_SUPPORT_GFX_CGCG |
 867                         AMD_CG_SUPPORT_GFX_CGLS |
 868                         AMD_CG_SUPPORT_BIF_MGCG |
 869                         AMD_CG_SUPPORT_BIF_LS |
 870                         AMD_CG_SUPPORT_HDP_LS |
 871                         AMD_CG_SUPPORT_DRM_MGCG |
 872                         AMD_CG_SUPPORT_DRM_LS |
 873                         AMD_CG_SUPPORT_ROM_MGCG |
 874                         AMD_CG_SUPPORT_DF_MGCG |
 875                         AMD_CG_SUPPORT_SDMA_MGCG |
 876                         AMD_CG_SUPPORT_SDMA_LS |
 877                         AMD_CG_SUPPORT_MC_MGCG |
 878                         AMD_CG_SUPPORT_MC_LS;
 879                 adev->pg_flags = 0;
 880                 adev->external_rev_id = 0x1;
 881                 break;
 882         case CHIP_VEGA12:
 883                 adev->asic_funcs = &soc15_asic_funcs;
 884                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 885                         AMD_CG_SUPPORT_GFX_MGLS |
 886                         AMD_CG_SUPPORT_GFX_CGCG |
 887                         AMD_CG_SUPPORT_GFX_CGLS |
 888                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 889                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 890                         AMD_CG_SUPPORT_GFX_CP_LS |
 891                         AMD_CG_SUPPORT_MC_LS |
 892                         AMD_CG_SUPPORT_MC_MGCG |
 893                         AMD_CG_SUPPORT_SDMA_MGCG |
 894                         AMD_CG_SUPPORT_SDMA_LS |
 895                         AMD_CG_SUPPORT_BIF_MGCG |
 896                         AMD_CG_SUPPORT_BIF_LS |
 897                         AMD_CG_SUPPORT_HDP_MGCG |
 898                         AMD_CG_SUPPORT_HDP_LS |
 899                         AMD_CG_SUPPORT_ROM_MGCG |
 900                         AMD_CG_SUPPORT_VCE_MGCG |
 901                         AMD_CG_SUPPORT_UVD_MGCG;
 902                 adev->pg_flags = 0;
 903                 adev->external_rev_id = adev->rev_id + 0x14;
 904                 break;
 905         case CHIP_VEGA20:
 906                 adev->asic_funcs = &vega20_asic_funcs;
 907                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 908                         AMD_CG_SUPPORT_GFX_MGLS |
 909                         AMD_CG_SUPPORT_GFX_CGCG |
 910                         AMD_CG_SUPPORT_GFX_CGLS |
 911                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 912                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 913                         AMD_CG_SUPPORT_GFX_CP_LS |
 914                         AMD_CG_SUPPORT_MC_LS |
 915                         AMD_CG_SUPPORT_MC_MGCG |
 916                         AMD_CG_SUPPORT_SDMA_MGCG |
 917                         AMD_CG_SUPPORT_SDMA_LS |
 918                         AMD_CG_SUPPORT_BIF_MGCG |
 919                         AMD_CG_SUPPORT_BIF_LS |
 920                         AMD_CG_SUPPORT_HDP_MGCG |
 921                         AMD_CG_SUPPORT_HDP_LS |
 922                         AMD_CG_SUPPORT_ROM_MGCG |
 923                         AMD_CG_SUPPORT_VCE_MGCG |
 924                         AMD_CG_SUPPORT_UVD_MGCG;
 925                 adev->pg_flags = 0;
 926                 adev->external_rev_id = adev->rev_id + 0x28;
 927                 break;
 928         case CHIP_RAVEN:
 929                 adev->asic_funcs = &soc15_asic_funcs;
 930                 if (adev->rev_id >= 0x8)
 931                         adev->external_rev_id = adev->rev_id + 0x79;
 932                 else if (adev->pdev->device == 0x15d8)
 933                         adev->external_rev_id = adev->rev_id + 0x41;
 934                 else if (adev->rev_id == 1)
 935                         adev->external_rev_id = adev->rev_id + 0x20;
 936                 else
 937                         adev->external_rev_id = adev->rev_id + 0x01;
 938
 939                 if (adev->rev_id >= 0x8) {
 940                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 941                                 AMD_CG_SUPPORT_GFX_MGLS |
 942                                 AMD_CG_SUPPORT_GFX_CP_LS |
 943                                 AMD_CG_SUPPORT_GFX_3D_CGCG |
 944                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
 945                                 AMD_CG_SUPPORT_GFX_CGCG |
 946                                 AMD_CG_SUPPORT_GFX_CGLS |
 947                                 AMD_CG_SUPPORT_BIF_LS |
 948                                 AMD_CG_SUPPORT_HDP_LS |
 949                                 AMD_CG_SUPPORT_ROM_MGCG |
 950                                 AMD_CG_SUPPORT_MC_MGCG |
 951                                 AMD_CG_SUPPORT_MC_LS |
 952                                 AMD_CG_SUPPORT_SDMA_MGCG |
 953                                 AMD_CG_SUPPORT_SDMA_LS |
 954                                 AMD_CG_SUPPORT_VCN_MGCG;
 955
 956                         adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
 957                 } else if (adev->pdev->device == 0x15d8) {
 958                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 959                                 AMD_CG_SUPPORT_GFX_MGLS |
 960                                 AMD_CG_SUPPORT_GFX_CP_LS |
 961                                 AMD_CG_SUPPORT_GFX_3D_CGCG |
 962                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
 963                                 AMD_CG_SUPPORT_GFX_CGCG |
 964                                 AMD_CG_SUPPORT_GFX_CGLS |
 965                                 AMD_CG_SUPPORT_BIF_LS |
 966                                 AMD_CG_SUPPORT_HDP_LS |
 967                                 AMD_CG_SUPPORT_ROM_MGCG |
 968                                 AMD_CG_SUPPORT_MC_MGCG |
 969                                 AMD_CG_SUPPORT_MC_LS |
 970                                 AMD_CG_SUPPORT_SDMA_MGCG |
 971                                 AMD_CG_SUPPORT_SDMA_LS;
 972
 973                         adev->pg_flags = AMD_PG_SUPPORT_SDMA |
 974                                 AMD_PG_SUPPORT_MMHUB |
 975                                 AMD_PG_SUPPORT_VCN |
 976                                 AMD_PG_SUPPORT_VCN_DPG;
 977                 } else {
 978                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 979                                 AMD_CG_SUPPORT_GFX_MGLS |
 980                                 AMD_CG_SUPPORT_GFX_RLC_LS |
 981                                 AMD_CG_SUPPORT_GFX_CP_LS |
 982                                 AMD_CG_SUPPORT_GFX_3D_CGCG |
 983                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
 984                                 AMD_CG_SUPPORT_GFX_CGCG |
 985                                 AMD_CG_SUPPORT_GFX_CGLS |
 986                                 AMD_CG_SUPPORT_BIF_MGCG |
 987                                 AMD_CG_SUPPORT_BIF_LS |
 988                                 AMD_CG_SUPPORT_HDP_MGCG |
 989                                 AMD_CG_SUPPORT_HDP_LS |
 990                                 AMD_CG_SUPPORT_DRM_MGCG |
 991                                 AMD_CG_SUPPORT_DRM_LS |
 992                                 AMD_CG_SUPPORT_ROM_MGCG |
 993                                 AMD_CG_SUPPORT_MC_MGCG |
 994                                 AMD_CG_SUPPORT_MC_LS |
 995                                 AMD_CG_SUPPORT_SDMA_MGCG |
 996                                 AMD_CG_SUPPORT_SDMA_LS |
 997                                 AMD_CG_SUPPORT_VCN_MGCG;
 998
 999                         adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1000                 }
1001
1002                 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
1003                         adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
1004                                 AMD_PG_SUPPORT_CP |
1005                                 AMD_PG_SUPPORT_RLC_SMU_HS;
1006                 break;
1007         default:
1008                 /* FIXME: not supported yet */
1009                 return -EINVAL;
1010         }
1011
1012         if (amdgpu_sriov_vf(adev)) {
1013                 amdgpu_virt_init_setting(adev);
1014                 xgpu_ai_mailbox_set_irq_funcs(adev);
1015         }
1016
1017         return 0;
1018 }
1019
1020 static int soc15_common_late_init(void *handle)
1021 {
1022         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1023
1024         if (amdgpu_sriov_vf(adev))
1025                 xgpu_ai_mailbox_get_irq(adev);
1026
1027         return 0;
1028 }
1029
1030 static int soc15_common_sw_init(void *handle)
1031 {
1032         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1033
1034         if (amdgpu_sriov_vf(adev))
1035                 xgpu_ai_mailbox_add_irq_id(adev);
1036
1037         adev->df_funcs->sw_init(adev);
1038
1039         return 0;
1040 }
1041
1042 static int soc15_common_sw_fini(void *handle)
1043 {
1044         return 0;
1045 }
1046
1047 static void soc15_doorbell_range_init(struct amdgpu_device *adev)
1048 {
1049         int i;
1050         struct amdgpu_ring *ring;
1051
1052         /*  Two reasons to skip
1053         *               1, Host driver already programmed them
1054         *               2, To avoid registers program violations in SR-IOV
1055         */
1056         if (!amdgpu_virt_support_skip_setting(adev)) {
1057                 for (i = 0; i < adev->sdma.num_instances; i++) {
1058                         ring = &adev->sdma.instance[i].ring;
1059                         adev->nbio_funcs->sdma_doorbell_range(adev, i,
1060                                 ring->use_doorbell, ring->doorbell_index,
1061                                 adev->doorbell_index.sdma_doorbell_range);
1062                 }
1063         }
1064
1065         adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
1066                                                 adev->irq.ih.doorbell_index);
1067 }
1068
1069 static int soc15_common_hw_init(void *handle)
1070 {
1071         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1072
1073         /* enable pcie gen2/3 link */
1074         soc15_pcie_gen3_enable(adev);
1075         /* enable aspm */
1076         soc15_program_aspm(adev);
1077         /* setup nbio registers */
1078         adev->nbio_funcs->init_registers(adev);
1079         /* remap HDP registers to a hole in mmio space,
1080          * for the purpose of expose those registers
1081          * to process space
1082          */
1083         if (adev->nbio_funcs->remap_hdp_registers)
1084                 adev->nbio_funcs->remap_hdp_registers(adev);
1085
1086         /* enable the doorbell aperture */
1087         soc15_enable_doorbell_aperture(adev, true);
1088         /* HW doorbell routing policy: doorbell writing not
1089          * in SDMA/IH/MM/ACV range will be routed to CP. So
1090          * we need to init SDMA/IH/MM/ACV doorbell range prior
1091          * to CP ip block init and ring test.
1092          */
1093         soc15_doorbell_range_init(adev);
1094
1095         return 0;
1096 }
1097
1098 static int soc15_common_hw_fini(void *handle)
1099 {
1100         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1101
1102         /* disable the doorbell aperture */
1103         soc15_enable_doorbell_aperture(adev, false);
1104         if (amdgpu_sriov_vf(adev))
1105                 xgpu_ai_mailbox_put_irq(adev);
1106
1107         return 0;
1108 }
1109
1110 static int soc15_common_suspend(void *handle)
1111 {
1112         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1113
1114         return soc15_common_hw_fini(adev);
1115 }
1116
1117 static int soc15_common_resume(void *handle)
1118 {
1119         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1120
1121         return soc15_common_hw_init(adev);
1122 }
1123
1124 static bool soc15_common_is_idle(void *handle)
1125 {
1126         return true;
1127 }
1128
1129 static int soc15_common_wait_for_idle(void *handle)
1130 {
1131         return 0;
1132 }
1133
1134 static int soc15_common_soft_reset(void *handle)
1135 {
1136         return 0;
1137 }
1138
1139 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
1140 {
1141         uint32_t def, data;
1142
1143         if (adev->asic_type == CHIP_VEGA20) {
1144                 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
1145
1146                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1147                         data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1148                                 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1149                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1150                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
1151                 else
1152                         data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1153                                 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1154                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1155                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
1156
1157                 if (def != data)
1158                         WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
1159         } else {
1160                 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1161
1162                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1163                         data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1164                 else
1165                         data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1166
1167                 if (def != data)
1168                         WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
1169         }
1170 }
1171
1172 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1173 {
1174         uint32_t def, data;
1175
1176         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1177
1178         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1179                 data &= ~(0x01000000 |
1180                           0x02000000 |
1181                           0x04000000 |
1182                           0x08000000 |
1183                           0x10000000 |
1184                           0x20000000 |
1185                           0x40000000 |
1186                           0x80000000);
1187         else
1188                 data |= (0x01000000 |
1189                          0x02000000 |
1190                          0x04000000 |
1191                          0x08000000 |
1192                          0x10000000 |
1193                          0x20000000 |
1194                          0x40000000 |
1195                          0x80000000);
1196
1197         if (def != data)
1198                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1199 }
1200
1201 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1202 {
1203         uint32_t def, data;
1204
1205         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1206
1207         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1208                 data |= 1;
1209         else
1210                 data &= ~1;
1211
1212         if (def != data)
1213                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1214 }
1215
1216 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1217                                                        bool enable)
1218 {
1219         uint32_t def, data;
1220
1221         def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1222
1223         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
1224                 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1225                         CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1226         else
1227                 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1228                         CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1229
1230         if (def != data)
1231                 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
1232 }
1233
1234 static int soc15_common_set_clockgating_state(void *handle,
1235                                             enum amd_clockgating_state state)
1236 {
1237         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1238
1239         if (amdgpu_sriov_vf(adev))
1240                 return 0;
1241
1242         switch (adev->asic_type) {
1243         case CHIP_VEGA10:
1244         case CHIP_VEGA12:
1245         case CHIP_VEGA20:
1246                 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
1247                                 state == AMD_CG_STATE_GATE ? true : false);
1248                 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
1249                                 state == AMD_CG_STATE_GATE ? true : false);
1250                 soc15_update_hdp_light_sleep(adev,
1251                                 state == AMD_CG_STATE_GATE ? true : false);
1252                 soc15_update_drm_clock_gating(adev,
1253                                 state == AMD_CG_STATE_GATE ? true : false);
1254                 soc15_update_drm_light_sleep(adev,
1255                                 state == AMD_CG_STATE_GATE ? true : false);
1256                 soc15_update_rom_medium_grain_clock_gating(adev,
1257                                 state == AMD_CG_STATE_GATE ? true : false);
1258                 adev->df_funcs->update_medium_grain_clock_gating(adev,
1259                                 state == AMD_CG_STATE_GATE ? true : false);
1260                 break;
1261         case CHIP_RAVEN:
1262                 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
1263                                 state == AMD_CG_STATE_GATE ? true : false);
1264                 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
1265                                 state == AMD_CG_STATE_GATE ? true : false);
1266                 soc15_update_hdp_light_sleep(adev,
1267                                 state == AMD_CG_STATE_GATE ? true : false);
1268                 soc15_update_drm_clock_gating(adev,
1269                                 state == AMD_CG_STATE_GATE ? true : false);
1270                 soc15_update_drm_light_sleep(adev,
1271                                 state == AMD_CG_STATE_GATE ? true : false);
1272                 soc15_update_rom_medium_grain_clock_gating(adev,
1273                                 state == AMD_CG_STATE_GATE ? true : false);
1274                 break;
1275         default:
1276                 break;
1277         }
1278         return 0;
1279 }
1280
1281 static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
1282 {
1283         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1284         int data;
1285
1286         if (amdgpu_sriov_vf(adev))
1287                 *flags = 0;
1288
1289         adev->nbio_funcs->get_clockgating_state(adev, flags);
1290
1291         /* AMD_CG_SUPPORT_HDP_LS */
1292         data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1293         if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1294                 *flags |= AMD_CG_SUPPORT_HDP_LS;
1295
1296         /* AMD_CG_SUPPORT_DRM_MGCG */
1297         data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1298         if (!(data & 0x01000000))
1299                 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1300
1301         /* AMD_CG_SUPPORT_DRM_LS */
1302         data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1303         if (data & 0x1)
1304                 *flags |= AMD_CG_SUPPORT_DRM_LS;
1305
1306         /* AMD_CG_SUPPORT_ROM_MGCG */
1307         data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1308         if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
1309                 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
1310
1311         adev->df_funcs->get_clockgating_state(adev, flags);
1312 }
1313
1314 static int soc15_common_set_powergating_state(void *handle,
1315                                             enum amd_powergating_state state)
1316 {
1317         /* todo */
1318         return 0;
1319 }
1320
1321 const struct amd_ip_funcs soc15_common_ip_funcs = {
1322         .name = "soc15_common",
1323         .early_init = soc15_common_early_init,
1324         .late_init = soc15_common_late_init,
1325         .sw_init = soc15_common_sw_init,
1326         .sw_fini = soc15_common_sw_fini,
1327         .hw_init = soc15_common_hw_init,
1328         .hw_fini = soc15_common_hw_fini,
1329         .suspend = soc15_common_suspend,
1330         .resume = soc15_common_resume,
1331         .is_idle = soc15_common_is_idle,
1332         .wait_for_idle = soc15_common_wait_for_idle,
1333         .soft_reset = soc15_common_soft_reset,
1334         .set_clockgating_state = soc15_common_set_clockgating_state,
1335         .set_powergating_state = soc15_common_set_powergating_state,
1336         .get_clockgating_state= soc15_common_get_clockgating_state,
1337 };