drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <drm/ttm/ttm_bo_api.h>
  33 #include <drm/ttm/ttm_bo_driver.h>
  34 #include <drm/ttm/ttm_placement.h>
  35 #include <drm/ttm/ttm_module.h>
  36 #include <drm/ttm/ttm_page_alloc.h>
  37 #include <drm/drmP.h>
  38 #include <drm/amdgpu_drm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swiotlb.h>
  42 #include <linux/swap.h>
  43 #include <linux/pagemap.h>
  44 #include <linux/debugfs.h>
  45 #include <linux/iommu.h>
  46 #include <linux/hmm.h>
  47 #include "amdgpu.h"
  48 #include "amdgpu_object.h"
  49 #include "amdgpu_trace.h"
  50 #include "amdgpu_amdkfd.h"
  51 #include "amdgpu_sdma.h"
  52 #include "bif/bif_4_1_d.h"
  53
  54 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
  55                              struct ttm_mem_reg *mem, unsigned num_pages,
  56                              uint64_t offset, unsigned window,
  57                              struct amdgpu_ring *ring,
  58                              uint64_t *addr);
  59
  60 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
  61 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
  62
  63 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
  64 {
  65         return 0;
  66 }
  67
  68 /**
  69  * amdgpu_init_mem_type - Initialize a memory manager for a specific type of
  70  * memory request.
  71  *
  72  * @bdev: The TTM BO device object (contains a reference to amdgpu_device)
  73  * @type: The type of memory requested
  74  * @man: The memory type manager for each domain
  75  *
  76  * This is called by ttm_bo_init_mm() when a buffer object is being
  77  * initialized.
  78  */
  79 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
  80                                 struct ttm_mem_type_manager *man)
  81 {
  82         struct amdgpu_device *adev;
  83
  84         adev = amdgpu_ttm_adev(bdev);
  85
  86         switch (type) {
  87         case TTM_PL_SYSTEM:
  88                 /* System memory */
  89                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
  90                 man->available_caching = TTM_PL_MASK_CACHING;
  91                 man->default_caching = TTM_PL_FLAG_CACHED;
  92                 break;
  93         case TTM_PL_TT:
  94                 /* GTT memory  */
  95                 man->func = &amdgpu_gtt_mgr_func;
  96                 man->gpu_offset = adev->gmc.gart_start;
  97                 man->available_caching = TTM_PL_MASK_CACHING;
  98                 man->default_caching = TTM_PL_FLAG_CACHED;
  99                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 100                 break;
 101         case TTM_PL_VRAM:
 102                 /* "On-card" video ram */
 103                 man->func = &amdgpu_vram_mgr_func;
 104                 man->gpu_offset = adev->gmc.vram_start;
 105                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 106                              TTM_MEMTYPE_FLAG_MAPPABLE;
 107                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 108                 man->default_caching = TTM_PL_FLAG_WC;
 109                 break;
 110         case AMDGPU_PL_GDS:
 111         case AMDGPU_PL_GWS:
 112         case AMDGPU_PL_OA:
 113                 /* On-chip GDS memory*/
 114                 man->func = &ttm_bo_manager_func;
 115                 man->gpu_offset = 0;
 116                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 117                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 118                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 119                 break;
 120         default:
 121                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 122                 return -EINVAL;
 123         }
 124         return 0;
 125 }
 126
 127 /**
 128  * amdgpu_evict_flags - Compute placement flags
 129  *
 130  * @bo: The buffer object to evict
 131  * @placement: Possible destination(s) for evicted BO
 132  *
 133  * Fill in placement data when ttm_bo_evict() is called
 134  */
 135 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 136                                 struct ttm_placement *placement)
 137 {
 138         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 139         struct amdgpu_bo *abo;
 140         static const struct ttm_place placements = {
 141                 .fpfn = 0,
 142                 .lpfn = 0,
 143                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 144         };
 145
 146         /* Don't handle scatter gather BOs */
 147         if (bo->type == ttm_bo_type_sg) {
 148                 placement->num_placement = 0;
 149                 placement->num_busy_placement = 0;
 150                 return;
 151         }
 152
 153         /* Object isn't an AMDGPU object so ignore */
 154         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 155                 placement->placement = &placements;
 156                 placement->busy_placement = &placements;
 157                 placement->num_placement = 1;
 158                 placement->num_busy_placement = 1;
 159                 return;
 160         }
 161
 162         abo = ttm_to_amdgpu_bo(bo);
 163         switch (bo->mem.mem_type) {
 164         case AMDGPU_PL_GDS:
 165         case AMDGPU_PL_GWS:
 166         case AMDGPU_PL_OA:
 167                 placement->num_placement = 0;
 168                 placement->num_busy_placement = 0;
 169                 return;
 170
 171         case TTM_PL_VRAM:
 172                 if (!adev->mman.buffer_funcs_enabled) {
 173                         /* Move to system memory */
 174                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 175                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 176                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 177                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 178
 179                         /* Try evicting to the CPU inaccessible part of VRAM
 180                          * first, but only set GTT as busy placement, so this
 181                          * BO will be evicted to GTT rather than causing other
 182                          * BOs to be evicted from VRAM
 183                          */
 184                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 185                                                          AMDGPU_GEM_DOMAIN_GTT);
 186                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 187                         abo->placements[0].lpfn = 0;
 188                         abo->placement.busy_placement = &abo->placements[1];
 189                         abo->placement.num_busy_placement = 1;
 190                 } else {
 191                         /* Move to GTT memory */
 192                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 193                 }
 194                 break;
 195         case TTM_PL_TT:
 196         default:
 197                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 198                 break;
 199         }
 200         *placement = abo->placement;
 201 }
 202
 203 /**
 204  * amdgpu_verify_access - Verify access for a mmap call
 205  *
 206  * @bo: The buffer object to map
 207  * @filp: The file pointer from the process performing the mmap
 208  *
 209  * This is called by ttm_bo_mmap() to verify whether a process
 210  * has the right to mmap a BO to their process space.
 211  */
 212 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 213 {
 214         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 215
 216         /*
 217          * Don't verify access for KFD BOs. They don't have a GEM
 218          * object associated with them.
 219          */
 220         if (abo->kfd_bo)
 221                 return 0;
 222
 223         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 224                 return -EPERM;
 225         return drm_vma_node_verify_access(&abo->gem_base.vma_node,
 226                                           filp->private_data);
 227 }
 228
 229 /**
 230  * amdgpu_move_null - Register memory for a buffer object
 231  *
 232  * @bo: The bo to assign the memory to
 233  * @new_mem: The memory to be assigned.
 234  *
 235  * Assign the memory from new_mem to the memory of the buffer object bo.
 236  */
 237 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 238                              struct ttm_mem_reg *new_mem)
 239 {
 240         struct ttm_mem_reg *old_mem = &bo->mem;
 241
 242         BUG_ON(old_mem->mm_node != NULL);
 243         *old_mem = *new_mem;
 244         new_mem->mm_node = NULL;
 245 }
 246
 247 /**
 248  * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
 249  *
 250  * @bo: The bo to assign the memory to.
 251  * @mm_node: Memory manager node for drm allocator.
 252  * @mem: The region where the bo resides.
 253  *
 254  */
 255 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 256                                     struct drm_mm_node *mm_node,
 257                                     struct ttm_mem_reg *mem)
 258 {
 259         uint64_t addr = 0;
 260
 261         if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
 262                 addr = mm_node->start << PAGE_SHIFT;
 263                 addr += bo->bdev->man[mem->mem_type].gpu_offset;
 264         }
 265         return addr;
 266 }
 267
 268 /**
 269  * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
 270  * @offset. It also modifies the offset to be within the drm_mm_node returned
 271  *
 272  * @mem: The region where the bo resides.
 273  * @offset: The offset that drm_mm_node is used for finding.
 274  *
 275  */
 276 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_mem_reg *mem,
 277                                                unsigned long *offset)
 278 {
 279         struct drm_mm_node *mm_node = mem->mm_node;
 280
 281         while (*offset >= (mm_node->size << PAGE_SHIFT)) {
 282                 *offset -= (mm_node->size << PAGE_SHIFT);
 283                 ++mm_node;
 284         }
 285         return mm_node;
 286 }
 287
 288 /**
 289  * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
 290  *
 291  * The function copies @size bytes from {src->mem + src->offset} to
 292  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 293  * move and different for a BO to BO copy.
 294  *
 295  * @f: Returns the last fence if multiple jobs are submitted.
 296  */
 297 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 298                                struct amdgpu_copy_mem *src,
 299                                struct amdgpu_copy_mem *dst,
 300                                uint64_t size,
 301                                struct reservation_object *resv,
 302                                struct dma_fence **f)
 303 {
 304         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 305         struct drm_mm_node *src_mm, *dst_mm;
 306         uint64_t src_node_start, dst_node_start, src_node_size,
 307                  dst_node_size, src_page_offset, dst_page_offset;
 308         struct dma_fence *fence = NULL;
 309         int r = 0;
 310         const uint64_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 311                                         AMDGPU_GPU_PAGE_SIZE);
 312
 313         if (!adev->mman.buffer_funcs_enabled) {
 314                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 315                 return -EINVAL;
 316         }
 317
 318         src_mm = amdgpu_find_mm_node(src->mem, &src->offset);
 319         src_node_start = amdgpu_mm_node_addr(src->bo, src_mm, src->mem) +
 320                                              src->offset;
 321         src_node_size = (src_mm->size << PAGE_SHIFT) - src->offset;
 322         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 323
 324         dst_mm = amdgpu_find_mm_node(dst->mem, &dst->offset);
 325         dst_node_start = amdgpu_mm_node_addr(dst->bo, dst_mm, dst->mem) +
 326                                              dst->offset;
 327         dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst->offset;
 328         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 329
 330         mutex_lock(&adev->mman.gtt_window_lock);
 331
 332         while (size) {
 333                 unsigned long cur_size;
 334                 uint64_t from = src_node_start, to = dst_node_start;
 335                 struct dma_fence *next;
 336
 337                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 338                  * begins at an offset, then adjust the size accordingly
 339                  */
 340                 cur_size = min3(min(src_node_size, dst_node_size), size,
 341                                 GTT_MAX_BYTES);
 342                 if (cur_size + src_page_offset > GTT_MAX_BYTES ||
 343                     cur_size + dst_page_offset > GTT_MAX_BYTES)
 344                         cur_size -= max(src_page_offset, dst_page_offset);
 345
 346                 /* Map only what needs to be accessed. Map src to window 0 and
 347                  * dst to window 1
 348                  */
 349                 if (src->mem->start == AMDGPU_BO_INVALID_OFFSET) {
 350                         r = amdgpu_map_buffer(src->bo, src->mem,
 351                                         PFN_UP(cur_size + src_page_offset),
 352                                         src_node_start, 0, ring,
 353                                         &from);
 354                         if (r)
 355                                 goto error;
 356                         /* Adjust the offset because amdgpu_map_buffer returns
 357                          * start of mapped page
 358                          */
 359                         from += src_page_offset;
 360                 }
 361
 362                 if (dst->mem->start == AMDGPU_BO_INVALID_OFFSET) {
 363                         r = amdgpu_map_buffer(dst->bo, dst->mem,
 364                                         PFN_UP(cur_size + dst_page_offset),
 365                                         dst_node_start, 1, ring,
 366                                         &to);
 367                         if (r)
 368                                 goto error;
 369                         to += dst_page_offset;
 370                 }
 371
 372                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 373                                        resv, &next, false, true);
 374                 if (r)
 375                         goto error;
 376
 377                 dma_fence_put(fence);
 378                 fence = next;
 379
 380                 size -= cur_size;
 381                 if (!size)
 382                         break;
 383
 384                 src_node_size -= cur_size;
 385                 if (!src_node_size) {
 386                         src_node_start = amdgpu_mm_node_addr(src->bo, ++src_mm,
 387                                                              src->mem);
 388                         src_node_size = (src_mm->size << PAGE_SHIFT);
 389                 } else {
 390                         src_node_start += cur_size;
 391                         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 392                 }
 393                 dst_node_size -= cur_size;
 394                 if (!dst_node_size) {
 395                         dst_node_start = amdgpu_mm_node_addr(dst->bo, ++dst_mm,
 396                                                              dst->mem);
 397                         dst_node_size = (dst_mm->size << PAGE_SHIFT);
 398                 } else {
 399                         dst_node_start += cur_size;
 400                         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 401                 }
 402         }
 403 error:
 404         mutex_unlock(&adev->mman.gtt_window_lock);
 405         if (f)
 406                 *f = dma_fence_get(fence);
 407         dma_fence_put(fence);
 408         return r;
 409 }
 410
 411 /**
 412  * amdgpu_move_blit - Copy an entire buffer to another buffer
 413  *
 414  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 415  * help move buffers to and from VRAM.
 416  */
 417 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 418                             bool evict, bool no_wait_gpu,
 419                             struct ttm_mem_reg *new_mem,
 420                             struct ttm_mem_reg *old_mem)
 421 {
 422         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 423         struct amdgpu_copy_mem src, dst;
 424         struct dma_fence *fence = NULL;
 425         int r;
 426
 427         src.bo = bo;
 428         dst.bo = bo;
 429         src.mem = old_mem;
 430         dst.mem = new_mem;
 431         src.offset = 0;
 432         dst.offset = 0;
 433
 434         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 435                                        new_mem->num_pages << PAGE_SHIFT,
 436                                        bo->resv, &fence);
 437         if (r)
 438                 goto error;
 439
 440         /* Always block for VM page tables before committing the new location */
 441         if (bo->type == ttm_bo_type_kernel)
 442                 r = ttm_bo_move_accel_cleanup(bo, fence, true, new_mem);
 443         else
 444                 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 445         dma_fence_put(fence);
 446         return r;
 447
 448 error:
 449         if (fence)
 450                 dma_fence_wait(fence, false);
 451         dma_fence_put(fence);
 452         return r;
 453 }
 454
 455 /**
 456  * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer
 457  *
 458  * Called by amdgpu_bo_move().
 459  */
 460 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
 461                                 struct ttm_operation_ctx *ctx,
 462                                 struct ttm_mem_reg *new_mem)
 463 {
 464         struct amdgpu_device *adev;
 465         struct ttm_mem_reg *old_mem = &bo->mem;
 466         struct ttm_mem_reg tmp_mem;
 467         struct ttm_place placements;
 468         struct ttm_placement placement;
 469         int r;
 470
 471         adev = amdgpu_ttm_adev(bo->bdev);
 472
 473         /* create space/pages for new_mem in GTT space */
 474         tmp_mem = *new_mem;
 475         tmp_mem.mm_node = NULL;
 476         placement.num_placement = 1;
 477         placement.placement = &placements;
 478         placement.num_busy_placement = 1;
 479         placement.busy_placement = &placements;
 480         placements.fpfn = 0;
 481         placements.lpfn = 0;
 482         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 483         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 484         if (unlikely(r)) {
 485                 return r;
 486         }
 487
 488         /* set caching flags */
 489         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 490         if (unlikely(r)) {
 491                 goto out_cleanup;
 492         }
 493
 494         /* Bind the memory to the GTT space */
 495         r = ttm_tt_bind(bo->ttm, &tmp_mem, ctx);
 496         if (unlikely(r)) {
 497                 goto out_cleanup;
 498         }
 499
 500         /* blit VRAM to GTT */
 501         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, &tmp_mem, old_mem);
 502         if (unlikely(r)) {
 503                 goto out_cleanup;
 504         }
 505
 506         /* move BO (in tmp_mem) to new_mem */
 507         r = ttm_bo_move_ttm(bo, ctx, new_mem);
 508 out_cleanup:
 509         ttm_bo_mem_put(bo, &tmp_mem);
 510         return r;
 511 }
 512
 513 /**
 514  * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM
 515  *
 516  * Called by amdgpu_bo_move().
 517  */
 518 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
 519                                 struct ttm_operation_ctx *ctx,
 520                                 struct ttm_mem_reg *new_mem)
 521 {
 522         struct amdgpu_device *adev;
 523         struct ttm_mem_reg *old_mem = &bo->mem;
 524         struct ttm_mem_reg tmp_mem;
 525         struct ttm_placement placement;
 526         struct ttm_place placements;
 527         int r;
 528
 529         adev = amdgpu_ttm_adev(bo->bdev);
 530
 531         /* make space in GTT for old_mem buffer */
 532         tmp_mem = *new_mem;
 533         tmp_mem.mm_node = NULL;
 534         placement.num_placement = 1;
 535         placement.placement = &placements;
 536         placement.num_busy_placement = 1;
 537         placement.busy_placement = &placements;
 538         placements.fpfn = 0;
 539         placements.lpfn = 0;
 540         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 541         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 542         if (unlikely(r)) {
 543                 return r;
 544         }
 545
 546         /* move/bind old memory to GTT space */
 547         r = ttm_bo_move_ttm(bo, ctx, &tmp_mem);
 548         if (unlikely(r)) {
 549                 goto out_cleanup;
 550         }
 551
 552         /* copy to VRAM */
 553         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, new_mem, old_mem);
 554         if (unlikely(r)) {
 555                 goto out_cleanup;
 556         }
 557 out_cleanup:
 558         ttm_bo_mem_put(bo, &tmp_mem);
 559         return r;
 560 }
 561
 562 /**
 563  * amdgpu_bo_move - Move a buffer object to a new memory location
 564  *
 565  * Called by ttm_bo_handle_move_mem()
 566  */
 567 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 568                           struct ttm_operation_ctx *ctx,
 569                           struct ttm_mem_reg *new_mem)
 570 {
 571         struct amdgpu_device *adev;
 572         struct amdgpu_bo *abo;
 573         struct ttm_mem_reg *old_mem = &bo->mem;
 574         int r;
 575
 576         /* Can't move a pinned BO */
 577         abo = ttm_to_amdgpu_bo(bo);
 578         if (WARN_ON_ONCE(abo->pin_count > 0))
 579                 return -EINVAL;
 580
 581         adev = amdgpu_ttm_adev(bo->bdev);
 582
 583         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 584                 amdgpu_move_null(bo, new_mem);
 585                 return 0;
 586         }
 587         if ((old_mem->mem_type == TTM_PL_TT &&
 588              new_mem->mem_type == TTM_PL_SYSTEM) ||
 589             (old_mem->mem_type == TTM_PL_SYSTEM &&
 590              new_mem->mem_type == TTM_PL_TT)) {
 591                 /* bind is enough */
 592                 amdgpu_move_null(bo, new_mem);
 593                 return 0;
 594         }
 595         if (old_mem->mem_type == AMDGPU_PL_GDS ||
 596             old_mem->mem_type == AMDGPU_PL_GWS ||
 597             old_mem->mem_type == AMDGPU_PL_OA ||
 598             new_mem->mem_type == AMDGPU_PL_GDS ||
 599             new_mem->mem_type == AMDGPU_PL_GWS ||
 600             new_mem->mem_type == AMDGPU_PL_OA) {
 601                 /* Nothing to save here */
 602                 amdgpu_move_null(bo, new_mem);
 603                 return 0;
 604         }
 605
 606         if (!adev->mman.buffer_funcs_enabled)
 607                 goto memcpy;
 608
 609         if (old_mem->mem_type == TTM_PL_VRAM &&
 610             new_mem->mem_type == TTM_PL_SYSTEM) {
 611                 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
 612         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 613                    new_mem->mem_type == TTM_PL_VRAM) {
 614                 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
 615         } else {
 616                 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu,
 617                                      new_mem, old_mem);
 618         }
 619
 620         if (r) {
 621 memcpy:
 622                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 623                 if (r) {
 624                         return r;
 625                 }
 626         }
 627
 628         if (bo->type == ttm_bo_type_device &&
 629             new_mem->mem_type == TTM_PL_VRAM &&
 630             old_mem->mem_type != TTM_PL_VRAM) {
 631                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 632                  * accesses the BO after it's moved.
 633                  */
 634                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 635         }
 636
 637         /* update statistics */
 638         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 639         return 0;
 640 }
 641
 642 /**
 643  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 644  *
 645  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 646  */
 647 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 648 {
 649         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 650         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 651         struct drm_mm_node *mm_node = mem->mm_node;
 652
 653         mem->bus.addr = NULL;
 654         mem->bus.offset = 0;
 655         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 656         mem->bus.base = 0;
 657         mem->bus.is_iomem = false;
 658         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 659                 return -EINVAL;
 660         switch (mem->mem_type) {
 661         case TTM_PL_SYSTEM:
 662                 /* system memory */
 663                 return 0;
 664         case TTM_PL_TT:
 665                 break;
 666         case TTM_PL_VRAM:
 667                 mem->bus.offset = mem->start << PAGE_SHIFT;
 668                 /* check if it's visible */
 669                 if ((mem->bus.offset + mem->bus.size) > adev->gmc.visible_vram_size)
 670                         return -EINVAL;
 671                 /* Only physically contiguous buffers apply. In a contiguous
 672                  * buffer, size of the first mm_node would match the number of
 673                  * pages in ttm_mem_reg.
 674                  */
 675                 if (adev->mman.aper_base_kaddr &&
 676                     (mm_node->size == mem->num_pages))
 677                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 678                                         mem->bus.offset;
 679
 680                 mem->bus.base = adev->gmc.aper_base;
 681                 mem->bus.is_iomem = true;
 682                 break;
 683         default:
 684                 return -EINVAL;
 685         }
 686         return 0;
 687 }
 688
 689 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 690 {
 691 }
 692
 693 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 694                                            unsigned long page_offset)
 695 {
 696         struct drm_mm_node *mm;
 697         unsigned long offset = (page_offset << PAGE_SHIFT);
 698
 699         mm = amdgpu_find_mm_node(&bo->mem, &offset);
 700         return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start +
 701                 (offset >> PAGE_SHIFT);
 702 }
 703
 704 /*
 705  * TTM backend functions.
 706  */
 707 struct amdgpu_ttm_tt {
 708         struct ttm_dma_tt       ttm;
 709         u64                     offset;
 710         uint64_t                userptr;
 711         struct task_struct      *usertask;
 712         uint32_t                userflags;
 713 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 714         struct hmm_range        *range;
 715 #endif
 716 };
 717
 718 /**
 719  * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 720  * memory and start HMM tracking CPU page table update
 721  *
 722  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 723  * once afterwards to stop HMM tracking
 724  */
 725 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 726
 727 #define MAX_RETRY_HMM_RANGE_FAULT       16
 728
 729 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
 730 {
 731         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 732         struct mm_struct *mm = gtt->usertask->mm;
 733         unsigned long start = gtt->userptr;
 734         struct vm_area_struct *vma;
 735         struct hmm_range *range;
 736         unsigned long i;
 737         uint64_t *pfns;
 738         int retry = 0;
 739         int r = 0;
 740
 741         if (!mm) /* Happens during process shutdown */
 742                 return -ESRCH;
 743
 744         vma = find_vma(mm, start);
 745         if (unlikely(!vma || start < vma->vm_start)) {
 746                 r = -EFAULT;
 747                 goto out;
 748         }
 749         if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
 750                 vma->vm_file)) {
 751                 r = -EPERM;
 752                 goto out;
 753         }
 754
 755         range = kzalloc(sizeof(*range), GFP_KERNEL);
 756         if (unlikely(!range)) {
 757                 r = -ENOMEM;
 758                 goto out;
 759         }
 760
 761         pfns = kvmalloc_array(ttm->num_pages, sizeof(*pfns), GFP_KERNEL);
 762         if (unlikely(!pfns)) {
 763                 r = -ENOMEM;
 764                 goto out_free_ranges;
 765         }
 766
 767         amdgpu_hmm_init_range(range);
 768         range->default_flags = range->flags[HMM_PFN_VALID];
 769         range->default_flags |= amdgpu_ttm_tt_is_readonly(ttm) ?
 770                                 0 : range->flags[HMM_PFN_WRITE];
 771         range->pfn_flags_mask = 0;
 772         range->pfns = pfns;
 773         hmm_range_register(range, mm, start,
 774                            start + ttm->num_pages * PAGE_SIZE, PAGE_SHIFT);
 775
 776 retry:
 777         /*
 778          * Just wait for range to be valid, safe to ignore return value as we
 779          * will use the return value of hmm_range_fault() below under the
 780          * mmap_sem to ascertain the validity of the range.
 781          */
 782         hmm_range_wait_until_valid(range, HMM_RANGE_DEFAULT_TIMEOUT);
 783
 784         down_read(&mm->mmap_sem);
 785
 786         r = hmm_range_fault(range, true);
 787         if (unlikely(r < 0)) {
 788                 if (likely(r == -EAGAIN)) {
 789                         /*
 790                          * return -EAGAIN, mmap_sem is dropped
 791                          */
 792                         if (retry++ < MAX_RETRY_HMM_RANGE_FAULT)
 793                                 goto retry;
 794                         else
 795                                 pr_err("Retry hmm fault too many times\n");
 796                 }
 797
 798                 goto out_up_read;
 799         }
 800
 801         up_read(&mm->mmap_sem);
 802
 803         for (i = 0; i < ttm->num_pages; i++) {
 804                 pages[i] = hmm_device_entry_to_page(range, pfns[i]);
 805                 if (unlikely(!pages[i])) {
 806                         pr_err("Page fault failed for pfn[%lu] = 0x%llx\n",
 807                                i, pfns[i]);
 808                         r = -ENOMEM;
 809
 810                         goto out_free_pfns;
 811                 }
 812         }
 813
 814         gtt->range = range;
 815
 816         return 0;
 817
 818 out_up_read:
 819         if (likely(r != -EAGAIN))
 820                 up_read(&mm->mmap_sem);
 821 out_free_pfns:
 822         hmm_range_unregister(range);
 823         kvfree(pfns);
 824 out_free_ranges:
 825         kfree(range);
 826 out:
 827         return r;
 828 }
 829
 830 /**
 831  * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
 832  * Check if the pages backing this ttm range have been invalidated
 833  *
 834  * Returns: true if pages are still valid
 835  */
 836 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
 837 {
 838         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 839         bool r = false;
 840
 841         if (!gtt || !gtt->userptr)
 842                 return false;
 843
 844         DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%lx\n",
 845                 gtt->userptr, ttm->num_pages);
 846
 847         WARN_ONCE(!gtt->range || !gtt->range->pfns,
 848                 "No user pages to check\n");
 849
 850         if (gtt->range) {
 851                 r = hmm_range_valid(gtt->range);
 852                 hmm_range_unregister(gtt->range);
 853
 854                 kvfree(gtt->range->pfns);
 855                 kfree(gtt->range);
 856                 gtt->range = NULL;
 857         }
 858
 859         return r;
 860 }
 861 #endif
 862
 863 /**
 864  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
 865  *
 866  * Called by amdgpu_cs_list_validate(). This creates the page list
 867  * that backs user memory and will ultimately be mapped into the device
 868  * address space.
 869  */
 870 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 871 {
 872         unsigned long i;
 873
 874         for (i = 0; i < ttm->num_pages; ++i)
 875                 ttm->pages[i] = pages ? pages[i] : NULL;
 876 }
 877
 878 /**
 879  * amdgpu_ttm_tt_pin_userptr -  prepare the sg table with the user pages
 880  *
 881  * Called by amdgpu_ttm_backend_bind()
 882  **/
 883 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 884 {
 885         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 886         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 887         unsigned nents;
 888         int r;
 889
 890         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 891         enum dma_data_direction direction = write ?
 892                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 893
 894         /* Allocate an SG array and squash pages into it */
 895         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 896                                       ttm->num_pages << PAGE_SHIFT,
 897                                       GFP_KERNEL);
 898         if (r)
 899                 goto release_sg;
 900
 901         /* Map SG to device */
 902         r = -ENOMEM;
 903         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 904         if (nents != ttm->sg->nents)
 905                 goto release_sg;
 906
 907         /* convert SG to linear array of pages and dma addresses */
 908         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 909                                          gtt->ttm.dma_address, ttm->num_pages);
 910
 911         return 0;
 912
 913 release_sg:
 914         kfree(ttm->sg);
 915         return r;
 916 }
 917
 918 /**
 919  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
 920  */
 921 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 922 {
 923         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 924         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 925
 926         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 927         enum dma_data_direction direction = write ?
 928                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 929
 930         /* double check that we don't free the table twice */
 931         if (!ttm->sg->sgl)
 932                 return;
 933
 934         /* unmap the pages mapped to the device */
 935         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 936
 937         sg_free_table(ttm->sg);
 938
 939 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 940         if (gtt->range &&
 941             ttm->pages[0] == hmm_device_entry_to_page(gtt->range,
 942                                                       gtt->range->pfns[0]))
 943                 WARN_ONCE(1, "Missing get_user_page_done\n");
 944 #endif
 945 }
 946
 947 int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
 948                                 struct ttm_buffer_object *tbo,
 949                                 uint64_t flags)
 950 {
 951         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
 952         struct ttm_tt *ttm = tbo->ttm;
 953         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 954         int r;
 955
 956         if (abo->flags & AMDGPU_GEM_CREATE_MQD_GFX9) {
 957                 uint64_t page_idx = 1;
 958
 959                 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
 960                                 ttm->pages, gtt->ttm.dma_address, flags);
 961                 if (r)
 962                         goto gart_bind_fail;
 963
 964                 /* Patch mtype of the second part BO */
 965                 flags &=  ~AMDGPU_PTE_MTYPE_MASK;
 966                 flags |= AMDGPU_PTE_MTYPE(AMDGPU_MTYPE_NC);
 967
 968                 r = amdgpu_gart_bind(adev,
 969                                 gtt->offset + (page_idx << PAGE_SHIFT),
 970                                 ttm->num_pages - page_idx,
 971                                 &ttm->pages[page_idx],
 972                                 &(gtt->ttm.dma_address[page_idx]), flags);
 973         } else {
 974                 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 975                                      ttm->pages, gtt->ttm.dma_address, flags);
 976         }
 977
 978 gart_bind_fail:
 979         if (r)
 980                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
 981                           ttm->num_pages, gtt->offset);
 982
 983         return r;
 984 }
 985
 986 /**
 987  * amdgpu_ttm_backend_bind - Bind GTT memory
 988  *
 989  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
 990  * This handles binding GTT memory to the device address space.
 991  */
 992 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
 993                                    struct ttm_mem_reg *bo_mem)
 994 {
 995         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 996         struct amdgpu_ttm_tt *gtt = (void*)ttm;
 997         uint64_t flags;
 998         int r = 0;
 999
1000         if (gtt->userptr) {
1001                 r = amdgpu_ttm_tt_pin_userptr(ttm);
1002                 if (r) {
1003                         DRM_ERROR("failed to pin userptr\n");
1004                         return r;
1005                 }
1006         }
1007         if (!ttm->num_pages) {
1008                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
1009                      ttm->num_pages, bo_mem, ttm);
1010         }
1011
1012         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
1013             bo_mem->mem_type == AMDGPU_PL_GWS ||
1014             bo_mem->mem_type == AMDGPU_PL_OA)
1015                 return -EINVAL;
1016
1017         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
1018                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
1019                 return 0;
1020         }
1021
1022         /* compute PTE flags relevant to this BO memory */
1023         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
1024
1025         /* bind pages into GART page tables */
1026         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
1027         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1028                 ttm->pages, gtt->ttm.dma_address, flags);
1029
1030         if (r)
1031                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1032                           ttm->num_pages, gtt->offset);
1033         return r;
1034 }
1035
1036 /**
1037  * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object
1038  */
1039 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
1040 {
1041         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1042         struct ttm_operation_ctx ctx = { false, false };
1043         struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
1044         struct ttm_mem_reg tmp;
1045         struct ttm_placement placement;
1046         struct ttm_place placements;
1047         uint64_t addr, flags;
1048         int r;
1049
1050         if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1051                 return 0;
1052
1053         addr = amdgpu_gmc_agp_addr(bo);
1054         if (addr != AMDGPU_BO_INVALID_OFFSET) {
1055                 bo->mem.start = addr >> PAGE_SHIFT;
1056         } else {
1057
1058                 /* allocate GART space */
1059                 tmp = bo->mem;
1060                 tmp.mm_node = NULL;
1061                 placement.num_placement = 1;
1062                 placement.placement = &placements;
1063                 placement.num_busy_placement = 1;
1064                 placement.busy_placement = &placements;
1065                 placements.fpfn = 0;
1066                 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
1067                 placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
1068                         TTM_PL_FLAG_TT;
1069
1070                 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
1071                 if (unlikely(r))
1072                         return r;
1073
1074                 /* compute PTE flags for this buffer object */
1075                 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
1076
1077                 /* Bind pages */
1078                 gtt->offset = (u64)tmp.start << PAGE_SHIFT;
1079                 r = amdgpu_ttm_gart_bind(adev, bo, flags);
1080                 if (unlikely(r)) {
1081                         ttm_bo_mem_put(bo, &tmp);
1082                         return r;
1083                 }
1084
1085                 ttm_bo_mem_put(bo, &bo->mem);
1086                 bo->mem = tmp;
1087         }
1088
1089         bo->offset = (bo->mem.start << PAGE_SHIFT) +
1090                 bo->bdev->man[bo->mem.mem_type].gpu_offset;
1091
1092         return 0;
1093 }
1094
1095 /**
1096  * amdgpu_ttm_recover_gart - Rebind GTT pages
1097  *
1098  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1099  * rebind GTT pages during a GPU reset.
1100  */
1101 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1102 {
1103         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1104         uint64_t flags;
1105         int r;
1106
1107         if (!tbo->ttm)
1108                 return 0;
1109
1110         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1111         r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1112
1113         return r;
1114 }
1115
1116 /**
1117  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1118  *
1119  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1120  * ttm_tt_destroy().
1121  */
1122 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
1123 {
1124         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1125         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1126         int r;
1127
1128         /* if the pages have userptr pinning then clear that first */
1129         if (gtt->userptr)
1130                 amdgpu_ttm_tt_unpin_userptr(ttm);
1131
1132         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1133                 return 0;
1134
1135         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1136         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1137         if (r)
1138                 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
1139                           gtt->ttm.ttm.num_pages, gtt->offset);
1140         return r;
1141 }
1142
1143 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
1144 {
1145         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1146
1147         if (gtt->usertask)
1148                 put_task_struct(gtt->usertask);
1149
1150         ttm_dma_tt_fini(&gtt->ttm);
1151         kfree(gtt);
1152 }
1153
1154 static struct ttm_backend_func amdgpu_backend_func = {
1155         .bind = &amdgpu_ttm_backend_bind,
1156         .unbind = &amdgpu_ttm_backend_unbind,
1157         .destroy = &amdgpu_ttm_backend_destroy,
1158 };
1159
1160 /**
1161  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1162  *
1163  * @bo: The buffer object to create a GTT ttm_tt object around
1164  *
1165  * Called by ttm_tt_create().
1166  */
1167 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1168                                            uint32_t page_flags)
1169 {
1170         struct amdgpu_device *adev;
1171         struct amdgpu_ttm_tt *gtt;
1172
1173         adev = amdgpu_ttm_adev(bo->bdev);
1174
1175         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1176         if (gtt == NULL) {
1177                 return NULL;
1178         }
1179         gtt->ttm.ttm.func = &amdgpu_backend_func;
1180
1181         /* allocate space for the uninitialized page entries */
1182         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags)) {
1183                 kfree(gtt);
1184                 return NULL;
1185         }
1186         return &gtt->ttm.ttm;
1187 }
1188
1189 /**
1190  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1191  *
1192  * Map the pages of a ttm_tt object to an address space visible
1193  * to the underlying device.
1194  */
1195 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm,
1196                         struct ttm_operation_ctx *ctx)
1197 {
1198         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1199         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1200         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1201
1202         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1203         if (gtt && gtt->userptr) {
1204                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1205                 if (!ttm->sg)
1206                         return -ENOMEM;
1207
1208                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1209                 ttm->state = tt_unbound;
1210                 return 0;
1211         }
1212
1213         if (slave && ttm->sg) {
1214                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1215                                                  gtt->ttm.dma_address,
1216                                                  ttm->num_pages);
1217                 ttm->state = tt_unbound;
1218                 return 0;
1219         }
1220
1221 #ifdef CONFIG_SWIOTLB
1222         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1223                 return ttm_dma_populate(&gtt->ttm, adev->dev, ctx);
1224         }
1225 #endif
1226
1227         /* fall back to generic helper to populate the page array
1228          * and map them to the device */
1229         return ttm_populate_and_map_pages(adev->dev, &gtt->ttm, ctx);
1230 }
1231
1232 /**
1233  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1234  *
1235  * Unmaps pages of a ttm_tt object from the device address space and
1236  * unpopulates the page array backing it.
1237  */
1238 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
1239 {
1240         struct amdgpu_device *adev;
1241         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1242         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1243
1244         if (gtt && gtt->userptr) {
1245                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1246                 kfree(ttm->sg);
1247                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1248                 return;
1249         }
1250
1251         if (slave)
1252                 return;
1253
1254         adev = amdgpu_ttm_adev(ttm->bdev);
1255
1256 #ifdef CONFIG_SWIOTLB
1257         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1258                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
1259                 return;
1260         }
1261 #endif
1262
1263         /* fall back to generic helper to unmap and unpopulate array */
1264         ttm_unmap_and_unpopulate_pages(adev->dev, &gtt->ttm);
1265 }
1266
1267 /**
1268  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1269  * task
1270  *
1271  * @ttm: The ttm_tt object to bind this userptr object to
1272  * @addr:  The address in the current tasks VM space to use
1273  * @flags: Requirements of userptr object.
1274  *
1275  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1276  * to current task
1277  */
1278 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1279                               uint32_t flags)
1280 {
1281         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1282
1283         if (gtt == NULL)
1284                 return -EINVAL;
1285
1286         gtt->userptr = addr;
1287         gtt->userflags = flags;
1288
1289         if (gtt->usertask)
1290                 put_task_struct(gtt->usertask);
1291         gtt->usertask = current->group_leader;
1292         get_task_struct(gtt->usertask);
1293
1294         return 0;
1295 }
1296
1297 /**
1298  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1299  */
1300 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1301 {
1302         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1303
1304         if (gtt == NULL)
1305                 return NULL;
1306
1307         if (gtt->usertask == NULL)
1308                 return NULL;
1309
1310         return gtt->usertask->mm;
1311 }
1312
1313 /**
1314  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1315  * address range for the current task.
1316  *
1317  */
1318 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1319                                   unsigned long end)
1320 {
1321         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1322         unsigned long size;
1323
1324         if (gtt == NULL || !gtt->userptr)
1325                 return false;
1326
1327         /* Return false if no part of the ttm_tt object lies within
1328          * the range
1329          */
1330         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1331         if (gtt->userptr > end || gtt->userptr + size <= start)
1332                 return false;
1333
1334         return true;
1335 }
1336
1337 /**
1338  * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1339  */
1340 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1341 {
1342         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1343
1344         if (gtt == NULL || !gtt->userptr)
1345                 return false;
1346
1347         return true;
1348 }
1349
1350 /**
1351  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1352  */
1353 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1354 {
1355         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1356
1357         if (gtt == NULL)
1358                 return false;
1359
1360         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1361 }
1362
1363 /**
1364  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1365  *
1366  * @ttm: The ttm_tt object to compute the flags for
1367  * @mem: The memory registry backing this ttm_tt object
1368  *
1369  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1370  */
1371 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
1372 {
1373         uint64_t flags = 0;
1374
1375         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1376                 flags |= AMDGPU_PTE_VALID;
1377
1378         if (mem && mem->mem_type == TTM_PL_TT) {
1379                 flags |= AMDGPU_PTE_SYSTEM;
1380
1381                 if (ttm->caching_state == tt_cached)
1382                         flags |= AMDGPU_PTE_SNOOPED;
1383         }
1384
1385         return flags;
1386 }
1387
1388 /**
1389  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1390  *
1391  * @ttm: The ttm_tt object to compute the flags for
1392  * @mem: The memory registry backing this ttm_tt object
1393
1394  * Figure out the flags to use for a VM PTE (Page Table Entry).
1395  */
1396 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1397                                  struct ttm_mem_reg *mem)
1398 {
1399         uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1400
1401         flags |= adev->gart.gart_pte_flags;
1402         flags |= AMDGPU_PTE_READABLE;
1403
1404         if (!amdgpu_ttm_tt_is_readonly(ttm))
1405                 flags |= AMDGPU_PTE_WRITEABLE;
1406
1407         return flags;
1408 }
1409
1410 /**
1411  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1412  * object.
1413  *
1414  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1415  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1416  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1417  * used to clean out a memory space.
1418  */
1419 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1420                                             const struct ttm_place *place)
1421 {
1422         unsigned long num_pages = bo->mem.num_pages;
1423         struct drm_mm_node *node = bo->mem.mm_node;
1424         struct reservation_object_list *flist;
1425         struct dma_fence *f;
1426         int i;
1427
1428         /* Don't evict VM page tables while they are busy, otherwise we can't
1429          * cleanly handle page faults.
1430          */
1431         if (bo->type == ttm_bo_type_kernel &&
1432             !reservation_object_test_signaled_rcu(bo->resv, true))
1433                 return false;
1434
1435         /* If bo is a KFD BO, check if the bo belongs to the current process.
1436          * If true, then return false as any KFD process needs all its BOs to
1437          * be resident to run successfully
1438          */
1439         flist = reservation_object_get_list(bo->resv);
1440         if (flist) {
1441                 for (i = 0; i < flist->shared_count; ++i) {
1442                         f = rcu_dereference_protected(flist->shared[i],
1443                                 reservation_object_held(bo->resv));
1444                         if (amdkfd_fence_check_mm(f, current->mm))
1445                                 return false;
1446                 }
1447         }
1448
1449         switch (bo->mem.mem_type) {
1450         case TTM_PL_TT:
1451                 return true;
1452
1453         case TTM_PL_VRAM:
1454                 /* Check each drm MM node individually */
1455                 while (num_pages) {
1456                         if (place->fpfn < (node->start + node->size) &&
1457                             !(place->lpfn && place->lpfn <= node->start))
1458                                 return true;
1459
1460                         num_pages -= node->size;
1461                         ++node;
1462                 }
1463                 return false;
1464
1465         default:
1466                 break;
1467         }
1468
1469         return ttm_bo_eviction_valuable(bo, place);
1470 }
1471
1472 /**
1473  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1474  *
1475  * @bo:  The buffer object to read/write
1476  * @offset:  Offset into buffer object
1477  * @buf:  Secondary buffer to write/read from
1478  * @len: Length in bytes of access
1479  * @write:  true if writing
1480  *
1481  * This is used to access VRAM that backs a buffer object via MMIO
1482  * access for debugging purposes.
1483  */
1484 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1485                                     unsigned long offset,
1486                                     void *buf, int len, int write)
1487 {
1488         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1489         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1490         struct drm_mm_node *nodes;
1491         uint32_t value = 0;
1492         int ret = 0;
1493         uint64_t pos;
1494         unsigned long flags;
1495
1496         if (bo->mem.mem_type != TTM_PL_VRAM)
1497                 return -EIO;
1498
1499         nodes = amdgpu_find_mm_node(&abo->tbo.mem, &offset);
1500         pos = (nodes->start << PAGE_SHIFT) + offset;
1501
1502         while (len && pos < adev->gmc.mc_vram_size) {
1503                 uint64_t aligned_pos = pos & ~(uint64_t)3;
1504                 uint32_t bytes = 4 - (pos & 3);
1505                 uint32_t shift = (pos & 3) * 8;
1506                 uint32_t mask = 0xffffffff << shift;
1507
1508                 if (len < bytes) {
1509                         mask &= 0xffffffff >> (bytes - len) * 8;
1510                         bytes = len;
1511                 }
1512
1513                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1514                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1515                 WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1516                 if (!write || mask != 0xffffffff)
1517                         value = RREG32_NO_KIQ(mmMM_DATA);
1518                 if (write) {
1519                         value &= ~mask;
1520                         value |= (*(uint32_t *)buf << shift) & mask;
1521                         WREG32_NO_KIQ(mmMM_DATA, value);
1522                 }
1523                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1524                 if (!write) {
1525                         value = (value & mask) >> shift;
1526                         memcpy(buf, &value, bytes);
1527                 }
1528
1529                 ret += bytes;
1530                 buf = (uint8_t *)buf + bytes;
1531                 pos += bytes;
1532                 len -= bytes;
1533                 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1534                         ++nodes;
1535                         pos = (nodes->start << PAGE_SHIFT);
1536                 }
1537         }
1538
1539         return ret;
1540 }
1541
1542 static struct ttm_bo_driver amdgpu_bo_driver = {
1543         .ttm_tt_create = &amdgpu_ttm_tt_create,
1544         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1545         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1546         .invalidate_caches = &amdgpu_invalidate_caches,
1547         .init_mem_type = &amdgpu_init_mem_type,
1548         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1549         .evict_flags = &amdgpu_evict_flags,
1550         .move = &amdgpu_bo_move,
1551         .verify_access = &amdgpu_verify_access,
1552         .move_notify = &amdgpu_bo_move_notify,
1553         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1554         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1555         .io_mem_free = &amdgpu_ttm_io_mem_free,
1556         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1557         .access_memory = &amdgpu_ttm_access_memory,
1558         .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1559 };
1560
1561 /*
1562  * Firmware Reservation functions
1563  */
1564 /**
1565  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1566  *
1567  * @adev: amdgpu_device pointer
1568  *
1569  * free fw reserved vram if it has been reserved.
1570  */
1571 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1572 {
1573         amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo,
1574                 NULL, &adev->fw_vram_usage.va);
1575 }
1576
1577 /**
1578  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1579  *
1580  * @adev: amdgpu_device pointer
1581  *
1582  * create bo vram reservation from fw.
1583  */
1584 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1585 {
1586         struct ttm_operation_ctx ctx = { false, false };
1587         struct amdgpu_bo_param bp;
1588         int r = 0;
1589         int i;
1590         u64 vram_size = adev->gmc.visible_vram_size;
1591         u64 offset = adev->fw_vram_usage.start_offset;
1592         u64 size = adev->fw_vram_usage.size;
1593         struct amdgpu_bo *bo;
1594
1595         memset(&bp, 0, sizeof(bp));
1596         bp.size = adev->fw_vram_usage.size;
1597         bp.byte_align = PAGE_SIZE;
1598         bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
1599         bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
1600                 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1601         bp.type = ttm_bo_type_kernel;
1602         bp.resv = NULL;
1603         adev->fw_vram_usage.va = NULL;
1604         adev->fw_vram_usage.reserved_bo = NULL;
1605
1606         if (adev->fw_vram_usage.size > 0 &&
1607                 adev->fw_vram_usage.size <= vram_size) {
1608
1609                 r = amdgpu_bo_create(adev, &bp,
1610                                      &adev->fw_vram_usage.reserved_bo);
1611                 if (r)
1612                         goto error_create;
1613
1614                 r = amdgpu_bo_reserve(adev->fw_vram_usage.reserved_bo, false);
1615                 if (r)
1616                         goto error_reserve;
1617
1618                 /* remove the original mem node and create a new one at the
1619                  * request position
1620                  */
1621                 bo = adev->fw_vram_usage.reserved_bo;
1622                 offset = ALIGN(offset, PAGE_SIZE);
1623                 for (i = 0; i < bo->placement.num_placement; ++i) {
1624                         bo->placements[i].fpfn = offset >> PAGE_SHIFT;
1625                         bo->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
1626                 }
1627
1628                 ttm_bo_mem_put(&bo->tbo, &bo->tbo.mem);
1629                 r = ttm_bo_mem_space(&bo->tbo, &bo->placement,
1630                                      &bo->tbo.mem, &ctx);
1631                 if (r)
1632                         goto error_pin;
1633
1634                 r = amdgpu_bo_pin_restricted(adev->fw_vram_usage.reserved_bo,
1635                         AMDGPU_GEM_DOMAIN_VRAM,
1636                         adev->fw_vram_usage.start_offset,
1637                         (adev->fw_vram_usage.start_offset +
1638                         adev->fw_vram_usage.size));
1639                 if (r)
1640                         goto error_pin;
1641                 r = amdgpu_bo_kmap(adev->fw_vram_usage.reserved_bo,
1642                         &adev->fw_vram_usage.va);
1643                 if (r)
1644                         goto error_kmap;
1645
1646                 amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
1647         }
1648         return r;
1649
1650 error_kmap:
1651         amdgpu_bo_unpin(adev->fw_vram_usage.reserved_bo);
1652 error_pin:
1653         amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
1654 error_reserve:
1655         amdgpu_bo_unref(&adev->fw_vram_usage.reserved_bo);
1656 error_create:
1657         adev->fw_vram_usage.va = NULL;
1658         adev->fw_vram_usage.reserved_bo = NULL;
1659         return r;
1660 }
1661 /**
1662  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1663  * gtt/vram related fields.
1664  *
1665  * This initializes all of the memory space pools that the TTM layer
1666  * will need such as the GTT space (system memory mapped to the device),
1667  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1668  * can be mapped per VMID.
1669  */
1670 int amdgpu_ttm_init(struct amdgpu_device *adev)
1671 {
1672         uint64_t gtt_size;
1673         int r;
1674         u64 vis_vram_limit;
1675
1676         mutex_init(&adev->mman.gtt_window_lock);
1677
1678         /* No others user of address space so set it to 0 */
1679         r = ttm_bo_device_init(&adev->mman.bdev,
1680                                &amdgpu_bo_driver,
1681                                adev->ddev->anon_inode->i_mapping,
1682                                adev->need_dma32);
1683         if (r) {
1684                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1685                 return r;
1686         }
1687         adev->mman.initialized = true;
1688
1689         /* We opt to avoid OOM on system pages allocations */
1690         adev->mman.bdev.no_retry = true;
1691
1692         /* Initialize VRAM pool with all of VRAM divided into pages */
1693         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1694                                 adev->gmc.real_vram_size >> PAGE_SHIFT);
1695         if (r) {
1696                 DRM_ERROR("Failed initializing VRAM heap.\n");
1697                 return r;
1698         }
1699
1700         /* Reduce size of CPU-visible VRAM if requested */
1701         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1702         if (amdgpu_vis_vram_limit > 0 &&
1703             vis_vram_limit <= adev->gmc.visible_vram_size)
1704                 adev->gmc.visible_vram_size = vis_vram_limit;
1705
1706         /* Change the size here instead of the init above so only lpfn is affected */
1707         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1708 #ifdef CONFIG_64BIT
1709         adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1710                                                 adev->gmc.visible_vram_size);
1711 #endif
1712
1713         /*
1714          *The reserved vram for firmware must be pinned to the specified
1715          *place on the VRAM, so reserve it early.
1716          */
1717         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1718         if (r) {
1719                 return r;
1720         }
1721
1722         /* allocate memory as required for VGA
1723          * This is used for VGA emulation and pre-OS scanout buffers to
1724          * avoid display artifacts while transitioning between pre-OS
1725          * and driver.  */
1726         r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE,
1727                                     AMDGPU_GEM_DOMAIN_VRAM,
1728                                     &adev->stolen_vga_memory,
1729                                     NULL, NULL);
1730         if (r)
1731                 return r;
1732         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1733                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1734
1735         /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1736          * or whatever the user passed on module init */
1737         if (amdgpu_gtt_size == -1) {
1738                 struct sysinfo si;
1739
1740                 si_meminfo(&si);
1741                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1742                                adev->gmc.mc_vram_size),
1743                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1744         }
1745         else
1746                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1747
1748         /* Initialize GTT memory pool */
1749         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
1750         if (r) {
1751                 DRM_ERROR("Failed initializing GTT heap.\n");
1752                 return r;
1753         }
1754         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1755                  (unsigned)(gtt_size / (1024 * 1024)));
1756
1757         /* Initialize various on-chip memory pools */
1758         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1759                            adev->gds.gds_size);
1760         if (r) {
1761                 DRM_ERROR("Failed initializing GDS heap.\n");
1762                 return r;
1763         }
1764
1765         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1766                            adev->gds.gws_size);
1767         if (r) {
1768                 DRM_ERROR("Failed initializing gws heap.\n");
1769                 return r;
1770         }
1771
1772         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1773                            adev->gds.oa_size);
1774         if (r) {
1775                 DRM_ERROR("Failed initializing oa heap.\n");
1776                 return r;
1777         }
1778
1779         /* Register debugfs entries for amdgpu_ttm */
1780         r = amdgpu_ttm_debugfs_init(adev);
1781         if (r) {
1782                 DRM_ERROR("Failed to init debugfs\n");
1783                 return r;
1784         }
1785         return 0;
1786 }
1787
1788 /**
1789  * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm
1790  */
1791 void amdgpu_ttm_late_init(struct amdgpu_device *adev)
1792 {
1793         /* return the VGA stolen memory (if any) back to VRAM */
1794         amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL);
1795 }
1796
1797 /**
1798  * amdgpu_ttm_fini - De-initialize the TTM memory pools
1799  */
1800 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1801 {
1802         if (!adev->mman.initialized)
1803                 return;
1804
1805         amdgpu_ttm_debugfs_fini(adev);
1806         amdgpu_ttm_fw_reserve_vram_fini(adev);
1807         if (adev->mman.aper_base_kaddr)
1808                 iounmap(adev->mman.aper_base_kaddr);
1809         adev->mman.aper_base_kaddr = NULL;
1810
1811         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1812         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1813         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1814         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1815         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1816         ttm_bo_device_release(&adev->mman.bdev);
1817         adev->mman.initialized = false;
1818         DRM_INFO("amdgpu: ttm finalized\n");
1819 }
1820
1821 /**
1822  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
1823  *
1824  * @adev: amdgpu_device pointer
1825  * @enable: true when we can use buffer functions.
1826  *
1827  * Enable/disable use of buffer functions during suspend/resume. This should
1828  * only be called at bootup or when userspace isn't running.
1829  */
1830 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
1831 {
1832         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[TTM_PL_VRAM];
1833         uint64_t size;
1834         int r;
1835
1836         if (!adev->mman.initialized || adev->in_gpu_reset ||
1837             adev->mman.buffer_funcs_enabled == enable)
1838                 return;
1839
1840         if (enable) {
1841                 struct amdgpu_ring *ring;
1842                 struct drm_sched_rq *rq;
1843
1844                 ring = adev->mman.buffer_funcs_ring;
1845                 rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
1846                 r = drm_sched_entity_init(&adev->mman.entity, &rq, 1, NULL);
1847                 if (r) {
1848                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
1849                                   r);
1850                         return;
1851                 }
1852         } else {
1853                 drm_sched_entity_destroy(&adev->mman.entity);
1854                 dma_fence_put(man->move);
1855                 man->move = NULL;
1856         }
1857
1858         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1859         if (enable)
1860                 size = adev->gmc.real_vram_size;
1861         else
1862                 size = adev->gmc.visible_vram_size;
1863         man->size = size >> PAGE_SHIFT;
1864         adev->mman.buffer_funcs_enabled = enable;
1865 }
1866
1867 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1868 {
1869         struct drm_file *file_priv = filp->private_data;
1870         struct amdgpu_device *adev = file_priv->minor->dev->dev_private;
1871
1872         if (adev == NULL)
1873                 return -EINVAL;
1874
1875         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1876 }
1877
1878 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
1879                              struct ttm_mem_reg *mem, unsigned num_pages,
1880                              uint64_t offset, unsigned window,
1881                              struct amdgpu_ring *ring,
1882                              uint64_t *addr)
1883 {
1884         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
1885         struct amdgpu_device *adev = ring->adev;
1886         struct ttm_tt *ttm = bo->ttm;
1887         struct amdgpu_job *job;
1888         unsigned num_dw, num_bytes;
1889         dma_addr_t *dma_address;
1890         struct dma_fence *fence;
1891         uint64_t src_addr, dst_addr;
1892         uint64_t flags;
1893         int r;
1894
1895         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
1896                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
1897
1898         *addr = adev->gmc.gart_start;
1899         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
1900                 AMDGPU_GPU_PAGE_SIZE;
1901
1902         num_dw = adev->mman.buffer_funcs->copy_num_dw;
1903         while (num_dw & 0x7)
1904                 num_dw++;
1905
1906         num_bytes = num_pages * 8;
1907
1908         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, &job);
1909         if (r)
1910                 return r;
1911
1912         src_addr = num_dw * 4;
1913         src_addr += job->ibs[0].gpu_addr;
1914
1915         dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
1916         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
1917         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
1918                                 dst_addr, num_bytes);
1919
1920         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1921         WARN_ON(job->ibs[0].length_dw > num_dw);
1922
1923         dma_address = &gtt->ttm.dma_address[offset >> PAGE_SHIFT];
1924         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, mem);
1925         r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
1926                             &job->ibs[0].ptr[num_dw]);
1927         if (r)
1928                 goto error_free;
1929
1930         r = amdgpu_job_submit(job, &adev->mman.entity,
1931                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
1932         if (r)
1933                 goto error_free;
1934
1935         dma_fence_put(fence);
1936
1937         return r;
1938
1939 error_free:
1940         amdgpu_job_free(job);
1941         return r;
1942 }
1943
1944 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
1945                        uint64_t dst_offset, uint32_t byte_count,
1946                        struct reservation_object *resv,
1947                        struct dma_fence **fence, bool direct_submit,
1948                        bool vm_needs_flush)
1949 {
1950         struct amdgpu_device *adev = ring->adev;
1951         struct amdgpu_job *job;
1952
1953         uint32_t max_bytes;
1954         unsigned num_loops, num_dw;
1955         unsigned i;
1956         int r;
1957
1958         if (direct_submit && !ring->sched.ready) {
1959                 DRM_ERROR("Trying to move memory with ring turned off.\n");
1960                 return -EINVAL;
1961         }
1962
1963         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1964         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1965         num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1966
1967         /* for IB padding */
1968         while (num_dw & 0x7)
1969                 num_dw++;
1970
1971         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1972         if (r)
1973                 return r;
1974
1975         if (vm_needs_flush) {
1976                 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
1977                 job->vm_needs_flush = true;
1978         }
1979         if (resv) {
1980                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1981                                      AMDGPU_FENCE_OWNER_UNDEFINED,
1982                                      false);
1983                 if (r) {
1984                         DRM_ERROR("sync failed (%d).\n", r);
1985                         goto error_free;
1986                 }
1987         }
1988
1989         for (i = 0; i < num_loops; i++) {
1990                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1991
1992                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1993                                         dst_offset, cur_size_in_bytes);
1994
1995                 src_offset += cur_size_in_bytes;
1996                 dst_offset += cur_size_in_bytes;
1997                 byte_count -= cur_size_in_bytes;
1998         }
1999
2000         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2001         WARN_ON(job->ibs[0].length_dw > num_dw);
2002         if (direct_submit)
2003                 r = amdgpu_job_submit_direct(job, ring, fence);
2004         else
2005                 r = amdgpu_job_submit(job, &adev->mman.entity,
2006                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2007         if (r)
2008                 goto error_free;
2009
2010         return r;
2011
2012 error_free:
2013         amdgpu_job_free(job);
2014         DRM_ERROR("Error scheduling IBs (%d)\n", r);
2015         return r;
2016 }
2017
2018 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2019                        uint32_t src_data,
2020                        struct reservation_object *resv,
2021                        struct dma_fence **fence)
2022 {
2023         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2024         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2025         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2026
2027         struct drm_mm_node *mm_node;
2028         unsigned long num_pages;
2029         unsigned int num_loops, num_dw;
2030
2031         struct amdgpu_job *job;
2032         int r;
2033
2034         if (!adev->mman.buffer_funcs_enabled) {
2035                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
2036                 return -EINVAL;
2037         }
2038
2039         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
2040                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
2041                 if (r)
2042                         return r;
2043         }
2044
2045         num_pages = bo->tbo.num_pages;
2046         mm_node = bo->tbo.mem.mm_node;
2047         num_loops = 0;
2048         while (num_pages) {
2049                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
2050
2051                 num_loops += DIV_ROUND_UP(byte_count, max_bytes);
2052                 num_pages -= mm_node->size;
2053                 ++mm_node;
2054         }
2055         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2056
2057         /* for IB padding */
2058         num_dw += 64;
2059
2060         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
2061         if (r)
2062                 return r;
2063
2064         if (resv) {
2065                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2066                                      AMDGPU_FENCE_OWNER_UNDEFINED, false);
2067                 if (r) {
2068                         DRM_ERROR("sync failed (%d).\n", r);
2069                         goto error_free;
2070                 }
2071         }
2072
2073         num_pages = bo->tbo.num_pages;
2074         mm_node = bo->tbo.mem.mm_node;
2075
2076         while (num_pages) {
2077                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
2078                 uint64_t dst_addr;
2079
2080                 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
2081                 while (byte_count) {
2082                         uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2083
2084                         amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
2085                                                 dst_addr, cur_size_in_bytes);
2086
2087                         dst_addr += cur_size_in_bytes;
2088                         byte_count -= cur_size_in_bytes;
2089                 }
2090
2091                 num_pages -= mm_node->size;
2092                 ++mm_node;
2093         }
2094
2095         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2096         WARN_ON(job->ibs[0].length_dw > num_dw);
2097         r = amdgpu_job_submit(job, &adev->mman.entity,
2098                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2099         if (r)
2100                 goto error_free;
2101
2102         return 0;
2103
2104 error_free:
2105         amdgpu_job_free(job);
2106         return r;
2107 }
2108
2109 #if defined(CONFIG_DEBUG_FS)
2110
2111 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
2112 {
2113         struct drm_info_node *node = (struct drm_info_node *)m->private;
2114         unsigned ttm_pl = (uintptr_t)node->info_ent->data;
2115         struct drm_device *dev = node->minor->dev;
2116         struct amdgpu_device *adev = dev->dev_private;
2117         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[ttm_pl];
2118         struct drm_printer p = drm_seq_file_printer(m);
2119
2120         man->func->debug(man, &p);
2121         return 0;
2122 }
2123
2124 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
2125         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM},
2126         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT},
2127         {"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS},
2128         {"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS},
2129         {"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA},
2130         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
2131 #ifdef CONFIG_SWIOTLB
2132         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
2133 #endif
2134 };
2135
2136 /**
2137  * amdgpu_ttm_vram_read - Linear read access to VRAM
2138  *
2139  * Accesses VRAM via MMIO for debugging purposes.
2140  */
2141 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2142                                     size_t size, loff_t *pos)
2143 {
2144         struct amdgpu_device *adev = file_inode(f)->i_private;
2145         ssize_t result = 0;
2146         int r;
2147
2148         if (size & 0x3 || *pos & 0x3)
2149                 return -EINVAL;
2150
2151         if (*pos >= adev->gmc.mc_vram_size)
2152                 return -ENXIO;
2153
2154         while (size) {
2155                 unsigned long flags;
2156                 uint32_t value;
2157
2158                 if (*pos >= adev->gmc.mc_vram_size)
2159                         return result;
2160
2161                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2162                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2163                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2164                 value = RREG32_NO_KIQ(mmMM_DATA);
2165                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2166
2167                 r = put_user(value, (uint32_t *)buf);
2168                 if (r)
2169                         return r;
2170
2171                 result += 4;
2172                 buf += 4;
2173                 *pos += 4;
2174                 size -= 4;
2175         }
2176
2177         return result;
2178 }
2179
2180 /**
2181  * amdgpu_ttm_vram_write - Linear write access to VRAM
2182  *
2183  * Accesses VRAM via MMIO for debugging purposes.
2184  */
2185 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2186                                     size_t size, loff_t *pos)
2187 {
2188         struct amdgpu_device *adev = file_inode(f)->i_private;
2189         ssize_t result = 0;
2190         int r;
2191
2192         if (size & 0x3 || *pos & 0x3)
2193                 return -EINVAL;
2194
2195         if (*pos >= adev->gmc.mc_vram_size)
2196                 return -ENXIO;
2197
2198         while (size) {
2199                 unsigned long flags;
2200                 uint32_t value;
2201
2202                 if (*pos >= adev->gmc.mc_vram_size)
2203                         return result;
2204
2205                 r = get_user(value, (uint32_t *)buf);
2206                 if (r)
2207                         return r;
2208
2209                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2210                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2211                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2212                 WREG32_NO_KIQ(mmMM_DATA, value);
2213                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2214
2215                 result += 4;
2216                 buf += 4;
2217                 *pos += 4;
2218                 size -= 4;
2219         }
2220
2221         return result;
2222 }
2223
2224 static const struct file_operations amdgpu_ttm_vram_fops = {
2225         .owner = THIS_MODULE,
2226         .read = amdgpu_ttm_vram_read,
2227         .write = amdgpu_ttm_vram_write,
2228         .llseek = default_llseek,
2229 };
2230
2231 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2232
2233 /**
2234  * amdgpu_ttm_gtt_read - Linear read access to GTT memory
2235  */
2236 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
2237                                    size_t size, loff_t *pos)
2238 {
2239         struct amdgpu_device *adev = file_inode(f)->i_private;
2240         ssize_t result = 0;
2241         int r;
2242
2243         while (size) {
2244                 loff_t p = *pos / PAGE_SIZE;
2245                 unsigned off = *pos & ~PAGE_MASK;
2246                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
2247                 struct page *page;
2248                 void *ptr;
2249
2250                 if (p >= adev->gart.num_cpu_pages)
2251                         return result;
2252
2253                 page = adev->gart.pages[p];
2254                 if (page) {
2255                         ptr = kmap(page);
2256                         ptr += off;
2257
2258                         r = copy_to_user(buf, ptr, cur_size);
2259                         kunmap(adev->gart.pages[p]);
2260                 } else
2261                         r = clear_user(buf, cur_size);
2262
2263                 if (r)
2264                         return -EFAULT;
2265
2266                 result += cur_size;
2267                 buf += cur_size;
2268                 *pos += cur_size;
2269                 size -= cur_size;
2270         }
2271
2272         return result;
2273 }
2274
2275 static const struct file_operations amdgpu_ttm_gtt_fops = {
2276         .owner = THIS_MODULE,
2277         .read = amdgpu_ttm_gtt_read,
2278         .llseek = default_llseek
2279 };
2280
2281 #endif
2282
2283 /**
2284  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2285  *
2286  * This function is used to read memory that has been mapped to the
2287  * GPU and the known addresses are not physical addresses but instead
2288  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2289  */
2290 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2291                                  size_t size, loff_t *pos)
2292 {
2293         struct amdgpu_device *adev = file_inode(f)->i_private;
2294         struct iommu_domain *dom;
2295         ssize_t result = 0;
2296         int r;
2297
2298         /* retrieve the IOMMU domain if any for this device */
2299         dom = iommu_get_domain_for_dev(adev->dev);
2300
2301         while (size) {
2302                 phys_addr_t addr = *pos & PAGE_MASK;
2303                 loff_t off = *pos & ~PAGE_MASK;
2304                 size_t bytes = PAGE_SIZE - off;
2305                 unsigned long pfn;
2306                 struct page *p;
2307                 void *ptr;
2308
2309                 bytes = bytes < size ? bytes : size;
2310
2311                 /* Translate the bus address to a physical address.  If
2312                  * the domain is NULL it means there is no IOMMU active
2313                  * and the address translation is the identity
2314                  */
2315                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2316
2317                 pfn = addr >> PAGE_SHIFT;
2318                 if (!pfn_valid(pfn))
2319                         return -EPERM;
2320
2321                 p = pfn_to_page(pfn);
2322                 if (p->mapping != adev->mman.bdev.dev_mapping)
2323                         return -EPERM;
2324
2325                 ptr = kmap(p);
2326                 r = copy_to_user(buf, ptr + off, bytes);
2327                 kunmap(p);
2328                 if (r)
2329                         return -EFAULT;
2330
2331                 size -= bytes;
2332                 *pos += bytes;
2333                 result += bytes;
2334         }
2335
2336         return result;
2337 }
2338
2339 /**
2340  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2341  *
2342  * This function is used to write memory that has been mapped to the
2343  * GPU and the known addresses are not physical addresses but instead
2344  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2345  */
2346 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2347                                  size_t size, loff_t *pos)
2348 {
2349         struct amdgpu_device *adev = file_inode(f)->i_private;
2350         struct iommu_domain *dom;
2351         ssize_t result = 0;
2352         int r;
2353
2354         dom = iommu_get_domain_for_dev(adev->dev);
2355
2356         while (size) {
2357                 phys_addr_t addr = *pos & PAGE_MASK;
2358                 loff_t off = *pos & ~PAGE_MASK;
2359                 size_t bytes = PAGE_SIZE - off;
2360                 unsigned long pfn;
2361                 struct page *p;
2362                 void *ptr;
2363
2364                 bytes = bytes < size ? bytes : size;
2365
2366                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2367
2368                 pfn = addr >> PAGE_SHIFT;
2369                 if (!pfn_valid(pfn))
2370                         return -EPERM;
2371
2372                 p = pfn_to_page(pfn);
2373                 if (p->mapping != adev->mman.bdev.dev_mapping)
2374                         return -EPERM;
2375
2376                 ptr = kmap(p);
2377                 r = copy_from_user(ptr + off, buf, bytes);
2378                 kunmap(p);
2379                 if (r)
2380                         return -EFAULT;
2381
2382                 size -= bytes;
2383                 *pos += bytes;
2384                 result += bytes;
2385         }
2386
2387         return result;
2388 }
2389
2390 static const struct file_operations amdgpu_ttm_iomem_fops = {
2391         .owner = THIS_MODULE,
2392         .read = amdgpu_iomem_read,
2393         .write = amdgpu_iomem_write,
2394         .llseek = default_llseek
2395 };
2396
2397 static const struct {
2398         char *name;
2399         const struct file_operations *fops;
2400         int domain;
2401 } ttm_debugfs_entries[] = {
2402         { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
2403 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2404         { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
2405 #endif
2406         { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM },
2407 };
2408
2409 #endif
2410
2411 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2412 {
2413 #if defined(CONFIG_DEBUG_FS)
2414         unsigned count;
2415
2416         struct drm_minor *minor = adev->ddev->primary;
2417         struct dentry *ent, *root = minor->debugfs_root;
2418
2419         for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
2420                 ent = debugfs_create_file(
2421                                 ttm_debugfs_entries[count].name,
2422                                 S_IFREG | S_IRUGO, root,
2423                                 adev,
2424                                 ttm_debugfs_entries[count].fops);
2425                 if (IS_ERR(ent))
2426                         return PTR_ERR(ent);
2427                 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
2428                         i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2429                 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2430                         i_size_write(ent->d_inode, adev->gmc.gart_size);
2431                 adev->mman.debugfs_entries[count] = ent;
2432         }
2433
2434         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
2435
2436 #ifdef CONFIG_SWIOTLB
2437         if (!(adev->need_swiotlb && swiotlb_nr_tbl()))
2438                 --count;
2439 #endif
2440
2441         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
2442 #else
2443         return 0;
2444 #endif
2445 }
2446
2447 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
2448 {
2449 #if defined(CONFIG_DEBUG_FS)
2450         unsigned i;
2451
2452         for (i = 0; i < ARRAY_SIZE(ttm_debugfs_entries); i++)
2453                 debugfs_remove(adev->mman.debugfs_entries[i]);
2454 #endif
2455 }