drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <[email protected]>
  23  *          Alex Deucher <[email protected]>
  24  */
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_drv.h"
  28 #include "amdgpu_pm.h"
  29 #include "amdgpu_dpm.h"
  30 #include "amdgpu_display.h"
  31 #include "amdgpu_smu.h"
  32 #include "atom.h"
  33 #include <linux/power_supply.h>
  34 #include <linux/hwmon.h>
  35 #include <linux/hwmon-sysfs.h>
  36 #include <linux/nospec.h>
  37 #include "hwmgr.h"
  38 #define WIDTH_4K 3840
  39
  40 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
  41
  42 static const struct cg_flag_name clocks[] = {
  43         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  44         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  45         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  46         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  47         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  48         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  49         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  50         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  51         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
  52         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
  53         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  54         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  55         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  56         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  57         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
  58         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  59         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  60         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  61         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  62         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  63         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
  64         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
  65         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  66         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
  67         {0, NULL},
  68 };
  69
  70 static const struct hwmon_temp_label {
  71         enum PP_HWMON_TEMP channel;
  72         const char *label;
  73 } temp_label[] = {
  74         {PP_TEMP_EDGE, "edge"},
  75         {PP_TEMP_JUNCTION, "junction"},
  76         {PP_TEMP_MEM, "mem"},
  77 };
  78
  79 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  80 {
  81         if (adev->pm.dpm_enabled) {
  82                 mutex_lock(&adev->pm.mutex);
  83                 if (power_supply_is_system_supplied() > 0)
  84                         adev->pm.ac_power = true;
  85                 else
  86                         adev->pm.ac_power = false;
  87                 if (adev->powerplay.pp_funcs->enable_bapm)
  88                         amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power);
  89                 mutex_unlock(&adev->pm.mutex);
  90         }
  91 }
  92
  93 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor,
  94                            void *data, uint32_t *size)
  95 {
  96         int ret = 0;
  97
  98         if (!data || !size)
  99                 return -EINVAL;
 100
 101         if (is_support_sw_smu(adev))
 102                 ret = smu_read_sensor(&adev->smu, sensor, data, size);
 103         else {
 104                 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
 105                         ret = adev->powerplay.pp_funcs->read_sensor((adev)->powerplay.pp_handle,
 106                                                                     sensor, data, size);
 107                 else
 108                         ret = -EINVAL;
 109         }
 110
 111         return ret;
 112 }
 113
 114 /**
 115  * DOC: power_dpm_state
 116  *
 117  * The power_dpm_state file is a legacy interface and is only provided for
 118  * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
 119  * certain power related parameters.  The file power_dpm_state is used for this.
 120  * It accepts the following arguments:
 121  *
 122  * - battery
 123  *
 124  * - balanced
 125  *
 126  * - performance
 127  *
 128  * battery
 129  *
 130  * On older GPUs, the vbios provided a special power state for battery
 131  * operation.  Selecting battery switched to this state.  This is no
 132  * longer provided on newer GPUs so the option does nothing in that case.
 133  *
 134  * balanced
 135  *
 136  * On older GPUs, the vbios provided a special power state for balanced
 137  * operation.  Selecting balanced switched to this state.  This is no
 138  * longer provided on newer GPUs so the option does nothing in that case.
 139  *
 140  * performance
 141  *
 142  * On older GPUs, the vbios provided a special power state for performance
 143  * operation.  Selecting performance switched to this state.  This is no
 144  * longer provided on newer GPUs so the option does nothing in that case.
 145  *
 146  */
 147
 148 static ssize_t amdgpu_get_dpm_state(struct device *dev,
 149                                     struct device_attribute *attr,
 150                                     char *buf)
 151 {
 152         struct drm_device *ddev = dev_get_drvdata(dev);
 153         struct amdgpu_device *adev = ddev->dev_private;
 154         enum amd_pm_state_type pm;
 155
 156         if (is_support_sw_smu(adev) && adev->smu.ppt_funcs->get_current_power_state)
 157                 pm = amdgpu_smu_get_current_power_state(adev);
 158         else if (adev->powerplay.pp_funcs->get_current_power_state)
 159                 pm = amdgpu_dpm_get_current_power_state(adev);
 160         else
 161                 pm = adev->pm.dpm.user_state;
 162
 163         return snprintf(buf, PAGE_SIZE, "%s\n",
 164                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 165                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 166 }
 167
 168 static ssize_t amdgpu_set_dpm_state(struct device *dev,
 169                                     struct device_attribute *attr,
 170                                     const char *buf,
 171                                     size_t count)
 172 {
 173         struct drm_device *ddev = dev_get_drvdata(dev);
 174         struct amdgpu_device *adev = ddev->dev_private;
 175         enum amd_pm_state_type  state;
 176
 177         if (strncmp("battery", buf, strlen("battery")) == 0)
 178                 state = POWER_STATE_TYPE_BATTERY;
 179         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 180                 state = POWER_STATE_TYPE_BALANCED;
 181         else if (strncmp("performance", buf, strlen("performance")) == 0)
 182                 state = POWER_STATE_TYPE_PERFORMANCE;
 183         else {
 184                 count = -EINVAL;
 185                 goto fail;
 186         }
 187
 188         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 189                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);
 190         } else {
 191                 mutex_lock(&adev->pm.mutex);
 192                 adev->pm.dpm.user_state = state;
 193                 mutex_unlock(&adev->pm.mutex);
 194
 195                 /* Can't set dpm state when the card is off */
 196                 if (!(adev->flags & AMD_IS_PX) ||
 197                     (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
 198                         amdgpu_pm_compute_clocks(adev);
 199         }
 200 fail:
 201         return count;
 202 }
 203
 204
 205 /**
 206  * DOC: power_dpm_force_performance_level
 207  *
 208  * The amdgpu driver provides a sysfs API for adjusting certain power
 209  * related parameters.  The file power_dpm_force_performance_level is
 210  * used for this.  It accepts the following arguments:
 211  *
 212  * - auto
 213  *
 214  * - low
 215  *
 216  * - high
 217  *
 218  * - manual
 219  *
 220  * - profile_standard
 221  *
 222  * - profile_min_sclk
 223  *
 224  * - profile_min_mclk
 225  *
 226  * - profile_peak
 227  *
 228  * auto
 229  *
 230  * When auto is selected, the driver will attempt to dynamically select
 231  * the optimal power profile for current conditions in the driver.
 232  *
 233  * low
 234  *
 235  * When low is selected, the clocks are forced to the lowest power state.
 236  *
 237  * high
 238  *
 239  * When high is selected, the clocks are forced to the highest power state.
 240  *
 241  * manual
 242  *
 243  * When manual is selected, the user can manually adjust which power states
 244  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 245  * and pp_dpm_pcie files and adjust the power state transition heuristics
 246  * via the pp_power_profile_mode sysfs file.
 247  *
 248  * profile_standard
 249  * profile_min_sclk
 250  * profile_min_mclk
 251  * profile_peak
 252  *
 253  * When the profiling modes are selected, clock and power gating are
 254  * disabled and the clocks are set for different profiling cases. This
 255  * mode is recommended for profiling specific work loads where you do
 256  * not want clock or power gating for clock fluctuation to interfere
 257  * with your results. profile_standard sets the clocks to a fixed clock
 258  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 259  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 260  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 261  *
 262  */
 263
 264 static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
 265                                                 struct device_attribute *attr,
 266                                                                 char *buf)
 267 {
 268         struct drm_device *ddev = dev_get_drvdata(dev);
 269         struct amdgpu_device *adev = ddev->dev_private;
 270         enum amd_dpm_forced_level level = 0xff;
 271
 272         if (amdgpu_sriov_vf(adev))
 273                 return 0;
 274
 275         if ((adev->flags & AMD_IS_PX) &&
 276             (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 277                 return snprintf(buf, PAGE_SIZE, "off\n");
 278
 279         if (is_support_sw_smu(adev))
 280                 level = smu_get_performance_level(&adev->smu);
 281         else if (adev->powerplay.pp_funcs->get_performance_level)
 282                 level = amdgpu_dpm_get_performance_level(adev);
 283         else
 284                 level = adev->pm.dpm.forced_level;
 285
 286         return snprintf(buf, PAGE_SIZE, "%s\n",
 287                         (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 288                         (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 289                         (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 290                         (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 291                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 292                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 293                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 294                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 295                         "unknown");
 296 }
 297
 298 static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
 299                                                        struct device_attribute *attr,
 300                                                        const char *buf,
 301                                                        size_t count)
 302 {
 303         struct drm_device *ddev = dev_get_drvdata(dev);
 304         struct amdgpu_device *adev = ddev->dev_private;
 305         enum amd_dpm_forced_level level;
 306         enum amd_dpm_forced_level current_level = 0xff;
 307         int ret = 0;
 308
 309         /* Can't force performance level when the card is off */
 310         if  ((adev->flags & AMD_IS_PX) &&
 311              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 312                 return -EINVAL;
 313
 314         if (!amdgpu_sriov_vf(adev)) {
 315                 if (is_support_sw_smu(adev))
 316                         current_level = smu_get_performance_level(&adev->smu);
 317                 else if (adev->powerplay.pp_funcs->get_performance_level)
 318                         current_level = amdgpu_dpm_get_performance_level(adev);
 319         }
 320
 321         if (strncmp("low", buf, strlen("low")) == 0) {
 322                 level = AMD_DPM_FORCED_LEVEL_LOW;
 323         } else if (strncmp("high", buf, strlen("high")) == 0) {
 324                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 325         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 326                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 327         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 328                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 329         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 330                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 331         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 332                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 333         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 334                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 335         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 336                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 337         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 338                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 339         }  else {
 340                 count = -EINVAL;
 341                 goto fail;
 342         }
 343
 344         if (amdgpu_sriov_vf(adev)) {
 345                 if (amdgim_is_hwperf(adev) &&
 346                     adev->virt.ops->force_dpm_level) {
 347                         mutex_lock(&adev->pm.mutex);
 348                         adev->virt.ops->force_dpm_level(adev, level);
 349                         mutex_unlock(&adev->pm.mutex);
 350                         return count;
 351                 } else {
 352                         return -EINVAL;
 353                 }
 354         }
 355
 356         if (current_level == level)
 357                 return count;
 358
 359         /* profile_exit setting is valid only when current mode is in profile mode */
 360         if (!(current_level & (AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
 361             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
 362             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
 363             AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) &&
 364             (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)) {
 365                 pr_err("Currently not in any profile mode!\n");
 366                 return -EINVAL;
 367         }
 368
 369         if (is_support_sw_smu(adev)) {
 370                 mutex_lock(&adev->pm.mutex);
 371                 if (adev->pm.dpm.thermal_active) {
 372                         count = -EINVAL;
 373                         mutex_unlock(&adev->pm.mutex);
 374                         goto fail;
 375                 }
 376                 ret = smu_force_performance_level(&adev->smu, level);
 377                 if (ret)
 378                         count = -EINVAL;
 379                 else
 380                         adev->pm.dpm.forced_level = level;
 381                 mutex_unlock(&adev->pm.mutex);
 382         } else if (adev->powerplay.pp_funcs->force_performance_level) {
 383                 mutex_lock(&adev->pm.mutex);
 384                 if (adev->pm.dpm.thermal_active) {
 385                         count = -EINVAL;
 386                         mutex_unlock(&adev->pm.mutex);
 387                         goto fail;
 388                 }
 389                 ret = amdgpu_dpm_force_performance_level(adev, level);
 390                 if (ret)
 391                         count = -EINVAL;
 392                 else
 393                         adev->pm.dpm.forced_level = level;
 394                 mutex_unlock(&adev->pm.mutex);
 395         }
 396
 397 fail:
 398         return count;
 399 }
 400
 401 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 402                 struct device_attribute *attr,
 403                 char *buf)
 404 {
 405         struct drm_device *ddev = dev_get_drvdata(dev);
 406         struct amdgpu_device *adev = ddev->dev_private;
 407         struct pp_states_info data;
 408         int i, buf_len, ret;
 409
 410         if (is_support_sw_smu(adev)) {
 411                 ret = smu_get_power_num_states(&adev->smu, &data);
 412                 if (ret)
 413                         return ret;
 414         } else if (adev->powerplay.pp_funcs->get_pp_num_states)
 415                 amdgpu_dpm_get_pp_num_states(adev, &data);
 416
 417         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 418         for (i = 0; i < data.nums; i++)
 419                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 420                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 421                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 422                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 423                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 424
 425         return buf_len;
 426 }
 427
 428 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 429                 struct device_attribute *attr,
 430                 char *buf)
 431 {
 432         struct drm_device *ddev = dev_get_drvdata(dev);
 433         struct amdgpu_device *adev = ddev->dev_private;
 434         struct pp_states_info data;
 435         struct smu_context *smu = &adev->smu;
 436         enum amd_pm_state_type pm = 0;
 437         int i = 0, ret = 0;
 438
 439         if (is_support_sw_smu(adev)) {
 440                 pm = smu_get_current_power_state(smu);
 441                 ret = smu_get_power_num_states(smu, &data);
 442                 if (ret)
 443                         return ret;
 444         } else if (adev->powerplay.pp_funcs->get_current_power_state
 445                  && adev->powerplay.pp_funcs->get_pp_num_states) {
 446                 pm = amdgpu_dpm_get_current_power_state(adev);
 447                 amdgpu_dpm_get_pp_num_states(adev, &data);
 448         }
 449
 450         for (i = 0; i < data.nums; i++) {
 451                 if (pm == data.states[i])
 452                         break;
 453         }
 454
 455         if (i == data.nums)
 456                 i = -EINVAL;
 457
 458         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 459 }
 460
 461 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 462                 struct device_attribute *attr,
 463                 char *buf)
 464 {
 465         struct drm_device *ddev = dev_get_drvdata(dev);
 466         struct amdgpu_device *adev = ddev->dev_private;
 467
 468         if (adev->pp_force_state_enabled)
 469                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 470         else
 471                 return snprintf(buf, PAGE_SIZE, "\n");
 472 }
 473
 474 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 475                 struct device_attribute *attr,
 476                 const char *buf,
 477                 size_t count)
 478 {
 479         struct drm_device *ddev = dev_get_drvdata(dev);
 480         struct amdgpu_device *adev = ddev->dev_private;
 481         enum amd_pm_state_type state = 0;
 482         unsigned long idx;
 483         int ret;
 484
 485         if (strlen(buf) == 1)
 486                 adev->pp_force_state_enabled = false;
 487         else if (is_support_sw_smu(adev))
 488                 adev->pp_force_state_enabled = false;
 489         else if (adev->powerplay.pp_funcs->dispatch_tasks &&
 490                         adev->powerplay.pp_funcs->get_pp_num_states) {
 491                 struct pp_states_info data;
 492
 493                 ret = kstrtoul(buf, 0, &idx);
 494                 if (ret || idx >= ARRAY_SIZE(data.states)) {
 495                         count = -EINVAL;
 496                         goto fail;
 497                 }
 498                 idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
 499
 500                 amdgpu_dpm_get_pp_num_states(adev, &data);
 501                 state = data.states[idx];
 502                 /* only set user selected power states */
 503                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 504                     state != POWER_STATE_TYPE_DEFAULT) {
 505                         amdgpu_dpm_dispatch_task(adev,
 506                                         AMD_PP_TASK_ENABLE_USER_STATE, &state);
 507                         adev->pp_force_state_enabled = true;
 508                 }
 509         }
 510 fail:
 511         return count;
 512 }
 513
 514 /**
 515  * DOC: pp_table
 516  *
 517  * The amdgpu driver provides a sysfs API for uploading new powerplay
 518  * tables.  The file pp_table is used for this.  Reading the file
 519  * will dump the current power play table.  Writing to the file
 520  * will attempt to upload a new powerplay table and re-initialize
 521  * powerplay using that new table.
 522  *
 523  */
 524
 525 static ssize_t amdgpu_get_pp_table(struct device *dev,
 526                 struct device_attribute *attr,
 527                 char *buf)
 528 {
 529         struct drm_device *ddev = dev_get_drvdata(dev);
 530         struct amdgpu_device *adev = ddev->dev_private;
 531         char *table = NULL;
 532         int size;
 533
 534         if (is_support_sw_smu(adev)) {
 535                 size = smu_sys_get_pp_table(&adev->smu, (void **)&table);
 536                 if (size < 0)
 537                         return size;
 538         }
 539         else if (adev->powerplay.pp_funcs->get_pp_table)
 540                 size = amdgpu_dpm_get_pp_table(adev, &table);
 541         else
 542                 return 0;
 543
 544         if (size >= PAGE_SIZE)
 545                 size = PAGE_SIZE - 1;
 546
 547         memcpy(buf, table, size);
 548
 549         return size;
 550 }
 551
 552 static ssize_t amdgpu_set_pp_table(struct device *dev,
 553                 struct device_attribute *attr,
 554                 const char *buf,
 555                 size_t count)
 556 {
 557         struct drm_device *ddev = dev_get_drvdata(dev);
 558         struct amdgpu_device *adev = ddev->dev_private;
 559         int ret = 0;
 560
 561         if (is_support_sw_smu(adev)) {
 562                 ret = smu_sys_set_pp_table(&adev->smu, (void *)buf, count);
 563                 if (ret)
 564                         return ret;
 565         } else if (adev->powerplay.pp_funcs->set_pp_table)
 566                 amdgpu_dpm_set_pp_table(adev, buf, count);
 567
 568         return count;
 569 }
 570
 571 /**
 572  * DOC: pp_od_clk_voltage
 573  *
 574  * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
 575  * in each power level within a power state.  The pp_od_clk_voltage is used for
 576  * this.
 577  *
 578  * < For Vega10 and previous ASICs >
 579  *
 580  * Reading the file will display:
 581  *
 582  * - a list of engine clock levels and voltages labeled OD_SCLK
 583  *
 584  * - a list of memory clock levels and voltages labeled OD_MCLK
 585  *
 586  * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
 587  *
 588  * To manually adjust these settings, first select manual using
 589  * power_dpm_force_performance_level. Enter a new value for each
 590  * level by writing a string that contains "s/m level clock voltage" to
 591  * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
 592  * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
 593  * 810 mV.  When you have edited all of the states as needed, write
 594  * "c" (commit) to the file to commit your changes.  If you want to reset to the
 595  * default power levels, write "r" (reset) to the file to reset them.
 596  *
 597  *
 598  * < For Vega20 >
 599  *
 600  * Reading the file will display:
 601  *
 602  * - minimum and maximum engine clock labeled OD_SCLK
 603  *
 604  * - maximum memory clock labeled OD_MCLK
 605  *
 606  * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
 607  *   They can be used to calibrate the sclk voltage curve.
 608  *
 609  * - a list of valid ranges for sclk, mclk, and voltage curve points
 610  *   labeled OD_RANGE
 611  *
 612  * To manually adjust these settings:
 613  *
 614  * - First select manual using power_dpm_force_performance_level
 615  *
 616  * - For clock frequency setting, enter a new value by writing a
 617  *   string that contains "s/m index clock" to the file. The index
 618  *   should be 0 if to set minimum clock. And 1 if to set maximum
 619  *   clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
 620  *   "m 1 800" will update maximum mclk to be 800Mhz.
 621  *
 622  *   For sclk voltage curve, enter the new values by writing a
 623  *   string that contains "vc point clock voltage" to the file. The
 624  *   points are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will
 625  *   update point1 with clock set as 300Mhz and voltage as
 626  *   600mV. "vc 2 1000 1000" will update point3 with clock set
 627  *   as 1000Mhz and voltage 1000mV.
 628  *
 629  * - When you have edited all of the states as needed, write "c" (commit)
 630  *   to the file to commit your changes
 631  *
 632  * - If you want to reset to the default power levels, write "r" (reset)
 633  *   to the file to reset them
 634  *
 635  */
 636
 637 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 638                 struct device_attribute *attr,
 639                 const char *buf,
 640                 size_t count)
 641 {
 642         struct drm_device *ddev = dev_get_drvdata(dev);
 643         struct amdgpu_device *adev = ddev->dev_private;
 644         int ret;
 645         uint32_t parameter_size = 0;
 646         long parameter[64];
 647         char buf_cpy[128];
 648         char *tmp_str;
 649         char *sub_str;
 650         const char delimiter[3] = {' ', '\n', '\0'};
 651         uint32_t type;
 652
 653         if (count > 127)
 654                 return -EINVAL;
 655
 656         if (*buf == 's')
 657                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 658         else if (*buf == 'm')
 659                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 660         else if(*buf == 'r')
 661                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 662         else if (*buf == 'c')
 663                 type = PP_OD_COMMIT_DPM_TABLE;
 664         else if (!strncmp(buf, "vc", 2))
 665                 type = PP_OD_EDIT_VDDC_CURVE;
 666         else
 667                 return -EINVAL;
 668
 669         memcpy(buf_cpy, buf, count+1);
 670
 671         tmp_str = buf_cpy;
 672
 673         if (type == PP_OD_EDIT_VDDC_CURVE)
 674                 tmp_str++;
 675         while (isspace(*++tmp_str));
 676
 677         while (tmp_str[0]) {
 678                 sub_str = strsep(&tmp_str, delimiter);
 679                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 680                 if (ret)
 681                         return -EINVAL;
 682                 parameter_size++;
 683
 684                 while (isspace(*tmp_str))
 685                         tmp_str++;
 686         }
 687
 688         if (is_support_sw_smu(adev)) {
 689                 ret = smu_od_edit_dpm_table(&adev->smu, type,
 690                                             parameter, parameter_size);
 691
 692                 if (ret)
 693                         return -EINVAL;
 694         } else {
 695                 if (adev->powerplay.pp_funcs->odn_edit_dpm_table)
 696                         ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
 697                                                 parameter, parameter_size);
 698
 699                 if (ret)
 700                         return -EINVAL;
 701
 702                 if (type == PP_OD_COMMIT_DPM_TABLE) {
 703                         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 704                                 amdgpu_dpm_dispatch_task(adev,
 705                                                 AMD_PP_TASK_READJUST_POWER_STATE,
 706                                                 NULL);
 707                                 return count;
 708                         } else {
 709                                 return -EINVAL;
 710                         }
 711                 }
 712         }
 713
 714         return count;
 715 }
 716
 717 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 718                 struct device_attribute *attr,
 719                 char *buf)
 720 {
 721         struct drm_device *ddev = dev_get_drvdata(dev);
 722         struct amdgpu_device *adev = ddev->dev_private;
 723         uint32_t size = 0;
 724
 725         if (is_support_sw_smu(adev)) {
 726                 size = smu_print_clk_levels(&adev->smu, OD_SCLK, buf);
 727                 size += smu_print_clk_levels(&adev->smu, OD_MCLK, buf+size);
 728                 size += smu_print_clk_levels(&adev->smu, OD_VDDC_CURVE, buf+size);
 729                 size += smu_print_clk_levels(&adev->smu, OD_RANGE, buf+size);
 730                 return size;
 731         } else if (adev->powerplay.pp_funcs->print_clock_levels) {
 732                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 733                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
 734                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf+size);
 735                 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
 736                 return size;
 737         } else {
 738                 return snprintf(buf, PAGE_SIZE, "\n");
 739         }
 740
 741 }
 742
 743 /**
 744  * DOC: ppfeatures
 745  *
 746  * The amdgpu driver provides a sysfs API for adjusting what powerplay
 747  * features to be enabled. The file ppfeatures is used for this. And
 748  * this is only available for Vega10 and later dGPUs.
 749  *
 750  * Reading back the file will show you the followings:
 751  * - Current ppfeature masks
 752  * - List of the all supported powerplay features with their naming,
 753  *   bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
 754  *
 755  * To manually enable or disable a specific feature, just set or clear
 756  * the corresponding bit from original ppfeature masks and input the
 757  * new ppfeature masks.
 758  */
 759 static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
 760                 struct device_attribute *attr,
 761                 const char *buf,
 762                 size_t count)
 763 {
 764         struct drm_device *ddev = dev_get_drvdata(dev);
 765         struct amdgpu_device *adev = ddev->dev_private;
 766         uint64_t featuremask;
 767         int ret;
 768
 769         ret = kstrtou64(buf, 0, &featuremask);
 770         if (ret)
 771                 return -EINVAL;
 772
 773         pr_debug("featuremask = 0x%llx\n", featuremask);
 774
 775         if (is_support_sw_smu(adev)) {
 776                 ret = smu_set_ppfeature_status(&adev->smu, featuremask);
 777                 if (ret)
 778                         return -EINVAL;
 779         } else if (adev->powerplay.pp_funcs->set_ppfeature_status) {
 780                 ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
 781                 if (ret)
 782                         return -EINVAL;
 783         }
 784
 785         return count;
 786 }
 787
 788 static ssize_t amdgpu_get_ppfeature_status(struct device *dev,
 789                 struct device_attribute *attr,
 790                 char *buf)
 791 {
 792         struct drm_device *ddev = dev_get_drvdata(dev);
 793         struct amdgpu_device *adev = ddev->dev_private;
 794
 795         if (is_support_sw_smu(adev)) {
 796                 return smu_get_ppfeature_status(&adev->smu, buf);
 797         } else if (adev->powerplay.pp_funcs->get_ppfeature_status)
 798                 return amdgpu_dpm_get_ppfeature_status(adev, buf);
 799
 800         return snprintf(buf, PAGE_SIZE, "\n");
 801 }
 802
 803 /**
 804  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk
 805  * pp_dpm_pcie
 806  *
 807  * The amdgpu driver provides a sysfs API for adjusting what power levels
 808  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
 809  * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
 810  * this.
 811  *
 812  * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
 813  * Vega10 and later ASICs.
 814  * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
 815  *
 816  * Reading back the files will show you the available power levels within
 817  * the power state and the clock information for those levels.
 818  *
 819  * To manually adjust these states, first select manual using
 820  * power_dpm_force_performance_level.
 821  * Secondly,Enter a new value for each level by inputing a string that
 822  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
 823  * E.g., echo 4 5 6 to > pp_dpm_sclk will enable sclk levels 4, 5, and 6.
 824  *
 825  * NOTE: change to the dcefclk max dpm level is not supported now
 826  */
 827
 828 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
 829                 struct device_attribute *attr,
 830                 char *buf)
 831 {
 832         struct drm_device *ddev = dev_get_drvdata(dev);
 833         struct amdgpu_device *adev = ddev->dev_private;
 834
 835         if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev) &&
 836             adev->virt.ops->get_pp_clk)
 837                 return adev->virt.ops->get_pp_clk(adev, PP_SCLK, buf);
 838
 839         if (is_support_sw_smu(adev))
 840                 return smu_print_clk_levels(&adev->smu, PP_SCLK, buf);
 841         else if (adev->powerplay.pp_funcs->print_clock_levels)
 842                 return amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
 843         else
 844                 return snprintf(buf, PAGE_SIZE, "\n");
 845 }
 846
 847 /*
 848  * Worst case: 32 bits individually specified, in octal at 12 characters
 849  * per line (+1 for \n).
 850  */
 851 #define AMDGPU_MASK_BUF_MAX     (32 * 13)
 852
 853 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
 854 {
 855         int ret;
 856         long level;
 857         char *sub_str = NULL;
 858         char *tmp;
 859         char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
 860         const char delimiter[3] = {' ', '\n', '\0'};
 861         size_t bytes;
 862
 863         *mask = 0;
 864
 865         bytes = min(count, sizeof(buf_cpy) - 1);
 866         memcpy(buf_cpy, buf, bytes);
 867         buf_cpy[bytes] = '\0';
 868         tmp = buf_cpy;
 869         while (tmp[0]) {
 870                 sub_str = strsep(&tmp, delimiter);
 871                 if (strlen(sub_str)) {
 872                         ret = kstrtol(sub_str, 0, &level);
 873                         if (ret)
 874                                 return -EINVAL;
 875                         *mask |= 1 << level;
 876                 } else
 877                         break;
 878         }
 879
 880         return 0;
 881 }
 882
 883 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
 884                 struct device_attribute *attr,
 885                 const char *buf,
 886                 size_t count)
 887 {
 888         struct drm_device *ddev = dev_get_drvdata(dev);
 889         struct amdgpu_device *adev = ddev->dev_private;
 890         int ret;
 891         uint32_t mask = 0;
 892
 893         if (amdgpu_sriov_vf(adev))
 894                 return 0;
 895
 896         ret = amdgpu_read_mask(buf, count, &mask);
 897         if (ret)
 898                 return ret;
 899
 900         if (is_support_sw_smu(adev))
 901                 ret = smu_force_clk_levels(&adev->smu, PP_SCLK, mask);
 902         else if (adev->powerplay.pp_funcs->force_clock_level)
 903                 ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
 904
 905         if (ret)
 906                 return -EINVAL;
 907
 908         return count;
 909 }
 910
 911 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
 912                 struct device_attribute *attr,
 913                 char *buf)
 914 {
 915         struct drm_device *ddev = dev_get_drvdata(dev);
 916         struct amdgpu_device *adev = ddev->dev_private;
 917
 918         if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev) &&
 919             adev->virt.ops->get_pp_clk)
 920                 return adev->virt.ops->get_pp_clk(adev, PP_MCLK, buf);
 921
 922         if (is_support_sw_smu(adev))
 923                 return smu_print_clk_levels(&adev->smu, PP_MCLK, buf);
 924         else if (adev->powerplay.pp_funcs->print_clock_levels)
 925                 return amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
 926         else
 927                 return snprintf(buf, PAGE_SIZE, "\n");
 928 }
 929
 930 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
 931                 struct device_attribute *attr,
 932                 const char *buf,
 933                 size_t count)
 934 {
 935         struct drm_device *ddev = dev_get_drvdata(dev);
 936         struct amdgpu_device *adev = ddev->dev_private;
 937         int ret;
 938         uint32_t mask = 0;
 939
 940         if (amdgpu_sriov_vf(adev))
 941                 return 0;
 942
 943         ret = amdgpu_read_mask(buf, count, &mask);
 944         if (ret)
 945                 return ret;
 946
 947         if (is_support_sw_smu(adev))
 948                 ret = smu_force_clk_levels(&adev->smu, PP_MCLK, mask);
 949         else if (adev->powerplay.pp_funcs->force_clock_level)
 950                 ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
 951
 952         if (ret)
 953                 return -EINVAL;
 954
 955         return count;
 956 }
 957
 958 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
 959                 struct device_attribute *attr,
 960                 char *buf)
 961 {
 962         struct drm_device *ddev = dev_get_drvdata(dev);
 963         struct amdgpu_device *adev = ddev->dev_private;
 964
 965         if (is_support_sw_smu(adev))
 966                 return smu_print_clk_levels(&adev->smu, PP_SOCCLK, buf);
 967         else if (adev->powerplay.pp_funcs->print_clock_levels)
 968                 return amdgpu_dpm_print_clock_levels(adev, PP_SOCCLK, buf);
 969         else
 970                 return snprintf(buf, PAGE_SIZE, "\n");
 971 }
 972
 973 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
 974                 struct device_attribute *attr,
 975                 const char *buf,
 976                 size_t count)
 977 {
 978         struct drm_device *ddev = dev_get_drvdata(dev);
 979         struct amdgpu_device *adev = ddev->dev_private;
 980         int ret;
 981         uint32_t mask = 0;
 982
 983         ret = amdgpu_read_mask(buf, count, &mask);
 984         if (ret)
 985                 return ret;
 986
 987         if (is_support_sw_smu(adev))
 988                 ret = smu_force_clk_levels(&adev->smu, PP_SOCCLK, mask);
 989         else if (adev->powerplay.pp_funcs->force_clock_level)
 990                 ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask);
 991
 992         if (ret)
 993                 return -EINVAL;
 994
 995         return count;
 996 }
 997
 998 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
 999                 struct device_attribute *attr,
1000                 char *buf)
1001 {
1002         struct drm_device *ddev = dev_get_drvdata(dev);
1003         struct amdgpu_device *adev = ddev->dev_private;
1004
1005         if (is_support_sw_smu(adev))
1006                 return smu_print_clk_levels(&adev->smu, PP_FCLK, buf);
1007         else if (adev->powerplay.pp_funcs->print_clock_levels)
1008                 return amdgpu_dpm_print_clock_levels(adev, PP_FCLK, buf);
1009         else
1010                 return snprintf(buf, PAGE_SIZE, "\n");
1011 }
1012
1013 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
1014                 struct device_attribute *attr,
1015                 const char *buf,
1016                 size_t count)
1017 {
1018         struct drm_device *ddev = dev_get_drvdata(dev);
1019         struct amdgpu_device *adev = ddev->dev_private;
1020         int ret;
1021         uint32_t mask = 0;
1022
1023         ret = amdgpu_read_mask(buf, count, &mask);
1024         if (ret)
1025                 return ret;
1026
1027         if (is_support_sw_smu(adev))
1028                 ret = smu_force_clk_levels(&adev->smu, PP_FCLK, mask);
1029         else if (adev->powerplay.pp_funcs->force_clock_level)
1030                 ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask);
1031
1032         if (ret)
1033                 return -EINVAL;
1034
1035         return count;
1036 }
1037
1038 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
1039                 struct device_attribute *attr,
1040                 char *buf)
1041 {
1042         struct drm_device *ddev = dev_get_drvdata(dev);
1043         struct amdgpu_device *adev = ddev->dev_private;
1044
1045         if (is_support_sw_smu(adev))
1046                 return smu_print_clk_levels(&adev->smu, PP_DCEFCLK, buf);
1047         else if (adev->powerplay.pp_funcs->print_clock_levels)
1048                 return amdgpu_dpm_print_clock_levels(adev, PP_DCEFCLK, buf);
1049         else
1050                 return snprintf(buf, PAGE_SIZE, "\n");
1051 }
1052
1053 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
1054                 struct device_attribute *attr,
1055                 const char *buf,
1056                 size_t count)
1057 {
1058         struct drm_device *ddev = dev_get_drvdata(dev);
1059         struct amdgpu_device *adev = ddev->dev_private;
1060         int ret;
1061         uint32_t mask = 0;
1062
1063         ret = amdgpu_read_mask(buf, count, &mask);
1064         if (ret)
1065                 return ret;
1066
1067         if (is_support_sw_smu(adev))
1068                 ret = smu_force_clk_levels(&adev->smu, PP_DCEFCLK, mask);
1069         else if (adev->powerplay.pp_funcs->force_clock_level)
1070                 ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask);
1071
1072         if (ret)
1073                 return -EINVAL;
1074
1075         return count;
1076 }
1077
1078 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
1079                 struct device_attribute *attr,
1080                 char *buf)
1081 {
1082         struct drm_device *ddev = dev_get_drvdata(dev);
1083         struct amdgpu_device *adev = ddev->dev_private;
1084
1085         if (is_support_sw_smu(adev))
1086                 return smu_print_clk_levels(&adev->smu, PP_PCIE, buf);
1087         else if (adev->powerplay.pp_funcs->print_clock_levels)
1088                 return amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
1089         else
1090                 return snprintf(buf, PAGE_SIZE, "\n");
1091 }
1092
1093 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
1094                 struct device_attribute *attr,
1095                 const char *buf,
1096                 size_t count)
1097 {
1098         struct drm_device *ddev = dev_get_drvdata(dev);
1099         struct amdgpu_device *adev = ddev->dev_private;
1100         int ret;
1101         uint32_t mask = 0;
1102
1103         ret = amdgpu_read_mask(buf, count, &mask);
1104         if (ret)
1105                 return ret;
1106
1107         if (is_support_sw_smu(adev))
1108                 ret = smu_force_clk_levels(&adev->smu, PP_PCIE, mask);
1109         else if (adev->powerplay.pp_funcs->force_clock_level)
1110                 ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
1111
1112         if (ret)
1113                 return -EINVAL;
1114
1115         return count;
1116 }
1117
1118 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
1119                 struct device_attribute *attr,
1120                 char *buf)
1121 {
1122         struct drm_device *ddev = dev_get_drvdata(dev);
1123         struct amdgpu_device *adev = ddev->dev_private;
1124         uint32_t value = 0;
1125
1126         if (is_support_sw_smu(adev))
1127                 value = smu_get_od_percentage(&(adev->smu), OD_SCLK);
1128         else if (adev->powerplay.pp_funcs->get_sclk_od)
1129                 value = amdgpu_dpm_get_sclk_od(adev);
1130
1131         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1132 }
1133
1134 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
1135                 struct device_attribute *attr,
1136                 const char *buf,
1137                 size_t count)
1138 {
1139         struct drm_device *ddev = dev_get_drvdata(dev);
1140         struct amdgpu_device *adev = ddev->dev_private;
1141         int ret;
1142         long int value;
1143
1144         ret = kstrtol(buf, 0, &value);
1145
1146         if (ret) {
1147                 count = -EINVAL;
1148                 goto fail;
1149         }
1150
1151         if (is_support_sw_smu(adev)) {
1152                 value = smu_set_od_percentage(&(adev->smu), OD_SCLK, (uint32_t)value);
1153         } else {
1154                 if (adev->powerplay.pp_funcs->set_sclk_od)
1155                         amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
1156
1157                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1158                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1159                 } else {
1160                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1161                         amdgpu_pm_compute_clocks(adev);
1162                 }
1163         }
1164
1165 fail:
1166         return count;
1167 }
1168
1169 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
1170                 struct device_attribute *attr,
1171                 char *buf)
1172 {
1173         struct drm_device *ddev = dev_get_drvdata(dev);
1174         struct amdgpu_device *adev = ddev->dev_private;
1175         uint32_t value = 0;
1176
1177         if (is_support_sw_smu(adev))
1178                 value = smu_get_od_percentage(&(adev->smu), OD_MCLK);
1179         else if (adev->powerplay.pp_funcs->get_mclk_od)
1180                 value = amdgpu_dpm_get_mclk_od(adev);
1181
1182         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1183 }
1184
1185 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
1186                 struct device_attribute *attr,
1187                 const char *buf,
1188                 size_t count)
1189 {
1190         struct drm_device *ddev = dev_get_drvdata(dev);
1191         struct amdgpu_device *adev = ddev->dev_private;
1192         int ret;
1193         long int value;
1194
1195         ret = kstrtol(buf, 0, &value);
1196
1197         if (ret) {
1198                 count = -EINVAL;
1199                 goto fail;
1200         }
1201
1202         if (is_support_sw_smu(adev)) {
1203                 value = smu_set_od_percentage(&(adev->smu), OD_MCLK, (uint32_t)value);
1204         } else {
1205                 if (adev->powerplay.pp_funcs->set_mclk_od)
1206                         amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
1207
1208                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1209                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1210                 } else {
1211                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1212                         amdgpu_pm_compute_clocks(adev);
1213                 }
1214         }
1215
1216 fail:
1217         return count;
1218 }
1219
1220 /**
1221  * DOC: pp_power_profile_mode
1222  *
1223  * The amdgpu driver provides a sysfs API for adjusting the heuristics
1224  * related to switching between power levels in a power state.  The file
1225  * pp_power_profile_mode is used for this.
1226  *
1227  * Reading this file outputs a list of all of the predefined power profiles
1228  * and the relevant heuristics settings for that profile.
1229  *
1230  * To select a profile or create a custom profile, first select manual using
1231  * power_dpm_force_performance_level.  Writing the number of a predefined
1232  * profile to pp_power_profile_mode will enable those heuristics.  To
1233  * create a custom set of heuristics, write a string of numbers to the file
1234  * starting with the number of the custom profile along with a setting
1235  * for each heuristic parameter.  Due to differences across asic families
1236  * the heuristic parameters vary from family to family.
1237  *
1238  */
1239
1240 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
1241                 struct device_attribute *attr,
1242                 char *buf)
1243 {
1244         struct drm_device *ddev = dev_get_drvdata(dev);
1245         struct amdgpu_device *adev = ddev->dev_private;
1246
1247         if (is_support_sw_smu(adev))
1248                 return smu_get_power_profile_mode(&adev->smu, buf);
1249         else if (adev->powerplay.pp_funcs->get_power_profile_mode)
1250                 return amdgpu_dpm_get_power_profile_mode(adev, buf);
1251
1252         return snprintf(buf, PAGE_SIZE, "\n");
1253 }
1254
1255
1256 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
1257                 struct device_attribute *attr,
1258                 const char *buf,
1259                 size_t count)
1260 {
1261         int ret = 0xff;
1262         struct drm_device *ddev = dev_get_drvdata(dev);
1263         struct amdgpu_device *adev = ddev->dev_private;
1264         uint32_t parameter_size = 0;
1265         long parameter[64];
1266         char *sub_str, buf_cpy[128];
1267         char *tmp_str;
1268         uint32_t i = 0;
1269         char tmp[2];
1270         long int profile_mode = 0;
1271         const char delimiter[3] = {' ', '\n', '\0'};
1272
1273         tmp[0] = *(buf);
1274         tmp[1] = '\0';
1275         ret = kstrtol(tmp, 0, &profile_mode);
1276         if (ret)
1277                 goto fail;
1278
1279         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1280                 if (count < 2 || count > 127)
1281                         return -EINVAL;
1282                 while (isspace(*++buf))
1283                         i++;
1284                 memcpy(buf_cpy, buf, count-i);
1285                 tmp_str = buf_cpy;
1286                 while (tmp_str[0]) {
1287                         sub_str = strsep(&tmp_str, delimiter);
1288                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
1289                         if (ret) {
1290                                 count = -EINVAL;
1291                                 goto fail;
1292                         }
1293                         parameter_size++;
1294                         while (isspace(*tmp_str))
1295                                 tmp_str++;
1296                 }
1297         }
1298         parameter[parameter_size] = profile_mode;
1299         if (is_support_sw_smu(adev))
1300                 ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size);
1301         else if (adev->powerplay.pp_funcs->set_power_profile_mode)
1302                 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
1303         if (!ret)
1304                 return count;
1305 fail:
1306         return -EINVAL;
1307 }
1308
1309 /**
1310  * DOC: busy_percent
1311  *
1312  * The amdgpu driver provides a sysfs API for reading how busy the GPU
1313  * is as a percentage.  The file gpu_busy_percent is used for this.
1314  * The SMU firmware computes a percentage of load based on the
1315  * aggregate activity level in the IP cores.
1316  */
1317 static ssize_t amdgpu_get_busy_percent(struct device *dev,
1318                 struct device_attribute *attr,
1319                 char *buf)
1320 {
1321         struct drm_device *ddev = dev_get_drvdata(dev);
1322         struct amdgpu_device *adev = ddev->dev_private;
1323         int r, value, size = sizeof(value);
1324
1325         /* read the IP busy sensor */
1326         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
1327                                    (void *)&value, &size);
1328
1329         if (r)
1330                 return r;
1331
1332         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1333 }
1334
1335 /**
1336  * DOC: mem_busy_percent
1337  *
1338  * The amdgpu driver provides a sysfs API for reading how busy the VRAM
1339  * is as a percentage.  The file mem_busy_percent is used for this.
1340  * The SMU firmware computes a percentage of load based on the
1341  * aggregate activity level in the IP cores.
1342  */
1343 static ssize_t amdgpu_get_memory_busy_percent(struct device *dev,
1344                 struct device_attribute *attr,
1345                 char *buf)
1346 {
1347         struct drm_device *ddev = dev_get_drvdata(dev);
1348         struct amdgpu_device *adev = ddev->dev_private;
1349         int r, value, size = sizeof(value);
1350
1351         /* read the IP busy sensor */
1352         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD,
1353                                    (void *)&value, &size);
1354
1355         if (r)
1356                 return r;
1357
1358         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1359 }
1360
1361 /**
1362  * DOC: pcie_bw
1363  *
1364  * The amdgpu driver provides a sysfs API for estimating how much data
1365  * has been received and sent by the GPU in the last second through PCIe.
1366  * The file pcie_bw is used for this.
1367  * The Perf counters count the number of received and sent messages and return
1368  * those values, as well as the maximum payload size of a PCIe packet (mps).
1369  * Note that it is not possible to easily and quickly obtain the size of each
1370  * packet transmitted, so we output the max payload size (mps) to allow for
1371  * quick estimation of the PCIe bandwidth usage
1372  */
1373 static ssize_t amdgpu_get_pcie_bw(struct device *dev,
1374                 struct device_attribute *attr,
1375                 char *buf)
1376 {
1377         struct drm_device *ddev = dev_get_drvdata(dev);
1378         struct amdgpu_device *adev = ddev->dev_private;
1379         uint64_t count0, count1;
1380
1381         amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
1382         return snprintf(buf, PAGE_SIZE, "%llu %llu %i\n",
1383                         count0, count1, pcie_get_mps(adev->pdev));
1384 }
1385
1386 /**
1387  * DOC: unique_id
1388  *
1389  * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU
1390  * The file unique_id is used for this.
1391  * This will provide a Unique ID that will persist from machine to machine
1392  *
1393  * NOTE: This will only work for GFX9 and newer. This file will be absent
1394  * on unsupported ASICs (GFX8 and older)
1395  */
1396 static ssize_t amdgpu_get_unique_id(struct device *dev,
1397                 struct device_attribute *attr,
1398                 char *buf)
1399 {
1400         struct drm_device *ddev = dev_get_drvdata(dev);
1401         struct amdgpu_device *adev = ddev->dev_private;
1402
1403         if (adev->unique_id)
1404                 return snprintf(buf, PAGE_SIZE, "%016llx\n", adev->unique_id);
1405
1406         return 0;
1407 }
1408
1409 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
1410 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
1411                    amdgpu_get_dpm_forced_performance_level,
1412                    amdgpu_set_dpm_forced_performance_level);
1413 static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
1414 static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
1415 static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
1416                 amdgpu_get_pp_force_state,
1417                 amdgpu_set_pp_force_state);
1418 static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
1419                 amdgpu_get_pp_table,
1420                 amdgpu_set_pp_table);
1421 static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
1422                 amdgpu_get_pp_dpm_sclk,
1423                 amdgpu_set_pp_dpm_sclk);
1424 static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
1425                 amdgpu_get_pp_dpm_mclk,
1426                 amdgpu_set_pp_dpm_mclk);
1427 static DEVICE_ATTR(pp_dpm_socclk, S_IRUGO | S_IWUSR,
1428                 amdgpu_get_pp_dpm_socclk,
1429                 amdgpu_set_pp_dpm_socclk);
1430 static DEVICE_ATTR(pp_dpm_fclk, S_IRUGO | S_IWUSR,
1431                 amdgpu_get_pp_dpm_fclk,
1432                 amdgpu_set_pp_dpm_fclk);
1433 static DEVICE_ATTR(pp_dpm_dcefclk, S_IRUGO | S_IWUSR,
1434                 amdgpu_get_pp_dpm_dcefclk,
1435                 amdgpu_set_pp_dpm_dcefclk);
1436 static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
1437                 amdgpu_get_pp_dpm_pcie,
1438                 amdgpu_set_pp_dpm_pcie);
1439 static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR,
1440                 amdgpu_get_pp_sclk_od,
1441                 amdgpu_set_pp_sclk_od);
1442 static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR,
1443                 amdgpu_get_pp_mclk_od,
1444                 amdgpu_set_pp_mclk_od);
1445 static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
1446                 amdgpu_get_pp_power_profile_mode,
1447                 amdgpu_set_pp_power_profile_mode);
1448 static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
1449                 amdgpu_get_pp_od_clk_voltage,
1450                 amdgpu_set_pp_od_clk_voltage);
1451 static DEVICE_ATTR(gpu_busy_percent, S_IRUGO,
1452                 amdgpu_get_busy_percent, NULL);
1453 static DEVICE_ATTR(mem_busy_percent, S_IRUGO,
1454                 amdgpu_get_memory_busy_percent, NULL);
1455 static DEVICE_ATTR(pcie_bw, S_IRUGO, amdgpu_get_pcie_bw, NULL);
1456 static DEVICE_ATTR(ppfeatures, S_IRUGO | S_IWUSR,
1457                 amdgpu_get_ppfeature_status,
1458                 amdgpu_set_ppfeature_status);
1459 static DEVICE_ATTR(unique_id, S_IRUGO, amdgpu_get_unique_id, NULL);
1460
1461 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
1462                                       struct device_attribute *attr,
1463                                       char *buf)
1464 {
1465         struct amdgpu_device *adev = dev_get_drvdata(dev);
1466         struct drm_device *ddev = adev->ddev;
1467         int channel = to_sensor_dev_attr(attr)->index;
1468         int r, temp, size = sizeof(temp);
1469
1470         /* Can't get temperature when the card is off */
1471         if  ((adev->flags & AMD_IS_PX) &&
1472              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1473                 return -EINVAL;
1474
1475         if (channel >= PP_TEMP_MAX)
1476                 return -EINVAL;
1477
1478         switch (channel) {
1479         case PP_TEMP_JUNCTION:
1480                 /* get current junction temperature */
1481                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
1482                                            (void *)&temp, &size);
1483                 if (r)
1484                         return r;
1485                 break;
1486         case PP_TEMP_EDGE:
1487                 /* get current edge temperature */
1488                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_EDGE_TEMP,
1489                                            (void *)&temp, &size);
1490                 if (r)
1491                         return r;
1492                 break;
1493         case PP_TEMP_MEM:
1494                 /* get current memory temperature */
1495                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_TEMP,
1496                                            (void *)&temp, &size);
1497                 if (r)
1498                         return r;
1499                 break;
1500         }
1501
1502         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1503 }
1504
1505 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
1506                                              struct device_attribute *attr,
1507                                              char *buf)
1508 {
1509         struct amdgpu_device *adev = dev_get_drvdata(dev);
1510         int hyst = to_sensor_dev_attr(attr)->index;
1511         int temp;
1512
1513         if (hyst)
1514                 temp = adev->pm.dpm.thermal.min_temp;
1515         else
1516                 temp = adev->pm.dpm.thermal.max_temp;
1517
1518         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1519 }
1520
1521 static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev,
1522                                              struct device_attribute *attr,
1523                                              char *buf)
1524 {
1525         struct amdgpu_device *adev = dev_get_drvdata(dev);
1526         int hyst = to_sensor_dev_attr(attr)->index;
1527         int temp;
1528
1529         if (hyst)
1530                 temp = adev->pm.dpm.thermal.min_hotspot_temp;
1531         else
1532                 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp;
1533
1534         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1535 }
1536
1537 static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev,
1538                                              struct device_attribute *attr,
1539                                              char *buf)
1540 {
1541         struct amdgpu_device *adev = dev_get_drvdata(dev);
1542         int hyst = to_sensor_dev_attr(attr)->index;
1543         int temp;
1544
1545         if (hyst)
1546                 temp = adev->pm.dpm.thermal.min_mem_temp;
1547         else
1548                 temp = adev->pm.dpm.thermal.max_mem_crit_temp;
1549
1550         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1551 }
1552
1553 static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev,
1554                                              struct device_attribute *attr,
1555                                              char *buf)
1556 {
1557         int channel = to_sensor_dev_attr(attr)->index;
1558
1559         if (channel >= PP_TEMP_MAX)
1560                 return -EINVAL;
1561
1562         return snprintf(buf, PAGE_SIZE, "%s\n", temp_label[channel].label);
1563 }
1564
1565 static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev,
1566                                              struct device_attribute *attr,
1567                                              char *buf)
1568 {
1569         struct amdgpu_device *adev = dev_get_drvdata(dev);
1570         int channel = to_sensor_dev_attr(attr)->index;
1571         int temp = 0;
1572
1573         if (channel >= PP_TEMP_MAX)
1574                 return -EINVAL;
1575
1576         switch (channel) {
1577         case PP_TEMP_JUNCTION:
1578                 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp;
1579                 break;
1580         case PP_TEMP_EDGE:
1581                 temp = adev->pm.dpm.thermal.max_edge_emergency_temp;
1582                 break;
1583         case PP_TEMP_MEM:
1584                 temp = adev->pm.dpm.thermal.max_mem_emergency_temp;
1585                 break;
1586         }
1587
1588         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1589 }
1590
1591 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
1592                                             struct device_attribute *attr,
1593                                             char *buf)
1594 {
1595         struct amdgpu_device *adev = dev_get_drvdata(dev);
1596         u32 pwm_mode = 0;
1597         if (is_support_sw_smu(adev)) {
1598                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1599         } else {
1600                 if (!adev->powerplay.pp_funcs->get_fan_control_mode)
1601                         return -EINVAL;
1602
1603                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1604         }
1605
1606         return sprintf(buf, "%i\n", pwm_mode);
1607 }
1608
1609 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
1610                                             struct device_attribute *attr,
1611                                             const char *buf,
1612                                             size_t count)
1613 {
1614         struct amdgpu_device *adev = dev_get_drvdata(dev);
1615         int err;
1616         int value;
1617
1618         /* Can't adjust fan when the card is off */
1619         if  ((adev->flags & AMD_IS_PX) &&
1620              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1621                 return -EINVAL;
1622
1623         if (is_support_sw_smu(adev)) {
1624                 err = kstrtoint(buf, 10, &value);
1625                 if (err)
1626                         return err;
1627
1628                 smu_set_fan_control_mode(&adev->smu, value);
1629         } else {
1630                 if (!adev->powerplay.pp_funcs->set_fan_control_mode)
1631                         return -EINVAL;
1632
1633                 err = kstrtoint(buf, 10, &value);
1634                 if (err)
1635                         return err;
1636
1637                 amdgpu_dpm_set_fan_control_mode(adev, value);
1638         }
1639
1640         return count;
1641 }
1642
1643 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
1644                                          struct device_attribute *attr,
1645                                          char *buf)
1646 {
1647         return sprintf(buf, "%i\n", 0);
1648 }
1649
1650 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
1651                                          struct device_attribute *attr,
1652                                          char *buf)
1653 {
1654         return sprintf(buf, "%i\n", 255);
1655 }
1656
1657 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
1658                                      struct device_attribute *attr,
1659                                      const char *buf, size_t count)
1660 {
1661         struct amdgpu_device *adev = dev_get_drvdata(dev);
1662         int err;
1663         u32 value;
1664         u32 pwm_mode;
1665
1666         /* Can't adjust fan when the card is off */
1667         if  ((adev->flags & AMD_IS_PX) &&
1668              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1669                 return -EINVAL;
1670         if (is_support_sw_smu(adev))
1671                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1672         else
1673                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1674         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
1675                 pr_info("manual fan speed control should be enabled first\n");
1676                 return -EINVAL;
1677         }
1678
1679         err = kstrtou32(buf, 10, &value);
1680         if (err)
1681                 return err;
1682
1683         value = (value * 100) / 255;
1684
1685         if (is_support_sw_smu(adev)) {
1686                 err = smu_set_fan_speed_percent(&adev->smu, value);
1687                 if (err)
1688                         return err;
1689         } else if (adev->powerplay.pp_funcs->set_fan_speed_percent) {
1690                 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
1691                 if (err)
1692                         return err;
1693         }
1694
1695         return count;
1696 }
1697
1698 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
1699                                      struct device_attribute *attr,
1700                                      char *buf)
1701 {
1702         struct amdgpu_device *adev = dev_get_drvdata(dev);
1703         int err;
1704         u32 speed = 0;
1705
1706         /* Can't adjust fan when the card is off */
1707         if  ((adev->flags & AMD_IS_PX) &&
1708              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1709                 return -EINVAL;
1710
1711         if (is_support_sw_smu(adev)) {
1712                 err = smu_get_fan_speed_percent(&adev->smu, &speed);
1713                 if (err)
1714                         return err;
1715         } else if (adev->powerplay.pp_funcs->get_fan_speed_percent) {
1716                 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
1717                 if (err)
1718                         return err;
1719         }
1720
1721         speed = (speed * 255) / 100;
1722
1723         return sprintf(buf, "%i\n", speed);
1724 }
1725
1726 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
1727                                            struct device_attribute *attr,
1728                                            char *buf)
1729 {
1730         struct amdgpu_device *adev = dev_get_drvdata(dev);
1731         int err;
1732         u32 speed = 0;
1733
1734         /* Can't adjust fan when the card is off */
1735         if  ((adev->flags & AMD_IS_PX) &&
1736              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1737                 return -EINVAL;
1738
1739         if (is_support_sw_smu(adev)) {
1740                 err = smu_get_current_rpm(&adev->smu, &speed);
1741                 if (err)
1742                         return err;
1743         } else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
1744                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
1745                 if (err)
1746                         return err;
1747         }
1748
1749         return sprintf(buf, "%i\n", speed);
1750 }
1751
1752 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
1753                                          struct device_attribute *attr,
1754                                          char *buf)
1755 {
1756         struct amdgpu_device *adev = dev_get_drvdata(dev);
1757         u32 min_rpm = 0;
1758         u32 size = sizeof(min_rpm);
1759         int r;
1760
1761         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
1762                                    (void *)&min_rpm, &size);
1763         if (r)
1764                 return r;
1765
1766         return snprintf(buf, PAGE_SIZE, "%d\n", min_rpm);
1767 }
1768
1769 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
1770                                          struct device_attribute *attr,
1771                                          char *buf)
1772 {
1773         struct amdgpu_device *adev = dev_get_drvdata(dev);
1774         u32 max_rpm = 0;
1775         u32 size = sizeof(max_rpm);
1776         int r;
1777
1778         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
1779                                    (void *)&max_rpm, &size);
1780         if (r)
1781                 return r;
1782
1783         return snprintf(buf, PAGE_SIZE, "%d\n", max_rpm);
1784 }
1785
1786 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
1787                                            struct device_attribute *attr,
1788                                            char *buf)
1789 {
1790         struct amdgpu_device *adev = dev_get_drvdata(dev);
1791         int err;
1792         u32 rpm = 0;
1793
1794         /* Can't adjust fan when the card is off */
1795         if  ((adev->flags & AMD_IS_PX) &&
1796              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1797                 return -EINVAL;
1798
1799         if (is_support_sw_smu(adev)) {
1800                 err = smu_get_current_rpm(&adev->smu, &rpm);
1801                 if (err)
1802                         return err;
1803         } else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
1804                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
1805                 if (err)
1806                         return err;
1807         }
1808
1809         return sprintf(buf, "%i\n", rpm);
1810 }
1811
1812 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
1813                                      struct device_attribute *attr,
1814                                      const char *buf, size_t count)
1815 {
1816         struct amdgpu_device *adev = dev_get_drvdata(dev);
1817         int err;
1818         u32 value;
1819         u32 pwm_mode;
1820
1821         if (is_support_sw_smu(adev))
1822                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1823         else
1824                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1825
1826         if (pwm_mode != AMD_FAN_CTRL_MANUAL)
1827                 return -ENODATA;
1828
1829         /* Can't adjust fan when the card is off */
1830         if  ((adev->flags & AMD_IS_PX) &&
1831              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1832                 return -EINVAL;
1833
1834         err = kstrtou32(buf, 10, &value);
1835         if (err)
1836                 return err;
1837
1838         if (is_support_sw_smu(adev)) {
1839                 err = smu_set_fan_speed_rpm(&adev->smu, value);
1840                 if (err)
1841                         return err;
1842         } else if (adev->powerplay.pp_funcs->set_fan_speed_rpm) {
1843                 err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
1844                 if (err)
1845                         return err;
1846         }
1847
1848         return count;
1849 }
1850
1851 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
1852                                             struct device_attribute *attr,
1853                                             char *buf)
1854 {
1855         struct amdgpu_device *adev = dev_get_drvdata(dev);
1856         u32 pwm_mode = 0;
1857
1858         if (is_support_sw_smu(adev)) {
1859                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1860         } else {
1861                 if (!adev->powerplay.pp_funcs->get_fan_control_mode)
1862                         return -EINVAL;
1863
1864                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1865         }
1866         return sprintf(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
1867 }
1868
1869 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
1870                                             struct device_attribute *attr,
1871                                             const char *buf,
1872                                             size_t count)
1873 {
1874         struct amdgpu_device *adev = dev_get_drvdata(dev);
1875         int err;
1876         int value;
1877         u32 pwm_mode;
1878
1879         /* Can't adjust fan when the card is off */
1880         if  ((adev->flags & AMD_IS_PX) &&
1881              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1882                 return -EINVAL;
1883
1884
1885         err = kstrtoint(buf, 10, &value);
1886         if (err)
1887                 return err;
1888
1889         if (value == 0)
1890                 pwm_mode = AMD_FAN_CTRL_AUTO;
1891         else if (value == 1)
1892                 pwm_mode = AMD_FAN_CTRL_MANUAL;
1893         else
1894                 return -EINVAL;
1895
1896         if (is_support_sw_smu(adev)) {
1897                 smu_set_fan_control_mode(&adev->smu, pwm_mode);
1898         } else {
1899                 if (!adev->powerplay.pp_funcs->set_fan_control_mode)
1900                         return -EINVAL;
1901                 amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
1902         }
1903
1904         return count;
1905 }
1906
1907 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
1908                                         struct device_attribute *attr,
1909                                         char *buf)
1910 {
1911         struct amdgpu_device *adev = dev_get_drvdata(dev);
1912         struct drm_device *ddev = adev->ddev;
1913         u32 vddgfx;
1914         int r, size = sizeof(vddgfx);
1915
1916         /* Can't get voltage when the card is off */
1917         if  ((adev->flags & AMD_IS_PX) &&
1918              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1919                 return -EINVAL;
1920
1921         /* get the voltage */
1922         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
1923                                    (void *)&vddgfx, &size);
1924         if (r)
1925                 return r;
1926
1927         return snprintf(buf, PAGE_SIZE, "%d\n", vddgfx);
1928 }
1929
1930 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
1931                                               struct device_attribute *attr,
1932                                               char *buf)
1933 {
1934         return snprintf(buf, PAGE_SIZE, "vddgfx\n");
1935 }
1936
1937 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
1938                                        struct device_attribute *attr,
1939                                        char *buf)
1940 {
1941         struct amdgpu_device *adev = dev_get_drvdata(dev);
1942         struct drm_device *ddev = adev->ddev;
1943         u32 vddnb;
1944         int r, size = sizeof(vddnb);
1945
1946         /* only APUs have vddnb */
1947         if  (!(adev->flags & AMD_IS_APU))
1948                 return -EINVAL;
1949
1950         /* Can't get voltage when the card is off */
1951         if  ((adev->flags & AMD_IS_PX) &&
1952              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1953                 return -EINVAL;
1954
1955         /* get the voltage */
1956         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
1957                                    (void *)&vddnb, &size);
1958         if (r)
1959                 return r;
1960
1961         return snprintf(buf, PAGE_SIZE, "%d\n", vddnb);
1962 }
1963
1964 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
1965                                               struct device_attribute *attr,
1966                                               char *buf)
1967 {
1968         return snprintf(buf, PAGE_SIZE, "vddnb\n");
1969 }
1970
1971 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
1972                                            struct device_attribute *attr,
1973                                            char *buf)
1974 {
1975         struct amdgpu_device *adev = dev_get_drvdata(dev);
1976         struct drm_device *ddev = adev->ddev;
1977         u32 query = 0;
1978         int r, size = sizeof(u32);
1979         unsigned uw;
1980
1981         /* Can't get power when the card is off */
1982         if  ((adev->flags & AMD_IS_PX) &&
1983              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1984                 return -EINVAL;
1985
1986         /* get the voltage */
1987         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
1988                                    (void *)&query, &size);
1989         if (r)
1990                 return r;
1991
1992         /* convert to microwatts */
1993         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
1994
1995         return snprintf(buf, PAGE_SIZE, "%u\n", uw);
1996 }
1997
1998 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
1999                                          struct device_attribute *attr,
2000                                          char *buf)
2001 {
2002         return sprintf(buf, "%i\n", 0);
2003 }
2004
2005 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
2006                                          struct device_attribute *attr,
2007                                          char *buf)
2008 {
2009         struct amdgpu_device *adev = dev_get_drvdata(dev);
2010         uint32_t limit = 0;
2011
2012         if (is_support_sw_smu(adev)) {
2013                 smu_get_power_limit(&adev->smu, &limit, true);
2014                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2015         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
2016                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
2017                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2018         } else {
2019                 return snprintf(buf, PAGE_SIZE, "\n");
2020         }
2021 }
2022
2023 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
2024                                          struct device_attribute *attr,
2025                                          char *buf)
2026 {
2027         struct amdgpu_device *adev = dev_get_drvdata(dev);
2028         uint32_t limit = 0;
2029
2030         if (is_support_sw_smu(adev)) {
2031                 smu_get_power_limit(&adev->smu, &limit, false);
2032                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2033         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
2034                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
2035                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2036         } else {
2037                 return snprintf(buf, PAGE_SIZE, "\n");
2038         }
2039 }
2040
2041
2042 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
2043                 struct device_attribute *attr,
2044                 const char *buf,
2045                 size_t count)
2046 {
2047         struct amdgpu_device *adev = dev_get_drvdata(dev);
2048         int err;
2049         u32 value;
2050
2051         err = kstrtou32(buf, 10, &value);
2052         if (err)
2053                 return err;
2054
2055         value = value / 1000000; /* convert to Watt */
2056         if (is_support_sw_smu(adev)) {
2057                 adev->smu.funcs->set_power_limit(&adev->smu, value);
2058         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) {
2059                 err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
2060                 if (err)
2061                         return err;
2062         } else {
2063                 return -EINVAL;
2064         }
2065
2066         return count;
2067 }
2068
2069 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
2070                                       struct device_attribute *attr,
2071                                       char *buf)
2072 {
2073         struct amdgpu_device *adev = dev_get_drvdata(dev);
2074         struct drm_device *ddev = adev->ddev;
2075         uint32_t sclk;
2076         int r, size = sizeof(sclk);
2077
2078         /* Can't get voltage when the card is off */
2079         if  ((adev->flags & AMD_IS_PX) &&
2080              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
2081                 return -EINVAL;
2082
2083         /* sanity check PP is enabled */
2084         if (!(adev->powerplay.pp_funcs &&
2085               adev->powerplay.pp_funcs->read_sensor))
2086               return -EINVAL;
2087
2088         /* get the sclk */
2089         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
2090                                    (void *)&sclk, &size);
2091         if (r)
2092                 return r;
2093
2094         return snprintf(buf, PAGE_SIZE, "%d\n", sclk * 10 * 1000);
2095 }
2096
2097 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
2098                                             struct device_attribute *attr,
2099                                             char *buf)
2100 {
2101         return snprintf(buf, PAGE_SIZE, "sclk\n");
2102 }
2103
2104 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
2105                                       struct device_attribute *attr,
2106                                       char *buf)
2107 {
2108         struct amdgpu_device *adev = dev_get_drvdata(dev);
2109         struct drm_device *ddev = adev->ddev;
2110         uint32_t mclk;
2111         int r, size = sizeof(mclk);
2112
2113         /* Can't get voltage when the card is off */
2114         if  ((adev->flags & AMD_IS_PX) &&
2115              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
2116                 return -EINVAL;
2117
2118         /* sanity check PP is enabled */
2119         if (!(adev->powerplay.pp_funcs &&
2120               adev->powerplay.pp_funcs->read_sensor))
2121               return -EINVAL;
2122
2123         /* get the sclk */
2124         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
2125                                    (void *)&mclk, &size);
2126         if (r)
2127                 return r;
2128
2129         return snprintf(buf, PAGE_SIZE, "%d\n", mclk * 10 * 1000);
2130 }
2131
2132 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
2133                                             struct device_attribute *attr,
2134                                             char *buf)
2135 {
2136         return snprintf(buf, PAGE_SIZE, "mclk\n");
2137 }
2138
2139 /**
2140  * DOC: hwmon
2141  *
2142  * The amdgpu driver exposes the following sensor interfaces:
2143  *
2144  * - GPU temperature (via the on-die sensor)
2145  *
2146  * - GPU voltage
2147  *
2148  * - Northbridge voltage (APUs only)
2149  *
2150  * - GPU power
2151  *
2152  * - GPU fan
2153  *
2154  * - GPU gfx/compute engine clock
2155  *
2156  * - GPU memory clock (dGPU only)
2157  *
2158  * hwmon interfaces for GPU temperature:
2159  *
2160  * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius
2161  *   - temp2_input and temp3_input are supported on SOC15 dGPUs only
2162  *
2163  * - temp[1-3]_label: temperature channel label
2164  *   - temp2_label and temp3_label are supported on SOC15 dGPUs only
2165  *
2166  * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
2167  *   - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
2168  *
2169  * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
2170  *   - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
2171  *
2172  * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius
2173  *   - these are supported on SOC15 dGPUs only
2174  *
2175  * hwmon interfaces for GPU voltage:
2176  *
2177  * - in0_input: the voltage on the GPU in millivolts
2178  *
2179  * - in1_input: the voltage on the Northbridge in millivolts
2180  *
2181  * hwmon interfaces for GPU power:
2182  *
2183  * - power1_average: average power used by the GPU in microWatts
2184  *
2185  * - power1_cap_min: minimum cap supported in microWatts
2186  *
2187  * - power1_cap_max: maximum cap supported in microWatts
2188  *
2189  * - power1_cap: selected power cap in microWatts
2190  *
2191  * hwmon interfaces for GPU fan:
2192  *
2193  * - pwm1: pulse width modulation fan level (0-255)
2194  *
2195  * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
2196  *
2197  * - pwm1_min: pulse width modulation fan control minimum level (0)
2198  *
2199  * - pwm1_max: pulse width modulation fan control maximum level (255)
2200  *
2201  * - fan1_min: an minimum value Unit: revolution/min (RPM)
2202  *
2203  * - fan1_max: an maxmum value Unit: revolution/max (RPM)
2204  *
2205  * - fan1_input: fan speed in RPM
2206  *
2207  * - fan[1-*]_target: Desired fan speed Unit: revolution/min (RPM)
2208  *
2209  * - fan[1-*]_enable: Enable or disable the sensors.1: Enable 0: Disable
2210  *
2211  * hwmon interfaces for GPU clocks:
2212  *
2213  * - freq1_input: the gfx/compute clock in hertz
2214  *
2215  * - freq2_input: the memory clock in hertz
2216  *
2217  * You can use hwmon tools like sensors to view this information on your system.
2218  *
2219  */
2220
2221 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE);
2222 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
2223 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
2224 static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE);
2225 static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION);
2226 static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0);
2227 static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1);
2228 static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION);
2229 static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM);
2230 static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0);
2231 static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1);
2232 static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM);
2233 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE);
2234 static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION);
2235 static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM);
2236 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
2237 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
2238 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
2239 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
2240 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
2241 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
2242 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
2243 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
2244 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
2245 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
2246 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
2247 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
2248 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
2249 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
2250 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
2251 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
2252 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
2253 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
2254 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
2255 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
2256 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
2257
2258 static struct attribute *hwmon_attributes[] = {
2259         &sensor_dev_attr_temp1_input.dev_attr.attr,
2260         &sensor_dev_attr_temp1_crit.dev_attr.attr,
2261         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
2262         &sensor_dev_attr_temp2_input.dev_attr.attr,
2263         &sensor_dev_attr_temp2_crit.dev_attr.attr,
2264         &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr,
2265         &sensor_dev_attr_temp3_input.dev_attr.attr,
2266         &sensor_dev_attr_temp3_crit.dev_attr.attr,
2267         &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr,
2268         &sensor_dev_attr_temp1_emergency.dev_attr.attr,
2269         &sensor_dev_attr_temp2_emergency.dev_attr.attr,
2270         &sensor_dev_attr_temp3_emergency.dev_attr.attr,
2271         &sensor_dev_attr_temp1_label.dev_attr.attr,
2272         &sensor_dev_attr_temp2_label.dev_attr.attr,
2273         &sensor_dev_attr_temp3_label.dev_attr.attr,
2274         &sensor_dev_attr_pwm1.dev_attr.attr,
2275         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2276         &sensor_dev_attr_pwm1_min.dev_attr.attr,
2277         &sensor_dev_attr_pwm1_max.dev_attr.attr,
2278         &sensor_dev_attr_fan1_input.dev_attr.attr,
2279         &sensor_dev_attr_fan1_min.dev_attr.attr,
2280         &sensor_dev_attr_fan1_max.dev_attr.attr,
2281         &sensor_dev_attr_fan1_target.dev_attr.attr,
2282         &sensor_dev_attr_fan1_enable.dev_attr.attr,
2283         &sensor_dev_attr_in0_input.dev_attr.attr,
2284         &sensor_dev_attr_in0_label.dev_attr.attr,
2285         &sensor_dev_attr_in1_input.dev_attr.attr,
2286         &sensor_dev_attr_in1_label.dev_attr.attr,
2287         &sensor_dev_attr_power1_average.dev_attr.attr,
2288         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
2289         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
2290         &sensor_dev_attr_power1_cap.dev_attr.attr,
2291         &sensor_dev_attr_freq1_input.dev_attr.attr,
2292         &sensor_dev_attr_freq1_label.dev_attr.attr,
2293         &sensor_dev_attr_freq2_input.dev_attr.attr,
2294         &sensor_dev_attr_freq2_label.dev_attr.attr,
2295         NULL
2296 };
2297
2298 static umode_t hwmon_attributes_visible(struct kobject *kobj,
2299                                         struct attribute *attr, int index)
2300 {
2301         struct device *dev = kobj_to_dev(kobj);
2302         struct amdgpu_device *adev = dev_get_drvdata(dev);
2303         umode_t effective_mode = attr->mode;
2304
2305         /* Skip fan attributes if fan is not present */
2306         if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2307             attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2308             attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2309             attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2310             attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2311             attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2312             attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2313             attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2314             attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2315                 return 0;
2316
2317         /* Skip fan attributes on APU */
2318         if ((adev->flags & AMD_IS_APU) &&
2319             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2320              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2321              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2322              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2323              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2324              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2325              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2326              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2327              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2328                 return 0;
2329
2330         /* Skip limit attributes if DPM is not enabled */
2331         if (!adev->pm.dpm_enabled &&
2332             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
2333              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
2334              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2335              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2336              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2337              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2338              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2339              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2340              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2341              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2342              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2343                 return 0;
2344
2345         if (!is_support_sw_smu(adev)) {
2346                 /* mask fan attributes if we have no bindings for this asic to expose */
2347                 if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
2348                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
2349                     (!adev->powerplay.pp_funcs->get_fan_control_mode &&
2350                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
2351                         effective_mode &= ~S_IRUGO;
2352
2353                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
2354                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
2355                     (!adev->powerplay.pp_funcs->set_fan_control_mode &&
2356                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
2357                         effective_mode &= ~S_IWUSR;
2358         }
2359
2360         if ((adev->flags & AMD_IS_APU) &&
2361             (attr == &sensor_dev_attr_power1_average.dev_attr.attr ||
2362              attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
2363              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
2364              attr == &sensor_dev_attr_power1_cap.dev_attr.attr))
2365                 return 0;
2366
2367         if (!is_support_sw_smu(adev)) {
2368                 /* hide max/min values if we can't both query and manage the fan */
2369                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
2370                      !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
2371                      (!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
2372                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
2373                     (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2374                      attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
2375                         return 0;
2376
2377                 if ((!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
2378                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
2379                     (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2380                      attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
2381                         return 0;
2382         }
2383
2384         /* only APUs have vddnb */
2385         if (!(adev->flags & AMD_IS_APU) &&
2386             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
2387              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
2388                 return 0;
2389
2390         /* no mclk on APUs */
2391         if ((adev->flags & AMD_IS_APU) &&
2392             (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
2393              attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
2394                 return 0;
2395
2396         /* only SOC15 dGPUs support hotspot and mem temperatures */
2397         if (((adev->flags & AMD_IS_APU) ||
2398              adev->asic_type < CHIP_VEGA10) &&
2399             (attr == &sensor_dev_attr_temp2_crit.dev_attr.attr ||
2400              attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr ||
2401              attr == &sensor_dev_attr_temp3_crit.dev_attr.attr ||
2402              attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr ||
2403              attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
2404              attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
2405              attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr ||
2406              attr == &sensor_dev_attr_temp2_input.dev_attr.attr ||
2407              attr == &sensor_dev_attr_temp3_input.dev_attr.attr ||
2408              attr == &sensor_dev_attr_temp2_label.dev_attr.attr ||
2409              attr == &sensor_dev_attr_temp3_label.dev_attr.attr))
2410                 return 0;
2411
2412         return effective_mode;
2413 }
2414
2415 static const struct attribute_group hwmon_attrgroup = {
2416         .attrs = hwmon_attributes,
2417         .is_visible = hwmon_attributes_visible,
2418 };
2419
2420 static const struct attribute_group *hwmon_groups[] = {
2421         &hwmon_attrgroup,
2422         NULL
2423 };
2424
2425 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
2426 {
2427         struct amdgpu_device *adev =
2428                 container_of(work, struct amdgpu_device,
2429                              pm.dpm.thermal.work);
2430         /* switch to the thermal state */
2431         enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
2432         int temp, size = sizeof(temp);
2433
2434         if (!adev->pm.dpm_enabled)
2435                 return;
2436
2437         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
2438                                     (void *)&temp, &size)) {
2439                 if (temp < adev->pm.dpm.thermal.min_temp)
2440                         /* switch back the user state */
2441                         dpm_state = adev->pm.dpm.user_state;
2442         } else {
2443                 if (adev->pm.dpm.thermal.high_to_low)
2444                         /* switch back the user state */
2445                         dpm_state = adev->pm.dpm.user_state;
2446         }
2447         mutex_lock(&adev->pm.mutex);
2448         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
2449                 adev->pm.dpm.thermal_active = true;
2450         else
2451                 adev->pm.dpm.thermal_active = false;
2452         adev->pm.dpm.state = dpm_state;
2453         mutex_unlock(&adev->pm.mutex);
2454
2455         amdgpu_pm_compute_clocks(adev);
2456 }
2457
2458 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
2459                                                      enum amd_pm_state_type dpm_state)
2460 {
2461         int i;
2462         struct amdgpu_ps *ps;
2463         u32 ui_class;
2464         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
2465                 true : false;
2466
2467         /* check if the vblank period is too short to adjust the mclk */
2468         if (single_display && adev->powerplay.pp_funcs->vblank_too_short) {
2469                 if (amdgpu_dpm_vblank_too_short(adev))
2470                         single_display = false;
2471         }
2472
2473         /* certain older asics have a separare 3D performance state,
2474          * so try that first if the user selected performance
2475          */
2476         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
2477                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
2478         /* balanced states don't exist at the moment */
2479         if (dpm_state == POWER_STATE_TYPE_BALANCED)
2480                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2481
2482 restart_search:
2483         /* Pick the best power state based on current conditions */
2484         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
2485                 ps = &adev->pm.dpm.ps[i];
2486                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
2487                 switch (dpm_state) {
2488                 /* user states */
2489                 case POWER_STATE_TYPE_BATTERY:
2490                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
2491                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
2492                                         if (single_display)
2493                                                 return ps;
2494                                 } else
2495                                         return ps;
2496                         }
2497                         break;
2498                 case POWER_STATE_TYPE_BALANCED:
2499                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
2500                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
2501                                         if (single_display)
2502                                                 return ps;
2503                                 } else
2504                                         return ps;
2505                         }
2506                         break;
2507                 case POWER_STATE_TYPE_PERFORMANCE:
2508                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
2509                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
2510                                         if (single_display)
2511                                                 return ps;
2512                                 } else
2513                                         return ps;
2514                         }
2515                         break;
2516                 /* internal states */
2517                 case POWER_STATE_TYPE_INTERNAL_UVD:
2518                         if (adev->pm.dpm.uvd_ps)
2519                                 return adev->pm.dpm.uvd_ps;
2520                         else
2521                                 break;
2522                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
2523                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
2524                                 return ps;
2525                         break;
2526                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
2527                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
2528                                 return ps;
2529                         break;
2530                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
2531                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
2532                                 return ps;
2533                         break;
2534                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
2535                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
2536                                 return ps;
2537                         break;
2538                 case POWER_STATE_TYPE_INTERNAL_BOOT:
2539                         return adev->pm.dpm.boot_ps;
2540                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
2541                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
2542                                 return ps;
2543                         break;
2544                 case POWER_STATE_TYPE_INTERNAL_ACPI:
2545                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
2546                                 return ps;
2547                         break;
2548                 case POWER_STATE_TYPE_INTERNAL_ULV:
2549                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
2550                                 return ps;
2551                         break;
2552                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
2553                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2554                                 return ps;
2555                         break;
2556                 default:
2557                         break;
2558                 }
2559         }
2560         /* use a fallback state if we didn't match */
2561         switch (dpm_state) {
2562         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
2563                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
2564                 goto restart_search;
2565         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
2566         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
2567         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
2568                 if (adev->pm.dpm.uvd_ps) {
2569                         return adev->pm.dpm.uvd_ps;
2570                 } else {
2571                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2572                         goto restart_search;
2573                 }
2574         case POWER_STATE_TYPE_INTERNAL_THERMAL:
2575                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
2576                 goto restart_search;
2577         case POWER_STATE_TYPE_INTERNAL_ACPI:
2578                 dpm_state = POWER_STATE_TYPE_BATTERY;
2579                 goto restart_search;
2580         case POWER_STATE_TYPE_BATTERY:
2581         case POWER_STATE_TYPE_BALANCED:
2582         case POWER_STATE_TYPE_INTERNAL_3DPERF:
2583                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2584                 goto restart_search;
2585         default:
2586                 break;
2587         }
2588
2589         return NULL;
2590 }
2591
2592 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
2593 {
2594         struct amdgpu_ps *ps;
2595         enum amd_pm_state_type dpm_state;
2596         int ret;
2597         bool equal = false;
2598
2599         /* if dpm init failed */
2600         if (!adev->pm.dpm_enabled)
2601                 return;
2602
2603         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
2604                 /* add other state override checks here */
2605                 if ((!adev->pm.dpm.thermal_active) &&
2606                     (!adev->pm.dpm.uvd_active))
2607                         adev->pm.dpm.state = adev->pm.dpm.user_state;
2608         }
2609         dpm_state = adev->pm.dpm.state;
2610
2611         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
2612         if (ps)
2613                 adev->pm.dpm.requested_ps = ps;
2614         else
2615                 return;
2616
2617         if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) {
2618                 printk("switching from power state:\n");
2619                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
2620                 printk("switching to power state:\n");
2621                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
2622         }
2623
2624         /* update whether vce is active */
2625         ps->vce_active = adev->pm.dpm.vce_active;
2626         if (adev->powerplay.pp_funcs->display_configuration_changed)
2627                 amdgpu_dpm_display_configuration_changed(adev);
2628
2629         ret = amdgpu_dpm_pre_set_power_state(adev);
2630         if (ret)
2631                 return;
2632
2633         if (adev->powerplay.pp_funcs->check_state_equal) {
2634                 if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
2635                         equal = false;
2636         }
2637
2638         if (equal)
2639                 return;
2640
2641         amdgpu_dpm_set_power_state(adev);
2642         amdgpu_dpm_post_set_power_state(adev);
2643
2644         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
2645         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
2646
2647         if (adev->powerplay.pp_funcs->force_performance_level) {
2648                 if (adev->pm.dpm.thermal_active) {
2649                         enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
2650                         /* force low perf level for thermal */
2651                         amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
2652                         /* save the user's level */
2653                         adev->pm.dpm.forced_level = level;
2654                 } else {
2655                         /* otherwise, user selected level */
2656                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
2657                 }
2658         }
2659 }
2660
2661 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
2662 {
2663         int ret = 0;
2664         if (is_support_sw_smu(adev)) {
2665             ret = smu_dpm_set_power_gate(&adev->smu, AMD_IP_BLOCK_TYPE_UVD, enable);
2666             if (ret)
2667                 DRM_ERROR("[SW SMU]: dpm enable uvd failed, state = %s, ret = %d. \n",
2668                           enable ? "true" : "false", ret);
2669         } else if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
2670                 /* enable/disable UVD */
2671                 mutex_lock(&adev->pm.mutex);
2672                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
2673                 mutex_unlock(&adev->pm.mutex);
2674         }
2675         /* enable/disable Low Memory PState for UVD (4k videos) */
2676         if (adev->asic_type == CHIP_STONEY &&
2677                 adev->uvd.decode_image_width >= WIDTH_4K) {
2678                 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2679
2680                 if (hwmgr && hwmgr->hwmgr_func &&
2681                     hwmgr->hwmgr_func->update_nbdpm_pstate)
2682                         hwmgr->hwmgr_func->update_nbdpm_pstate(hwmgr,
2683                                                                !enable,
2684                                                                true);
2685         }
2686 }
2687
2688 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
2689 {
2690         int ret = 0;
2691         if (is_support_sw_smu(adev)) {
2692             ret = smu_dpm_set_power_gate(&adev->smu, AMD_IP_BLOCK_TYPE_VCE, enable);
2693             if (ret)
2694                 DRM_ERROR("[SW SMU]: dpm enable vce failed, state = %s, ret = %d. \n",
2695                           enable ? "true" : "false", ret);
2696         } else if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
2697                 /* enable/disable VCE */
2698                 mutex_lock(&adev->pm.mutex);
2699                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
2700                 mutex_unlock(&adev->pm.mutex);
2701         }
2702 }
2703
2704 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
2705 {
2706         int i;
2707
2708         if (adev->powerplay.pp_funcs->print_power_state == NULL)
2709                 return;
2710
2711         for (i = 0; i < adev->pm.dpm.num_ps; i++)
2712                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
2713
2714 }
2715
2716 int amdgpu_pm_virt_sysfs_init(struct amdgpu_device *adev)
2717 {
2718         int ret = 0;
2719
2720         if (!(amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev)))
2721                 return ret;
2722
2723         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
2724         if (ret) {
2725                 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
2726                 return ret;
2727         }
2728
2729         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
2730         if (ret) {
2731                 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
2732                 return ret;
2733         }
2734
2735         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
2736         if (ret) {
2737                 DRM_ERROR("failed to create device file for dpm state\n");
2738                 return ret;
2739         }
2740
2741         return ret;
2742 }
2743
2744 void amdgpu_pm_virt_sysfs_fini(struct amdgpu_device *adev)
2745 {
2746         if (!(amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev)))
2747                 return;
2748
2749         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
2750         device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
2751         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
2752 }
2753
2754 int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version)
2755 {
2756         int r;
2757
2758
2759         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->load_firmware) {
2760                 r = adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
2761                 if (r) {
2762                         pr_err("smu firmware loading failed\n");
2763                         return r;
2764                 }
2765                 *smu_version = adev->pm.fw_version;
2766         }
2767         return 0;
2768 }
2769
2770 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
2771 {
2772         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2773         int ret;
2774
2775         if (adev->pm.sysfs_initialized)
2776                 return 0;
2777
2778         if (adev->pm.dpm_enabled == 0)
2779                 return 0;
2780
2781         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
2782                                                                    DRIVER_NAME, adev,
2783                                                                    hwmon_groups);
2784         if (IS_ERR(adev->pm.int_hwmon_dev)) {
2785                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
2786                 dev_err(adev->dev,
2787                         "Unable to register hwmon device: %d\n", ret);
2788                 return ret;
2789         }
2790
2791         ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
2792         if (ret) {
2793                 DRM_ERROR("failed to create device file for dpm state\n");
2794                 return ret;
2795         }
2796         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
2797         if (ret) {
2798                 DRM_ERROR("failed to create device file for dpm state\n");
2799                 return ret;
2800         }
2801
2802
2803         ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
2804         if (ret) {
2805                 DRM_ERROR("failed to create device file pp_num_states\n");
2806                 return ret;
2807         }
2808         ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
2809         if (ret) {
2810                 DRM_ERROR("failed to create device file pp_cur_state\n");
2811                 return ret;
2812         }
2813         ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
2814         if (ret) {
2815                 DRM_ERROR("failed to create device file pp_force_state\n");
2816                 return ret;
2817         }
2818         ret = device_create_file(adev->dev, &dev_attr_pp_table);
2819         if (ret) {
2820                 DRM_ERROR("failed to create device file pp_table\n");
2821                 return ret;
2822         }
2823
2824         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
2825         if (ret) {
2826                 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
2827                 return ret;
2828         }
2829         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
2830         if (ret) {
2831                 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
2832                 return ret;
2833         }
2834         if (adev->asic_type >= CHIP_VEGA10) {
2835                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_socclk);
2836                 if (ret) {
2837                         DRM_ERROR("failed to create device file pp_dpm_socclk\n");
2838                         return ret;
2839                 }
2840                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
2841                 if (ret) {
2842                         DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");
2843                         return ret;
2844                 }
2845         }
2846         if (adev->asic_type >= CHIP_VEGA20) {
2847                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_fclk);
2848                 if (ret) {
2849                         DRM_ERROR("failed to create device file pp_dpm_fclk\n");
2850                         return ret;
2851                 }
2852         }
2853         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
2854         if (ret) {
2855                 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
2856                 return ret;
2857         }
2858         ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
2859         if (ret) {
2860                 DRM_ERROR("failed to create device file pp_sclk_od\n");
2861                 return ret;
2862         }
2863         ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od);
2864         if (ret) {
2865                 DRM_ERROR("failed to create device file pp_mclk_od\n");
2866                 return ret;
2867         }
2868         ret = device_create_file(adev->dev,
2869                         &dev_attr_pp_power_profile_mode);
2870         if (ret) {
2871                 DRM_ERROR("failed to create device file "
2872                                 "pp_power_profile_mode\n");
2873                 return ret;
2874         }
2875         if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
2876             (!is_support_sw_smu(adev) && hwmgr->od_enabled)) {
2877                 ret = device_create_file(adev->dev,
2878                                 &dev_attr_pp_od_clk_voltage);
2879                 if (ret) {
2880                         DRM_ERROR("failed to create device file "
2881                                         "pp_od_clk_voltage\n");
2882                         return ret;
2883                 }
2884         }
2885         ret = device_create_file(adev->dev,
2886                         &dev_attr_gpu_busy_percent);
2887         if (ret) {
2888                 DRM_ERROR("failed to create device file "
2889                                 "gpu_busy_level\n");
2890                 return ret;
2891         }
2892         /* APU does not have its own dedicated memory */
2893         if (!(adev->flags & AMD_IS_APU)) {
2894                 ret = device_create_file(adev->dev,
2895                                 &dev_attr_mem_busy_percent);
2896                 if (ret) {
2897                         DRM_ERROR("failed to create device file "
2898                                         "mem_busy_percent\n");
2899                         return ret;
2900                 }
2901         }
2902         /* PCIe Perf counters won't work on APU nodes */
2903         if (!(adev->flags & AMD_IS_APU)) {
2904                 ret = device_create_file(adev->dev, &dev_attr_pcie_bw);
2905                 if (ret) {
2906                         DRM_ERROR("failed to create device file pcie_bw\n");
2907                         return ret;
2908                 }
2909         }
2910         if (adev->unique_id)
2911                 ret = device_create_file(adev->dev, &dev_attr_unique_id);
2912         if (ret) {
2913                 DRM_ERROR("failed to create device file unique_id\n");
2914                 return ret;
2915         }
2916         ret = amdgpu_debugfs_pm_init(adev);
2917         if (ret) {
2918                 DRM_ERROR("Failed to register debugfs file for dpm!\n");
2919                 return ret;
2920         }
2921
2922         if ((adev->asic_type >= CHIP_VEGA10) &&
2923             !(adev->flags & AMD_IS_APU)) {
2924                 ret = device_create_file(adev->dev,
2925                                 &dev_attr_ppfeatures);
2926                 if (ret) {
2927                         DRM_ERROR("failed to create device file "
2928                                         "ppfeatures\n");
2929                         return ret;
2930                 }
2931         }
2932
2933         adev->pm.sysfs_initialized = true;
2934
2935         return 0;
2936 }
2937
2938 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
2939 {
2940         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2941
2942         if (adev->pm.dpm_enabled == 0)
2943                 return;
2944
2945         if (adev->pm.int_hwmon_dev)
2946                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
2947         device_remove_file(adev->dev, &dev_attr_power_dpm_state);
2948         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
2949
2950         device_remove_file(adev->dev, &dev_attr_pp_num_states);
2951         device_remove_file(adev->dev, &dev_attr_pp_cur_state);
2952         device_remove_file(adev->dev, &dev_attr_pp_force_state);
2953         device_remove_file(adev->dev, &dev_attr_pp_table);
2954
2955         device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
2956         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
2957         if (adev->asic_type >= CHIP_VEGA10) {
2958                 device_remove_file(adev->dev, &dev_attr_pp_dpm_socclk);
2959                 device_remove_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
2960         }
2961         device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
2962         if (adev->asic_type >= CHIP_VEGA20)
2963                 device_remove_file(adev->dev, &dev_attr_pp_dpm_fclk);
2964         device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
2965         device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
2966         device_remove_file(adev->dev,
2967                         &dev_attr_pp_power_profile_mode);
2968         if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
2969             (!is_support_sw_smu(adev) && hwmgr->od_enabled))
2970                 device_remove_file(adev->dev,
2971                                 &dev_attr_pp_od_clk_voltage);
2972         device_remove_file(adev->dev, &dev_attr_gpu_busy_percent);
2973         if (!(adev->flags & AMD_IS_APU))
2974                 device_remove_file(adev->dev, &dev_attr_mem_busy_percent);
2975         if (!(adev->flags & AMD_IS_APU))
2976                 device_remove_file(adev->dev, &dev_attr_pcie_bw);
2977         if (adev->unique_id)
2978                 device_remove_file(adev->dev, &dev_attr_unique_id);
2979         if ((adev->asic_type >= CHIP_VEGA10) &&
2980             !(adev->flags & AMD_IS_APU))
2981                 device_remove_file(adev->dev, &dev_attr_ppfeatures);
2982 }
2983
2984 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
2985 {
2986         int i = 0;
2987
2988         if (!adev->pm.dpm_enabled)
2989                 return;
2990
2991         if (adev->mode_info.num_crtc)
2992                 amdgpu_display_bandwidth_update(adev);
2993
2994         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
2995                 struct amdgpu_ring *ring = adev->rings[i];
2996                 if (ring && ring->sched.ready)
2997                         amdgpu_fence_wait_empty(ring);
2998         }
2999
3000         if (is_support_sw_smu(adev)) {
3001                 struct smu_context *smu = &adev->smu;
3002                 struct smu_dpm_context *smu_dpm = &adev->smu.smu_dpm;
3003                 mutex_lock(&(smu->mutex));
3004                 smu_handle_task(&adev->smu,
3005                                 smu_dpm->dpm_level,
3006                                 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE);
3007                 mutex_unlock(&(smu->mutex));
3008         } else {
3009                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
3010                         if (!amdgpu_device_has_dc_support(adev)) {
3011                                 mutex_lock(&adev->pm.mutex);
3012                                 amdgpu_dpm_get_active_displays(adev);
3013                                 adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count;
3014                                 adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
3015                                 adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
3016                                 /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
3017                                 if (adev->pm.pm_display_cfg.vrefresh > 120)
3018                                         adev->pm.pm_display_cfg.min_vblank_time = 0;
3019                                 if (adev->powerplay.pp_funcs->display_configuration_change)
3020                                         adev->powerplay.pp_funcs->display_configuration_change(
3021                                                                         adev->powerplay.pp_handle,
3022                                                                         &adev->pm.pm_display_cfg);
3023                                 mutex_unlock(&adev->pm.mutex);
3024                         }
3025                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
3026                 } else {
3027                         mutex_lock(&adev->pm.mutex);
3028                         amdgpu_dpm_get_active_displays(adev);
3029                         amdgpu_dpm_change_power_state_locked(adev);
3030                         mutex_unlock(&adev->pm.mutex);
3031                 }
3032         }
3033 }
3034
3035 /*
3036  * Debugfs info
3037  */
3038 #if defined(CONFIG_DEBUG_FS)
3039
3040 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
3041 {
3042         uint32_t value;
3043         uint64_t value64;
3044         uint32_t query = 0;
3045         int size;
3046
3047         /* GPU Clocks */
3048         size = sizeof(value);
3049         seq_printf(m, "GFX Clocks and Power:\n");
3050         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
3051                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
3052         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
3053                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
3054         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
3055                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
3056         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
3057                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
3058         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
3059                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
3060         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
3061                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
3062         size = sizeof(uint32_t);
3063         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
3064                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
3065         size = sizeof(value);
3066         seq_printf(m, "\n");
3067
3068         /* GPU Temp */
3069         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
3070                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
3071
3072         /* GPU Load */
3073         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
3074                 seq_printf(m, "GPU Load: %u %%\n", value);
3075         /* MEM Load */
3076         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size))
3077                 seq_printf(m, "MEM Load: %u %%\n", value);
3078
3079         seq_printf(m, "\n");
3080
3081         /* SMC feature mask */
3082         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
3083                 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
3084
3085         /* UVD clocks */
3086         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
3087                 if (!value) {
3088                         seq_printf(m, "UVD: Disabled\n");
3089                 } else {
3090                         seq_printf(m, "UVD: Enabled\n");
3091                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3092                                 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3093                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3094                                 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3095                 }
3096         }
3097         seq_printf(m, "\n");
3098
3099         /* VCE clocks */
3100         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
3101                 if (!value) {
3102                         seq_printf(m, "VCE: Disabled\n");
3103                 } else {
3104                         seq_printf(m, "VCE: Enabled\n");
3105                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
3106                                 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
3107                 }
3108         }
3109
3110         return 0;
3111 }
3112
3113 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
3114 {
3115         int i;
3116
3117         for (i = 0; clocks[i].flag; i++)
3118                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
3119                            (flags & clocks[i].flag) ? "On" : "Off");
3120 }
3121
3122 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
3123 {
3124         struct drm_info_node *node = (struct drm_info_node *) m->private;
3125         struct drm_device *dev = node->minor->dev;
3126         struct amdgpu_device *adev = dev->dev_private;
3127         struct drm_device *ddev = adev->ddev;
3128         u32 flags = 0;
3129
3130         amdgpu_device_ip_get_clockgating_state(adev, &flags);
3131         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
3132         amdgpu_parse_cg_state(m, flags);
3133         seq_printf(m, "\n");
3134
3135         if (!adev->pm.dpm_enabled) {
3136                 seq_printf(m, "dpm not enabled\n");
3137                 return 0;
3138         }
3139         if  ((adev->flags & AMD_IS_PX) &&
3140              (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
3141                 seq_printf(m, "PX asic powered off\n");
3142         } else if (!is_support_sw_smu(adev) && adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
3143                 mutex_lock(&adev->pm.mutex);
3144                 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
3145                         adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
3146                 else
3147                         seq_printf(m, "Debugfs support not implemented for this asic\n");
3148                 mutex_unlock(&adev->pm.mutex);
3149         } else {
3150                 return amdgpu_debugfs_pm_info_pp(m, adev);
3151         }
3152
3153         return 0;
3154 }
3155
3156 static const struct drm_info_list amdgpu_pm_info_list[] = {
3157         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
3158 };
3159 #endif
3160
3161 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
3162 {
3163 #if defined(CONFIG_DEBUG_FS)
3164         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
3165 #else
3166         return 0;
3167 #endif
3168 }