drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef __AMDGPU_GFX_H__
  25 #define __AMDGPU_GFX_H__
  26
  27 /*
  28  * GFX stuff
  29  */
  30 #include "clearstate_defs.h"
  31 #include "amdgpu_ring.h"
  32 #include "amdgpu_rlc.h"
  33
  34 /* GFX current status */
  35 #define AMDGPU_GFX_NORMAL_MODE                  0x00000000L
  36 #define AMDGPU_GFX_SAFE_MODE                    0x00000001L
  37 #define AMDGPU_GFX_PG_DISABLED_MODE             0x00000002L
  38 #define AMDGPU_GFX_CG_DISABLED_MODE             0x00000004L
  39 #define AMDGPU_GFX_LBPW_DISABLED_MODE           0x00000008L
  40
  41 #define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES
  42 #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
  43
  44 struct amdgpu_mec {
  45         struct amdgpu_bo        *hpd_eop_obj;
  46         u64                     hpd_eop_gpu_addr;
  47         struct amdgpu_bo        *mec_fw_obj;
  48         u64                     mec_fw_gpu_addr;
  49         u32 num_mec;
  50         u32 num_pipe_per_mec;
  51         u32 num_queue_per_pipe;
  52         void                    *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
  53
  54         /* These are the resources for which amdgpu takes ownership */
  55         DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
  56 };
  57
  58 struct amdgpu_kiq {
  59         u64                     eop_gpu_addr;
  60         struct amdgpu_bo        *eop_obj;
  61         spinlock_t              ring_lock;
  62         struct amdgpu_ring      ring;
  63         struct amdgpu_irq_src   irq;
  64 };
  65
  66 /*
  67  * GPU scratch registers structures, functions & helpers
  68  */
  69 struct amdgpu_scratch {
  70         unsigned                num_reg;
  71         uint32_t                reg_base;
  72         uint32_t                free_mask;
  73 };
  74
  75 /*
  76  * GFX configurations
  77  */
  78 #define AMDGPU_GFX_MAX_SE 4
  79 #define AMDGPU_GFX_MAX_SH_PER_SE 2
  80
  81 struct amdgpu_rb_config {
  82         uint32_t rb_backend_disable;
  83         uint32_t user_rb_backend_disable;
  84         uint32_t raster_config;
  85         uint32_t raster_config_1;
  86 };
  87
  88 struct gb_addr_config {
  89         uint16_t pipe_interleave_size;
  90         uint8_t num_pipes;
  91         uint8_t max_compress_frags;
  92         uint8_t num_banks;
  93         uint8_t num_se;
  94         uint8_t num_rb_per_se;
  95 };
  96
  97 struct amdgpu_gfx_config {
  98         unsigned max_shader_engines;
  99         unsigned max_tile_pipes;
 100         unsigned max_cu_per_sh;
 101         unsigned max_sh_per_se;
 102         unsigned max_backends_per_se;
 103         unsigned max_texture_channel_caches;
 104         unsigned max_gprs;
 105         unsigned max_gs_threads;
 106         unsigned max_hw_contexts;
 107         unsigned sc_prim_fifo_size_frontend;
 108         unsigned sc_prim_fifo_size_backend;
 109         unsigned sc_hiz_tile_fifo_size;
 110         unsigned sc_earlyz_tile_fifo_size;
 111
 112         unsigned num_tile_pipes;
 113         unsigned backend_enable_mask;
 114         unsigned mem_max_burst_length_bytes;
 115         unsigned mem_row_size_in_kb;
 116         unsigned shader_engine_tile_size;
 117         unsigned num_gpus;
 118         unsigned multi_gpu_tile_size;
 119         unsigned mc_arb_ramcfg;
 120         unsigned gb_addr_config;
 121         unsigned num_rbs;
 122         unsigned gs_vgt_table_depth;
 123         unsigned gs_prim_buffer_depth;
 124
 125         uint32_t tile_mode_array[32];
 126         uint32_t macrotile_mode_array[16];
 127
 128         struct gb_addr_config gb_addr_config_fields;
 129         struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
 130
 131         /* gfx configure feature */
 132         uint32_t double_offchip_lds_buf;
 133         /* cached value of DB_DEBUG2 */
 134         uint32_t db_debug2;
 135         /* gfx10 specific config */
 136         uint32_t num_sc_per_sh;
 137         uint32_t num_packer_per_sc;
 138         uint32_t pa_sc_tile_steering_override;
 139 };
 140
 141 struct amdgpu_cu_info {
 142         uint32_t simd_per_cu;
 143         uint32_t max_waves_per_simd;
 144         uint32_t wave_front_size;
 145         uint32_t max_scratch_slots_per_cu;
 146         uint32_t lds_size;
 147
 148         /* total active CU number */
 149         uint32_t number;
 150         uint32_t ao_cu_mask;
 151         uint32_t ao_cu_bitmap[4][4];
 152         uint32_t bitmap[4][4];
 153 };
 154
 155 struct amdgpu_gfx_funcs {
 156         /* get the gpu clock counter */
 157         uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
 158         void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,
 159                              u32 sh_num, u32 instance);
 160         void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd,
 161                                uint32_t wave, uint32_t *dst, int *no_fields);
 162         void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd,
 163                                 uint32_t wave, uint32_t thread, uint32_t start,
 164                                 uint32_t size, uint32_t *dst);
 165         void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd,
 166                                 uint32_t wave, uint32_t start, uint32_t size,
 167                                 uint32_t *dst);
 168         void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,
 169                                  u32 queue);
 170 };
 171
 172 struct amdgpu_ngg_buf {
 173         struct amdgpu_bo        *bo;
 174         uint64_t                gpu_addr;
 175         uint32_t                size;
 176         uint32_t                bo_size;
 177 };
 178
 179 enum {
 180         NGG_PRIM = 0,
 181         NGG_POS,
 182         NGG_CNTL,
 183         NGG_PARAM,
 184         NGG_BUF_MAX
 185 };
 186
 187 struct amdgpu_ngg {
 188         struct amdgpu_ngg_buf   buf[NGG_BUF_MAX];
 189         uint32_t                gds_reserve_addr;
 190         uint32_t                gds_reserve_size;
 191         bool                    init;
 192 };
 193
 194 struct sq_work {
 195         struct work_struct      work;
 196         unsigned ih_data;
 197 };
 198
 199 struct amdgpu_pfp {
 200         struct amdgpu_bo                *pfp_fw_obj;
 201         uint64_t                        pfp_fw_gpu_addr;
 202         uint32_t                        *pfp_fw_ptr;
 203 };
 204
 205 struct amdgpu_ce {
 206         struct amdgpu_bo                *ce_fw_obj;
 207         uint64_t                        ce_fw_gpu_addr;
 208         uint32_t                        *ce_fw_ptr;
 209 };
 210
 211 struct amdgpu_me {
 212         struct amdgpu_bo                *me_fw_obj;
 213         uint64_t                        me_fw_gpu_addr;
 214         uint32_t                        *me_fw_ptr;
 215         uint32_t                        num_me;
 216         uint32_t                        num_pipe_per_me;
 217         uint32_t                        num_queue_per_pipe;
 218         void                            *mqd_backup[AMDGPU_MAX_GFX_RINGS + 1];
 219
 220         /* These are the resources for which amdgpu takes ownership */
 221         DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
 222 };
 223
 224 struct amdgpu_gfx {
 225         struct mutex                    gpu_clock_mutex;
 226         struct amdgpu_gfx_config        config;
 227         struct amdgpu_rlc               rlc;
 228         struct amdgpu_pfp               pfp;
 229         struct amdgpu_ce                ce;
 230         struct amdgpu_me                me;
 231         struct amdgpu_mec               mec;
 232         struct amdgpu_kiq               kiq;
 233         struct amdgpu_scratch           scratch;
 234         const struct firmware           *me_fw; /* ME firmware */
 235         uint32_t                        me_fw_version;
 236         const struct firmware           *pfp_fw; /* PFP firmware */
 237         uint32_t                        pfp_fw_version;
 238         const struct firmware           *ce_fw; /* CE firmware */
 239         uint32_t                        ce_fw_version;
 240         const struct firmware           *rlc_fw; /* RLC firmware */
 241         uint32_t                        rlc_fw_version;
 242         const struct firmware           *mec_fw; /* MEC firmware */
 243         uint32_t                        mec_fw_version;
 244         const struct firmware           *mec2_fw; /* MEC2 firmware */
 245         uint32_t                        mec2_fw_version;
 246         uint32_t                        me_feature_version;
 247         uint32_t                        ce_feature_version;
 248         uint32_t                        pfp_feature_version;
 249         uint32_t                        rlc_feature_version;
 250         uint32_t                        rlc_srlc_fw_version;
 251         uint32_t                        rlc_srlc_feature_version;
 252         uint32_t                        rlc_srlg_fw_version;
 253         uint32_t                        rlc_srlg_feature_version;
 254         uint32_t                        rlc_srls_fw_version;
 255         uint32_t                        rlc_srls_feature_version;
 256         uint32_t                        mec_feature_version;
 257         uint32_t                        mec2_feature_version;
 258         bool                            mec_fw_write_wait;
 259         bool                            me_fw_write_wait;
 260         struct amdgpu_ring              gfx_ring[AMDGPU_MAX_GFX_RINGS];
 261         unsigned                        num_gfx_rings;
 262         struct amdgpu_ring              compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
 263         unsigned                        num_compute_rings;
 264         struct amdgpu_irq_src           eop_irq;
 265         struct amdgpu_irq_src           priv_reg_irq;
 266         struct amdgpu_irq_src           priv_inst_irq;
 267         struct amdgpu_irq_src           cp_ecc_error_irq;
 268         struct amdgpu_irq_src           sq_irq;
 269         struct sq_work                  sq_work;
 270
 271         /* gfx status */
 272         uint32_t                        gfx_current_status;
 273         /* ce ram size*/
 274         unsigned                        ce_ram_size;
 275         struct amdgpu_cu_info           cu_info;
 276         const struct amdgpu_gfx_funcs   *funcs;
 277
 278         /* reset mask */
 279         uint32_t                        grbm_soft_reset;
 280         uint32_t                        srbm_soft_reset;
 281
 282         /* NGG */
 283         struct amdgpu_ngg               ngg;
 284
 285         /* gfx off */
 286         bool                            gfx_off_state; /* true: enabled, false: disabled */
 287         struct mutex                    gfx_off_mutex;
 288         uint32_t                        gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */
 289         struct delayed_work             gfx_off_delay_work;
 290
 291         /* pipe reservation */
 292         struct mutex                    pipe_reserve_mutex;
 293         DECLARE_BITMAP                  (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
 294
 295         /*ras */
 296         struct ras_common_if            *ras_if;
 297 };
 298
 299 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
 300 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
 301 #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q))
 302
 303 /**
 304  * amdgpu_gfx_create_bitmask - create a bitmask
 305  *
 306  * @bit_width: length of the mask
 307  *
 308  * create a variable length bit mask.
 309  * Returns the bitmask.
 310  */
 311 static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width)
 312 {
 313         return (u32)((1ULL << bit_width) - 1);
 314 }
 315
 316 int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg);
 317 void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg);
 318
 319 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se,
 320                                  unsigned max_sh);
 321
 322 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
 323                              struct amdgpu_ring *ring,
 324                              struct amdgpu_irq_src *irq);
 325
 326 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring,
 327                               struct amdgpu_irq_src *irq);
 328
 329 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev);
 330 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
 331                         unsigned hpd_size);
 332
 333 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
 334                            unsigned mqd_size);
 335 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev);
 336
 337 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
 338 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev);
 339
 340 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
 341                                 int pipe, int queue);
 342 void amdgpu_gfx_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
 343                                  int *mec, int *pipe, int *queue);
 344 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
 345                                      int pipe, int queue);
 346 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
 347                                int pipe, int queue);
 348 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
 349                                 int *me, int *pipe, int *queue);
 350 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
 351                                     int pipe, int queue);
 352 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
 353
 354 #endif