drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "amdgpu_amdkfd.h"
  24 #include "amd_shared.h"
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_gfx.h"
  28 #include "amdgpu_dma_buf.h"
  29 #include <linux/module.h>
  30 #include <linux/dma-buf.h>
  31 #include "amdgpu_xgmi.h"
  32
  33 static const unsigned int compute_vmid_bitmap = 0xFF00;
  34
  35 /* Total memory size in system memory and all GPU VRAM. Used to
  36  * estimate worst case amount of memory to reserve for page tables
  37  */
  38 uint64_t amdgpu_amdkfd_total_mem_size;
  39
  40 int amdgpu_amdkfd_init(void)
  41 {
  42         struct sysinfo si;
  43         int ret;
  44
  45         si_meminfo(&si);
  46         amdgpu_amdkfd_total_mem_size = si.totalram - si.totalhigh;
  47         amdgpu_amdkfd_total_mem_size *= si.mem_unit;
  48
  49 #ifdef CONFIG_HSA_AMD
  50         ret = kgd2kfd_init();
  51         amdgpu_amdkfd_gpuvm_init_mem_limits();
  52 #else
  53         ret = -ENOENT;
  54 #endif
  55
  56         return ret;
  57 }
  58
  59 void amdgpu_amdkfd_fini(void)
  60 {
  61         kgd2kfd_exit();
  62 }
  63
  64 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
  65 {
  66         const struct kfd2kgd_calls *kfd2kgd;
  67
  68         switch (adev->asic_type) {
  69 #ifdef CONFIG_DRM_AMDGPU_CIK
  70         case CHIP_KAVERI:
  71         case CHIP_HAWAII:
  72                 kfd2kgd = amdgpu_amdkfd_gfx_7_get_functions();
  73                 break;
  74 #endif
  75         case CHIP_CARRIZO:
  76         case CHIP_TONGA:
  77         case CHIP_FIJI:
  78         case CHIP_POLARIS10:
  79         case CHIP_POLARIS11:
  80         case CHIP_POLARIS12:
  81         case CHIP_VEGAM:
  82                 kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions();
  83                 break;
  84         case CHIP_VEGA10:
  85         case CHIP_VEGA12:
  86         case CHIP_VEGA20:
  87         case CHIP_RAVEN:
  88                 kfd2kgd = amdgpu_amdkfd_gfx_9_0_get_functions();
  89                 break;
  90         default:
  91                 dev_info(adev->dev, "kfd not supported on this ASIC\n");
  92                 return;
  93         }
  94
  95         adev->kfd.dev = kgd2kfd_probe((struct kgd_dev *)adev,
  96                                       adev->pdev, kfd2kgd);
  97
  98         if (adev->kfd.dev)
  99                 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size;
 100 }
 101
 102 /**
 103  * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
 104  *                                setup amdkfd
 105  *
 106  * @adev: amdgpu_device pointer
 107  * @aperture_base: output returning doorbell aperture base physical address
 108  * @aperture_size: output returning doorbell aperture size in bytes
 109  * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
 110  *
 111  * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
 112  * takes doorbells required for its own rings and reports the setup to amdkfd.
 113  * amdgpu reserved doorbells are at the start of the doorbell aperture.
 114  */
 115 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
 116                                          phys_addr_t *aperture_base,
 117                                          size_t *aperture_size,
 118                                          size_t *start_offset)
 119 {
 120         /*
 121          * The first num_doorbells are used by amdgpu.
 122          * amdkfd takes whatever's left in the aperture.
 123          */
 124         if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
 125                 *aperture_base = adev->doorbell.base;
 126                 *aperture_size = adev->doorbell.size;
 127                 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
 128         } else {
 129                 *aperture_base = 0;
 130                 *aperture_size = 0;
 131                 *start_offset = 0;
 132         }
 133 }
 134
 135 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
 136 {
 137         int i;
 138         int last_valid_bit;
 139
 140         if (adev->kfd.dev) {
 141                 struct kgd2kfd_shared_resources gpu_resources = {
 142                         .compute_vmid_bitmap = compute_vmid_bitmap,
 143                         .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,
 144                         .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,
 145                         .gpuvm_size = min(adev->vm_manager.max_pfn
 146                                           << AMDGPU_GPU_PAGE_SHIFT,
 147                                           AMDGPU_GMC_HOLE_START),
 148                         .drm_render_minor = adev->ddev->render->index,
 149                         .sdma_doorbell_idx = adev->doorbell_index.sdma_engine,
 150
 151                 };
 152
 153                 /* this is going to have a few of the MSBs set that we need to
 154                  * clear
 155                  */
 156                 bitmap_complement(gpu_resources.queue_bitmap,
 157                                   adev->gfx.mec.queue_bitmap,
 158                                   KGD_MAX_QUEUES);
 159
 160                 /* remove the KIQ bit as well */
 161                 if (adev->gfx.kiq.ring.sched.ready)
 162                         clear_bit(amdgpu_gfx_mec_queue_to_bit(adev,
 163                                                           adev->gfx.kiq.ring.me - 1,
 164                                                           adev->gfx.kiq.ring.pipe,
 165                                                           adev->gfx.kiq.ring.queue),
 166                                   gpu_resources.queue_bitmap);
 167
 168                 /* According to linux/bitmap.h we shouldn't use bitmap_clear if
 169                  * nbits is not compile time constant
 170                  */
 171                 last_valid_bit = 1 /* only first MEC can have compute queues */
 172                                 * adev->gfx.mec.num_pipe_per_mec
 173                                 * adev->gfx.mec.num_queue_per_pipe;
 174                 for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i)
 175                         clear_bit(i, gpu_resources.queue_bitmap);
 176
 177                 amdgpu_doorbell_get_kfd_info(adev,
 178                                 &gpu_resources.doorbell_physical_address,
 179                                 &gpu_resources.doorbell_aperture_size,
 180                                 &gpu_resources.doorbell_start_offset);
 181
 182                 /* Since SOC15, BIF starts to statically use the
 183                  * lower 12 bits of doorbell addresses for routing
 184                  * based on settings in registers like
 185                  * SDMA0_DOORBELL_RANGE etc..
 186                  * In order to route a doorbell to CP engine, the lower
 187                  * 12 bits of its address has to be outside the range
 188                  * set for SDMA, VCN, and IH blocks.
 189                  */
 190                 if (adev->asic_type >= CHIP_VEGA10) {
 191                         gpu_resources.non_cp_doorbells_start =
 192                                         adev->doorbell_index.first_non_cp;
 193                         gpu_resources.non_cp_doorbells_end =
 194                                         adev->doorbell_index.last_non_cp;
 195                 }
 196
 197                 kgd2kfd_device_init(adev->kfd.dev, &gpu_resources);
 198         }
 199 }
 200
 201 void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev)
 202 {
 203         if (adev->kfd.dev) {
 204                 kgd2kfd_device_exit(adev->kfd.dev);
 205                 adev->kfd.dev = NULL;
 206         }
 207 }
 208
 209 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
 210                 const void *ih_ring_entry)
 211 {
 212         if (adev->kfd.dev)
 213                 kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry);
 214 }
 215
 216 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev)
 217 {
 218         if (adev->kfd.dev)
 219                 kgd2kfd_suspend(adev->kfd.dev);
 220 }
 221
 222 int amdgpu_amdkfd_resume(struct amdgpu_device *adev)
 223 {
 224         int r = 0;
 225
 226         if (adev->kfd.dev)
 227                 r = kgd2kfd_resume(adev->kfd.dev);
 228
 229         return r;
 230 }
 231
 232 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev)
 233 {
 234         int r = 0;
 235
 236         if (adev->kfd.dev)
 237                 r = kgd2kfd_pre_reset(adev->kfd.dev);
 238
 239         return r;
 240 }
 241
 242 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev)
 243 {
 244         int r = 0;
 245
 246         if (adev->kfd.dev)
 247                 r = kgd2kfd_post_reset(adev->kfd.dev);
 248
 249         return r;
 250 }
 251
 252 void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd)
 253 {
 254         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 255
 256         if (amdgpu_device_should_recover_gpu(adev))
 257                 amdgpu_device_gpu_recover(adev, NULL);
 258 }
 259
 260 int amdgpu_amdkfd_alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
 261                                 void **mem_obj, uint64_t *gpu_addr,
 262                                 void **cpu_ptr, bool mqd_gfx9)
 263 {
 264         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 265         struct amdgpu_bo *bo = NULL;
 266         struct amdgpu_bo_param bp;
 267         int r;
 268         void *cpu_ptr_tmp = NULL;
 269
 270         memset(&bp, 0, sizeof(bp));
 271         bp.size = size;
 272         bp.byte_align = PAGE_SIZE;
 273         bp.domain = AMDGPU_GEM_DOMAIN_GTT;
 274         bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 275         bp.type = ttm_bo_type_kernel;
 276         bp.resv = NULL;
 277
 278         if (mqd_gfx9)
 279                 bp.flags |= AMDGPU_GEM_CREATE_MQD_GFX9;
 280
 281         r = amdgpu_bo_create(adev, &bp, &bo);
 282         if (r) {
 283                 dev_err(adev->dev,
 284                         "failed to allocate BO for amdkfd (%d)\n", r);
 285                 return r;
 286         }
 287
 288         /* map the buffer */
 289         r = amdgpu_bo_reserve(bo, true);
 290         if (r) {
 291                 dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
 292                 goto allocate_mem_reserve_bo_failed;
 293         }
 294
 295         r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
 296         if (r) {
 297                 dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
 298                 goto allocate_mem_pin_bo_failed;
 299         }
 300
 301         r = amdgpu_ttm_alloc_gart(&bo->tbo);
 302         if (r) {
 303                 dev_err(adev->dev, "%p bind failed\n", bo);
 304                 goto allocate_mem_kmap_bo_failed;
 305         }
 306
 307         r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp);
 308         if (r) {
 309                 dev_err(adev->dev,
 310                         "(%d) failed to map bo to kernel for amdkfd\n", r);
 311                 goto allocate_mem_kmap_bo_failed;
 312         }
 313
 314         *mem_obj = bo;
 315         *gpu_addr = amdgpu_bo_gpu_offset(bo);
 316         *cpu_ptr = cpu_ptr_tmp;
 317
 318         amdgpu_bo_unreserve(bo);
 319
 320         return 0;
 321
 322 allocate_mem_kmap_bo_failed:
 323         amdgpu_bo_unpin(bo);
 324 allocate_mem_pin_bo_failed:
 325         amdgpu_bo_unreserve(bo);
 326 allocate_mem_reserve_bo_failed:
 327         amdgpu_bo_unref(&bo);
 328
 329         return r;
 330 }
 331
 332 void amdgpu_amdkfd_free_gtt_mem(struct kgd_dev *kgd, void *mem_obj)
 333 {
 334         struct amdgpu_bo *bo = (struct amdgpu_bo *) mem_obj;
 335
 336         amdgpu_bo_reserve(bo, true);
 337         amdgpu_bo_kunmap(bo);
 338         amdgpu_bo_unpin(bo);
 339         amdgpu_bo_unreserve(bo);
 340         amdgpu_bo_unref(&(bo));
 341 }
 342
 343 int amdgpu_amdkfd_alloc_gws(struct kgd_dev *kgd, size_t size,
 344                                 void **mem_obj)
 345 {
 346         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 347         struct amdgpu_bo *bo = NULL;
 348         struct amdgpu_bo_param bp;
 349         int r;
 350
 351         memset(&bp, 0, sizeof(bp));
 352         bp.size = size;
 353         bp.byte_align = 1;
 354         bp.domain = AMDGPU_GEM_DOMAIN_GWS;
 355         bp.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
 356         bp.type = ttm_bo_type_device;
 357         bp.resv = NULL;
 358
 359         r = amdgpu_bo_create(adev, &bp, &bo);
 360         if (r) {
 361                 dev_err(adev->dev,
 362                         "failed to allocate gws BO for amdkfd (%d)\n", r);
 363                 return r;
 364         }
 365
 366         *mem_obj = bo;
 367         return 0;
 368 }
 369
 370 void amdgpu_amdkfd_free_gws(struct kgd_dev *kgd, void *mem_obj)
 371 {
 372         struct amdgpu_bo *bo = (struct amdgpu_bo *)mem_obj;
 373
 374         amdgpu_bo_unref(&bo);
 375 }
 376
 377 uint32_t amdgpu_amdkfd_get_fw_version(struct kgd_dev *kgd,
 378                                       enum kgd_engine_type type)
 379 {
 380         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 381
 382         switch (type) {
 383         case KGD_ENGINE_PFP:
 384                 return adev->gfx.pfp_fw_version;
 385
 386         case KGD_ENGINE_ME:
 387                 return adev->gfx.me_fw_version;
 388
 389         case KGD_ENGINE_CE:
 390                 return adev->gfx.ce_fw_version;
 391
 392         case KGD_ENGINE_MEC1:
 393                 return adev->gfx.mec_fw_version;
 394
 395         case KGD_ENGINE_MEC2:
 396                 return adev->gfx.mec2_fw_version;
 397
 398         case KGD_ENGINE_RLC:
 399                 return adev->gfx.rlc_fw_version;
 400
 401         case KGD_ENGINE_SDMA1:
 402                 return adev->sdma.instance[0].fw_version;
 403
 404         case KGD_ENGINE_SDMA2:
 405                 return adev->sdma.instance[1].fw_version;
 406
 407         default:
 408                 return 0;
 409         }
 410
 411         return 0;
 412 }
 413
 414 void amdgpu_amdkfd_get_local_mem_info(struct kgd_dev *kgd,
 415                                       struct kfd_local_mem_info *mem_info)
 416 {
 417         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 418         uint64_t address_mask = adev->dev->dma_mask ? ~*adev->dev->dma_mask :
 419                                              ~((1ULL << 32) - 1);
 420         resource_size_t aper_limit = adev->gmc.aper_base + adev->gmc.aper_size;
 421
 422         memset(mem_info, 0, sizeof(*mem_info));
 423         if (!(adev->gmc.aper_base & address_mask || aper_limit & address_mask)) {
 424                 mem_info->local_mem_size_public = adev->gmc.visible_vram_size;
 425                 mem_info->local_mem_size_private = adev->gmc.real_vram_size -
 426                                 adev->gmc.visible_vram_size;
 427         } else {
 428                 mem_info->local_mem_size_public = 0;
 429                 mem_info->local_mem_size_private = adev->gmc.real_vram_size;
 430         }
 431         mem_info->vram_width = adev->gmc.vram_width;
 432
 433         pr_debug("Address base: %pap limit %pap public 0x%llx private 0x%llx\n",
 434                         &adev->gmc.aper_base, &aper_limit,
 435                         mem_info->local_mem_size_public,
 436                         mem_info->local_mem_size_private);
 437
 438         if (amdgpu_sriov_vf(adev))
 439                 mem_info->mem_clk_max = adev->clock.default_mclk / 100;
 440         else if (adev->powerplay.pp_funcs)
 441                 mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100;
 442         else
 443                 mem_info->mem_clk_max = 100;
 444 }
 445
 446 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct kgd_dev *kgd)
 447 {
 448         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 449
 450         if (adev->gfx.funcs->get_gpu_clock_counter)
 451                 return adev->gfx.funcs->get_gpu_clock_counter(adev);
 452         return 0;
 453 }
 454
 455 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct kgd_dev *kgd)
 456 {
 457         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 458
 459         /* the sclk is in quantas of 10kHz */
 460         if (amdgpu_sriov_vf(adev))
 461                 return adev->clock.default_sclk / 100;
 462         else if (adev->powerplay.pp_funcs)
 463                 return amdgpu_dpm_get_sclk(adev, false) / 100;
 464         else
 465                 return 100;
 466 }
 467
 468 void amdgpu_amdkfd_get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info)
 469 {
 470         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 471         struct amdgpu_cu_info acu_info = adev->gfx.cu_info;
 472
 473         memset(cu_info, 0, sizeof(*cu_info));
 474         if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap))
 475                 return;
 476
 477         cu_info->cu_active_number = acu_info.number;
 478         cu_info->cu_ao_mask = acu_info.ao_cu_mask;
 479         memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0],
 480                sizeof(acu_info.bitmap));
 481         cu_info->num_shader_engines = adev->gfx.config.max_shader_engines;
 482         cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 483         cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 484         cu_info->simd_per_cu = acu_info.simd_per_cu;
 485         cu_info->max_waves_per_simd = acu_info.max_waves_per_simd;
 486         cu_info->wave_front_size = acu_info.wave_front_size;
 487         cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu;
 488         cu_info->lds_size = acu_info.lds_size;
 489 }
 490
 491 int amdgpu_amdkfd_get_dmabuf_info(struct kgd_dev *kgd, int dma_buf_fd,
 492                                   struct kgd_dev **dma_buf_kgd,
 493                                   uint64_t *bo_size, void *metadata_buffer,
 494                                   size_t buffer_size, uint32_t *metadata_size,
 495                                   uint32_t *flags)
 496 {
 497         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 498         struct dma_buf *dma_buf;
 499         struct drm_gem_object *obj;
 500         struct amdgpu_bo *bo;
 501         uint64_t metadata_flags;
 502         int r = -EINVAL;
 503
 504         dma_buf = dma_buf_get(dma_buf_fd);
 505         if (IS_ERR(dma_buf))
 506                 return PTR_ERR(dma_buf);
 507
 508         if (dma_buf->ops != &amdgpu_dmabuf_ops)
 509                 /* Can't handle non-graphics buffers */
 510                 goto out_put;
 511
 512         obj = dma_buf->priv;
 513         if (obj->dev->driver != adev->ddev->driver)
 514                 /* Can't handle buffers from different drivers */
 515                 goto out_put;
 516
 517         adev = obj->dev->dev_private;
 518         bo = gem_to_amdgpu_bo(obj);
 519         if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM |
 520                                     AMDGPU_GEM_DOMAIN_GTT)))
 521                 /* Only VRAM and GTT BOs are supported */
 522                 goto out_put;
 523
 524         r = 0;
 525         if (dma_buf_kgd)
 526                 *dma_buf_kgd = (struct kgd_dev *)adev;
 527         if (bo_size)
 528                 *bo_size = amdgpu_bo_size(bo);
 529         if (metadata_size)
 530                 *metadata_size = bo->metadata_size;
 531         if (metadata_buffer)
 532                 r = amdgpu_bo_get_metadata(bo, metadata_buffer, buffer_size,
 533                                            metadata_size, &metadata_flags);
 534         if (flags) {
 535                 *flags = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
 536                         ALLOC_MEM_FLAGS_VRAM : ALLOC_MEM_FLAGS_GTT;
 537
 538                 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
 539                         *flags |= ALLOC_MEM_FLAGS_PUBLIC;
 540         }
 541
 542 out_put:
 543         dma_buf_put(dma_buf);
 544         return r;
 545 }
 546
 547 uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd)
 548 {
 549         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 550
 551         return amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 552 }
 553
 554 uint64_t amdgpu_amdkfd_get_hive_id(struct kgd_dev *kgd)
 555 {
 556         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 557
 558         return adev->gmc.xgmi.hive_id;
 559 }
 560 uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *src)
 561 {
 562         struct amdgpu_device *peer_adev = (struct amdgpu_device *)src;
 563         struct amdgpu_device *adev = (struct amdgpu_device *)dst;
 564         int ret = amdgpu_xgmi_get_hops_count(adev, peer_adev);
 565
 566         if (ret < 0) {
 567                 DRM_ERROR("amdgpu: failed to get  xgmi hops count between node %d and %d. ret = %d\n",
 568                         adev->gmc.xgmi.physical_node_id,
 569                         peer_adev->gmc.xgmi.physical_node_id, ret);
 570                 ret = 0;
 571         }
 572         return  (uint8_t)ret;
 573 }
 574
 575 uint64_t amdgpu_amdkfd_get_mmio_remap_phys_addr(struct kgd_dev *kgd)
 576 {
 577         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 578
 579         return adev->rmmio_remap.bus_addr;
 580 }
 581
 582 uint32_t amdgpu_amdkfd_get_num_gws(struct kgd_dev *kgd)
 583 {
 584         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 585
 586         return adev->gds.gws_size;
 587 }
 588
 589 int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
 590                                 uint32_t vmid, uint64_t gpu_addr,
 591                                 uint32_t *ib_cmd, uint32_t ib_len)
 592 {
 593         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 594         struct amdgpu_job *job;
 595         struct amdgpu_ib *ib;
 596         struct amdgpu_ring *ring;
 597         struct dma_fence *f = NULL;
 598         int ret;
 599
 600         switch (engine) {
 601         case KGD_ENGINE_MEC1:
 602                 ring = &adev->gfx.compute_ring[0];
 603                 break;
 604         case KGD_ENGINE_SDMA1:
 605                 ring = &adev->sdma.instance[0].ring;
 606                 break;
 607         case KGD_ENGINE_SDMA2:
 608                 ring = &adev->sdma.instance[1].ring;
 609                 break;
 610         default:
 611                 pr_err("Invalid engine in IB submission: %d\n", engine);
 612                 ret = -EINVAL;
 613                 goto err;
 614         }
 615
 616         ret = amdgpu_job_alloc(adev, 1, &job, NULL);
 617         if (ret)
 618                 goto err;
 619
 620         ib = &job->ibs[0];
 621         memset(ib, 0, sizeof(struct amdgpu_ib));
 622
 623         ib->gpu_addr = gpu_addr;
 624         ib->ptr = ib_cmd;
 625         ib->length_dw = ib_len;
 626         /* This works for NO_HWS. TODO: need to handle without knowing VMID */
 627         job->vmid = vmid;
 628
 629         ret = amdgpu_ib_schedule(ring, 1, ib, job, &f);
 630         if (ret) {
 631                 DRM_ERROR("amdgpu: failed to schedule IB.\n");
 632                 goto err_ib_sched;
 633         }
 634
 635         ret = dma_fence_wait(f, false);
 636
 637 err_ib_sched:
 638         dma_fence_put(f);
 639         amdgpu_job_free(job);
 640 err:
 641         return ret;
 642 }
 643
 644 void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle)
 645 {
 646         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 647
 648         if (adev->powerplay.pp_funcs &&
 649             adev->powerplay.pp_funcs->switch_power_profile)
 650                 amdgpu_dpm_switch_power_profile(adev,
 651                                                 PP_SMC_POWER_PROFILE_COMPUTE,
 652                                                 !idle);
 653 }
 654
 655 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
 656 {
 657         if (adev->kfd.dev) {
 658                 if ((1 << vmid) & compute_vmid_bitmap)
 659                         return true;
 660         }
 661
 662         return false;
 663 }
 664
 665 #ifndef CONFIG_HSA_AMD
 666 bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm)
 667 {
 668         return false;
 669 }
 670
 671 void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo)
 672 {
 673 }
 674
 675 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
 676                                         struct amdgpu_vm *vm)
 677 {
 678 }
 679
 680 struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f)
 681 {
 682         return NULL;
 683 }
 684
 685 int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm)
 686 {
 687         return 0;
 688 }
 689
 690 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void)
 691 {
 692         return NULL;
 693 }
 694
 695 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void)
 696 {
 697         return NULL;
 698 }
 699
 700 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void)
 701 {
 702         return NULL;
 703 }
 704
 705 struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev,
 706                               const struct kfd2kgd_calls *f2g)
 707 {
 708         return NULL;
 709 }
 710
 711 bool kgd2kfd_device_init(struct kfd_dev *kfd,
 712                          const struct kgd2kfd_shared_resources *gpu_resources)
 713 {
 714         return false;
 715 }
 716
 717 void kgd2kfd_device_exit(struct kfd_dev *kfd)
 718 {
 719 }
 720
 721 void kgd2kfd_exit(void)
 722 {
 723 }
 724
 725 void kgd2kfd_suspend(struct kfd_dev *kfd)
 726 {
 727 }
 728
 729 int kgd2kfd_resume(struct kfd_dev *kfd)
 730 {
 731         return 0;
 732 }
 733
 734 int kgd2kfd_pre_reset(struct kfd_dev *kfd)
 735 {
 736         return 0;
 737 }
 738
 739 int kgd2kfd_post_reset(struct kfd_dev *kfd)
 740 {
 741         return 0;
 742 }
 743
 744 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
 745 {
 746 }
 747
 748 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
 749 {
 750 }
 751 #endif