drivers/gpu/drm/amd/pm/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <[email protected]>
  23  *          Alex Deucher <[email protected]>
  24  */
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_drv.h"
  28 #include "amdgpu_pm.h"
  29 #include "amdgpu_dpm.h"
  30 #include "atom.h"
  31 #include <linux/pci.h>
  32 #include <linux/hwmon.h>
  33 #include <linux/hwmon-sysfs.h>
  34 #include <linux/nospec.h>
  35 #include <linux/pm_runtime.h>
  36 #include <asm/processor.h>
  37
  38 #define MAX_NUM_OF_FEATURES_PER_SUBSET          8
  39 #define MAX_NUM_OF_SUBSETS                      8
  40
  41 struct od_attribute {
  42         struct kobj_attribute   attribute;
  43         struct list_head        entry;
  44 };
  45
  46 struct od_kobj {
  47         struct kobject          kobj;
  48         struct list_head        entry;
  49         struct list_head        attribute;
  50         void                    *priv;
  51 };
  52
  53 struct od_feature_ops {
  54         umode_t (*is_visible)(struct amdgpu_device *adev);
  55         ssize_t (*show)(struct kobject *kobj, struct kobj_attribute *attr,
  56                         char *buf);
  57         ssize_t (*store)(struct kobject *kobj, struct kobj_attribute *attr,
  58                          const char *buf, size_t count);
  59 };
  60
  61 struct od_feature_item {
  62         const char              *name;
  63         struct od_feature_ops   ops;
  64 };
  65
  66 struct od_feature_container {
  67         char                            *name;
  68         struct od_feature_ops           ops;
  69         struct od_feature_item          sub_feature[MAX_NUM_OF_FEATURES_PER_SUBSET];
  70 };
  71
  72 struct od_feature_set {
  73         struct od_feature_container     containers[MAX_NUM_OF_SUBSETS];
  74 };
  75
  76 static const struct hwmon_temp_label {
  77         enum PP_HWMON_TEMP channel;
  78         const char *label;
  79 } temp_label[] = {
  80         {PP_TEMP_EDGE, "edge"},
  81         {PP_TEMP_JUNCTION, "junction"},
  82         {PP_TEMP_MEM, "mem"},
  83 };
  84
  85 const char * const amdgpu_pp_profile_name[] = {
  86         "BOOTUP_DEFAULT",
  87         "3D_FULL_SCREEN",
  88         "POWER_SAVING",
  89         "VIDEO",
  90         "VR",
  91         "COMPUTE",
  92         "CUSTOM",
  93         "WINDOW_3D",
  94         "CAPPED",
  95         "UNCAPPED",
  96 };
  97
  98 /**
  99  * DOC: power_dpm_state
 100  *
 101  * The power_dpm_state file is a legacy interface and is only provided for
 102  * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
 103  * certain power related parameters.  The file power_dpm_state is used for this.
 104  * It accepts the following arguments:
 105  *
 106  * - battery
 107  *
 108  * - balanced
 109  *
 110  * - performance
 111  *
 112  * battery
 113  *
 114  * On older GPUs, the vbios provided a special power state for battery
 115  * operation.  Selecting battery switched to this state.  This is no
 116  * longer provided on newer GPUs so the option does nothing in that case.
 117  *
 118  * balanced
 119  *
 120  * On older GPUs, the vbios provided a special power state for balanced
 121  * operation.  Selecting balanced switched to this state.  This is no
 122  * longer provided on newer GPUs so the option does nothing in that case.
 123  *
 124  * performance
 125  *
 126  * On older GPUs, the vbios provided a special power state for performance
 127  * operation.  Selecting performance switched to this state.  This is no
 128  * longer provided on newer GPUs so the option does nothing in that case.
 129  *
 130  */
 131
 132 static ssize_t amdgpu_get_power_dpm_state(struct device *dev,
 133                                           struct device_attribute *attr,
 134                                           char *buf)
 135 {
 136         struct drm_device *ddev = dev_get_drvdata(dev);
 137         struct amdgpu_device *adev = drm_to_adev(ddev);
 138         enum amd_pm_state_type pm;
 139         int ret;
 140
 141         if (amdgpu_in_reset(adev))
 142                 return -EPERM;
 143         if (adev->in_suspend && !adev->in_runpm)
 144                 return -EPERM;
 145
 146         ret = pm_runtime_get_sync(ddev->dev);
 147         if (ret < 0) {
 148                 pm_runtime_put_autosuspend(ddev->dev);
 149                 return ret;
 150         }
 151
 152         amdgpu_dpm_get_current_power_state(adev, &pm);
 153
 154         pm_runtime_mark_last_busy(ddev->dev);
 155         pm_runtime_put_autosuspend(ddev->dev);
 156
 157         return sysfs_emit(buf, "%s\n",
 158                           (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 159                           (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 160 }
 161
 162 static ssize_t amdgpu_set_power_dpm_state(struct device *dev,
 163                                           struct device_attribute *attr,
 164                                           const char *buf,
 165                                           size_t count)
 166 {
 167         struct drm_device *ddev = dev_get_drvdata(dev);
 168         struct amdgpu_device *adev = drm_to_adev(ddev);
 169         enum amd_pm_state_type  state;
 170         int ret;
 171
 172         if (amdgpu_in_reset(adev))
 173                 return -EPERM;
 174         if (adev->in_suspend && !adev->in_runpm)
 175                 return -EPERM;
 176
 177         if (strncmp("battery", buf, strlen("battery")) == 0)
 178                 state = POWER_STATE_TYPE_BATTERY;
 179         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 180                 state = POWER_STATE_TYPE_BALANCED;
 181         else if (strncmp("performance", buf, strlen("performance")) == 0)
 182                 state = POWER_STATE_TYPE_PERFORMANCE;
 183         else
 184                 return -EINVAL;
 185
 186         ret = pm_runtime_get_sync(ddev->dev);
 187         if (ret < 0) {
 188                 pm_runtime_put_autosuspend(ddev->dev);
 189                 return ret;
 190         }
 191
 192         amdgpu_dpm_set_power_state(adev, state);
 193
 194         pm_runtime_mark_last_busy(ddev->dev);
 195         pm_runtime_put_autosuspend(ddev->dev);
 196
 197         return count;
 198 }
 199
 200
 201 /**
 202  * DOC: power_dpm_force_performance_level
 203  *
 204  * The amdgpu driver provides a sysfs API for adjusting certain power
 205  * related parameters.  The file power_dpm_force_performance_level is
 206  * used for this.  It accepts the following arguments:
 207  *
 208  * - auto
 209  *
 210  * - low
 211  *
 212  * - high
 213  *
 214  * - manual
 215  *
 216  * - profile_standard
 217  *
 218  * - profile_min_sclk
 219  *
 220  * - profile_min_mclk
 221  *
 222  * - profile_peak
 223  *
 224  * auto
 225  *
 226  * When auto is selected, the driver will attempt to dynamically select
 227  * the optimal power profile for current conditions in the driver.
 228  *
 229  * low
 230  *
 231  * When low is selected, the clocks are forced to the lowest power state.
 232  *
 233  * high
 234  *
 235  * When high is selected, the clocks are forced to the highest power state.
 236  *
 237  * manual
 238  *
 239  * When manual is selected, the user can manually adjust which power states
 240  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 241  * and pp_dpm_pcie files and adjust the power state transition heuristics
 242  * via the pp_power_profile_mode sysfs file.
 243  *
 244  * profile_standard
 245  * profile_min_sclk
 246  * profile_min_mclk
 247  * profile_peak
 248  *
 249  * When the profiling modes are selected, clock and power gating are
 250  * disabled and the clocks are set for different profiling cases. This
 251  * mode is recommended for profiling specific work loads where you do
 252  * not want clock or power gating for clock fluctuation to interfere
 253  * with your results. profile_standard sets the clocks to a fixed clock
 254  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 255  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 256  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 257  *
 258  */
 259
 260 static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev,
 261                                                             struct device_attribute *attr,
 262                                                             char *buf)
 263 {
 264         struct drm_device *ddev = dev_get_drvdata(dev);
 265         struct amdgpu_device *adev = drm_to_adev(ddev);
 266         enum amd_dpm_forced_level level = 0xff;
 267         int ret;
 268
 269         if (amdgpu_in_reset(adev))
 270                 return -EPERM;
 271         if (adev->in_suspend && !adev->in_runpm)
 272                 return -EPERM;
 273
 274         ret = pm_runtime_get_sync(ddev->dev);
 275         if (ret < 0) {
 276                 pm_runtime_put_autosuspend(ddev->dev);
 277                 return ret;
 278         }
 279
 280         level = amdgpu_dpm_get_performance_level(adev);
 281
 282         pm_runtime_mark_last_busy(ddev->dev);
 283         pm_runtime_put_autosuspend(ddev->dev);
 284
 285         return sysfs_emit(buf, "%s\n",
 286                           (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 287                           (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 288                           (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 289                           (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 290                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 291                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 292                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 293                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 294                           (level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) ? "perf_determinism" :
 295                           "unknown");
 296 }
 297
 298 static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
 299                                                             struct device_attribute *attr,
 300                                                             const char *buf,
 301                                                             size_t count)
 302 {
 303         struct drm_device *ddev = dev_get_drvdata(dev);
 304         struct amdgpu_device *adev = drm_to_adev(ddev);
 305         enum amd_dpm_forced_level level;
 306         int ret = 0;
 307
 308         if (amdgpu_in_reset(adev))
 309                 return -EPERM;
 310         if (adev->in_suspend && !adev->in_runpm)
 311                 return -EPERM;
 312
 313         if (strncmp("low", buf, strlen("low")) == 0) {
 314                 level = AMD_DPM_FORCED_LEVEL_LOW;
 315         } else if (strncmp("high", buf, strlen("high")) == 0) {
 316                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 317         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 318                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 319         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 320                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 321         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 322                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 323         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 324                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 325         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 326                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 327         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 328                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 329         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 330                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 331         } else if (strncmp("perf_determinism", buf, strlen("perf_determinism")) == 0) {
 332                 level = AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM;
 333         }  else {
 334                 return -EINVAL;
 335         }
 336
 337         ret = pm_runtime_get_sync(ddev->dev);
 338         if (ret < 0) {
 339                 pm_runtime_put_autosuspend(ddev->dev);
 340                 return ret;
 341         }
 342
 343         mutex_lock(&adev->pm.stable_pstate_ctx_lock);
 344         if (amdgpu_dpm_force_performance_level(adev, level)) {
 345                 pm_runtime_mark_last_busy(ddev->dev);
 346                 pm_runtime_put_autosuspend(ddev->dev);
 347                 mutex_unlock(&adev->pm.stable_pstate_ctx_lock);
 348                 return -EINVAL;
 349         }
 350         /* override whatever a user ctx may have set */
 351         adev->pm.stable_pstate_ctx = NULL;
 352         mutex_unlock(&adev->pm.stable_pstate_ctx_lock);
 353
 354         pm_runtime_mark_last_busy(ddev->dev);
 355         pm_runtime_put_autosuspend(ddev->dev);
 356
 357         return count;
 358 }
 359
 360 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 361                 struct device_attribute *attr,
 362                 char *buf)
 363 {
 364         struct drm_device *ddev = dev_get_drvdata(dev);
 365         struct amdgpu_device *adev = drm_to_adev(ddev);
 366         struct pp_states_info data;
 367         uint32_t i;
 368         int buf_len, ret;
 369
 370         if (amdgpu_in_reset(adev))
 371                 return -EPERM;
 372         if (adev->in_suspend && !adev->in_runpm)
 373                 return -EPERM;
 374
 375         ret = pm_runtime_get_sync(ddev->dev);
 376         if (ret < 0) {
 377                 pm_runtime_put_autosuspend(ddev->dev);
 378                 return ret;
 379         }
 380
 381         if (amdgpu_dpm_get_pp_num_states(adev, &data))
 382                 memset(&data, 0, sizeof(data));
 383
 384         pm_runtime_mark_last_busy(ddev->dev);
 385         pm_runtime_put_autosuspend(ddev->dev);
 386
 387         buf_len = sysfs_emit(buf, "states: %d\n", data.nums);
 388         for (i = 0; i < data.nums; i++)
 389                 buf_len += sysfs_emit_at(buf, buf_len, "%d %s\n", i,
 390                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 391                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 392                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 393                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 394
 395         return buf_len;
 396 }
 397
 398 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 399                 struct device_attribute *attr,
 400                 char *buf)
 401 {
 402         struct drm_device *ddev = dev_get_drvdata(dev);
 403         struct amdgpu_device *adev = drm_to_adev(ddev);
 404         struct pp_states_info data = {0};
 405         enum amd_pm_state_type pm = 0;
 406         int i = 0, ret = 0;
 407
 408         if (amdgpu_in_reset(adev))
 409                 return -EPERM;
 410         if (adev->in_suspend && !adev->in_runpm)
 411                 return -EPERM;
 412
 413         ret = pm_runtime_get_sync(ddev->dev);
 414         if (ret < 0) {
 415                 pm_runtime_put_autosuspend(ddev->dev);
 416                 return ret;
 417         }
 418
 419         amdgpu_dpm_get_current_power_state(adev, &pm);
 420
 421         ret = amdgpu_dpm_get_pp_num_states(adev, &data);
 422
 423         pm_runtime_mark_last_busy(ddev->dev);
 424         pm_runtime_put_autosuspend(ddev->dev);
 425
 426         if (ret)
 427                 return ret;
 428
 429         for (i = 0; i < data.nums; i++) {
 430                 if (pm == data.states[i])
 431                         break;
 432         }
 433
 434         if (i == data.nums)
 435                 i = -EINVAL;
 436
 437         return sysfs_emit(buf, "%d\n", i);
 438 }
 439
 440 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 441                 struct device_attribute *attr,
 442                 char *buf)
 443 {
 444         struct drm_device *ddev = dev_get_drvdata(dev);
 445         struct amdgpu_device *adev = drm_to_adev(ddev);
 446
 447         if (amdgpu_in_reset(adev))
 448                 return -EPERM;
 449         if (adev->in_suspend && !adev->in_runpm)
 450                 return -EPERM;
 451
 452         if (adev->pm.pp_force_state_enabled)
 453                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 454         else
 455                 return sysfs_emit(buf, "\n");
 456 }
 457
 458 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 459                 struct device_attribute *attr,
 460                 const char *buf,
 461                 size_t count)
 462 {
 463         struct drm_device *ddev = dev_get_drvdata(dev);
 464         struct amdgpu_device *adev = drm_to_adev(ddev);
 465         enum amd_pm_state_type state = 0;
 466         struct pp_states_info data;
 467         unsigned long idx;
 468         int ret;
 469
 470         if (amdgpu_in_reset(adev))
 471                 return -EPERM;
 472         if (adev->in_suspend && !adev->in_runpm)
 473                 return -EPERM;
 474
 475         adev->pm.pp_force_state_enabled = false;
 476
 477         if (strlen(buf) == 1)
 478                 return count;
 479
 480         ret = kstrtoul(buf, 0, &idx);
 481         if (ret || idx >= ARRAY_SIZE(data.states))
 482                 return -EINVAL;
 483
 484         idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
 485
 486         ret = pm_runtime_get_sync(ddev->dev);
 487         if (ret < 0) {
 488                 pm_runtime_put_autosuspend(ddev->dev);
 489                 return ret;
 490         }
 491
 492         ret = amdgpu_dpm_get_pp_num_states(adev, &data);
 493         if (ret)
 494                 goto err_out;
 495
 496         state = data.states[idx];
 497
 498         /* only set user selected power states */
 499         if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 500             state != POWER_STATE_TYPE_DEFAULT) {
 501                 ret = amdgpu_dpm_dispatch_task(adev,
 502                                 AMD_PP_TASK_ENABLE_USER_STATE, &state);
 503                 if (ret)
 504                         goto err_out;
 505
 506                 adev->pm.pp_force_state_enabled = true;
 507         }
 508
 509         pm_runtime_mark_last_busy(ddev->dev);
 510         pm_runtime_put_autosuspend(ddev->dev);
 511
 512         return count;
 513
 514 err_out:
 515         pm_runtime_mark_last_busy(ddev->dev);
 516         pm_runtime_put_autosuspend(ddev->dev);
 517         return ret;
 518 }
 519
 520 /**
 521  * DOC: pp_table
 522  *
 523  * The amdgpu driver provides a sysfs API for uploading new powerplay
 524  * tables.  The file pp_table is used for this.  Reading the file
 525  * will dump the current power play table.  Writing to the file
 526  * will attempt to upload a new powerplay table and re-initialize
 527  * powerplay using that new table.
 528  *
 529  */
 530
 531 static ssize_t amdgpu_get_pp_table(struct device *dev,
 532                 struct device_attribute *attr,
 533                 char *buf)
 534 {
 535         struct drm_device *ddev = dev_get_drvdata(dev);
 536         struct amdgpu_device *adev = drm_to_adev(ddev);
 537         char *table = NULL;
 538         int size, ret;
 539
 540         if (amdgpu_in_reset(adev))
 541                 return -EPERM;
 542         if (adev->in_suspend && !adev->in_runpm)
 543                 return -EPERM;
 544
 545         ret = pm_runtime_get_sync(ddev->dev);
 546         if (ret < 0) {
 547                 pm_runtime_put_autosuspend(ddev->dev);
 548                 return ret;
 549         }
 550
 551         size = amdgpu_dpm_get_pp_table(adev, &table);
 552
 553         pm_runtime_mark_last_busy(ddev->dev);
 554         pm_runtime_put_autosuspend(ddev->dev);
 555
 556         if (size <= 0)
 557                 return size;
 558
 559         if (size >= PAGE_SIZE)
 560                 size = PAGE_SIZE - 1;
 561
 562         memcpy(buf, table, size);
 563
 564         return size;
 565 }
 566
 567 static ssize_t amdgpu_set_pp_table(struct device *dev,
 568                 struct device_attribute *attr,
 569                 const char *buf,
 570                 size_t count)
 571 {
 572         struct drm_device *ddev = dev_get_drvdata(dev);
 573         struct amdgpu_device *adev = drm_to_adev(ddev);
 574         int ret = 0;
 575
 576         if (amdgpu_in_reset(adev))
 577                 return -EPERM;
 578         if (adev->in_suspend && !adev->in_runpm)
 579                 return -EPERM;
 580
 581         ret = pm_runtime_get_sync(ddev->dev);
 582         if (ret < 0) {
 583                 pm_runtime_put_autosuspend(ddev->dev);
 584                 return ret;
 585         }
 586
 587         ret = amdgpu_dpm_set_pp_table(adev, buf, count);
 588
 589         pm_runtime_mark_last_busy(ddev->dev);
 590         pm_runtime_put_autosuspend(ddev->dev);
 591
 592         if (ret)
 593                 return ret;
 594
 595         return count;
 596 }
 597
 598 /**
 599  * DOC: pp_od_clk_voltage
 600  *
 601  * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
 602  * in each power level within a power state.  The pp_od_clk_voltage is used for
 603  * this.
 604  *
 605  * Note that the actual memory controller clock rate are exposed, not
 606  * the effective memory clock of the DRAMs. To translate it, use the
 607  * following formula:
 608  *
 609  * Clock conversion (Mhz):
 610  *
 611  * HBM: effective_memory_clock = memory_controller_clock * 1
 612  *
 613  * G5: effective_memory_clock = memory_controller_clock * 1
 614  *
 615  * G6: effective_memory_clock = memory_controller_clock * 2
 616  *
 617  * DRAM data rate (MT/s):
 618  *
 619  * HBM: effective_memory_clock * 2 = data_rate
 620  *
 621  * G5: effective_memory_clock * 4 = data_rate
 622  *
 623  * G6: effective_memory_clock * 8 = data_rate
 624  *
 625  * Bandwidth (MB/s):
 626  *
 627  * data_rate * vram_bit_width / 8 = memory_bandwidth
 628  *
 629  * Some examples:
 630  *
 631  * G5 on RX460:
 632  *
 633  * memory_controller_clock = 1750 Mhz
 634  *
 635  * effective_memory_clock = 1750 Mhz * 1 = 1750 Mhz
 636  *
 637  * data rate = 1750 * 4 = 7000 MT/s
 638  *
 639  * memory_bandwidth = 7000 * 128 bits / 8 = 112000 MB/s
 640  *
 641  * G6 on RX5700:
 642  *
 643  * memory_controller_clock = 875 Mhz
 644  *
 645  * effective_memory_clock = 875 Mhz * 2 = 1750 Mhz
 646  *
 647  * data rate = 1750 * 8 = 14000 MT/s
 648  *
 649  * memory_bandwidth = 14000 * 256 bits / 8 = 448000 MB/s
 650  *
 651  * < For Vega10 and previous ASICs >
 652  *
 653  * Reading the file will display:
 654  *
 655  * - a list of engine clock levels and voltages labeled OD_SCLK
 656  *
 657  * - a list of memory clock levels and voltages labeled OD_MCLK
 658  *
 659  * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
 660  *
 661  * To manually adjust these settings, first select manual using
 662  * power_dpm_force_performance_level. Enter a new value for each
 663  * level by writing a string that contains "s/m level clock voltage" to
 664  * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
 665  * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
 666  * 810 mV.  When you have edited all of the states as needed, write
 667  * "c" (commit) to the file to commit your changes.  If you want to reset to the
 668  * default power levels, write "r" (reset) to the file to reset them.
 669  *
 670  *
 671  * < For Vega20 and newer ASICs >
 672  *
 673  * Reading the file will display:
 674  *
 675  * - minimum and maximum engine clock labeled OD_SCLK
 676  *
 677  * - minimum(not available for Vega20 and Navi1x) and maximum memory
 678  *   clock labeled OD_MCLK
 679  *
 680  * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
 681  *   They can be used to calibrate the sclk voltage curve. This is
 682  *   available for Vega20 and NV1X.
 683  *
 684  * - voltage offset(in mV) applied on target voltage calculation.
 685  *   This is available for Sienna Cichlid, Navy Flounder, Dimgrey
 686  *   Cavefish and some later SMU13 ASICs. For these ASICs, the target
 687  *   voltage calculation can be illustrated by "voltage = voltage
 688  *   calculated from v/f curve + overdrive vddgfx offset"
 689  *
 690  * - a list of valid ranges for sclk, mclk, voltage curve points
 691  *   or voltage offset labeled OD_RANGE
 692  *
 693  * < For APUs >
 694  *
 695  * Reading the file will display:
 696  *
 697  * - minimum and maximum engine clock labeled OD_SCLK
 698  *
 699  * - a list of valid ranges for sclk labeled OD_RANGE
 700  *
 701  * < For VanGogh >
 702  *
 703  * Reading the file will display:
 704  *
 705  * - minimum and maximum engine clock labeled OD_SCLK
 706  * - minimum and maximum core clocks labeled OD_CCLK
 707  *
 708  * - a list of valid ranges for sclk and cclk labeled OD_RANGE
 709  *
 710  * To manually adjust these settings:
 711  *
 712  * - First select manual using power_dpm_force_performance_level
 713  *
 714  * - For clock frequency setting, enter a new value by writing a
 715  *   string that contains "s/m index clock" to the file. The index
 716  *   should be 0 if to set minimum clock. And 1 if to set maximum
 717  *   clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
 718  *   "m 1 800" will update maximum mclk to be 800Mhz. For core
 719  *   clocks on VanGogh, the string contains "p core index clock".
 720  *   E.g., "p 2 0 800" would set the minimum core clock on core
 721  *   2 to 800Mhz.
 722  *
 723  *   For sclk voltage curve supported by Vega20 and NV1X, enter the new
 724  *   values by writing a string that contains "vc point clock voltage"
 725  *   to the file. The points are indexed by 0, 1 and 2. E.g., "vc 0 300
 726  *   600" will update point1 with clock set as 300Mhz and voltage as 600mV.
 727  *   "vc 2 1000 1000" will update point3 with clock set as 1000Mhz and
 728  *   voltage 1000mV.
 729  *
 730  *   For voltage offset supported by Sienna Cichlid, Navy Flounder, Dimgrey
 731  *   Cavefish and some later SMU13 ASICs, enter the new value by writing a
 732  *   string that contains "vo offset". E.g., "vo -10" will update the extra
 733  *   voltage offset applied to the whole v/f curve line as -10mv.
 734  *
 735  * - When you have edited all of the states as needed, write "c" (commit)
 736  *   to the file to commit your changes
 737  *
 738  * - If you want to reset to the default power levels, write "r" (reset)
 739  *   to the file to reset them
 740  *
 741  */
 742
 743 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 744                 struct device_attribute *attr,
 745                 const char *buf,
 746                 size_t count)
 747 {
 748         struct drm_device *ddev = dev_get_drvdata(dev);
 749         struct amdgpu_device *adev = drm_to_adev(ddev);
 750         int ret;
 751         uint32_t parameter_size = 0;
 752         long parameter[64];
 753         char buf_cpy[128];
 754         char *tmp_str;
 755         char *sub_str;
 756         const char delimiter[3] = {' ', '\n', '\0'};
 757         uint32_t type;
 758
 759         if (amdgpu_in_reset(adev))
 760                 return -EPERM;
 761         if (adev->in_suspend && !adev->in_runpm)
 762                 return -EPERM;
 763
 764         if (count > 127 || count == 0)
 765                 return -EINVAL;
 766
 767         if (*buf == 's')
 768                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 769         else if (*buf == 'p')
 770                 type = PP_OD_EDIT_CCLK_VDDC_TABLE;
 771         else if (*buf == 'm')
 772                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 773         else if (*buf == 'r')
 774                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 775         else if (*buf == 'c')
 776                 type = PP_OD_COMMIT_DPM_TABLE;
 777         else if (!strncmp(buf, "vc", 2))
 778                 type = PP_OD_EDIT_VDDC_CURVE;
 779         else if (!strncmp(buf, "vo", 2))
 780                 type = PP_OD_EDIT_VDDGFX_OFFSET;
 781         else
 782                 return -EINVAL;
 783
 784         memcpy(buf_cpy, buf, count);
 785         buf_cpy[count] = 0;
 786
 787         tmp_str = buf_cpy;
 788
 789         if ((type == PP_OD_EDIT_VDDC_CURVE) ||
 790              (type == PP_OD_EDIT_VDDGFX_OFFSET))
 791                 tmp_str++;
 792         while (isspace(*++tmp_str));
 793
 794         while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
 795                 if (strlen(sub_str) == 0)
 796                         continue;
 797                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 798                 if (ret)
 799                         return -EINVAL;
 800                 parameter_size++;
 801
 802                 if (!tmp_str)
 803                         break;
 804
 805                 while (isspace(*tmp_str))
 806                         tmp_str++;
 807         }
 808
 809         ret = pm_runtime_get_sync(ddev->dev);
 810         if (ret < 0) {
 811                 pm_runtime_put_autosuspend(ddev->dev);
 812                 return ret;
 813         }
 814
 815         if (amdgpu_dpm_set_fine_grain_clk_vol(adev,
 816                                               type,
 817                                               parameter,
 818                                               parameter_size))
 819                 goto err_out;
 820
 821         if (amdgpu_dpm_odn_edit_dpm_table(adev, type,
 822                                           parameter, parameter_size))
 823                 goto err_out;
 824
 825         if (type == PP_OD_COMMIT_DPM_TABLE) {
 826                 if (amdgpu_dpm_dispatch_task(adev,
 827                                              AMD_PP_TASK_READJUST_POWER_STATE,
 828                                              NULL))
 829                         goto err_out;
 830         }
 831
 832         pm_runtime_mark_last_busy(ddev->dev);
 833         pm_runtime_put_autosuspend(ddev->dev);
 834
 835         return count;
 836
 837 err_out:
 838         pm_runtime_mark_last_busy(ddev->dev);
 839         pm_runtime_put_autosuspend(ddev->dev);
 840         return -EINVAL;
 841 }
 842
 843 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 844                 struct device_attribute *attr,
 845                 char *buf)
 846 {
 847         struct drm_device *ddev = dev_get_drvdata(dev);
 848         struct amdgpu_device *adev = drm_to_adev(ddev);
 849         int size = 0;
 850         int ret;
 851         enum pp_clock_type od_clocks[6] = {
 852                 OD_SCLK,
 853                 OD_MCLK,
 854                 OD_VDDC_CURVE,
 855                 OD_RANGE,
 856                 OD_VDDGFX_OFFSET,
 857                 OD_CCLK,
 858         };
 859         uint clk_index;
 860
 861         if (amdgpu_in_reset(adev))
 862                 return -EPERM;
 863         if (adev->in_suspend && !adev->in_runpm)
 864                 return -EPERM;
 865
 866         ret = pm_runtime_get_sync(ddev->dev);
 867         if (ret < 0) {
 868                 pm_runtime_put_autosuspend(ddev->dev);
 869                 return ret;
 870         }
 871
 872         for (clk_index = 0 ; clk_index < 6 ; clk_index++) {
 873                 ret = amdgpu_dpm_emit_clock_levels(adev, od_clocks[clk_index], buf, &size);
 874                 if (ret)
 875                         break;
 876         }
 877         if (ret == -ENOENT) {
 878                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 879                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf + size);
 880                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf + size);
 881                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf + size);
 882                 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf + size);
 883                 size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf + size);
 884         }
 885
 886         if (size == 0)
 887                 size = sysfs_emit(buf, "\n");
 888
 889         pm_runtime_mark_last_busy(ddev->dev);
 890         pm_runtime_put_autosuspend(ddev->dev);
 891
 892         return size;
 893 }
 894
 895 /**
 896  * DOC: pp_features
 897  *
 898  * The amdgpu driver provides a sysfs API for adjusting what powerplay
 899  * features to be enabled. The file pp_features is used for this. And
 900  * this is only available for Vega10 and later dGPUs.
 901  *
 902  * Reading back the file will show you the followings:
 903  * - Current ppfeature masks
 904  * - List of the all supported powerplay features with their naming,
 905  *   bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
 906  *
 907  * To manually enable or disable a specific feature, just set or clear
 908  * the corresponding bit from original ppfeature masks and input the
 909  * new ppfeature masks.
 910  */
 911 static ssize_t amdgpu_set_pp_features(struct device *dev,
 912                                       struct device_attribute *attr,
 913                                       const char *buf,
 914                                       size_t count)
 915 {
 916         struct drm_device *ddev = dev_get_drvdata(dev);
 917         struct amdgpu_device *adev = drm_to_adev(ddev);
 918         uint64_t featuremask;
 919         int ret;
 920
 921         if (amdgpu_in_reset(adev))
 922                 return -EPERM;
 923         if (adev->in_suspend && !adev->in_runpm)
 924                 return -EPERM;
 925
 926         ret = kstrtou64(buf, 0, &featuremask);
 927         if (ret)
 928                 return -EINVAL;
 929
 930         ret = pm_runtime_get_sync(ddev->dev);
 931         if (ret < 0) {
 932                 pm_runtime_put_autosuspend(ddev->dev);
 933                 return ret;
 934         }
 935
 936         ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
 937
 938         pm_runtime_mark_last_busy(ddev->dev);
 939         pm_runtime_put_autosuspend(ddev->dev);
 940
 941         if (ret)
 942                 return -EINVAL;
 943
 944         return count;
 945 }
 946
 947 static ssize_t amdgpu_get_pp_features(struct device *dev,
 948                                       struct device_attribute *attr,
 949                                       char *buf)
 950 {
 951         struct drm_device *ddev = dev_get_drvdata(dev);
 952         struct amdgpu_device *adev = drm_to_adev(ddev);
 953         ssize_t size;
 954         int ret;
 955
 956         if (amdgpu_in_reset(adev))
 957                 return -EPERM;
 958         if (adev->in_suspend && !adev->in_runpm)
 959                 return -EPERM;
 960
 961         ret = pm_runtime_get_sync(ddev->dev);
 962         if (ret < 0) {
 963                 pm_runtime_put_autosuspend(ddev->dev);
 964                 return ret;
 965         }
 966
 967         size = amdgpu_dpm_get_ppfeature_status(adev, buf);
 968         if (size <= 0)
 969                 size = sysfs_emit(buf, "\n");
 970
 971         pm_runtime_mark_last_busy(ddev->dev);
 972         pm_runtime_put_autosuspend(ddev->dev);
 973
 974         return size;
 975 }
 976
 977 /**
 978  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie
 979  *
 980  * The amdgpu driver provides a sysfs API for adjusting what power levels
 981  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
 982  * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
 983  * this.
 984  *
 985  * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
 986  * Vega10 and later ASICs.
 987  * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
 988  *
 989  * Reading back the files will show you the available power levels within
 990  * the power state and the clock information for those levels. If deep sleep is
 991  * applied to a clock, the level will be denoted by a special level 'S:'
 992  * E.g., ::
 993  *
 994  *  S: 19Mhz *
 995  *  0: 615Mhz
 996  *  1: 800Mhz
 997  *  2: 888Mhz
 998  *  3: 1000Mhz
 999  *
1000  *
1001  * To manually adjust these states, first select manual using
1002  * power_dpm_force_performance_level.
1003  * Secondly, enter a new value for each level by inputing a string that
1004  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
1005  * E.g.,
1006  *
1007  * .. code-block:: bash
1008  *
1009  *      echo "4 5 6" > pp_dpm_sclk
1010  *
1011  * will enable sclk levels 4, 5, and 6.
1012  *
1013  * NOTE: change to the dcefclk max dpm level is not supported now
1014  */
1015
1016 static ssize_t amdgpu_get_pp_dpm_clock(struct device *dev,
1017                 enum pp_clock_type type,
1018                 char *buf)
1019 {
1020         struct drm_device *ddev = dev_get_drvdata(dev);
1021         struct amdgpu_device *adev = drm_to_adev(ddev);
1022         int size = 0;
1023         int ret = 0;
1024
1025         if (amdgpu_in_reset(adev))
1026                 return -EPERM;
1027         if (adev->in_suspend && !adev->in_runpm)
1028                 return -EPERM;
1029
1030         ret = pm_runtime_get_sync(ddev->dev);
1031         if (ret < 0) {
1032                 pm_runtime_put_autosuspend(ddev->dev);
1033                 return ret;
1034         }
1035
1036         ret = amdgpu_dpm_emit_clock_levels(adev, type, buf, &size);
1037         if (ret == -ENOENT)
1038                 size = amdgpu_dpm_print_clock_levels(adev, type, buf);
1039
1040         if (size == 0)
1041                 size = sysfs_emit(buf, "\n");
1042
1043         pm_runtime_mark_last_busy(ddev->dev);
1044         pm_runtime_put_autosuspend(ddev->dev);
1045
1046         return size;
1047 }
1048
1049 /*
1050  * Worst case: 32 bits individually specified, in octal at 12 characters
1051  * per line (+1 for \n).
1052  */
1053 #define AMDGPU_MASK_BUF_MAX     (32 * 13)
1054
1055 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
1056 {
1057         int ret;
1058         unsigned long level;
1059         char *sub_str = NULL;
1060         char *tmp;
1061         char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
1062         const char delimiter[3] = {' ', '\n', '\0'};
1063         size_t bytes;
1064
1065         *mask = 0;
1066
1067         bytes = min(count, sizeof(buf_cpy) - 1);
1068         memcpy(buf_cpy, buf, bytes);
1069         buf_cpy[bytes] = '\0';
1070         tmp = buf_cpy;
1071         while ((sub_str = strsep(&tmp, delimiter)) != NULL) {
1072                 if (strlen(sub_str)) {
1073                         ret = kstrtoul(sub_str, 0, &level);
1074                         if (ret || level > 31)
1075                                 return -EINVAL;
1076                         *mask |= 1 << level;
1077                 } else
1078                         break;
1079         }
1080
1081         return 0;
1082 }
1083
1084 static ssize_t amdgpu_set_pp_dpm_clock(struct device *dev,
1085                 enum pp_clock_type type,
1086                 const char *buf,
1087                 size_t count)
1088 {
1089         struct drm_device *ddev = dev_get_drvdata(dev);
1090         struct amdgpu_device *adev = drm_to_adev(ddev);
1091         int ret;
1092         uint32_t mask = 0;
1093
1094         if (amdgpu_in_reset(adev))
1095                 return -EPERM;
1096         if (adev->in_suspend && !adev->in_runpm)
1097                 return -EPERM;
1098
1099         ret = amdgpu_read_mask(buf, count, &mask);
1100         if (ret)
1101                 return ret;
1102
1103         ret = pm_runtime_get_sync(ddev->dev);
1104         if (ret < 0) {
1105                 pm_runtime_put_autosuspend(ddev->dev);
1106                 return ret;
1107         }
1108
1109         ret = amdgpu_dpm_force_clock_level(adev, type, mask);
1110
1111         pm_runtime_mark_last_busy(ddev->dev);
1112         pm_runtime_put_autosuspend(ddev->dev);
1113
1114         if (ret)
1115                 return -EINVAL;
1116
1117         return count;
1118 }
1119
1120 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
1121                 struct device_attribute *attr,
1122                 char *buf)
1123 {
1124         return amdgpu_get_pp_dpm_clock(dev, PP_SCLK, buf);
1125 }
1126
1127 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
1128                 struct device_attribute *attr,
1129                 const char *buf,
1130                 size_t count)
1131 {
1132         return amdgpu_set_pp_dpm_clock(dev, PP_SCLK, buf, count);
1133 }
1134
1135 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
1136                 struct device_attribute *attr,
1137                 char *buf)
1138 {
1139         return amdgpu_get_pp_dpm_clock(dev, PP_MCLK, buf);
1140 }
1141
1142 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
1143                 struct device_attribute *attr,
1144                 const char *buf,
1145                 size_t count)
1146 {
1147         return amdgpu_set_pp_dpm_clock(dev, PP_MCLK, buf, count);
1148 }
1149
1150 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
1151                 struct device_attribute *attr,
1152                 char *buf)
1153 {
1154         return amdgpu_get_pp_dpm_clock(dev, PP_SOCCLK, buf);
1155 }
1156
1157 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
1158                 struct device_attribute *attr,
1159                 const char *buf,
1160                 size_t count)
1161 {
1162         return amdgpu_set_pp_dpm_clock(dev, PP_SOCCLK, buf, count);
1163 }
1164
1165 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
1166                 struct device_attribute *attr,
1167                 char *buf)
1168 {
1169         return amdgpu_get_pp_dpm_clock(dev, PP_FCLK, buf);
1170 }
1171
1172 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
1173                 struct device_attribute *attr,
1174                 const char *buf,
1175                 size_t count)
1176 {
1177         return amdgpu_set_pp_dpm_clock(dev, PP_FCLK, buf, count);
1178 }
1179
1180 static ssize_t amdgpu_get_pp_dpm_vclk(struct device *dev,
1181                 struct device_attribute *attr,
1182                 char *buf)
1183 {
1184         return amdgpu_get_pp_dpm_clock(dev, PP_VCLK, buf);
1185 }
1186
1187 static ssize_t amdgpu_set_pp_dpm_vclk(struct device *dev,
1188                 struct device_attribute *attr,
1189                 const char *buf,
1190                 size_t count)
1191 {
1192         return amdgpu_set_pp_dpm_clock(dev, PP_VCLK, buf, count);
1193 }
1194
1195 static ssize_t amdgpu_get_pp_dpm_vclk1(struct device *dev,
1196                 struct device_attribute *attr,
1197                 char *buf)
1198 {
1199         return amdgpu_get_pp_dpm_clock(dev, PP_VCLK1, buf);
1200 }
1201
1202 static ssize_t amdgpu_set_pp_dpm_vclk1(struct device *dev,
1203                 struct device_attribute *attr,
1204                 const char *buf,
1205                 size_t count)
1206 {
1207         return amdgpu_set_pp_dpm_clock(dev, PP_VCLK1, buf, count);
1208 }
1209
1210 static ssize_t amdgpu_get_pp_dpm_dclk(struct device *dev,
1211                 struct device_attribute *attr,
1212                 char *buf)
1213 {
1214         return amdgpu_get_pp_dpm_clock(dev, PP_DCLK, buf);
1215 }
1216
1217 static ssize_t amdgpu_set_pp_dpm_dclk(struct device *dev,
1218                 struct device_attribute *attr,
1219                 const char *buf,
1220                 size_t count)
1221 {
1222         return amdgpu_set_pp_dpm_clock(dev, PP_DCLK, buf, count);
1223 }
1224
1225 static ssize_t amdgpu_get_pp_dpm_dclk1(struct device *dev,
1226                 struct device_attribute *attr,
1227                 char *buf)
1228 {
1229         return amdgpu_get_pp_dpm_clock(dev, PP_DCLK1, buf);
1230 }
1231
1232 static ssize_t amdgpu_set_pp_dpm_dclk1(struct device *dev,
1233                 struct device_attribute *attr,
1234                 const char *buf,
1235                 size_t count)
1236 {
1237         return amdgpu_set_pp_dpm_clock(dev, PP_DCLK1, buf, count);
1238 }
1239
1240 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
1241                 struct device_attribute *attr,
1242                 char *buf)
1243 {
1244         return amdgpu_get_pp_dpm_clock(dev, PP_DCEFCLK, buf);
1245 }
1246
1247 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
1248                 struct device_attribute *attr,
1249                 const char *buf,
1250                 size_t count)
1251 {
1252         return amdgpu_set_pp_dpm_clock(dev, PP_DCEFCLK, buf, count);
1253 }
1254
1255 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
1256                 struct device_attribute *attr,
1257                 char *buf)
1258 {
1259         return amdgpu_get_pp_dpm_clock(dev, PP_PCIE, buf);
1260 }
1261
1262 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
1263                 struct device_attribute *attr,
1264                 const char *buf,
1265                 size_t count)
1266 {
1267         return amdgpu_set_pp_dpm_clock(dev, PP_PCIE, buf, count);
1268 }
1269
1270 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
1271                 struct device_attribute *attr,
1272                 char *buf)
1273 {
1274         struct drm_device *ddev = dev_get_drvdata(dev);
1275         struct amdgpu_device *adev = drm_to_adev(ddev);
1276         uint32_t value = 0;
1277         int ret;
1278
1279         if (amdgpu_in_reset(adev))
1280                 return -EPERM;
1281         if (adev->in_suspend && !adev->in_runpm)
1282                 return -EPERM;
1283
1284         ret = pm_runtime_get_sync(ddev->dev);
1285         if (ret < 0) {
1286                 pm_runtime_put_autosuspend(ddev->dev);
1287                 return ret;
1288         }
1289
1290         value = amdgpu_dpm_get_sclk_od(adev);
1291
1292         pm_runtime_mark_last_busy(ddev->dev);
1293         pm_runtime_put_autosuspend(ddev->dev);
1294
1295         return sysfs_emit(buf, "%d\n", value);
1296 }
1297
1298 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
1299                 struct device_attribute *attr,
1300                 const char *buf,
1301                 size_t count)
1302 {
1303         struct drm_device *ddev = dev_get_drvdata(dev);
1304         struct amdgpu_device *adev = drm_to_adev(ddev);
1305         int ret;
1306         long int value;
1307
1308         if (amdgpu_in_reset(adev))
1309                 return -EPERM;
1310         if (adev->in_suspend && !adev->in_runpm)
1311                 return -EPERM;
1312
1313         ret = kstrtol(buf, 0, &value);
1314
1315         if (ret)
1316                 return -EINVAL;
1317
1318         ret = pm_runtime_get_sync(ddev->dev);
1319         if (ret < 0) {
1320                 pm_runtime_put_autosuspend(ddev->dev);
1321                 return ret;
1322         }
1323
1324         amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
1325
1326         pm_runtime_mark_last_busy(ddev->dev);
1327         pm_runtime_put_autosuspend(ddev->dev);
1328
1329         return count;
1330 }
1331
1332 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
1333                 struct device_attribute *attr,
1334                 char *buf)
1335 {
1336         struct drm_device *ddev = dev_get_drvdata(dev);
1337         struct amdgpu_device *adev = drm_to_adev(ddev);
1338         uint32_t value = 0;
1339         int ret;
1340
1341         if (amdgpu_in_reset(adev))
1342                 return -EPERM;
1343         if (adev->in_suspend && !adev->in_runpm)
1344                 return -EPERM;
1345
1346         ret = pm_runtime_get_sync(ddev->dev);
1347         if (ret < 0) {
1348                 pm_runtime_put_autosuspend(ddev->dev);
1349                 return ret;
1350         }
1351
1352         value = amdgpu_dpm_get_mclk_od(adev);
1353
1354         pm_runtime_mark_last_busy(ddev->dev);
1355         pm_runtime_put_autosuspend(ddev->dev);
1356
1357         return sysfs_emit(buf, "%d\n", value);
1358 }
1359
1360 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
1361                 struct device_attribute *attr,
1362                 const char *buf,
1363                 size_t count)
1364 {
1365         struct drm_device *ddev = dev_get_drvdata(dev);
1366         struct amdgpu_device *adev = drm_to_adev(ddev);
1367         int ret;
1368         long int value;
1369
1370         if (amdgpu_in_reset(adev))
1371                 return -EPERM;
1372         if (adev->in_suspend && !adev->in_runpm)
1373                 return -EPERM;
1374
1375         ret = kstrtol(buf, 0, &value);
1376
1377         if (ret)
1378                 return -EINVAL;
1379
1380         ret = pm_runtime_get_sync(ddev->dev);
1381         if (ret < 0) {
1382                 pm_runtime_put_autosuspend(ddev->dev);
1383                 return ret;
1384         }
1385
1386         amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
1387
1388         pm_runtime_mark_last_busy(ddev->dev);
1389         pm_runtime_put_autosuspend(ddev->dev);
1390
1391         return count;
1392 }
1393
1394 /**
1395  * DOC: pp_power_profile_mode
1396  *
1397  * The amdgpu driver provides a sysfs API for adjusting the heuristics
1398  * related to switching between power levels in a power state.  The file
1399  * pp_power_profile_mode is used for this.
1400  *
1401  * Reading this file outputs a list of all of the predefined power profiles
1402  * and the relevant heuristics settings for that profile.
1403  *
1404  * To select a profile or create a custom profile, first select manual using
1405  * power_dpm_force_performance_level.  Writing the number of a predefined
1406  * profile to pp_power_profile_mode will enable those heuristics.  To
1407  * create a custom set of heuristics, write a string of numbers to the file
1408  * starting with the number of the custom profile along with a setting
1409  * for each heuristic parameter.  Due to differences across asic families
1410  * the heuristic parameters vary from family to family.
1411  *
1412  */
1413
1414 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
1415                 struct device_attribute *attr,
1416                 char *buf)
1417 {
1418         struct drm_device *ddev = dev_get_drvdata(dev);
1419         struct amdgpu_device *adev = drm_to_adev(ddev);
1420         ssize_t size;
1421         int ret;
1422
1423         if (amdgpu_in_reset(adev))
1424                 return -EPERM;
1425         if (adev->in_suspend && !adev->in_runpm)
1426                 return -EPERM;
1427
1428         ret = pm_runtime_get_sync(ddev->dev);
1429         if (ret < 0) {
1430                 pm_runtime_put_autosuspend(ddev->dev);
1431                 return ret;
1432         }
1433
1434         size = amdgpu_dpm_get_power_profile_mode(adev, buf);
1435         if (size <= 0)
1436                 size = sysfs_emit(buf, "\n");
1437
1438         pm_runtime_mark_last_busy(ddev->dev);
1439         pm_runtime_put_autosuspend(ddev->dev);
1440
1441         return size;
1442 }
1443
1444
1445 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
1446                 struct device_attribute *attr,
1447                 const char *buf,
1448                 size_t count)
1449 {
1450         int ret;
1451         struct drm_device *ddev = dev_get_drvdata(dev);
1452         struct amdgpu_device *adev = drm_to_adev(ddev);
1453         uint32_t parameter_size = 0;
1454         long parameter[64];
1455         char *sub_str, buf_cpy[128];
1456         char *tmp_str;
1457         uint32_t i = 0;
1458         char tmp[2];
1459         long int profile_mode = 0;
1460         const char delimiter[3] = {' ', '\n', '\0'};
1461
1462         if (amdgpu_in_reset(adev))
1463                 return -EPERM;
1464         if (adev->in_suspend && !adev->in_runpm)
1465                 return -EPERM;
1466
1467         tmp[0] = *(buf);
1468         tmp[1] = '\0';
1469         ret = kstrtol(tmp, 0, &profile_mode);
1470         if (ret)
1471                 return -EINVAL;
1472
1473         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1474                 if (count < 2 || count > 127)
1475                         return -EINVAL;
1476                 while (isspace(*++buf))
1477                         i++;
1478                 memcpy(buf_cpy, buf, count-i);
1479                 tmp_str = buf_cpy;
1480                 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
1481                         if (strlen(sub_str) == 0)
1482                                 continue;
1483                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
1484                         if (ret)
1485                                 return -EINVAL;
1486                         parameter_size++;
1487                         while (isspace(*tmp_str))
1488                                 tmp_str++;
1489                 }
1490         }
1491         parameter[parameter_size] = profile_mode;
1492
1493         ret = pm_runtime_get_sync(ddev->dev);
1494         if (ret < 0) {
1495                 pm_runtime_put_autosuspend(ddev->dev);
1496                 return ret;
1497         }
1498
1499         ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
1500
1501         pm_runtime_mark_last_busy(ddev->dev);
1502         pm_runtime_put_autosuspend(ddev->dev);
1503
1504         if (!ret)
1505                 return count;
1506
1507         return -EINVAL;
1508 }
1509
1510 static int amdgpu_hwmon_get_sensor_generic(struct amdgpu_device *adev,
1511                                            enum amd_pp_sensors sensor,
1512                                            void *query)
1513 {
1514         int r, size = sizeof(uint32_t);
1515
1516         if (amdgpu_in_reset(adev))
1517                 return -EPERM;
1518         if (adev->in_suspend && !adev->in_runpm)
1519                 return -EPERM;
1520
1521         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1522         if (r < 0) {
1523                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1524                 return r;
1525         }
1526
1527         /* get the sensor value */
1528         r = amdgpu_dpm_read_sensor(adev, sensor, query, &size);
1529
1530         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1531         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1532
1533         return r;
1534 }
1535
1536 /**
1537  * DOC: gpu_busy_percent
1538  *
1539  * The amdgpu driver provides a sysfs API for reading how busy the GPU
1540  * is as a percentage.  The file gpu_busy_percent is used for this.
1541  * The SMU firmware computes a percentage of load based on the
1542  * aggregate activity level in the IP cores.
1543  */
1544 static ssize_t amdgpu_get_gpu_busy_percent(struct device *dev,
1545                                            struct device_attribute *attr,
1546                                            char *buf)
1547 {
1548         struct drm_device *ddev = dev_get_drvdata(dev);
1549         struct amdgpu_device *adev = drm_to_adev(ddev);
1550         unsigned int value;
1551         int r;
1552
1553         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_LOAD, &value);
1554         if (r)
1555                 return r;
1556
1557         return sysfs_emit(buf, "%d\n", value);
1558 }
1559
1560 /**
1561  * DOC: mem_busy_percent
1562  *
1563  * The amdgpu driver provides a sysfs API for reading how busy the VRAM
1564  * is as a percentage.  The file mem_busy_percent is used for this.
1565  * The SMU firmware computes a percentage of load based on the
1566  * aggregate activity level in the IP cores.
1567  */
1568 static ssize_t amdgpu_get_mem_busy_percent(struct device *dev,
1569                                            struct device_attribute *attr,
1570                                            char *buf)
1571 {
1572         struct drm_device *ddev = dev_get_drvdata(dev);
1573         struct amdgpu_device *adev = drm_to_adev(ddev);
1574         unsigned int value;
1575         int r;
1576
1577         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MEM_LOAD, &value);
1578         if (r)
1579                 return r;
1580
1581         return sysfs_emit(buf, "%d\n", value);
1582 }
1583
1584 /**
1585  * DOC: pcie_bw
1586  *
1587  * The amdgpu driver provides a sysfs API for estimating how much data
1588  * has been received and sent by the GPU in the last second through PCIe.
1589  * The file pcie_bw is used for this.
1590  * The Perf counters count the number of received and sent messages and return
1591  * those values, as well as the maximum payload size of a PCIe packet (mps).
1592  * Note that it is not possible to easily and quickly obtain the size of each
1593  * packet transmitted, so we output the max payload size (mps) to allow for
1594  * quick estimation of the PCIe bandwidth usage
1595  */
1596 static ssize_t amdgpu_get_pcie_bw(struct device *dev,
1597                 struct device_attribute *attr,
1598                 char *buf)
1599 {
1600         struct drm_device *ddev = dev_get_drvdata(dev);
1601         struct amdgpu_device *adev = drm_to_adev(ddev);
1602         uint64_t count0 = 0, count1 = 0;
1603         int ret;
1604
1605         if (amdgpu_in_reset(adev))
1606                 return -EPERM;
1607         if (adev->in_suspend && !adev->in_runpm)
1608                 return -EPERM;
1609
1610         if (adev->flags & AMD_IS_APU)
1611                 return -ENODATA;
1612
1613         if (!adev->asic_funcs->get_pcie_usage)
1614                 return -ENODATA;
1615
1616         ret = pm_runtime_get_sync(ddev->dev);
1617         if (ret < 0) {
1618                 pm_runtime_put_autosuspend(ddev->dev);
1619                 return ret;
1620         }
1621
1622         amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
1623
1624         pm_runtime_mark_last_busy(ddev->dev);
1625         pm_runtime_put_autosuspend(ddev->dev);
1626
1627         return sysfs_emit(buf, "%llu %llu %i\n",
1628                           count0, count1, pcie_get_mps(adev->pdev));
1629 }
1630
1631 /**
1632  * DOC: unique_id
1633  *
1634  * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU
1635  * The file unique_id is used for this.
1636  * This will provide a Unique ID that will persist from machine to machine
1637  *
1638  * NOTE: This will only work for GFX9 and newer. This file will be absent
1639  * on unsupported ASICs (GFX8 and older)
1640  */
1641 static ssize_t amdgpu_get_unique_id(struct device *dev,
1642                 struct device_attribute *attr,
1643                 char *buf)
1644 {
1645         struct drm_device *ddev = dev_get_drvdata(dev);
1646         struct amdgpu_device *adev = drm_to_adev(ddev);
1647
1648         if (amdgpu_in_reset(adev))
1649                 return -EPERM;
1650         if (adev->in_suspend && !adev->in_runpm)
1651                 return -EPERM;
1652
1653         if (adev->unique_id)
1654                 return sysfs_emit(buf, "%016llx\n", adev->unique_id);
1655
1656         return 0;
1657 }
1658
1659 /**
1660  * DOC: thermal_throttling_logging
1661  *
1662  * Thermal throttling pulls down the clock frequency and thus the performance.
1663  * It's an useful mechanism to protect the chip from overheating. Since it
1664  * impacts performance, the user controls whether it is enabled and if so,
1665  * the log frequency.
1666  *
1667  * Reading back the file shows you the status(enabled or disabled) and
1668  * the interval(in seconds) between each thermal logging.
1669  *
1670  * Writing an integer to the file, sets a new logging interval, in seconds.
1671  * The value should be between 1 and 3600. If the value is less than 1,
1672  * thermal logging is disabled. Values greater than 3600 are ignored.
1673  */
1674 static ssize_t amdgpu_get_thermal_throttling_logging(struct device *dev,
1675                                                      struct device_attribute *attr,
1676                                                      char *buf)
1677 {
1678         struct drm_device *ddev = dev_get_drvdata(dev);
1679         struct amdgpu_device *adev = drm_to_adev(ddev);
1680
1681         return sysfs_emit(buf, "%s: thermal throttling logging %s, with interval %d seconds\n",
1682                           adev_to_drm(adev)->unique,
1683                           atomic_read(&adev->throttling_logging_enabled) ? "enabled" : "disabled",
1684                           adev->throttling_logging_rs.interval / HZ + 1);
1685 }
1686
1687 static ssize_t amdgpu_set_thermal_throttling_logging(struct device *dev,
1688                                                      struct device_attribute *attr,
1689                                                      const char *buf,
1690                                                      size_t count)
1691 {
1692         struct drm_device *ddev = dev_get_drvdata(dev);
1693         struct amdgpu_device *adev = drm_to_adev(ddev);
1694         long throttling_logging_interval;
1695         unsigned long flags;
1696         int ret = 0;
1697
1698         ret = kstrtol(buf, 0, &throttling_logging_interval);
1699         if (ret)
1700                 return ret;
1701
1702         if (throttling_logging_interval > 3600)
1703                 return -EINVAL;
1704
1705         if (throttling_logging_interval > 0) {
1706                 raw_spin_lock_irqsave(&adev->throttling_logging_rs.lock, flags);
1707                 /*
1708                  * Reset the ratelimit timer internals.
1709                  * This can effectively restart the timer.
1710                  */
1711                 adev->throttling_logging_rs.interval =
1712                         (throttling_logging_interval - 1) * HZ;
1713                 adev->throttling_logging_rs.begin = 0;
1714                 adev->throttling_logging_rs.printed = 0;
1715                 adev->throttling_logging_rs.missed = 0;
1716                 raw_spin_unlock_irqrestore(&adev->throttling_logging_rs.lock, flags);
1717
1718                 atomic_set(&adev->throttling_logging_enabled, 1);
1719         } else {
1720                 atomic_set(&adev->throttling_logging_enabled, 0);
1721         }
1722
1723         return count;
1724 }
1725
1726 /**
1727  * DOC: apu_thermal_cap
1728  *
1729  * The amdgpu driver provides a sysfs API for retrieving/updating thermal
1730  * limit temperature in millidegrees Celsius
1731  *
1732  * Reading back the file shows you core limit value
1733  *
1734  * Writing an integer to the file, sets a new thermal limit. The value
1735  * should be between 0 and 100. If the value is less than 0 or greater
1736  * than 100, then the write request will be ignored.
1737  */
1738 static ssize_t amdgpu_get_apu_thermal_cap(struct device *dev,
1739                                          struct device_attribute *attr,
1740                                          char *buf)
1741 {
1742         int ret, size;
1743         u32 limit;
1744         struct drm_device *ddev = dev_get_drvdata(dev);
1745         struct amdgpu_device *adev = drm_to_adev(ddev);
1746
1747         ret = pm_runtime_get_sync(ddev->dev);
1748         if (ret < 0) {
1749                 pm_runtime_put_autosuspend(ddev->dev);
1750                 return ret;
1751         }
1752
1753         ret = amdgpu_dpm_get_apu_thermal_limit(adev, &limit);
1754         if (!ret)
1755                 size = sysfs_emit(buf, "%u\n", limit);
1756         else
1757                 size = sysfs_emit(buf, "failed to get thermal limit\n");
1758
1759         pm_runtime_mark_last_busy(ddev->dev);
1760         pm_runtime_put_autosuspend(ddev->dev);
1761
1762         return size;
1763 }
1764
1765 static ssize_t amdgpu_set_apu_thermal_cap(struct device *dev,
1766                                          struct device_attribute *attr,
1767                                          const char *buf,
1768                                          size_t count)
1769 {
1770         int ret;
1771         u32 value;
1772         struct drm_device *ddev = dev_get_drvdata(dev);
1773         struct amdgpu_device *adev = drm_to_adev(ddev);
1774
1775         ret = kstrtou32(buf, 10, &value);
1776         if (ret)
1777                 return ret;
1778
1779         if (value > 100) {
1780                 dev_err(dev, "Invalid argument !\n");
1781                 return -EINVAL;
1782         }
1783
1784         ret = pm_runtime_get_sync(ddev->dev);
1785         if (ret < 0) {
1786                 pm_runtime_put_autosuspend(ddev->dev);
1787                 return ret;
1788         }
1789
1790         ret = amdgpu_dpm_set_apu_thermal_limit(adev, value);
1791         if (ret) {
1792                 dev_err(dev, "failed to update thermal limit\n");
1793                 return ret;
1794         }
1795
1796         pm_runtime_mark_last_busy(ddev->dev);
1797         pm_runtime_put_autosuspend(ddev->dev);
1798
1799         return count;
1800 }
1801
1802 static int amdgpu_pm_metrics_attr_update(struct amdgpu_device *adev,
1803                                          struct amdgpu_device_attr *attr,
1804                                          uint32_t mask,
1805                                          enum amdgpu_device_attr_states *states)
1806 {
1807         if (amdgpu_dpm_get_pm_metrics(adev, NULL, 0) == -EOPNOTSUPP)
1808                 *states = ATTR_STATE_UNSUPPORTED;
1809
1810         return 0;
1811 }
1812
1813 static ssize_t amdgpu_get_pm_metrics(struct device *dev,
1814                                      struct device_attribute *attr, char *buf)
1815 {
1816         struct drm_device *ddev = dev_get_drvdata(dev);
1817         struct amdgpu_device *adev = drm_to_adev(ddev);
1818         ssize_t size = 0;
1819         int ret;
1820
1821         if (amdgpu_in_reset(adev))
1822                 return -EPERM;
1823         if (adev->in_suspend && !adev->in_runpm)
1824                 return -EPERM;
1825
1826         ret = pm_runtime_get_sync(ddev->dev);
1827         if (ret < 0) {
1828                 pm_runtime_put_autosuspend(ddev->dev);
1829                 return ret;
1830         }
1831
1832         size = amdgpu_dpm_get_pm_metrics(adev, buf, PAGE_SIZE);
1833
1834         pm_runtime_mark_last_busy(ddev->dev);
1835         pm_runtime_put_autosuspend(ddev->dev);
1836
1837         return size;
1838 }
1839
1840 /**
1841  * DOC: gpu_metrics
1842  *
1843  * The amdgpu driver provides a sysfs API for retrieving current gpu
1844  * metrics data. The file gpu_metrics is used for this. Reading the
1845  * file will dump all the current gpu metrics data.
1846  *
1847  * These data include temperature, frequency, engines utilization,
1848  * power consume, throttler status, fan speed and cpu core statistics(
1849  * available for APU only). That's it will give a snapshot of all sensors
1850  * at the same time.
1851  */
1852 static ssize_t amdgpu_get_gpu_metrics(struct device *dev,
1853                                       struct device_attribute *attr,
1854                                       char *buf)
1855 {
1856         struct drm_device *ddev = dev_get_drvdata(dev);
1857         struct amdgpu_device *adev = drm_to_adev(ddev);
1858         void *gpu_metrics;
1859         ssize_t size = 0;
1860         int ret;
1861
1862         if (amdgpu_in_reset(adev))
1863                 return -EPERM;
1864         if (adev->in_suspend && !adev->in_runpm)
1865                 return -EPERM;
1866
1867         ret = pm_runtime_get_sync(ddev->dev);
1868         if (ret < 0) {
1869                 pm_runtime_put_autosuspend(ddev->dev);
1870                 return ret;
1871         }
1872
1873         size = amdgpu_dpm_get_gpu_metrics(adev, &gpu_metrics);
1874         if (size <= 0)
1875                 goto out;
1876
1877         if (size >= PAGE_SIZE)
1878                 size = PAGE_SIZE - 1;
1879
1880         memcpy(buf, gpu_metrics, size);
1881
1882 out:
1883         pm_runtime_mark_last_busy(ddev->dev);
1884         pm_runtime_put_autosuspend(ddev->dev);
1885
1886         return size;
1887 }
1888
1889 static int amdgpu_show_powershift_percent(struct device *dev,
1890                                         char *buf, enum amd_pp_sensors sensor)
1891 {
1892         struct drm_device *ddev = dev_get_drvdata(dev);
1893         struct amdgpu_device *adev = drm_to_adev(ddev);
1894         uint32_t ss_power;
1895         int r = 0, i;
1896
1897         r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&ss_power);
1898         if (r == -EOPNOTSUPP) {
1899                 /* sensor not available on dGPU, try to read from APU */
1900                 adev = NULL;
1901                 mutex_lock(&mgpu_info.mutex);
1902                 for (i = 0; i < mgpu_info.num_gpu; i++) {
1903                         if (mgpu_info.gpu_ins[i].adev->flags & AMD_IS_APU) {
1904                                 adev = mgpu_info.gpu_ins[i].adev;
1905                                 break;
1906                         }
1907                 }
1908                 mutex_unlock(&mgpu_info.mutex);
1909                 if (adev)
1910                         r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&ss_power);
1911         }
1912
1913         if (r)
1914                 return r;
1915
1916         return sysfs_emit(buf, "%u%%\n", ss_power);
1917 }
1918
1919 /**
1920  * DOC: smartshift_apu_power
1921  *
1922  * The amdgpu driver provides a sysfs API for reporting APU power
1923  * shift in percentage if platform supports smartshift. Value 0 means that
1924  * there is no powershift and values between [1-100] means that the power
1925  * is shifted to APU, the percentage of boost is with respect to APU power
1926  * limit on the platform.
1927  */
1928
1929 static ssize_t amdgpu_get_smartshift_apu_power(struct device *dev, struct device_attribute *attr,
1930                                                char *buf)
1931 {
1932         return amdgpu_show_powershift_percent(dev, buf, AMDGPU_PP_SENSOR_SS_APU_SHARE);
1933 }
1934
1935 /**
1936  * DOC: smartshift_dgpu_power
1937  *
1938  * The amdgpu driver provides a sysfs API for reporting dGPU power
1939  * shift in percentage if platform supports smartshift. Value 0 means that
1940  * there is no powershift and values between [1-100] means that the power is
1941  * shifted to dGPU, the percentage of boost is with respect to dGPU power
1942  * limit on the platform.
1943  */
1944
1945 static ssize_t amdgpu_get_smartshift_dgpu_power(struct device *dev, struct device_attribute *attr,
1946                                                 char *buf)
1947 {
1948         return amdgpu_show_powershift_percent(dev, buf, AMDGPU_PP_SENSOR_SS_DGPU_SHARE);
1949 }
1950
1951 /**
1952  * DOC: smartshift_bias
1953  *
1954  * The amdgpu driver provides a sysfs API for reporting the
1955  * smartshift(SS2.0) bias level. The value ranges from -100 to 100
1956  * and the default is 0. -100 sets maximum preference to APU
1957  * and 100 sets max perference to dGPU.
1958  */
1959
1960 static ssize_t amdgpu_get_smartshift_bias(struct device *dev,
1961                                           struct device_attribute *attr,
1962                                           char *buf)
1963 {
1964         int r = 0;
1965
1966         r = sysfs_emit(buf, "%d\n", amdgpu_smartshift_bias);
1967
1968         return r;
1969 }
1970
1971 static ssize_t amdgpu_set_smartshift_bias(struct device *dev,
1972                                           struct device_attribute *attr,
1973                                           const char *buf, size_t count)
1974 {
1975         struct drm_device *ddev = dev_get_drvdata(dev);
1976         struct amdgpu_device *adev = drm_to_adev(ddev);
1977         int r = 0;
1978         int bias = 0;
1979
1980         if (amdgpu_in_reset(adev))
1981                 return -EPERM;
1982         if (adev->in_suspend && !adev->in_runpm)
1983                 return -EPERM;
1984
1985         r = pm_runtime_get_sync(ddev->dev);
1986         if (r < 0) {
1987                 pm_runtime_put_autosuspend(ddev->dev);
1988                 return r;
1989         }
1990
1991         r = kstrtoint(buf, 10, &bias);
1992         if (r)
1993                 goto out;
1994
1995         if (bias > AMDGPU_SMARTSHIFT_MAX_BIAS)
1996                 bias = AMDGPU_SMARTSHIFT_MAX_BIAS;
1997         else if (bias < AMDGPU_SMARTSHIFT_MIN_BIAS)
1998                 bias = AMDGPU_SMARTSHIFT_MIN_BIAS;
1999
2000         amdgpu_smartshift_bias = bias;
2001         r = count;
2002
2003         /* TODO: update bias level with SMU message */
2004
2005 out:
2006         pm_runtime_mark_last_busy(ddev->dev);
2007         pm_runtime_put_autosuspend(ddev->dev);
2008         return r;
2009 }
2010
2011 static int ss_power_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2012                                 uint32_t mask, enum amdgpu_device_attr_states *states)
2013 {
2014         if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev)))
2015                 *states = ATTR_STATE_UNSUPPORTED;
2016
2017         return 0;
2018 }
2019
2020 static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2021                                uint32_t mask, enum amdgpu_device_attr_states *states)
2022 {
2023         uint32_t ss_power;
2024
2025         if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev)))
2026                 *states = ATTR_STATE_UNSUPPORTED;
2027         else if (amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE,
2028                  (void *)&ss_power))
2029                 *states = ATTR_STATE_UNSUPPORTED;
2030         else if (amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
2031                  (void *)&ss_power))
2032                 *states = ATTR_STATE_UNSUPPORTED;
2033
2034         return 0;
2035 }
2036
2037 /* Following items will be read out to indicate current plpd policy:
2038  *  - -1: none
2039  *  - 0: disallow
2040  *  - 1: default
2041  *  - 2: optimized
2042  */
2043 static ssize_t amdgpu_get_xgmi_plpd_policy(struct device *dev,
2044                                            struct device_attribute *attr,
2045                                            char *buf)
2046 {
2047         struct drm_device *ddev = dev_get_drvdata(dev);
2048         struct amdgpu_device *adev = drm_to_adev(ddev);
2049         char *mode_desc = "none";
2050         int mode;
2051
2052         if (amdgpu_in_reset(adev))
2053                 return -EPERM;
2054         if (adev->in_suspend && !adev->in_runpm)
2055                 return -EPERM;
2056
2057         mode = amdgpu_dpm_get_xgmi_plpd_mode(adev, &mode_desc);
2058
2059         return sysfs_emit(buf, "%d: %s\n", mode, mode_desc);
2060 }
2061
2062 /* Following argument value is expected from user to change plpd policy
2063  *  - arg 0: disallow plpd
2064  *  - arg 1: default policy
2065  *  - arg 2: optimized policy
2066  */
2067 static ssize_t amdgpu_set_xgmi_plpd_policy(struct device *dev,
2068                                            struct device_attribute *attr,
2069                                            const char *buf, size_t count)
2070 {
2071         struct drm_device *ddev = dev_get_drvdata(dev);
2072         struct amdgpu_device *adev = drm_to_adev(ddev);
2073         int mode, ret;
2074
2075         if (amdgpu_in_reset(adev))
2076                 return -EPERM;
2077         if (adev->in_suspend && !adev->in_runpm)
2078                 return -EPERM;
2079
2080         ret = kstrtos32(buf, 0, &mode);
2081         if (ret)
2082                 return -EINVAL;
2083
2084         ret = pm_runtime_get_sync(ddev->dev);
2085         if (ret < 0) {
2086                 pm_runtime_put_autosuspend(ddev->dev);
2087                 return ret;
2088         }
2089
2090         ret = amdgpu_dpm_set_xgmi_plpd_mode(adev, mode);
2091
2092         pm_runtime_mark_last_busy(ddev->dev);
2093         pm_runtime_put_autosuspend(ddev->dev);
2094
2095         if (ret)
2096                 return ret;
2097
2098         return count;
2099 }
2100
2101 static struct amdgpu_device_attr amdgpu_device_attrs[] = {
2102         AMDGPU_DEVICE_ATTR_RW(power_dpm_state,                          ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2103         AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level,        ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2104         AMDGPU_DEVICE_ATTR_RO(pp_num_states,                            ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2105         AMDGPU_DEVICE_ATTR_RO(pp_cur_state,                             ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2106         AMDGPU_DEVICE_ATTR_RW(pp_force_state,                           ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2107         AMDGPU_DEVICE_ATTR_RW(pp_table,                                 ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2108         AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2109         AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2110         AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk,                            ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2111         AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2112         AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2113         AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk1,                             ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2114         AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2115         AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk1,                             ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2116         AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk,                           ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2117         AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2118         AMDGPU_DEVICE_ATTR_RW(pp_sclk_od,                               ATTR_FLAG_BASIC),
2119         AMDGPU_DEVICE_ATTR_RW(pp_mclk_od,                               ATTR_FLAG_BASIC),
2120         AMDGPU_DEVICE_ATTR_RW(pp_power_profile_mode,                    ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2121         AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage,                        ATTR_FLAG_BASIC),
2122         AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent,                         ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2123         AMDGPU_DEVICE_ATTR_RO(mem_busy_percent,                         ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2124         AMDGPU_DEVICE_ATTR_RO(pcie_bw,                                  ATTR_FLAG_BASIC),
2125         AMDGPU_DEVICE_ATTR_RW(pp_features,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2126         AMDGPU_DEVICE_ATTR_RO(unique_id,                                ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2127         AMDGPU_DEVICE_ATTR_RW(thermal_throttling_logging,               ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2128         AMDGPU_DEVICE_ATTR_RW(apu_thermal_cap,                          ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2129         AMDGPU_DEVICE_ATTR_RO(gpu_metrics,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2130         AMDGPU_DEVICE_ATTR_RO(smartshift_apu_power,                     ATTR_FLAG_BASIC,
2131                               .attr_update = ss_power_attr_update),
2132         AMDGPU_DEVICE_ATTR_RO(smartshift_dgpu_power,                    ATTR_FLAG_BASIC,
2133                               .attr_update = ss_power_attr_update),
2134         AMDGPU_DEVICE_ATTR_RW(smartshift_bias,                          ATTR_FLAG_BASIC,
2135                               .attr_update = ss_bias_attr_update),
2136         AMDGPU_DEVICE_ATTR_RW(xgmi_plpd_policy,                         ATTR_FLAG_BASIC),
2137         AMDGPU_DEVICE_ATTR_RO(pm_metrics,                               ATTR_FLAG_BASIC,
2138                               .attr_update = amdgpu_pm_metrics_attr_update),
2139 };
2140
2141 static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2142                                uint32_t mask, enum amdgpu_device_attr_states *states)
2143 {
2144         struct device_attribute *dev_attr = &attr->dev_attr;
2145         uint32_t mp1_ver = amdgpu_ip_version(adev, MP1_HWIP, 0);
2146         uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);
2147         const char *attr_name = dev_attr->attr.name;
2148
2149         if (!(attr->flags & mask)) {
2150                 *states = ATTR_STATE_UNSUPPORTED;
2151                 return 0;
2152         }
2153
2154 #define DEVICE_ATTR_IS(_name)   (!strcmp(attr_name, #_name))
2155
2156         if (DEVICE_ATTR_IS(pp_dpm_socclk)) {
2157                 if (gc_ver < IP_VERSION(9, 0, 0))
2158                         *states = ATTR_STATE_UNSUPPORTED;
2159         } else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
2160                 if (gc_ver < IP_VERSION(9, 0, 0) ||
2161                     !amdgpu_device_has_display_hardware(adev))
2162                         *states = ATTR_STATE_UNSUPPORTED;
2163         } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
2164                 if (mp1_ver < IP_VERSION(10, 0, 0))
2165                         *states = ATTR_STATE_UNSUPPORTED;
2166         } else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
2167                 *states = ATTR_STATE_UNSUPPORTED;
2168                 if (amdgpu_dpm_is_overdrive_supported(adev))
2169                         *states = ATTR_STATE_SUPPORTED;
2170         } else if (DEVICE_ATTR_IS(mem_busy_percent)) {
2171                 if ((adev->flags & AMD_IS_APU &&
2172                      gc_ver != IP_VERSION(9, 4, 3)) ||
2173                     gc_ver == IP_VERSION(9, 0, 1))
2174                         *states = ATTR_STATE_UNSUPPORTED;
2175         } else if (DEVICE_ATTR_IS(pcie_bw)) {
2176                 /* PCIe Perf counters won't work on APU nodes */
2177                 if (adev->flags & AMD_IS_APU)
2178                         *states = ATTR_STATE_UNSUPPORTED;
2179         } else if (DEVICE_ATTR_IS(unique_id)) {
2180                 switch (gc_ver) {
2181                 case IP_VERSION(9, 0, 1):
2182                 case IP_VERSION(9, 4, 0):
2183                 case IP_VERSION(9, 4, 1):
2184                 case IP_VERSION(9, 4, 2):
2185                 case IP_VERSION(9, 4, 3):
2186                 case IP_VERSION(10, 3, 0):
2187                 case IP_VERSION(11, 0, 0):
2188                 case IP_VERSION(11, 0, 1):
2189                 case IP_VERSION(11, 0, 2):
2190                 case IP_VERSION(11, 0, 3):
2191                         *states = ATTR_STATE_SUPPORTED;
2192                         break;
2193                 default:
2194                         *states = ATTR_STATE_UNSUPPORTED;
2195                 }
2196         } else if (DEVICE_ATTR_IS(pp_features)) {
2197                 if ((adev->flags & AMD_IS_APU &&
2198                      gc_ver != IP_VERSION(9, 4, 3)) ||
2199                     gc_ver < IP_VERSION(9, 0, 0))
2200                         *states = ATTR_STATE_UNSUPPORTED;
2201         } else if (DEVICE_ATTR_IS(gpu_metrics)) {
2202                 if (gc_ver < IP_VERSION(9, 1, 0))
2203                         *states = ATTR_STATE_UNSUPPORTED;
2204         } else if (DEVICE_ATTR_IS(pp_dpm_vclk)) {
2205                 if (!(gc_ver == IP_VERSION(10, 3, 1) ||
2206                       gc_ver == IP_VERSION(10, 3, 0) ||
2207                       gc_ver == IP_VERSION(10, 1, 2) ||
2208                       gc_ver == IP_VERSION(11, 0, 0) ||
2209                       gc_ver == IP_VERSION(11, 0, 2) ||
2210                       gc_ver == IP_VERSION(11, 0, 3) ||
2211                       gc_ver == IP_VERSION(9, 4, 3)))
2212                         *states = ATTR_STATE_UNSUPPORTED;
2213         } else if (DEVICE_ATTR_IS(pp_dpm_vclk1)) {
2214                 if (!((gc_ver == IP_VERSION(10, 3, 1) ||
2215                            gc_ver == IP_VERSION(10, 3, 0) ||
2216                            gc_ver == IP_VERSION(11, 0, 2) ||
2217                            gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2))
2218                         *states = ATTR_STATE_UNSUPPORTED;
2219         } else if (DEVICE_ATTR_IS(pp_dpm_dclk)) {
2220                 if (!(gc_ver == IP_VERSION(10, 3, 1) ||
2221                       gc_ver == IP_VERSION(10, 3, 0) ||
2222                       gc_ver == IP_VERSION(10, 1, 2) ||
2223                       gc_ver == IP_VERSION(11, 0, 0) ||
2224                       gc_ver == IP_VERSION(11, 0, 2) ||
2225                       gc_ver == IP_VERSION(11, 0, 3) ||
2226                       gc_ver == IP_VERSION(9, 4, 3)))
2227                         *states = ATTR_STATE_UNSUPPORTED;
2228         } else if (DEVICE_ATTR_IS(pp_dpm_dclk1)) {
2229                 if (!((gc_ver == IP_VERSION(10, 3, 1) ||
2230                            gc_ver == IP_VERSION(10, 3, 0) ||
2231                            gc_ver == IP_VERSION(11, 0, 2) ||
2232                            gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2))
2233                         *states = ATTR_STATE_UNSUPPORTED;
2234         } else if (DEVICE_ATTR_IS(pp_power_profile_mode)) {
2235                 if (amdgpu_dpm_get_power_profile_mode(adev, NULL) == -EOPNOTSUPP)
2236                         *states = ATTR_STATE_UNSUPPORTED;
2237                 else if ((gc_ver == IP_VERSION(10, 3, 0) ||
2238                           gc_ver == IP_VERSION(11, 0, 3)) && amdgpu_sriov_vf(adev))
2239                         *states = ATTR_STATE_UNSUPPORTED;
2240         } else if (DEVICE_ATTR_IS(xgmi_plpd_policy)) {
2241                 if (amdgpu_dpm_get_xgmi_plpd_mode(adev, NULL) == XGMI_PLPD_NONE)
2242                         *states = ATTR_STATE_UNSUPPORTED;
2243         } else if (DEVICE_ATTR_IS(pp_mclk_od)) {
2244                 if (amdgpu_dpm_get_mclk_od(adev) == -EOPNOTSUPP)
2245                         *states = ATTR_STATE_UNSUPPORTED;
2246         } else if (DEVICE_ATTR_IS(pp_sclk_od)) {
2247                 if (amdgpu_dpm_get_sclk_od(adev) == -EOPNOTSUPP)
2248                         *states = ATTR_STATE_UNSUPPORTED;
2249         } else if (DEVICE_ATTR_IS(apu_thermal_cap)) {
2250                 u32 limit;
2251
2252                 if (amdgpu_dpm_get_apu_thermal_limit(adev, &limit) ==
2253                     -EOPNOTSUPP)
2254                         *states = ATTR_STATE_UNSUPPORTED;
2255         } else if (DEVICE_ATTR_IS(pp_dpm_pcie)) {
2256                 if (gc_ver == IP_VERSION(9, 4, 2) ||
2257                     gc_ver == IP_VERSION(9, 4, 3))
2258                         *states = ATTR_STATE_UNSUPPORTED;
2259         }
2260
2261         switch (gc_ver) {
2262         case IP_VERSION(9, 4, 1):
2263         case IP_VERSION(9, 4, 2):
2264                 /* the Mi series card does not support standalone mclk/socclk/fclk level setting */
2265                 if (DEVICE_ATTR_IS(pp_dpm_mclk) ||
2266                     DEVICE_ATTR_IS(pp_dpm_socclk) ||
2267                     DEVICE_ATTR_IS(pp_dpm_fclk)) {
2268                         dev_attr->attr.mode &= ~S_IWUGO;
2269                         dev_attr->store = NULL;
2270                 }
2271                 break;
2272         case IP_VERSION(10, 3, 0):
2273                 if (DEVICE_ATTR_IS(power_dpm_force_performance_level) &&
2274                     amdgpu_sriov_vf(adev)) {
2275                         dev_attr->attr.mode &= ~0222;
2276                         dev_attr->store = NULL;
2277                 }
2278                 break;
2279         default:
2280                 break;
2281         }
2282
2283         if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
2284                 /* SMU MP1 does not support dcefclk level setting */
2285                 if (gc_ver >= IP_VERSION(10, 0, 0)) {
2286                         dev_attr->attr.mode &= ~S_IWUGO;
2287                         dev_attr->store = NULL;
2288                 }
2289         }
2290
2291         /* setting should not be allowed from VF if not in one VF mode */
2292         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) {
2293                 dev_attr->attr.mode &= ~S_IWUGO;
2294                 dev_attr->store = NULL;
2295         }
2296
2297 #undef DEVICE_ATTR_IS
2298
2299         return 0;
2300 }
2301
2302
2303 static int amdgpu_device_attr_create(struct amdgpu_device *adev,
2304                                      struct amdgpu_device_attr *attr,
2305                                      uint32_t mask, struct list_head *attr_list)
2306 {
2307         int ret = 0;
2308         enum amdgpu_device_attr_states attr_states = ATTR_STATE_SUPPORTED;
2309         struct amdgpu_device_attr_entry *attr_entry;
2310         struct device_attribute *dev_attr;
2311         const char *name;
2312
2313         int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2314                            uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update;
2315
2316         if (!attr)
2317                 return -EINVAL;
2318
2319         dev_attr = &attr->dev_attr;
2320         name = dev_attr->attr.name;
2321
2322         attr_update = attr->attr_update ? attr->attr_update : default_attr_update;
2323
2324         ret = attr_update(adev, attr, mask, &attr_states);
2325         if (ret) {
2326                 dev_err(adev->dev, "failed to update device file %s, ret = %d\n",
2327                         name, ret);
2328                 return ret;
2329         }
2330
2331         if (attr_states == ATTR_STATE_UNSUPPORTED)
2332                 return 0;
2333
2334         ret = device_create_file(adev->dev, dev_attr);
2335         if (ret) {
2336                 dev_err(adev->dev, "failed to create device file %s, ret = %d\n",
2337                         name, ret);
2338         }
2339
2340         attr_entry = kmalloc(sizeof(*attr_entry), GFP_KERNEL);
2341         if (!attr_entry)
2342                 return -ENOMEM;
2343
2344         attr_entry->attr = attr;
2345         INIT_LIST_HEAD(&attr_entry->entry);
2346
2347         list_add_tail(&attr_entry->entry, attr_list);
2348
2349         return ret;
2350 }
2351
2352 static void amdgpu_device_attr_remove(struct amdgpu_device *adev, struct amdgpu_device_attr *attr)
2353 {
2354         struct device_attribute *dev_attr = &attr->dev_attr;
2355
2356         device_remove_file(adev->dev, dev_attr);
2357 }
2358
2359 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
2360                                              struct list_head *attr_list);
2361
2362 static int amdgpu_device_attr_create_groups(struct amdgpu_device *adev,
2363                                             struct amdgpu_device_attr *attrs,
2364                                             uint32_t counts,
2365                                             uint32_t mask,
2366                                             struct list_head *attr_list)
2367 {
2368         int ret = 0;
2369         uint32_t i = 0;
2370
2371         for (i = 0; i < counts; i++) {
2372                 ret = amdgpu_device_attr_create(adev, &attrs[i], mask, attr_list);
2373                 if (ret)
2374                         goto failed;
2375         }
2376
2377         return 0;
2378
2379 failed:
2380         amdgpu_device_attr_remove_groups(adev, attr_list);
2381
2382         return ret;
2383 }
2384
2385 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
2386                                              struct list_head *attr_list)
2387 {
2388         struct amdgpu_device_attr_entry *entry, *entry_tmp;
2389
2390         if (list_empty(attr_list))
2391                 return ;
2392
2393         list_for_each_entry_safe(entry, entry_tmp, attr_list, entry) {
2394                 amdgpu_device_attr_remove(adev, entry->attr);
2395                 list_del(&entry->entry);
2396                 kfree(entry);
2397         }
2398 }
2399
2400 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
2401                                       struct device_attribute *attr,
2402                                       char *buf)
2403 {
2404         struct amdgpu_device *adev = dev_get_drvdata(dev);
2405         int channel = to_sensor_dev_attr(attr)->index;
2406         int r, temp = 0;
2407
2408         if (channel >= PP_TEMP_MAX)
2409                 return -EINVAL;
2410
2411         switch (channel) {
2412         case PP_TEMP_JUNCTION:
2413                 /* get current junction temperature */
2414                 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
2415                                            (void *)&temp);
2416                 break;
2417         case PP_TEMP_EDGE:
2418                 /* get current edge temperature */
2419                 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_EDGE_TEMP,
2420                                            (void *)&temp);
2421                 break;
2422         case PP_TEMP_MEM:
2423                 /* get current memory temperature */
2424                 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MEM_TEMP,
2425                                            (void *)&temp);
2426                 break;
2427         default:
2428                 r = -EINVAL;
2429                 break;
2430         }
2431
2432         if (r)
2433                 return r;
2434
2435         return sysfs_emit(buf, "%d\n", temp);
2436 }
2437
2438 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
2439                                              struct device_attribute *attr,
2440                                              char *buf)
2441 {
2442         struct amdgpu_device *adev = dev_get_drvdata(dev);
2443         int hyst = to_sensor_dev_attr(attr)->index;
2444         int temp;
2445
2446         if (hyst)
2447                 temp = adev->pm.dpm.thermal.min_temp;
2448         else
2449                 temp = adev->pm.dpm.thermal.max_temp;
2450
2451         return sysfs_emit(buf, "%d\n", temp);
2452 }
2453
2454 static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev,
2455                                              struct device_attribute *attr,
2456                                              char *buf)
2457 {
2458         struct amdgpu_device *adev = dev_get_drvdata(dev);
2459         int hyst = to_sensor_dev_attr(attr)->index;
2460         int temp;
2461
2462         if (hyst)
2463                 temp = adev->pm.dpm.thermal.min_hotspot_temp;
2464         else
2465                 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp;
2466
2467         return sysfs_emit(buf, "%d\n", temp);
2468 }
2469
2470 static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev,
2471                                              struct device_attribute *attr,
2472                                              char *buf)
2473 {
2474         struct amdgpu_device *adev = dev_get_drvdata(dev);
2475         int hyst = to_sensor_dev_attr(attr)->index;
2476         int temp;
2477
2478         if (hyst)
2479                 temp = adev->pm.dpm.thermal.min_mem_temp;
2480         else
2481                 temp = adev->pm.dpm.thermal.max_mem_crit_temp;
2482
2483         return sysfs_emit(buf, "%d\n", temp);
2484 }
2485
2486 static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev,
2487                                              struct device_attribute *attr,
2488                                              char *buf)
2489 {
2490         int channel = to_sensor_dev_attr(attr)->index;
2491
2492         if (channel >= PP_TEMP_MAX)
2493                 return -EINVAL;
2494
2495         return sysfs_emit(buf, "%s\n", temp_label[channel].label);
2496 }
2497
2498 static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev,
2499                                              struct device_attribute *attr,
2500                                              char *buf)
2501 {
2502         struct amdgpu_device *adev = dev_get_drvdata(dev);
2503         int channel = to_sensor_dev_attr(attr)->index;
2504         int temp = 0;
2505
2506         if (channel >= PP_TEMP_MAX)
2507                 return -EINVAL;
2508
2509         switch (channel) {
2510         case PP_TEMP_JUNCTION:
2511                 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp;
2512                 break;
2513         case PP_TEMP_EDGE:
2514                 temp = adev->pm.dpm.thermal.max_edge_emergency_temp;
2515                 break;
2516         case PP_TEMP_MEM:
2517                 temp = adev->pm.dpm.thermal.max_mem_emergency_temp;
2518                 break;
2519         }
2520
2521         return sysfs_emit(buf, "%d\n", temp);
2522 }
2523
2524 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
2525                                             struct device_attribute *attr,
2526                                             char *buf)
2527 {
2528         struct amdgpu_device *adev = dev_get_drvdata(dev);
2529         u32 pwm_mode = 0;
2530         int ret;
2531
2532         if (amdgpu_in_reset(adev))
2533                 return -EPERM;
2534         if (adev->in_suspend && !adev->in_runpm)
2535                 return -EPERM;
2536
2537         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2538         if (ret < 0) {
2539                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2540                 return ret;
2541         }
2542
2543         ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2544
2545         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2546         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2547
2548         if (ret)
2549                 return -EINVAL;
2550
2551         return sysfs_emit(buf, "%u\n", pwm_mode);
2552 }
2553
2554 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
2555                                             struct device_attribute *attr,
2556                                             const char *buf,
2557                                             size_t count)
2558 {
2559         struct amdgpu_device *adev = dev_get_drvdata(dev);
2560         int err, ret;
2561         int value;
2562
2563         if (amdgpu_in_reset(adev))
2564                 return -EPERM;
2565         if (adev->in_suspend && !adev->in_runpm)
2566                 return -EPERM;
2567
2568         err = kstrtoint(buf, 10, &value);
2569         if (err)
2570                 return err;
2571
2572         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2573         if (ret < 0) {
2574                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2575                 return ret;
2576         }
2577
2578         ret = amdgpu_dpm_set_fan_control_mode(adev, value);
2579
2580         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2581         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2582
2583         if (ret)
2584                 return -EINVAL;
2585
2586         return count;
2587 }
2588
2589 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
2590                                          struct device_attribute *attr,
2591                                          char *buf)
2592 {
2593         return sysfs_emit(buf, "%i\n", 0);
2594 }
2595
2596 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
2597                                          struct device_attribute *attr,
2598                                          char *buf)
2599 {
2600         return sysfs_emit(buf, "%i\n", 255);
2601 }
2602
2603 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
2604                                      struct device_attribute *attr,
2605                                      const char *buf, size_t count)
2606 {
2607         struct amdgpu_device *adev = dev_get_drvdata(dev);
2608         int err;
2609         u32 value;
2610         u32 pwm_mode;
2611
2612         if (amdgpu_in_reset(adev))
2613                 return -EPERM;
2614         if (adev->in_suspend && !adev->in_runpm)
2615                 return -EPERM;
2616
2617         err = kstrtou32(buf, 10, &value);
2618         if (err)
2619                 return err;
2620
2621         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2622         if (err < 0) {
2623                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2624                 return err;
2625         }
2626
2627         err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2628         if (err)
2629                 goto out;
2630
2631         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2632                 pr_info("manual fan speed control should be enabled first\n");
2633                 err = -EINVAL;
2634                 goto out;
2635         }
2636
2637         err = amdgpu_dpm_set_fan_speed_pwm(adev, value);
2638
2639 out:
2640         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2641         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2642
2643         if (err)
2644                 return err;
2645
2646         return count;
2647 }
2648
2649 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
2650                                      struct device_attribute *attr,
2651                                      char *buf)
2652 {
2653         struct amdgpu_device *adev = dev_get_drvdata(dev);
2654         int err;
2655         u32 speed = 0;
2656
2657         if (amdgpu_in_reset(adev))
2658                 return -EPERM;
2659         if (adev->in_suspend && !adev->in_runpm)
2660                 return -EPERM;
2661
2662         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2663         if (err < 0) {
2664                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2665                 return err;
2666         }
2667
2668         err = amdgpu_dpm_get_fan_speed_pwm(adev, &speed);
2669
2670         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2671         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2672
2673         if (err)
2674                 return err;
2675
2676         return sysfs_emit(buf, "%i\n", speed);
2677 }
2678
2679 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
2680                                            struct device_attribute *attr,
2681                                            char *buf)
2682 {
2683         struct amdgpu_device *adev = dev_get_drvdata(dev);
2684         int err;
2685         u32 speed = 0;
2686
2687         if (amdgpu_in_reset(adev))
2688                 return -EPERM;
2689         if (adev->in_suspend && !adev->in_runpm)
2690                 return -EPERM;
2691
2692         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2693         if (err < 0) {
2694                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2695                 return err;
2696         }
2697
2698         err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
2699
2700         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2701         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2702
2703         if (err)
2704                 return err;
2705
2706         return sysfs_emit(buf, "%i\n", speed);
2707 }
2708
2709 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
2710                                          struct device_attribute *attr,
2711                                          char *buf)
2712 {
2713         struct amdgpu_device *adev = dev_get_drvdata(dev);
2714         u32 min_rpm = 0;
2715         int r;
2716
2717         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
2718                                    (void *)&min_rpm);
2719
2720         if (r)
2721                 return r;
2722
2723         return sysfs_emit(buf, "%d\n", min_rpm);
2724 }
2725
2726 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
2727                                          struct device_attribute *attr,
2728                                          char *buf)
2729 {
2730         struct amdgpu_device *adev = dev_get_drvdata(dev);
2731         u32 max_rpm = 0;
2732         int r;
2733
2734         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
2735                                    (void *)&max_rpm);
2736
2737         if (r)
2738                 return r;
2739
2740         return sysfs_emit(buf, "%d\n", max_rpm);
2741 }
2742
2743 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
2744                                            struct device_attribute *attr,
2745                                            char *buf)
2746 {
2747         struct amdgpu_device *adev = dev_get_drvdata(dev);
2748         int err;
2749         u32 rpm = 0;
2750
2751         if (amdgpu_in_reset(adev))
2752                 return -EPERM;
2753         if (adev->in_suspend && !adev->in_runpm)
2754                 return -EPERM;
2755
2756         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2757         if (err < 0) {
2758                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2759                 return err;
2760         }
2761
2762         err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
2763
2764         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2765         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2766
2767         if (err)
2768                 return err;
2769
2770         return sysfs_emit(buf, "%i\n", rpm);
2771 }
2772
2773 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
2774                                      struct device_attribute *attr,
2775                                      const char *buf, size_t count)
2776 {
2777         struct amdgpu_device *adev = dev_get_drvdata(dev);
2778         int err;
2779         u32 value;
2780         u32 pwm_mode;
2781
2782         if (amdgpu_in_reset(adev))
2783                 return -EPERM;
2784         if (adev->in_suspend && !adev->in_runpm)
2785                 return -EPERM;
2786
2787         err = kstrtou32(buf, 10, &value);
2788         if (err)
2789                 return err;
2790
2791         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2792         if (err < 0) {
2793                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2794                 return err;
2795         }
2796
2797         err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2798         if (err)
2799                 goto out;
2800
2801         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2802                 err = -ENODATA;
2803                 goto out;
2804         }
2805
2806         err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
2807
2808 out:
2809         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2810         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2811
2812         if (err)
2813                 return err;
2814
2815         return count;
2816 }
2817
2818 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
2819                                             struct device_attribute *attr,
2820                                             char *buf)
2821 {
2822         struct amdgpu_device *adev = dev_get_drvdata(dev);
2823         u32 pwm_mode = 0;
2824         int ret;
2825
2826         if (amdgpu_in_reset(adev))
2827                 return -EPERM;
2828         if (adev->in_suspend && !adev->in_runpm)
2829                 return -EPERM;
2830
2831         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2832         if (ret < 0) {
2833                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2834                 return ret;
2835         }
2836
2837         ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2838
2839         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2840         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2841
2842         if (ret)
2843                 return -EINVAL;
2844
2845         return sysfs_emit(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
2846 }
2847
2848 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
2849                                             struct device_attribute *attr,
2850                                             const char *buf,
2851                                             size_t count)
2852 {
2853         struct amdgpu_device *adev = dev_get_drvdata(dev);
2854         int err;
2855         int value;
2856         u32 pwm_mode;
2857
2858         if (amdgpu_in_reset(adev))
2859                 return -EPERM;
2860         if (adev->in_suspend && !adev->in_runpm)
2861                 return -EPERM;
2862
2863         err = kstrtoint(buf, 10, &value);
2864         if (err)
2865                 return err;
2866
2867         if (value == 0)
2868                 pwm_mode = AMD_FAN_CTRL_AUTO;
2869         else if (value == 1)
2870                 pwm_mode = AMD_FAN_CTRL_MANUAL;
2871         else
2872                 return -EINVAL;
2873
2874         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2875         if (err < 0) {
2876                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2877                 return err;
2878         }
2879
2880         err = amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
2881
2882         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2883         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2884
2885         if (err)
2886                 return -EINVAL;
2887
2888         return count;
2889 }
2890
2891 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
2892                                         struct device_attribute *attr,
2893                                         char *buf)
2894 {
2895         struct amdgpu_device *adev = dev_get_drvdata(dev);
2896         u32 vddgfx;
2897         int r;
2898
2899         /* get the voltage */
2900         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDGFX,
2901                                    (void *)&vddgfx);
2902         if (r)
2903                 return r;
2904
2905         return sysfs_emit(buf, "%d\n", vddgfx);
2906 }
2907
2908 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
2909                                               struct device_attribute *attr,
2910                                               char *buf)
2911 {
2912         return sysfs_emit(buf, "vddgfx\n");
2913 }
2914
2915 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
2916                                        struct device_attribute *attr,
2917                                        char *buf)
2918 {
2919         struct amdgpu_device *adev = dev_get_drvdata(dev);
2920         u32 vddnb;
2921         int r;
2922
2923         /* only APUs have vddnb */
2924         if  (!(adev->flags & AMD_IS_APU))
2925                 return -EINVAL;
2926
2927         /* get the voltage */
2928         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDNB,
2929                                    (void *)&vddnb);
2930         if (r)
2931                 return r;
2932
2933         return sysfs_emit(buf, "%d\n", vddnb);
2934 }
2935
2936 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
2937                                               struct device_attribute *attr,
2938                                               char *buf)
2939 {
2940         return sysfs_emit(buf, "vddnb\n");
2941 }
2942
2943 static int amdgpu_hwmon_get_power(struct device *dev,
2944                                   enum amd_pp_sensors sensor)
2945 {
2946         struct amdgpu_device *adev = dev_get_drvdata(dev);
2947         unsigned int uw;
2948         u32 query = 0;
2949         int r;
2950
2951         r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&query);
2952         if (r)
2953                 return r;
2954
2955         /* convert to microwatts */
2956         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
2957
2958         return uw;
2959 }
2960
2961 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
2962                                            struct device_attribute *attr,
2963                                            char *buf)
2964 {
2965         ssize_t val;
2966
2967         val = amdgpu_hwmon_get_power(dev, AMDGPU_PP_SENSOR_GPU_AVG_POWER);
2968         if (val < 0)
2969                 return val;
2970
2971         return sysfs_emit(buf, "%zd\n", val);
2972 }
2973
2974 static ssize_t amdgpu_hwmon_show_power_input(struct device *dev,
2975                                              struct device_attribute *attr,
2976                                              char *buf)
2977 {
2978         ssize_t val;
2979
2980         val = amdgpu_hwmon_get_power(dev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER);
2981         if (val < 0)
2982                 return val;
2983
2984         return sysfs_emit(buf, "%zd\n", val);
2985 }
2986
2987 static ssize_t amdgpu_hwmon_show_power_cap_generic(struct device *dev,
2988                                         struct device_attribute *attr,
2989                                         char *buf,
2990                                         enum pp_power_limit_level pp_limit_level)
2991 {
2992         struct amdgpu_device *adev = dev_get_drvdata(dev);
2993         enum pp_power_type power_type = to_sensor_dev_attr(attr)->index;
2994         uint32_t limit;
2995         ssize_t size;
2996         int r;
2997
2998         if (amdgpu_in_reset(adev))
2999                 return -EPERM;
3000         if (adev->in_suspend && !adev->in_runpm)
3001                 return -EPERM;
3002
3003         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
3004         if (r < 0) {
3005                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3006                 return r;
3007         }
3008
3009         r = amdgpu_dpm_get_power_limit(adev, &limit,
3010                                       pp_limit_level, power_type);
3011
3012         if (!r)
3013                 size = sysfs_emit(buf, "%u\n", limit * 1000000);
3014         else
3015                 size = sysfs_emit(buf, "\n");
3016
3017         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
3018         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3019
3020         return size;
3021 }
3022
3023 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
3024                                          struct device_attribute *attr,
3025                                          char *buf)
3026 {
3027         return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_MIN);
3028 }
3029
3030 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
3031                                          struct device_attribute *attr,
3032                                          char *buf)
3033 {
3034         return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_MAX);
3035
3036 }
3037
3038 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
3039                                          struct device_attribute *attr,
3040                                          char *buf)
3041 {
3042         return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_CURRENT);
3043
3044 }
3045
3046 static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev,
3047                                          struct device_attribute *attr,
3048                                          char *buf)
3049 {
3050         return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_DEFAULT);
3051
3052 }
3053
3054 static ssize_t amdgpu_hwmon_show_power_label(struct device *dev,
3055                                          struct device_attribute *attr,
3056                                          char *buf)
3057 {
3058         struct amdgpu_device *adev = dev_get_drvdata(dev);
3059         uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);
3060
3061         if (gc_ver == IP_VERSION(10, 3, 1))
3062                 return sysfs_emit(buf, "%s\n",
3063                                   to_sensor_dev_attr(attr)->index == PP_PWR_TYPE_FAST ?
3064                                   "fastPPT" : "slowPPT");
3065         else
3066                 return sysfs_emit(buf, "PPT\n");
3067 }
3068
3069 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
3070                 struct device_attribute *attr,
3071                 const char *buf,
3072                 size_t count)
3073 {
3074         struct amdgpu_device *adev = dev_get_drvdata(dev);
3075         int limit_type = to_sensor_dev_attr(attr)->index;
3076         int err;
3077         u32 value;
3078
3079         if (amdgpu_in_reset(adev))
3080                 return -EPERM;
3081         if (adev->in_suspend && !adev->in_runpm)
3082                 return -EPERM;
3083
3084         if (amdgpu_sriov_vf(adev))
3085                 return -EINVAL;
3086
3087         err = kstrtou32(buf, 10, &value);
3088         if (err)
3089                 return err;
3090
3091         value = value / 1000000; /* convert to Watt */
3092         value |= limit_type << 24;
3093
3094         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
3095         if (err < 0) {
3096                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3097                 return err;
3098         }
3099
3100         err = amdgpu_dpm_set_power_limit(adev, value);
3101
3102         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
3103         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3104
3105         if (err)
3106                 return err;
3107
3108         return count;
3109 }
3110
3111 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
3112                                       struct device_attribute *attr,
3113                                       char *buf)
3114 {
3115         struct amdgpu_device *adev = dev_get_drvdata(dev);
3116         uint32_t sclk;
3117         int r;
3118
3119         /* get the sclk */
3120         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
3121                                    (void *)&sclk);
3122         if (r)
3123                 return r;
3124
3125         return sysfs_emit(buf, "%u\n", sclk * 10 * 1000);
3126 }
3127
3128 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
3129                                             struct device_attribute *attr,
3130                                             char *buf)
3131 {
3132         return sysfs_emit(buf, "sclk\n");
3133 }
3134
3135 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
3136                                       struct device_attribute *attr,
3137                                       char *buf)
3138 {
3139         struct amdgpu_device *adev = dev_get_drvdata(dev);
3140         uint32_t mclk;
3141         int r;
3142
3143         /* get the sclk */
3144         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
3145                                    (void *)&mclk);
3146         if (r)
3147                 return r;
3148
3149         return sysfs_emit(buf, "%u\n", mclk * 10 * 1000);
3150 }
3151
3152 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
3153                                             struct device_attribute *attr,
3154                                             char *buf)
3155 {
3156         return sysfs_emit(buf, "mclk\n");
3157 }
3158
3159 /**
3160  * DOC: hwmon
3161  *
3162  * The amdgpu driver exposes the following sensor interfaces:
3163  *
3164  * - GPU temperature (via the on-die sensor)
3165  *
3166  * - GPU voltage
3167  *
3168  * - Northbridge voltage (APUs only)
3169  *
3170  * - GPU power
3171  *
3172  * - GPU fan
3173  *
3174  * - GPU gfx/compute engine clock
3175  *
3176  * - GPU memory clock (dGPU only)
3177  *
3178  * hwmon interfaces for GPU temperature:
3179  *
3180  * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius
3181  *   - temp2_input and temp3_input are supported on SOC15 dGPUs only
3182  *
3183  * - temp[1-3]_label: temperature channel label
3184  *   - temp2_label and temp3_label are supported on SOC15 dGPUs only
3185  *
3186  * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
3187  *   - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
3188  *
3189  * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
3190  *   - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
3191  *
3192  * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius
3193  *   - these are supported on SOC15 dGPUs only
3194  *
3195  * hwmon interfaces for GPU voltage:
3196  *
3197  * - in0_input: the voltage on the GPU in millivolts
3198  *
3199  * - in1_input: the voltage on the Northbridge in millivolts
3200  *
3201  * hwmon interfaces for GPU power:
3202  *
3203  * - power1_average: average power used by the SoC in microWatts.  On APUs this includes the CPU.
3204  *
3205  * - power1_input: instantaneous power used by the SoC in microWatts.  On APUs this includes the CPU.
3206  *
3207  * - power1_cap_min: minimum cap supported in microWatts
3208  *
3209  * - power1_cap_max: maximum cap supported in microWatts
3210  *
3211  * - power1_cap: selected power cap in microWatts
3212  *
3213  * hwmon interfaces for GPU fan:
3214  *
3215  * - pwm1: pulse width modulation fan level (0-255)
3216  *
3217  * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
3218  *
3219  * - pwm1_min: pulse width modulation fan control minimum level (0)
3220  *
3221  * - pwm1_max: pulse width modulation fan control maximum level (255)
3222  *
3223  * - fan1_min: a minimum value Unit: revolution/min (RPM)
3224  *
3225  * - fan1_max: a maximum value Unit: revolution/max (RPM)
3226  *
3227  * - fan1_input: fan speed in RPM
3228  *
3229  * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM)
3230  *
3231  * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable
3232  *
3233  * NOTE: DO NOT set the fan speed via "pwm1" and "fan[1-\*]_target" interfaces at the same time.
3234  *       That will get the former one overridden.
3235  *
3236  * hwmon interfaces for GPU clocks:
3237  *
3238  * - freq1_input: the gfx/compute clock in hertz
3239  *
3240  * - freq2_input: the memory clock in hertz
3241  *
3242  * You can use hwmon tools like sensors to view this information on your system.
3243  *
3244  */
3245
3246 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE);
3247 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
3248 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
3249 static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE);
3250 static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION);
3251 static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0);
3252 static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1);
3253 static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION);
3254 static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM);
3255 static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0);
3256 static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1);
3257 static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM);
3258 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE);
3259 static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION);
3260 static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM);
3261 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
3262 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
3263 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
3264 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
3265 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
3266 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
3267 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
3268 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
3269 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
3270 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
3271 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
3272 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
3273 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
3274 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
3275 static SENSOR_DEVICE_ATTR(power1_input, S_IRUGO, amdgpu_hwmon_show_power_input, NULL, 0);
3276 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
3277 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
3278 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
3279 static SENSOR_DEVICE_ATTR(power1_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 0);
3280 static SENSOR_DEVICE_ATTR(power1_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 0);
3281 static SENSOR_DEVICE_ATTR(power2_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 1);
3282 static SENSOR_DEVICE_ATTR(power2_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 1);
3283 static SENSOR_DEVICE_ATTR(power2_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 1);
3284 static SENSOR_DEVICE_ATTR(power2_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 1);
3285 static SENSOR_DEVICE_ATTR(power2_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 1);
3286 static SENSOR_DEVICE_ATTR(power2_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 1);
3287 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
3288 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
3289 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
3290 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
3291
3292 static struct attribute *hwmon_attributes[] = {
3293         &sensor_dev_attr_temp1_input.dev_attr.attr,
3294         &sensor_dev_attr_temp1_crit.dev_attr.attr,
3295         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
3296         &sensor_dev_attr_temp2_input.dev_attr.attr,
3297         &sensor_dev_attr_temp2_crit.dev_attr.attr,
3298         &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr,
3299         &sensor_dev_attr_temp3_input.dev_attr.attr,
3300         &sensor_dev_attr_temp3_crit.dev_attr.attr,
3301         &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr,
3302         &sensor_dev_attr_temp1_emergency.dev_attr.attr,
3303         &sensor_dev_attr_temp2_emergency.dev_attr.attr,
3304         &sensor_dev_attr_temp3_emergency.dev_attr.attr,
3305         &sensor_dev_attr_temp1_label.dev_attr.attr,
3306         &sensor_dev_attr_temp2_label.dev_attr.attr,
3307         &sensor_dev_attr_temp3_label.dev_attr.attr,
3308         &sensor_dev_attr_pwm1.dev_attr.attr,
3309         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
3310         &sensor_dev_attr_pwm1_min.dev_attr.attr,
3311         &sensor_dev_attr_pwm1_max.dev_attr.attr,
3312         &sensor_dev_attr_fan1_input.dev_attr.attr,
3313         &sensor_dev_attr_fan1_min.dev_attr.attr,
3314         &sensor_dev_attr_fan1_max.dev_attr.attr,
3315         &sensor_dev_attr_fan1_target.dev_attr.attr,
3316         &sensor_dev_attr_fan1_enable.dev_attr.attr,
3317         &sensor_dev_attr_in0_input.dev_attr.attr,
3318         &sensor_dev_attr_in0_label.dev_attr.attr,
3319         &sensor_dev_attr_in1_input.dev_attr.attr,
3320         &sensor_dev_attr_in1_label.dev_attr.attr,
3321         &sensor_dev_attr_power1_average.dev_attr.attr,
3322         &sensor_dev_attr_power1_input.dev_attr.attr,
3323         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
3324         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
3325         &sensor_dev_attr_power1_cap.dev_attr.attr,
3326         &sensor_dev_attr_power1_cap_default.dev_attr.attr,
3327         &sensor_dev_attr_power1_label.dev_attr.attr,
3328         &sensor_dev_attr_power2_average.dev_attr.attr,
3329         &sensor_dev_attr_power2_cap_max.dev_attr.attr,
3330         &sensor_dev_attr_power2_cap_min.dev_attr.attr,
3331         &sensor_dev_attr_power2_cap.dev_attr.attr,
3332         &sensor_dev_attr_power2_cap_default.dev_attr.attr,
3333         &sensor_dev_attr_power2_label.dev_attr.attr,
3334         &sensor_dev_attr_freq1_input.dev_attr.attr,
3335         &sensor_dev_attr_freq1_label.dev_attr.attr,
3336         &sensor_dev_attr_freq2_input.dev_attr.attr,
3337         &sensor_dev_attr_freq2_label.dev_attr.attr,
3338         NULL
3339 };
3340
3341 static umode_t hwmon_attributes_visible(struct kobject *kobj,
3342                                         struct attribute *attr, int index)
3343 {
3344         struct device *dev = kobj_to_dev(kobj);
3345         struct amdgpu_device *adev = dev_get_drvdata(dev);
3346         umode_t effective_mode = attr->mode;
3347         uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);
3348         uint32_t tmp;
3349
3350         /* under pp one vf mode manage of hwmon attributes is not supported */
3351         if (amdgpu_sriov_is_pp_one_vf(adev))
3352                 effective_mode &= ~S_IWUSR;
3353
3354         /* Skip fan attributes if fan is not present */
3355         if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3356             attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3357             attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3358             attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3359             attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3360             attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3361             attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3362             attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3363             attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3364                 return 0;
3365
3366         /* Skip fan attributes on APU */
3367         if ((adev->flags & AMD_IS_APU) &&
3368             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3369              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3370              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3371              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3372              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3373              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3374              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3375              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3376              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3377                 return 0;
3378
3379         /* Skip crit temp on APU */
3380         if ((((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ)) ||
3381             (gc_ver == IP_VERSION(9, 4, 3))) &&
3382             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3383              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
3384                 return 0;
3385
3386         /* Skip limit attributes if DPM is not enabled */
3387         if (!adev->pm.dpm_enabled &&
3388             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3389              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
3390              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3391              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3392              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3393              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3394              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3395              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3396              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3397              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3398              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3399                 return 0;
3400
3401         /* mask fan attributes if we have no bindings for this asic to expose */
3402         if (((amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) &&
3403               attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
3404             ((amdgpu_dpm_get_fan_control_mode(adev, NULL) == -EOPNOTSUPP) &&
3405              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
3406                 effective_mode &= ~S_IRUGO;
3407
3408         if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) &&
3409               attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
3410               ((amdgpu_dpm_set_fan_control_mode(adev, U32_MAX) == -EOPNOTSUPP) &&
3411               attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
3412                 effective_mode &= ~S_IWUSR;
3413
3414         /* not implemented yet for APUs other than GC 10.3.1 (vangogh) and 9.4.3 */
3415         if (((adev->family == AMDGPU_FAMILY_SI) ||
3416              ((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(10, 3, 1)) &&
3417               (gc_ver != IP_VERSION(9, 4, 3)))) &&
3418             (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
3419              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr ||
3420              attr == &sensor_dev_attr_power1_cap.dev_attr.attr ||
3421              attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr))
3422                 return 0;
3423
3424         /* not implemented yet for APUs having < GC 9.3.0 (Renoir) */
3425         if (((adev->family == AMDGPU_FAMILY_SI) ||
3426              ((adev->flags & AMD_IS_APU) && (gc_ver < IP_VERSION(9, 3, 0)))) &&
3427             (attr == &sensor_dev_attr_power1_average.dev_attr.attr))
3428                 return 0;
3429
3430         /* not all products support both average and instantaneous */
3431         if (attr == &sensor_dev_attr_power1_average.dev_attr.attr &&
3432             amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_AVG_POWER, (void *)&tmp) == -EOPNOTSUPP)
3433                 return 0;
3434         if (attr == &sensor_dev_attr_power1_input.dev_attr.attr &&
3435             amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER, (void *)&tmp) == -EOPNOTSUPP)
3436                 return 0;
3437
3438         /* hide max/min values if we can't both query and manage the fan */
3439         if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) &&
3440               (amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) &&
3441               (amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) &&
3442               (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP)) &&
3443             (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3444              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
3445                 return 0;
3446
3447         if ((amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) &&
3448              (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP) &&
3449              (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3450              attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
3451                 return 0;
3452
3453         if ((adev->family == AMDGPU_FAMILY_SI ||        /* not implemented yet */
3454              adev->family == AMDGPU_FAMILY_KV ||        /* not implemented yet */
3455              (gc_ver == IP_VERSION(9, 4, 3))) &&
3456             (attr == &sensor_dev_attr_in0_input.dev_attr.attr ||
3457              attr == &sensor_dev_attr_in0_label.dev_attr.attr))
3458                 return 0;
3459
3460         /* only APUs other than gc 9,4,3 have vddnb */
3461         if ((!(adev->flags & AMD_IS_APU) || (gc_ver == IP_VERSION(9, 4, 3))) &&
3462             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
3463              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
3464                 return 0;
3465
3466         /* no mclk on APUs other than gc 9,4,3*/
3467         if (((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(9, 4, 3))) &&
3468             (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
3469              attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
3470                 return 0;
3471
3472         if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0)) &&
3473             (gc_ver != IP_VERSION(9, 4, 3)) &&
3474             (attr == &sensor_dev_attr_temp2_input.dev_attr.attr ||
3475              attr == &sensor_dev_attr_temp2_label.dev_attr.attr ||
3476              attr == &sensor_dev_attr_temp2_crit.dev_attr.attr ||
3477              attr == &sensor_dev_attr_temp3_input.dev_attr.attr ||
3478              attr == &sensor_dev_attr_temp3_label.dev_attr.attr ||
3479              attr == &sensor_dev_attr_temp3_crit.dev_attr.attr))
3480                 return 0;
3481
3482         /* hotspot temperature for gc 9,4,3*/
3483         if (gc_ver == IP_VERSION(9, 4, 3)) {
3484                 if (attr == &sensor_dev_attr_temp1_input.dev_attr.attr ||
3485                     attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
3486                     attr == &sensor_dev_attr_temp1_label.dev_attr.attr)
3487                         return 0;
3488
3489                 if (attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
3490                     attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr)
3491                         return attr->mode;
3492         }
3493
3494         /* only SOC15 dGPUs support hotspot and mem temperatures */
3495         if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0)) &&
3496             (attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr ||
3497              attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr ||
3498              attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
3499              attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
3500              attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr))
3501                 return 0;
3502
3503         /* only Vangogh has fast PPT limit and power labels */
3504         if (!(gc_ver == IP_VERSION(10, 3, 1)) &&
3505             (attr == &sensor_dev_attr_power2_average.dev_attr.attr ||
3506              attr == &sensor_dev_attr_power2_cap_max.dev_attr.attr ||
3507              attr == &sensor_dev_attr_power2_cap_min.dev_attr.attr ||
3508              attr == &sensor_dev_attr_power2_cap.dev_attr.attr ||
3509              attr == &sensor_dev_attr_power2_cap_default.dev_attr.attr ||
3510              attr == &sensor_dev_attr_power2_label.dev_attr.attr))
3511                 return 0;
3512
3513         return effective_mode;
3514 }
3515
3516 static const struct attribute_group hwmon_attrgroup = {
3517         .attrs = hwmon_attributes,
3518         .is_visible = hwmon_attributes_visible,
3519 };
3520
3521 static const struct attribute_group *hwmon_groups[] = {
3522         &hwmon_attrgroup,
3523         NULL
3524 };
3525
3526 static int amdgpu_retrieve_od_settings(struct amdgpu_device *adev,
3527                                        enum pp_clock_type od_type,
3528                                        char *buf)
3529 {
3530         int size = 0;
3531         int ret;
3532
3533         if (amdgpu_in_reset(adev))
3534                 return -EPERM;
3535         if (adev->in_suspend && !adev->in_runpm)
3536                 return -EPERM;
3537
3538         ret = pm_runtime_get_sync(adev->dev);
3539         if (ret < 0) {
3540                 pm_runtime_put_autosuspend(adev->dev);
3541                 return ret;
3542         }
3543
3544         size = amdgpu_dpm_print_clock_levels(adev, od_type, buf);
3545         if (size == 0)
3546                 size = sysfs_emit(buf, "\n");
3547
3548         pm_runtime_mark_last_busy(adev->dev);
3549         pm_runtime_put_autosuspend(adev->dev);
3550
3551         return size;
3552 }
3553
3554 static int parse_input_od_command_lines(const char *buf,
3555                                         size_t count,
3556                                         u32 *type,
3557                                         long *params,
3558                                         uint32_t *num_of_params)
3559 {
3560         const char delimiter[3] = {' ', '\n', '\0'};
3561         uint32_t parameter_size = 0;
3562         char buf_cpy[128] = {0};
3563         char *tmp_str, *sub_str;
3564         int ret;
3565
3566         if (count > sizeof(buf_cpy) - 1)
3567                 return -EINVAL;
3568
3569         memcpy(buf_cpy, buf, count);
3570         tmp_str = buf_cpy;
3571
3572         /* skip heading spaces */
3573         while (isspace(*tmp_str))
3574                 tmp_str++;
3575
3576         switch (*tmp_str) {
3577         case 'c':
3578                 *type = PP_OD_COMMIT_DPM_TABLE;
3579                 return 0;
3580         case 'r':
3581                 params[parameter_size] = *type;
3582                 *num_of_params = 1;
3583                 *type = PP_OD_RESTORE_DEFAULT_TABLE;
3584                 return 0;
3585         default:
3586                 break;
3587         }
3588
3589         while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
3590                 if (strlen(sub_str) == 0)
3591                         continue;
3592
3593                 ret = kstrtol(sub_str, 0, &params[parameter_size]);
3594                 if (ret)
3595                         return -EINVAL;
3596                 parameter_size++;
3597
3598                 while (isspace(*tmp_str))
3599                         tmp_str++;
3600         }
3601
3602         *num_of_params = parameter_size;
3603
3604         return 0;
3605 }
3606
3607 static int
3608 amdgpu_distribute_custom_od_settings(struct amdgpu_device *adev,
3609                                      enum PP_OD_DPM_TABLE_COMMAND cmd_type,
3610                                      const char *in_buf,
3611                                      size_t count)
3612 {
3613         uint32_t parameter_size = 0;
3614         long parameter[64];
3615         int ret;
3616
3617         if (amdgpu_in_reset(adev))
3618                 return -EPERM;
3619         if (adev->in_suspend && !adev->in_runpm)
3620                 return -EPERM;
3621
3622         ret = parse_input_od_command_lines(in_buf,
3623                                            count,
3624                                            &cmd_type,
3625                                            parameter,
3626                                            &parameter_size);
3627         if (ret)
3628                 return ret;
3629
3630         ret = pm_runtime_get_sync(adev->dev);
3631         if (ret < 0)
3632                 goto err_out0;
3633
3634         ret = amdgpu_dpm_odn_edit_dpm_table(adev,
3635                                             cmd_type,
3636                                             parameter,
3637                                             parameter_size);
3638         if (ret)
3639                 goto err_out1;
3640
3641         if (cmd_type == PP_OD_COMMIT_DPM_TABLE) {
3642                 ret = amdgpu_dpm_dispatch_task(adev,
3643                                                AMD_PP_TASK_READJUST_POWER_STATE,
3644                                                NULL);
3645                 if (ret)
3646                         goto err_out1;
3647         }
3648
3649         pm_runtime_mark_last_busy(adev->dev);
3650         pm_runtime_put_autosuspend(adev->dev);
3651
3652         return count;
3653
3654 err_out1:
3655         pm_runtime_mark_last_busy(adev->dev);
3656 err_out0:
3657         pm_runtime_put_autosuspend(adev->dev);
3658
3659         return ret;
3660 }
3661
3662 /**
3663  * DOC: fan_curve
3664  *
3665  * The amdgpu driver provides a sysfs API for checking and adjusting the fan
3666  * control curve line.
3667  *
3668  * Reading back the file shows you the current settings(temperature in Celsius
3669  * degree and fan speed in pwm) applied to every anchor point of the curve line
3670  * and their permitted ranges if changable.
3671  *
3672  * Writing a desired string(with the format like "anchor_point_index temperature
3673  * fan_speed_in_pwm") to the file, change the settings for the specific anchor
3674  * point accordingly.
3675  *
3676  * When you have finished the editing, write "c" (commit) to the file to commit
3677  * your changes.
3678  *
3679  * If you want to reset to the default value, write "r" (reset) to the file to
3680  * reset them
3681  *
3682  * There are two fan control modes supported: auto and manual. With auto mode,
3683  * PMFW handles the fan speed control(how fan speed reacts to ASIC temperature).
3684  * While with manual mode, users can set their own fan curve line as what
3685  * described here. Normally the ASIC is booted up with auto mode. Any
3686  * settings via this interface will switch the fan control to manual mode
3687  * implicitly.
3688  */
3689 static ssize_t fan_curve_show(struct kobject *kobj,
3690                               struct kobj_attribute *attr,
3691                               char *buf)
3692 {
3693         struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3694         struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3695
3696         return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_CURVE, buf);
3697 }
3698
3699 static ssize_t fan_curve_store(struct kobject *kobj,
3700                                struct kobj_attribute *attr,
3701                                const char *buf,
3702                                size_t count)
3703 {
3704         struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3705         struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3706
3707         return (ssize_t)amdgpu_distribute_custom_od_settings(adev,
3708                                                              PP_OD_EDIT_FAN_CURVE,
3709                                                              buf,
3710                                                              count);
3711 }
3712
3713 static umode_t fan_curve_visible(struct amdgpu_device *adev)
3714 {
3715         umode_t umode = 0000;
3716
3717         if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_CURVE_RETRIEVE)
3718                 umode |= S_IRUSR | S_IRGRP | S_IROTH;
3719
3720         if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_CURVE_SET)
3721                 umode |= S_IWUSR;
3722
3723         return umode;
3724 }
3725
3726 /**
3727  * DOC: acoustic_limit_rpm_threshold
3728  *
3729  * The amdgpu driver provides a sysfs API for checking and adjusting the
3730  * acoustic limit in RPM for fan control.
3731  *
3732  * Reading back the file shows you the current setting and the permitted
3733  * ranges if changable.
3734  *
3735  * Writing an integer to the file, change the setting accordingly.
3736  *
3737  * When you have finished the editing, write "c" (commit) to the file to commit
3738  * your changes.
3739  *
3740  * If you want to reset to the default value, write "r" (reset) to the file to
3741  * reset them
3742  *
3743  * This setting works under auto fan control mode only. It adjusts the PMFW's
3744  * behavior about the maximum speed in RPM the fan can spin. Setting via this
3745  * interface will switch the fan control to auto mode implicitly.
3746  */
3747 static ssize_t acoustic_limit_threshold_show(struct kobject *kobj,
3748                                              struct kobj_attribute *attr,
3749                                              char *buf)
3750 {
3751         struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3752         struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3753
3754         return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_ACOUSTIC_LIMIT, buf);
3755 }
3756
3757 static ssize_t acoustic_limit_threshold_store(struct kobject *kobj,
3758                                               struct kobj_attribute *attr,
3759                                               const char *buf,
3760                                               size_t count)
3761 {
3762         struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3763         struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3764
3765         return (ssize_t)amdgpu_distribute_custom_od_settings(adev,
3766                                                              PP_OD_EDIT_ACOUSTIC_LIMIT,
3767                                                              buf,
3768                                                              count);
3769 }
3770
3771 static umode_t acoustic_limit_threshold_visible(struct amdgpu_device *adev)
3772 {
3773         umode_t umode = 0000;
3774
3775         if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_RETRIEVE)
3776                 umode |= S_IRUSR | S_IRGRP | S_IROTH;
3777
3778         if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_SET)
3779                 umode |= S_IWUSR;
3780
3781         return umode;
3782 }
3783
3784 /**
3785  * DOC: acoustic_target_rpm_threshold
3786  *
3787  * The amdgpu driver provides a sysfs API for checking and adjusting the
3788  * acoustic target in RPM for fan control.
3789  *
3790  * Reading back the file shows you the current setting and the permitted
3791  * ranges if changable.
3792  *
3793  * Writing an integer to the file, change the setting accordingly.
3794  *
3795  * When you have finished the editing, write "c" (commit) to the file to commit
3796  * your changes.
3797  *
3798  * If you want to reset to the default value, write "r" (reset) to the file to
3799  * reset them
3800  *
3801  * This setting works under auto fan control mode only. It can co-exist with
3802  * other settings which can work also under auto mode. It adjusts the PMFW's
3803  * behavior about the maximum speed in RPM the fan can spin when ASIC
3804  * temperature is not greater than target temperature. Setting via this
3805  * interface will switch the fan control to auto mode implicitly.
3806  */
3807 static ssize_t acoustic_target_threshold_show(struct kobject *kobj,
3808                                               struct kobj_attribute *attr,
3809                                               char *buf)
3810 {
3811         struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3812         struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3813
3814         return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_ACOUSTIC_TARGET, buf);
3815 }
3816
3817 static ssize_t acoustic_target_threshold_store(struct kobject *kobj,
3818                                                struct kobj_attribute *attr,
3819                                                const char *buf,
3820                                                size_t count)
3821 {
3822         struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3823         struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3824
3825         return (ssize_t)amdgpu_distribute_custom_od_settings(adev,
3826                                                              PP_OD_EDIT_ACOUSTIC_TARGET,
3827                                                              buf,
3828                                                              count);
3829 }
3830
3831 static umode_t acoustic_target_threshold_visible(struct amdgpu_device *adev)
3832 {
3833         umode_t umode = 0000;
3834
3835         if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_RETRIEVE)
3836                 umode |= S_IRUSR | S_IRGRP | S_IROTH;
3837
3838         if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_SET)
3839                 umode |= S_IWUSR;
3840
3841         return umode;
3842 }
3843
3844 /**
3845  * DOC: fan_target_temperature
3846  *
3847  * The amdgpu driver provides a sysfs API for checking and adjusting the
3848  * target tempeature in Celsius degree for fan control.
3849  *
3850  * Reading back the file shows you the current setting and the permitted
3851  * ranges if changable.
3852  *
3853  * Writing an integer to the file, change the setting accordingly.
3854  *
3855  * When you have finished the editing, write "c" (commit) to the file to commit
3856  * your changes.
3857  *
3858  * If you want to reset to the default value, write "r" (reset) to the file to
3859  * reset them
3860  *
3861  * This setting works under auto fan control mode only. It can co-exist with
3862  * other settings which can work also under auto mode. Paring with the
3863  * acoustic_target_rpm_threshold setting, they define the maximum speed in
3864  * RPM the fan can spin when ASIC temperature is not greater than target
3865  * temperature. Setting via this interface will switch the fan control to
3866  * auto mode implicitly.
3867  */
3868 static ssize_t fan_target_temperature_show(struct kobject *kobj,
3869                                            struct kobj_attribute *attr,
3870                                            char *buf)
3871 {
3872         struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3873         struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3874
3875         return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_TARGET_TEMPERATURE, buf);
3876 }
3877
3878 static ssize_t fan_target_temperature_store(struct kobject *kobj,
3879                                             struct kobj_attribute *attr,
3880                                             const char *buf,
3881                                             size_t count)
3882 {
3883         struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3884         struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3885
3886         return (ssize_t)amdgpu_distribute_custom_od_settings(adev,
3887                                                              PP_OD_EDIT_FAN_TARGET_TEMPERATURE,
3888                                                              buf,
3889                                                              count);
3890 }
3891
3892 static umode_t fan_target_temperature_visible(struct amdgpu_device *adev)
3893 {
3894         umode_t umode = 0000;
3895
3896         if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_RETRIEVE)
3897                 umode |= S_IRUSR | S_IRGRP | S_IROTH;
3898
3899         if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_SET)
3900                 umode |= S_IWUSR;
3901
3902         return umode;
3903 }
3904
3905 /**
3906  * DOC: fan_minimum_pwm
3907  *
3908  * The amdgpu driver provides a sysfs API for checking and adjusting the
3909  * minimum fan speed in PWM.
3910  *
3911  * Reading back the file shows you the current setting and the permitted
3912  * ranges if changable.
3913  *
3914  * Writing an integer to the file, change the setting accordingly.
3915  *
3916  * When you have finished the editing, write "c" (commit) to the file to commit
3917  * your changes.
3918  *
3919  * If you want to reset to the default value, write "r" (reset) to the file to
3920  * reset them
3921  *
3922  * This setting works under auto fan control mode only. It can co-exist with
3923  * other settings which can work also under auto mode. It adjusts the PMFW's
3924  * behavior about the minimum fan speed in PWM the fan should spin. Setting
3925  * via this interface will switch the fan control to auto mode implicitly.
3926  */
3927 static ssize_t fan_minimum_pwm_show(struct kobject *kobj,
3928                                     struct kobj_attribute *attr,
3929                                     char *buf)
3930 {
3931         struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3932         struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3933
3934         return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_MINIMUM_PWM, buf);
3935 }
3936
3937 static ssize_t fan_minimum_pwm_store(struct kobject *kobj,
3938                                      struct kobj_attribute *attr,
3939                                      const char *buf,
3940                                      size_t count)
3941 {
3942         struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3943         struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3944
3945         return (ssize_t)amdgpu_distribute_custom_od_settings(adev,
3946                                                              PP_OD_EDIT_FAN_MINIMUM_PWM,
3947                                                              buf,
3948                                                              count);
3949 }
3950
3951 static umode_t fan_minimum_pwm_visible(struct amdgpu_device *adev)
3952 {
3953         umode_t umode = 0000;
3954
3955         if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_MINIMUM_PWM_RETRIEVE)
3956                 umode |= S_IRUSR | S_IRGRP | S_IROTH;
3957
3958         if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_MINIMUM_PWM_SET)
3959                 umode |= S_IWUSR;
3960
3961         return umode;
3962 }
3963
3964 static struct od_feature_set amdgpu_od_set = {
3965         .containers = {
3966                 [0] = {
3967                         .name = "fan_ctrl",
3968                         .sub_feature = {
3969                                 [0] = {
3970                                         .name = "fan_curve",
3971                                         .ops = {
3972                                                 .is_visible = fan_curve_visible,
3973                                                 .show = fan_curve_show,
3974                                                 .store = fan_curve_store,
3975                                         },
3976                                 },
3977                                 [1] = {
3978                                         .name = "acoustic_limit_rpm_threshold",
3979                                         .ops = {
3980                                                 .is_visible = acoustic_limit_threshold_visible,
3981                                                 .show = acoustic_limit_threshold_show,
3982                                                 .store = acoustic_limit_threshold_store,
3983                                         },
3984                                 },
3985                                 [2] = {
3986                                         .name = "acoustic_target_rpm_threshold",
3987                                         .ops = {
3988                                                 .is_visible = acoustic_target_threshold_visible,
3989                                                 .show = acoustic_target_threshold_show,
3990                                                 .store = acoustic_target_threshold_store,
3991                                         },
3992                                 },
3993                                 [3] = {
3994                                         .name = "fan_target_temperature",
3995                                         .ops = {
3996                                                 .is_visible = fan_target_temperature_visible,
3997                                                 .show = fan_target_temperature_show,
3998                                                 .store = fan_target_temperature_store,
3999                                         },
4000                                 },
4001                                 [4] = {
4002                                         .name = "fan_minimum_pwm",
4003                                         .ops = {
4004                                                 .is_visible = fan_minimum_pwm_visible,
4005                                                 .show = fan_minimum_pwm_show,
4006                                                 .store = fan_minimum_pwm_store,
4007                                         },
4008                                 },
4009                         },
4010                 },
4011         },
4012 };
4013
4014 static void od_kobj_release(struct kobject *kobj)
4015 {
4016         struct od_kobj *od_kobj = container_of(kobj, struct od_kobj, kobj);
4017
4018         kfree(od_kobj);
4019 }
4020
4021 static const struct kobj_type od_ktype = {
4022         .release        = od_kobj_release,
4023         .sysfs_ops      = &kobj_sysfs_ops,
4024 };
4025
4026 static void amdgpu_od_set_fini(struct amdgpu_device *adev)
4027 {
4028         struct od_kobj *container, *container_next;
4029         struct od_attribute *attribute, *attribute_next;
4030
4031         if (list_empty(&adev->pm.od_kobj_list))
4032                 return;
4033
4034         list_for_each_entry_safe(container, container_next,
4035                                  &adev->pm.od_kobj_list, entry) {
4036                 list_del(&container->entry);
4037
4038                 list_for_each_entry_safe(attribute, attribute_next,
4039                                          &container->attribute, entry) {
4040                         list_del(&attribute->entry);
4041                         sysfs_remove_file(&container->kobj,
4042                                           &attribute->attribute.attr);
4043                         kfree(attribute);
4044                 }
4045
4046                 kobject_put(&container->kobj);
4047         }
4048 }
4049
4050 static bool amdgpu_is_od_feature_supported(struct amdgpu_device *adev,
4051                                            struct od_feature_ops *feature_ops)
4052 {
4053         umode_t mode;
4054
4055         if (!feature_ops->is_visible)
4056                 return false;
4057
4058         /*
4059          * If the feature has no user read and write mode set,
4060          * we can assume the feature is actually not supported.(?)
4061          * And the revelant sysfs interface should not be exposed.
4062          */
4063         mode = feature_ops->is_visible(adev);
4064         if (mode & (S_IRUSR | S_IWUSR))
4065                 return true;
4066
4067         return false;
4068 }
4069
4070 static bool amdgpu_od_is_self_contained(struct amdgpu_device *adev,
4071                                         struct od_feature_container *container)
4072 {
4073         int i;
4074
4075         /*
4076          * If there is no valid entry within the container, the container
4077          * is recognized as a self contained container. And the valid entry
4078          * here means it has a valid naming and it is visible/supported by
4079          * the ASIC.
4080          */
4081         for (i = 0; i < ARRAY_SIZE(container->sub_feature); i++) {
4082                 if (container->sub_feature[i].name &&
4083                     amdgpu_is_od_feature_supported(adev,
4084                         &container->sub_feature[i].ops))
4085                         return false;
4086         }
4087
4088         return true;
4089 }
4090
4091 static int amdgpu_od_set_init(struct amdgpu_device *adev)
4092 {
4093         struct od_kobj *top_set, *sub_set;
4094         struct od_attribute *attribute;
4095         struct od_feature_container *container;
4096         struct od_feature_item *feature;
4097         int i, j;
4098         int ret;
4099
4100         /* Setup the top `gpu_od` directory which holds all other OD interfaces */
4101         top_set = kzalloc(sizeof(*top_set), GFP_KERNEL);
4102         if (!top_set)
4103                 return -ENOMEM;
4104         list_add(&top_set->entry, &adev->pm.od_kobj_list);
4105
4106         ret = kobject_init_and_add(&top_set->kobj,
4107                                    &od_ktype,
4108                                    &adev->dev->kobj,
4109                                    "%s",
4110                                    "gpu_od");
4111         if (ret)
4112                 goto err_out;
4113         INIT_LIST_HEAD(&top_set->attribute);
4114         top_set->priv = adev;
4115
4116         for (i = 0; i < ARRAY_SIZE(amdgpu_od_set.containers); i++) {
4117                 container = &amdgpu_od_set.containers[i];
4118
4119                 if (!container->name)
4120                         continue;
4121
4122                 /*
4123                  * If there is valid entries within the container, the container
4124                  * will be presented as a sub directory and all its holding entries
4125                  * will be presented as plain files under it.
4126                  * While if there is no valid entry within the container, the container
4127                  * itself will be presented as a plain file under top `gpu_od` directory.
4128                  */
4129                 if (amdgpu_od_is_self_contained(adev, container)) {
4130                         if (!amdgpu_is_od_feature_supported(adev,
4131                              &container->ops))
4132                                 continue;
4133
4134                         /*
4135                          * The container is presented as a plain file under top `gpu_od`
4136                          * directory.
4137                          */
4138                         attribute = kzalloc(sizeof(*attribute), GFP_KERNEL);
4139                         if (!attribute) {
4140                                 ret = -ENOMEM;
4141                                 goto err_out;
4142                         }
4143                         list_add(&attribute->entry, &top_set->attribute);
4144
4145                         attribute->attribute.attr.mode =
4146                                         container->ops.is_visible(adev);
4147                         attribute->attribute.attr.name = container->name;
4148                         attribute->attribute.show =
4149                                         container->ops.show;
4150                         attribute->attribute.store =
4151                                         container->ops.store;
4152                         ret = sysfs_create_file(&top_set->kobj,
4153                                                 &attribute->attribute.attr);
4154                         if (ret)
4155                                 goto err_out;
4156                 } else {
4157                         /* The container is presented as a sub directory. */
4158                         sub_set = kzalloc(sizeof(*sub_set), GFP_KERNEL);
4159                         if (!sub_set) {
4160                                 ret = -ENOMEM;
4161                                 goto err_out;
4162                         }
4163                         list_add(&sub_set->entry, &adev->pm.od_kobj_list);
4164
4165                         ret = kobject_init_and_add(&sub_set->kobj,
4166                                                    &od_ktype,
4167                                                    &top_set->kobj,
4168                                                    "%s",
4169                                                    container->name);
4170                         if (ret)
4171                                 goto err_out;
4172                         INIT_LIST_HEAD(&sub_set->attribute);
4173                         sub_set->priv = adev;
4174
4175                         for (j = 0; j < ARRAY_SIZE(container->sub_feature); j++) {
4176                                 feature = &container->sub_feature[j];
4177                                 if (!feature->name)
4178                                         continue;
4179
4180                                 if (!amdgpu_is_od_feature_supported(adev,
4181                                      &feature->ops))
4182                                         continue;
4183
4184                                 /*
4185                                  * With the container presented as a sub directory, the entry within
4186                                  * it is presented as a plain file under the sub directory.
4187                                  */
4188                                 attribute = kzalloc(sizeof(*attribute), GFP_KERNEL);
4189                                 if (!attribute) {
4190                                         ret = -ENOMEM;
4191                                         goto err_out;
4192                                 }
4193                                 list_add(&attribute->entry, &sub_set->attribute);
4194
4195                                 attribute->attribute.attr.mode =
4196                                                 feature->ops.is_visible(adev);
4197                                 attribute->attribute.attr.name = feature->name;
4198                                 attribute->attribute.show =
4199                                                 feature->ops.show;
4200                                 attribute->attribute.store =
4201                                                 feature->ops.store;
4202                                 ret = sysfs_create_file(&sub_set->kobj,
4203                                                         &attribute->attribute.attr);
4204                                 if (ret)
4205                                         goto err_out;
4206                         }
4207                 }
4208         }
4209
4210         return 0;
4211
4212 err_out:
4213         amdgpu_od_set_fini(adev);
4214
4215         return ret;
4216 }
4217
4218 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
4219 {
4220         enum amdgpu_sriov_vf_mode mode;
4221         uint32_t mask = 0;
4222         int ret;
4223
4224         if (adev->pm.sysfs_initialized)
4225                 return 0;
4226
4227         INIT_LIST_HEAD(&adev->pm.pm_attr_list);
4228
4229         if (adev->pm.dpm_enabled == 0)
4230                 return 0;
4231
4232         mode = amdgpu_virt_get_sriov_vf_mode(adev);
4233
4234         /* under multi-vf mode, the hwmon attributes are all not supported */
4235         if (mode != SRIOV_VF_MODE_MULTI_VF) {
4236                 adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
4237                                                                                                                 DRIVER_NAME, adev,
4238                                                                                                                 hwmon_groups);
4239                 if (IS_ERR(adev->pm.int_hwmon_dev)) {
4240                         ret = PTR_ERR(adev->pm.int_hwmon_dev);
4241                         dev_err(adev->dev, "Unable to register hwmon device: %d\n", ret);
4242                         return ret;
4243                 }
4244         }
4245
4246         switch (mode) {
4247         case SRIOV_VF_MODE_ONE_VF:
4248                 mask = ATTR_FLAG_ONEVF;
4249                 break;
4250         case SRIOV_VF_MODE_MULTI_VF:
4251                 mask = 0;
4252                 break;
4253         case SRIOV_VF_MODE_BARE_METAL:
4254         default:
4255                 mask = ATTR_FLAG_MASK_ALL;
4256                 break;
4257         }
4258
4259         ret = amdgpu_device_attr_create_groups(adev,
4260                                                amdgpu_device_attrs,
4261                                                ARRAY_SIZE(amdgpu_device_attrs),
4262                                                mask,
4263                                                &adev->pm.pm_attr_list);
4264         if (ret)
4265                 goto err_out0;
4266
4267         if (amdgpu_dpm_is_overdrive_supported(adev)) {
4268                 ret = amdgpu_od_set_init(adev);
4269                 if (ret)
4270                         goto err_out1;
4271         }
4272
4273         adev->pm.sysfs_initialized = true;
4274
4275         return 0;
4276
4277 err_out1:
4278         amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list);
4279 err_out0:
4280         if (adev->pm.int_hwmon_dev)
4281                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
4282
4283         return ret;
4284 }
4285
4286 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
4287 {
4288         amdgpu_od_set_fini(adev);
4289
4290         if (adev->pm.int_hwmon_dev)
4291                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
4292
4293         amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list);
4294 }
4295
4296 /*
4297  * Debugfs info
4298  */
4299 #if defined(CONFIG_DEBUG_FS)
4300
4301 static void amdgpu_debugfs_prints_cpu_info(struct seq_file *m,
4302                                            struct amdgpu_device *adev)
4303 {
4304         uint16_t *p_val;
4305         uint32_t size;
4306         int i;
4307         uint32_t num_cpu_cores = amdgpu_dpm_get_num_cpu_cores(adev);
4308
4309         if (amdgpu_dpm_is_cclk_dpm_supported(adev)) {
4310                 p_val = kcalloc(num_cpu_cores, sizeof(uint16_t),
4311                                 GFP_KERNEL);
4312
4313                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_CPU_CLK,
4314                                             (void *)p_val, &size)) {
4315                         for (i = 0; i < num_cpu_cores; i++)
4316                                 seq_printf(m, "\t%u MHz (CPU%d)\n",
4317                                            *(p_val + i), i);
4318                 }
4319
4320                 kfree(p_val);
4321         }
4322 }
4323
4324 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
4325 {
4326         uint32_t mp1_ver = amdgpu_ip_version(adev, MP1_HWIP, 0);
4327         uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);
4328         uint32_t value;
4329         uint64_t value64 = 0;
4330         uint32_t query = 0;
4331         int size;
4332
4333         /* GPU Clocks */
4334         size = sizeof(value);
4335         seq_printf(m, "GFX Clocks and Power:\n");
4336
4337         amdgpu_debugfs_prints_cpu_info(m, adev);
4338
4339         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
4340                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
4341         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
4342                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
4343         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
4344                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
4345         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
4346                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
4347         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
4348                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
4349         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
4350                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
4351         size = sizeof(uint32_t);
4352         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_AVG_POWER, (void *)&query, &size)) {
4353                 if (adev->flags & AMD_IS_APU)
4354                         seq_printf(m, "\t%u.%02u W (average SoC including CPU)\n", query >> 8, query & 0xff);
4355                 else
4356                         seq_printf(m, "\t%u.%02u W (average SoC)\n", query >> 8, query & 0xff);
4357         }
4358         size = sizeof(uint32_t);
4359         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER, (void *)&query, &size)) {
4360                 if (adev->flags & AMD_IS_APU)
4361                         seq_printf(m, "\t%u.%02u W (current SoC including CPU)\n", query >> 8, query & 0xff);
4362                 else
4363                         seq_printf(m, "\t%u.%02u W (current SoC)\n", query >> 8, query & 0xff);
4364         }
4365         size = sizeof(value);
4366         seq_printf(m, "\n");
4367
4368         /* GPU Temp */
4369         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
4370                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
4371
4372         /* GPU Load */
4373         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
4374                 seq_printf(m, "GPU Load: %u %%\n", value);
4375         /* MEM Load */
4376         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size))
4377                 seq_printf(m, "MEM Load: %u %%\n", value);
4378
4379         seq_printf(m, "\n");
4380
4381         /* SMC feature mask */
4382         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
4383                 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
4384
4385         /* ASICs greater than CHIP_VEGA20 supports these sensors */
4386         if (gc_ver != IP_VERSION(9, 4, 0) && mp1_ver > IP_VERSION(9, 0, 0)) {
4387                 /* VCN clocks */
4388                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) {
4389                         if (!value) {
4390                                 seq_printf(m, "VCN: Powered down\n");
4391                         } else {
4392                                 seq_printf(m, "VCN: Powered up\n");
4393                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
4394                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
4395                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
4396                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
4397                         }
4398                 }
4399                 seq_printf(m, "\n");
4400         } else {
4401                 /* UVD clocks */
4402                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
4403                         if (!value) {
4404                                 seq_printf(m, "UVD: Powered down\n");
4405                         } else {
4406                                 seq_printf(m, "UVD: Powered up\n");
4407                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
4408                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
4409                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
4410                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
4411                         }
4412                 }
4413                 seq_printf(m, "\n");
4414
4415                 /* VCE clocks */
4416                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
4417                         if (!value) {
4418                                 seq_printf(m, "VCE: Powered down\n");
4419                         } else {
4420                                 seq_printf(m, "VCE: Powered up\n");
4421                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
4422                                         seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
4423                         }
4424                 }
4425         }
4426
4427         return 0;
4428 }
4429
4430 static const struct cg_flag_name clocks[] = {
4431         {AMD_CG_SUPPORT_GFX_FGCG, "Graphics Fine Grain Clock Gating"},
4432         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
4433         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
4434         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
4435         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
4436         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
4437         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
4438         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
4439         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
4440         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
4441         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
4442         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
4443         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
4444         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
4445         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
4446         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
4447         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
4448         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
4449         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
4450         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
4451         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
4452         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
4453         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
4454         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
4455         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
4456         {AMD_CG_SUPPORT_VCN_MGCG, "VCN Medium Grain Clock Gating"},
4457         {AMD_CG_SUPPORT_HDP_DS, "Host Data Path Deep Sleep"},
4458         {AMD_CG_SUPPORT_HDP_SD, "Host Data Path Shutdown"},
4459         {AMD_CG_SUPPORT_IH_CG, "Interrupt Handler Clock Gating"},
4460         {AMD_CG_SUPPORT_JPEG_MGCG, "JPEG Medium Grain Clock Gating"},
4461         {AMD_CG_SUPPORT_REPEATER_FGCG, "Repeater Fine Grain Clock Gating"},
4462         {AMD_CG_SUPPORT_GFX_PERF_CLK, "Perfmon Clock Gating"},
4463         {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"},
4464         {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"},
4465         {0, NULL},
4466 };
4467
4468 static void amdgpu_parse_cg_state(struct seq_file *m, u64 flags)
4469 {
4470         int i;
4471
4472         for (i = 0; clocks[i].flag; i++)
4473                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
4474                            (flags & clocks[i].flag) ? "On" : "Off");
4475 }
4476
4477 static int amdgpu_debugfs_pm_info_show(struct seq_file *m, void *unused)
4478 {
4479         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
4480         struct drm_device *dev = adev_to_drm(adev);
4481         u64 flags = 0;
4482         int r;
4483
4484         if (amdgpu_in_reset(adev))
4485                 return -EPERM;
4486         if (adev->in_suspend && !adev->in_runpm)
4487                 return -EPERM;
4488
4489         r = pm_runtime_get_sync(dev->dev);
4490         if (r < 0) {
4491                 pm_runtime_put_autosuspend(dev->dev);
4492                 return r;
4493         }
4494
4495         if (amdgpu_dpm_debugfs_print_current_performance_level(adev, m)) {
4496                 r = amdgpu_debugfs_pm_info_pp(m, adev);
4497                 if (r)
4498                         goto out;
4499         }
4500
4501         amdgpu_device_ip_get_clockgating_state(adev, &flags);
4502
4503         seq_printf(m, "Clock Gating Flags Mask: 0x%llx\n", flags);
4504         amdgpu_parse_cg_state(m, flags);
4505         seq_printf(m, "\n");
4506
4507 out:
4508         pm_runtime_mark_last_busy(dev->dev);
4509         pm_runtime_put_autosuspend(dev->dev);
4510
4511         return r;
4512 }
4513
4514 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_pm_info);
4515
4516 /*
4517  * amdgpu_pm_priv_buffer_read - Read memory region allocated to FW
4518  *
4519  * Reads debug memory region allocated to PMFW
4520  */
4521 static ssize_t amdgpu_pm_prv_buffer_read(struct file *f, char __user *buf,
4522                                          size_t size, loff_t *pos)
4523 {
4524         struct amdgpu_device *adev = file_inode(f)->i_private;
4525         size_t smu_prv_buf_size;
4526         void *smu_prv_buf;
4527         int ret = 0;
4528
4529         if (amdgpu_in_reset(adev))
4530                 return -EPERM;
4531         if (adev->in_suspend && !adev->in_runpm)
4532                 return -EPERM;
4533
4534         ret = amdgpu_dpm_get_smu_prv_buf_details(adev, &smu_prv_buf, &smu_prv_buf_size);
4535         if (ret)
4536                 return ret;
4537
4538         if (!smu_prv_buf || !smu_prv_buf_size)
4539                 return -EINVAL;
4540
4541         return simple_read_from_buffer(buf, size, pos, smu_prv_buf,
4542                                        smu_prv_buf_size);
4543 }
4544
4545 static const struct file_operations amdgpu_debugfs_pm_prv_buffer_fops = {
4546         .owner = THIS_MODULE,
4547         .open = simple_open,
4548         .read = amdgpu_pm_prv_buffer_read,
4549         .llseek = default_llseek,
4550 };
4551
4552 #endif
4553
4554 void amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
4555 {
4556 #if defined(CONFIG_DEBUG_FS)
4557         struct drm_minor *minor = adev_to_drm(adev)->primary;
4558         struct dentry *root = minor->debugfs_root;
4559
4560         if (!adev->pm.dpm_enabled)
4561                 return;
4562
4563         debugfs_create_file("amdgpu_pm_info", 0444, root, adev,
4564                             &amdgpu_debugfs_pm_info_fops);
4565
4566         if (adev->pm.smu_prv_buffer_size > 0)
4567                 debugfs_create_file_size("amdgpu_pm_prv_buffer", 0444, root,
4568                                          adev,
4569                                          &amdgpu_debugfs_pm_prv_buffer_fops,
4570                                          adev->pm.smu_prv_buffer_size);
4571
4572         amdgpu_dpm_stb_debug_fs_init(adev);
4573 #endif
4574 }