drivers/gpu/drm/amd/include/kgd_pp_interface.h

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef __KGD_PP_INTERFACE_H__
  25 #define __KGD_PP_INTERFACE_H__
  26
  27 extern const struct amdgpu_ip_block_version pp_smu_ip_block;
  28 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
  29 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
  30 extern const struct amdgpu_ip_block_version smu_v13_0_ip_block;
  31 extern const struct amdgpu_ip_block_version smu_v14_0_ip_block;
  32
  33 enum smu_event_type {
  34         SMU_EVENT_RESET_COMPLETE = 0,
  35 };
  36
  37 struct amd_vce_state {
  38         /* vce clocks */
  39         u32 evclk;
  40         u32 ecclk;
  41         /* gpu clocks */
  42         u32 sclk;
  43         u32 mclk;
  44         u8 clk_idx;
  45         u8 pstate;
  46 };
  47
  48
  49 enum amd_dpm_forced_level {
  50         AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
  51         AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
  52         AMD_DPM_FORCED_LEVEL_LOW = 0x4,
  53         AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
  54         AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10,
  55         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20,
  56         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
  57         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
  58         AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
  59         AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200,
  60 };
  61
  62 enum amd_pm_state_type {
  63         /* not used for dpm */
  64         POWER_STATE_TYPE_DEFAULT,
  65         POWER_STATE_TYPE_POWERSAVE,
  66         /* user selectable states */
  67         POWER_STATE_TYPE_BATTERY,
  68         POWER_STATE_TYPE_BALANCED,
  69         POWER_STATE_TYPE_PERFORMANCE,
  70         /* internal states */
  71         POWER_STATE_TYPE_INTERNAL_UVD,
  72         POWER_STATE_TYPE_INTERNAL_UVD_SD,
  73         POWER_STATE_TYPE_INTERNAL_UVD_HD,
  74         POWER_STATE_TYPE_INTERNAL_UVD_HD2,
  75         POWER_STATE_TYPE_INTERNAL_UVD_MVC,
  76         POWER_STATE_TYPE_INTERNAL_BOOT,
  77         POWER_STATE_TYPE_INTERNAL_THERMAL,
  78         POWER_STATE_TYPE_INTERNAL_ACPI,
  79         POWER_STATE_TYPE_INTERNAL_ULV,
  80         POWER_STATE_TYPE_INTERNAL_3DPERF,
  81 };
  82
  83 #define AMD_MAX_VCE_LEVELS 6
  84
  85 enum amd_vce_level {
  86         AMD_VCE_LEVEL_AC_ALL = 0,     /* AC, All cases */
  87         AMD_VCE_LEVEL_DC_EE = 1,      /* DC, entropy encoding */
  88         AMD_VCE_LEVEL_DC_LL_LOW = 2,  /* DC, low latency queue, res <= 720 */
  89         AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
  90         AMD_VCE_LEVEL_DC_GP_LOW = 4,  /* DC, general purpose queue, res <= 720 */
  91         AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
  92 };
  93
  94 enum amd_fan_ctrl_mode {
  95         AMD_FAN_CTRL_NONE = 0,
  96         AMD_FAN_CTRL_MANUAL = 1,
  97         AMD_FAN_CTRL_AUTO = 2,
  98 };
  99
 100 enum pp_clock_type {
 101         PP_SCLK,
 102         PP_MCLK,
 103         PP_PCIE,
 104         PP_SOCCLK,
 105         PP_FCLK,
 106         PP_DCEFCLK,
 107         PP_VCLK,
 108         PP_VCLK1,
 109         PP_DCLK,
 110         PP_DCLK1,
 111         OD_SCLK,
 112         OD_MCLK,
 113         OD_VDDC_CURVE,
 114         OD_RANGE,
 115         OD_VDDGFX_OFFSET,
 116         OD_CCLK,
 117         OD_FAN_CURVE,
 118         OD_ACOUSTIC_LIMIT,
 119         OD_ACOUSTIC_TARGET,
 120         OD_FAN_TARGET_TEMPERATURE,
 121         OD_FAN_MINIMUM_PWM,
 122 };
 123
 124 enum amd_pp_sensors {
 125         AMDGPU_PP_SENSOR_GFX_SCLK = 0,
 126         AMDGPU_PP_SENSOR_CPU_CLK,
 127         AMDGPU_PP_SENSOR_VDDNB,
 128         AMDGPU_PP_SENSOR_VDDGFX,
 129         AMDGPU_PP_SENSOR_UVD_VCLK,
 130         AMDGPU_PP_SENSOR_UVD_DCLK,
 131         AMDGPU_PP_SENSOR_VCE_ECCLK,
 132         AMDGPU_PP_SENSOR_GPU_LOAD,
 133         AMDGPU_PP_SENSOR_MEM_LOAD,
 134         AMDGPU_PP_SENSOR_GFX_MCLK,
 135         AMDGPU_PP_SENSOR_GPU_TEMP,
 136         AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP,
 137         AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
 138         AMDGPU_PP_SENSOR_MEM_TEMP,
 139         AMDGPU_PP_SENSOR_VCE_POWER,
 140         AMDGPU_PP_SENSOR_UVD_POWER,
 141         AMDGPU_PP_SENSOR_GPU_AVG_POWER,
 142         AMDGPU_PP_SENSOR_GPU_INPUT_POWER,
 143         AMDGPU_PP_SENSOR_SS_APU_SHARE,
 144         AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
 145         AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
 146         AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
 147         AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK,
 148         AMDGPU_PP_SENSOR_MIN_FAN_RPM,
 149         AMDGPU_PP_SENSOR_MAX_FAN_RPM,
 150         AMDGPU_PP_SENSOR_VCN_POWER_STATE,
 151         AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK,
 152         AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK,
 153 };
 154
 155 enum amd_pp_task {
 156         AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
 157         AMD_PP_TASK_ENABLE_USER_STATE,
 158         AMD_PP_TASK_READJUST_POWER_STATE,
 159         AMD_PP_TASK_COMPLETE_INIT,
 160         AMD_PP_TASK_MAX
 161 };
 162
 163 enum PP_SMC_POWER_PROFILE {
 164         PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0,
 165         PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1,
 166         PP_SMC_POWER_PROFILE_POWERSAVING  = 0x2,
 167         PP_SMC_POWER_PROFILE_VIDEO        = 0x3,
 168         PP_SMC_POWER_PROFILE_VR           = 0x4,
 169         PP_SMC_POWER_PROFILE_COMPUTE      = 0x5,
 170         PP_SMC_POWER_PROFILE_CUSTOM       = 0x6,
 171         PP_SMC_POWER_PROFILE_WINDOW3D     = 0x7,
 172         PP_SMC_POWER_PROFILE_CAPPED       = 0x8,
 173         PP_SMC_POWER_PROFILE_UNCAPPED     = 0x9,
 174         PP_SMC_POWER_PROFILE_COUNT,
 175 };
 176
 177 extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT];
 178
 179
 180
 181 enum {
 182         PP_GROUP_UNKNOWN = 0,
 183         PP_GROUP_GFX = 1,
 184         PP_GROUP_SYS,
 185         PP_GROUP_MAX
 186 };
 187
 188 enum PP_OD_DPM_TABLE_COMMAND {
 189         PP_OD_EDIT_SCLK_VDDC_TABLE,
 190         PP_OD_EDIT_MCLK_VDDC_TABLE,
 191         PP_OD_EDIT_CCLK_VDDC_TABLE,
 192         PP_OD_EDIT_VDDC_CURVE,
 193         PP_OD_RESTORE_DEFAULT_TABLE,
 194         PP_OD_COMMIT_DPM_TABLE,
 195         PP_OD_EDIT_VDDGFX_OFFSET,
 196         PP_OD_EDIT_FAN_CURVE,
 197         PP_OD_EDIT_ACOUSTIC_LIMIT,
 198         PP_OD_EDIT_ACOUSTIC_TARGET,
 199         PP_OD_EDIT_FAN_TARGET_TEMPERATURE,
 200         PP_OD_EDIT_FAN_MINIMUM_PWM,
 201 };
 202
 203 struct pp_states_info {
 204         uint32_t nums;
 205         uint32_t states[16];
 206 };
 207
 208 enum PP_HWMON_TEMP {
 209         PP_TEMP_EDGE = 0,
 210         PP_TEMP_JUNCTION,
 211         PP_TEMP_MEM,
 212         PP_TEMP_MAX
 213 };
 214
 215 enum pp_mp1_state {
 216         PP_MP1_STATE_NONE,
 217         PP_MP1_STATE_SHUTDOWN,
 218         PP_MP1_STATE_UNLOAD,
 219         PP_MP1_STATE_RESET,
 220 };
 221
 222 enum pp_df_cstate {
 223         DF_CSTATE_DISALLOW = 0,
 224         DF_CSTATE_ALLOW,
 225 };
 226
 227 /**
 228  * DOC: amdgpu_pp_power
 229  *
 230  * APU power is managed to system-level requirements through the PPT
 231  * (package power tracking) feature. PPT is intended to limit power to the
 232  * requirements of the power source and could be dynamically updated to
 233  * maximize APU performance within the system power budget.
 234  *
 235  * Two types of power measurement can be requested, where supported, with
 236  * :c:type:`enum pp_power_type <pp_power_type>`.
 237  */
 238
 239 /**
 240  * enum pp_power_limit_level - Used to query the power limits
 241  *
 242  * @PP_PWR_LIMIT_MIN: Minimum Power Limit
 243  * @PP_PWR_LIMIT_CURRENT: Current Power Limit
 244  * @PP_PWR_LIMIT_DEFAULT: Default Power Limit
 245  * @PP_PWR_LIMIT_MAX: Maximum Power Limit
 246  */
 247 enum pp_power_limit_level
 248 {
 249         PP_PWR_LIMIT_MIN = -1,
 250         PP_PWR_LIMIT_CURRENT,
 251         PP_PWR_LIMIT_DEFAULT,
 252         PP_PWR_LIMIT_MAX,
 253 };
 254
 255 /**
 256  * enum pp_power_type - Used to specify the type of the requested power
 257  *
 258  * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant
 259  * moving average of APU power (default ~5000 ms).
 260  * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power,
 261  * where supported.
 262  */
 263 enum pp_power_type
 264 {
 265         PP_PWR_TYPE_SUSTAINED,
 266         PP_PWR_TYPE_FAST,
 267 };
 268
 269 enum pp_xgmi_plpd_mode {
 270         XGMI_PLPD_NONE = -1,
 271         XGMI_PLPD_DISALLOW,
 272         XGMI_PLPD_DEFAULT,
 273         XGMI_PLPD_OPTIMIZED,
 274         XGMI_PLPD_COUNT,
 275 };
 276
 277 #define PP_GROUP_MASK        0xF0000000
 278 #define PP_GROUP_SHIFT       28
 279
 280 #define PP_BLOCK_MASK        0x0FFFFF00
 281 #define PP_BLOCK_SHIFT       8
 282
 283 #define PP_BLOCK_GFX_CG         0x01
 284 #define PP_BLOCK_GFX_MG         0x02
 285 #define PP_BLOCK_GFX_3D         0x04
 286 #define PP_BLOCK_GFX_RLC        0x08
 287 #define PP_BLOCK_GFX_CP         0x10
 288 #define PP_BLOCK_SYS_BIF        0x01
 289 #define PP_BLOCK_SYS_MC         0x02
 290 #define PP_BLOCK_SYS_ROM        0x04
 291 #define PP_BLOCK_SYS_DRM        0x08
 292 #define PP_BLOCK_SYS_HDP        0x10
 293 #define PP_BLOCK_SYS_SDMA       0x20
 294
 295 #define PP_STATE_MASK           0x0000000F
 296 #define PP_STATE_SHIFT          0
 297 #define PP_STATE_SUPPORT_MASK   0x000000F0
 298 #define PP_STATE_SUPPORT_SHIFT  0
 299
 300 #define PP_STATE_CG             0x01
 301 #define PP_STATE_LS             0x02
 302 #define PP_STATE_DS             0x04
 303 #define PP_STATE_SD             0x08
 304 #define PP_STATE_SUPPORT_CG     0x10
 305 #define PP_STATE_SUPPORT_LS     0x20
 306 #define PP_STATE_SUPPORT_DS     0x40
 307 #define PP_STATE_SUPPORT_SD     0x80
 308
 309 #define PP_CG_MSG_ID(group, block, support, state) \
 310                 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \
 311                 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT)
 312
 313 #define XGMI_MODE_PSTATE_D3 0
 314 #define XGMI_MODE_PSTATE_D0 1
 315
 316 #define NUM_HBM_INSTANCES 4
 317 #define NUM_XGMI_LINKS 8
 318 #define MAX_GFX_CLKS 8
 319 #define MAX_CLKS 4
 320 #define NUM_VCN 4
 321 #define NUM_JPEG_ENG 32
 322
 323 struct seq_file;
 324 enum amd_pp_clock_type;
 325 struct amd_pp_simple_clock_info;
 326 struct amd_pp_display_configuration;
 327 struct amd_pp_clock_info;
 328 struct pp_display_clock_request;
 329 struct pp_clock_levels_with_voltage;
 330 struct pp_clock_levels_with_latency;
 331 struct amd_pp_clocks;
 332 struct pp_smu_wm_range_sets;
 333 struct pp_smu_nv_clock_table;
 334 struct dpm_clocks;
 335
 336 struct amd_pm_funcs {
 337 /* export for dpm on ci and si */
 338         int (*pre_set_power_state)(void *handle);
 339         int (*set_power_state)(void *handle);
 340         void (*post_set_power_state)(void *handle);
 341         void (*display_configuration_changed)(void *handle);
 342         void (*print_power_state)(void *handle, void *ps);
 343         bool (*vblank_too_short)(void *handle);
 344         void (*enable_bapm)(void *handle, bool enable);
 345         int (*check_state_equal)(void *handle,
 346                                 void  *cps,
 347                                 void  *rps,
 348                                 bool  *equal);
 349 /* export for sysfs */
 350         int (*set_fan_control_mode)(void *handle, u32 mode);
 351         int (*get_fan_control_mode)(void *handle, u32 *fan_mode);
 352         int (*set_fan_speed_pwm)(void *handle, u32 speed);
 353         int (*get_fan_speed_pwm)(void *handle, u32 *speed);
 354         int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
 355         int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
 356         int (*emit_clock_levels)(void *handle, enum pp_clock_type type, char *buf, int *offset);
 357         int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
 358         int (*get_sclk_od)(void *handle);
 359         int (*set_sclk_od)(void *handle, uint32_t value);
 360         int (*get_mclk_od)(void *handle);
 361         int (*set_mclk_od)(void *handle, uint32_t value);
 362         int (*read_sensor)(void *handle, int idx, void *value, int *size);
 363         int (*get_apu_thermal_limit)(void *handle, uint32_t *limit);
 364         int (*set_apu_thermal_limit)(void *handle, uint32_t limit);
 365         enum amd_dpm_forced_level (*get_performance_level)(void *handle);
 366         enum amd_pm_state_type (*get_current_power_state)(void *handle);
 367         int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
 368         int (*set_fan_speed_rpm)(void *handle, uint32_t rpm);
 369         int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
 370         int (*get_pp_table)(void *handle, char **table);
 371         int (*set_pp_table)(void *handle, const char *buf, size_t size);
 372         void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m);
 373         int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en);
 374 /* export to amdgpu */
 375         struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx);
 376         int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
 377                         enum amd_pm_state_type *user_state);
 378         int (*load_firmware)(void *handle);
 379         int (*wait_for_fw_loading_complete)(void *handle);
 380         int (*set_powergating_by_smu)(void *handle,
 381                                 uint32_t block_type, bool gate);
 382         int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
 383         int (*set_power_limit)(void *handle, uint32_t n);
 384         int (*get_power_limit)(void *handle, uint32_t *limit,
 385                         enum pp_power_limit_level pp_limit_level,
 386                         enum pp_power_type power_type);
 387         int (*get_power_profile_mode)(void *handle, char *buf);
 388         int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
 389         int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size);
 390         int (*odn_edit_dpm_table)(void *handle, enum PP_OD_DPM_TABLE_COMMAND type,
 391                                   long *input, uint32_t size);
 392         int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state);
 393         int (*smu_i2c_bus_access)(void *handle, bool acquire);
 394         int (*gfx_state_change_set)(void *handle, uint32_t state);
 395 /* export to DC */
 396         u32 (*get_sclk)(void *handle, bool low);
 397         u32 (*get_mclk)(void *handle, bool low);
 398         int (*display_configuration_change)(void *handle,
 399                 const struct amd_pp_display_configuration *input);
 400         int (*get_display_power_level)(void *handle,
 401                 struct amd_pp_simple_clock_info *output);
 402         int (*get_current_clocks)(void *handle,
 403                 struct amd_pp_clock_info *clocks);
 404         int (*get_clock_by_type)(void *handle,
 405                 enum amd_pp_clock_type type,
 406                 struct amd_pp_clocks *clocks);
 407         int (*get_clock_by_type_with_latency)(void *handle,
 408                 enum amd_pp_clock_type type,
 409                 struct pp_clock_levels_with_latency *clocks);
 410         int (*get_clock_by_type_with_voltage)(void *handle,
 411                 enum amd_pp_clock_type type,
 412                 struct pp_clock_levels_with_voltage *clocks);
 413         int (*set_watermarks_for_clocks_ranges)(void *handle,
 414                                                 void *clock_ranges);
 415         int (*display_clock_voltage_request)(void *handle,
 416                                 struct pp_display_clock_request *clock);
 417         int (*get_display_mode_validation_clocks)(void *handle,
 418                 struct amd_pp_simple_clock_info *clocks);
 419         int (*notify_smu_enable_pwe)(void *handle);
 420         int (*enable_mgpu_fan_boost)(void *handle);
 421         int (*set_active_display_count)(void *handle, uint32_t count);
 422         int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock);
 423         int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock);
 424         int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock);
 425         bool (*get_asic_baco_capability)(void *handle);
 426         int (*get_asic_baco_state)(void *handle, int *state);
 427         int (*set_asic_baco_state)(void *handle, int state);
 428         int (*get_ppfeature_status)(void *handle, char *buf);
 429         int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks);
 430         int (*asic_reset_mode_2)(void *handle);
 431         int (*asic_reset_enable_gfx_features)(void *handle);
 432         int (*set_df_cstate)(void *handle, enum pp_df_cstate state);
 433         int (*set_xgmi_pstate)(void *handle, uint32_t pstate);
 434         ssize_t (*get_gpu_metrics)(void *handle, void **table);
 435         ssize_t (*get_pm_metrics)(void *handle, void *pmmetrics, size_t size);
 436         int (*set_watermarks_for_clock_ranges)(void *handle,
 437                                                struct pp_smu_wm_range_sets *ranges);
 438         int (*display_disable_memory_clock_switch)(void *handle,
 439                                                    bool disable_memory_clock_switch);
 440         int (*get_max_sustainable_clocks_by_dc)(void *handle,
 441                                                 struct pp_smu_nv_clock_table *max_clocks);
 442         int (*get_uclk_dpm_states)(void *handle,
 443                                    unsigned int *clock_values_in_khz,
 444                                    unsigned int *num_states);
 445         int (*get_dpm_clock_table)(void *handle,
 446                                    struct dpm_clocks *clock_table);
 447         int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size);
 448         void (*pm_compute_clocks)(void *handle);
 449         int (*notify_rlc_state)(void *handle, bool en);
 450 };
 451
 452 struct metrics_table_header {
 453         uint16_t                        structure_size;
 454         uint8_t                         format_revision;
 455         uint8_t                         content_revision;
 456 };
 457
 458 /*
 459  * gpu_metrics_v1_0 is not recommended as it's not naturally aligned.
 460  * Use gpu_metrics_v1_1 or later instead.
 461  */
 462 struct gpu_metrics_v1_0 {
 463         struct metrics_table_header     common_header;
 464
 465         /* Driver attached timestamp (in ns) */
 466         uint64_t                        system_clock_counter;
 467
 468         /* Temperature */
 469         uint16_t                        temperature_edge;
 470         uint16_t                        temperature_hotspot;
 471         uint16_t                        temperature_mem;
 472         uint16_t                        temperature_vrgfx;
 473         uint16_t                        temperature_vrsoc;
 474         uint16_t                        temperature_vrmem;
 475
 476         /* Utilization */
 477         uint16_t                        average_gfx_activity;
 478         uint16_t                        average_umc_activity; // memory controller
 479         uint16_t                        average_mm_activity; // UVD or VCN
 480
 481         /* Power/Energy */
 482         uint16_t                        average_socket_power;
 483         uint32_t                        energy_accumulator;
 484
 485         /* Average clocks */
 486         uint16_t                        average_gfxclk_frequency;
 487         uint16_t                        average_socclk_frequency;
 488         uint16_t                        average_uclk_frequency;
 489         uint16_t                        average_vclk0_frequency;
 490         uint16_t                        average_dclk0_frequency;
 491         uint16_t                        average_vclk1_frequency;
 492         uint16_t                        average_dclk1_frequency;
 493
 494         /* Current clocks */
 495         uint16_t                        current_gfxclk;
 496         uint16_t                        current_socclk;
 497         uint16_t                        current_uclk;
 498         uint16_t                        current_vclk0;
 499         uint16_t                        current_dclk0;
 500         uint16_t                        current_vclk1;
 501         uint16_t                        current_dclk1;
 502
 503         /* Throttle status */
 504         uint32_t                        throttle_status;
 505
 506         /* Fans */
 507         uint16_t                        current_fan_speed;
 508
 509         /* Link width/speed */
 510         uint8_t                         pcie_link_width;
 511         uint8_t                         pcie_link_speed; // in 0.1 GT/s
 512 };
 513
 514 struct gpu_metrics_v1_1 {
 515         struct metrics_table_header     common_header;
 516
 517         /* Temperature */
 518         uint16_t                        temperature_edge;
 519         uint16_t                        temperature_hotspot;
 520         uint16_t                        temperature_mem;
 521         uint16_t                        temperature_vrgfx;
 522         uint16_t                        temperature_vrsoc;
 523         uint16_t                        temperature_vrmem;
 524
 525         /* Utilization */
 526         uint16_t                        average_gfx_activity;
 527         uint16_t                        average_umc_activity; // memory controller
 528         uint16_t                        average_mm_activity; // UVD or VCN
 529
 530         /* Power/Energy */
 531         uint16_t                        average_socket_power;
 532         uint64_t                        energy_accumulator;
 533
 534         /* Driver attached timestamp (in ns) */
 535         uint64_t                        system_clock_counter;
 536
 537         /* Average clocks */
 538         uint16_t                        average_gfxclk_frequency;
 539         uint16_t                        average_socclk_frequency;
 540         uint16_t                        average_uclk_frequency;
 541         uint16_t                        average_vclk0_frequency;
 542         uint16_t                        average_dclk0_frequency;
 543         uint16_t                        average_vclk1_frequency;
 544         uint16_t                        average_dclk1_frequency;
 545
 546         /* Current clocks */
 547         uint16_t                        current_gfxclk;
 548         uint16_t                        current_socclk;
 549         uint16_t                        current_uclk;
 550         uint16_t                        current_vclk0;
 551         uint16_t                        current_dclk0;
 552         uint16_t                        current_vclk1;
 553         uint16_t                        current_dclk1;
 554
 555         /* Throttle status */
 556         uint32_t                        throttle_status;
 557
 558         /* Fans */
 559         uint16_t                        current_fan_speed;
 560
 561         /* Link width/speed */
 562         uint16_t                        pcie_link_width;
 563         uint16_t                        pcie_link_speed; // in 0.1 GT/s
 564
 565         uint16_t                        padding;
 566
 567         uint32_t                        gfx_activity_acc;
 568         uint32_t                        mem_activity_acc;
 569
 570         uint16_t                        temperature_hbm[NUM_HBM_INSTANCES];
 571 };
 572
 573 struct gpu_metrics_v1_2 {
 574         struct metrics_table_header     common_header;
 575
 576         /* Temperature */
 577         uint16_t                        temperature_edge;
 578         uint16_t                        temperature_hotspot;
 579         uint16_t                        temperature_mem;
 580         uint16_t                        temperature_vrgfx;
 581         uint16_t                        temperature_vrsoc;
 582         uint16_t                        temperature_vrmem;
 583
 584         /* Utilization */
 585         uint16_t                        average_gfx_activity;
 586         uint16_t                        average_umc_activity; // memory controller
 587         uint16_t                        average_mm_activity; // UVD or VCN
 588
 589         /* Power/Energy */
 590         uint16_t                        average_socket_power;
 591         uint64_t                        energy_accumulator;
 592
 593         /* Driver attached timestamp (in ns) */
 594         uint64_t                        system_clock_counter;
 595
 596         /* Average clocks */
 597         uint16_t                        average_gfxclk_frequency;
 598         uint16_t                        average_socclk_frequency;
 599         uint16_t                        average_uclk_frequency;
 600         uint16_t                        average_vclk0_frequency;
 601         uint16_t                        average_dclk0_frequency;
 602         uint16_t                        average_vclk1_frequency;
 603         uint16_t                        average_dclk1_frequency;
 604
 605         /* Current clocks */
 606         uint16_t                        current_gfxclk;
 607         uint16_t                        current_socclk;
 608         uint16_t                        current_uclk;
 609         uint16_t                        current_vclk0;
 610         uint16_t                        current_dclk0;
 611         uint16_t                        current_vclk1;
 612         uint16_t                        current_dclk1;
 613
 614         /* Throttle status (ASIC dependent) */
 615         uint32_t                        throttle_status;
 616
 617         /* Fans */
 618         uint16_t                        current_fan_speed;
 619
 620         /* Link width/speed */
 621         uint16_t                        pcie_link_width;
 622         uint16_t                        pcie_link_speed; // in 0.1 GT/s
 623
 624         uint16_t                        padding;
 625
 626         uint32_t                        gfx_activity_acc;
 627         uint32_t                        mem_activity_acc;
 628
 629         uint16_t                        temperature_hbm[NUM_HBM_INSTANCES];
 630
 631         /* PMFW attached timestamp (10ns resolution) */
 632         uint64_t                        firmware_timestamp;
 633 };
 634
 635 struct gpu_metrics_v1_3 {
 636         struct metrics_table_header     common_header;
 637
 638         /* Temperature */
 639         uint16_t                        temperature_edge;
 640         uint16_t                        temperature_hotspot;
 641         uint16_t                        temperature_mem;
 642         uint16_t                        temperature_vrgfx;
 643         uint16_t                        temperature_vrsoc;
 644         uint16_t                        temperature_vrmem;
 645
 646         /* Utilization */
 647         uint16_t                        average_gfx_activity;
 648         uint16_t                        average_umc_activity; // memory controller
 649         uint16_t                        average_mm_activity; // UVD or VCN
 650
 651         /* Power/Energy */
 652         uint16_t                        average_socket_power;
 653         uint64_t                        energy_accumulator;
 654
 655         /* Driver attached timestamp (in ns) */
 656         uint64_t                        system_clock_counter;
 657
 658         /* Average clocks */
 659         uint16_t                        average_gfxclk_frequency;
 660         uint16_t                        average_socclk_frequency;
 661         uint16_t                        average_uclk_frequency;
 662         uint16_t                        average_vclk0_frequency;
 663         uint16_t                        average_dclk0_frequency;
 664         uint16_t                        average_vclk1_frequency;
 665         uint16_t                        average_dclk1_frequency;
 666
 667         /* Current clocks */
 668         uint16_t                        current_gfxclk;
 669         uint16_t                        current_socclk;
 670         uint16_t                        current_uclk;
 671         uint16_t                        current_vclk0;
 672         uint16_t                        current_dclk0;
 673         uint16_t                        current_vclk1;
 674         uint16_t                        current_dclk1;
 675
 676         /* Throttle status */
 677         uint32_t                        throttle_status;
 678
 679         /* Fans */
 680         uint16_t                        current_fan_speed;
 681
 682         /* Link width/speed */
 683         uint16_t                        pcie_link_width;
 684         uint16_t                        pcie_link_speed; // in 0.1 GT/s
 685
 686         uint16_t                        padding;
 687
 688         uint32_t                        gfx_activity_acc;
 689         uint32_t                        mem_activity_acc;
 690
 691         uint16_t                        temperature_hbm[NUM_HBM_INSTANCES];
 692
 693         /* PMFW attached timestamp (10ns resolution) */
 694         uint64_t                        firmware_timestamp;
 695
 696         /* Voltage (mV) */
 697         uint16_t                        voltage_soc;
 698         uint16_t                        voltage_gfx;
 699         uint16_t                        voltage_mem;
 700
 701         uint16_t                        padding1;
 702
 703         /* Throttle status (ASIC independent) */
 704         uint64_t                        indep_throttle_status;
 705 };
 706
 707 struct gpu_metrics_v1_4 {
 708         struct metrics_table_header     common_header;
 709
 710         /* Temperature (Celsius) */
 711         uint16_t                        temperature_hotspot;
 712         uint16_t                        temperature_mem;
 713         uint16_t                        temperature_vrsoc;
 714
 715         /* Power (Watts) */
 716         uint16_t                        curr_socket_power;
 717
 718         /* Utilization (%) */
 719         uint16_t                        average_gfx_activity;
 720         uint16_t                        average_umc_activity; // memory controller
 721         uint16_t                        vcn_activity[NUM_VCN];
 722
 723         /* Energy (15.259uJ (2^-16) units) */
 724         uint64_t                        energy_accumulator;
 725
 726         /* Driver attached timestamp (in ns) */
 727         uint64_t                        system_clock_counter;
 728
 729         /* Throttle status */
 730         uint32_t                        throttle_status;
 731
 732         /* Clock Lock Status. Each bit corresponds to clock instance */
 733         uint32_t                        gfxclk_lock_status;
 734
 735         /* Link width (number of lanes) and speed (in 0.1 GT/s) */
 736         uint16_t                        pcie_link_width;
 737         uint16_t                        pcie_link_speed;
 738
 739         /* XGMI bus width and bitrate (in Gbps) */
 740         uint16_t                        xgmi_link_width;
 741         uint16_t                        xgmi_link_speed;
 742
 743         /* Utilization Accumulated (%) */
 744         uint32_t                        gfx_activity_acc;
 745         uint32_t                        mem_activity_acc;
 746
 747         /*PCIE accumulated bandwidth (GB/sec) */
 748         uint64_t                        pcie_bandwidth_acc;
 749
 750         /*PCIE instantaneous bandwidth (GB/sec) */
 751         uint64_t                        pcie_bandwidth_inst;
 752
 753         /* PCIE L0 to recovery state transition accumulated count */
 754         uint64_t                        pcie_l0_to_recov_count_acc;
 755
 756         /* PCIE replay accumulated count */
 757         uint64_t                        pcie_replay_count_acc;
 758
 759         /* PCIE replay rollover accumulated count */
 760         uint64_t                        pcie_replay_rover_count_acc;
 761
 762         /* XGMI accumulated data transfer size(KiloBytes) */
 763         uint64_t                        xgmi_read_data_acc[NUM_XGMI_LINKS];
 764         uint64_t                        xgmi_write_data_acc[NUM_XGMI_LINKS];
 765
 766         /* PMFW attached timestamp (10ns resolution) */
 767         uint64_t                        firmware_timestamp;
 768
 769         /* Current clocks (Mhz) */
 770         uint16_t                        current_gfxclk[MAX_GFX_CLKS];
 771         uint16_t                        current_socclk[MAX_CLKS];
 772         uint16_t                        current_vclk0[MAX_CLKS];
 773         uint16_t                        current_dclk0[MAX_CLKS];
 774         uint16_t                        current_uclk;
 775
 776         uint16_t                        padding;
 777 };
 778
 779 struct gpu_metrics_v1_5 {
 780         struct metrics_table_header     common_header;
 781
 782         /* Temperature (Celsius) */
 783         uint16_t                        temperature_hotspot;
 784         uint16_t                        temperature_mem;
 785         uint16_t                        temperature_vrsoc;
 786
 787         /* Power (Watts) */
 788         uint16_t                        curr_socket_power;
 789
 790         /* Utilization (%) */
 791         uint16_t                        average_gfx_activity;
 792         uint16_t                        average_umc_activity; // memory controller
 793         uint16_t                        vcn_activity[NUM_VCN];
 794         uint16_t                        jpeg_activity[NUM_JPEG_ENG];
 795
 796         /* Energy (15.259uJ (2^-16) units) */
 797         uint64_t                        energy_accumulator;
 798
 799         /* Driver attached timestamp (in ns) */
 800         uint64_t                        system_clock_counter;
 801
 802         /* Throttle status */
 803         uint32_t                        throttle_status;
 804
 805         /* Clock Lock Status. Each bit corresponds to clock instance */
 806         uint32_t                        gfxclk_lock_status;
 807
 808         /* Link width (number of lanes) and speed (in 0.1 GT/s) */
 809         uint16_t                        pcie_link_width;
 810         uint16_t                        pcie_link_speed;
 811
 812         /* XGMI bus width and bitrate (in Gbps) */
 813         uint16_t                        xgmi_link_width;
 814         uint16_t                        xgmi_link_speed;
 815
 816         /* Utilization Accumulated (%) */
 817         uint32_t                        gfx_activity_acc;
 818         uint32_t                        mem_activity_acc;
 819
 820         /*PCIE accumulated bandwidth (GB/sec) */
 821         uint64_t                        pcie_bandwidth_acc;
 822
 823         /*PCIE instantaneous bandwidth (GB/sec) */
 824         uint64_t                        pcie_bandwidth_inst;
 825
 826         /* PCIE L0 to recovery state transition accumulated count */
 827         uint64_t                        pcie_l0_to_recov_count_acc;
 828
 829         /* PCIE replay accumulated count */
 830         uint64_t                        pcie_replay_count_acc;
 831
 832         /* PCIE replay rollover accumulated count */
 833         uint64_t                        pcie_replay_rover_count_acc;
 834
 835         /* PCIE NAK sent  accumulated count */
 836         uint32_t                        pcie_nak_sent_count_acc;
 837
 838         /* PCIE NAK received accumulated count */
 839         uint32_t                        pcie_nak_rcvd_count_acc;
 840
 841         /* XGMI accumulated data transfer size(KiloBytes) */
 842         uint64_t                        xgmi_read_data_acc[NUM_XGMI_LINKS];
 843         uint64_t                        xgmi_write_data_acc[NUM_XGMI_LINKS];
 844
 845         /* PMFW attached timestamp (10ns resolution) */
 846         uint64_t                        firmware_timestamp;
 847
 848         /* Current clocks (Mhz) */
 849         uint16_t                        current_gfxclk[MAX_GFX_CLKS];
 850         uint16_t                        current_socclk[MAX_CLKS];
 851         uint16_t                        current_vclk0[MAX_CLKS];
 852         uint16_t                        current_dclk0[MAX_CLKS];
 853         uint16_t                        current_uclk;
 854
 855         uint16_t                        padding;
 856 };
 857
 858 /*
 859  * gpu_metrics_v2_0 is not recommended as it's not naturally aligned.
 860  * Use gpu_metrics_v2_1 or later instead.
 861  */
 862 struct gpu_metrics_v2_0 {
 863         struct metrics_table_header     common_header;
 864
 865         /* Driver attached timestamp (in ns) */
 866         uint64_t                        system_clock_counter;
 867
 868         /* Temperature */
 869         uint16_t                        temperature_gfx; // gfx temperature on APUs
 870         uint16_t                        temperature_soc; // soc temperature on APUs
 871         uint16_t                        temperature_core[8]; // CPU core temperature on APUs
 872         uint16_t                        temperature_l3[2];
 873
 874         /* Utilization */
 875         uint16_t                        average_gfx_activity;
 876         uint16_t                        average_mm_activity; // UVD or VCN
 877
 878         /* Power/Energy */
 879         uint16_t                        average_socket_power; // dGPU + APU power on A + A platform
 880         uint16_t                        average_cpu_power;
 881         uint16_t                        average_soc_power;
 882         uint16_t                        average_gfx_power;
 883         uint16_t                        average_core_power[8]; // CPU core power on APUs
 884
 885         /* Average clocks */
 886         uint16_t                        average_gfxclk_frequency;
 887         uint16_t                        average_socclk_frequency;
 888         uint16_t                        average_uclk_frequency;
 889         uint16_t                        average_fclk_frequency;
 890         uint16_t                        average_vclk_frequency;
 891         uint16_t                        average_dclk_frequency;
 892
 893         /* Current clocks */
 894         uint16_t                        current_gfxclk;
 895         uint16_t                        current_socclk;
 896         uint16_t                        current_uclk;
 897         uint16_t                        current_fclk;
 898         uint16_t                        current_vclk;
 899         uint16_t                        current_dclk;
 900         uint16_t                        current_coreclk[8]; // CPU core clocks
 901         uint16_t                        current_l3clk[2];
 902
 903         /* Throttle status */
 904         uint32_t                        throttle_status;
 905
 906         /* Fans */
 907         uint16_t                        fan_pwm;
 908
 909         uint16_t                        padding;
 910 };
 911
 912 struct gpu_metrics_v2_1 {
 913         struct metrics_table_header     common_header;
 914
 915         /* Temperature */
 916         uint16_t                        temperature_gfx; // gfx temperature on APUs
 917         uint16_t                        temperature_soc; // soc temperature on APUs
 918         uint16_t                        temperature_core[8]; // CPU core temperature on APUs
 919         uint16_t                        temperature_l3[2];
 920
 921         /* Utilization */
 922         uint16_t                        average_gfx_activity;
 923         uint16_t                        average_mm_activity; // UVD or VCN
 924
 925         /* Driver attached timestamp (in ns) */
 926         uint64_t                        system_clock_counter;
 927
 928         /* Power/Energy */
 929         uint16_t                        average_socket_power; // dGPU + APU power on A + A platform
 930         uint16_t                        average_cpu_power;
 931         uint16_t                        average_soc_power;
 932         uint16_t                        average_gfx_power;
 933         uint16_t                        average_core_power[8]; // CPU core power on APUs
 934
 935         /* Average clocks */
 936         uint16_t                        average_gfxclk_frequency;
 937         uint16_t                        average_socclk_frequency;
 938         uint16_t                        average_uclk_frequency;
 939         uint16_t                        average_fclk_frequency;
 940         uint16_t                        average_vclk_frequency;
 941         uint16_t                        average_dclk_frequency;
 942
 943         /* Current clocks */
 944         uint16_t                        current_gfxclk;
 945         uint16_t                        current_socclk;
 946         uint16_t                        current_uclk;
 947         uint16_t                        current_fclk;
 948         uint16_t                        current_vclk;
 949         uint16_t                        current_dclk;
 950         uint16_t                        current_coreclk[8]; // CPU core clocks
 951         uint16_t                        current_l3clk[2];
 952
 953         /* Throttle status */
 954         uint32_t                        throttle_status;
 955
 956         /* Fans */
 957         uint16_t                        fan_pwm;
 958
 959         uint16_t                        padding[3];
 960 };
 961
 962 struct gpu_metrics_v2_2 {
 963         struct metrics_table_header     common_header;
 964
 965         /* Temperature */
 966         uint16_t                        temperature_gfx; // gfx temperature on APUs
 967         uint16_t                        temperature_soc; // soc temperature on APUs
 968         uint16_t                        temperature_core[8]; // CPU core temperature on APUs
 969         uint16_t                        temperature_l3[2];
 970
 971         /* Utilization */
 972         uint16_t                        average_gfx_activity;
 973         uint16_t                        average_mm_activity; // UVD or VCN
 974
 975         /* Driver attached timestamp (in ns) */
 976         uint64_t                        system_clock_counter;
 977
 978         /* Power/Energy */
 979         uint16_t                        average_socket_power; // dGPU + APU power on A + A platform
 980         uint16_t                        average_cpu_power;
 981         uint16_t                        average_soc_power;
 982         uint16_t                        average_gfx_power;
 983         uint16_t                        average_core_power[8]; // CPU core power on APUs
 984
 985         /* Average clocks */
 986         uint16_t                        average_gfxclk_frequency;
 987         uint16_t                        average_socclk_frequency;
 988         uint16_t                        average_uclk_frequency;
 989         uint16_t                        average_fclk_frequency;
 990         uint16_t                        average_vclk_frequency;
 991         uint16_t                        average_dclk_frequency;
 992
 993         /* Current clocks */
 994         uint16_t                        current_gfxclk;
 995         uint16_t                        current_socclk;
 996         uint16_t                        current_uclk;
 997         uint16_t                        current_fclk;
 998         uint16_t                        current_vclk;
 999         uint16_t                        current_dclk;
1000         uint16_t                        current_coreclk[8]; // CPU core clocks
1001         uint16_t                        current_l3clk[2];
1002
1003         /* Throttle status (ASIC dependent) */
1004         uint32_t                        throttle_status;
1005
1006         /* Fans */
1007         uint16_t                        fan_pwm;
1008
1009         uint16_t                        padding[3];
1010
1011         /* Throttle status (ASIC independent) */
1012         uint64_t                        indep_throttle_status;
1013 };
1014
1015 struct gpu_metrics_v2_3 {
1016         struct metrics_table_header     common_header;
1017
1018         /* Temperature */
1019         uint16_t                        temperature_gfx; // gfx temperature on APUs
1020         uint16_t                        temperature_soc; // soc temperature on APUs
1021         uint16_t                        temperature_core[8]; // CPU core temperature on APUs
1022         uint16_t                        temperature_l3[2];
1023
1024         /* Utilization */
1025         uint16_t                        average_gfx_activity;
1026         uint16_t                        average_mm_activity; // UVD or VCN
1027
1028         /* Driver attached timestamp (in ns) */
1029         uint64_t                        system_clock_counter;
1030
1031         /* Power/Energy */
1032         uint16_t                        average_socket_power; // dGPU + APU power on A + A platform
1033         uint16_t                        average_cpu_power;
1034         uint16_t                        average_soc_power;
1035         uint16_t                        average_gfx_power;
1036         uint16_t                        average_core_power[8]; // CPU core power on APUs
1037
1038         /* Average clocks */
1039         uint16_t                        average_gfxclk_frequency;
1040         uint16_t                        average_socclk_frequency;
1041         uint16_t                        average_uclk_frequency;
1042         uint16_t                        average_fclk_frequency;
1043         uint16_t                        average_vclk_frequency;
1044         uint16_t                        average_dclk_frequency;
1045
1046         /* Current clocks */
1047         uint16_t                        current_gfxclk;
1048         uint16_t                        current_socclk;
1049         uint16_t                        current_uclk;
1050         uint16_t                        current_fclk;
1051         uint16_t                        current_vclk;
1052         uint16_t                        current_dclk;
1053         uint16_t                        current_coreclk[8]; // CPU core clocks
1054         uint16_t                        current_l3clk[2];
1055
1056         /* Throttle status (ASIC dependent) */
1057         uint32_t                        throttle_status;
1058
1059         /* Fans */
1060         uint16_t                        fan_pwm;
1061
1062         uint16_t                        padding[3];
1063
1064         /* Throttle status (ASIC independent) */
1065         uint64_t                        indep_throttle_status;
1066
1067         /* Average Temperature */
1068         uint16_t                        average_temperature_gfx; // average gfx temperature on APUs
1069         uint16_t                        average_temperature_soc; // average soc temperature on APUs
1070         uint16_t                        average_temperature_core[8]; // average CPU core temperature on APUs
1071         uint16_t                        average_temperature_l3[2];
1072 };
1073
1074 struct gpu_metrics_v2_4 {
1075         struct metrics_table_header     common_header;
1076
1077         /* Temperature (unit: centi-Celsius) */
1078         uint16_t                        temperature_gfx;
1079         uint16_t                        temperature_soc;
1080         uint16_t                        temperature_core[8];
1081         uint16_t                        temperature_l3[2];
1082
1083         /* Utilization (unit: centi) */
1084         uint16_t                        average_gfx_activity;
1085         uint16_t                        average_mm_activity;
1086
1087         /* Driver attached timestamp (in ns) */
1088         uint64_t                        system_clock_counter;
1089
1090         /* Power/Energy (unit: mW) */
1091         uint16_t                        average_socket_power;
1092         uint16_t                        average_cpu_power;
1093         uint16_t                        average_soc_power;
1094         uint16_t                        average_gfx_power;
1095         uint16_t                        average_core_power[8];
1096
1097         /* Average clocks (unit: MHz) */
1098         uint16_t                        average_gfxclk_frequency;
1099         uint16_t                        average_socclk_frequency;
1100         uint16_t                        average_uclk_frequency;
1101         uint16_t                        average_fclk_frequency;
1102         uint16_t                        average_vclk_frequency;
1103         uint16_t                        average_dclk_frequency;
1104
1105         /* Current clocks (unit: MHz) */
1106         uint16_t                        current_gfxclk;
1107         uint16_t                        current_socclk;
1108         uint16_t                        current_uclk;
1109         uint16_t                        current_fclk;
1110         uint16_t                        current_vclk;
1111         uint16_t                        current_dclk;
1112         uint16_t                        current_coreclk[8];
1113         uint16_t                        current_l3clk[2];
1114
1115         /* Throttle status (ASIC dependent) */
1116         uint32_t                        throttle_status;
1117
1118         /* Fans */
1119         uint16_t                        fan_pwm;
1120
1121         uint16_t                        padding[3];
1122
1123         /* Throttle status (ASIC independent) */
1124         uint64_t                        indep_throttle_status;
1125
1126         /* Average Temperature (unit: centi-Celsius) */
1127         uint16_t                        average_temperature_gfx;
1128         uint16_t                        average_temperature_soc;
1129         uint16_t                        average_temperature_core[8];
1130         uint16_t                        average_temperature_l3[2];
1131
1132         /* Power/Voltage (unit: mV) */
1133         uint16_t                        average_cpu_voltage;
1134         uint16_t                        average_soc_voltage;
1135         uint16_t                        average_gfx_voltage;
1136
1137         /* Power/Current (unit: mA) */
1138         uint16_t                        average_cpu_current;
1139         uint16_t                        average_soc_current;
1140         uint16_t                        average_gfx_current;
1141 };
1142
1143 struct gpu_metrics_v3_0 {
1144         struct metrics_table_header     common_header;
1145
1146         /* Temperature */
1147         /* gfx temperature on APUs */
1148         uint16_t                        temperature_gfx;
1149         /* soc temperature on APUs */
1150         uint16_t                        temperature_soc;
1151         /* CPU core temperature on APUs */
1152         uint16_t                        temperature_core[16];
1153         /* skin temperature on APUs */
1154         uint16_t                        temperature_skin;
1155
1156         /* Utilization */
1157         /* time filtered GFX busy % [0-100] */
1158         uint16_t                        average_gfx_activity;
1159         /* time filtered VCN busy % [0-100] */
1160         uint16_t                        average_vcn_activity;
1161         /* time filtered IPU per-column busy % [0-100] */
1162         uint16_t                        average_ipu_activity[8];
1163         /* time filtered per-core C0 residency % [0-100]*/
1164         uint16_t                        average_core_c0_activity[16];
1165         /* time filtered DRAM read bandwidth [MB/sec] */
1166         uint16_t                        average_dram_reads;
1167         /* time filtered DRAM write bandwidth [MB/sec] */
1168         uint16_t                        average_dram_writes;
1169         /* time filtered IPU read bandwidth [MB/sec] */
1170         uint16_t                        average_ipu_reads;
1171         /* time filtered IPU write bandwidth [MB/sec] */
1172         uint16_t                        average_ipu_writes;
1173
1174         /* Driver attached timestamp (in ns) */
1175         uint64_t                        system_clock_counter;
1176
1177         /* Power/Energy */
1178         /* time filtered power used for PPT/STAPM [APU+dGPU] [mW] */
1179         uint32_t                        average_socket_power;
1180         /* time filtered IPU power [mW] */
1181         uint16_t                        average_ipu_power;
1182         /* time filtered APU power [mW] */
1183         uint32_t                        average_apu_power;
1184         /* time filtered GFX power [mW] */
1185         uint32_t                        average_gfx_power;
1186         /* time filtered dGPU power [mW] */
1187         uint32_t                        average_dgpu_power;
1188         /* time filtered sum of core power across all cores in the socket [mW] */
1189         uint32_t                        average_all_core_power;
1190         /* calculated core power [mW] */
1191         uint16_t                        average_core_power[16];
1192         /* time filtered total system power [mW] */
1193         uint16_t                        average_sys_power;
1194         /* maximum IRM defined STAPM power limit [mW] */
1195         uint16_t                        stapm_power_limit;
1196         /* time filtered STAPM power limit [mW] */
1197         uint16_t                        current_stapm_power_limit;
1198
1199         /* time filtered clocks [MHz] */
1200         uint16_t                        average_gfxclk_frequency;
1201         uint16_t                        average_socclk_frequency;
1202         uint16_t                        average_vpeclk_frequency;
1203         uint16_t                        average_ipuclk_frequency;
1204         uint16_t                        average_fclk_frequency;
1205         uint16_t                        average_vclk_frequency;
1206         uint16_t                        average_uclk_frequency;
1207         uint16_t                        average_mpipu_frequency;
1208
1209         /* Current clocks */
1210         /* target core frequency [MHz] */
1211         uint16_t                        current_coreclk[16];
1212         /* CCLK frequency limit enforced on classic cores [MHz] */
1213         uint16_t                        current_core_maxfreq;
1214         /* GFXCLK frequency limit enforced on GFX [MHz] */
1215         uint16_t                        current_gfx_maxfreq;
1216
1217         /* Throttle Residency (ASIC dependent) */
1218         uint32_t                        throttle_residency_prochot;
1219         uint32_t                        throttle_residency_spl;
1220         uint32_t                        throttle_residency_fppt;
1221         uint32_t                        throttle_residency_sppt;
1222         uint32_t                        throttle_residency_thm_core;
1223         uint32_t                        throttle_residency_thm_gfx;
1224         uint32_t                        throttle_residency_thm_soc;
1225
1226         /* Metrics table alpha filter time constant [us] */
1227         uint32_t                        time_filter_alphavalue;
1228 };
1229
1230 struct amdgpu_pmmetrics_header {
1231         uint16_t structure_size;
1232         uint16_t pad;
1233         uint32_t mp1_ip_discovery_version;
1234         uint32_t pmfw_version;
1235         uint32_t pmmetrics_version;
1236 };
1237
1238 struct amdgpu_pm_metrics {
1239         struct amdgpu_pmmetrics_header common_header;
1240
1241         uint8_t data[];
1242 };
1243
1244 #endif