drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  * Authors: Christian König <[email protected]>
  26  */
  27
  28 #include <linux/firmware.h>
  29 #include <linux/module.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm.h>
  32
  33 #include "amdgpu.h"
  34 #include "amdgpu_pm.h"
  35 #include "amdgpu_vce.h"
  36 #include "cikd.h"
  37
  38 /* 1 second timeout */
  39 #define VCE_IDLE_TIMEOUT        msecs_to_jiffies(1000)
  40
  41 /* Firmware Names */
  42 #ifdef CONFIG_DRM_AMDGPU_CIK
  43 #define FIRMWARE_BONAIRE        "radeon/bonaire_vce.bin"
  44 #define FIRMWARE_KABINI "radeon/kabini_vce.bin"
  45 #define FIRMWARE_KAVERI "radeon/kaveri_vce.bin"
  46 #define FIRMWARE_HAWAII "radeon/hawaii_vce.bin"
  47 #define FIRMWARE_MULLINS        "radeon/mullins_vce.bin"
  48 #endif
  49 #define FIRMWARE_TONGA          "amdgpu/tonga_vce.bin"
  50 #define FIRMWARE_CARRIZO        "amdgpu/carrizo_vce.bin"
  51 #define FIRMWARE_FIJI           "amdgpu/fiji_vce.bin"
  52 #define FIRMWARE_STONEY         "amdgpu/stoney_vce.bin"
  53 #define FIRMWARE_POLARIS10      "amdgpu/polaris10_vce.bin"
  54 #define FIRMWARE_POLARIS11         "amdgpu/polaris11_vce.bin"
  55 #define FIRMWARE_POLARIS12         "amdgpu/polaris12_vce.bin"
  56
  57 #define FIRMWARE_VEGA10         "amdgpu/vega10_vce.bin"
  58
  59 #ifdef CONFIG_DRM_AMDGPU_CIK
  60 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
  61 MODULE_FIRMWARE(FIRMWARE_KABINI);
  62 MODULE_FIRMWARE(FIRMWARE_KAVERI);
  63 MODULE_FIRMWARE(FIRMWARE_HAWAII);
  64 MODULE_FIRMWARE(FIRMWARE_MULLINS);
  65 #endif
  66 MODULE_FIRMWARE(FIRMWARE_TONGA);
  67 MODULE_FIRMWARE(FIRMWARE_CARRIZO);
  68 MODULE_FIRMWARE(FIRMWARE_FIJI);
  69 MODULE_FIRMWARE(FIRMWARE_STONEY);
  70 MODULE_FIRMWARE(FIRMWARE_POLARIS10);
  71 MODULE_FIRMWARE(FIRMWARE_POLARIS11);
  72 MODULE_FIRMWARE(FIRMWARE_POLARIS12);
  73
  74 MODULE_FIRMWARE(FIRMWARE_VEGA10);
  75
  76 static void amdgpu_vce_idle_work_handler(struct work_struct *work);
  77
  78 /**
  79  * amdgpu_vce_init - allocate memory, load vce firmware
  80  *
  81  * @adev: amdgpu_device pointer
  82  *
  83  * First step to get VCE online, allocate memory and load the firmware
  84  */
  85 int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)
  86 {
  87         struct amdgpu_ring *ring;
  88         struct drm_sched_rq *rq;
  89         const char *fw_name;
  90         const struct common_firmware_header *hdr;
  91         unsigned ucode_version, version_major, version_minor, binary_id;
  92         int i, r;
  93
  94         switch (adev->asic_type) {
  95 #ifdef CONFIG_DRM_AMDGPU_CIK
  96         case CHIP_BONAIRE:
  97                 fw_name = FIRMWARE_BONAIRE;
  98                 break;
  99         case CHIP_KAVERI:
 100                 fw_name = FIRMWARE_KAVERI;
 101                 break;
 102         case CHIP_KABINI:
 103                 fw_name = FIRMWARE_KABINI;
 104                 break;
 105         case CHIP_HAWAII:
 106                 fw_name = FIRMWARE_HAWAII;
 107                 break;
 108         case CHIP_MULLINS:
 109                 fw_name = FIRMWARE_MULLINS;
 110                 break;
 111 #endif
 112         case CHIP_TONGA:
 113                 fw_name = FIRMWARE_TONGA;
 114                 break;
 115         case CHIP_CARRIZO:
 116                 fw_name = FIRMWARE_CARRIZO;
 117                 break;
 118         case CHIP_FIJI:
 119                 fw_name = FIRMWARE_FIJI;
 120                 break;
 121         case CHIP_STONEY:
 122                 fw_name = FIRMWARE_STONEY;
 123                 break;
 124         case CHIP_POLARIS10:
 125                 fw_name = FIRMWARE_POLARIS10;
 126                 break;
 127         case CHIP_POLARIS11:
 128                 fw_name = FIRMWARE_POLARIS11;
 129                 break;
 130         case CHIP_VEGA10:
 131                 fw_name = FIRMWARE_VEGA10;
 132                 break;
 133         case CHIP_POLARIS12:
 134                 fw_name = FIRMWARE_POLARIS12;
 135                 break;
 136
 137         default:
 138                 return -EINVAL;
 139         }
 140
 141         r = request_firmware(&adev->vce.fw, fw_name, adev->dev);
 142         if (r) {
 143                 dev_err(adev->dev, "amdgpu_vce: Can't load firmware \"%s\"\n",
 144                         fw_name);
 145                 return r;
 146         }
 147
 148         r = amdgpu_ucode_validate(adev->vce.fw);
 149         if (r) {
 150                 dev_err(adev->dev, "amdgpu_vce: Can't validate firmware \"%s\"\n",
 151                         fw_name);
 152                 release_firmware(adev->vce.fw);
 153                 adev->vce.fw = NULL;
 154                 return r;
 155         }
 156
 157         hdr = (const struct common_firmware_header *)adev->vce.fw->data;
 158
 159         ucode_version = le32_to_cpu(hdr->ucode_version);
 160         version_major = (ucode_version >> 20) & 0xfff;
 161         version_minor = (ucode_version >> 8) & 0xfff;
 162         binary_id = ucode_version & 0xff;
 163         DRM_INFO("Found VCE firmware Version: %hhd.%hhd Binary ID: %hhd\n",
 164                 version_major, version_minor, binary_id);
 165         adev->vce.fw_version = ((version_major << 24) | (version_minor << 16) |
 166                                 (binary_id << 8));
 167
 168         r = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
 169                                     AMDGPU_GEM_DOMAIN_VRAM, &adev->vce.vcpu_bo,
 170                                     &adev->vce.gpu_addr, &adev->vce.cpu_addr);
 171         if (r) {
 172                 dev_err(adev->dev, "(%d) failed to allocate VCE bo\n", r);
 173                 return r;
 174         }
 175
 176         ring = &adev->vce.ring[0];
 177         rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
 178         r = drm_sched_entity_init(&ring->sched, &adev->vce.entity,
 179                                   rq, amdgpu_sched_jobs, NULL);
 180         if (r != 0) {
 181                 DRM_ERROR("Failed setting up VCE run queue.\n");
 182                 return r;
 183         }
 184
 185         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 186                 atomic_set(&adev->vce.handles[i], 0);
 187                 adev->vce.filp[i] = NULL;
 188         }
 189
 190         INIT_DELAYED_WORK(&adev->vce.idle_work, amdgpu_vce_idle_work_handler);
 191         mutex_init(&adev->vce.idle_mutex);
 192
 193         return 0;
 194 }
 195
 196 /**
 197  * amdgpu_vce_fini - free memory
 198  *
 199  * @adev: amdgpu_device pointer
 200  *
 201  * Last step on VCE teardown, free firmware memory
 202  */
 203 int amdgpu_vce_sw_fini(struct amdgpu_device *adev)
 204 {
 205         unsigned i;
 206
 207         if (adev->vce.vcpu_bo == NULL)
 208                 return 0;
 209
 210         drm_sched_entity_fini(&adev->vce.ring[0].sched, &adev->vce.entity);
 211
 212         amdgpu_bo_free_kernel(&adev->vce.vcpu_bo, &adev->vce.gpu_addr,
 213                 (void **)&adev->vce.cpu_addr);
 214
 215         for (i = 0; i < adev->vce.num_rings; i++)
 216                 amdgpu_ring_fini(&adev->vce.ring[i]);
 217
 218         release_firmware(adev->vce.fw);
 219         mutex_destroy(&adev->vce.idle_mutex);
 220
 221         return 0;
 222 }
 223
 224 /**
 225  * amdgpu_vce_suspend - unpin VCE fw memory
 226  *
 227  * @adev: amdgpu_device pointer
 228  *
 229  */
 230 int amdgpu_vce_suspend(struct amdgpu_device *adev)
 231 {
 232         int i;
 233
 234         if (adev->vce.vcpu_bo == NULL)
 235                 return 0;
 236
 237         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
 238                 if (atomic_read(&adev->vce.handles[i]))
 239                         break;
 240
 241         if (i == AMDGPU_MAX_VCE_HANDLES)
 242                 return 0;
 243
 244         cancel_delayed_work_sync(&adev->vce.idle_work);
 245         /* TODO: suspending running encoding sessions isn't supported */
 246         return -EINVAL;
 247 }
 248
 249 /**
 250  * amdgpu_vce_resume - pin VCE fw memory
 251  *
 252  * @adev: amdgpu_device pointer
 253  *
 254  */
 255 int amdgpu_vce_resume(struct amdgpu_device *adev)
 256 {
 257         void *cpu_addr;
 258         const struct common_firmware_header *hdr;
 259         unsigned offset;
 260         int r;
 261
 262         if (adev->vce.vcpu_bo == NULL)
 263                 return -EINVAL;
 264
 265         r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false);
 266         if (r) {
 267                 dev_err(adev->dev, "(%d) failed to reserve VCE bo\n", r);
 268                 return r;
 269         }
 270
 271         r = amdgpu_bo_kmap(adev->vce.vcpu_bo, &cpu_addr);
 272         if (r) {
 273                 amdgpu_bo_unreserve(adev->vce.vcpu_bo);
 274                 dev_err(adev->dev, "(%d) VCE map failed\n", r);
 275                 return r;
 276         }
 277
 278         hdr = (const struct common_firmware_header *)adev->vce.fw->data;
 279         offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
 280         memcpy_toio(cpu_addr, adev->vce.fw->data + offset,
 281                     adev->vce.fw->size - offset);
 282
 283         amdgpu_bo_kunmap(adev->vce.vcpu_bo);
 284
 285         amdgpu_bo_unreserve(adev->vce.vcpu_bo);
 286
 287         return 0;
 288 }
 289
 290 /**
 291  * amdgpu_vce_idle_work_handler - power off VCE
 292  *
 293  * @work: pointer to work structure
 294  *
 295  * power of VCE when it's not used any more
 296  */
 297 static void amdgpu_vce_idle_work_handler(struct work_struct *work)
 298 {
 299         struct amdgpu_device *adev =
 300                 container_of(work, struct amdgpu_device, vce.idle_work.work);
 301         unsigned i, count = 0;
 302
 303         for (i = 0; i < adev->vce.num_rings; i++)
 304                 count += amdgpu_fence_count_emitted(&adev->vce.ring[i]);
 305
 306         if (count == 0) {
 307                 if (adev->pm.dpm_enabled) {
 308                         amdgpu_dpm_enable_vce(adev, false);
 309                 } else {
 310                         amdgpu_asic_set_vce_clocks(adev, 0, 0);
 311                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
 312                                                                AMD_PG_STATE_GATE);
 313                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
 314                                                                AMD_CG_STATE_GATE);
 315                 }
 316         } else {
 317                 schedule_delayed_work(&adev->vce.idle_work, VCE_IDLE_TIMEOUT);
 318         }
 319 }
 320
 321 /**
 322  * amdgpu_vce_ring_begin_use - power up VCE
 323  *
 324  * @ring: amdgpu ring
 325  *
 326  * Make sure VCE is powerd up when we want to use it
 327  */
 328 void amdgpu_vce_ring_begin_use(struct amdgpu_ring *ring)
 329 {
 330         struct amdgpu_device *adev = ring->adev;
 331         bool set_clocks;
 332
 333         if (amdgpu_sriov_vf(adev))
 334                 return;
 335
 336         mutex_lock(&adev->vce.idle_mutex);
 337         set_clocks = !cancel_delayed_work_sync(&adev->vce.idle_work);
 338         if (set_clocks) {
 339                 if (adev->pm.dpm_enabled) {
 340                         amdgpu_dpm_enable_vce(adev, true);
 341                 } else {
 342                         amdgpu_asic_set_vce_clocks(adev, 53300, 40000);
 343                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
 344                                                                AMD_CG_STATE_UNGATE);
 345                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
 346                                                                AMD_PG_STATE_UNGATE);
 347
 348                 }
 349         }
 350         mutex_unlock(&adev->vce.idle_mutex);
 351 }
 352
 353 /**
 354  * amdgpu_vce_ring_end_use - power VCE down
 355  *
 356  * @ring: amdgpu ring
 357  *
 358  * Schedule work to power VCE down again
 359  */
 360 void amdgpu_vce_ring_end_use(struct amdgpu_ring *ring)
 361 {
 362         if (!amdgpu_sriov_vf(ring->adev))
 363                 schedule_delayed_work(&ring->adev->vce.idle_work, VCE_IDLE_TIMEOUT);
 364 }
 365
 366 /**
 367  * amdgpu_vce_free_handles - free still open VCE handles
 368  *
 369  * @adev: amdgpu_device pointer
 370  * @filp: drm file pointer
 371  *
 372  * Close all VCE handles still open by this file pointer
 373  */
 374 void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
 375 {
 376         struct amdgpu_ring *ring = &adev->vce.ring[0];
 377         int i, r;
 378         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 379                 uint32_t handle = atomic_read(&adev->vce.handles[i]);
 380
 381                 if (!handle || adev->vce.filp[i] != filp)
 382                         continue;
 383
 384                 r = amdgpu_vce_get_destroy_msg(ring, handle, false, NULL);
 385                 if (r)
 386                         DRM_ERROR("Error destroying VCE handle (%d)!\n", r);
 387
 388                 adev->vce.filp[i] = NULL;
 389                 atomic_set(&adev->vce.handles[i], 0);
 390         }
 391 }
 392
 393 /**
 394  * amdgpu_vce_get_create_msg - generate a VCE create msg
 395  *
 396  * @adev: amdgpu_device pointer
 397  * @ring: ring we should submit the msg to
 398  * @handle: VCE session handle to use
 399  * @fence: optional fence to return
 400  *
 401  * Open up a stream for HW test
 402  */
 403 int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 404                               struct dma_fence **fence)
 405 {
 406         const unsigned ib_size_dw = 1024;
 407         struct amdgpu_job *job;
 408         struct amdgpu_ib *ib;
 409         struct dma_fence *f = NULL;
 410         uint64_t dummy;
 411         int i, r;
 412
 413         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 414         if (r)
 415                 return r;
 416
 417         ib = &job->ibs[0];
 418
 419         dummy = ib->gpu_addr + 1024;
 420
 421         /* stitch together an VCE create msg */
 422         ib->length_dw = 0;
 423         ib->ptr[ib->length_dw++] = 0x0000000c; /* len */
 424         ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
 425         ib->ptr[ib->length_dw++] = handle;
 426
 427         if ((ring->adev->vce.fw_version >> 24) >= 52)
 428                 ib->ptr[ib->length_dw++] = 0x00000040; /* len */
 429         else
 430                 ib->ptr[ib->length_dw++] = 0x00000030; /* len */
 431         ib->ptr[ib->length_dw++] = 0x01000001; /* create cmd */
 432         ib->ptr[ib->length_dw++] = 0x00000000;
 433         ib->ptr[ib->length_dw++] = 0x00000042;
 434         ib->ptr[ib->length_dw++] = 0x0000000a;
 435         ib->ptr[ib->length_dw++] = 0x00000001;
 436         ib->ptr[ib->length_dw++] = 0x00000080;
 437         ib->ptr[ib->length_dw++] = 0x00000060;
 438         ib->ptr[ib->length_dw++] = 0x00000100;
 439         ib->ptr[ib->length_dw++] = 0x00000100;
 440         ib->ptr[ib->length_dw++] = 0x0000000c;
 441         ib->ptr[ib->length_dw++] = 0x00000000;
 442         if ((ring->adev->vce.fw_version >> 24) >= 52) {
 443                 ib->ptr[ib->length_dw++] = 0x00000000;
 444                 ib->ptr[ib->length_dw++] = 0x00000000;
 445                 ib->ptr[ib->length_dw++] = 0x00000000;
 446                 ib->ptr[ib->length_dw++] = 0x00000000;
 447         }
 448
 449         ib->ptr[ib->length_dw++] = 0x00000014; /* len */
 450         ib->ptr[ib->length_dw++] = 0x05000005; /* feedback buffer */
 451         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 452         ib->ptr[ib->length_dw++] = dummy;
 453         ib->ptr[ib->length_dw++] = 0x00000001;
 454
 455         for (i = ib->length_dw; i < ib_size_dw; ++i)
 456                 ib->ptr[i] = 0x0;
 457
 458         r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
 459         job->fence = dma_fence_get(f);
 460         if (r)
 461                 goto err;
 462
 463         amdgpu_job_free(job);
 464         if (fence)
 465                 *fence = dma_fence_get(f);
 466         dma_fence_put(f);
 467         return 0;
 468
 469 err:
 470         amdgpu_job_free(job);
 471         return r;
 472 }
 473
 474 /**
 475  * amdgpu_vce_get_destroy_msg - generate a VCE destroy msg
 476  *
 477  * @adev: amdgpu_device pointer
 478  * @ring: ring we should submit the msg to
 479  * @handle: VCE session handle to use
 480  * @fence: optional fence to return
 481  *
 482  * Close up a stream for HW test or if userspace failed to do so
 483  */
 484 int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 485                                bool direct, struct dma_fence **fence)
 486 {
 487         const unsigned ib_size_dw = 1024;
 488         struct amdgpu_job *job;
 489         struct amdgpu_ib *ib;
 490         struct dma_fence *f = NULL;
 491         int i, r;
 492
 493         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 494         if (r)
 495                 return r;
 496
 497         ib = &job->ibs[0];
 498
 499         /* stitch together an VCE destroy msg */
 500         ib->length_dw = 0;
 501         ib->ptr[ib->length_dw++] = 0x0000000c; /* len */
 502         ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
 503         ib->ptr[ib->length_dw++] = handle;
 504
 505         ib->ptr[ib->length_dw++] = 0x00000020; /* len */
 506         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 507         ib->ptr[ib->length_dw++] = 0xffffffff; /* next task info, set to 0xffffffff if no */
 508         ib->ptr[ib->length_dw++] = 0x00000001; /* destroy session */
 509         ib->ptr[ib->length_dw++] = 0x00000000;
 510         ib->ptr[ib->length_dw++] = 0x00000000;
 511         ib->ptr[ib->length_dw++] = 0xffffffff; /* feedback is not needed, set to 0xffffffff and firmware will not output feedback */
 512         ib->ptr[ib->length_dw++] = 0x00000000;
 513
 514         ib->ptr[ib->length_dw++] = 0x00000008; /* len */
 515         ib->ptr[ib->length_dw++] = 0x02000001; /* destroy cmd */
 516
 517         for (i = ib->length_dw; i < ib_size_dw; ++i)
 518                 ib->ptr[i] = 0x0;
 519
 520         if (direct) {
 521                 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
 522                 job->fence = dma_fence_get(f);
 523                 if (r)
 524                         goto err;
 525
 526                 amdgpu_job_free(job);
 527         } else {
 528                 r = amdgpu_job_submit(job, ring, &ring->adev->vce.entity,
 529                                       AMDGPU_FENCE_OWNER_UNDEFINED, &f);
 530                 if (r)
 531                         goto err;
 532         }
 533
 534         if (fence)
 535                 *fence = dma_fence_get(f);
 536         dma_fence_put(f);
 537         return 0;
 538
 539 err:
 540         amdgpu_job_free(job);
 541         return r;
 542 }
 543
 544 /**
 545  * amdgpu_vce_cs_validate_bo - make sure not to cross 4GB boundary
 546  *
 547  * @p: parser context
 548  * @lo: address of lower dword
 549  * @hi: address of higher dword
 550  * @size: minimum size
 551  * @index: bs/fb index
 552  *
 553  * Make sure that no BO cross a 4GB boundary.
 554  */
 555 static int amdgpu_vce_validate_bo(struct amdgpu_cs_parser *p, uint32_t ib_idx,
 556                                   int lo, int hi, unsigned size, int32_t index)
 557 {
 558         int64_t offset = ((uint64_t)size) * ((int64_t)index);
 559         struct ttm_operation_ctx ctx = { false, false };
 560         struct amdgpu_bo_va_mapping *mapping;
 561         unsigned i, fpfn, lpfn;
 562         struct amdgpu_bo *bo;
 563         uint64_t addr;
 564         int r;
 565
 566         addr = ((uint64_t)amdgpu_get_ib_value(p, ib_idx, lo)) |
 567                ((uint64_t)amdgpu_get_ib_value(p, ib_idx, hi)) << 32;
 568         if (index >= 0) {
 569                 addr += offset;
 570                 fpfn = PAGE_ALIGN(offset) >> PAGE_SHIFT;
 571                 lpfn = 0x100000000ULL >> PAGE_SHIFT;
 572         } else {
 573                 fpfn = 0;
 574                 lpfn = (0x100000000ULL - PAGE_ALIGN(offset)) >> PAGE_SHIFT;
 575         }
 576
 577         r = amdgpu_cs_find_mapping(p, addr, &bo, &mapping);
 578         if (r) {
 579                 DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d %d %d\n",
 580                           addr, lo, hi, size, index);
 581                 return r;
 582         }
 583
 584         for (i = 0; i < bo->placement.num_placement; ++i) {
 585                 bo->placements[i].fpfn = max(bo->placements[i].fpfn, fpfn);
 586                 bo->placements[i].lpfn = bo->placements[i].lpfn ?
 587                         min(bo->placements[i].lpfn, lpfn) : lpfn;
 588         }
 589         return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 590 }
 591
 592
 593 /**
 594  * amdgpu_vce_cs_reloc - command submission relocation
 595  *
 596  * @p: parser context
 597  * @lo: address of lower dword
 598  * @hi: address of higher dword
 599  * @size: minimum size
 600  *
 601  * Patch relocation inside command stream with real buffer address
 602  */
 603 static int amdgpu_vce_cs_reloc(struct amdgpu_cs_parser *p, uint32_t ib_idx,
 604                                int lo, int hi, unsigned size, uint32_t index)
 605 {
 606         struct amdgpu_bo_va_mapping *mapping;
 607         struct amdgpu_bo *bo;
 608         uint64_t addr;
 609         int r;
 610
 611         if (index == 0xffffffff)
 612                 index = 0;
 613
 614         addr = ((uint64_t)amdgpu_get_ib_value(p, ib_idx, lo)) |
 615                ((uint64_t)amdgpu_get_ib_value(p, ib_idx, hi)) << 32;
 616         addr += ((uint64_t)size) * ((uint64_t)index);
 617
 618         r = amdgpu_cs_find_mapping(p, addr, &bo, &mapping);
 619         if (r) {
 620                 DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d %d %d\n",
 621                           addr, lo, hi, size, index);
 622                 return r;
 623         }
 624
 625         if ((addr + (uint64_t)size) >
 626             (mapping->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 627                 DRM_ERROR("BO to small for addr 0x%010Lx %d %d\n",
 628                           addr, lo, hi);
 629                 return -EINVAL;
 630         }
 631
 632         addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE;
 633         addr += amdgpu_bo_gpu_offset(bo);
 634         addr -= ((uint64_t)size) * ((uint64_t)index);
 635
 636         amdgpu_set_ib_value(p, ib_idx, lo, lower_32_bits(addr));
 637         amdgpu_set_ib_value(p, ib_idx, hi, upper_32_bits(addr));
 638
 639         return 0;
 640 }
 641
 642 /**
 643  * amdgpu_vce_validate_handle - validate stream handle
 644  *
 645  * @p: parser context
 646  * @handle: handle to validate
 647  * @allocated: allocated a new handle?
 648  *
 649  * Validates the handle and return the found session index or -EINVAL
 650  * we we don't have another free session index.
 651  */
 652 static int amdgpu_vce_validate_handle(struct amdgpu_cs_parser *p,
 653                                       uint32_t handle, uint32_t *allocated)
 654 {
 655         unsigned i;
 656
 657         /* validate the handle */
 658         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 659                 if (atomic_read(&p->adev->vce.handles[i]) == handle) {
 660                         if (p->adev->vce.filp[i] != p->filp) {
 661                                 DRM_ERROR("VCE handle collision detected!\n");
 662                                 return -EINVAL;
 663                         }
 664                         return i;
 665                 }
 666         }
 667
 668         /* handle not found try to alloc a new one */
 669         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 670                 if (!atomic_cmpxchg(&p->adev->vce.handles[i], 0, handle)) {
 671                         p->adev->vce.filp[i] = p->filp;
 672                         p->adev->vce.img_size[i] = 0;
 673                         *allocated |= 1 << i;
 674                         return i;
 675                 }
 676         }
 677
 678         DRM_ERROR("No more free VCE handles!\n");
 679         return -EINVAL;
 680 }
 681
 682 /**
 683  * amdgpu_vce_cs_parse - parse and validate the command stream
 684  *
 685  * @p: parser context
 686  *
 687  */
 688 int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
 689 {
 690         struct amdgpu_ib *ib = &p->job->ibs[ib_idx];
 691         unsigned fb_idx = 0, bs_idx = 0;
 692         int session_idx = -1;
 693         uint32_t destroyed = 0;
 694         uint32_t created = 0;
 695         uint32_t allocated = 0;
 696         uint32_t tmp, handle = 0;
 697         uint32_t *size = &tmp;
 698         unsigned idx;
 699         int i, r = 0;
 700
 701         p->job->vm = NULL;
 702         ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
 703
 704         for (idx = 0; idx < ib->length_dw;) {
 705                 uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
 706                 uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
 707
 708                 if ((len < 8) || (len & 3)) {
 709                         DRM_ERROR("invalid VCE command length (%d)!\n", len);
 710                         r = -EINVAL;
 711                         goto out;
 712                 }
 713
 714                 switch (cmd) {
 715                 case 0x00000002: /* task info */
 716                         fb_idx = amdgpu_get_ib_value(p, ib_idx, idx + 6);
 717                         bs_idx = amdgpu_get_ib_value(p, ib_idx, idx + 7);
 718                         break;
 719
 720                 case 0x03000001: /* encode */
 721                         r = amdgpu_vce_validate_bo(p, ib_idx, idx + 10,
 722                                                    idx + 9, 0, 0);
 723                         if (r)
 724                                 goto out;
 725
 726                         r = amdgpu_vce_validate_bo(p, ib_idx, idx + 12,
 727                                                    idx + 11, 0, 0);
 728                         if (r)
 729                                 goto out;
 730                         break;
 731
 732                 case 0x05000001: /* context buffer */
 733                         r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3,
 734                                                    idx + 2, 0, 0);
 735                         if (r)
 736                                 goto out;
 737                         break;
 738
 739                 case 0x05000004: /* video bitstream buffer */
 740                         tmp = amdgpu_get_ib_value(p, ib_idx, idx + 4);
 741                         r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3, idx + 2,
 742                                                    tmp, bs_idx);
 743                         if (r)
 744                                 goto out;
 745                         break;
 746
 747                 case 0x05000005: /* feedback buffer */
 748                         r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3, idx + 2,
 749                                                    4096, fb_idx);
 750                         if (r)
 751                                 goto out;
 752                         break;
 753                 }
 754
 755                 idx += len / 4;
 756         }
 757
 758         for (idx = 0; idx < ib->length_dw;) {
 759                 uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
 760                 uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
 761
 762                 switch (cmd) {
 763                 case 0x00000001: /* session */
 764                         handle = amdgpu_get_ib_value(p, ib_idx, idx + 2);
 765                         session_idx = amdgpu_vce_validate_handle(p, handle,
 766                                                                  &allocated);
 767                         if (session_idx < 0) {
 768                                 r = session_idx;
 769                                 goto out;
 770                         }
 771                         size = &p->adev->vce.img_size[session_idx];
 772                         break;
 773
 774                 case 0x00000002: /* task info */
 775                         fb_idx = amdgpu_get_ib_value(p, ib_idx, idx + 6);
 776                         bs_idx = amdgpu_get_ib_value(p, ib_idx, idx + 7);
 777                         break;
 778
 779                 case 0x01000001: /* create */
 780                         created |= 1 << session_idx;
 781                         if (destroyed & (1 << session_idx)) {
 782                                 destroyed &= ~(1 << session_idx);
 783                                 allocated |= 1 << session_idx;
 784
 785                         } else if (!(allocated & (1 << session_idx))) {
 786                                 DRM_ERROR("Handle already in use!\n");
 787                                 r = -EINVAL;
 788                                 goto out;
 789                         }
 790
 791                         *size = amdgpu_get_ib_value(p, ib_idx, idx + 8) *
 792                                 amdgpu_get_ib_value(p, ib_idx, idx + 10) *
 793                                 8 * 3 / 2;
 794                         break;
 795
 796                 case 0x04000001: /* config extension */
 797                 case 0x04000002: /* pic control */
 798                 case 0x04000005: /* rate control */
 799                 case 0x04000007: /* motion estimation */
 800                 case 0x04000008: /* rdo */
 801                 case 0x04000009: /* vui */
 802                 case 0x05000002: /* auxiliary buffer */
 803                 case 0x05000009: /* clock table */
 804                         break;
 805
 806                 case 0x0500000c: /* hw config */
 807                         switch (p->adev->asic_type) {
 808 #ifdef CONFIG_DRM_AMDGPU_CIK
 809                         case CHIP_KAVERI:
 810                         case CHIP_MULLINS:
 811 #endif
 812                         case CHIP_CARRIZO:
 813                                 break;
 814                         default:
 815                                 r = -EINVAL;
 816                                 goto out;
 817                         }
 818                         break;
 819
 820                 case 0x03000001: /* encode */
 821                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 10, idx + 9,
 822                                                 *size, 0);
 823                         if (r)
 824                                 goto out;
 825
 826                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 12, idx + 11,
 827                                                 *size / 3, 0);
 828                         if (r)
 829                                 goto out;
 830                         break;
 831
 832                 case 0x02000001: /* destroy */
 833                         destroyed |= 1 << session_idx;
 834                         break;
 835
 836                 case 0x05000001: /* context buffer */
 837                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
 838                                                 *size * 2, 0);
 839                         if (r)
 840                                 goto out;
 841                         break;
 842
 843                 case 0x05000004: /* video bitstream buffer */
 844                         tmp = amdgpu_get_ib_value(p, ib_idx, idx + 4);
 845                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
 846                                                 tmp, bs_idx);
 847                         if (r)
 848                                 goto out;
 849                         break;
 850
 851                 case 0x05000005: /* feedback buffer */
 852                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
 853                                                 4096, fb_idx);
 854                         if (r)
 855                                 goto out;
 856                         break;
 857
 858                 default:
 859                         DRM_ERROR("invalid VCE command (0x%x)!\n", cmd);
 860                         r = -EINVAL;
 861                         goto out;
 862                 }
 863
 864                 if (session_idx == -1) {
 865                         DRM_ERROR("no session command at start of IB\n");
 866                         r = -EINVAL;
 867                         goto out;
 868                 }
 869
 870                 idx += len / 4;
 871         }
 872
 873         if (allocated & ~created) {
 874                 DRM_ERROR("New session without create command!\n");
 875                 r = -ENOENT;
 876         }
 877
 878 out:
 879         if (!r) {
 880                 /* No error, free all destroyed handle slots */
 881                 tmp = destroyed;
 882         } else {
 883                 /* Error during parsing, free all allocated handle slots */
 884                 tmp = allocated;
 885         }
 886
 887         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
 888                 if (tmp & (1 << i))
 889                         atomic_set(&p->adev->vce.handles[i], 0);
 890
 891         return r;
 892 }
 893
 894 /**
 895  * amdgpu_vce_cs_parse_vm - parse the command stream in VM mode
 896  *
 897  * @p: parser context
 898  *
 899  */
 900 int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p, uint32_t ib_idx)
 901 {
 902         struct amdgpu_ib *ib = &p->job->ibs[ib_idx];
 903         int session_idx = -1;
 904         uint32_t destroyed = 0;
 905         uint32_t created = 0;
 906         uint32_t allocated = 0;
 907         uint32_t tmp, handle = 0;
 908         int i, r = 0, idx = 0;
 909
 910         while (idx < ib->length_dw) {
 911                 uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
 912                 uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
 913
 914                 if ((len < 8) || (len & 3)) {
 915                         DRM_ERROR("invalid VCE command length (%d)!\n", len);
 916                         r = -EINVAL;
 917                         goto out;
 918                 }
 919
 920                 switch (cmd) {
 921                 case 0x00000001: /* session */
 922                         handle = amdgpu_get_ib_value(p, ib_idx, idx + 2);
 923                         session_idx = amdgpu_vce_validate_handle(p, handle,
 924                                                                  &allocated);
 925                         if (session_idx < 0) {
 926                                 r = session_idx;
 927                                 goto out;
 928                         }
 929                         break;
 930
 931                 case 0x01000001: /* create */
 932                         created |= 1 << session_idx;
 933                         if (destroyed & (1 << session_idx)) {
 934                                 destroyed &= ~(1 << session_idx);
 935                                 allocated |= 1 << session_idx;
 936
 937                         } else if (!(allocated & (1 << session_idx))) {
 938                                 DRM_ERROR("Handle already in use!\n");
 939                                 r = -EINVAL;
 940                                 goto out;
 941                         }
 942
 943                         break;
 944
 945                 case 0x02000001: /* destroy */
 946                         destroyed |= 1 << session_idx;
 947                         break;
 948
 949                 default:
 950                         break;
 951                 }
 952
 953                 if (session_idx == -1) {
 954                         DRM_ERROR("no session command at start of IB\n");
 955                         r = -EINVAL;
 956                         goto out;
 957                 }
 958
 959                 idx += len / 4;
 960         }
 961
 962         if (allocated & ~created) {
 963                 DRM_ERROR("New session without create command!\n");
 964                 r = -ENOENT;
 965         }
 966
 967 out:
 968         if (!r) {
 969                 /* No error, free all destroyed handle slots */
 970                 tmp = destroyed;
 971                 amdgpu_ib_free(p->adev, ib, NULL);
 972         } else {
 973                 /* Error during parsing, free all allocated handle slots */
 974                 tmp = allocated;
 975         }
 976
 977         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
 978                 if (tmp & (1 << i))
 979                         atomic_set(&p->adev->vce.handles[i], 0);
 980
 981         return r;
 982 }
 983
 984 /**
 985  * amdgpu_vce_ring_emit_ib - execute indirect buffer
 986  *
 987  * @ring: engine to use
 988  * @ib: the IB to execute
 989  *
 990  */
 991 void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib,
 992                              unsigned vmid, bool ctx_switch)
 993 {
 994         amdgpu_ring_write(ring, VCE_CMD_IB);
 995         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
 996         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 997         amdgpu_ring_write(ring, ib->length_dw);
 998 }
 999
1000 /**
1001  * amdgpu_vce_ring_emit_fence - add a fence command to the ring
1002  *
1003  * @ring: engine to use
1004  * @fence: the fence
1005  *
1006  */
1007 void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1008                                 unsigned flags)
1009 {
1010         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1011
1012         amdgpu_ring_write(ring, VCE_CMD_FENCE);
1013         amdgpu_ring_write(ring, addr);
1014         amdgpu_ring_write(ring, upper_32_bits(addr));
1015         amdgpu_ring_write(ring, seq);
1016         amdgpu_ring_write(ring, VCE_CMD_TRAP);
1017         amdgpu_ring_write(ring, VCE_CMD_END);
1018 }
1019
1020 /**
1021  * amdgpu_vce_ring_test_ring - test if VCE ring is working
1022  *
1023  * @ring: the engine to test on
1024  *
1025  */
1026 int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring)
1027 {
1028         struct amdgpu_device *adev = ring->adev;
1029         uint32_t rptr = amdgpu_ring_get_rptr(ring);
1030         unsigned i;
1031         int r, timeout = adev->usec_timeout;
1032
1033         /* skip ring test for sriov*/
1034         if (amdgpu_sriov_vf(adev))
1035                 return 0;
1036
1037         r = amdgpu_ring_alloc(ring, 16);
1038         if (r) {
1039                 DRM_ERROR("amdgpu: vce failed to lock ring %d (%d).\n",
1040                           ring->idx, r);
1041                 return r;
1042         }
1043         amdgpu_ring_write(ring, VCE_CMD_END);
1044         amdgpu_ring_commit(ring);
1045
1046         for (i = 0; i < timeout; i++) {
1047                 if (amdgpu_ring_get_rptr(ring) != rptr)
1048                         break;
1049                 DRM_UDELAY(1);
1050         }
1051
1052         if (i < timeout) {
1053                 DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
1054                          ring->idx, i);
1055         } else {
1056                 DRM_ERROR("amdgpu: ring %d test failed\n",
1057                           ring->idx);
1058                 r = -ETIMEDOUT;
1059         }
1060
1061         return r;
1062 }
1063
1064 /**
1065  * amdgpu_vce_ring_test_ib - test if VCE IBs are working
1066  *
1067  * @ring: the engine to test on
1068  *
1069  */
1070 int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1071 {
1072         struct dma_fence *fence = NULL;
1073         long r;
1074
1075         /* skip vce ring1/2 ib test for now, since it's not reliable */
1076         if (ring != &ring->adev->vce.ring[0])
1077                 return 0;
1078
1079         r = amdgpu_vce_get_create_msg(ring, 1, NULL);
1080         if (r) {
1081                 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
1082                 goto error;
1083         }
1084
1085         r = amdgpu_vce_get_destroy_msg(ring, 1, true, &fence);
1086         if (r) {
1087                 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
1088                 goto error;
1089         }
1090
1091         r = dma_fence_wait_timeout(fence, false, timeout);
1092         if (r == 0) {
1093                 DRM_ERROR("amdgpu: IB test timed out.\n");
1094                 r = -ETIMEDOUT;
1095         } else if (r < 0) {
1096                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1097         } else {
1098                 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
1099                 r = 0;
1100         }
1101 error:
1102         dma_fence_put(fence);
1103         return r;
1104 }