drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #ifndef _AMDGPU_RAS_H
  25 #define _AMDGPU_RAS_H
  26
  27 #include <linux/debugfs.h>
  28 #include <linux/list.h>
  29 #include "ta_ras_if.h"
  30 #include "amdgpu_ras_eeprom.h"
  31
  32 struct amdgpu_iv_entry;
  33
  34 #define AMDGPU_RAS_FLAG_INIT_BY_VBIOS           (0x1 << 0)
  35 /* position of instance value in sub_block_index of
  36  * ta_ras_trigger_error_input, the sub block uses lower 12 bits
  37  */
  38 #define AMDGPU_RAS_INST_MASK 0xfffff000
  39 #define AMDGPU_RAS_INST_SHIFT 0xc
  40
  41 enum amdgpu_ras_block {
  42         AMDGPU_RAS_BLOCK__UMC = 0,
  43         AMDGPU_RAS_BLOCK__SDMA,
  44         AMDGPU_RAS_BLOCK__GFX,
  45         AMDGPU_RAS_BLOCK__MMHUB,
  46         AMDGPU_RAS_BLOCK__ATHUB,
  47         AMDGPU_RAS_BLOCK__PCIE_BIF,
  48         AMDGPU_RAS_BLOCK__HDP,
  49         AMDGPU_RAS_BLOCK__XGMI_WAFL,
  50         AMDGPU_RAS_BLOCK__DF,
  51         AMDGPU_RAS_BLOCK__SMN,
  52         AMDGPU_RAS_BLOCK__SEM,
  53         AMDGPU_RAS_BLOCK__MP0,
  54         AMDGPU_RAS_BLOCK__MP1,
  55         AMDGPU_RAS_BLOCK__FUSE,
  56         AMDGPU_RAS_BLOCK__MCA,
  57         AMDGPU_RAS_BLOCK__VCN,
  58         AMDGPU_RAS_BLOCK__JPEG,
  59
  60         AMDGPU_RAS_BLOCK__LAST
  61 };
  62
  63 enum amdgpu_ras_mca_block {
  64         AMDGPU_RAS_MCA_BLOCK__MP0 = 0,
  65         AMDGPU_RAS_MCA_BLOCK__MP1,
  66         AMDGPU_RAS_MCA_BLOCK__MPIO,
  67         AMDGPU_RAS_MCA_BLOCK__IOHC,
  68
  69         AMDGPU_RAS_MCA_BLOCK__LAST
  70 };
  71
  72 #define AMDGPU_RAS_BLOCK_COUNT  AMDGPU_RAS_BLOCK__LAST
  73 #define AMDGPU_RAS_MCA_BLOCK_COUNT      AMDGPU_RAS_MCA_BLOCK__LAST
  74 #define AMDGPU_RAS_BLOCK_MASK   ((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1)
  75
  76 enum amdgpu_ras_gfx_subblock {
  77         /* CPC */
  78         AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
  79         AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH =
  80                 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START,
  81         AMDGPU_RAS_BLOCK__GFX_CPC_UCODE,
  82         AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1,
  83         AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1,
  84         AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1,
  85         AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2,
  86         AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2,
  87         AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
  88         AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END =
  89                 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
  90         /* CPF */
  91         AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
  92         AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2 =
  93                 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
  94         AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1,
  95         AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
  96         AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
  97         /* CPG */
  98         AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
  99         AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ =
 100                 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
 101         AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG,
 102         AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
 103         AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
 104         /* GDS */
 105         AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
 106         AMDGPU_RAS_BLOCK__GFX_GDS_MEM = AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
 107         AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE,
 108         AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM,
 109         AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM,
 110         AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
 111         AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END =
 112                 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
 113         /* SPI */
 114         AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM,
 115         /* SQ */
 116         AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
 117         AMDGPU_RAS_BLOCK__GFX_SQ_SGPR = AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
 118         AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D,
 119         AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I,
 120         AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
 121         AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END = AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
 122         /* SQC (3 ranges) */
 123         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
 124         /* SQC range 0 */
 125         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START =
 126                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
 127         AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO =
 128                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START,
 129         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF,
 130         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO,
 131         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF,
 132         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO,
 133         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF,
 134         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
 135         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END =
 136                 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
 137         /* SQC range 1 */
 138         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
 139         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM =
 140                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
 141         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO,
 142         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO,
 143         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM,
 144         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM,
 145         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO,
 146         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO,
 147         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM,
 148         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
 149         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END =
 150                 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
 151         /* SQC range 2 */
 152         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
 153         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM =
 154                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
 155         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO,
 156         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO,
 157         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM,
 158         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM,
 159         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO,
 160         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO,
 161         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM,
 162         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
 163         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END =
 164                 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
 165         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END =
 166                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END,
 167         /* TA */
 168         AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
 169         AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO =
 170                 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
 171         AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO,
 172         AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO,
 173         AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO,
 174         AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
 175         AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
 176         /* TCA */
 177         AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
 178         AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO =
 179                 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
 180         AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
 181         AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END =
 182                 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
 183         /* TCC (5 sub-ranges) */
 184         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
 185         /* TCC range 0 */
 186         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START =
 187                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
 188         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA =
 189                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START,
 190         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1,
 191         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0,
 192         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1,
 193         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0,
 194         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1,
 195         AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG,
 196         AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
 197         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END =
 198                 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
 199         /* TCC range 1 */
 200         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
 201         AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC =
 202                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
 203         AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
 204         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END =
 205                 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
 206         /* TCC range 2 */
 207         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
 208         AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA =
 209                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
 210         AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL,
 211         AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO,
 212         AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN,
 213         AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ,
 214         AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO,
 215         AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM,
 216         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
 217         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END =
 218                 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
 219         /* TCC range 3 */
 220         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
 221         AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO =
 222                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
 223         AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
 224         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END =
 225                 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
 226         /* TCC range 4 */
 227         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
 228         AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN =
 229                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
 230         AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
 231         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END =
 232                 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
 233         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END =
 234                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END,
 235         /* TCI */
 236         AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM,
 237         /* TCP */
 238         AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
 239         AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM =
 240                 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
 241         AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM,
 242         AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO,
 243         AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO,
 244         AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM,
 245         AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0,
 246         AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
 247         AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END =
 248                 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
 249         /* TD */
 250         AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
 251         AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO =
 252                 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
 253         AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI,
 254         AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
 255         AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
 256         /* EA (3 sub-ranges) */
 257         AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
 258         /* EA range 0 */
 259         AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START =
 260                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
 261         AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM =
 262                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START,
 263         AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM,
 264         AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM,
 265         AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM,
 266         AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM,
 267         AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM,
 268         AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM,
 269         AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
 270         AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END =
 271                 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
 272         /* EA range 1 */
 273         AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
 274         AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM =
 275                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
 276         AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM,
 277         AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM,
 278         AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM,
 279         AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM,
 280         AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM,
 281         AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
 282         AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END =
 283                 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
 284         /* EA range 2 */
 285         AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
 286         AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM =
 287                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
 288         AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM,
 289         AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM,
 290         AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
 291         AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END =
 292                 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
 293         AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END =
 294                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END,
 295         /* UTC VM L2 bank */
 296         AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE,
 297         /* UTC VM walker */
 298         AMDGPU_RAS_BLOCK__UTC_VML2_WALKER,
 299         /* UTC ATC L2 2MB cache */
 300         AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK,
 301         /* UTC ATC L2 4KB cache */
 302         AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK,
 303         AMDGPU_RAS_BLOCK__GFX_MAX
 304 };
 305
 306 enum amdgpu_ras_error_type {
 307         AMDGPU_RAS_ERROR__NONE                                                  = 0,
 308         AMDGPU_RAS_ERROR__PARITY                                                = 1,
 309         AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE                                    = 2,
 310         AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE                                   = 4,
 311         AMDGPU_RAS_ERROR__POISON                                                = 8,
 312 };
 313
 314 enum amdgpu_ras_ret {
 315         AMDGPU_RAS_SUCCESS = 0,
 316         AMDGPU_RAS_FAIL,
 317         AMDGPU_RAS_UE,
 318         AMDGPU_RAS_CE,
 319         AMDGPU_RAS_PT,
 320 };
 321
 322 /* ras error status reisger fields */
 323 #define ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT     0x0
 324 #define ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK       0x00000001L
 325 #define ERR_STATUS_LO__MEMORY_ID__SHIFT                 0x18
 326 #define ERR_STATUS_LO__MEMORY_ID_MASK                   0xFF000000L
 327 #define ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT       0x2
 328 #define ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK         0x00000004L
 329 #define ERR_STATUS__ERR_CNT__SHIFT                      0x17
 330 #define ERR_STATUS__ERR_CNT_MASK                        0x03800000L
 331
 332 #define AMDGPU_RAS_REG_ENTRY(ip, inst, reg_lo, reg_hi) \
 333         ip##_HWIP, inst, reg_lo##_BASE_IDX, reg_lo, reg_hi##_BASE_IDX, reg_hi
 334
 335 #define AMDGPU_RAS_REG_ENTRY_OFFSET(hwip, ip_inst, segment, reg) \
 336         (adev->reg_offset[hwip][ip_inst][segment] + (reg))
 337
 338 #define AMDGPU_RAS_ERR_INFO_VALID       (1 << 0)
 339 #define AMDGPU_RAS_ERR_STATUS_VALID     (1 << 1)
 340 #define AMDGPU_RAS_ERR_ADDRESS_VALID    (1 << 2)
 341
 342 #define AMDGPU_RAS_GPU_RESET_MODE2_RESET  (0x1 << 0)
 343
 344 struct amdgpu_ras_err_status_reg_entry {
 345         uint32_t hwip;
 346         uint32_t ip_inst;
 347         uint32_t seg_lo;
 348         uint32_t reg_lo;
 349         uint32_t seg_hi;
 350         uint32_t reg_hi;
 351         uint32_t reg_inst;
 352         uint32_t flags;
 353         const char *block_name;
 354 };
 355
 356 struct amdgpu_ras_memory_id_entry {
 357         uint32_t memory_id;
 358         const char *name;
 359 };
 360
 361 struct ras_common_if {
 362         enum amdgpu_ras_block block;
 363         enum amdgpu_ras_error_type type;
 364         uint32_t sub_block_index;
 365         char name[32];
 366 };
 367
 368 #define MAX_UMC_CHANNEL_NUM 32
 369
 370 struct ecc_info_per_ch {
 371         uint16_t ce_count_lo_chip;
 372         uint16_t ce_count_hi_chip;
 373         uint64_t mca_umc_status;
 374         uint64_t mca_umc_addr;
 375         uint64_t mca_ceumc_addr;
 376 };
 377
 378 struct umc_ecc_info {
 379         struct ecc_info_per_ch ecc[MAX_UMC_CHANNEL_NUM];
 380
 381         /* Determine smu ecctable whether support
 382          * record correctable error address
 383          */
 384         int record_ce_addr_supported;
 385 };
 386
 387 struct amdgpu_ras {
 388         /* ras infrastructure */
 389         /* for ras itself. */
 390         uint32_t features;
 391         struct list_head head;
 392         /* sysfs */
 393         struct device_attribute features_attr;
 394         struct bin_attribute badpages_attr;
 395         struct dentry *de_ras_eeprom_table;
 396         /* block array */
 397         struct ras_manager *objs;
 398
 399         /* gpu recovery */
 400         struct work_struct recovery_work;
 401         atomic_t in_recovery;
 402         struct amdgpu_device *adev;
 403         /* error handler data */
 404         struct ras_err_handler_data *eh_data;
 405         struct mutex recovery_lock;
 406
 407         uint32_t flags;
 408         bool reboot;
 409         struct amdgpu_ras_eeprom_control eeprom_control;
 410
 411         bool error_query_ready;
 412
 413         /* bad page count threshold */
 414         uint32_t bad_page_cnt_threshold;
 415
 416         /* disable ras error count harvest in recovery */
 417         bool disable_ras_err_cnt_harvest;
 418
 419         /* is poison mode supported */
 420         bool poison_supported;
 421
 422         /* RAS count errors delayed work */
 423         struct delayed_work ras_counte_delay_work;
 424         atomic_t ras_ue_count;
 425         atomic_t ras_ce_count;
 426
 427         /* record umc error info queried from smu */
 428         struct umc_ecc_info umc_ecc;
 429
 430         /* Indicates smu whether need update bad channel info */
 431         bool update_channel_flag;
 432
 433         /* Record special requirements of gpu reset caller */
 434         uint32_t  gpu_reset_flags;
 435 };
 436
 437 struct ras_fs_data {
 438         char sysfs_name[32];
 439         char debugfs_name[32];
 440 };
 441
 442 struct ras_err_data {
 443         unsigned long ue_count;
 444         unsigned long ce_count;
 445         unsigned long err_addr_cnt;
 446         struct eeprom_table_record *err_addr;
 447 };
 448
 449 struct ras_err_handler_data {
 450         /* point to bad page records array */
 451         struct eeprom_table_record *bps;
 452         /* the count of entries */
 453         int count;
 454         /* the space can place new entries */
 455         int space_left;
 456 };
 457
 458 typedef int (*ras_ih_cb)(struct amdgpu_device *adev,
 459                 void *err_data,
 460                 struct amdgpu_iv_entry *entry);
 461
 462 struct ras_ih_data {
 463         /* interrupt bottom half */
 464         struct work_struct ih_work;
 465         int inuse;
 466         /* IP callback */
 467         ras_ih_cb cb;
 468         /* full of entries */
 469         unsigned char *ring;
 470         unsigned int ring_size;
 471         unsigned int element_size;
 472         unsigned int aligned_element_size;
 473         unsigned int rptr;
 474         unsigned int wptr;
 475 };
 476
 477 struct ras_manager {
 478         struct ras_common_if head;
 479         /* reference count */
 480         int use;
 481         /* ras block link */
 482         struct list_head node;
 483         /* the device */
 484         struct amdgpu_device *adev;
 485         /* sysfs */
 486         struct device_attribute sysfs_attr;
 487         int attr_inuse;
 488
 489         /* fs node name */
 490         struct ras_fs_data fs_data;
 491
 492         /* IH data */
 493         struct ras_ih_data ih_data;
 494
 495         struct ras_err_data err_data;
 496 };
 497
 498 struct ras_badpage {
 499         unsigned int bp;
 500         unsigned int size;
 501         unsigned int flags;
 502 };
 503
 504 /* interfaces for IP */
 505 struct ras_fs_if {
 506         struct ras_common_if head;
 507         const char* sysfs_name;
 508         char debugfs_name[32];
 509 };
 510
 511 struct ras_query_if {
 512         struct ras_common_if head;
 513         unsigned long ue_count;
 514         unsigned long ce_count;
 515 };
 516
 517 struct ras_inject_if {
 518         struct ras_common_if head;
 519         uint64_t address;
 520         uint64_t value;
 521         uint32_t instance_mask;
 522 };
 523
 524 struct ras_cure_if {
 525         struct ras_common_if head;
 526         uint64_t address;
 527 };
 528
 529 struct ras_ih_if {
 530         struct ras_common_if head;
 531         ras_ih_cb cb;
 532 };
 533
 534 struct ras_dispatch_if {
 535         struct ras_common_if head;
 536         struct amdgpu_iv_entry *entry;
 537 };
 538
 539 struct ras_debug_if {
 540         union {
 541                 struct ras_common_if head;
 542                 struct ras_inject_if inject;
 543         };
 544         int op;
 545 };
 546
 547 struct amdgpu_ras_block_object {
 548         struct ras_common_if  ras_comm;
 549
 550         int (*ras_block_match)(struct amdgpu_ras_block_object *block_obj,
 551                                 enum amdgpu_ras_block block, uint32_t sub_block_index);
 552         int (*ras_late_init)(struct amdgpu_device *adev, struct ras_common_if *ras_block);
 553         void (*ras_fini)(struct amdgpu_device *adev, struct ras_common_if *ras_block);
 554         ras_ih_cb ras_cb;
 555         const struct amdgpu_ras_block_hw_ops *hw_ops;
 556 };
 557
 558 struct amdgpu_ras_block_hw_ops {
 559         int  (*ras_error_inject)(struct amdgpu_device *adev,
 560                         void *inject_if, uint32_t instance_mask);
 561         void (*query_ras_error_count)(struct amdgpu_device *adev, void *ras_error_status);
 562         void (*query_ras_error_status)(struct amdgpu_device *adev);
 563         void (*query_ras_error_address)(struct amdgpu_device *adev, void *ras_error_status);
 564         void (*reset_ras_error_count)(struct amdgpu_device *adev);
 565         void (*reset_ras_error_status)(struct amdgpu_device *adev);
 566         bool (*query_poison_status)(struct amdgpu_device *adev);
 567         bool (*handle_poison_consumption)(struct amdgpu_device *adev);
 568 };
 569
 570 /* work flow
 571  * vbios
 572  * 1: ras feature enable (enabled by default)
 573  * psp
 574  * 2: ras framework init (in ip_init)
 575  * IP
 576  * 3: IH add
 577  * 4: debugfs/sysfs create
 578  * 5: query/inject
 579  * 6: debugfs/sysfs remove
 580  * 7: IH remove
 581  * 8: feature disable
 582  */
 583
 584
 585 int amdgpu_ras_recovery_init(struct amdgpu_device *adev);
 586
 587 void amdgpu_ras_resume(struct amdgpu_device *adev);
 588 void amdgpu_ras_suspend(struct amdgpu_device *adev);
 589
 590 int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
 591                                  unsigned long *ce_count,
 592                                  unsigned long *ue_count,
 593                                  struct ras_query_if *query_info);
 594
 595 /* error handling functions */
 596 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
 597                 struct eeprom_table_record *bps, int pages);
 598
 599 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev,
 600                 unsigned long *new_cnt);
 601
 602 static inline enum ta_ras_block
 603 amdgpu_ras_block_to_ta(enum amdgpu_ras_block block) {
 604         switch (block) {
 605         case AMDGPU_RAS_BLOCK__UMC:
 606                 return TA_RAS_BLOCK__UMC;
 607         case AMDGPU_RAS_BLOCK__SDMA:
 608                 return TA_RAS_BLOCK__SDMA;
 609         case AMDGPU_RAS_BLOCK__GFX:
 610                 return TA_RAS_BLOCK__GFX;
 611         case AMDGPU_RAS_BLOCK__MMHUB:
 612                 return TA_RAS_BLOCK__MMHUB;
 613         case AMDGPU_RAS_BLOCK__ATHUB:
 614                 return TA_RAS_BLOCK__ATHUB;
 615         case AMDGPU_RAS_BLOCK__PCIE_BIF:
 616                 return TA_RAS_BLOCK__PCIE_BIF;
 617         case AMDGPU_RAS_BLOCK__HDP:
 618                 return TA_RAS_BLOCK__HDP;
 619         case AMDGPU_RAS_BLOCK__XGMI_WAFL:
 620                 return TA_RAS_BLOCK__XGMI_WAFL;
 621         case AMDGPU_RAS_BLOCK__DF:
 622                 return TA_RAS_BLOCK__DF;
 623         case AMDGPU_RAS_BLOCK__SMN:
 624                 return TA_RAS_BLOCK__SMN;
 625         case AMDGPU_RAS_BLOCK__SEM:
 626                 return TA_RAS_BLOCK__SEM;
 627         case AMDGPU_RAS_BLOCK__MP0:
 628                 return TA_RAS_BLOCK__MP0;
 629         case AMDGPU_RAS_BLOCK__MP1:
 630                 return TA_RAS_BLOCK__MP1;
 631         case AMDGPU_RAS_BLOCK__FUSE:
 632                 return TA_RAS_BLOCK__FUSE;
 633         case AMDGPU_RAS_BLOCK__MCA:
 634                 return TA_RAS_BLOCK__MCA;
 635         case AMDGPU_RAS_BLOCK__VCN:
 636                 return TA_RAS_BLOCK__VCN;
 637         case AMDGPU_RAS_BLOCK__JPEG:
 638                 return TA_RAS_BLOCK__JPEG;
 639         default:
 640                 WARN_ONCE(1, "RAS ERROR: unexpected block id %d\n", block);
 641                 return TA_RAS_BLOCK__UMC;
 642         }
 643 }
 644
 645 static inline enum ta_ras_error_type
 646 amdgpu_ras_error_to_ta(enum amdgpu_ras_error_type error) {
 647         switch (error) {
 648         case AMDGPU_RAS_ERROR__NONE:
 649                 return TA_RAS_ERROR__NONE;
 650         case AMDGPU_RAS_ERROR__PARITY:
 651                 return TA_RAS_ERROR__PARITY;
 652         case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE:
 653                 return TA_RAS_ERROR__SINGLE_CORRECTABLE;
 654         case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE:
 655                 return TA_RAS_ERROR__MULTI_UNCORRECTABLE;
 656         case AMDGPU_RAS_ERROR__POISON:
 657                 return TA_RAS_ERROR__POISON;
 658         default:
 659                 WARN_ONCE(1, "RAS ERROR: unexpected error type %d\n", error);
 660                 return TA_RAS_ERROR__NONE;
 661         }
 662 }
 663
 664 /* called in ip_init and ip_fini */
 665 int amdgpu_ras_init(struct amdgpu_device *adev);
 666 int amdgpu_ras_late_init(struct amdgpu_device *adev);
 667 int amdgpu_ras_fini(struct amdgpu_device *adev);
 668 int amdgpu_ras_pre_fini(struct amdgpu_device *adev);
 669
 670 int amdgpu_ras_block_late_init(struct amdgpu_device *adev,
 671                         struct ras_common_if *ras_block);
 672
 673 void amdgpu_ras_block_late_fini(struct amdgpu_device *adev,
 674                           struct ras_common_if *ras_block);
 675
 676 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 677                 struct ras_common_if *head, bool enable);
 678
 679 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
 680                 struct ras_common_if *head, bool enable);
 681
 682 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
 683                 struct ras_common_if *head);
 684
 685 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
 686                 struct ras_common_if *head);
 687
 688 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev);
 689
 690 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
 691                 struct ras_query_if *info);
 692
 693 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
 694                 enum amdgpu_ras_block block);
 695
 696 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
 697                 struct ras_inject_if *info);
 698
 699 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
 700                 struct ras_common_if *head);
 701
 702 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
 703                 struct ras_common_if *head);
 704
 705 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
 706                 struct ras_dispatch_if *info);
 707
 708 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 709                 struct ras_common_if *head);
 710
 711 extern atomic_t amdgpu_ras_in_intr;
 712
 713 static inline bool amdgpu_ras_intr_triggered(void)
 714 {
 715         return !!atomic_read(&amdgpu_ras_in_intr);
 716 }
 717
 718 static inline void amdgpu_ras_intr_cleared(void)
 719 {
 720         atomic_set(&amdgpu_ras_in_intr, 0);
 721 }
 722
 723 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev);
 724
 725 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready);
 726
 727 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev);
 728
 729 void amdgpu_release_ras_context(struct amdgpu_device *adev);
 730
 731 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev);
 732
 733 const char *get_ras_block_str(struct ras_common_if *ras_block);
 734
 735 bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev);
 736
 737 int amdgpu_ras_is_supported(struct amdgpu_device *adev, unsigned int block);
 738
 739 int amdgpu_ras_reset_gpu(struct amdgpu_device *adev);
 740
 741 struct amdgpu_ras* amdgpu_ras_get_context(struct amdgpu_device *adev);
 742
 743 int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con);
 744
 745 int amdgpu_ras_register_ras_block(struct amdgpu_device *adev,
 746                                 struct amdgpu_ras_block_object *ras_block_obj);
 747 void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev);
 748 void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name);
 749 bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev,
 750                                          const struct amdgpu_ras_err_status_reg_entry *reg_entry,
 751                                          uint32_t instance,
 752                                          uint32_t *memory_id);
 753 bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev,
 754                                        const struct amdgpu_ras_err_status_reg_entry *reg_entry,
 755                                        uint32_t instance,
 756                                        unsigned long *err_cnt);
 757 void amdgpu_ras_inst_query_ras_error_count(struct amdgpu_device *adev,
 758                                            const struct amdgpu_ras_err_status_reg_entry *reg_list,
 759                                            uint32_t reg_list_size,
 760                                            const struct amdgpu_ras_memory_id_entry *mem_list,
 761                                            uint32_t mem_list_size,
 762                                            uint32_t instance,
 763                                            uint32_t err_type,
 764                                            unsigned long *err_count);
 765 void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev,
 766                                            const struct amdgpu_ras_err_status_reg_entry *reg_list,
 767                                            uint32_t reg_list_size,
 768                                            uint32_t instance);
 769 #endif