drivers/phy/phy-omap-control.c

   1 /*
   2  * omap-control-phy.c - The PHY part of control module.
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * Author: Kishon Vijay Abraham I <[email protected]>
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/slab.h>
  22 #include <linux/of.h>
  23 #include <linux/of_device.h>
  24 #include <linux/err.h>
  25 #include <linux/io.h>
  26 #include <linux/clk.h>
  27 #include <linux/phy/omap_control_phy.h>
  28
  29 /**
  30  * omap_control_pcie_pcs - set the PCS delay count
  31  * @dev: the control module device
  32  * @id: index of the pcie PHY (should be 1 or 2)
  33  * @delay: 8 bit delay value
  34  */
  35 void omap_control_pcie_pcs(struct device *dev, u8 id, u8 delay)
  36 {
  37         u32 val;
  38         struct omap_control_phy *control_phy;
  39
  40         if (IS_ERR(dev) || !dev) {
  41                 pr_err("%s: invalid device\n", __func__);
  42                 return;
  43         }
  44
  45         control_phy = dev_get_drvdata(dev);
  46         if (!control_phy) {
  47                 dev_err(dev, "%s: invalid control phy device\n", __func__);
  48                 return;
  49         }
  50
  51         if (control_phy->type != OMAP_CTRL_TYPE_PCIE) {
  52                 dev_err(dev, "%s: unsupported operation\n", __func__);
  53                 return;
  54         }
  55
  56         val = readl(control_phy->pcie_pcs);
  57         val &= ~(OMAP_CTRL_PCIE_PCS_MASK <<
  58                 (id * OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT));
  59         val |= delay << (id * OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT);
  60         writel(val, control_phy->pcie_pcs);
  61 }
  62 EXPORT_SYMBOL_GPL(omap_control_pcie_pcs);
  63
  64 /**
  65  * omap_control_phy_power - power on/off the phy using control module reg
  66  * @dev: the control module device
  67  * @on: 0 or 1, based on powering on or off the PHY
  68  */
  69 void omap_control_phy_power(struct device *dev, int on)
  70 {
  71         u32 val;
  72         unsigned long rate;
  73         struct omap_control_phy *control_phy;
  74
  75         if (IS_ERR(dev) || !dev) {
  76                 pr_err("%s: invalid device\n", __func__);
  77                 return;
  78         }
  79
  80         control_phy = dev_get_drvdata(dev);
  81         if (!control_phy) {
  82                 dev_err(dev, "%s: invalid control phy device\n", __func__);
  83                 return;
  84         }
  85
  86         if (control_phy->type == OMAP_CTRL_TYPE_OTGHS)
  87                 return;
  88
  89         val = readl(control_phy->power);
  90
  91         switch (control_phy->type) {
  92         case OMAP_CTRL_TYPE_USB2:
  93                 if (on)
  94                         val &= ~OMAP_CTRL_DEV_PHY_PD;
  95                 else
  96                         val |= OMAP_CTRL_DEV_PHY_PD;
  97                 break;
  98
  99         case OMAP_CTRL_TYPE_PCIE:
 100         case OMAP_CTRL_TYPE_PIPE3:
 101                 rate = clk_get_rate(control_phy->sys_clk);
 102                 rate = rate/1000000;
 103
 104                 if (on) {
 105                         val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
 106                                 OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
 107                         val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON <<
 108                                 OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
 109                         val |= rate <<
 110                                 OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
 111                 } else {
 112                         val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
 113                         val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF <<
 114                                 OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
 115                 }
 116                 break;
 117
 118         case OMAP_CTRL_TYPE_DRA7USB2:
 119                 if (on)
 120                         val &= ~OMAP_CTRL_USB2_PHY_PD;
 121                 else
 122                         val |= OMAP_CTRL_USB2_PHY_PD;
 123                 break;
 124
 125         case OMAP_CTRL_TYPE_AM437USB2:
 126                 if (on) {
 127                         val &= ~(AM437X_CTRL_USB2_PHY_PD |
 128                                         AM437X_CTRL_USB2_OTG_PD);
 129                         val |= (AM437X_CTRL_USB2_OTGVDET_EN |
 130                                         AM437X_CTRL_USB2_OTGSESSEND_EN);
 131                 } else {
 132                         val &= ~(AM437X_CTRL_USB2_OTGVDET_EN |
 133                                         AM437X_CTRL_USB2_OTGSESSEND_EN);
 134                         val |= (AM437X_CTRL_USB2_PHY_PD |
 135                                          AM437X_CTRL_USB2_OTG_PD);
 136                 }
 137                 break;
 138         default:
 139                 dev_err(dev, "%s: type %d not recognized\n",
 140                         __func__, control_phy->type);
 141                 break;
 142         }
 143
 144         writel(val, control_phy->power);
 145 }
 146 EXPORT_SYMBOL_GPL(omap_control_phy_power);
 147
 148 /**
 149  * omap_control_usb_host_mode - set AVALID, VBUSVALID and ID pin in grounded
 150  * @ctrl_phy: struct omap_control_phy *
 151  *
 152  * Writes to the mailbox register to notify the usb core that a usb
 153  * device has been connected.
 154  */
 155 static void omap_control_usb_host_mode(struct omap_control_phy *ctrl_phy)
 156 {
 157         u32 val;
 158
 159         val = readl(ctrl_phy->otghs_control);
 160         val &= ~(OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_SESSEND);
 161         val |= OMAP_CTRL_DEV_AVALID | OMAP_CTRL_DEV_VBUSVALID;
 162         writel(val, ctrl_phy->otghs_control);
 163 }
 164
 165 /**
 166  * omap_control_usb_device_mode - set AVALID, VBUSVALID and ID pin in high
 167  * impedance
 168  * @ctrl_phy: struct omap_control_phy *
 169  *
 170  * Writes to the mailbox register to notify the usb core that it has been
 171  * connected to a usb host.
 172  */
 173 static void omap_control_usb_device_mode(struct omap_control_phy *ctrl_phy)
 174 {
 175         u32 val;
 176
 177         val = readl(ctrl_phy->otghs_control);
 178         val &= ~OMAP_CTRL_DEV_SESSEND;
 179         val |= OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_AVALID |
 180                 OMAP_CTRL_DEV_VBUSVALID;
 181         writel(val, ctrl_phy->otghs_control);
 182 }
 183
 184 /**
 185  * omap_control_usb_set_sessionend - Enable SESSIONEND and IDIG to high
 186  * impedance
 187  * @ctrl_phy: struct omap_control_phy *
 188  *
 189  * Writes to the mailbox register to notify the usb core it's now in
 190  * disconnected state.
 191  */
 192 static void omap_control_usb_set_sessionend(struct omap_control_phy *ctrl_phy)
 193 {
 194         u32 val;
 195
 196         val = readl(ctrl_phy->otghs_control);
 197         val &= ~(OMAP_CTRL_DEV_AVALID | OMAP_CTRL_DEV_VBUSVALID);
 198         val |= OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_SESSEND;
 199         writel(val, ctrl_phy->otghs_control);
 200 }
 201
 202 /**
 203  * omap_control_usb_set_mode - Calls to functions to set USB in one of host mode
 204  * or device mode or to denote disconnected state
 205  * @dev: the control module device
 206  * @mode: The mode to which usb should be configured
 207  *
 208  * This is an API to write to the mailbox register to notify the usb core that
 209  * a usb device has been connected.
 210  */
 211 void omap_control_usb_set_mode(struct device *dev,
 212         enum omap_control_usb_mode mode)
 213 {
 214         struct omap_control_phy *ctrl_phy;
 215
 216         if (IS_ERR(dev) || !dev)
 217                 return;
 218
 219         ctrl_phy = dev_get_drvdata(dev);
 220
 221         if (!ctrl_phy) {
 222                 dev_err(dev, "Invalid control phy device\n");
 223                 return;
 224         }
 225
 226         if (ctrl_phy->type != OMAP_CTRL_TYPE_OTGHS)
 227                 return;
 228
 229         switch (mode) {
 230         case USB_MODE_HOST:
 231                 omap_control_usb_host_mode(ctrl_phy);
 232                 break;
 233         case USB_MODE_DEVICE:
 234                 omap_control_usb_device_mode(ctrl_phy);
 235                 break;
 236         case USB_MODE_DISCONNECT:
 237                 omap_control_usb_set_sessionend(ctrl_phy);
 238                 break;
 239         default:
 240                 dev_vdbg(dev, "invalid omap control usb mode\n");
 241         }
 242 }
 243 EXPORT_SYMBOL_GPL(omap_control_usb_set_mode);
 244
 245 #ifdef CONFIG_OF
 246
 247 static const enum omap_control_phy_type otghs_data = OMAP_CTRL_TYPE_OTGHS;
 248 static const enum omap_control_phy_type usb2_data = OMAP_CTRL_TYPE_USB2;
 249 static const enum omap_control_phy_type pipe3_data = OMAP_CTRL_TYPE_PIPE3;
 250 static const enum omap_control_phy_type pcie_data = OMAP_CTRL_TYPE_PCIE;
 251 static const enum omap_control_phy_type dra7usb2_data = OMAP_CTRL_TYPE_DRA7USB2;
 252 static const enum omap_control_phy_type am437usb2_data = OMAP_CTRL_TYPE_AM437USB2;
 253
 254 static const struct of_device_id omap_control_phy_id_table[] = {
 255         {
 256                 .compatible = "ti,control-phy-otghs",
 257                 .data = &otghs_data,
 258         },
 259         {
 260                 .compatible = "ti,control-phy-usb2",
 261                 .data = &usb2_data,
 262         },
 263         {
 264                 .compatible = "ti,control-phy-pipe3",
 265                 .data = &pipe3_data,
 266         },
 267         {
 268                 .compatible = "ti,control-phy-pcie",
 269                 .data = &pcie_data,
 270         },
 271         {
 272                 .compatible = "ti,control-phy-usb2-dra7",
 273                 .data = &dra7usb2_data,
 274         },
 275         {
 276                 .compatible = "ti,control-phy-usb2-am437",
 277                 .data = &am437usb2_data,
 278         },
 279         {},
 280 };
 281 MODULE_DEVICE_TABLE(of, omap_control_phy_id_table);
 282 #endif
 283
 284
 285 static int omap_control_phy_probe(struct platform_device *pdev)
 286 {
 287         struct resource *res;
 288         const struct of_device_id *of_id;
 289         struct omap_control_phy *control_phy;
 290
 291         of_id = of_match_device(of_match_ptr(omap_control_phy_id_table),
 292                                 &pdev->dev);
 293         if (!of_id)
 294                 return -EINVAL;
 295
 296         control_phy = devm_kzalloc(&pdev->dev, sizeof(*control_phy),
 297                 GFP_KERNEL);
 298         if (!control_phy)
 299                 return -ENOMEM;
 300
 301         control_phy->dev = &pdev->dev;
 302         control_phy->type = *(enum omap_control_phy_type *)of_id->data;
 303
 304         if (control_phy->type == OMAP_CTRL_TYPE_OTGHS) {
 305                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 306                         "otghs_control");
 307                 control_phy->otghs_control = devm_ioremap_resource(
 308                         &pdev->dev, res);
 309                 if (IS_ERR(control_phy->otghs_control))
 310                         return PTR_ERR(control_phy->otghs_control);
 311         } else {
 312                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 313                                 "power");
 314                 control_phy->power = devm_ioremap_resource(&pdev->dev, res);
 315                 if (IS_ERR(control_phy->power)) {
 316                         dev_err(&pdev->dev, "Couldn't get power register\n");
 317                         return PTR_ERR(control_phy->power);
 318                 }
 319         }
 320
 321         if (control_phy->type == OMAP_CTRL_TYPE_PIPE3 ||
 322             control_phy->type == OMAP_CTRL_TYPE_PCIE) {
 323                 control_phy->sys_clk = devm_clk_get(control_phy->dev,
 324                         "sys_clkin");
 325                 if (IS_ERR(control_phy->sys_clk)) {
 326                         pr_err("%s: unable to get sys_clkin\n", __func__);
 327                         return -EINVAL;
 328                 }
 329         }
 330
 331         if (control_phy->type == OMAP_CTRL_TYPE_PCIE) {
 332                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 333                                                    "pcie_pcs");
 334                 control_phy->pcie_pcs = devm_ioremap_resource(&pdev->dev, res);
 335                 if (IS_ERR(control_phy->pcie_pcs))
 336                         return PTR_ERR(control_phy->pcie_pcs);
 337         }
 338
 339         dev_set_drvdata(control_phy->dev, control_phy);
 340
 341         return 0;
 342 }
 343
 344 static struct platform_driver omap_control_phy_driver = {
 345         .probe          = omap_control_phy_probe,
 346         .driver         = {
 347                 .name   = "omap-control-phy",
 348                 .of_match_table = of_match_ptr(omap_control_phy_id_table),
 349         },
 350 };
 351
 352 static int __init omap_control_phy_init(void)
 353 {
 354         return platform_driver_register(&omap_control_phy_driver);
 355 }
 356 subsys_initcall(omap_control_phy_init);
 357
 358 static void __exit omap_control_phy_exit(void)
 359 {
 360         platform_driver_unregister(&omap_control_phy_driver);
 361 }
 362 module_exit(omap_control_phy_exit);
 363
 364 MODULE_ALIAS("platform: omap_control_phy");
 365 MODULE_AUTHOR("Texas Instruments Inc.");
 366 MODULE_DESCRIPTION("OMAP Control Module PHY Driver");
 367 MODULE_LICENSE("GPL v2");