drivers/gpu/drm/tilcdc/tilcdc_drv.c

   1 /*
   2  * Copyright (C) 2012 Texas Instruments
   3  * Author: Rob Clark <[email protected]>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 /* LCDC DRM driver, based on da8xx-fb */
  19
  20 #include <linux/component.h>
  21 #include <linux/pinctrl/consumer.h>
  22 #include <linux/suspend.h>
  23 #include <drm/drm_atomic.h>
  24 #include <drm/drm_atomic_helper.h>
  25 #include <drm/drm_fb_helper.h>
  26 #include <drm/drm_gem_framebuffer_helper.h>
  27 #include <drm/drm_probe_helper.h>
  28
  29 #include "tilcdc_drv.h"
  30 #include "tilcdc_regs.h"
  31 #include "tilcdc_tfp410.h"
  32 #include "tilcdc_panel.h"
  33 #include "tilcdc_external.h"
  34
  35 static LIST_HEAD(module_list);
  36
  37 static const u32 tilcdc_rev1_formats[] = { DRM_FORMAT_RGB565 };
  38
  39 static const u32 tilcdc_straight_formats[] = { DRM_FORMAT_RGB565,
  40                                                DRM_FORMAT_BGR888,
  41                                                DRM_FORMAT_XBGR8888 };
  42
  43 static const u32 tilcdc_crossed_formats[] = { DRM_FORMAT_BGR565,
  44                                               DRM_FORMAT_RGB888,
  45                                               DRM_FORMAT_XRGB8888 };
  46
  47 static const u32 tilcdc_legacy_formats[] = { DRM_FORMAT_RGB565,
  48                                              DRM_FORMAT_RGB888,
  49                                              DRM_FORMAT_XRGB8888 };
  50
  51 void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
  52                 const struct tilcdc_module_ops *funcs)
  53 {
  54         mod->name = name;
  55         mod->funcs = funcs;
  56         INIT_LIST_HEAD(&mod->list);
  57         list_add(&mod->list, &module_list);
  58 }
  59
  60 void tilcdc_module_cleanup(struct tilcdc_module *mod)
  61 {
  62         list_del(&mod->list);
  63 }
  64
  65 static struct of_device_id tilcdc_of_match[];
  66
  67 static struct drm_framebuffer *tilcdc_fb_create(struct drm_device *dev,
  68                 struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd)
  69 {
  70         return drm_gem_fb_create(dev, file_priv, mode_cmd);
  71 }
  72
  73 static int tilcdc_atomic_check(struct drm_device *dev,
  74                                struct drm_atomic_state *state)
  75 {
  76         int ret;
  77
  78         ret = drm_atomic_helper_check_modeset(dev, state);
  79         if (ret)
  80                 return ret;
  81
  82         ret = drm_atomic_helper_check_planes(dev, state);
  83         if (ret)
  84                 return ret;
  85
  86         /*
  87          * tilcdc ->atomic_check can update ->mode_changed if pixel format
  88          * changes, hence will we check modeset changes again.
  89          */
  90         ret = drm_atomic_helper_check_modeset(dev, state);
  91         if (ret)
  92                 return ret;
  93
  94         return ret;
  95 }
  96
  97 static int tilcdc_commit(struct drm_device *dev,
  98                   struct drm_atomic_state *state,
  99                   bool async)
 100 {
 101         int ret;
 102
 103         ret = drm_atomic_helper_prepare_planes(dev, state);
 104         if (ret)
 105                 return ret;
 106
 107         ret = drm_atomic_helper_swap_state(state, true);
 108         if (ret) {
 109                 drm_atomic_helper_cleanup_planes(dev, state);
 110                 return ret;
 111         }
 112
 113         /*
 114          * Everything below can be run asynchronously without the need to grab
 115          * any modeset locks at all under one condition: It must be guaranteed
 116          * that the asynchronous work has either been cancelled (if the driver
 117          * supports it, which at least requires that the framebuffers get
 118          * cleaned up with drm_atomic_helper_cleanup_planes()) or completed
 119          * before the new state gets committed on the software side with
 120          * drm_atomic_helper_swap_state().
 121          *
 122          * This scheme allows new atomic state updates to be prepared and
 123          * checked in parallel to the asynchronous completion of the previous
 124          * update. Which is important since compositors need to figure out the
 125          * composition of the next frame right after having submitted the
 126          * current layout.
 127          */
 128
 129         drm_atomic_helper_commit_modeset_disables(dev, state);
 130
 131         drm_atomic_helper_commit_planes(dev, state, 0);
 132
 133         drm_atomic_helper_commit_modeset_enables(dev, state);
 134
 135         drm_atomic_helper_wait_for_vblanks(dev, state);
 136
 137         drm_atomic_helper_cleanup_planes(dev, state);
 138
 139         return 0;
 140 }
 141
 142 static const struct drm_mode_config_funcs mode_config_funcs = {
 143         .fb_create = tilcdc_fb_create,
 144         .atomic_check = tilcdc_atomic_check,
 145         .atomic_commit = tilcdc_commit,
 146 };
 147
 148 static void modeset_init(struct drm_device *dev)
 149 {
 150         struct tilcdc_drm_private *priv = dev->dev_private;
 151         struct tilcdc_module *mod;
 152
 153         list_for_each_entry(mod, &module_list, list) {
 154                 DBG("loading module: %s", mod->name);
 155                 mod->funcs->modeset_init(mod, dev);
 156         }
 157
 158         dev->mode_config.min_width = 0;
 159         dev->mode_config.min_height = 0;
 160         dev->mode_config.max_width = tilcdc_crtc_max_width(priv->crtc);
 161         dev->mode_config.max_height = 2048;
 162         dev->mode_config.funcs = &mode_config_funcs;
 163 }
 164
 165 #ifdef CONFIG_CPU_FREQ
 166 static int cpufreq_transition(struct notifier_block *nb,
 167                                      unsigned long val, void *data)
 168 {
 169         struct tilcdc_drm_private *priv = container_of(nb,
 170                         struct tilcdc_drm_private, freq_transition);
 171
 172         if (val == CPUFREQ_POSTCHANGE)
 173                 tilcdc_crtc_update_clk(priv->crtc);
 174
 175         return 0;
 176 }
 177 #endif
 178
 179 /*
 180  * DRM operations:
 181  */
 182
 183 static void tilcdc_fini(struct drm_device *dev)
 184 {
 185         struct tilcdc_drm_private *priv = dev->dev_private;
 186
 187 #ifdef CONFIG_CPU_FREQ
 188         if (priv->freq_transition.notifier_call)
 189                 cpufreq_unregister_notifier(&priv->freq_transition,
 190                                             CPUFREQ_TRANSITION_NOTIFIER);
 191 #endif
 192
 193         if (priv->crtc)
 194                 tilcdc_crtc_shutdown(priv->crtc);
 195
 196         if (priv->is_registered)
 197                 drm_dev_unregister(dev);
 198
 199         drm_kms_helper_poll_fini(dev);
 200         drm_irq_uninstall(dev);
 201         drm_mode_config_cleanup(dev);
 202         tilcdc_remove_external_device(dev);
 203
 204         if (priv->clk)
 205                 clk_put(priv->clk);
 206
 207         if (priv->mmio)
 208                 iounmap(priv->mmio);
 209
 210         if (priv->wq) {
 211                 flush_workqueue(priv->wq);
 212                 destroy_workqueue(priv->wq);
 213         }
 214
 215         dev->dev_private = NULL;
 216
 217         pm_runtime_disable(dev->dev);
 218
 219         drm_dev_put(dev);
 220 }
 221
 222 static int tilcdc_init(struct drm_driver *ddrv, struct device *dev)
 223 {
 224         struct drm_device *ddev;
 225         struct platform_device *pdev = to_platform_device(dev);
 226         struct device_node *node = dev->of_node;
 227         struct tilcdc_drm_private *priv;
 228         struct resource *res;
 229         u32 bpp = 0;
 230         int ret;
 231
 232         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 233         if (!priv)
 234                 return -ENOMEM;
 235
 236         ddev = drm_dev_alloc(ddrv, dev);
 237         if (IS_ERR(ddev))
 238                 return PTR_ERR(ddev);
 239
 240         ddev->dev_private = priv;
 241         platform_set_drvdata(pdev, ddev);
 242         drm_mode_config_init(ddev);
 243
 244         priv->is_componentized =
 245                 tilcdc_get_external_components(dev, NULL) > 0;
 246
 247         priv->wq = alloc_ordered_workqueue("tilcdc", 0);
 248         if (!priv->wq) {
 249                 ret = -ENOMEM;
 250                 goto init_failed;
 251         }
 252
 253         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 254         if (!res) {
 255                 dev_err(dev, "failed to get memory resource\n");
 256                 ret = -EINVAL;
 257                 goto init_failed;
 258         }
 259
 260         priv->mmio = ioremap_nocache(res->start, resource_size(res));
 261         if (!priv->mmio) {
 262                 dev_err(dev, "failed to ioremap\n");
 263                 ret = -ENOMEM;
 264                 goto init_failed;
 265         }
 266
 267         priv->clk = clk_get(dev, "fck");
 268         if (IS_ERR(priv->clk)) {
 269                 dev_err(dev, "failed to get functional clock\n");
 270                 ret = -ENODEV;
 271                 goto init_failed;
 272         }
 273
 274         if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth))
 275                 priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH;
 276
 277         DBG("Maximum Bandwidth Value %d", priv->max_bandwidth);
 278
 279         if (of_property_read_u32(node, "max-width", &priv->max_width))
 280                 priv->max_width = TILCDC_DEFAULT_MAX_WIDTH;
 281
 282         DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width);
 283
 284         if (of_property_read_u32(node, "max-pixelclock",
 285                                         &priv->max_pixelclock))
 286                 priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK;
 287
 288         DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock);
 289
 290         pm_runtime_enable(dev);
 291
 292         /* Determine LCD IP Version */
 293         pm_runtime_get_sync(dev);
 294         switch (tilcdc_read(ddev, LCDC_PID_REG)) {
 295         case 0x4c100102:
 296                 priv->rev = 1;
 297                 break;
 298         case 0x4f200800:
 299         case 0x4f201000:
 300                 priv->rev = 2;
 301                 break;
 302         default:
 303                 dev_warn(dev, "Unknown PID Reg value 0x%08x, "
 304                         "defaulting to LCD revision 1\n",
 305                         tilcdc_read(ddev, LCDC_PID_REG));
 306                 priv->rev = 1;
 307                 break;
 308         }
 309
 310         pm_runtime_put_sync(dev);
 311
 312         if (priv->rev == 1) {
 313                 DBG("Revision 1 LCDC supports only RGB565 format");
 314                 priv->pixelformats = tilcdc_rev1_formats;
 315                 priv->num_pixelformats = ARRAY_SIZE(tilcdc_rev1_formats);
 316                 bpp = 16;
 317         } else {
 318                 const char *str = "\0";
 319
 320                 of_property_read_string(node, "blue-and-red-wiring", &str);
 321                 if (0 == strcmp(str, "crossed")) {
 322                         DBG("Configured for crossed blue and red wires");
 323                         priv->pixelformats = tilcdc_crossed_formats;
 324                         priv->num_pixelformats =
 325                                 ARRAY_SIZE(tilcdc_crossed_formats);
 326                         bpp = 32; /* Choose bpp with RGB support for fbdef */
 327                 } else if (0 == strcmp(str, "straight")) {
 328                         DBG("Configured for straight blue and red wires");
 329                         priv->pixelformats = tilcdc_straight_formats;
 330                         priv->num_pixelformats =
 331                                 ARRAY_SIZE(tilcdc_straight_formats);
 332                         bpp = 16; /* Choose bpp with RGB support for fbdef */
 333                 } else {
 334                         DBG("Blue and red wiring '%s' unknown, use legacy mode",
 335                             str);
 336                         priv->pixelformats = tilcdc_legacy_formats;
 337                         priv->num_pixelformats =
 338                                 ARRAY_SIZE(tilcdc_legacy_formats);
 339                         bpp = 16; /* This is just a guess */
 340                 }
 341         }
 342
 343         ret = tilcdc_crtc_create(ddev);
 344         if (ret < 0) {
 345                 dev_err(dev, "failed to create crtc\n");
 346                 goto init_failed;
 347         }
 348         modeset_init(ddev);
 349
 350 #ifdef CONFIG_CPU_FREQ
 351         priv->freq_transition.notifier_call = cpufreq_transition;
 352         ret = cpufreq_register_notifier(&priv->freq_transition,
 353                         CPUFREQ_TRANSITION_NOTIFIER);
 354         if (ret) {
 355                 dev_err(dev, "failed to register cpufreq notifier\n");
 356                 priv->freq_transition.notifier_call = NULL;
 357                 goto init_failed;
 358         }
 359 #endif
 360
 361         if (priv->is_componentized) {
 362                 ret = component_bind_all(dev, ddev);
 363                 if (ret < 0)
 364                         goto init_failed;
 365
 366                 ret = tilcdc_add_component_encoder(ddev);
 367                 if (ret < 0)
 368                         goto init_failed;
 369         } else {
 370                 ret = tilcdc_attach_external_device(ddev);
 371                 if (ret)
 372                         goto init_failed;
 373         }
 374
 375         if (!priv->external_connector &&
 376             ((priv->num_encoders == 0) || (priv->num_connectors == 0))) {
 377                 dev_err(dev, "no encoders/connectors found\n");
 378                 ret = -EPROBE_DEFER;
 379                 goto init_failed;
 380         }
 381
 382         ret = drm_vblank_init(ddev, 1);
 383         if (ret < 0) {
 384                 dev_err(dev, "failed to initialize vblank\n");
 385                 goto init_failed;
 386         }
 387
 388         ret = drm_irq_install(ddev, platform_get_irq(pdev, 0));
 389         if (ret < 0) {
 390                 dev_err(dev, "failed to install IRQ handler\n");
 391                 goto init_failed;
 392         }
 393
 394         drm_mode_config_reset(ddev);
 395
 396         drm_kms_helper_poll_init(ddev);
 397
 398         ret = drm_dev_register(ddev, 0);
 399         if (ret)
 400                 goto init_failed;
 401
 402         drm_fbdev_generic_setup(ddev, bpp);
 403
 404         priv->is_registered = true;
 405         return 0;
 406
 407 init_failed:
 408         tilcdc_fini(ddev);
 409
 410         return ret;
 411 }
 412
 413 static irqreturn_t tilcdc_irq(int irq, void *arg)
 414 {
 415         struct drm_device *dev = arg;
 416         struct tilcdc_drm_private *priv = dev->dev_private;
 417         return tilcdc_crtc_irq(priv->crtc);
 418 }
 419
 420 #if defined(CONFIG_DEBUG_FS)
 421 static const struct {
 422         const char *name;
 423         uint8_t  rev;
 424         uint8_t  save;
 425         uint32_t reg;
 426 } registers[] =         {
 427 #define REG(rev, save, reg) { #reg, rev, save, reg }
 428                 /* exists in revision 1: */
 429                 REG(1, false, LCDC_PID_REG),
 430                 REG(1, true,  LCDC_CTRL_REG),
 431                 REG(1, false, LCDC_STAT_REG),
 432                 REG(1, true,  LCDC_RASTER_CTRL_REG),
 433                 REG(1, true,  LCDC_RASTER_TIMING_0_REG),
 434                 REG(1, true,  LCDC_RASTER_TIMING_1_REG),
 435                 REG(1, true,  LCDC_RASTER_TIMING_2_REG),
 436                 REG(1, true,  LCDC_DMA_CTRL_REG),
 437                 REG(1, true,  LCDC_DMA_FB_BASE_ADDR_0_REG),
 438                 REG(1, true,  LCDC_DMA_FB_CEILING_ADDR_0_REG),
 439                 REG(1, true,  LCDC_DMA_FB_BASE_ADDR_1_REG),
 440                 REG(1, true,  LCDC_DMA_FB_CEILING_ADDR_1_REG),
 441                 /* new in revision 2: */
 442                 REG(2, false, LCDC_RAW_STAT_REG),
 443                 REG(2, false, LCDC_MASKED_STAT_REG),
 444                 REG(2, true, LCDC_INT_ENABLE_SET_REG),
 445                 REG(2, false, LCDC_INT_ENABLE_CLR_REG),
 446                 REG(2, false, LCDC_END_OF_INT_IND_REG),
 447                 REG(2, true,  LCDC_CLK_ENABLE_REG),
 448 #undef REG
 449 };
 450
 451 #endif
 452
 453 #ifdef CONFIG_DEBUG_FS
 454 static int tilcdc_regs_show(struct seq_file *m, void *arg)
 455 {
 456         struct drm_info_node *node = (struct drm_info_node *) m->private;
 457         struct drm_device *dev = node->minor->dev;
 458         struct tilcdc_drm_private *priv = dev->dev_private;
 459         unsigned i;
 460
 461         pm_runtime_get_sync(dev->dev);
 462
 463         seq_printf(m, "revision: %d\n", priv->rev);
 464
 465         for (i = 0; i < ARRAY_SIZE(registers); i++)
 466                 if (priv->rev >= registers[i].rev)
 467                         seq_printf(m, "%s:\t %08x\n", registers[i].name,
 468                                         tilcdc_read(dev, registers[i].reg));
 469
 470         pm_runtime_put_sync(dev->dev);
 471
 472         return 0;
 473 }
 474
 475 static int tilcdc_mm_show(struct seq_file *m, void *arg)
 476 {
 477         struct drm_info_node *node = (struct drm_info_node *) m->private;
 478         struct drm_device *dev = node->minor->dev;
 479         struct drm_printer p = drm_seq_file_printer(m);
 480         drm_mm_print(&dev->vma_offset_manager->vm_addr_space_mm, &p);
 481         return 0;
 482 }
 483
 484 static struct drm_info_list tilcdc_debugfs_list[] = {
 485                 { "regs", tilcdc_regs_show, 0 },
 486                 { "mm",   tilcdc_mm_show,   0 },
 487 };
 488
 489 static int tilcdc_debugfs_init(struct drm_minor *minor)
 490 {
 491         struct drm_device *dev = minor->dev;
 492         struct tilcdc_module *mod;
 493         int ret;
 494
 495         ret = drm_debugfs_create_files(tilcdc_debugfs_list,
 496                         ARRAY_SIZE(tilcdc_debugfs_list),
 497                         minor->debugfs_root, minor);
 498
 499         list_for_each_entry(mod, &module_list, list)
 500                 if (mod->funcs->debugfs_init)
 501                         mod->funcs->debugfs_init(mod, minor);
 502
 503         if (ret) {
 504                 dev_err(dev->dev, "could not install tilcdc_debugfs_list\n");
 505                 return ret;
 506         }
 507
 508         return ret;
 509 }
 510 #endif
 511
 512 DEFINE_DRM_GEM_CMA_FOPS(fops);
 513
 514 static struct drm_driver tilcdc_driver = {
 515         .driver_features    = (DRIVER_GEM | DRIVER_MODESET |
 516                                DRIVER_PRIME | DRIVER_ATOMIC),
 517         .irq_handler        = tilcdc_irq,
 518         .gem_free_object_unlocked = drm_gem_cma_free_object,
 519         .gem_print_info     = drm_gem_cma_print_info,
 520         .gem_vm_ops         = &drm_gem_cma_vm_ops,
 521         .dumb_create        = drm_gem_cma_dumb_create,
 522
 523         .prime_handle_to_fd     = drm_gem_prime_handle_to_fd,
 524         .prime_fd_to_handle     = drm_gem_prime_fd_to_handle,
 525         .gem_prime_import       = drm_gem_prime_import,
 526         .gem_prime_export       = drm_gem_prime_export,
 527         .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
 528         .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
 529         .gem_prime_vmap         = drm_gem_cma_prime_vmap,
 530         .gem_prime_vunmap       = drm_gem_cma_prime_vunmap,
 531         .gem_prime_mmap         = drm_gem_cma_prime_mmap,
 532 #ifdef CONFIG_DEBUG_FS
 533         .debugfs_init       = tilcdc_debugfs_init,
 534 #endif
 535         .fops               = &fops,
 536         .name               = "tilcdc",
 537         .desc               = "TI LCD Controller DRM",
 538         .date               = "20121205",
 539         .major              = 1,
 540         .minor              = 0,
 541 };
 542
 543 /*
 544  * Power management:
 545  */
 546
 547 #ifdef CONFIG_PM_SLEEP
 548 static int tilcdc_pm_suspend(struct device *dev)
 549 {
 550         struct drm_device *ddev = dev_get_drvdata(dev);
 551         int ret = 0;
 552
 553         ret = drm_mode_config_helper_suspend(ddev);
 554
 555         /* Select sleep pin state */
 556         pinctrl_pm_select_sleep_state(dev);
 557
 558         return ret;
 559 }
 560
 561 static int tilcdc_pm_resume(struct device *dev)
 562 {
 563         struct drm_device *ddev = dev_get_drvdata(dev);
 564
 565         /* Select default pin state */
 566         pinctrl_pm_select_default_state(dev);
 567         return  drm_mode_config_helper_resume(ddev);
 568 }
 569 #endif
 570
 571 static const struct dev_pm_ops tilcdc_pm_ops = {
 572         SET_SYSTEM_SLEEP_PM_OPS(tilcdc_pm_suspend, tilcdc_pm_resume)
 573 };
 574
 575 /*
 576  * Platform driver:
 577  */
 578 static int tilcdc_bind(struct device *dev)
 579 {
 580         return tilcdc_init(&tilcdc_driver, dev);
 581 }
 582
 583 static void tilcdc_unbind(struct device *dev)
 584 {
 585         struct drm_device *ddev = dev_get_drvdata(dev);
 586
 587         /* Check if a subcomponent has already triggered the unloading. */
 588         if (!ddev->dev_private)
 589                 return;
 590
 591         tilcdc_fini(dev_get_drvdata(dev));
 592 }
 593
 594 static const struct component_master_ops tilcdc_comp_ops = {
 595         .bind = tilcdc_bind,
 596         .unbind = tilcdc_unbind,
 597 };
 598
 599 static int tilcdc_pdev_probe(struct platform_device *pdev)
 600 {
 601         struct component_match *match = NULL;
 602         int ret;
 603
 604         /* bail out early if no DT data: */
 605         if (!pdev->dev.of_node) {
 606                 dev_err(&pdev->dev, "device-tree data is missing\n");
 607                 return -ENXIO;
 608         }
 609
 610         ret = tilcdc_get_external_components(&pdev->dev, &match);
 611         if (ret < 0)
 612                 return ret;
 613         else if (ret == 0)
 614                 return tilcdc_init(&tilcdc_driver, &pdev->dev);
 615         else
 616                 return component_master_add_with_match(&pdev->dev,
 617                                                        &tilcdc_comp_ops,
 618                                                        match);
 619 }
 620
 621 static int tilcdc_pdev_remove(struct platform_device *pdev)
 622 {
 623         int ret;
 624
 625         ret = tilcdc_get_external_components(&pdev->dev, NULL);
 626         if (ret < 0)
 627                 return ret;
 628         else if (ret == 0)
 629                 tilcdc_fini(platform_get_drvdata(pdev));
 630         else
 631                 component_master_del(&pdev->dev, &tilcdc_comp_ops);
 632
 633         return 0;
 634 }
 635
 636 static struct of_device_id tilcdc_of_match[] = {
 637                 { .compatible = "ti,am33xx-tilcdc", },
 638                 { .compatible = "ti,da850-tilcdc", },
 639                 { },
 640 };
 641 MODULE_DEVICE_TABLE(of, tilcdc_of_match);
 642
 643 static struct platform_driver tilcdc_platform_driver = {
 644         .probe      = tilcdc_pdev_probe,
 645         .remove     = tilcdc_pdev_remove,
 646         .driver     = {
 647                 .name   = "tilcdc",
 648                 .pm     = &tilcdc_pm_ops,
 649                 .of_match_table = tilcdc_of_match,
 650         },
 651 };
 652
 653 static int __init tilcdc_drm_init(void)
 654 {
 655         DBG("init");
 656         tilcdc_tfp410_init();
 657         tilcdc_panel_init();
 658         return platform_driver_register(&tilcdc_platform_driver);
 659 }
 660
 661 static void __exit tilcdc_drm_fini(void)
 662 {
 663         DBG("fini");
 664         platform_driver_unregister(&tilcdc_platform_driver);
 665         tilcdc_panel_fini();
 666         tilcdc_tfp410_fini();
 667 }
 668
 669 module_init(tilcdc_drm_init);
 670 module_exit(tilcdc_drm_fini);
 671
 672 MODULE_AUTHOR("Rob Clark <[email protected]");
 673 MODULE_DESCRIPTION("TI LCD Controller DRM Driver");
 674 MODULE_LICENSE("GPL");