drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26
  27 #include <linux/firmware.h>
  28 #include <linux/module.h>
  29 #include <linux/dmi.h>
  30 #include <linux/pci.h>
  31 #include <linux/debugfs.h>
  32 #include <drm/drm_drv.h>
  33
  34 #include "amdgpu.h"
  35 #include "amdgpu_pm.h"
  36 #include "amdgpu_vcn.h"
  37 #include "soc15d.h"
  38
  39 /* Firmware Names */
  40 #define FIRMWARE_RAVEN                  "amdgpu/raven_vcn.bin"
  41 #define FIRMWARE_PICASSO                "amdgpu/picasso_vcn.bin"
  42 #define FIRMWARE_RAVEN2                 "amdgpu/raven2_vcn.bin"
  43 #define FIRMWARE_ARCTURUS               "amdgpu/arcturus_vcn.bin"
  44 #define FIRMWARE_RENOIR                 "amdgpu/renoir_vcn.bin"
  45 #define FIRMWARE_GREEN_SARDINE          "amdgpu/green_sardine_vcn.bin"
  46 #define FIRMWARE_NAVI10                 "amdgpu/navi10_vcn.bin"
  47 #define FIRMWARE_NAVI14                 "amdgpu/navi14_vcn.bin"
  48 #define FIRMWARE_NAVI12                 "amdgpu/navi12_vcn.bin"
  49 #define FIRMWARE_SIENNA_CICHLID         "amdgpu/sienna_cichlid_vcn.bin"
  50 #define FIRMWARE_NAVY_FLOUNDER          "amdgpu/navy_flounder_vcn.bin"
  51 #define FIRMWARE_VANGOGH                "amdgpu/vangogh_vcn.bin"
  52 #define FIRMWARE_DIMGREY_CAVEFISH       "amdgpu/dimgrey_cavefish_vcn.bin"
  53 #define FIRMWARE_ALDEBARAN              "amdgpu/aldebaran_vcn.bin"
  54 #define FIRMWARE_BEIGE_GOBY             "amdgpu/beige_goby_vcn.bin"
  55 #define FIRMWARE_YELLOW_CARP            "amdgpu/yellow_carp_vcn.bin"
  56 #define FIRMWARE_VCN_3_1_2              "amdgpu/vcn_3_1_2.bin"
  57 #define FIRMWARE_VCN4_0_0               "amdgpu/vcn_4_0_0.bin"
  58 #define FIRMWARE_VCN4_0_2               "amdgpu/vcn_4_0_2.bin"
  59 #define FIRMWARE_VCN4_0_3               "amdgpu/vcn_4_0_3.bin"
  60 #define FIRMWARE_VCN4_0_4               "amdgpu/vcn_4_0_4.bin"
  61 #define FIRMWARE_VCN4_0_5               "amdgpu/vcn_4_0_5.bin"
  62
  63 MODULE_FIRMWARE(FIRMWARE_RAVEN);
  64 MODULE_FIRMWARE(FIRMWARE_PICASSO);
  65 MODULE_FIRMWARE(FIRMWARE_RAVEN2);
  66 MODULE_FIRMWARE(FIRMWARE_ARCTURUS);
  67 MODULE_FIRMWARE(FIRMWARE_RENOIR);
  68 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE);
  69 MODULE_FIRMWARE(FIRMWARE_ALDEBARAN);
  70 MODULE_FIRMWARE(FIRMWARE_NAVI10);
  71 MODULE_FIRMWARE(FIRMWARE_NAVI14);
  72 MODULE_FIRMWARE(FIRMWARE_NAVI12);
  73 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID);
  74 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER);
  75 MODULE_FIRMWARE(FIRMWARE_VANGOGH);
  76 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH);
  77 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY);
  78 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP);
  79 MODULE_FIRMWARE(FIRMWARE_VCN_3_1_2);
  80 MODULE_FIRMWARE(FIRMWARE_VCN4_0_0);
  81 MODULE_FIRMWARE(FIRMWARE_VCN4_0_2);
  82 MODULE_FIRMWARE(FIRMWARE_VCN4_0_3);
  83 MODULE_FIRMWARE(FIRMWARE_VCN4_0_4);
  84 MODULE_FIRMWARE(FIRMWARE_VCN4_0_5);
  85
  86 static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
  87
  88 int amdgpu_vcn_early_init(struct amdgpu_device *adev)
  89 {
  90         char ucode_prefix[30];
  91         char fw_name[40];
  92         int r;
  93
  94         amdgpu_ucode_ip_version_decode(adev, UVD_HWIP, ucode_prefix, sizeof(ucode_prefix));
  95         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix);
  96         r = amdgpu_ucode_request(adev, &adev->vcn.fw, fw_name);
  97         if (r)
  98                 amdgpu_ucode_release(&adev->vcn.fw);
  99
 100         return r;
 101 }
 102
 103 int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
 104 {
 105         unsigned long bo_size;
 106         const struct common_firmware_header *hdr;
 107         unsigned char fw_check;
 108         unsigned int fw_shared_size, log_offset;
 109         int i, r;
 110
 111         INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
 112         mutex_init(&adev->vcn.vcn_pg_lock);
 113         mutex_init(&adev->vcn.vcn1_jpeg1_workaround);
 114         atomic_set(&adev->vcn.total_submission_cnt, 0);
 115         for (i = 0; i < adev->vcn.num_vcn_inst; i++)
 116                 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0);
 117
 118         if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
 119             (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
 120                 adev->vcn.indirect_sram = true;
 121
 122         /*
 123          * Some Steam Deck's BIOS versions are incompatible with the
 124          * indirect SRAM mode, leading to amdgpu being unable to get
 125          * properly probed (and even potentially crashing the kernel).
 126          * Hence, check for these versions here - notice this is
 127          * restricted to Vangogh (Deck's APU).
 128          */
 129         if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(3, 0, 2)) {
 130                 const char *bios_ver = dmi_get_system_info(DMI_BIOS_VERSION);
 131
 132                 if (bios_ver && (!strncmp("F7A0113", bios_ver, 7) ||
 133                      !strncmp("F7A0114", bios_ver, 7))) {
 134                         adev->vcn.indirect_sram = false;
 135                         dev_info(adev->dev,
 136                                 "Steam Deck quirk: indirect SRAM disabled on BIOS %s\n", bios_ver);
 137                 }
 138         }
 139
 140         hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
 141         adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version);
 142
 143         /* Bit 20-23, it is encode major and non-zero for new naming convention.
 144          * This field is part of version minor and DRM_DISABLED_FLAG in old naming
 145          * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG
 146          * is zero in old naming convention, this field is always zero so far.
 147          * These four bits are used to tell which naming convention is present.
 148          */
 149         fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf;
 150         if (fw_check) {
 151                 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev;
 152
 153                 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff;
 154                 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff;
 155                 enc_major = fw_check;
 156                 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf;
 157                 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf;
 158                 DRM_INFO("Found VCN firmware Version ENC: %u.%u DEC: %u VEP: %u Revision: %u\n",
 159                         enc_major, enc_minor, dec_ver, vep, fw_rev);
 160         } else {
 161                 unsigned int version_major, version_minor, family_id;
 162
 163                 family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
 164                 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
 165                 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
 166                 DRM_INFO("Found VCN firmware Version: %u.%u Family ID: %u\n",
 167                         version_major, version_minor, family_id);
 168         }
 169
 170         bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE;
 171         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 172                 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
 173
 174         if (amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(4, 0, 0)) {
 175                 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared));
 176                 log_offset = offsetof(struct amdgpu_vcn4_fw_shared, fw_log);
 177         } else {
 178                 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared));
 179                 log_offset = offsetof(struct amdgpu_fw_shared, fw_log);
 180         }
 181
 182         bo_size += fw_shared_size;
 183
 184         if (amdgpu_vcnfw_log)
 185                 bo_size += AMDGPU_VCNFW_LOG_SIZE;
 186
 187         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 188                 if (adev->vcn.harvest_config & (1 << i))
 189                         continue;
 190
 191                 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
 192                                             AMDGPU_GEM_DOMAIN_VRAM |
 193                                             AMDGPU_GEM_DOMAIN_GTT,
 194                                             &adev->vcn.inst[i].vcpu_bo,
 195                                             &adev->vcn.inst[i].gpu_addr,
 196                                             &adev->vcn.inst[i].cpu_addr);
 197                 if (r) {
 198                         dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
 199                         return r;
 200                 }
 201
 202                 adev->vcn.inst[i].fw_shared.cpu_addr = adev->vcn.inst[i].cpu_addr +
 203                                 bo_size - fw_shared_size;
 204                 adev->vcn.inst[i].fw_shared.gpu_addr = adev->vcn.inst[i].gpu_addr +
 205                                 bo_size - fw_shared_size;
 206
 207                 adev->vcn.inst[i].fw_shared.mem_size = fw_shared_size;
 208
 209                 if (amdgpu_vcnfw_log) {
 210                         adev->vcn.inst[i].fw_shared.cpu_addr -= AMDGPU_VCNFW_LOG_SIZE;
 211                         adev->vcn.inst[i].fw_shared.gpu_addr -= AMDGPU_VCNFW_LOG_SIZE;
 212                         adev->vcn.inst[i].fw_shared.log_offset = log_offset;
 213                 }
 214
 215                 if (adev->vcn.indirect_sram) {
 216                         r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE,
 217                                         AMDGPU_GEM_DOMAIN_VRAM |
 218                                         AMDGPU_GEM_DOMAIN_GTT,
 219                                         &adev->vcn.inst[i].dpg_sram_bo,
 220                                         &adev->vcn.inst[i].dpg_sram_gpu_addr,
 221                                         &adev->vcn.inst[i].dpg_sram_cpu_addr);
 222                         if (r) {
 223                                 dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r);
 224                                 return r;
 225                         }
 226                 }
 227         }
 228
 229         return 0;
 230 }
 231
 232 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
 233 {
 234         int i, j;
 235
 236         for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
 237                 if (adev->vcn.harvest_config & (1 << j))
 238                         continue;
 239
 240                 amdgpu_bo_free_kernel(
 241                         &adev->vcn.inst[j].dpg_sram_bo,
 242                         &adev->vcn.inst[j].dpg_sram_gpu_addr,
 243                         (void **)&adev->vcn.inst[j].dpg_sram_cpu_addr);
 244
 245                 kvfree(adev->vcn.inst[j].saved_bo);
 246
 247                 amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo,
 248                                           &adev->vcn.inst[j].gpu_addr,
 249                                           (void **)&adev->vcn.inst[j].cpu_addr);
 250
 251                 amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec);
 252
 253                 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
 254                         amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]);
 255         }
 256
 257         amdgpu_ucode_release(&adev->vcn.fw);
 258         mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround);
 259         mutex_destroy(&adev->vcn.vcn_pg_lock);
 260
 261         return 0;
 262 }
 263
 264 /* from vcn4 and above, only unified queue is used */
 265 static bool amdgpu_vcn_using_unified_queue(struct amdgpu_ring *ring)
 266 {
 267         struct amdgpu_device *adev = ring->adev;
 268         bool ret = false;
 269
 270         if (amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(4, 0, 0))
 271                 ret = true;
 272
 273         return ret;
 274 }
 275
 276 bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance)
 277 {
 278         bool ret = false;
 279         int vcn_config = adev->vcn.vcn_config[vcn_instance];
 280
 281         if ((type == VCN_ENCODE_RING) && (vcn_config & VCN_BLOCK_ENCODE_DISABLE_MASK))
 282                 ret = true;
 283         else if ((type == VCN_DECODE_RING) && (vcn_config & VCN_BLOCK_DECODE_DISABLE_MASK))
 284                 ret = true;
 285         else if ((type == VCN_UNIFIED_RING) && (vcn_config & VCN_BLOCK_QUEUE_DISABLE_MASK))
 286                 ret = true;
 287
 288         return ret;
 289 }
 290
 291 int amdgpu_vcn_suspend(struct amdgpu_device *adev)
 292 {
 293         unsigned int size;
 294         void *ptr;
 295         int i, idx;
 296
 297         cancel_delayed_work_sync(&adev->vcn.idle_work);
 298
 299         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 300                 if (adev->vcn.harvest_config & (1 << i))
 301                         continue;
 302                 if (adev->vcn.inst[i].vcpu_bo == NULL)
 303                         return 0;
 304
 305                 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
 306                 ptr = adev->vcn.inst[i].cpu_addr;
 307
 308                 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL);
 309                 if (!adev->vcn.inst[i].saved_bo)
 310                         return -ENOMEM;
 311
 312                 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
 313                         memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size);
 314                         drm_dev_exit(idx);
 315                 }
 316         }
 317         return 0;
 318 }
 319
 320 int amdgpu_vcn_resume(struct amdgpu_device *adev)
 321 {
 322         unsigned int size;
 323         void *ptr;
 324         int i, idx;
 325
 326         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 327                 if (adev->vcn.harvest_config & (1 << i))
 328                         continue;
 329                 if (adev->vcn.inst[i].vcpu_bo == NULL)
 330                         return -EINVAL;
 331
 332                 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
 333                 ptr = adev->vcn.inst[i].cpu_addr;
 334
 335                 if (adev->vcn.inst[i].saved_bo != NULL) {
 336                         if (drm_dev_enter(adev_to_drm(adev), &idx)) {
 337                                 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size);
 338                                 drm_dev_exit(idx);
 339                         }
 340                         kvfree(adev->vcn.inst[i].saved_bo);
 341                         adev->vcn.inst[i].saved_bo = NULL;
 342                 } else {
 343                         const struct common_firmware_header *hdr;
 344                         unsigned int offset;
 345
 346                         hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
 347                         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 348                                 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
 349                                 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
 350                                         memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset,
 351                                                     le32_to_cpu(hdr->ucode_size_bytes));
 352                                         drm_dev_exit(idx);
 353                                 }
 354                                 size -= le32_to_cpu(hdr->ucode_size_bytes);
 355                                 ptr += le32_to_cpu(hdr->ucode_size_bytes);
 356                         }
 357                         memset_io(ptr, 0, size);
 358                 }
 359         }
 360         return 0;
 361 }
 362
 363 static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
 364 {
 365         struct amdgpu_device *adev =
 366                 container_of(work, struct amdgpu_device, vcn.idle_work.work);
 367         unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0};
 368         unsigned int i, j;
 369         int r = 0;
 370
 371         for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
 372                 if (adev->vcn.harvest_config & (1 << j))
 373                         continue;
 374
 375                 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
 376                         fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]);
 377
 378                 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)    {
 379                         struct dpg_pause_state new_state;
 380
 381                         if (fence[j] ||
 382                                 unlikely(atomic_read(&adev->vcn.inst[j].dpg_enc_submission_cnt)))
 383                                 new_state.fw_based = VCN_DPG_STATE__PAUSE;
 384                         else
 385                                 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
 386
 387                         adev->vcn.pause_dpg_mode(adev, j, &new_state);
 388                 }
 389
 390                 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec);
 391                 fences += fence[j];
 392         }
 393
 394         if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) {
 395                 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
 396                        AMD_PG_STATE_GATE);
 397                 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
 398                                 false);
 399                 if (r)
 400                         dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r);
 401         } else {
 402                 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
 403         }
 404 }
 405
 406 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
 407 {
 408         struct amdgpu_device *adev = ring->adev;
 409         int r = 0;
 410
 411         atomic_inc(&adev->vcn.total_submission_cnt);
 412
 413         if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) {
 414                 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
 415                                 true);
 416                 if (r)
 417                         dev_warn(adev->dev, "(%d) failed to switch to video power profile mode\n", r);
 418         }
 419
 420         mutex_lock(&adev->vcn.vcn_pg_lock);
 421         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
 422                AMD_PG_STATE_UNGATE);
 423
 424         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)    {
 425                 struct dpg_pause_state new_state;
 426
 427                 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) {
 428                         atomic_inc(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt);
 429                         new_state.fw_based = VCN_DPG_STATE__PAUSE;
 430                 } else {
 431                         unsigned int fences = 0;
 432                         unsigned int i;
 433
 434                         for (i = 0; i < adev->vcn.num_enc_rings; ++i)
 435                                 fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]);
 436
 437                         if (fences || atomic_read(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt))
 438                                 new_state.fw_based = VCN_DPG_STATE__PAUSE;
 439                         else
 440                                 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
 441                 }
 442
 443                 adev->vcn.pause_dpg_mode(adev, ring->me, &new_state);
 444         }
 445         mutex_unlock(&adev->vcn.vcn_pg_lock);
 446 }
 447
 448 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring)
 449 {
 450         if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG &&
 451                 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC)
 452                 atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt);
 453
 454         atomic_dec(&ring->adev->vcn.total_submission_cnt);
 455
 456         schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
 457 }
 458
 459 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
 460 {
 461         struct amdgpu_device *adev = ring->adev;
 462         uint32_t tmp = 0;
 463         unsigned int i;
 464         int r;
 465
 466         /* VCN in SRIOV does not support direct register read/write */
 467         if (amdgpu_sriov_vf(adev))
 468                 return 0;
 469
 470         WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
 471         r = amdgpu_ring_alloc(ring, 3);
 472         if (r)
 473                 return r;
 474         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));
 475         amdgpu_ring_write(ring, 0xDEADBEEF);
 476         amdgpu_ring_commit(ring);
 477         for (i = 0; i < adev->usec_timeout; i++) {
 478                 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
 479                 if (tmp == 0xDEADBEEF)
 480                         break;
 481                 udelay(1);
 482         }
 483
 484         if (i >= adev->usec_timeout)
 485                 r = -ETIMEDOUT;
 486
 487         return r;
 488 }
 489
 490 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring)
 491 {
 492         struct amdgpu_device *adev = ring->adev;
 493         uint32_t rptr;
 494         unsigned int i;
 495         int r;
 496
 497         if (amdgpu_sriov_vf(adev))
 498                 return 0;
 499
 500         r = amdgpu_ring_alloc(ring, 16);
 501         if (r)
 502                 return r;
 503
 504         rptr = amdgpu_ring_get_rptr(ring);
 505
 506         amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END);
 507         amdgpu_ring_commit(ring);
 508
 509         for (i = 0; i < adev->usec_timeout; i++) {
 510                 if (amdgpu_ring_get_rptr(ring) != rptr)
 511                         break;
 512                 udelay(1);
 513         }
 514
 515         if (i >= adev->usec_timeout)
 516                 r = -ETIMEDOUT;
 517
 518         return r;
 519 }
 520
 521 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
 522                                    struct amdgpu_ib *ib_msg,
 523                                    struct dma_fence **fence)
 524 {
 525         u64 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
 526         struct amdgpu_device *adev = ring->adev;
 527         struct dma_fence *f = NULL;
 528         struct amdgpu_job *job;
 529         struct amdgpu_ib *ib;
 530         int i, r;
 531
 532         r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
 533                                      64, AMDGPU_IB_POOL_DIRECT,
 534                                      &job);
 535         if (r)
 536                 goto err;
 537
 538         ib = &job->ibs[0];
 539         ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0);
 540         ib->ptr[1] = addr;
 541         ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0);
 542         ib->ptr[3] = addr >> 32;
 543         ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0);
 544         ib->ptr[5] = 0;
 545         for (i = 6; i < 16; i += 2) {
 546                 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0);
 547                 ib->ptr[i+1] = 0;
 548         }
 549         ib->length_dw = 16;
 550
 551         r = amdgpu_job_submit_direct(job, ring, &f);
 552         if (r)
 553                 goto err_free;
 554
 555         amdgpu_ib_free(adev, ib_msg, f);
 556
 557         if (fence)
 558                 *fence = dma_fence_get(f);
 559         dma_fence_put(f);
 560
 561         return 0;
 562
 563 err_free:
 564         amdgpu_job_free(job);
 565 err:
 566         amdgpu_ib_free(adev, ib_msg, f);
 567         return r;
 568 }
 569
 570 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 571                 struct amdgpu_ib *ib)
 572 {
 573         struct amdgpu_device *adev = ring->adev;
 574         uint32_t *msg;
 575         int r, i;
 576
 577         memset(ib, 0, sizeof(*ib));
 578         r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2,
 579                         AMDGPU_IB_POOL_DIRECT,
 580                         ib);
 581         if (r)
 582                 return r;
 583
 584         msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr);
 585         msg[0] = cpu_to_le32(0x00000028);
 586         msg[1] = cpu_to_le32(0x00000038);
 587         msg[2] = cpu_to_le32(0x00000001);
 588         msg[3] = cpu_to_le32(0x00000000);
 589         msg[4] = cpu_to_le32(handle);
 590         msg[5] = cpu_to_le32(0x00000000);
 591         msg[6] = cpu_to_le32(0x00000001);
 592         msg[7] = cpu_to_le32(0x00000028);
 593         msg[8] = cpu_to_le32(0x00000010);
 594         msg[9] = cpu_to_le32(0x00000000);
 595         msg[10] = cpu_to_le32(0x00000007);
 596         msg[11] = cpu_to_le32(0x00000000);
 597         msg[12] = cpu_to_le32(0x00000780);
 598         msg[13] = cpu_to_le32(0x00000440);
 599         for (i = 14; i < 1024; ++i)
 600                 msg[i] = cpu_to_le32(0x0);
 601
 602         return 0;
 603 }
 604
 605 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 606                                           struct amdgpu_ib *ib)
 607 {
 608         struct amdgpu_device *adev = ring->adev;
 609         uint32_t *msg;
 610         int r, i;
 611
 612         memset(ib, 0, sizeof(*ib));
 613         r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2,
 614                         AMDGPU_IB_POOL_DIRECT,
 615                         ib);
 616         if (r)
 617                 return r;
 618
 619         msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr);
 620         msg[0] = cpu_to_le32(0x00000028);
 621         msg[1] = cpu_to_le32(0x00000018);
 622         msg[2] = cpu_to_le32(0x00000000);
 623         msg[3] = cpu_to_le32(0x00000002);
 624         msg[4] = cpu_to_le32(handle);
 625         msg[5] = cpu_to_le32(0x00000000);
 626         for (i = 6; i < 1024; ++i)
 627                 msg[i] = cpu_to_le32(0x0);
 628
 629         return 0;
 630 }
 631
 632 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 633 {
 634         struct dma_fence *fence = NULL;
 635         struct amdgpu_ib ib;
 636         long r;
 637
 638         r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib);
 639         if (r)
 640                 goto error;
 641
 642         r = amdgpu_vcn_dec_send_msg(ring, &ib, NULL);
 643         if (r)
 644                 goto error;
 645         r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib);
 646         if (r)
 647                 goto error;
 648
 649         r = amdgpu_vcn_dec_send_msg(ring, &ib, &fence);
 650         if (r)
 651                 goto error;
 652
 653         r = dma_fence_wait_timeout(fence, false, timeout);
 654         if (r == 0)
 655                 r = -ETIMEDOUT;
 656         else if (r > 0)
 657                 r = 0;
 658
 659         dma_fence_put(fence);
 660 error:
 661         return r;
 662 }
 663
 664 static uint32_t *amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib *ib,
 665                                                 uint32_t ib_pack_in_dw, bool enc)
 666 {
 667         uint32_t *ib_checksum;
 668
 669         ib->ptr[ib->length_dw++] = 0x00000010; /* single queue checksum */
 670         ib->ptr[ib->length_dw++] = 0x30000002;
 671         ib_checksum = &ib->ptr[ib->length_dw++];
 672         ib->ptr[ib->length_dw++] = ib_pack_in_dw;
 673
 674         ib->ptr[ib->length_dw++] = 0x00000010; /* engine info */
 675         ib->ptr[ib->length_dw++] = 0x30000001;
 676         ib->ptr[ib->length_dw++] = enc ? 0x2 : 0x3;
 677         ib->ptr[ib->length_dw++] = ib_pack_in_dw * sizeof(uint32_t);
 678
 679         return ib_checksum;
 680 }
 681
 682 static void amdgpu_vcn_unified_ring_ib_checksum(uint32_t **ib_checksum,
 683                                                 uint32_t ib_pack_in_dw)
 684 {
 685         uint32_t i;
 686         uint32_t checksum = 0;
 687
 688         for (i = 0; i < ib_pack_in_dw; i++)
 689                 checksum += *(*ib_checksum + 2 + i);
 690
 691         **ib_checksum = checksum;
 692 }
 693
 694 static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,
 695                                       struct amdgpu_ib *ib_msg,
 696                                       struct dma_fence **fence)
 697 {
 698         struct amdgpu_vcn_decode_buffer *decode_buffer = NULL;
 699         unsigned int ib_size_dw = 64;
 700         struct amdgpu_device *adev = ring->adev;
 701         struct dma_fence *f = NULL;
 702         struct amdgpu_job *job;
 703         struct amdgpu_ib *ib;
 704         uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
 705         bool sq = amdgpu_vcn_using_unified_queue(ring);
 706         uint32_t *ib_checksum;
 707         uint32_t ib_pack_in_dw;
 708         int i, r;
 709
 710         if (sq)
 711                 ib_size_dw += 8;
 712
 713         r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
 714                                      ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,
 715                                      &job);
 716         if (r)
 717                 goto err;
 718
 719         ib = &job->ibs[0];
 720         ib->length_dw = 0;
 721
 722         /* single queue headers */
 723         if (sq) {
 724                 ib_pack_in_dw = sizeof(struct amdgpu_vcn_decode_buffer) / sizeof(uint32_t)
 725                                                 + 4 + 2; /* engine info + decoding ib in dw */
 726                 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, ib_pack_in_dw, false);
 727         }
 728
 729         ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8;
 730         ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER);
 731         decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]);
 732         ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4;
 733         memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer));
 734
 735         decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER);
 736         decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32);
 737         decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr);
 738
 739         for (i = ib->length_dw; i < ib_size_dw; ++i)
 740                 ib->ptr[i] = 0x0;
 741
 742         if (sq)
 743                 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, ib_pack_in_dw);
 744
 745         r = amdgpu_job_submit_direct(job, ring, &f);
 746         if (r)
 747                 goto err_free;
 748
 749         amdgpu_ib_free(adev, ib_msg, f);
 750
 751         if (fence)
 752                 *fence = dma_fence_get(f);
 753         dma_fence_put(f);
 754
 755         return 0;
 756
 757 err_free:
 758         amdgpu_job_free(job);
 759 err:
 760         amdgpu_ib_free(adev, ib_msg, f);
 761         return r;
 762 }
 763
 764 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 765 {
 766         struct dma_fence *fence = NULL;
 767         struct amdgpu_ib ib;
 768         long r;
 769
 770         r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib);
 771         if (r)
 772                 goto error;
 773
 774         r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, NULL);
 775         if (r)
 776                 goto error;
 777         r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib);
 778         if (r)
 779                 goto error;
 780
 781         r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, &fence);
 782         if (r)
 783                 goto error;
 784
 785         r = dma_fence_wait_timeout(fence, false, timeout);
 786         if (r == 0)
 787                 r = -ETIMEDOUT;
 788         else if (r > 0)
 789                 r = 0;
 790
 791         dma_fence_put(fence);
 792 error:
 793         return r;
 794 }
 795
 796 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring)
 797 {
 798         struct amdgpu_device *adev = ring->adev;
 799         uint32_t rptr;
 800         unsigned int i;
 801         int r;
 802
 803         if (amdgpu_sriov_vf(adev))
 804                 return 0;
 805
 806         r = amdgpu_ring_alloc(ring, 16);
 807         if (r)
 808                 return r;
 809
 810         rptr = amdgpu_ring_get_rptr(ring);
 811
 812         amdgpu_ring_write(ring, VCN_ENC_CMD_END);
 813         amdgpu_ring_commit(ring);
 814
 815         for (i = 0; i < adev->usec_timeout; i++) {
 816                 if (amdgpu_ring_get_rptr(ring) != rptr)
 817                         break;
 818                 udelay(1);
 819         }
 820
 821         if (i >= adev->usec_timeout)
 822                 r = -ETIMEDOUT;
 823
 824         return r;
 825 }
 826
 827 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 828                                          struct amdgpu_ib *ib_msg,
 829                                          struct dma_fence **fence)
 830 {
 831         unsigned int ib_size_dw = 16;
 832         struct amdgpu_job *job;
 833         struct amdgpu_ib *ib;
 834         struct dma_fence *f = NULL;
 835         uint32_t *ib_checksum = NULL;
 836         uint64_t addr;
 837         bool sq = amdgpu_vcn_using_unified_queue(ring);
 838         int i, r;
 839
 840         if (sq)
 841                 ib_size_dw += 8;
 842
 843         r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
 844                                      ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,
 845                                      &job);
 846         if (r)
 847                 return r;
 848
 849         ib = &job->ibs[0];
 850         addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
 851
 852         ib->length_dw = 0;
 853
 854         if (sq)
 855                 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true);
 856
 857         ib->ptr[ib->length_dw++] = 0x00000018;
 858         ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
 859         ib->ptr[ib->length_dw++] = handle;
 860         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
 861         ib->ptr[ib->length_dw++] = addr;
 862         ib->ptr[ib->length_dw++] = 0x0000000b;
 863
 864         ib->ptr[ib->length_dw++] = 0x00000014;
 865         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 866         ib->ptr[ib->length_dw++] = 0x0000001c;
 867         ib->ptr[ib->length_dw++] = 0x00000000;
 868         ib->ptr[ib->length_dw++] = 0x00000000;
 869
 870         ib->ptr[ib->length_dw++] = 0x00000008;
 871         ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
 872
 873         for (i = ib->length_dw; i < ib_size_dw; ++i)
 874                 ib->ptr[i] = 0x0;
 875
 876         if (sq)
 877                 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11);
 878
 879         r = amdgpu_job_submit_direct(job, ring, &f);
 880         if (r)
 881                 goto err;
 882
 883         if (fence)
 884                 *fence = dma_fence_get(f);
 885         dma_fence_put(f);
 886
 887         return 0;
 888
 889 err:
 890         amdgpu_job_free(job);
 891         return r;
 892 }
 893
 894 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 895                                           struct amdgpu_ib *ib_msg,
 896                                           struct dma_fence **fence)
 897 {
 898         unsigned int ib_size_dw = 16;
 899         struct amdgpu_job *job;
 900         struct amdgpu_ib *ib;
 901         struct dma_fence *f = NULL;
 902         uint32_t *ib_checksum = NULL;
 903         uint64_t addr;
 904         bool sq = amdgpu_vcn_using_unified_queue(ring);
 905         int i, r;
 906
 907         if (sq)
 908                 ib_size_dw += 8;
 909
 910         r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
 911                                      ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,
 912                                      &job);
 913         if (r)
 914                 return r;
 915
 916         ib = &job->ibs[0];
 917         addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
 918
 919         ib->length_dw = 0;
 920
 921         if (sq)
 922                 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true);
 923
 924         ib->ptr[ib->length_dw++] = 0x00000018;
 925         ib->ptr[ib->length_dw++] = 0x00000001;
 926         ib->ptr[ib->length_dw++] = handle;
 927         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
 928         ib->ptr[ib->length_dw++] = addr;
 929         ib->ptr[ib->length_dw++] = 0x0000000b;
 930
 931         ib->ptr[ib->length_dw++] = 0x00000014;
 932         ib->ptr[ib->length_dw++] = 0x00000002;
 933         ib->ptr[ib->length_dw++] = 0x0000001c;
 934         ib->ptr[ib->length_dw++] = 0x00000000;
 935         ib->ptr[ib->length_dw++] = 0x00000000;
 936
 937         ib->ptr[ib->length_dw++] = 0x00000008;
 938         ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
 939
 940         for (i = ib->length_dw; i < ib_size_dw; ++i)
 941                 ib->ptr[i] = 0x0;
 942
 943         if (sq)
 944                 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11);
 945
 946         r = amdgpu_job_submit_direct(job, ring, &f);
 947         if (r)
 948                 goto err;
 949
 950         if (fence)
 951                 *fence = dma_fence_get(f);
 952         dma_fence_put(f);
 953
 954         return 0;
 955
 956 err:
 957         amdgpu_job_free(job);
 958         return r;
 959 }
 960
 961 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 962 {
 963         struct amdgpu_device *adev = ring->adev;
 964         struct dma_fence *fence = NULL;
 965         struct amdgpu_ib ib;
 966         long r;
 967
 968         memset(&ib, 0, sizeof(ib));
 969         r = amdgpu_ib_get(adev, NULL, (128 << 10) + AMDGPU_GPU_PAGE_SIZE,
 970                         AMDGPU_IB_POOL_DIRECT,
 971                         &ib);
 972         if (r)
 973                 return r;
 974
 975         r = amdgpu_vcn_enc_get_create_msg(ring, 1, &ib, NULL);
 976         if (r)
 977                 goto error;
 978
 979         r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &ib, &fence);
 980         if (r)
 981                 goto error;
 982
 983         r = dma_fence_wait_timeout(fence, false, timeout);
 984         if (r == 0)
 985                 r = -ETIMEDOUT;
 986         else if (r > 0)
 987                 r = 0;
 988
 989 error:
 990         amdgpu_ib_free(adev, &ib, fence);
 991         dma_fence_put(fence);
 992
 993         return r;
 994 }
 995
 996 int amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 997 {
 998         struct amdgpu_device *adev = ring->adev;
 999         long r;
1000
1001         if (amdgpu_ip_version(adev, UVD_HWIP, 0) != IP_VERSION(4, 0, 3)) {
1002                 r = amdgpu_vcn_enc_ring_test_ib(ring, timeout);
1003                 if (r)
1004                         goto error;
1005         }
1006
1007         r =  amdgpu_vcn_dec_sw_ring_test_ib(ring, timeout);
1008
1009 error:
1010         return r;
1011 }
1012
1013 enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring)
1014 {
1015         switch (ring) {
1016         case 0:
1017                 return AMDGPU_RING_PRIO_0;
1018         case 1:
1019                 return AMDGPU_RING_PRIO_1;
1020         case 2:
1021                 return AMDGPU_RING_PRIO_2;
1022         default:
1023                 return AMDGPU_RING_PRIO_0;
1024         }
1025 }
1026
1027 void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev)
1028 {
1029         int i;
1030         unsigned int idx;
1031
1032         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1033                 const struct common_firmware_header *hdr;
1034
1035                 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
1036
1037                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1038                         if (adev->vcn.harvest_config & (1 << i))
1039                                 continue;
1040                         /* currently only support 2 FW instances */
1041                         if (i >= 2) {
1042                                 dev_info(adev->dev, "More then 2 VCN FW instances!\n");
1043                                 break;
1044                         }
1045                         idx = AMDGPU_UCODE_ID_VCN + i;
1046                         adev->firmware.ucode[idx].ucode_id = idx;
1047                         adev->firmware.ucode[idx].fw = adev->vcn.fw;
1048                         adev->firmware.fw_size +=
1049                                 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
1050
1051                         if (amdgpu_ip_version(adev, UVD_HWIP, 0) ==
1052                             IP_VERSION(4, 0, 3))
1053                                 break;
1054                 }
1055                 dev_info(adev->dev, "Will use PSP to load VCN firmware\n");
1056         }
1057 }
1058
1059 /*
1060  * debugfs for mapping vcn firmware log buffer.
1061  */
1062 #if defined(CONFIG_DEBUG_FS)
1063 static ssize_t amdgpu_debugfs_vcn_fwlog_read(struct file *f, char __user *buf,
1064                                              size_t size, loff_t *pos)
1065 {
1066         struct amdgpu_vcn_inst *vcn;
1067         void *log_buf;
1068         volatile struct amdgpu_vcn_fwlog *plog;
1069         unsigned int read_pos, write_pos, available, i, read_bytes = 0;
1070         unsigned int read_num[2] = {0};
1071
1072         vcn = file_inode(f)->i_private;
1073         if (!vcn)
1074                 return -ENODEV;
1075
1076         if (!vcn->fw_shared.cpu_addr || !amdgpu_vcnfw_log)
1077                 return -EFAULT;
1078
1079         log_buf = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size;
1080
1081         plog = (volatile struct amdgpu_vcn_fwlog *)log_buf;
1082         read_pos = plog->rptr;
1083         write_pos = plog->wptr;
1084
1085         if (read_pos > AMDGPU_VCNFW_LOG_SIZE || write_pos > AMDGPU_VCNFW_LOG_SIZE)
1086                 return -EFAULT;
1087
1088         if (!size || (read_pos == write_pos))
1089                 return 0;
1090
1091         if (write_pos > read_pos) {
1092                 available = write_pos - read_pos;
1093                 read_num[0] = min_t(size_t, size, available);
1094         } else {
1095                 read_num[0] = AMDGPU_VCNFW_LOG_SIZE - read_pos;
1096                 available = read_num[0] + write_pos - plog->header_size;
1097                 if (size > available)
1098                         read_num[1] = write_pos - plog->header_size;
1099                 else if (size > read_num[0])
1100                         read_num[1] = size - read_num[0];
1101                 else
1102                         read_num[0] = size;
1103         }
1104
1105         for (i = 0; i < 2; i++) {
1106                 if (read_num[i]) {
1107                         if (read_pos == AMDGPU_VCNFW_LOG_SIZE)
1108                                 read_pos = plog->header_size;
1109                         if (read_num[i] == copy_to_user((buf + read_bytes),
1110                                                         (log_buf + read_pos), read_num[i]))
1111                                 return -EFAULT;
1112
1113                         read_bytes += read_num[i];
1114                         read_pos += read_num[i];
1115                 }
1116         }
1117
1118         plog->rptr = read_pos;
1119         *pos += read_bytes;
1120         return read_bytes;
1121 }
1122
1123 static const struct file_operations amdgpu_debugfs_vcnfwlog_fops = {
1124         .owner = THIS_MODULE,
1125         .read = amdgpu_debugfs_vcn_fwlog_read,
1126         .llseek = default_llseek
1127 };
1128 #endif
1129
1130 void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev, uint8_t i,
1131                                    struct amdgpu_vcn_inst *vcn)
1132 {
1133 #if defined(CONFIG_DEBUG_FS)
1134         struct drm_minor *minor = adev_to_drm(adev)->primary;
1135         struct dentry *root = minor->debugfs_root;
1136         char name[32];
1137
1138         sprintf(name, "amdgpu_vcn_%d_fwlog", i);
1139         debugfs_create_file_size(name, S_IFREG | 0444, root, vcn,
1140                                  &amdgpu_debugfs_vcnfwlog_fops,
1141                                  AMDGPU_VCNFW_LOG_SIZE);
1142 #endif
1143 }
1144
1145 void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn)
1146 {
1147 #if defined(CONFIG_DEBUG_FS)
1148         volatile uint32_t *flag = vcn->fw_shared.cpu_addr;
1149         void *fw_log_cpu_addr = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size;
1150         uint64_t fw_log_gpu_addr = vcn->fw_shared.gpu_addr + vcn->fw_shared.mem_size;
1151         volatile struct amdgpu_vcn_fwlog *log_buf = fw_log_cpu_addr;
1152         volatile struct amdgpu_fw_shared_fw_logging *fw_log = vcn->fw_shared.cpu_addr
1153                                                          + vcn->fw_shared.log_offset;
1154         *flag |= cpu_to_le32(AMDGPU_VCN_FW_LOGGING_FLAG);
1155         fw_log->is_enabled = 1;
1156         fw_log->addr_lo = cpu_to_le32(fw_log_gpu_addr & 0xFFFFFFFF);
1157         fw_log->addr_hi = cpu_to_le32(fw_log_gpu_addr >> 32);
1158         fw_log->size = cpu_to_le32(AMDGPU_VCNFW_LOG_SIZE);
1159
1160         log_buf->header_size = sizeof(struct amdgpu_vcn_fwlog);
1161         log_buf->buffer_size = AMDGPU_VCNFW_LOG_SIZE;
1162         log_buf->rptr = log_buf->header_size;
1163         log_buf->wptr = log_buf->header_size;
1164         log_buf->wrapped = 0;
1165 #endif
1166 }
1167
1168 int amdgpu_vcn_process_poison_irq(struct amdgpu_device *adev,
1169                                 struct amdgpu_irq_src *source,
1170                                 struct amdgpu_iv_entry *entry)
1171 {
1172         struct ras_common_if *ras_if = adev->vcn.ras_if;
1173         struct ras_dispatch_if ih_data = {
1174                 .entry = entry,
1175         };
1176
1177         if (!ras_if)
1178                 return 0;
1179
1180         if (!amdgpu_sriov_vf(adev)) {
1181                 ih_data.head = *ras_if;
1182                 amdgpu_ras_interrupt_dispatch(adev, &ih_data);
1183         } else {
1184                 if (adev->virt.ops && adev->virt.ops->ras_poison_handler)
1185                         adev->virt.ops->ras_poison_handler(adev);
1186                 else
1187                         dev_warn(adev->dev,
1188                                 "No ras_poison_handler interface in SRIOV for VCN!\n");
1189         }
1190
1191         return 0;
1192 }
1193
1194 int amdgpu_vcn_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
1195 {
1196         int r, i;
1197
1198         r = amdgpu_ras_block_late_init(adev, ras_block);
1199         if (r)
1200                 return r;
1201
1202         if (amdgpu_ras_is_supported(adev, ras_block->block)) {
1203                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1204                         if (adev->vcn.harvest_config & (1 << i) ||
1205                             !adev->vcn.inst[i].ras_poison_irq.funcs)
1206                                 continue;
1207
1208                         r = amdgpu_irq_get(adev, &adev->vcn.inst[i].ras_poison_irq, 0);
1209                         if (r)
1210                                 goto late_fini;
1211                 }
1212         }
1213         return 0;
1214
1215 late_fini:
1216         amdgpu_ras_block_late_fini(adev, ras_block);
1217         return r;
1218 }
1219
1220 int amdgpu_vcn_ras_sw_init(struct amdgpu_device *adev)
1221 {
1222         int err;
1223         struct amdgpu_vcn_ras *ras;
1224
1225         if (!adev->vcn.ras)
1226                 return 0;
1227
1228         ras = adev->vcn.ras;
1229         err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
1230         if (err) {
1231                 dev_err(adev->dev, "Failed to register vcn ras block!\n");
1232                 return err;
1233         }
1234
1235         strcpy(ras->ras_block.ras_comm.name, "vcn");
1236         ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__VCN;
1237         ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON;
1238         adev->vcn.ras_if = &ras->ras_block.ras_comm;
1239
1240         if (!ras->ras_block.ras_late_init)
1241                 ras->ras_block.ras_late_init = amdgpu_vcn_ras_late_init;
1242
1243         return 0;
1244 }
1245
1246 int amdgpu_vcn_psp_update_sram(struct amdgpu_device *adev, int inst_idx,
1247                                enum AMDGPU_UCODE_ID ucode_id)
1248 {
1249         struct amdgpu_firmware_info ucode = {
1250                 .ucode_id = (ucode_id ? ucode_id :
1251                             (inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
1252                                         AMDGPU_UCODE_ID_VCN0_RAM)),
1253                 .mc_addr = adev->vcn.inst[inst_idx].dpg_sram_gpu_addr,
1254                 .ucode_size = ((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -
1255                               (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr),
1256         };
1257
1258         return psp_execute_ip_fw_load(&adev->psp, &ucode);
1259 }