drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include <drm/drm_drv.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_psp.h"
  31 #include "amdgpu_ucode.h"
  32 #include "amdgpu_xgmi.h"
  33 #include "soc15_common.h"
  34 #include "psp_v3_1.h"
  35 #include "psp_v10_0.h"
  36 #include "psp_v11_0.h"
  37 #include "psp_v11_0_8.h"
  38 #include "psp_v12_0.h"
  39 #include "psp_v13_0.h"
  40 #include "psp_v13_0_4.h"
  41
  42 #include "amdgpu_ras.h"
  43 #include "amdgpu_securedisplay.h"
  44 #include "amdgpu_atomfirmware.h"
  45
  46 #define AMD_VBIOS_FILE_MAX_SIZE_B      (1024*1024*3)
  47
  48 static int psp_load_smu_fw(struct psp_context *psp);
  49 static int psp_rap_terminate(struct psp_context *psp);
  50 static int psp_securedisplay_terminate(struct psp_context *psp);
  51
  52 static int psp_ring_init(struct psp_context *psp,
  53                          enum psp_ring_type ring_type)
  54 {
  55         int ret = 0;
  56         struct psp_ring *ring;
  57         struct amdgpu_device *adev = psp->adev;
  58
  59         ring = &psp->km_ring;
  60
  61         ring->ring_type = ring_type;
  62
  63         /* allocate 4k Page of Local Frame Buffer memory for ring */
  64         ring->ring_size = 0x1000;
  65         ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
  66                                       AMDGPU_GEM_DOMAIN_VRAM |
  67                                       AMDGPU_GEM_DOMAIN_GTT,
  68                                       &adev->firmware.rbuf,
  69                                       &ring->ring_mem_mc_addr,
  70                                       (void **)&ring->ring_mem);
  71         if (ret) {
  72                 ring->ring_size = 0;
  73                 return ret;
  74         }
  75
  76         return 0;
  77 }
  78
  79 /*
  80  * Due to DF Cstate management centralized to PMFW, the firmware
  81  * loading sequence will be updated as below:
  82  *   - Load KDB
  83  *   - Load SYS_DRV
  84  *   - Load tOS
  85  *   - Load PMFW
  86  *   - Setup TMR
  87  *   - Load other non-psp fw
  88  *   - Load ASD
  89  *   - Load XGMI/RAS/HDCP/DTM TA if any
  90  *
  91  * This new sequence is required for
  92  *   - Arcturus and onwards
  93  */
  94 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp)
  95 {
  96         struct amdgpu_device *adev = psp->adev;
  97
  98         if (amdgpu_sriov_vf(adev)) {
  99                 psp->pmfw_centralized_cstate_management = false;
 100                 return;
 101         }
 102
 103         switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
 104         case IP_VERSION(11, 0, 0):
 105         case IP_VERSION(11, 0, 4):
 106         case IP_VERSION(11, 0, 5):
 107         case IP_VERSION(11, 0, 7):
 108         case IP_VERSION(11, 0, 9):
 109         case IP_VERSION(11, 0, 11):
 110         case IP_VERSION(11, 0, 12):
 111         case IP_VERSION(11, 0, 13):
 112         case IP_VERSION(13, 0, 0):
 113         case IP_VERSION(13, 0, 2):
 114         case IP_VERSION(13, 0, 7):
 115                 psp->pmfw_centralized_cstate_management = true;
 116                 break;
 117         default:
 118                 psp->pmfw_centralized_cstate_management = false;
 119                 break;
 120         }
 121 }
 122
 123 static int psp_init_sriov_microcode(struct psp_context *psp)
 124 {
 125         struct amdgpu_device *adev = psp->adev;
 126         char ucode_prefix[30];
 127         int ret = 0;
 128
 129         amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
 130
 131         switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
 132         case IP_VERSION(9, 0, 0):
 133         case IP_VERSION(11, 0, 7):
 134         case IP_VERSION(11, 0, 9):
 135                 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 136                 ret = psp_init_cap_microcode(psp, ucode_prefix);
 137                 break;
 138         case IP_VERSION(13, 0, 2):
 139                 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 140                 ret = psp_init_cap_microcode(psp, ucode_prefix);
 141                 ret &= psp_init_ta_microcode(psp, ucode_prefix);
 142                 break;
 143         case IP_VERSION(13, 0, 0):
 144                 adev->virt.autoload_ucode_id = 0;
 145                 break;
 146         case IP_VERSION(13, 0, 6):
 147                 ret = psp_init_cap_microcode(psp, ucode_prefix);
 148                 ret &= psp_init_ta_microcode(psp, ucode_prefix);
 149                 break;
 150         case IP_VERSION(13, 0, 10):
 151                 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA;
 152                 ret = psp_init_cap_microcode(psp, ucode_prefix);
 153                 break;
 154         default:
 155                 return -EINVAL;
 156         }
 157         return ret;
 158 }
 159
 160 static int psp_early_init(void *handle)
 161 {
 162         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 163         struct psp_context *psp = &adev->psp;
 164
 165         switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
 166         case IP_VERSION(9, 0, 0):
 167                 psp_v3_1_set_psp_funcs(psp);
 168                 psp->autoload_supported = false;
 169                 break;
 170         case IP_VERSION(10, 0, 0):
 171         case IP_VERSION(10, 0, 1):
 172                 psp_v10_0_set_psp_funcs(psp);
 173                 psp->autoload_supported = false;
 174                 break;
 175         case IP_VERSION(11, 0, 2):
 176         case IP_VERSION(11, 0, 4):
 177                 psp_v11_0_set_psp_funcs(psp);
 178                 psp->autoload_supported = false;
 179                 break;
 180         case IP_VERSION(11, 0, 0):
 181         case IP_VERSION(11, 0, 7):
 182                 adev->psp.sup_pd_fw_up = !amdgpu_sriov_vf(adev);
 183                 fallthrough;
 184         case IP_VERSION(11, 0, 5):
 185         case IP_VERSION(11, 0, 9):
 186         case IP_VERSION(11, 0, 11):
 187         case IP_VERSION(11, 5, 0):
 188         case IP_VERSION(11, 0, 12):
 189         case IP_VERSION(11, 0, 13):
 190                 psp_v11_0_set_psp_funcs(psp);
 191                 psp->autoload_supported = true;
 192                 break;
 193         case IP_VERSION(11, 0, 3):
 194         case IP_VERSION(12, 0, 1):
 195                 psp_v12_0_set_psp_funcs(psp);
 196                 break;
 197         case IP_VERSION(13, 0, 2):
 198         case IP_VERSION(13, 0, 6):
 199                 psp_v13_0_set_psp_funcs(psp);
 200                 break;
 201         case IP_VERSION(13, 0, 1):
 202         case IP_VERSION(13, 0, 3):
 203         case IP_VERSION(13, 0, 5):
 204         case IP_VERSION(13, 0, 8):
 205         case IP_VERSION(13, 0, 11):
 206         case IP_VERSION(14, 0, 0):
 207                 psp_v13_0_set_psp_funcs(psp);
 208                 psp->autoload_supported = true;
 209                 break;
 210         case IP_VERSION(11, 0, 8):
 211                 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) {
 212                         psp_v11_0_8_set_psp_funcs(psp);
 213                         psp->autoload_supported = false;
 214                 }
 215                 break;
 216         case IP_VERSION(13, 0, 0):
 217         case IP_VERSION(13, 0, 7):
 218         case IP_VERSION(13, 0, 10):
 219                 psp_v13_0_set_psp_funcs(psp);
 220                 psp->autoload_supported = true;
 221                 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev);
 222                 break;
 223         case IP_VERSION(13, 0, 4):
 224                 psp_v13_0_4_set_psp_funcs(psp);
 225                 psp->autoload_supported = true;
 226                 break;
 227         default:
 228                 return -EINVAL;
 229         }
 230
 231         psp->adev = adev;
 232
 233         psp_check_pmfw_centralized_cstate_management(psp);
 234
 235         if (amdgpu_sriov_vf(adev))
 236                 return psp_init_sriov_microcode(psp);
 237         else
 238                 return psp_init_microcode(psp);
 239 }
 240
 241 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx)
 242 {
 243         amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr,
 244                               &mem_ctx->shared_buf);
 245         mem_ctx->shared_bo = NULL;
 246 }
 247
 248 static void psp_free_shared_bufs(struct psp_context *psp)
 249 {
 250         void *tmr_buf;
 251         void **pptr;
 252
 253         /* free TMR memory buffer */
 254         pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 255         amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
 256         psp->tmr_bo = NULL;
 257
 258         /* free xgmi shared memory */
 259         psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context);
 260
 261         /* free ras shared memory */
 262         psp_ta_free_shared_buf(&psp->ras_context.context.mem_context);
 263
 264         /* free hdcp shared memory */
 265         psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context);
 266
 267         /* free dtm shared memory */
 268         psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context);
 269
 270         /* free rap shared memory */
 271         psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
 272
 273         /* free securedisplay shared memory */
 274         psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
 275
 276
 277 }
 278
 279 static void psp_memory_training_fini(struct psp_context *psp)
 280 {
 281         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 282
 283         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
 284         kfree(ctx->sys_cache);
 285         ctx->sys_cache = NULL;
 286 }
 287
 288 static int psp_memory_training_init(struct psp_context *psp)
 289 {
 290         int ret;
 291         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 292
 293         if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
 294                 DRM_DEBUG("memory training is not supported!\n");
 295                 return 0;
 296         }
 297
 298         ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
 299         if (ctx->sys_cache == NULL) {
 300                 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
 301                 ret = -ENOMEM;
 302                 goto Err_out;
 303         }
 304
 305         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
 306                   ctx->train_data_size,
 307                   ctx->p2c_train_data_offset,
 308                   ctx->c2p_train_data_offset);
 309         ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
 310         return 0;
 311
 312 Err_out:
 313         psp_memory_training_fini(psp);
 314         return ret;
 315 }
 316
 317 /*
 318  * Helper funciton to query psp runtime database entry
 319  *
 320  * @adev: amdgpu_device pointer
 321  * @entry_type: the type of psp runtime database entry
 322  * @db_entry: runtime database entry pointer
 323  *
 324  * Return false if runtime database doesn't exit or entry is invalid
 325  * or true if the specific database entry is found, and copy to @db_entry
 326  */
 327 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev,
 328                                      enum psp_runtime_entry_type entry_type,
 329                                      void *db_entry)
 330 {
 331         uint64_t db_header_pos, db_dir_pos;
 332         struct psp_runtime_data_header db_header = {0};
 333         struct psp_runtime_data_directory db_dir = {0};
 334         bool ret = false;
 335         int i;
 336
 337         if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6))
 338                 return false;
 339
 340         db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET;
 341         db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header);
 342
 343         /* read runtime db header from vram */
 344         amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header,
 345                         sizeof(struct psp_runtime_data_header), false);
 346
 347         if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) {
 348                 /* runtime db doesn't exist, exit */
 349                 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n");
 350                 return false;
 351         }
 352
 353         /* read runtime database entry from vram */
 354         amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir,
 355                         sizeof(struct psp_runtime_data_directory), false);
 356
 357         if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) {
 358                 /* invalid db entry count, exit */
 359                 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n");
 360                 return false;
 361         }
 362
 363         /* look up for requested entry type */
 364         for (i = 0; i < db_dir.entry_count && !ret; i++) {
 365                 if (db_dir.entry_list[i].entry_type == entry_type) {
 366                         switch (entry_type) {
 367                         case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG:
 368                                 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) {
 369                                         /* invalid db entry size */
 370                                         dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n");
 371                                         return false;
 372                                 }
 373                                 /* read runtime database entry */
 374                                 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
 375                                                           (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false);
 376                                 ret = true;
 377                                 break;
 378                         case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS:
 379                                 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) {
 380                                         /* invalid db entry size */
 381                                         dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n");
 382                                         return false;
 383                                 }
 384                                 /* read runtime database entry */
 385                                 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
 386                                                           (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false);
 387                                 ret = true;
 388                                 break;
 389                         default:
 390                                 ret = false;
 391                                 break;
 392                         }
 393                 }
 394         }
 395
 396         return ret;
 397 }
 398
 399 static int psp_sw_init(void *handle)
 400 {
 401         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 402         struct psp_context *psp = &adev->psp;
 403         int ret;
 404         struct psp_runtime_boot_cfg_entry boot_cfg_entry;
 405         struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx;
 406         struct psp_runtime_scpm_entry scpm_entry;
 407
 408         psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 409         if (!psp->cmd) {
 410                 DRM_ERROR("Failed to allocate memory to command buffer!\n");
 411                 ret = -ENOMEM;
 412         }
 413
 414         adev->psp.xgmi_context.supports_extended_data =
 415                 !adev->gmc.xgmi.connected_to_cpu &&
 416                 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2);
 417
 418         memset(&scpm_entry, 0, sizeof(scpm_entry));
 419         if ((psp_get_runtime_db_entry(adev,
 420                                 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS,
 421                                 &scpm_entry)) &&
 422             (scpm_entry.scpm_status != SCPM_DISABLE)) {
 423                 adev->scpm_enabled = true;
 424                 adev->scpm_status = scpm_entry.scpm_status;
 425         } else {
 426                 adev->scpm_enabled = false;
 427                 adev->scpm_status = SCPM_DISABLE;
 428         }
 429
 430         /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */
 431
 432         memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry));
 433         if (psp_get_runtime_db_entry(adev,
 434                                 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG,
 435                                 &boot_cfg_entry)) {
 436                 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask;
 437                 if ((psp->boot_cfg_bitmask) &
 438                     BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) {
 439                         /* If psp runtime database exists, then
 440                          * only enable two stage memory training
 441                          * when TWO_STAGE_DRAM_TRAINING bit is set
 442                          * in runtime database
 443                          */
 444                         mem_training_ctx->enable_mem_training = true;
 445                 }
 446
 447         } else {
 448                 /* If psp runtime database doesn't exist or is
 449                  * invalid, force enable two stage memory training
 450                  */
 451                 mem_training_ctx->enable_mem_training = true;
 452         }
 453
 454         if (mem_training_ctx->enable_mem_training) {
 455                 ret = psp_memory_training_init(psp);
 456                 if (ret) {
 457                         DRM_ERROR("Failed to initialize memory training!\n");
 458                         return ret;
 459                 }
 460
 461                 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
 462                 if (ret) {
 463                         DRM_ERROR("Failed to process memory training!\n");
 464                         return ret;
 465                 }
 466         }
 467
 468         ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
 469                                       amdgpu_sriov_vf(adev) ?
 470                                       AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
 471                                       &psp->fw_pri_bo,
 472                                       &psp->fw_pri_mc_addr,
 473                                       &psp->fw_pri_buf);
 474         if (ret)
 475                 return ret;
 476
 477         ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
 478                                       AMDGPU_GEM_DOMAIN_VRAM |
 479                                       AMDGPU_GEM_DOMAIN_GTT,
 480                                       &psp->fence_buf_bo,
 481                                       &psp->fence_buf_mc_addr,
 482                                       &psp->fence_buf);
 483         if (ret)
 484                 goto failed1;
 485
 486         ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
 487                                       AMDGPU_GEM_DOMAIN_VRAM |
 488                                       AMDGPU_GEM_DOMAIN_GTT,
 489                                       &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 490                                       (void **)&psp->cmd_buf_mem);
 491         if (ret)
 492                 goto failed2;
 493
 494         return 0;
 495
 496 failed2:
 497         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 498                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 499 failed1:
 500         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 501                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 502         return ret;
 503 }
 504
 505 static int psp_sw_fini(void *handle)
 506 {
 507         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 508         struct psp_context *psp = &adev->psp;
 509         struct psp_gfx_cmd_resp *cmd = psp->cmd;
 510
 511         psp_memory_training_fini(psp);
 512
 513         amdgpu_ucode_release(&psp->sos_fw);
 514         amdgpu_ucode_release(&psp->asd_fw);
 515         amdgpu_ucode_release(&psp->ta_fw);
 516         amdgpu_ucode_release(&psp->cap_fw);
 517         amdgpu_ucode_release(&psp->toc_fw);
 518
 519         kfree(cmd);
 520         cmd = NULL;
 521
 522         psp_free_shared_bufs(psp);
 523
 524         if (psp->km_ring.ring_mem)
 525                 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 526                                       &psp->km_ring.ring_mem_mc_addr,
 527                                       (void **)&psp->km_ring.ring_mem);
 528
 529         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 530                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 531         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 532                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 533         amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 534                               (void **)&psp->cmd_buf_mem);
 535
 536         return 0;
 537 }
 538
 539 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
 540                  uint32_t reg_val, uint32_t mask, bool check_changed)
 541 {
 542         uint32_t val;
 543         int i;
 544         struct amdgpu_device *adev = psp->adev;
 545
 546         if (psp->adev->no_hw_access)
 547                 return 0;
 548
 549         for (i = 0; i < adev->usec_timeout; i++) {
 550                 val = RREG32(reg_index);
 551                 if (check_changed) {
 552                         if (val != reg_val)
 553                                 return 0;
 554                 } else {
 555                         if ((val & mask) == reg_val)
 556                                 return 0;
 557                 }
 558                 udelay(1);
 559         }
 560
 561         return -ETIME;
 562 }
 563
 564 int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index,
 565                                uint32_t reg_val, uint32_t mask, uint32_t msec_timeout)
 566 {
 567         uint32_t val;
 568         int i;
 569         struct amdgpu_device *adev = psp->adev;
 570
 571         if (psp->adev->no_hw_access)
 572                 return 0;
 573
 574         for (i = 0; i < msec_timeout; i++) {
 575                 val = RREG32(reg_index);
 576                 if ((val & mask) == reg_val)
 577                         return 0;
 578                 msleep(1);
 579         }
 580
 581         return -ETIME;
 582 }
 583
 584 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id)
 585 {
 586         switch (cmd_id) {
 587         case GFX_CMD_ID_LOAD_TA:
 588                 return "LOAD_TA";
 589         case GFX_CMD_ID_UNLOAD_TA:
 590                 return "UNLOAD_TA";
 591         case GFX_CMD_ID_INVOKE_CMD:
 592                 return "INVOKE_CMD";
 593         case GFX_CMD_ID_LOAD_ASD:
 594                 return "LOAD_ASD";
 595         case GFX_CMD_ID_SETUP_TMR:
 596                 return "SETUP_TMR";
 597         case GFX_CMD_ID_LOAD_IP_FW:
 598                 return "LOAD_IP_FW";
 599         case GFX_CMD_ID_DESTROY_TMR:
 600                 return "DESTROY_TMR";
 601         case GFX_CMD_ID_SAVE_RESTORE:
 602                 return "SAVE_RESTORE_IP_FW";
 603         case GFX_CMD_ID_SETUP_VMR:
 604                 return "SETUP_VMR";
 605         case GFX_CMD_ID_DESTROY_VMR:
 606                 return "DESTROY_VMR";
 607         case GFX_CMD_ID_PROG_REG:
 608                 return "PROG_REG";
 609         case GFX_CMD_ID_GET_FW_ATTESTATION:
 610                 return "GET_FW_ATTESTATION";
 611         case GFX_CMD_ID_LOAD_TOC:
 612                 return "ID_LOAD_TOC";
 613         case GFX_CMD_ID_AUTOLOAD_RLC:
 614                 return "AUTOLOAD_RLC";
 615         case GFX_CMD_ID_BOOT_CFG:
 616                 return "BOOT_CFG";
 617         default:
 618                 return "UNKNOWN CMD";
 619         }
 620 }
 621
 622 static int
 623 psp_cmd_submit_buf(struct psp_context *psp,
 624                    struct amdgpu_firmware_info *ucode,
 625                    struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
 626 {
 627         int ret;
 628         int index;
 629         int timeout = 20000;
 630         bool ras_intr = false;
 631         bool skip_unsupport = false;
 632
 633         if (psp->adev->no_hw_access)
 634                 return 0;
 635
 636         memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
 637
 638         memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 639
 640         index = atomic_inc_return(&psp->fence_value);
 641         ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
 642         if (ret) {
 643                 atomic_dec(&psp->fence_value);
 644                 goto exit;
 645         }
 646
 647         amdgpu_device_invalidate_hdp(psp->adev, NULL);
 648         while (*((unsigned int *)psp->fence_buf) != index) {
 649                 if (--timeout == 0)
 650                         break;
 651                 /*
 652                  * Shouldn't wait for timeout when err_event_athub occurs,
 653                  * because gpu reset thread triggered and lock resource should
 654                  * be released for psp resume sequence.
 655                  */
 656                 ras_intr = amdgpu_ras_intr_triggered();
 657                 if (ras_intr)
 658                         break;
 659                 usleep_range(10, 100);
 660                 amdgpu_device_invalidate_hdp(psp->adev, NULL);
 661         }
 662
 663         /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
 664         skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED ||
 665                 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev);
 666
 667         memcpy(&cmd->resp, &psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp));
 668
 669         /* In some cases, psp response status is not 0 even there is no
 670          * problem while the command is submitted. Some version of PSP FW
 671          * doesn't write 0 to that field.
 672          * So here we would like to only print a warning instead of an error
 673          * during psp initialization to avoid breaking hw_init and it doesn't
 674          * return -EINVAL.
 675          */
 676         if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
 677                 if (ucode)
 678                         DRM_WARN("failed to load ucode %s(0x%X) ",
 679                                   amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id);
 680                 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n",
 681                          psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id,
 682                          psp->cmd_buf_mem->resp.status);
 683                 /* If any firmware (including CAP) load fails under SRIOV, it should
 684                  * return failure to stop the VF from initializing.
 685                  * Also return failure in case of timeout
 686                  */
 687                 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) {
 688                         ret = -EINVAL;
 689                         goto exit;
 690                 }
 691         }
 692
 693         if (ucode) {
 694                 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
 695                 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
 696         }
 697
 698 exit:
 699         return ret;
 700 }
 701
 702 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp)
 703 {
 704         struct psp_gfx_cmd_resp *cmd = psp->cmd;
 705
 706         mutex_lock(&psp->mutex);
 707
 708         memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
 709
 710         return cmd;
 711 }
 712
 713 static void release_psp_cmd_buf(struct psp_context *psp)
 714 {
 715         mutex_unlock(&psp->mutex);
 716 }
 717
 718 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
 719                                  struct psp_gfx_cmd_resp *cmd,
 720                                  uint64_t tmr_mc, struct amdgpu_bo *tmr_bo)
 721 {
 722         struct amdgpu_device *adev = psp->adev;
 723         uint32_t size = 0;
 724         uint64_t tmr_pa = 0;
 725
 726         if (tmr_bo) {
 727                 size = amdgpu_bo_size(tmr_bo);
 728                 tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo);
 729         }
 730
 731         if (amdgpu_sriov_vf(psp->adev))
 732                 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
 733         else
 734                 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
 735         cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
 736         cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
 737         cmd->cmd.cmd_setup_tmr.buf_size = size;
 738         cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1;
 739         cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa);
 740         cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa);
 741 }
 742
 743 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 744                                       uint64_t pri_buf_mc, uint32_t size)
 745 {
 746         cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
 747         cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
 748         cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
 749         cmd->cmd.cmd_load_toc.toc_size = size;
 750 }
 751
 752 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
 753 static int psp_load_toc(struct psp_context *psp,
 754                         uint32_t *tmr_size)
 755 {
 756         int ret;
 757         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
 758
 759         /* Copy toc to psp firmware private buffer */
 760         psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes);
 761
 762         psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes);
 763
 764         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 765                                  psp->fence_buf_mc_addr);
 766         if (!ret)
 767                 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
 768
 769         release_psp_cmd_buf(psp);
 770
 771         return ret;
 772 }
 773
 774 static bool psp_boottime_tmr(struct psp_context *psp)
 775 {
 776         switch (amdgpu_ip_version(psp->adev, MP0_HWIP, 0)) {
 777         case IP_VERSION(13, 0, 6):
 778                 return true;
 779         default:
 780                 return false;
 781         }
 782 }
 783
 784 /* Set up Trusted Memory Region */
 785 static int psp_tmr_init(struct psp_context *psp)
 786 {
 787         int ret = 0;
 788         int tmr_size;
 789         void *tmr_buf;
 790         void **pptr;
 791
 792         /*
 793          * According to HW engineer, they prefer the TMR address be "naturally
 794          * aligned" , e.g. the start address be an integer divide of TMR size.
 795          *
 796          * Note: this memory need be reserved till the driver
 797          * uninitializes.
 798          */
 799         tmr_size = PSP_TMR_SIZE(psp->adev);
 800
 801         /* For ASICs support RLC autoload, psp will parse the toc
 802          * and calculate the total size of TMR needed
 803          */
 804         if (!amdgpu_sriov_vf(psp->adev) &&
 805             psp->toc.start_addr &&
 806             psp->toc.size_bytes &&
 807             psp->fw_pri_buf) {
 808                 ret = psp_load_toc(psp, &tmr_size);
 809                 if (ret) {
 810                         DRM_ERROR("Failed to load toc\n");
 811                         return ret;
 812                 }
 813         }
 814
 815         if (!psp->tmr_bo) {
 816                 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 817                 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size,
 818                                               PSP_TMR_ALIGNMENT,
 819                                               AMDGPU_HAS_VRAM(psp->adev) ?
 820                                               AMDGPU_GEM_DOMAIN_VRAM :
 821                                               AMDGPU_GEM_DOMAIN_GTT,
 822                                               &psp->tmr_bo, &psp->tmr_mc_addr,
 823                                               pptr);
 824         }
 825
 826         return ret;
 827 }
 828
 829 static bool psp_skip_tmr(struct psp_context *psp)
 830 {
 831         switch (amdgpu_ip_version(psp->adev, MP0_HWIP, 0)) {
 832         case IP_VERSION(11, 0, 9):
 833         case IP_VERSION(11, 0, 7):
 834         case IP_VERSION(13, 0, 2):
 835         case IP_VERSION(13, 0, 6):
 836         case IP_VERSION(13, 0, 10):
 837                 return true;
 838         default:
 839                 return false;
 840         }
 841 }
 842
 843 static int psp_tmr_load(struct psp_context *psp)
 844 {
 845         int ret;
 846         struct psp_gfx_cmd_resp *cmd;
 847
 848         /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR.
 849          * Already set up by host driver.
 850          */
 851         if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
 852                 return 0;
 853
 854         cmd = acquire_psp_cmd_buf(psp);
 855
 856         psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo);
 857         if (psp->tmr_bo)
 858                 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
 859                          amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
 860
 861         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 862                                  psp->fence_buf_mc_addr);
 863
 864         release_psp_cmd_buf(psp);
 865
 866         return ret;
 867 }
 868
 869 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp,
 870                                         struct psp_gfx_cmd_resp *cmd)
 871 {
 872         if (amdgpu_sriov_vf(psp->adev))
 873                 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR;
 874         else
 875                 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR;
 876 }
 877
 878 static int psp_tmr_unload(struct psp_context *psp)
 879 {
 880         int ret;
 881         struct psp_gfx_cmd_resp *cmd;
 882
 883         /* skip TMR unload for Navi12 and CHIP_SIENNA_CICHLID SRIOV,
 884          * as TMR is not loaded at all
 885          */
 886         if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
 887                 return 0;
 888
 889         cmd = acquire_psp_cmd_buf(psp);
 890
 891         psp_prep_tmr_unload_cmd_buf(psp, cmd);
 892         dev_dbg(psp->adev->dev, "free PSP TMR buffer\n");
 893
 894         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 895                                  psp->fence_buf_mc_addr);
 896
 897         release_psp_cmd_buf(psp);
 898
 899         return ret;
 900 }
 901
 902 static int psp_tmr_terminate(struct psp_context *psp)
 903 {
 904         return psp_tmr_unload(psp);
 905 }
 906
 907 int psp_get_fw_attestation_records_addr(struct psp_context *psp,
 908                                         uint64_t *output_ptr)
 909 {
 910         int ret;
 911         struct psp_gfx_cmd_resp *cmd;
 912
 913         if (!output_ptr)
 914                 return -EINVAL;
 915
 916         if (amdgpu_sriov_vf(psp->adev))
 917                 return 0;
 918
 919         cmd = acquire_psp_cmd_buf(psp);
 920
 921         cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION;
 922
 923         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 924                                  psp->fence_buf_mc_addr);
 925
 926         if (!ret) {
 927                 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) +
 928                               ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32);
 929         }
 930
 931         release_psp_cmd_buf(psp);
 932
 933         return ret;
 934 }
 935
 936 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg)
 937 {
 938         struct psp_context *psp = &adev->psp;
 939         struct psp_gfx_cmd_resp *cmd;
 940         int ret;
 941
 942         if (amdgpu_sriov_vf(adev))
 943                 return 0;
 944
 945         cmd = acquire_psp_cmd_buf(psp);
 946
 947         cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
 948         cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET;
 949
 950         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 951         if (!ret) {
 952                 *boot_cfg =
 953                         (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0;
 954         }
 955
 956         release_psp_cmd_buf(psp);
 957
 958         return ret;
 959 }
 960
 961 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg)
 962 {
 963         int ret;
 964         struct psp_context *psp = &adev->psp;
 965         struct psp_gfx_cmd_resp *cmd;
 966
 967         if (amdgpu_sriov_vf(adev))
 968                 return 0;
 969
 970         cmd = acquire_psp_cmd_buf(psp);
 971
 972         cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
 973         cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET;
 974         cmd->cmd.boot_cfg.boot_config = boot_cfg;
 975         cmd->cmd.boot_cfg.boot_config_valid = boot_cfg;
 976
 977         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 978
 979         release_psp_cmd_buf(psp);
 980
 981         return ret;
 982 }
 983
 984 static int psp_rl_load(struct amdgpu_device *adev)
 985 {
 986         int ret;
 987         struct psp_context *psp = &adev->psp;
 988         struct psp_gfx_cmd_resp *cmd;
 989
 990         if (!is_psp_fw_valid(psp->rl))
 991                 return 0;
 992
 993         cmd = acquire_psp_cmd_buf(psp);
 994
 995         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 996         memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes);
 997
 998         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
 999         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr);
1000         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr);
1001         cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes;
1002         cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST;
1003
1004         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1005
1006         release_psp_cmd_buf(psp);
1007
1008         return ret;
1009 }
1010
1011 int psp_spatial_partition(struct psp_context *psp, int mode)
1012 {
1013         struct psp_gfx_cmd_resp *cmd;
1014         int ret;
1015
1016         if (amdgpu_sriov_vf(psp->adev))
1017                 return 0;
1018
1019         cmd = acquire_psp_cmd_buf(psp);
1020
1021         cmd->cmd_id = GFX_CMD_ID_SRIOV_SPATIAL_PART;
1022         cmd->cmd.cmd_spatial_part.mode = mode;
1023
1024         dev_info(psp->adev->dev, "Requesting %d partitions through PSP", mode);
1025         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1026
1027         release_psp_cmd_buf(psp);
1028
1029         return ret;
1030 }
1031
1032 static int psp_asd_initialize(struct psp_context *psp)
1033 {
1034         int ret;
1035
1036         /* If PSP version doesn't match ASD version, asd loading will be failed.
1037          * add workaround to bypass it for sriov now.
1038          * TODO: add version check to make it common
1039          */
1040         if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes)
1041                 return 0;
1042
1043         psp->asd_context.mem_context.shared_mc_addr  = 0;
1044         psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE;
1045         psp->asd_context.ta_load_type                = GFX_CMD_ID_LOAD_ASD;
1046
1047         ret = psp_ta_load(psp, &psp->asd_context);
1048         if (!ret)
1049                 psp->asd_context.initialized = true;
1050
1051         return ret;
1052 }
1053
1054 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1055                                        uint32_t session_id)
1056 {
1057         cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
1058         cmd->cmd.cmd_unload_ta.session_id = session_id;
1059 }
1060
1061 int psp_ta_unload(struct psp_context *psp, struct ta_context *context)
1062 {
1063         int ret;
1064         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1065
1066         psp_prep_ta_unload_cmd_buf(cmd, context->session_id);
1067
1068         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1069
1070         context->resp_status = cmd->resp.status;
1071
1072         release_psp_cmd_buf(psp);
1073
1074         return ret;
1075 }
1076
1077 static int psp_asd_terminate(struct psp_context *psp)
1078 {
1079         int ret;
1080
1081         if (amdgpu_sriov_vf(psp->adev))
1082                 return 0;
1083
1084         if (!psp->asd_context.initialized)
1085                 return 0;
1086
1087         ret = psp_ta_unload(psp, &psp->asd_context);
1088         if (!ret)
1089                 psp->asd_context.initialized = false;
1090
1091         return ret;
1092 }
1093
1094 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1095                 uint32_t id, uint32_t value)
1096 {
1097         cmd->cmd_id = GFX_CMD_ID_PROG_REG;
1098         cmd->cmd.cmd_setup_reg_prog.reg_value = value;
1099         cmd->cmd.cmd_setup_reg_prog.reg_id = id;
1100 }
1101
1102 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
1103                 uint32_t value)
1104 {
1105         struct psp_gfx_cmd_resp *cmd;
1106         int ret = 0;
1107
1108         if (reg >= PSP_REG_LAST)
1109                 return -EINVAL;
1110
1111         cmd = acquire_psp_cmd_buf(psp);
1112
1113         psp_prep_reg_prog_cmd_buf(cmd, reg, value);
1114         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1115         if (ret)
1116                 DRM_ERROR("PSP failed to program reg id %d", reg);
1117
1118         release_psp_cmd_buf(psp);
1119
1120         return ret;
1121 }
1122
1123 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1124                                      uint64_t ta_bin_mc,
1125                                      struct ta_context *context)
1126 {
1127         cmd->cmd_id                             = context->ta_load_type;
1128         cmd->cmd.cmd_load_ta.app_phy_addr_lo    = lower_32_bits(ta_bin_mc);
1129         cmd->cmd.cmd_load_ta.app_phy_addr_hi    = upper_32_bits(ta_bin_mc);
1130         cmd->cmd.cmd_load_ta.app_len            = context->bin_desc.size_bytes;
1131
1132         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo =
1133                 lower_32_bits(context->mem_context.shared_mc_addr);
1134         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi =
1135                 upper_32_bits(context->mem_context.shared_mc_addr);
1136         cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size;
1137 }
1138
1139 int psp_ta_init_shared_buf(struct psp_context *psp,
1140                                   struct ta_mem_context *mem_ctx)
1141 {
1142         /*
1143          * Allocate 16k memory aligned to 4k from Frame Buffer (local
1144          * physical) for ta to host memory
1145          */
1146         return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size,
1147                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM |
1148                                       AMDGPU_GEM_DOMAIN_GTT,
1149                                       &mem_ctx->shared_bo,
1150                                       &mem_ctx->shared_mc_addr,
1151                                       &mem_ctx->shared_buf);
1152 }
1153
1154 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1155                                        uint32_t ta_cmd_id,
1156                                        uint32_t session_id)
1157 {
1158         cmd->cmd_id                             = GFX_CMD_ID_INVOKE_CMD;
1159         cmd->cmd.cmd_invoke_cmd.session_id      = session_id;
1160         cmd->cmd.cmd_invoke_cmd.ta_cmd_id       = ta_cmd_id;
1161 }
1162
1163 int psp_ta_invoke(struct psp_context *psp,
1164                   uint32_t ta_cmd_id,
1165                   struct ta_context *context)
1166 {
1167         int ret;
1168         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1169
1170         psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id);
1171
1172         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1173                                  psp->fence_buf_mc_addr);
1174
1175         context->resp_status = cmd->resp.status;
1176
1177         release_psp_cmd_buf(psp);
1178
1179         return ret;
1180 }
1181
1182 int psp_ta_load(struct psp_context *psp, struct ta_context *context)
1183 {
1184         int ret;
1185         struct psp_gfx_cmd_resp *cmd;
1186
1187         cmd = acquire_psp_cmd_buf(psp);
1188
1189         psp_copy_fw(psp, context->bin_desc.start_addr,
1190                     context->bin_desc.size_bytes);
1191
1192         psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context);
1193
1194         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1195                                  psp->fence_buf_mc_addr);
1196
1197         context->resp_status = cmd->resp.status;
1198
1199         if (!ret)
1200                 context->session_id = cmd->resp.session_id;
1201
1202         release_psp_cmd_buf(psp);
1203
1204         return ret;
1205 }
1206
1207 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1208 {
1209         return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context);
1210 }
1211
1212 int psp_xgmi_terminate(struct psp_context *psp)
1213 {
1214         int ret;
1215         struct amdgpu_device *adev = psp->adev;
1216
1217         /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
1218         if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) ||
1219             (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) &&
1220              adev->gmc.xgmi.connected_to_cpu))
1221                 return 0;
1222
1223         if (!psp->xgmi_context.context.initialized)
1224                 return 0;
1225
1226         ret = psp_ta_unload(psp, &psp->xgmi_context.context);
1227
1228         psp->xgmi_context.context.initialized = false;
1229
1230         return ret;
1231 }
1232
1233 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta)
1234 {
1235         struct ta_xgmi_shared_memory *xgmi_cmd;
1236         int ret;
1237
1238         if (!psp->ta_fw ||
1239             !psp->xgmi_context.context.bin_desc.size_bytes ||
1240             !psp->xgmi_context.context.bin_desc.start_addr)
1241                 return -ENOENT;
1242
1243         if (!load_ta)
1244                 goto invoke;
1245
1246         psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE;
1247         psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1248
1249         if (!psp->xgmi_context.context.mem_context.shared_buf) {
1250                 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context);
1251                 if (ret)
1252                         return ret;
1253         }
1254
1255         /* Load XGMI TA */
1256         ret = psp_ta_load(psp, &psp->xgmi_context.context);
1257         if (!ret)
1258                 psp->xgmi_context.context.initialized = true;
1259         else
1260                 return ret;
1261
1262 invoke:
1263         /* Initialize XGMI session */
1264         xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf);
1265         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1266         xgmi_cmd->flag_extend_link_record = set_extended_data;
1267         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
1268
1269         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1270
1271         return ret;
1272 }
1273
1274 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
1275 {
1276         struct ta_xgmi_shared_memory *xgmi_cmd;
1277         int ret;
1278
1279         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1280         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1281
1282         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
1283
1284         /* Invoke xgmi ta to get hive id */
1285         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1286         if (ret)
1287                 return ret;
1288
1289         *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
1290
1291         return 0;
1292 }
1293
1294 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
1295 {
1296         struct ta_xgmi_shared_memory *xgmi_cmd;
1297         int ret;
1298
1299         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1300         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1301
1302         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
1303
1304         /* Invoke xgmi ta to get the node id */
1305         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1306         if (ret)
1307                 return ret;
1308
1309         *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
1310
1311         return 0;
1312 }
1313
1314 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp)
1315 {
1316         return (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) ==
1317                         IP_VERSION(13, 0, 2) &&
1318                 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b) ||
1319                amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >=
1320                        IP_VERSION(13, 0, 6);
1321 }
1322
1323 /*
1324  * Chips that support extended topology information require the driver to
1325  * reflect topology information in the opposite direction.  This is
1326  * because the TA has already exceeded its link record limit and if the
1327  * TA holds bi-directional information, the driver would have to do
1328  * multiple fetches instead of just two.
1329  */
1330 static void psp_xgmi_reflect_topology_info(struct psp_context *psp,
1331                                         struct psp_xgmi_node_info node_info)
1332 {
1333         struct amdgpu_device *mirror_adev;
1334         struct amdgpu_hive_info *hive;
1335         uint64_t src_node_id = psp->adev->gmc.xgmi.node_id;
1336         uint64_t dst_node_id = node_info.node_id;
1337         uint8_t dst_num_hops = node_info.num_hops;
1338         uint8_t dst_num_links = node_info.num_links;
1339
1340         hive = amdgpu_get_xgmi_hive(psp->adev);
1341         list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) {
1342                 struct psp_xgmi_topology_info *mirror_top_info;
1343                 int j;
1344
1345                 if (mirror_adev->gmc.xgmi.node_id != dst_node_id)
1346                         continue;
1347
1348                 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info;
1349                 for (j = 0; j < mirror_top_info->num_nodes; j++) {
1350                         if (mirror_top_info->nodes[j].node_id != src_node_id)
1351                                 continue;
1352
1353                         mirror_top_info->nodes[j].num_hops = dst_num_hops;
1354                         /*
1355                          * prevent 0 num_links value re-reflection since reflection
1356                          * criteria is based on num_hops (direct or indirect).
1357                          *
1358                          */
1359                         if (dst_num_links)
1360                                 mirror_top_info->nodes[j].num_links = dst_num_links;
1361
1362                         break;
1363                 }
1364
1365                 break;
1366         }
1367
1368         amdgpu_put_xgmi_hive(hive);
1369 }
1370
1371 int psp_xgmi_get_topology_info(struct psp_context *psp,
1372                                int number_devices,
1373                                struct psp_xgmi_topology_info *topology,
1374                                bool get_extended_data)
1375 {
1376         struct ta_xgmi_shared_memory *xgmi_cmd;
1377         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1378         struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
1379         int i;
1380         int ret;
1381
1382         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1383                 return -EINVAL;
1384
1385         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1386         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1387         xgmi_cmd->flag_extend_link_record = get_extended_data;
1388
1389         /* Fill in the shared memory with topology information as input */
1390         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1391         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
1392         topology_info_input->num_nodes = number_devices;
1393
1394         for (i = 0; i < topology_info_input->num_nodes; i++) {
1395                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1396                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1397                 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
1398                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1399         }
1400
1401         /* Invoke xgmi ta to get the topology information */
1402         ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
1403         if (ret)
1404                 return ret;
1405
1406         /* Read the output topology information from the shared memory */
1407         topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
1408         topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
1409         for (i = 0; i < topology->num_nodes; i++) {
1410                 /* extended data will either be 0 or equal to non-extended data */
1411                 if (topology_info_output->nodes[i].num_hops)
1412                         topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
1413
1414                 /* non-extended data gets everything here so no need to update */
1415                 if (!get_extended_data) {
1416                         topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
1417                         topology->nodes[i].is_sharing_enabled =
1418                                         topology_info_output->nodes[i].is_sharing_enabled;
1419                         topology->nodes[i].sdma_engine =
1420                                         topology_info_output->nodes[i].sdma_engine;
1421                 }
1422
1423         }
1424
1425         /* Invoke xgmi ta again to get the link information */
1426         if (psp_xgmi_peer_link_info_supported(psp)) {
1427                 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output;
1428                 bool requires_reflection =
1429                         (psp->xgmi_context.supports_extended_data &&
1430                          get_extended_data) ||
1431                         amdgpu_ip_version(psp->adev, MP0_HWIP, 0) ==
1432                                 IP_VERSION(13, 0, 6);
1433
1434                 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS;
1435
1436                 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS);
1437
1438                 if (ret)
1439                         return ret;
1440
1441                 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info;
1442                 for (i = 0; i < topology->num_nodes; i++) {
1443                         /* accumulate num_links on extended data */
1444                         topology->nodes[i].num_links = get_extended_data ?
1445                                         topology->nodes[i].num_links +
1446                                                         link_info_output->nodes[i].num_links :
1447                                         ((requires_reflection && topology->nodes[i].num_links) ? topology->nodes[i].num_links :
1448                                          link_info_output->nodes[i].num_links);
1449
1450                         /* reflect the topology information for bi-directionality */
1451                         if (requires_reflection && topology->nodes[i].num_hops)
1452                                 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]);
1453                 }
1454         }
1455
1456         return 0;
1457 }
1458
1459 int psp_xgmi_set_topology_info(struct psp_context *psp,
1460                                int number_devices,
1461                                struct psp_xgmi_topology_info *topology)
1462 {
1463         struct ta_xgmi_shared_memory *xgmi_cmd;
1464         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1465         int i;
1466
1467         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1468                 return -EINVAL;
1469
1470         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1471         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1472
1473         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1474         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
1475         topology_info_input->num_nodes = number_devices;
1476
1477         for (i = 0; i < topology_info_input->num_nodes; i++) {
1478                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1479                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1480                 topology_info_input->nodes[i].is_sharing_enabled = 1;
1481                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1482         }
1483
1484         /* Invoke xgmi ta to set topology information */
1485         return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
1486 }
1487
1488 // ras begin
1489 static void psp_ras_ta_check_status(struct psp_context *psp)
1490 {
1491         struct ta_ras_shared_memory *ras_cmd =
1492                 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1493
1494         switch (ras_cmd->ras_status) {
1495         case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP:
1496                 dev_warn(psp->adev->dev,
1497                                 "RAS WARNING: cmd failed due to unsupported ip\n");
1498                 break;
1499         case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ:
1500                 dev_warn(psp->adev->dev,
1501                                 "RAS WARNING: cmd failed due to unsupported error injection\n");
1502                 break;
1503         case TA_RAS_STATUS__SUCCESS:
1504                 break;
1505         case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED:
1506                 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR)
1507                         dev_warn(psp->adev->dev,
1508                                         "RAS WARNING: Inject error to critical region is not allowed\n");
1509                 break;
1510         default:
1511                 dev_warn(psp->adev->dev,
1512                                 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status);
1513                 break;
1514         }
1515 }
1516
1517 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1518 {
1519         struct ta_ras_shared_memory *ras_cmd;
1520         int ret;
1521
1522         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1523
1524         /*
1525          * TODO: bypass the loading in sriov for now
1526          */
1527         if (amdgpu_sriov_vf(psp->adev))
1528                 return 0;
1529
1530         ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context);
1531
1532         if (amdgpu_ras_intr_triggered())
1533                 return ret;
1534
1535         if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) {
1536                 DRM_WARN("RAS: Unsupported Interface");
1537                 return -EINVAL;
1538         }
1539
1540         if (!ret) {
1541                 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) {
1542                         dev_warn(psp->adev->dev, "ECC switch disabled\n");
1543
1544                         ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE;
1545                 } else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag)
1546                         dev_warn(psp->adev->dev,
1547                                  "RAS internal register access blocked\n");
1548
1549                 psp_ras_ta_check_status(psp);
1550         }
1551
1552         return ret;
1553 }
1554
1555 int psp_ras_enable_features(struct psp_context *psp,
1556                 union ta_ras_cmd_input *info, bool enable)
1557 {
1558         struct ta_ras_shared_memory *ras_cmd;
1559         int ret;
1560
1561         if (!psp->ras_context.context.initialized)
1562                 return -EINVAL;
1563
1564         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1565         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1566
1567         if (enable)
1568                 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
1569         else
1570                 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
1571
1572         ras_cmd->ras_in_message = *info;
1573
1574         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1575         if (ret)
1576                 return -EINVAL;
1577
1578         return 0;
1579 }
1580
1581 int psp_ras_terminate(struct psp_context *psp)
1582 {
1583         int ret;
1584
1585         /*
1586          * TODO: bypass the terminate in sriov for now
1587          */
1588         if (amdgpu_sriov_vf(psp->adev))
1589                 return 0;
1590
1591         if (!psp->ras_context.context.initialized)
1592                 return 0;
1593
1594         ret = psp_ta_unload(psp, &psp->ras_context.context);
1595
1596         psp->ras_context.context.initialized = false;
1597
1598         return ret;
1599 }
1600
1601 int psp_ras_initialize(struct psp_context *psp)
1602 {
1603         int ret;
1604         uint32_t boot_cfg = 0xFF;
1605         struct amdgpu_device *adev = psp->adev;
1606         struct ta_ras_shared_memory *ras_cmd;
1607
1608         /*
1609          * TODO: bypass the initialize in sriov for now
1610          */
1611         if (amdgpu_sriov_vf(adev))
1612                 return 0;
1613
1614         if (!adev->psp.ras_context.context.bin_desc.size_bytes ||
1615             !adev->psp.ras_context.context.bin_desc.start_addr) {
1616                 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n");
1617                 return 0;
1618         }
1619
1620         if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) {
1621                 /* query GECC enablement status from boot config
1622                  * boot_cfg: 1: GECC is enabled or 0: GECC is disabled
1623                  */
1624                 ret = psp_boot_config_get(adev, &boot_cfg);
1625                 if (ret)
1626                         dev_warn(adev->dev, "PSP get boot config failed\n");
1627
1628                 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) {
1629                         if (!boot_cfg) {
1630                                 dev_info(adev->dev, "GECC is disabled\n");
1631                         } else {
1632                                 /* disable GECC in next boot cycle if ras is
1633                                  * disabled by module parameter amdgpu_ras_enable
1634                                  * and/or amdgpu_ras_mask, or boot_config_get call
1635                                  * is failed
1636                                  */
1637                                 ret = psp_boot_config_set(adev, 0);
1638                                 if (ret)
1639                                         dev_warn(adev->dev, "PSP set boot config failed\n");
1640                                 else
1641                                         dev_warn(adev->dev, "GECC will be disabled in next boot cycle if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n");
1642                         }
1643                 } else {
1644                         if (boot_cfg == 1) {
1645                                 dev_info(adev->dev, "GECC is enabled\n");
1646                         } else {
1647                                 /* enable GECC in next boot cycle if it is disabled
1648                                  * in boot config, or force enable GECC if failed to
1649                                  * get boot configuration
1650                                  */
1651                                 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC);
1652                                 if (ret)
1653                                         dev_warn(adev->dev, "PSP set boot config failed\n");
1654                                 else
1655                                         dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n");
1656                         }
1657                 }
1658         }
1659
1660         psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE;
1661         psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1662
1663         if (!psp->ras_context.context.mem_context.shared_buf) {
1664                 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context);
1665                 if (ret)
1666                         return ret;
1667         }
1668
1669         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1670         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1671
1672         if (amdgpu_ras_is_poison_mode_supported(adev))
1673                 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1;
1674         if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu)
1675                 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1;
1676         ras_cmd->ras_in_message.init_flags.xcc_mask =
1677                 adev->gfx.xcc_mask;
1678         ras_cmd->ras_in_message.init_flags.channel_dis_num = hweight32(adev->gmc.m_half_use) * 2;
1679
1680         ret = psp_ta_load(psp, &psp->ras_context.context);
1681
1682         if (!ret && !ras_cmd->ras_status)
1683                 psp->ras_context.context.initialized = true;
1684         else {
1685                 if (ras_cmd->ras_status)
1686                         dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status);
1687
1688                 /* fail to load RAS TA */
1689                 psp->ras_context.context.initialized = false;
1690         }
1691
1692         return ret;
1693 }
1694
1695 int psp_ras_trigger_error(struct psp_context *psp,
1696                           struct ta_ras_trigger_error_input *info, uint32_t instance_mask)
1697 {
1698         struct ta_ras_shared_memory *ras_cmd;
1699         struct amdgpu_device *adev = psp->adev;
1700         int ret;
1701         uint32_t dev_mask;
1702
1703         if (!psp->ras_context.context.initialized)
1704                 return -EINVAL;
1705
1706         switch (info->block_id) {
1707         case TA_RAS_BLOCK__GFX:
1708                 dev_mask = GET_MASK(GC, instance_mask);
1709                 break;
1710         case TA_RAS_BLOCK__SDMA:
1711                 dev_mask = GET_MASK(SDMA0, instance_mask);
1712                 break;
1713         case TA_RAS_BLOCK__VCN:
1714         case TA_RAS_BLOCK__JPEG:
1715                 dev_mask = GET_MASK(VCN, instance_mask);
1716                 break;
1717         default:
1718                 dev_mask = instance_mask;
1719                 break;
1720         }
1721
1722         /* reuse sub_block_index for backward compatibility */
1723         dev_mask <<= AMDGPU_RAS_INST_SHIFT;
1724         dev_mask &= AMDGPU_RAS_INST_MASK;
1725         info->sub_block_index |= dev_mask;
1726
1727         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1728         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1729
1730         ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
1731         ras_cmd->ras_in_message.trigger_error = *info;
1732
1733         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1734         if (ret)
1735                 return -EINVAL;
1736
1737         /* If err_event_athub occurs error inject was successful, however
1738          *  return status from TA is no long reliable
1739          */
1740         if (amdgpu_ras_intr_triggered())
1741                 return 0;
1742
1743         if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED)
1744                 return -EACCES;
1745         else if (ras_cmd->ras_status)
1746                 return -EINVAL;
1747
1748         return 0;
1749 }
1750 // ras end
1751
1752 // HDCP start
1753 static int psp_hdcp_initialize(struct psp_context *psp)
1754 {
1755         int ret;
1756
1757         /*
1758          * TODO: bypass the initialize in sriov for now
1759          */
1760         if (amdgpu_sriov_vf(psp->adev))
1761                 return 0;
1762
1763         if (!psp->hdcp_context.context.bin_desc.size_bytes ||
1764             !psp->hdcp_context.context.bin_desc.start_addr) {
1765                 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");
1766                 return 0;
1767         }
1768
1769         psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE;
1770         psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1771
1772         if (!psp->hdcp_context.context.mem_context.shared_buf) {
1773                 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context);
1774                 if (ret)
1775                         return ret;
1776         }
1777
1778         ret = psp_ta_load(psp, &psp->hdcp_context.context);
1779         if (!ret) {
1780                 psp->hdcp_context.context.initialized = true;
1781                 mutex_init(&psp->hdcp_context.mutex);
1782         }
1783
1784         return ret;
1785 }
1786
1787 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1788 {
1789         /*
1790          * TODO: bypass the loading in sriov for now
1791          */
1792         if (amdgpu_sriov_vf(psp->adev))
1793                 return 0;
1794
1795         return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context);
1796 }
1797
1798 static int psp_hdcp_terminate(struct psp_context *psp)
1799 {
1800         int ret;
1801
1802         /*
1803          * TODO: bypass the terminate in sriov for now
1804          */
1805         if (amdgpu_sriov_vf(psp->adev))
1806                 return 0;
1807
1808         if (!psp->hdcp_context.context.initialized)
1809                 return 0;
1810
1811         ret = psp_ta_unload(psp, &psp->hdcp_context.context);
1812
1813         psp->hdcp_context.context.initialized = false;
1814
1815         return ret;
1816 }
1817 // HDCP end
1818
1819 // DTM start
1820 static int psp_dtm_initialize(struct psp_context *psp)
1821 {
1822         int ret;
1823
1824         /*
1825          * TODO: bypass the initialize in sriov for now
1826          */
1827         if (amdgpu_sriov_vf(psp->adev))
1828                 return 0;
1829
1830         if (!psp->dtm_context.context.bin_desc.size_bytes ||
1831             !psp->dtm_context.context.bin_desc.start_addr) {
1832                 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");
1833                 return 0;
1834         }
1835
1836         psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE;
1837         psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1838
1839         if (!psp->dtm_context.context.mem_context.shared_buf) {
1840                 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context);
1841                 if (ret)
1842                         return ret;
1843         }
1844
1845         ret = psp_ta_load(psp, &psp->dtm_context.context);
1846         if (!ret) {
1847                 psp->dtm_context.context.initialized = true;
1848                 mutex_init(&psp->dtm_context.mutex);
1849         }
1850
1851         return ret;
1852 }
1853
1854 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1855 {
1856         /*
1857          * TODO: bypass the loading in sriov for now
1858          */
1859         if (amdgpu_sriov_vf(psp->adev))
1860                 return 0;
1861
1862         return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context);
1863 }
1864
1865 static int psp_dtm_terminate(struct psp_context *psp)
1866 {
1867         int ret;
1868
1869         /*
1870          * TODO: bypass the terminate in sriov for now
1871          */
1872         if (amdgpu_sriov_vf(psp->adev))
1873                 return 0;
1874
1875         if (!psp->dtm_context.context.initialized)
1876                 return 0;
1877
1878         ret = psp_ta_unload(psp, &psp->dtm_context.context);
1879
1880         psp->dtm_context.context.initialized = false;
1881
1882         return ret;
1883 }
1884 // DTM end
1885
1886 // RAP start
1887 static int psp_rap_initialize(struct psp_context *psp)
1888 {
1889         int ret;
1890         enum ta_rap_status status = TA_RAP_STATUS__SUCCESS;
1891
1892         /*
1893          * TODO: bypass the initialize in sriov for now
1894          */
1895         if (amdgpu_sriov_vf(psp->adev))
1896                 return 0;
1897
1898         if (!psp->rap_context.context.bin_desc.size_bytes ||
1899             !psp->rap_context.context.bin_desc.start_addr) {
1900                 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n");
1901                 return 0;
1902         }
1903
1904         psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE;
1905         psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1906
1907         if (!psp->rap_context.context.mem_context.shared_buf) {
1908                 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context);
1909                 if (ret)
1910                         return ret;
1911         }
1912
1913         ret = psp_ta_load(psp, &psp->rap_context.context);
1914         if (!ret) {
1915                 psp->rap_context.context.initialized = true;
1916                 mutex_init(&psp->rap_context.mutex);
1917         } else
1918                 return ret;
1919
1920         ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status);
1921         if (ret || status != TA_RAP_STATUS__SUCCESS) {
1922                 psp_rap_terminate(psp);
1923                 /* free rap shared memory */
1924                 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
1925
1926                 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n",
1927                          ret, status);
1928
1929                 return ret;
1930         }
1931
1932         return 0;
1933 }
1934
1935 static int psp_rap_terminate(struct psp_context *psp)
1936 {
1937         int ret;
1938
1939         if (!psp->rap_context.context.initialized)
1940                 return 0;
1941
1942         ret = psp_ta_unload(psp, &psp->rap_context.context);
1943
1944         psp->rap_context.context.initialized = false;
1945
1946         return ret;
1947 }
1948
1949 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status)
1950 {
1951         struct ta_rap_shared_memory *rap_cmd;
1952         int ret = 0;
1953
1954         if (!psp->rap_context.context.initialized)
1955                 return 0;
1956
1957         if (ta_cmd_id != TA_CMD_RAP__INITIALIZE &&
1958             ta_cmd_id != TA_CMD_RAP__VALIDATE_L0)
1959                 return -EINVAL;
1960
1961         mutex_lock(&psp->rap_context.mutex);
1962
1963         rap_cmd = (struct ta_rap_shared_memory *)
1964                   psp->rap_context.context.mem_context.shared_buf;
1965         memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory));
1966
1967         rap_cmd->cmd_id = ta_cmd_id;
1968         rap_cmd->validation_method_id = METHOD_A;
1969
1970         ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context);
1971         if (ret)
1972                 goto out_unlock;
1973
1974         if (status)
1975                 *status = rap_cmd->rap_status;
1976
1977 out_unlock:
1978         mutex_unlock(&psp->rap_context.mutex);
1979
1980         return ret;
1981 }
1982 // RAP end
1983
1984 /* securedisplay start */
1985 static int psp_securedisplay_initialize(struct psp_context *psp)
1986 {
1987         int ret;
1988         struct ta_securedisplay_cmd *securedisplay_cmd;
1989
1990         /*
1991          * TODO: bypass the initialize in sriov for now
1992          */
1993         if (amdgpu_sriov_vf(psp->adev))
1994                 return 0;
1995
1996         if (!psp->securedisplay_context.context.bin_desc.size_bytes ||
1997             !psp->securedisplay_context.context.bin_desc.start_addr) {
1998                 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n");
1999                 return 0;
2000         }
2001
2002         psp->securedisplay_context.context.mem_context.shared_mem_size =
2003                 PSP_SECUREDISPLAY_SHARED_MEM_SIZE;
2004         psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
2005
2006         if (!psp->securedisplay_context.context.initialized) {
2007                 ret = psp_ta_init_shared_buf(psp,
2008                                              &psp->securedisplay_context.context.mem_context);
2009                 if (ret)
2010                         return ret;
2011         }
2012
2013         ret = psp_ta_load(psp, &psp->securedisplay_context.context);
2014         if (!ret) {
2015                 psp->securedisplay_context.context.initialized = true;
2016                 mutex_init(&psp->securedisplay_context.mutex);
2017         } else
2018                 return ret;
2019
2020         mutex_lock(&psp->securedisplay_context.mutex);
2021
2022         psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
2023                         TA_SECUREDISPLAY_COMMAND__QUERY_TA);
2024
2025         ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA);
2026
2027         mutex_unlock(&psp->securedisplay_context.mutex);
2028
2029         if (ret) {
2030                 psp_securedisplay_terminate(psp);
2031                 /* free securedisplay shared memory */
2032                 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
2033                 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n");
2034                 return -EINVAL;
2035         }
2036
2037         if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) {
2038                 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
2039                 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n",
2040                         securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret);
2041                 /* don't try again */
2042                 psp->securedisplay_context.context.bin_desc.size_bytes = 0;
2043         }
2044
2045         return 0;
2046 }
2047
2048 static int psp_securedisplay_terminate(struct psp_context *psp)
2049 {
2050         int ret;
2051
2052         /*
2053          * TODO:bypass the terminate in sriov for now
2054          */
2055         if (amdgpu_sriov_vf(psp->adev))
2056                 return 0;
2057
2058         if (!psp->securedisplay_context.context.initialized)
2059                 return 0;
2060
2061         ret = psp_ta_unload(psp, &psp->securedisplay_context.context);
2062
2063         psp->securedisplay_context.context.initialized = false;
2064
2065         return ret;
2066 }
2067
2068 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
2069 {
2070         int ret;
2071
2072         if (!psp->securedisplay_context.context.initialized)
2073                 return -EINVAL;
2074
2075         if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA &&
2076             ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC)
2077                 return -EINVAL;
2078
2079         ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context);
2080
2081         return ret;
2082 }
2083 /* SECUREDISPLAY end */
2084
2085 int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev)
2086 {
2087         struct psp_context *psp = &adev->psp;
2088         int ret = 0;
2089
2090         if (!amdgpu_sriov_vf(adev) && psp->funcs && psp->funcs->wait_for_bootloader != NULL)
2091                 ret = psp->funcs->wait_for_bootloader(psp);
2092
2093         return ret;
2094 }
2095
2096 static int psp_hw_start(struct psp_context *psp)
2097 {
2098         struct amdgpu_device *adev = psp->adev;
2099         int ret;
2100
2101         if (!amdgpu_sriov_vf(adev)) {
2102                 if ((is_psp_fw_valid(psp->kdb)) &&
2103                     (psp->funcs->bootloader_load_kdb != NULL)) {
2104                         ret = psp_bootloader_load_kdb(psp);
2105                         if (ret) {
2106                                 DRM_ERROR("PSP load kdb failed!\n");
2107                                 return ret;
2108                         }
2109                 }
2110
2111                 if ((is_psp_fw_valid(psp->spl)) &&
2112                     (psp->funcs->bootloader_load_spl != NULL)) {
2113                         ret = psp_bootloader_load_spl(psp);
2114                         if (ret) {
2115                                 DRM_ERROR("PSP load spl failed!\n");
2116                                 return ret;
2117                         }
2118                 }
2119
2120                 if ((is_psp_fw_valid(psp->sys)) &&
2121                     (psp->funcs->bootloader_load_sysdrv != NULL)) {
2122                         ret = psp_bootloader_load_sysdrv(psp);
2123                         if (ret) {
2124                                 DRM_ERROR("PSP load sys drv failed!\n");
2125                                 return ret;
2126                         }
2127                 }
2128
2129                 if ((is_psp_fw_valid(psp->soc_drv)) &&
2130                     (psp->funcs->bootloader_load_soc_drv != NULL)) {
2131                         ret = psp_bootloader_load_soc_drv(psp);
2132                         if (ret) {
2133                                 DRM_ERROR("PSP load soc drv failed!\n");
2134                                 return ret;
2135                         }
2136                 }
2137
2138                 if ((is_psp_fw_valid(psp->intf_drv)) &&
2139                     (psp->funcs->bootloader_load_intf_drv != NULL)) {
2140                         ret = psp_bootloader_load_intf_drv(psp);
2141                         if (ret) {
2142                                 DRM_ERROR("PSP load intf drv failed!\n");
2143                                 return ret;
2144                         }
2145                 }
2146
2147                 if ((is_psp_fw_valid(psp->dbg_drv)) &&
2148                     (psp->funcs->bootloader_load_dbg_drv != NULL)) {
2149                         ret = psp_bootloader_load_dbg_drv(psp);
2150                         if (ret) {
2151                                 DRM_ERROR("PSP load dbg drv failed!\n");
2152                                 return ret;
2153                         }
2154                 }
2155
2156                 if ((is_psp_fw_valid(psp->ras_drv)) &&
2157                     (psp->funcs->bootloader_load_ras_drv != NULL)) {
2158                         ret = psp_bootloader_load_ras_drv(psp);
2159                         if (ret) {
2160                                 DRM_ERROR("PSP load ras_drv failed!\n");
2161                                 return ret;
2162                         }
2163                 }
2164
2165                 if ((is_psp_fw_valid(psp->sos)) &&
2166                     (psp->funcs->bootloader_load_sos != NULL)) {
2167                         ret = psp_bootloader_load_sos(psp);
2168                         if (ret) {
2169                                 DRM_ERROR("PSP load sos failed!\n");
2170                                 return ret;
2171                         }
2172                 }
2173         }
2174
2175         ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
2176         if (ret) {
2177                 DRM_ERROR("PSP create ring failed!\n");
2178                 return ret;
2179         }
2180
2181         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
2182                 goto skip_pin_bo;
2183
2184         if (!psp_boottime_tmr(psp)) {
2185                 ret = psp_tmr_init(psp);
2186                 if (ret) {
2187                         DRM_ERROR("PSP tmr init failed!\n");
2188                         return ret;
2189                 }
2190         }
2191
2192 skip_pin_bo:
2193         /*
2194          * For ASICs with DF Cstate management centralized
2195          * to PMFW, TMR setup should be performed after PMFW
2196          * loaded and before other non-psp firmware loaded.
2197          */
2198         if (psp->pmfw_centralized_cstate_management) {
2199                 ret = psp_load_smu_fw(psp);
2200                 if (ret)
2201                         return ret;
2202         }
2203
2204         ret = psp_tmr_load(psp);
2205         if (ret) {
2206                 DRM_ERROR("PSP load tmr failed!\n");
2207                 return ret;
2208         }
2209
2210         return 0;
2211 }
2212
2213 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
2214                            enum psp_gfx_fw_type *type)
2215 {
2216         switch (ucode->ucode_id) {
2217         case AMDGPU_UCODE_ID_CAP:
2218                 *type = GFX_FW_TYPE_CAP;
2219                 break;
2220         case AMDGPU_UCODE_ID_SDMA0:
2221                 *type = GFX_FW_TYPE_SDMA0;
2222                 break;
2223         case AMDGPU_UCODE_ID_SDMA1:
2224                 *type = GFX_FW_TYPE_SDMA1;
2225                 break;
2226         case AMDGPU_UCODE_ID_SDMA2:
2227                 *type = GFX_FW_TYPE_SDMA2;
2228                 break;
2229         case AMDGPU_UCODE_ID_SDMA3:
2230                 *type = GFX_FW_TYPE_SDMA3;
2231                 break;
2232         case AMDGPU_UCODE_ID_SDMA4:
2233                 *type = GFX_FW_TYPE_SDMA4;
2234                 break;
2235         case AMDGPU_UCODE_ID_SDMA5:
2236                 *type = GFX_FW_TYPE_SDMA5;
2237                 break;
2238         case AMDGPU_UCODE_ID_SDMA6:
2239                 *type = GFX_FW_TYPE_SDMA6;
2240                 break;
2241         case AMDGPU_UCODE_ID_SDMA7:
2242                 *type = GFX_FW_TYPE_SDMA7;
2243                 break;
2244         case AMDGPU_UCODE_ID_CP_MES:
2245                 *type = GFX_FW_TYPE_CP_MES;
2246                 break;
2247         case AMDGPU_UCODE_ID_CP_MES_DATA:
2248                 *type = GFX_FW_TYPE_MES_STACK;
2249                 break;
2250         case AMDGPU_UCODE_ID_CP_MES1:
2251                 *type = GFX_FW_TYPE_CP_MES_KIQ;
2252                 break;
2253         case AMDGPU_UCODE_ID_CP_MES1_DATA:
2254                 *type = GFX_FW_TYPE_MES_KIQ_STACK;
2255                 break;
2256         case AMDGPU_UCODE_ID_CP_CE:
2257                 *type = GFX_FW_TYPE_CP_CE;
2258                 break;
2259         case AMDGPU_UCODE_ID_CP_PFP:
2260                 *type = GFX_FW_TYPE_CP_PFP;
2261                 break;
2262         case AMDGPU_UCODE_ID_CP_ME:
2263                 *type = GFX_FW_TYPE_CP_ME;
2264                 break;
2265         case AMDGPU_UCODE_ID_CP_MEC1:
2266                 *type = GFX_FW_TYPE_CP_MEC;
2267                 break;
2268         case AMDGPU_UCODE_ID_CP_MEC1_JT:
2269                 *type = GFX_FW_TYPE_CP_MEC_ME1;
2270                 break;
2271         case AMDGPU_UCODE_ID_CP_MEC2:
2272                 *type = GFX_FW_TYPE_CP_MEC;
2273                 break;
2274         case AMDGPU_UCODE_ID_CP_MEC2_JT:
2275                 *type = GFX_FW_TYPE_CP_MEC_ME2;
2276                 break;
2277         case AMDGPU_UCODE_ID_RLC_P:
2278                 *type = GFX_FW_TYPE_RLC_P;
2279                 break;
2280         case AMDGPU_UCODE_ID_RLC_V:
2281                 *type = GFX_FW_TYPE_RLC_V;
2282                 break;
2283         case AMDGPU_UCODE_ID_RLC_G:
2284                 *type = GFX_FW_TYPE_RLC_G;
2285                 break;
2286         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
2287                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
2288                 break;
2289         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
2290                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
2291                 break;
2292         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
2293                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
2294                 break;
2295         case AMDGPU_UCODE_ID_RLC_IRAM:
2296                 *type = GFX_FW_TYPE_RLC_IRAM;
2297                 break;
2298         case AMDGPU_UCODE_ID_RLC_DRAM:
2299                 *type = GFX_FW_TYPE_RLC_DRAM_BOOT;
2300                 break;
2301         case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
2302                 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS;
2303                 break;
2304         case AMDGPU_UCODE_ID_SE0_TAP_DELAYS:
2305                 *type = GFX_FW_TYPE_SE0_TAP_DELAYS;
2306                 break;
2307         case AMDGPU_UCODE_ID_SE1_TAP_DELAYS:
2308                 *type = GFX_FW_TYPE_SE1_TAP_DELAYS;
2309                 break;
2310         case AMDGPU_UCODE_ID_SE2_TAP_DELAYS:
2311                 *type = GFX_FW_TYPE_SE2_TAP_DELAYS;
2312                 break;
2313         case AMDGPU_UCODE_ID_SE3_TAP_DELAYS:
2314                 *type = GFX_FW_TYPE_SE3_TAP_DELAYS;
2315                 break;
2316         case AMDGPU_UCODE_ID_SMC:
2317                 *type = GFX_FW_TYPE_SMU;
2318                 break;
2319         case AMDGPU_UCODE_ID_PPTABLE:
2320                 *type = GFX_FW_TYPE_PPTABLE;
2321                 break;
2322         case AMDGPU_UCODE_ID_UVD:
2323                 *type = GFX_FW_TYPE_UVD;
2324                 break;
2325         case AMDGPU_UCODE_ID_UVD1:
2326                 *type = GFX_FW_TYPE_UVD1;
2327                 break;
2328         case AMDGPU_UCODE_ID_VCE:
2329                 *type = GFX_FW_TYPE_VCE;
2330                 break;
2331         case AMDGPU_UCODE_ID_VCN:
2332                 *type = GFX_FW_TYPE_VCN;
2333                 break;
2334         case AMDGPU_UCODE_ID_VCN1:
2335                 *type = GFX_FW_TYPE_VCN1;
2336                 break;
2337         case AMDGPU_UCODE_ID_DMCU_ERAM:
2338                 *type = GFX_FW_TYPE_DMCU_ERAM;
2339                 break;
2340         case AMDGPU_UCODE_ID_DMCU_INTV:
2341                 *type = GFX_FW_TYPE_DMCU_ISR;
2342                 break;
2343         case AMDGPU_UCODE_ID_VCN0_RAM:
2344                 *type = GFX_FW_TYPE_VCN0_RAM;
2345                 break;
2346         case AMDGPU_UCODE_ID_VCN1_RAM:
2347                 *type = GFX_FW_TYPE_VCN1_RAM;
2348                 break;
2349         case AMDGPU_UCODE_ID_DMCUB:
2350                 *type = GFX_FW_TYPE_DMUB;
2351                 break;
2352         case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
2353                 *type = GFX_FW_TYPE_SDMA_UCODE_TH0;
2354                 break;
2355         case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
2356                 *type = GFX_FW_TYPE_SDMA_UCODE_TH1;
2357                 break;
2358         case AMDGPU_UCODE_ID_IMU_I:
2359                 *type = GFX_FW_TYPE_IMU_I;
2360                 break;
2361         case AMDGPU_UCODE_ID_IMU_D:
2362                 *type = GFX_FW_TYPE_IMU_D;
2363                 break;
2364         case AMDGPU_UCODE_ID_CP_RS64_PFP:
2365                 *type = GFX_FW_TYPE_RS64_PFP;
2366                 break;
2367         case AMDGPU_UCODE_ID_CP_RS64_ME:
2368                 *type = GFX_FW_TYPE_RS64_ME;
2369                 break;
2370         case AMDGPU_UCODE_ID_CP_RS64_MEC:
2371                 *type = GFX_FW_TYPE_RS64_MEC;
2372                 break;
2373         case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
2374                 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK;
2375                 break;
2376         case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
2377                 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK;
2378                 break;
2379         case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
2380                 *type = GFX_FW_TYPE_RS64_ME_P0_STACK;
2381                 break;
2382         case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
2383                 *type = GFX_FW_TYPE_RS64_ME_P1_STACK;
2384                 break;
2385         case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
2386                 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK;
2387                 break;
2388         case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
2389                 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK;
2390                 break;
2391         case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
2392                 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK;
2393                 break;
2394         case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
2395                 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK;
2396                 break;
2397         case AMDGPU_UCODE_ID_VPE_CTX:
2398                 *type = GFX_FW_TYPE_VPEC_FW1;
2399                 break;
2400         case AMDGPU_UCODE_ID_VPE_CTL:
2401                 *type = GFX_FW_TYPE_VPEC_FW2;
2402                 break;
2403         case AMDGPU_UCODE_ID_VPE:
2404                 *type = GFX_FW_TYPE_VPE;
2405                 break;
2406         case AMDGPU_UCODE_ID_UMSCH_MM_UCODE:
2407                 *type = GFX_FW_TYPE_UMSCH_UCODE;
2408                 break;
2409         case AMDGPU_UCODE_ID_UMSCH_MM_DATA:
2410                 *type = GFX_FW_TYPE_UMSCH_DATA;
2411                 break;
2412         case AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER:
2413                 *type = GFX_FW_TYPE_UMSCH_CMD_BUFFER;
2414                 break;
2415         case AMDGPU_UCODE_ID_MAXIMUM:
2416         default:
2417                 return -EINVAL;
2418         }
2419
2420         return 0;
2421 }
2422
2423 static void psp_print_fw_hdr(struct psp_context *psp,
2424                              struct amdgpu_firmware_info *ucode)
2425 {
2426         struct amdgpu_device *adev = psp->adev;
2427         struct common_firmware_header *hdr;
2428
2429         switch (ucode->ucode_id) {
2430         case AMDGPU_UCODE_ID_SDMA0:
2431         case AMDGPU_UCODE_ID_SDMA1:
2432         case AMDGPU_UCODE_ID_SDMA2:
2433         case AMDGPU_UCODE_ID_SDMA3:
2434         case AMDGPU_UCODE_ID_SDMA4:
2435         case AMDGPU_UCODE_ID_SDMA5:
2436         case AMDGPU_UCODE_ID_SDMA6:
2437         case AMDGPU_UCODE_ID_SDMA7:
2438                 hdr = (struct common_firmware_header *)
2439                         adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
2440                 amdgpu_ucode_print_sdma_hdr(hdr);
2441                 break;
2442         case AMDGPU_UCODE_ID_CP_CE:
2443                 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
2444                 amdgpu_ucode_print_gfx_hdr(hdr);
2445                 break;
2446         case AMDGPU_UCODE_ID_CP_PFP:
2447                 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
2448                 amdgpu_ucode_print_gfx_hdr(hdr);
2449                 break;
2450         case AMDGPU_UCODE_ID_CP_ME:
2451                 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
2452                 amdgpu_ucode_print_gfx_hdr(hdr);
2453                 break;
2454         case AMDGPU_UCODE_ID_CP_MEC1:
2455                 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
2456                 amdgpu_ucode_print_gfx_hdr(hdr);
2457                 break;
2458         case AMDGPU_UCODE_ID_RLC_G:
2459                 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
2460                 amdgpu_ucode_print_rlc_hdr(hdr);
2461                 break;
2462         case AMDGPU_UCODE_ID_SMC:
2463                 hdr = (struct common_firmware_header *)adev->pm.fw->data;
2464                 amdgpu_ucode_print_smc_hdr(hdr);
2465                 break;
2466         default:
2467                 break;
2468         }
2469 }
2470
2471 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
2472                                        struct psp_gfx_cmd_resp *cmd)
2473 {
2474         int ret;
2475         uint64_t fw_mem_mc_addr = ucode->mc_addr;
2476
2477         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
2478         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
2479         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
2480         cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
2481
2482         ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
2483         if (ret)
2484                 DRM_ERROR("Unknown firmware type\n");
2485
2486         return ret;
2487 }
2488
2489 int psp_execute_ip_fw_load(struct psp_context *psp,
2490                            struct amdgpu_firmware_info *ucode)
2491 {
2492         int ret = 0;
2493         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2494
2495         ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd);
2496         if (!ret) {
2497                 ret = psp_cmd_submit_buf(psp, ucode, cmd,
2498                                          psp->fence_buf_mc_addr);
2499         }
2500
2501         release_psp_cmd_buf(psp);
2502
2503         return ret;
2504 }
2505
2506 static int psp_load_smu_fw(struct psp_context *psp)
2507 {
2508         int ret;
2509         struct amdgpu_device *adev = psp->adev;
2510         struct amdgpu_firmware_info *ucode =
2511                         &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
2512         struct amdgpu_ras *ras = psp->ras_context.ras;
2513
2514         /*
2515          * Skip SMU FW reloading in case of using BACO for runpm only,
2516          * as SMU is always alive.
2517          */
2518         if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO))
2519                 return 0;
2520
2521         if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
2522                 return 0;
2523
2524         if ((amdgpu_in_reset(adev) && ras && adev->ras_enabled &&
2525              (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) ||
2526               amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 2)))) {
2527                 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
2528                 if (ret)
2529                         DRM_WARN("Failed to set MP1 state prepare for reload\n");
2530         }
2531
2532         ret = psp_execute_ip_fw_load(psp, ucode);
2533
2534         if (ret)
2535                 DRM_ERROR("PSP load smu failed!\n");
2536
2537         return ret;
2538 }
2539
2540 static bool fw_load_skip_check(struct psp_context *psp,
2541                                struct amdgpu_firmware_info *ucode)
2542 {
2543         if (!ucode->fw || !ucode->ucode_size)
2544                 return true;
2545
2546         if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2547             (psp_smu_reload_quirk(psp) ||
2548              psp->autoload_supported ||
2549              psp->pmfw_centralized_cstate_management))
2550                 return true;
2551
2552         if (amdgpu_sriov_vf(psp->adev) &&
2553             amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id))
2554                 return true;
2555
2556         if (psp->autoload_supported &&
2557             (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
2558              ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
2559                 /* skip mec JT when autoload is enabled */
2560                 return true;
2561
2562         return false;
2563 }
2564
2565 int psp_load_fw_list(struct psp_context *psp,
2566                      struct amdgpu_firmware_info **ucode_list, int ucode_count)
2567 {
2568         int ret = 0, i;
2569         struct amdgpu_firmware_info *ucode;
2570
2571         for (i = 0; i < ucode_count; ++i) {
2572                 ucode = ucode_list[i];
2573                 psp_print_fw_hdr(psp, ucode);
2574                 ret = psp_execute_ip_fw_load(psp, ucode);
2575                 if (ret)
2576                         return ret;
2577         }
2578         return ret;
2579 }
2580
2581 static int psp_load_non_psp_fw(struct psp_context *psp)
2582 {
2583         int i, ret;
2584         struct amdgpu_firmware_info *ucode;
2585         struct amdgpu_device *adev = psp->adev;
2586
2587         if (psp->autoload_supported &&
2588             !psp->pmfw_centralized_cstate_management) {
2589                 ret = psp_load_smu_fw(psp);
2590                 if (ret)
2591                         return ret;
2592         }
2593
2594         for (i = 0; i < adev->firmware.max_ucodes; i++) {
2595                 ucode = &adev->firmware.ucode[i];
2596
2597                 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2598                     !fw_load_skip_check(psp, ucode)) {
2599                         ret = psp_load_smu_fw(psp);
2600                         if (ret)
2601                                 return ret;
2602                         continue;
2603                 }
2604
2605                 if (fw_load_skip_check(psp, ucode))
2606                         continue;
2607
2608                 if (psp->autoload_supported &&
2609                     (amdgpu_ip_version(adev, MP0_HWIP, 0) ==
2610                              IP_VERSION(11, 0, 7) ||
2611                      amdgpu_ip_version(adev, MP0_HWIP, 0) ==
2612                              IP_VERSION(11, 0, 11) ||
2613                      amdgpu_ip_version(adev, MP0_HWIP, 0) ==
2614                              IP_VERSION(11, 0, 12)) &&
2615                     (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
2616                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
2617                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
2618                         /* PSP only receive one SDMA fw for sienna_cichlid,
2619                          * as all four sdma fw are same
2620                          */
2621                         continue;
2622
2623                 psp_print_fw_hdr(psp, ucode);
2624
2625                 ret = psp_execute_ip_fw_load(psp, ucode);
2626                 if (ret)
2627                         return ret;
2628
2629                 /* Start rlc autoload after psp recieved all the gfx firmware */
2630                 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
2631                     adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) {
2632                         ret = psp_rlc_autoload_start(psp);
2633                         if (ret) {
2634                                 DRM_ERROR("Failed to start rlc autoload\n");
2635                                 return ret;
2636                         }
2637                 }
2638         }
2639
2640         return 0;
2641 }
2642
2643 static int psp_load_fw(struct amdgpu_device *adev)
2644 {
2645         int ret;
2646         struct psp_context *psp = &adev->psp;
2647
2648         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2649                 /* should not destroy ring, only stop */
2650                 psp_ring_stop(psp, PSP_RING_TYPE__KM);
2651         } else {
2652                 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
2653
2654                 ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
2655                 if (ret) {
2656                         DRM_ERROR("PSP ring init failed!\n");
2657                         goto failed;
2658                 }
2659         }
2660
2661         ret = psp_hw_start(psp);
2662         if (ret)
2663                 goto failed;
2664
2665         ret = psp_load_non_psp_fw(psp);
2666         if (ret)
2667                 goto failed1;
2668
2669         ret = psp_asd_initialize(psp);
2670         if (ret) {
2671                 DRM_ERROR("PSP load asd failed!\n");
2672                 goto failed1;
2673         }
2674
2675         ret = psp_rl_load(adev);
2676         if (ret) {
2677                 DRM_ERROR("PSP load RL failed!\n");
2678                 goto failed1;
2679         }
2680
2681         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2682                 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2683                         ret = psp_xgmi_initialize(psp, false, true);
2684                         /* Warning the XGMI seesion initialize failure
2685                          * Instead of stop driver initialization
2686                          */
2687                         if (ret)
2688                                 dev_err(psp->adev->dev,
2689                                         "XGMI: Failed to initialize XGMI session\n");
2690                 }
2691         }
2692
2693         if (psp->ta_fw) {
2694                 ret = psp_ras_initialize(psp);
2695                 if (ret)
2696                         dev_err(psp->adev->dev,
2697                                         "RAS: Failed to initialize RAS\n");
2698
2699                 ret = psp_hdcp_initialize(psp);
2700                 if (ret)
2701                         dev_err(psp->adev->dev,
2702                                 "HDCP: Failed to initialize HDCP\n");
2703
2704                 ret = psp_dtm_initialize(psp);
2705                 if (ret)
2706                         dev_err(psp->adev->dev,
2707                                 "DTM: Failed to initialize DTM\n");
2708
2709                 ret = psp_rap_initialize(psp);
2710                 if (ret)
2711                         dev_err(psp->adev->dev,
2712                                 "RAP: Failed to initialize RAP\n");
2713
2714                 ret = psp_securedisplay_initialize(psp);
2715                 if (ret)
2716                         dev_err(psp->adev->dev,
2717                                 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2718         }
2719
2720         return 0;
2721
2722 failed1:
2723         psp_free_shared_bufs(psp);
2724 failed:
2725         /*
2726          * all cleanup jobs (xgmi terminate, ras terminate,
2727          * ring destroy, cmd/fence/fw buffers destory,
2728          * psp->cmd destory) are delayed to psp_hw_fini
2729          */
2730         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2731         return ret;
2732 }
2733
2734 static int psp_hw_init(void *handle)
2735 {
2736         int ret;
2737         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2738
2739         mutex_lock(&adev->firmware.mutex);
2740         /*
2741          * This sequence is just used on hw_init only once, no need on
2742          * resume.
2743          */
2744         ret = amdgpu_ucode_init_bo(adev);
2745         if (ret)
2746                 goto failed;
2747
2748         ret = psp_load_fw(adev);
2749         if (ret) {
2750                 DRM_ERROR("PSP firmware loading failed\n");
2751                 goto failed;
2752         }
2753
2754         mutex_unlock(&adev->firmware.mutex);
2755         return 0;
2756
2757 failed:
2758         adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
2759         mutex_unlock(&adev->firmware.mutex);
2760         return -EINVAL;
2761 }
2762
2763 static int psp_hw_fini(void *handle)
2764 {
2765         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2766         struct psp_context *psp = &adev->psp;
2767
2768         if (psp->ta_fw) {
2769                 psp_ras_terminate(psp);
2770                 psp_securedisplay_terminate(psp);
2771                 psp_rap_terminate(psp);
2772                 psp_dtm_terminate(psp);
2773                 psp_hdcp_terminate(psp);
2774
2775                 if (adev->gmc.xgmi.num_physical_nodes > 1)
2776                         psp_xgmi_terminate(psp);
2777         }
2778
2779         psp_asd_terminate(psp);
2780         psp_tmr_terminate(psp);
2781
2782         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2783
2784         return 0;
2785 }
2786
2787 static int psp_suspend(void *handle)
2788 {
2789         int ret = 0;
2790         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2791         struct psp_context *psp = &adev->psp;
2792
2793         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
2794             psp->xgmi_context.context.initialized) {
2795                 ret = psp_xgmi_terminate(psp);
2796                 if (ret) {
2797                         DRM_ERROR("Failed to terminate xgmi ta\n");
2798                         goto out;
2799                 }
2800         }
2801
2802         if (psp->ta_fw) {
2803                 ret = psp_ras_terminate(psp);
2804                 if (ret) {
2805                         DRM_ERROR("Failed to terminate ras ta\n");
2806                         goto out;
2807                 }
2808                 ret = psp_hdcp_terminate(psp);
2809                 if (ret) {
2810                         DRM_ERROR("Failed to terminate hdcp ta\n");
2811                         goto out;
2812                 }
2813                 ret = psp_dtm_terminate(psp);
2814                 if (ret) {
2815                         DRM_ERROR("Failed to terminate dtm ta\n");
2816                         goto out;
2817                 }
2818                 ret = psp_rap_terminate(psp);
2819                 if (ret) {
2820                         DRM_ERROR("Failed to terminate rap ta\n");
2821                         goto out;
2822                 }
2823                 ret = psp_securedisplay_terminate(psp);
2824                 if (ret) {
2825                         DRM_ERROR("Failed to terminate securedisplay ta\n");
2826                         goto out;
2827                 }
2828         }
2829
2830         ret = psp_asd_terminate(psp);
2831         if (ret) {
2832                 DRM_ERROR("Failed to terminate asd\n");
2833                 goto out;
2834         }
2835
2836         ret = psp_tmr_terminate(psp);
2837         if (ret) {
2838                 DRM_ERROR("Failed to terminate tmr\n");
2839                 goto out;
2840         }
2841
2842         ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
2843         if (ret)
2844                 DRM_ERROR("PSP ring stop failed\n");
2845
2846 out:
2847         return ret;
2848 }
2849
2850 static int psp_resume(void *handle)
2851 {
2852         int ret;
2853         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2854         struct psp_context *psp = &adev->psp;
2855
2856         DRM_INFO("PSP is resuming...\n");
2857
2858         if (psp->mem_train_ctx.enable_mem_training) {
2859                 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
2860                 if (ret) {
2861                         DRM_ERROR("Failed to process memory training!\n");
2862                         return ret;
2863                 }
2864         }
2865
2866         mutex_lock(&adev->firmware.mutex);
2867
2868         ret = psp_hw_start(psp);
2869         if (ret)
2870                 goto failed;
2871
2872         ret = psp_load_non_psp_fw(psp);
2873         if (ret)
2874                 goto failed;
2875
2876         ret = psp_asd_initialize(psp);
2877         if (ret) {
2878                 DRM_ERROR("PSP load asd failed!\n");
2879                 goto failed;
2880         }
2881
2882         ret = psp_rl_load(adev);
2883         if (ret) {
2884                 dev_err(adev->dev, "PSP load RL failed!\n");
2885                 goto failed;
2886         }
2887
2888         if (adev->gmc.xgmi.num_physical_nodes > 1) {
2889                 ret = psp_xgmi_initialize(psp, false, true);
2890                 /* Warning the XGMI seesion initialize failure
2891                  * Instead of stop driver initialization
2892                  */
2893                 if (ret)
2894                         dev_err(psp->adev->dev,
2895                                 "XGMI: Failed to initialize XGMI session\n");
2896         }
2897
2898         if (psp->ta_fw) {
2899                 ret = psp_ras_initialize(psp);
2900                 if (ret)
2901                         dev_err(psp->adev->dev,
2902                                         "RAS: Failed to initialize RAS\n");
2903
2904                 ret = psp_hdcp_initialize(psp);
2905                 if (ret)
2906                         dev_err(psp->adev->dev,
2907                                 "HDCP: Failed to initialize HDCP\n");
2908
2909                 ret = psp_dtm_initialize(psp);
2910                 if (ret)
2911                         dev_err(psp->adev->dev,
2912                                 "DTM: Failed to initialize DTM\n");
2913
2914                 ret = psp_rap_initialize(psp);
2915                 if (ret)
2916                         dev_err(psp->adev->dev,
2917                                 "RAP: Failed to initialize RAP\n");
2918
2919                 ret = psp_securedisplay_initialize(psp);
2920                 if (ret)
2921                         dev_err(psp->adev->dev,
2922                                 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2923         }
2924
2925         mutex_unlock(&adev->firmware.mutex);
2926
2927         return 0;
2928
2929 failed:
2930         DRM_ERROR("PSP resume failed\n");
2931         mutex_unlock(&adev->firmware.mutex);
2932         return ret;
2933 }
2934
2935 int psp_gpu_reset(struct amdgpu_device *adev)
2936 {
2937         int ret;
2938
2939         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
2940                 return 0;
2941
2942         mutex_lock(&adev->psp.mutex);
2943         ret = psp_mode1_reset(&adev->psp);
2944         mutex_unlock(&adev->psp.mutex);
2945
2946         return ret;
2947 }
2948
2949 int psp_rlc_autoload_start(struct psp_context *psp)
2950 {
2951         int ret;
2952         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2953
2954         cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
2955
2956         ret = psp_cmd_submit_buf(psp, NULL, cmd,
2957                                  psp->fence_buf_mc_addr);
2958
2959         release_psp_cmd_buf(psp);
2960
2961         return ret;
2962 }
2963
2964 int psp_ring_cmd_submit(struct psp_context *psp,
2965                         uint64_t cmd_buf_mc_addr,
2966                         uint64_t fence_mc_addr,
2967                         int index)
2968 {
2969         unsigned int psp_write_ptr_reg = 0;
2970         struct psp_gfx_rb_frame *write_frame;
2971         struct psp_ring *ring = &psp->km_ring;
2972         struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
2973         struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
2974                 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
2975         struct amdgpu_device *adev = psp->adev;
2976         uint32_t ring_size_dw = ring->ring_size / 4;
2977         uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
2978
2979         /* KM (GPCOM) prepare write pointer */
2980         psp_write_ptr_reg = psp_ring_get_wptr(psp);
2981
2982         /* Update KM RB frame pointer to new frame */
2983         /* write_frame ptr increments by size of rb_frame in bytes */
2984         /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
2985         if ((psp_write_ptr_reg % ring_size_dw) == 0)
2986                 write_frame = ring_buffer_start;
2987         else
2988                 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
2989         /* Check invalid write_frame ptr address */
2990         if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
2991                 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
2992                           ring_buffer_start, ring_buffer_end, write_frame);
2993                 DRM_ERROR("write_frame is pointing to address out of bounds\n");
2994                 return -EINVAL;
2995         }
2996
2997         /* Initialize KM RB frame */
2998         memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
2999
3000         /* Update KM RB frame */
3001         write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
3002         write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
3003         write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
3004         write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
3005         write_frame->fence_value = index;
3006         amdgpu_device_flush_hdp(adev, NULL);
3007
3008         /* Update the write Pointer in DWORDs */
3009         psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
3010         psp_ring_set_wptr(psp, psp_write_ptr_reg);
3011         return 0;
3012 }
3013
3014 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name)
3015 {
3016         struct amdgpu_device *adev = psp->adev;
3017         char fw_name[PSP_FW_NAME_LEN];
3018         const struct psp_firmware_header_v1_0 *asd_hdr;
3019         int err = 0;
3020
3021         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
3022         err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, fw_name);
3023         if (err)
3024                 goto out;
3025
3026         asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
3027         adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
3028         adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version);
3029         adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
3030         adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr +
3031                                 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
3032         return 0;
3033 out:
3034         amdgpu_ucode_release(&adev->psp.asd_fw);
3035         return err;
3036 }
3037
3038 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name)
3039 {
3040         struct amdgpu_device *adev = psp->adev;
3041         char fw_name[PSP_FW_NAME_LEN];
3042         const struct psp_firmware_header_v1_0 *toc_hdr;
3043         int err = 0;
3044
3045         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
3046         err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name);
3047         if (err)
3048                 goto out;
3049
3050         toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
3051         adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
3052         adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
3053         adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
3054         adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
3055                                 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
3056         return 0;
3057 out:
3058         amdgpu_ucode_release(&adev->psp.toc_fw);
3059         return err;
3060 }
3061
3062 static int parse_sos_bin_descriptor(struct psp_context *psp,
3063                                    const struct psp_fw_bin_desc *desc,
3064                                    const struct psp_firmware_header_v2_0 *sos_hdr)
3065 {
3066         uint8_t *ucode_start_addr  = NULL;
3067
3068         if (!psp || !desc || !sos_hdr)
3069                 return -EINVAL;
3070
3071         ucode_start_addr  = (uint8_t *)sos_hdr +
3072                             le32_to_cpu(desc->offset_bytes) +
3073                             le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3074
3075         switch (desc->fw_type) {
3076         case PSP_FW_TYPE_PSP_SOS:
3077                 psp->sos.fw_version        = le32_to_cpu(desc->fw_version);
3078                 psp->sos.feature_version   = le32_to_cpu(desc->fw_version);
3079                 psp->sos.size_bytes        = le32_to_cpu(desc->size_bytes);
3080                 psp->sos.start_addr        = ucode_start_addr;
3081                 break;
3082         case PSP_FW_TYPE_PSP_SYS_DRV:
3083                 psp->sys.fw_version        = le32_to_cpu(desc->fw_version);
3084                 psp->sys.feature_version   = le32_to_cpu(desc->fw_version);
3085                 psp->sys.size_bytes        = le32_to_cpu(desc->size_bytes);
3086                 psp->sys.start_addr        = ucode_start_addr;
3087                 break;
3088         case PSP_FW_TYPE_PSP_KDB:
3089                 psp->kdb.fw_version        = le32_to_cpu(desc->fw_version);
3090                 psp->kdb.feature_version   = le32_to_cpu(desc->fw_version);
3091                 psp->kdb.size_bytes        = le32_to_cpu(desc->size_bytes);
3092                 psp->kdb.start_addr        = ucode_start_addr;
3093                 break;
3094         case PSP_FW_TYPE_PSP_TOC:
3095                 psp->toc.fw_version        = le32_to_cpu(desc->fw_version);
3096                 psp->toc.feature_version   = le32_to_cpu(desc->fw_version);
3097                 psp->toc.size_bytes        = le32_to_cpu(desc->size_bytes);
3098                 psp->toc.start_addr        = ucode_start_addr;
3099                 break;
3100         case PSP_FW_TYPE_PSP_SPL:
3101                 psp->spl.fw_version        = le32_to_cpu(desc->fw_version);
3102                 psp->spl.feature_version   = le32_to_cpu(desc->fw_version);
3103                 psp->spl.size_bytes        = le32_to_cpu(desc->size_bytes);
3104                 psp->spl.start_addr        = ucode_start_addr;
3105                 break;
3106         case PSP_FW_TYPE_PSP_RL:
3107                 psp->rl.fw_version         = le32_to_cpu(desc->fw_version);
3108                 psp->rl.feature_version    = le32_to_cpu(desc->fw_version);
3109                 psp->rl.size_bytes         = le32_to_cpu(desc->size_bytes);
3110                 psp->rl.start_addr         = ucode_start_addr;
3111                 break;
3112         case PSP_FW_TYPE_PSP_SOC_DRV:
3113                 psp->soc_drv.fw_version         = le32_to_cpu(desc->fw_version);
3114                 psp->soc_drv.feature_version    = le32_to_cpu(desc->fw_version);
3115                 psp->soc_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
3116                 psp->soc_drv.start_addr         = ucode_start_addr;
3117                 break;
3118         case PSP_FW_TYPE_PSP_INTF_DRV:
3119                 psp->intf_drv.fw_version        = le32_to_cpu(desc->fw_version);
3120                 psp->intf_drv.feature_version   = le32_to_cpu(desc->fw_version);
3121                 psp->intf_drv.size_bytes        = le32_to_cpu(desc->size_bytes);
3122                 psp->intf_drv.start_addr        = ucode_start_addr;
3123                 break;
3124         case PSP_FW_TYPE_PSP_DBG_DRV:
3125                 psp->dbg_drv.fw_version         = le32_to_cpu(desc->fw_version);
3126                 psp->dbg_drv.feature_version    = le32_to_cpu(desc->fw_version);
3127                 psp->dbg_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
3128                 psp->dbg_drv.start_addr         = ucode_start_addr;
3129                 break;
3130         case PSP_FW_TYPE_PSP_RAS_DRV:
3131                 psp->ras_drv.fw_version         = le32_to_cpu(desc->fw_version);
3132                 psp->ras_drv.feature_version    = le32_to_cpu(desc->fw_version);
3133                 psp->ras_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
3134                 psp->ras_drv.start_addr         = ucode_start_addr;
3135                 break;
3136         default:
3137                 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type);
3138                 break;
3139         }
3140
3141         return 0;
3142 }
3143
3144 static int psp_init_sos_base_fw(struct amdgpu_device *adev)
3145 {
3146         const struct psp_firmware_header_v1_0 *sos_hdr;
3147         const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3148         uint8_t *ucode_array_start_addr;
3149
3150         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3151         ucode_array_start_addr = (uint8_t *)sos_hdr +
3152                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3153
3154         if (adev->gmc.xgmi.connected_to_cpu ||
3155             (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2))) {
3156                 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
3157                 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version);
3158
3159                 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes);
3160                 adev->psp.sys.start_addr = ucode_array_start_addr;
3161
3162                 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes);
3163                 adev->psp.sos.start_addr = ucode_array_start_addr +
3164                                 le32_to_cpu(sos_hdr->sos.offset_bytes);
3165         } else {
3166                 /* Load alternate PSP SOS FW */
3167                 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3168
3169                 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3170                 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3171
3172                 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes);
3173                 adev->psp.sys.start_addr = ucode_array_start_addr +
3174                         le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes);
3175
3176                 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes);
3177                 adev->psp.sos.start_addr = ucode_array_start_addr +
3178                         le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes);
3179         }
3180
3181         if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) {
3182                 dev_warn(adev->dev, "PSP SOS FW not available");
3183                 return -EINVAL;
3184         }
3185
3186         return 0;
3187 }
3188
3189 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name)
3190 {
3191         struct amdgpu_device *adev = psp->adev;
3192         char fw_name[PSP_FW_NAME_LEN];
3193         const struct psp_firmware_header_v1_0 *sos_hdr;
3194         const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
3195         const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
3196         const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3197         const struct psp_firmware_header_v2_0 *sos_hdr_v2_0;
3198         int err = 0;
3199         uint8_t *ucode_array_start_addr;
3200         int fw_index = 0;
3201
3202         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
3203         err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, fw_name);
3204         if (err)
3205                 goto out;
3206
3207         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3208         ucode_array_start_addr = (uint8_t *)sos_hdr +
3209                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3210         amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
3211
3212         switch (sos_hdr->header.header_version_major) {
3213         case 1:
3214                 err = psp_init_sos_base_fw(adev);
3215                 if (err)
3216                         goto out;
3217
3218                 if (sos_hdr->header.header_version_minor == 1) {
3219                         sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
3220                         adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes);
3221                         adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3222                                         le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes);
3223                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes);
3224                         adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3225                                         le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes);
3226                 }
3227                 if (sos_hdr->header.header_version_minor == 2) {
3228                         sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
3229                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes);
3230                         adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3231                                                     le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes);
3232                 }
3233                 if (sos_hdr->header.header_version_minor == 3) {
3234                         sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3235                         adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes);
3236                         adev->psp.toc.start_addr = ucode_array_start_addr +
3237                                 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes);
3238                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes);
3239                         adev->psp.kdb.start_addr = ucode_array_start_addr +
3240                                 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes);
3241                         adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes);
3242                         adev->psp.spl.start_addr = ucode_array_start_addr +
3243                                 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes);
3244                         adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes);
3245                         adev->psp.rl.start_addr = ucode_array_start_addr +
3246                                 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes);
3247                 }
3248                 break;
3249         case 2:
3250                 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data;
3251
3252                 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3253                         dev_err(adev->dev, "packed SOS count exceeds maximum limit\n");
3254                         err = -EINVAL;
3255                         goto out;
3256                 }
3257
3258                 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) {
3259                         err = parse_sos_bin_descriptor(psp,
3260                                                        &sos_hdr_v2_0->psp_fw_bin[fw_index],
3261                                                        sos_hdr_v2_0);
3262                         if (err)
3263                                 goto out;
3264                 }
3265                 break;
3266         default:
3267                 dev_err(adev->dev,
3268                         "unsupported psp sos firmware\n");
3269                 err = -EINVAL;
3270                 goto out;
3271         }
3272
3273         return 0;
3274 out:
3275         amdgpu_ucode_release(&adev->psp.sos_fw);
3276
3277         return err;
3278 }
3279
3280 static int parse_ta_bin_descriptor(struct psp_context *psp,
3281                                    const struct psp_fw_bin_desc *desc,
3282                                    const struct ta_firmware_header_v2_0 *ta_hdr)
3283 {
3284         uint8_t *ucode_start_addr  = NULL;
3285
3286         if (!psp || !desc || !ta_hdr)
3287                 return -EINVAL;
3288
3289         ucode_start_addr  = (uint8_t *)ta_hdr +
3290                             le32_to_cpu(desc->offset_bytes) +
3291                             le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3292
3293         switch (desc->fw_type) {
3294         case TA_FW_TYPE_PSP_ASD:
3295                 psp->asd_context.bin_desc.fw_version        = le32_to_cpu(desc->fw_version);
3296                 psp->asd_context.bin_desc.feature_version   = le32_to_cpu(desc->fw_version);
3297                 psp->asd_context.bin_desc.size_bytes        = le32_to_cpu(desc->size_bytes);
3298                 psp->asd_context.bin_desc.start_addr        = ucode_start_addr;
3299                 break;
3300         case TA_FW_TYPE_PSP_XGMI:
3301                 psp->xgmi_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3302                 psp->xgmi_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3303                 psp->xgmi_context.context.bin_desc.start_addr       = ucode_start_addr;
3304                 break;
3305         case TA_FW_TYPE_PSP_RAS:
3306                 psp->ras_context.context.bin_desc.fw_version        = le32_to_cpu(desc->fw_version);
3307                 psp->ras_context.context.bin_desc.size_bytes        = le32_to_cpu(desc->size_bytes);
3308                 psp->ras_context.context.bin_desc.start_addr        = ucode_start_addr;
3309                 break;
3310         case TA_FW_TYPE_PSP_HDCP:
3311                 psp->hdcp_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3312                 psp->hdcp_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3313                 psp->hdcp_context.context.bin_desc.start_addr       = ucode_start_addr;
3314                 break;
3315         case TA_FW_TYPE_PSP_DTM:
3316                 psp->dtm_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3317                 psp->dtm_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3318                 psp->dtm_context.context.bin_desc.start_addr       = ucode_start_addr;
3319                 break;
3320         case TA_FW_TYPE_PSP_RAP:
3321                 psp->rap_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3322                 psp->rap_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3323                 psp->rap_context.context.bin_desc.start_addr       = ucode_start_addr;
3324                 break;
3325         case TA_FW_TYPE_PSP_SECUREDISPLAY:
3326                 psp->securedisplay_context.context.bin_desc.fw_version =
3327                         le32_to_cpu(desc->fw_version);
3328                 psp->securedisplay_context.context.bin_desc.size_bytes =
3329                         le32_to_cpu(desc->size_bytes);
3330                 psp->securedisplay_context.context.bin_desc.start_addr =
3331                         ucode_start_addr;
3332                 break;
3333         default:
3334                 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type);
3335                 break;
3336         }
3337
3338         return 0;
3339 }
3340
3341 static int parse_ta_v1_microcode(struct psp_context *psp)
3342 {
3343         const struct ta_firmware_header_v1_0 *ta_hdr;
3344         struct amdgpu_device *adev = psp->adev;
3345
3346         ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data;
3347
3348         if (le16_to_cpu(ta_hdr->header.header_version_major) != 1)
3349                 return -EINVAL;
3350
3351         adev->psp.xgmi_context.context.bin_desc.fw_version =
3352                 le32_to_cpu(ta_hdr->xgmi.fw_version);
3353         adev->psp.xgmi_context.context.bin_desc.size_bytes =
3354                 le32_to_cpu(ta_hdr->xgmi.size_bytes);
3355         adev->psp.xgmi_context.context.bin_desc.start_addr =
3356                 (uint8_t *)ta_hdr +
3357                 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3358
3359         adev->psp.ras_context.context.bin_desc.fw_version =
3360                 le32_to_cpu(ta_hdr->ras.fw_version);
3361         adev->psp.ras_context.context.bin_desc.size_bytes =
3362                 le32_to_cpu(ta_hdr->ras.size_bytes);
3363         adev->psp.ras_context.context.bin_desc.start_addr =
3364                 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr +
3365                 le32_to_cpu(ta_hdr->ras.offset_bytes);
3366
3367         adev->psp.hdcp_context.context.bin_desc.fw_version =
3368                 le32_to_cpu(ta_hdr->hdcp.fw_version);
3369         adev->psp.hdcp_context.context.bin_desc.size_bytes =
3370                 le32_to_cpu(ta_hdr->hdcp.size_bytes);
3371         adev->psp.hdcp_context.context.bin_desc.start_addr =
3372                 (uint8_t *)ta_hdr +
3373                 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3374
3375         adev->psp.dtm_context.context.bin_desc.fw_version =
3376                 le32_to_cpu(ta_hdr->dtm.fw_version);
3377         adev->psp.dtm_context.context.bin_desc.size_bytes =
3378                 le32_to_cpu(ta_hdr->dtm.size_bytes);
3379         adev->psp.dtm_context.context.bin_desc.start_addr =
3380                 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
3381                 le32_to_cpu(ta_hdr->dtm.offset_bytes);
3382
3383         adev->psp.securedisplay_context.context.bin_desc.fw_version =
3384                 le32_to_cpu(ta_hdr->securedisplay.fw_version);
3385         adev->psp.securedisplay_context.context.bin_desc.size_bytes =
3386                 le32_to_cpu(ta_hdr->securedisplay.size_bytes);
3387         adev->psp.securedisplay_context.context.bin_desc.start_addr =
3388                 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
3389                 le32_to_cpu(ta_hdr->securedisplay.offset_bytes);
3390
3391         adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
3392
3393         return 0;
3394 }
3395
3396 static int parse_ta_v2_microcode(struct psp_context *psp)
3397 {
3398         const struct ta_firmware_header_v2_0 *ta_hdr;
3399         struct amdgpu_device *adev = psp->adev;
3400         int err = 0;
3401         int ta_index = 0;
3402
3403         ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data;
3404
3405         if (le16_to_cpu(ta_hdr->header.header_version_major) != 2)
3406                 return -EINVAL;
3407
3408         if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3409                 dev_err(adev->dev, "packed TA count exceeds maximum limit\n");
3410                 return -EINVAL;
3411         }
3412
3413         for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) {
3414                 err = parse_ta_bin_descriptor(psp,
3415                                               &ta_hdr->ta_fw_bin[ta_index],
3416                                               ta_hdr);
3417                 if (err)
3418                         return err;
3419         }
3420
3421         return 0;
3422 }
3423
3424 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name)
3425 {
3426         const struct common_firmware_header *hdr;
3427         struct amdgpu_device *adev = psp->adev;
3428         char fw_name[PSP_FW_NAME_LEN];
3429         int err;
3430
3431         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
3432         err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, fw_name);
3433         if (err)
3434                 return err;
3435
3436         hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data;
3437         switch (le16_to_cpu(hdr->header_version_major)) {
3438         case 1:
3439                 err = parse_ta_v1_microcode(psp);
3440                 break;
3441         case 2:
3442                 err = parse_ta_v2_microcode(psp);
3443                 break;
3444         default:
3445                 dev_err(adev->dev, "unsupported TA header version\n");
3446                 err = -EINVAL;
3447         }
3448
3449         if (err)
3450                 amdgpu_ucode_release(&adev->psp.ta_fw);
3451
3452         return err;
3453 }
3454
3455 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name)
3456 {
3457         struct amdgpu_device *adev = psp->adev;
3458         char fw_name[PSP_FW_NAME_LEN];
3459         const struct psp_firmware_header_v1_0 *cap_hdr_v1_0;
3460         struct amdgpu_firmware_info *info = NULL;
3461         int err = 0;
3462
3463         if (!amdgpu_sriov_vf(adev)) {
3464                 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n");
3465                 return -EINVAL;
3466         }
3467
3468         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name);
3469         err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, fw_name);
3470         if (err) {
3471                 if (err == -ENODEV) {
3472                         dev_warn(adev->dev, "cap microcode does not exist, skip\n");
3473                         err = 0;
3474                         goto out;
3475                 }
3476                 dev_err(adev->dev, "fail to initialize cap microcode\n");
3477         }
3478
3479         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP];
3480         info->ucode_id = AMDGPU_UCODE_ID_CAP;
3481         info->fw = adev->psp.cap_fw;
3482         cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *)
3483                 adev->psp.cap_fw->data;
3484         adev->firmware.fw_size += ALIGN(
3485                         le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE);
3486         adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version);
3487         adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version);
3488         adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes);
3489
3490         return 0;
3491
3492 out:
3493         amdgpu_ucode_release(&adev->psp.cap_fw);
3494         return err;
3495 }
3496
3497 static int psp_set_clockgating_state(void *handle,
3498                                      enum amd_clockgating_state state)
3499 {
3500         return 0;
3501 }
3502
3503 static int psp_set_powergating_state(void *handle,
3504                                      enum amd_powergating_state state)
3505 {
3506         return 0;
3507 }
3508
3509 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,
3510                                          struct device_attribute *attr,
3511                                          char *buf)
3512 {
3513         struct drm_device *ddev = dev_get_drvdata(dev);
3514         struct amdgpu_device *adev = drm_to_adev(ddev);
3515         uint32_t fw_ver;
3516         int ret;
3517
3518         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3519                 DRM_INFO("PSP block is not ready yet.");
3520                 return -EBUSY;
3521         }
3522
3523         mutex_lock(&adev->psp.mutex);
3524         ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver);
3525         mutex_unlock(&adev->psp.mutex);
3526
3527         if (ret) {
3528                 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret);
3529                 return ret;
3530         }
3531
3532         return sysfs_emit(buf, "%x\n", fw_ver);
3533 }
3534
3535 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
3536                                                        struct device_attribute *attr,
3537                                                        const char *buf,
3538                                                        size_t count)
3539 {
3540         struct drm_device *ddev = dev_get_drvdata(dev);
3541         struct amdgpu_device *adev = drm_to_adev(ddev);
3542         int ret, idx;
3543         char fw_name[100];
3544         const struct firmware *usbc_pd_fw;
3545         struct amdgpu_bo *fw_buf_bo = NULL;
3546         uint64_t fw_pri_mc_addr;
3547         void *fw_pri_cpu_addr;
3548
3549         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3550                 DRM_INFO("PSP block is not ready yet.");
3551                 return -EBUSY;
3552         }
3553
3554         if (!drm_dev_enter(ddev, &idx))
3555                 return -ENODEV;
3556
3557         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf);
3558         ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev);
3559         if (ret)
3560                 goto fail;
3561
3562         /* LFB address which is aligned to 1MB boundary per PSP request */
3563         ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000,
3564                                       AMDGPU_GEM_DOMAIN_VRAM |
3565                                       AMDGPU_GEM_DOMAIN_GTT,
3566                                       &fw_buf_bo, &fw_pri_mc_addr,
3567                                       &fw_pri_cpu_addr);
3568         if (ret)
3569                 goto rel_buf;
3570
3571         memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size);
3572
3573         mutex_lock(&adev->psp.mutex);
3574         ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr);
3575         mutex_unlock(&adev->psp.mutex);
3576
3577         amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3578
3579 rel_buf:
3580         release_firmware(usbc_pd_fw);
3581 fail:
3582         if (ret) {
3583                 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret);
3584                 count = ret;
3585         }
3586
3587         drm_dev_exit(idx);
3588         return count;
3589 }
3590
3591 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size)
3592 {
3593         int idx;
3594
3595         if (!drm_dev_enter(adev_to_drm(psp->adev), &idx))
3596                 return;
3597
3598         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
3599         memcpy(psp->fw_pri_buf, start_addr, bin_size);
3600
3601         drm_dev_exit(idx);
3602 }
3603
3604 /**
3605  * DOC: usbc_pd_fw
3606  * Reading from this file will retrieve the USB-C PD firmware version. Writing to
3607  * this file will trigger the update process.
3608  */
3609 static DEVICE_ATTR(usbc_pd_fw, 0644,
3610                    psp_usbc_pd_fw_sysfs_read,
3611                    psp_usbc_pd_fw_sysfs_write);
3612
3613 int is_psp_fw_valid(struct psp_bin_desc bin)
3614 {
3615         return bin.size_bytes;
3616 }
3617
3618 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj,
3619                                         struct bin_attribute *bin_attr,
3620                                         char *buffer, loff_t pos, size_t count)
3621 {
3622         struct device *dev = kobj_to_dev(kobj);
3623         struct drm_device *ddev = dev_get_drvdata(dev);
3624         struct amdgpu_device *adev = drm_to_adev(ddev);
3625
3626         adev->psp.vbflash_done = false;
3627
3628         /* Safeguard against memory drain */
3629         if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) {
3630                 dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B);
3631                 kvfree(adev->psp.vbflash_tmp_buf);
3632                 adev->psp.vbflash_tmp_buf = NULL;
3633                 adev->psp.vbflash_image_size = 0;
3634                 return -ENOMEM;
3635         }
3636
3637         /* TODO Just allocate max for now and optimize to realloc later if needed */
3638         if (!adev->psp.vbflash_tmp_buf) {
3639                 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL);
3640                 if (!adev->psp.vbflash_tmp_buf)
3641                         return -ENOMEM;
3642         }
3643
3644         mutex_lock(&adev->psp.mutex);
3645         memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count);
3646         adev->psp.vbflash_image_size += count;
3647         mutex_unlock(&adev->psp.mutex);
3648
3649         dev_dbg(adev->dev, "IFWI staged for update");
3650
3651         return count;
3652 }
3653
3654 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj,
3655                                        struct bin_attribute *bin_attr, char *buffer,
3656                                        loff_t pos, size_t count)
3657 {
3658         struct device *dev = kobj_to_dev(kobj);
3659         struct drm_device *ddev = dev_get_drvdata(dev);
3660         struct amdgpu_device *adev = drm_to_adev(ddev);
3661         struct amdgpu_bo *fw_buf_bo = NULL;
3662         uint64_t fw_pri_mc_addr;
3663         void *fw_pri_cpu_addr;
3664         int ret;
3665
3666         if (adev->psp.vbflash_image_size == 0)
3667                 return -EINVAL;
3668
3669         dev_dbg(adev->dev, "PSP IFWI flash process initiated");
3670
3671         ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size,
3672                                         AMDGPU_GPU_PAGE_SIZE,
3673                                         AMDGPU_GEM_DOMAIN_VRAM,
3674                                         &fw_buf_bo,
3675                                         &fw_pri_mc_addr,
3676                                         &fw_pri_cpu_addr);
3677         if (ret)
3678                 goto rel_buf;
3679
3680         memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size);
3681
3682         mutex_lock(&adev->psp.mutex);
3683         ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr);
3684         mutex_unlock(&adev->psp.mutex);
3685
3686         amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3687
3688 rel_buf:
3689         kvfree(adev->psp.vbflash_tmp_buf);
3690         adev->psp.vbflash_tmp_buf = NULL;
3691         adev->psp.vbflash_image_size = 0;
3692
3693         if (ret) {
3694                 dev_err(adev->dev, "Failed to load IFWI, err = %d", ret);
3695                 return ret;
3696         }
3697
3698         dev_dbg(adev->dev, "PSP IFWI flash process done");
3699         return 0;
3700 }
3701
3702 /**
3703  * DOC: psp_vbflash
3704  * Writing to this file will stage an IFWI for update. Reading from this file
3705  * will trigger the update process.
3706  */
3707 static struct bin_attribute psp_vbflash_bin_attr = {
3708         .attr = {.name = "psp_vbflash", .mode = 0660},
3709         .size = 0,
3710         .write = amdgpu_psp_vbflash_write,
3711         .read = amdgpu_psp_vbflash_read,
3712 };
3713
3714 /**
3715  * DOC: psp_vbflash_status
3716  * The status of the flash process.
3717  * 0: IFWI flash not complete.
3718  * 1: IFWI flash complete.
3719  */
3720 static ssize_t amdgpu_psp_vbflash_status(struct device *dev,
3721                                          struct device_attribute *attr,
3722                                          char *buf)
3723 {
3724         struct drm_device *ddev = dev_get_drvdata(dev);
3725         struct amdgpu_device *adev = drm_to_adev(ddev);
3726         uint32_t vbflash_status;
3727
3728         vbflash_status = psp_vbflash_status(&adev->psp);
3729         if (!adev->psp.vbflash_done)
3730                 vbflash_status = 0;
3731         else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000))
3732                 vbflash_status = 1;
3733
3734         return sysfs_emit(buf, "0x%x\n", vbflash_status);
3735 }
3736 static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL);
3737
3738 static struct bin_attribute *bin_flash_attrs[] = {
3739         &psp_vbflash_bin_attr,
3740         NULL
3741 };
3742
3743 static struct attribute *flash_attrs[] = {
3744         &dev_attr_psp_vbflash_status.attr,
3745         &dev_attr_usbc_pd_fw.attr,
3746         NULL
3747 };
3748
3749 static umode_t amdgpu_flash_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx)
3750 {
3751         struct device *dev = kobj_to_dev(kobj);
3752         struct drm_device *ddev = dev_get_drvdata(dev);
3753         struct amdgpu_device *adev = drm_to_adev(ddev);
3754
3755         if (attr == &dev_attr_usbc_pd_fw.attr)
3756                 return adev->psp.sup_pd_fw_up ? 0660 : 0;
3757
3758         return adev->psp.sup_ifwi_up ? 0440 : 0;
3759 }
3760
3761 static umode_t amdgpu_bin_flash_attr_is_visible(struct kobject *kobj,
3762                                                 struct bin_attribute *attr,
3763                                                 int idx)
3764 {
3765         struct device *dev = kobj_to_dev(kobj);
3766         struct drm_device *ddev = dev_get_drvdata(dev);
3767         struct amdgpu_device *adev = drm_to_adev(ddev);
3768
3769         return adev->psp.sup_ifwi_up ? 0660 : 0;
3770 }
3771
3772 const struct attribute_group amdgpu_flash_attr_group = {
3773         .attrs = flash_attrs,
3774         .bin_attrs = bin_flash_attrs,
3775         .is_bin_visible = amdgpu_bin_flash_attr_is_visible,
3776         .is_visible = amdgpu_flash_attr_is_visible,
3777 };
3778
3779 const struct amd_ip_funcs psp_ip_funcs = {
3780         .name = "psp",
3781         .early_init = psp_early_init,
3782         .late_init = NULL,
3783         .sw_init = psp_sw_init,
3784         .sw_fini = psp_sw_fini,
3785         .hw_init = psp_hw_init,
3786         .hw_fini = psp_hw_fini,
3787         .suspend = psp_suspend,
3788         .resume = psp_resume,
3789         .is_idle = NULL,
3790         .check_soft_reset = NULL,
3791         .wait_for_idle = NULL,
3792         .soft_reset = NULL,
3793         .set_clockgating_state = psp_set_clockgating_state,
3794         .set_powergating_state = psp_set_powergating_state,
3795 };
3796
3797 const struct amdgpu_ip_block_version psp_v3_1_ip_block = {
3798         .type = AMD_IP_BLOCK_TYPE_PSP,
3799         .major = 3,
3800         .minor = 1,
3801         .rev = 0,
3802         .funcs = &psp_ip_funcs,
3803 };
3804
3805 const struct amdgpu_ip_block_version psp_v10_0_ip_block = {
3806         .type = AMD_IP_BLOCK_TYPE_PSP,
3807         .major = 10,
3808         .minor = 0,
3809         .rev = 0,
3810         .funcs = &psp_ip_funcs,
3811 };
3812
3813 const struct amdgpu_ip_block_version psp_v11_0_ip_block = {
3814         .type = AMD_IP_BLOCK_TYPE_PSP,
3815         .major = 11,
3816         .minor = 0,
3817         .rev = 0,
3818         .funcs = &psp_ip_funcs,
3819 };
3820
3821 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = {
3822         .type = AMD_IP_BLOCK_TYPE_PSP,
3823         .major = 11,
3824         .minor = 0,
3825         .rev = 8,
3826         .funcs = &psp_ip_funcs,
3827 };
3828
3829 const struct amdgpu_ip_block_version psp_v12_0_ip_block = {
3830         .type = AMD_IP_BLOCK_TYPE_PSP,
3831         .major = 12,
3832         .minor = 0,
3833         .rev = 0,
3834         .funcs = &psp_ip_funcs,
3835 };
3836
3837 const struct amdgpu_ip_block_version psp_v13_0_ip_block = {
3838         .type = AMD_IP_BLOCK_TYPE_PSP,
3839         .major = 13,
3840         .minor = 0,
3841         .rev = 0,
3842         .funcs = &psp_ip_funcs,
3843 };
3844
3845 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = {
3846         .type = AMD_IP_BLOCK_TYPE_PSP,
3847         .major = 13,
3848         .minor = 0,
3849         .rev = 4,
3850         .funcs = &psp_ip_funcs,
3851 };