drivers/gpu/drm/vc4/vc4_crtc.c

   1 /*
   2  * Copyright (C) 2015 Broadcom
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /**
  10  * DOC: VC4 CRTC module
  11  *
  12  * In VC4, the Pixel Valve is what most closely corresponds to the
  13  * DRM's concept of a CRTC.  The PV generates video timings from the
  14  * encoder's clock plus its configuration.  It pulls scaled pixels from
  15  * the HVS at that timing, and feeds it to the encoder.
  16  *
  17  * However, the DRM CRTC also collects the configuration of all the
  18  * DRM planes attached to it.  As a result, the CRTC is also
  19  * responsible for writing the display list for the HVS channel that
  20  * the CRTC will use.
  21  *
  22  * The 2835 has 3 different pixel valves.  pv0 in the audio power
  23  * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI.  pv2 in the
  24  * image domain can feed either HDMI or the SDTV controller.  The
  25  * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
  26  * SDTV, etc.) according to which output type is chosen in the mux.
  27  *
  28  * For power management, the pixel valve's registers are all clocked
  29  * by the AXI clock, while the timings and FIFOs make use of the
  30  * output-specific clock.  Since the encoders also directly consume
  31  * the CPRMAN clocks, and know what timings they need, they are the
  32  * ones that set the clock.
  33  */
  34
  35 #include <drm/drm_atomic.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc_helper.h>
  38 #include <drm/drm_atomic_uapi.h>
  39 #include <linux/clk.h>
  40 #include <drm/drm_fb_cma_helper.h>
  41 #include <linux/component.h>
  42 #include <linux/of_device.h>
  43 #include "vc4_drv.h"
  44 #include "vc4_regs.h"
  45
  46 struct vc4_crtc_state {
  47         struct drm_crtc_state base;
  48         /* Dlist area for this CRTC configuration. */
  49         struct drm_mm_node mm;
  50         bool feed_txp;
  51         bool txp_armed;
  52 };
  53
  54 static inline struct vc4_crtc_state *
  55 to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
  56 {
  57         return (struct vc4_crtc_state *)crtc_state;
  58 }
  59
  60 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
  61 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
  62
  63 #define CRTC_REG(reg) { reg, #reg }
  64 static const struct {
  65         u32 reg;
  66         const char *name;
  67 } crtc_regs[] = {
  68         CRTC_REG(PV_CONTROL),
  69         CRTC_REG(PV_V_CONTROL),
  70         CRTC_REG(PV_VSYNCD_EVEN),
  71         CRTC_REG(PV_HORZA),
  72         CRTC_REG(PV_HORZB),
  73         CRTC_REG(PV_VERTA),
  74         CRTC_REG(PV_VERTB),
  75         CRTC_REG(PV_VERTA_EVEN),
  76         CRTC_REG(PV_VERTB_EVEN),
  77         CRTC_REG(PV_INTEN),
  78         CRTC_REG(PV_INTSTAT),
  79         CRTC_REG(PV_STAT),
  80         CRTC_REG(PV_HACT_ACT),
  81 };
  82
  83 static void vc4_crtc_dump_regs(struct vc4_crtc *vc4_crtc)
  84 {
  85         int i;
  86
  87         for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
  88                 DRM_INFO("0x%04x (%s): 0x%08x\n",
  89                          crtc_regs[i].reg, crtc_regs[i].name,
  90                          CRTC_READ(crtc_regs[i].reg));
  91         }
  92 }
  93
  94 #ifdef CONFIG_DEBUG_FS
  95 int vc4_crtc_debugfs_regs(struct seq_file *m, void *unused)
  96 {
  97         struct drm_info_node *node = (struct drm_info_node *)m->private;
  98         struct drm_device *dev = node->minor->dev;
  99         int crtc_index = (uintptr_t)node->info_ent->data;
 100         struct drm_crtc *crtc;
 101         struct vc4_crtc *vc4_crtc;
 102         int i;
 103
 104         i = 0;
 105         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 106                 if (i == crtc_index)
 107                         break;
 108                 i++;
 109         }
 110         if (!crtc)
 111                 return 0;
 112         vc4_crtc = to_vc4_crtc(crtc);
 113
 114         for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
 115                 seq_printf(m, "%s (0x%04x): 0x%08x\n",
 116                            crtc_regs[i].name, crtc_regs[i].reg,
 117                            CRTC_READ(crtc_regs[i].reg));
 118         }
 119
 120         return 0;
 121 }
 122 #endif
 123
 124 bool vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
 125                              bool in_vblank_irq, int *vpos, int *hpos,
 126                              ktime_t *stime, ktime_t *etime,
 127                              const struct drm_display_mode *mode)
 128 {
 129         struct vc4_dev *vc4 = to_vc4_dev(dev);
 130         struct drm_crtc *crtc = drm_crtc_from_index(dev, crtc_id);
 131         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 132         u32 val;
 133         int fifo_lines;
 134         int vblank_lines;
 135         bool ret = false;
 136
 137         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 138
 139         /* Get optional system timestamp before query. */
 140         if (stime)
 141                 *stime = ktime_get();
 142
 143         /*
 144          * Read vertical scanline which is currently composed for our
 145          * pixelvalve by the HVS, and also the scaler status.
 146          */
 147         val = HVS_READ(SCALER_DISPSTATX(vc4_crtc->channel));
 148
 149         /* Get optional system timestamp after query. */
 150         if (etime)
 151                 *etime = ktime_get();
 152
 153         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 154
 155         /* Vertical position of hvs composed scanline. */
 156         *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
 157         *hpos = 0;
 158
 159         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 160                 *vpos /= 2;
 161
 162                 /* Use hpos to correct for field offset in interlaced mode. */
 163                 if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2)
 164                         *hpos += mode->crtc_htotal / 2;
 165         }
 166
 167         /* This is the offset we need for translating hvs -> pv scanout pos. */
 168         fifo_lines = vc4_crtc->cob_size / mode->crtc_hdisplay;
 169
 170         if (fifo_lines > 0)
 171                 ret = true;
 172
 173         /* HVS more than fifo_lines into frame for compositing? */
 174         if (*vpos > fifo_lines) {
 175                 /*
 176                  * We are in active scanout and can get some meaningful results
 177                  * from HVS. The actual PV scanout can not trail behind more
 178                  * than fifo_lines as that is the fifo's capacity. Assume that
 179                  * in active scanout the HVS and PV work in lockstep wrt. HVS
 180                  * refilling the fifo and PV consuming from the fifo, ie.
 181                  * whenever the PV consumes and frees up a scanline in the
 182                  * fifo, the HVS will immediately refill it, therefore
 183                  * incrementing vpos. Therefore we choose HVS read position -
 184                  * fifo size in scanlines as a estimate of the real scanout
 185                  * position of the PV.
 186                  */
 187                 *vpos -= fifo_lines + 1;
 188
 189                 return ret;
 190         }
 191
 192         /*
 193          * Less: This happens when we are in vblank and the HVS, after getting
 194          * the VSTART restart signal from the PV, just started refilling its
 195          * fifo with new lines from the top-most lines of the new framebuffers.
 196          * The PV does not scan out in vblank, so does not remove lines from
 197          * the fifo, so the fifo will be full quickly and the HVS has to pause.
 198          * We can't get meaningful readings wrt. scanline position of the PV
 199          * and need to make things up in a approximative but consistent way.
 200          */
 201         vblank_lines = mode->vtotal - mode->vdisplay;
 202
 203         if (in_vblank_irq) {
 204                 /*
 205                  * Assume the irq handler got called close to first
 206                  * line of vblank, so PV has about a full vblank
 207                  * scanlines to go, and as a base timestamp use the
 208                  * one taken at entry into vblank irq handler, so it
 209                  * is not affected by random delays due to lock
 210                  * contention on event_lock or vblank_time lock in
 211                  * the core.
 212                  */
 213                 *vpos = -vblank_lines;
 214
 215                 if (stime)
 216                         *stime = vc4_crtc->t_vblank;
 217                 if (etime)
 218                         *etime = vc4_crtc->t_vblank;
 219
 220                 /*
 221                  * If the HVS fifo is not yet full then we know for certain
 222                  * we are at the very beginning of vblank, as the hvs just
 223                  * started refilling, and the stime and etime timestamps
 224                  * truly correspond to start of vblank.
 225                  *
 226                  * Unfortunately there's no way to report this to upper levels
 227                  * and make it more useful.
 228                  */
 229         } else {
 230                 /*
 231                  * No clue where we are inside vblank. Return a vpos of zero,
 232                  * which will cause calling code to just return the etime
 233                  * timestamp uncorrected. At least this is no worse than the
 234                  * standard fallback.
 235                  */
 236                 *vpos = 0;
 237         }
 238
 239         return ret;
 240 }
 241
 242 static void vc4_crtc_destroy(struct drm_crtc *crtc)
 243 {
 244         drm_crtc_cleanup(crtc);
 245 }
 246
 247 static void
 248 vc4_crtc_lut_load(struct drm_crtc *crtc)
 249 {
 250         struct drm_device *dev = crtc->dev;
 251         struct vc4_dev *vc4 = to_vc4_dev(dev);
 252         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 253         u32 i;
 254
 255         /* The LUT memory is laid out with each HVS channel in order,
 256          * each of which takes 256 writes for R, 256 for G, then 256
 257          * for B.
 258          */
 259         HVS_WRITE(SCALER_GAMADDR,
 260                   SCALER_GAMADDR_AUTOINC |
 261                   (vc4_crtc->channel * 3 * crtc->gamma_size));
 262
 263         for (i = 0; i < crtc->gamma_size; i++)
 264                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
 265         for (i = 0; i < crtc->gamma_size; i++)
 266                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
 267         for (i = 0; i < crtc->gamma_size; i++)
 268                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
 269 }
 270
 271 static void
 272 vc4_crtc_update_gamma_lut(struct drm_crtc *crtc)
 273 {
 274         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 275         struct drm_color_lut *lut = crtc->state->gamma_lut->data;
 276         u32 length = drm_color_lut_size(crtc->state->gamma_lut);
 277         u32 i;
 278
 279         for (i = 0; i < length; i++) {
 280                 vc4_crtc->lut_r[i] = drm_color_lut_extract(lut[i].red, 8);
 281                 vc4_crtc->lut_g[i] = drm_color_lut_extract(lut[i].green, 8);
 282                 vc4_crtc->lut_b[i] = drm_color_lut_extract(lut[i].blue, 8);
 283         }
 284
 285         vc4_crtc_lut_load(crtc);
 286 }
 287
 288 static u32 vc4_get_fifo_full_level(u32 format)
 289 {
 290         static const u32 fifo_len_bytes = 64;
 291         static const u32 hvs_latency_pix = 6;
 292
 293         switch (format) {
 294         case PV_CONTROL_FORMAT_DSIV_16:
 295         case PV_CONTROL_FORMAT_DSIC_16:
 296                 return fifo_len_bytes - 2 * hvs_latency_pix;
 297         case PV_CONTROL_FORMAT_DSIV_18:
 298                 return fifo_len_bytes - 14;
 299         case PV_CONTROL_FORMAT_24:
 300         case PV_CONTROL_FORMAT_DSIV_24:
 301         default:
 302                 return fifo_len_bytes - 3 * hvs_latency_pix;
 303         }
 304 }
 305
 306 /*
 307  * Returns the encoder attached to the CRTC.
 308  *
 309  * VC4 can only scan out to one encoder at a time, while the DRM core
 310  * allows drivers to push pixels to more than one encoder from the
 311  * same CRTC.
 312  */
 313 static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc)
 314 {
 315         struct drm_connector *connector;
 316         struct drm_connector_list_iter conn_iter;
 317
 318         drm_connector_list_iter_begin(crtc->dev, &conn_iter);
 319         drm_for_each_connector_iter(connector, &conn_iter) {
 320                 if (connector->state->crtc == crtc) {
 321                         drm_connector_list_iter_end(&conn_iter);
 322                         return connector->encoder;
 323                 }
 324         }
 325         drm_connector_list_iter_end(&conn_iter);
 326
 327         return NULL;
 328 }
 329
 330 static void vc4_crtc_config_pv(struct drm_crtc *crtc)
 331 {
 332         struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
 333         struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 334         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 335         struct drm_crtc_state *state = crtc->state;
 336         struct drm_display_mode *mode = &state->adjusted_mode;
 337         bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
 338         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 339         bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
 340                        vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
 341         u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
 342
 343         /* Reset the PV fifo. */
 344         CRTC_WRITE(PV_CONTROL, 0);
 345         CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
 346         CRTC_WRITE(PV_CONTROL, 0);
 347
 348         CRTC_WRITE(PV_HORZA,
 349                    VC4_SET_FIELD((mode->htotal -
 350                                   mode->hsync_end) * pixel_rep,
 351                                  PV_HORZA_HBP) |
 352                    VC4_SET_FIELD((mode->hsync_end -
 353                                   mode->hsync_start) * pixel_rep,
 354                                  PV_HORZA_HSYNC));
 355         CRTC_WRITE(PV_HORZB,
 356                    VC4_SET_FIELD((mode->hsync_start -
 357                                   mode->hdisplay) * pixel_rep,
 358                                  PV_HORZB_HFP) |
 359                    VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE));
 360
 361         CRTC_WRITE(PV_VERTA,
 362                    VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 363                                  PV_VERTA_VBP) |
 364                    VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 365                                  PV_VERTA_VSYNC));
 366         CRTC_WRITE(PV_VERTB,
 367                    VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 368                                  PV_VERTB_VFP) |
 369                    VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 370
 371         if (interlace) {
 372                 CRTC_WRITE(PV_VERTA_EVEN,
 373                            VC4_SET_FIELD(mode->crtc_vtotal -
 374                                          mode->crtc_vsync_end - 1,
 375                                          PV_VERTA_VBP) |
 376                            VC4_SET_FIELD(mode->crtc_vsync_end -
 377                                          mode->crtc_vsync_start,
 378                                          PV_VERTA_VSYNC));
 379                 CRTC_WRITE(PV_VERTB_EVEN,
 380                            VC4_SET_FIELD(mode->crtc_vsync_start -
 381                                          mode->crtc_vdisplay,
 382                                          PV_VERTB_VFP) |
 383                            VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 384
 385                 /* We set up first field even mode for HDMI.  VEC's
 386                  * NTSC mode would want first field odd instead, once
 387                  * we support it (to do so, set ODD_FIRST and put the
 388                  * delay in VSYNCD_EVEN instead).
 389                  */
 390                 CRTC_WRITE(PV_V_CONTROL,
 391                            PV_VCONTROL_CONTINUOUS |
 392                            (is_dsi ? PV_VCONTROL_DSI : 0) |
 393                            PV_VCONTROL_INTERLACE |
 394                            VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
 395                                          PV_VCONTROL_ODD_DELAY));
 396                 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
 397         } else {
 398                 CRTC_WRITE(PV_V_CONTROL,
 399                            PV_VCONTROL_CONTINUOUS |
 400                            (is_dsi ? PV_VCONTROL_DSI : 0));
 401         }
 402
 403         CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
 404
 405         CRTC_WRITE(PV_CONTROL,
 406                    VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
 407                    VC4_SET_FIELD(vc4_get_fifo_full_level(format),
 408                                  PV_CONTROL_FIFO_LEVEL) |
 409                    VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
 410                    PV_CONTROL_CLR_AT_START |
 411                    PV_CONTROL_TRIGGER_UNDERFLOW |
 412                    PV_CONTROL_WAIT_HSTART |
 413                    VC4_SET_FIELD(vc4_encoder->clock_select,
 414                                  PV_CONTROL_CLK_SELECT) |
 415                    PV_CONTROL_FIFO_CLR |
 416                    PV_CONTROL_EN);
 417 }
 418
 419 static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
 420 {
 421         struct drm_device *dev = crtc->dev;
 422         struct vc4_dev *vc4 = to_vc4_dev(dev);
 423         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 424         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 425         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 426         bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
 427         bool debug_dump_regs = false;
 428
 429         if (debug_dump_regs) {
 430                 DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc));
 431                 vc4_crtc_dump_regs(vc4_crtc);
 432         }
 433
 434         if (vc4_crtc->channel == 2) {
 435                 u32 dispctrl;
 436                 u32 dsp3_mux;
 437
 438                 /*
 439                  * SCALER_DISPCTRL_DSP3 = X, where X < 2 means 'connect DSP3 to
 440                  * FIFO X'.
 441                  * SCALER_DISPCTRL_DSP3 = 3 means 'disable DSP 3'.
 442                  *
 443                  * DSP3 is connected to FIFO2 unless the transposer is
 444                  * enabled. In this case, FIFO 2 is directly accessed by the
 445                  * TXP IP, and we need to disable the FIFO2 -> pixelvalve1
 446                  * route.
 447                  */
 448                 if (vc4_state->feed_txp)
 449                         dsp3_mux = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX);
 450                 else
 451                         dsp3_mux = VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
 452
 453                 dispctrl = HVS_READ(SCALER_DISPCTRL) &
 454                            ~SCALER_DISPCTRL_DSP3_MUX_MASK;
 455                 HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux);
 456         }
 457
 458         if (!vc4_state->feed_txp)
 459                 vc4_crtc_config_pv(crtc);
 460
 461         HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
 462                   SCALER_DISPBKGND_AUTOHS |
 463                   SCALER_DISPBKGND_GAMMA |
 464                   (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
 465
 466         /* Reload the LUT, since the SRAMs would have been disabled if
 467          * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
 468          */
 469         vc4_crtc_lut_load(crtc);
 470
 471         if (debug_dump_regs) {
 472                 DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc));
 473                 vc4_crtc_dump_regs(vc4_crtc);
 474         }
 475 }
 476
 477 static void require_hvs_enabled(struct drm_device *dev)
 478 {
 479         struct vc4_dev *vc4 = to_vc4_dev(dev);
 480
 481         WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
 482                      SCALER_DISPCTRL_ENABLE);
 483 }
 484
 485 static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
 486                                     struct drm_crtc_state *old_state)
 487 {
 488         struct drm_device *dev = crtc->dev;
 489         struct vc4_dev *vc4 = to_vc4_dev(dev);
 490         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 491         u32 chan = vc4_crtc->channel;
 492         int ret;
 493         require_hvs_enabled(dev);
 494
 495         /* Disable vblank irq handling before crtc is disabled. */
 496         drm_crtc_vblank_off(crtc);
 497
 498         CRTC_WRITE(PV_V_CONTROL,
 499                    CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
 500         ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
 501         WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
 502
 503         if (HVS_READ(SCALER_DISPCTRLX(chan)) &
 504             SCALER_DISPCTRLX_ENABLE) {
 505                 HVS_WRITE(SCALER_DISPCTRLX(chan),
 506                           SCALER_DISPCTRLX_RESET);
 507
 508                 /* While the docs say that reset is self-clearing, it
 509                  * seems it doesn't actually.
 510                  */
 511                 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
 512         }
 513
 514         /* Once we leave, the scaler should be disabled and its fifo empty. */
 515
 516         WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
 517
 518         WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
 519                                    SCALER_DISPSTATX_MODE) !=
 520                      SCALER_DISPSTATX_MODE_DISABLED);
 521
 522         WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
 523                       (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) !=
 524                      SCALER_DISPSTATX_EMPTY);
 525
 526         /*
 527          * Make sure we issue a vblank event after disabling the CRTC if
 528          * someone was waiting it.
 529          */
 530         if (crtc->state->event) {
 531                 unsigned long flags;
 532
 533                 spin_lock_irqsave(&dev->event_lock, flags);
 534                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 535                 crtc->state->event = NULL;
 536                 spin_unlock_irqrestore(&dev->event_lock, flags);
 537         }
 538 }
 539
 540 void vc4_crtc_txp_armed(struct drm_crtc_state *state)
 541 {
 542         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 543
 544         vc4_state->txp_armed = true;
 545 }
 546
 547 static void vc4_crtc_update_dlist(struct drm_crtc *crtc)
 548 {
 549         struct drm_device *dev = crtc->dev;
 550         struct vc4_dev *vc4 = to_vc4_dev(dev);
 551         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 552         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 553
 554         if (crtc->state->event) {
 555                 unsigned long flags;
 556
 557                 crtc->state->event->pipe = drm_crtc_index(crtc);
 558
 559                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 560
 561                 spin_lock_irqsave(&dev->event_lock, flags);
 562
 563                 if (!vc4_state->feed_txp || vc4_state->txp_armed) {
 564                         vc4_crtc->event = crtc->state->event;
 565                         crtc->state->event = NULL;
 566                 }
 567
 568                 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
 569                           vc4_state->mm.start);
 570
 571                 spin_unlock_irqrestore(&dev->event_lock, flags);
 572         } else {
 573                 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
 574                           vc4_state->mm.start);
 575         }
 576 }
 577
 578 static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
 579                                    struct drm_crtc_state *old_state)
 580 {
 581         struct drm_device *dev = crtc->dev;
 582         struct vc4_dev *vc4 = to_vc4_dev(dev);
 583         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 584         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 585         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 586
 587         require_hvs_enabled(dev);
 588
 589         /* Enable vblank irq handling before crtc is started otherwise
 590          * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist().
 591          */
 592         drm_crtc_vblank_on(crtc);
 593         vc4_crtc_update_dlist(crtc);
 594
 595         /* Turn on the scaler, which will wait for vstart to start
 596          * compositing.
 597          * When feeding the transposer, we should operate in oneshot
 598          * mode.
 599          */
 600         HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel),
 601                   VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) |
 602                   VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) |
 603                   SCALER_DISPCTRLX_ENABLE |
 604                   (vc4_state->feed_txp ? SCALER_DISPCTRLX_ONESHOT : 0));
 605
 606         /* When feeding the transposer block the pixelvalve is unneeded and
 607          * should not be enabled.
 608          */
 609         if (!vc4_state->feed_txp)
 610                 CRTC_WRITE(PV_V_CONTROL,
 611                            CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
 612 }
 613
 614 static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc,
 615                                                 const struct drm_display_mode *mode)
 616 {
 617         /* Do not allow doublescan modes from user space */
 618         if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 619                 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
 620                               crtc->base.id);
 621                 return MODE_NO_DBLESCAN;
 622         }
 623
 624         return MODE_OK;
 625 }
 626
 627 static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
 628                                  struct drm_crtc_state *state)
 629 {
 630         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 631         struct drm_device *dev = crtc->dev;
 632         struct vc4_dev *vc4 = to_vc4_dev(dev);
 633         struct drm_plane *plane;
 634         unsigned long flags;
 635         const struct drm_plane_state *plane_state;
 636         struct drm_connector *conn;
 637         struct drm_connector_state *conn_state;
 638         u32 dlist_count = 0;
 639         int ret, i;
 640
 641         /* The pixelvalve can only feed one encoder (and encoders are
 642          * 1:1 with connectors.)
 643          */
 644         if (hweight32(state->connector_mask) > 1)
 645                 return -EINVAL;
 646
 647         drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state)
 648                 dlist_count += vc4_plane_dlist_size(plane_state);
 649
 650         dlist_count++; /* Account for SCALER_CTL0_END. */
 651
 652         spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
 653         ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm,
 654                                  dlist_count);
 655         spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
 656         if (ret)
 657                 return ret;
 658
 659         for_each_new_connector_in_state(state->state, conn, conn_state, i) {
 660                 if (conn_state->crtc != crtc)
 661                         continue;
 662
 663                 /* The writeback connector is implemented using the transposer
 664                  * block which is directly taking its data from the HVS FIFO.
 665                  */
 666                 if (conn->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) {
 667                         state->no_vblank = true;
 668                         vc4_state->feed_txp = true;
 669                 } else {
 670                         state->no_vblank = false;
 671                         vc4_state->feed_txp = false;
 672                 }
 673
 674                 break;
 675         }
 676
 677         return 0;
 678 }
 679
 680 static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
 681                                   struct drm_crtc_state *old_state)
 682 {
 683         struct drm_device *dev = crtc->dev;
 684         struct vc4_dev *vc4 = to_vc4_dev(dev);
 685         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 686         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 687         struct drm_plane *plane;
 688         struct vc4_plane_state *vc4_plane_state;
 689         bool debug_dump_regs = false;
 690         bool enable_bg_fill = false;
 691         u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
 692         u32 __iomem *dlist_next = dlist_start;
 693
 694         if (debug_dump_regs) {
 695                 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
 696                 vc4_hvs_dump_state(dev);
 697         }
 698
 699         /* Copy all the active planes' dlist contents to the hardware dlist. */
 700         drm_atomic_crtc_for_each_plane(plane, crtc) {
 701                 /* Is this the first active plane? */
 702                 if (dlist_next == dlist_start) {
 703                         /* We need to enable background fill when a plane
 704                          * could be alpha blending from the background, i.e.
 705                          * where no other plane is underneath. It suffices to
 706                          * consider the first active plane here since we set
 707                          * needs_bg_fill such that either the first plane
 708                          * already needs it or all planes on top blend from
 709                          * the first or a lower plane.
 710                          */
 711                         vc4_plane_state = to_vc4_plane_state(plane->state);
 712                         enable_bg_fill = vc4_plane_state->needs_bg_fill;
 713                 }
 714
 715                 dlist_next += vc4_plane_write_dlist(plane, dlist_next);
 716         }
 717
 718         writel(SCALER_CTL0_END, dlist_next);
 719         dlist_next++;
 720
 721         WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
 722
 723         if (enable_bg_fill)
 724                 /* This sets a black background color fill, as is the case
 725                  * with other DRM drivers.
 726                  */
 727                 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
 728                           HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel)) |
 729                           SCALER_DISPBKGND_FILL);
 730
 731         /* Only update DISPLIST if the CRTC was already running and is not
 732          * being disabled.
 733          * vc4_crtc_enable() takes care of updating the dlist just after
 734          * re-enabling VBLANK interrupts and before enabling the engine.
 735          * If the CRTC is being disabled, there's no point in updating this
 736          * information.
 737          */
 738         if (crtc->state->active && old_state->active)
 739                 vc4_crtc_update_dlist(crtc);
 740
 741         if (crtc->state->color_mgmt_changed) {
 742                 u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel));
 743
 744                 if (crtc->state->gamma_lut) {
 745                         vc4_crtc_update_gamma_lut(crtc);
 746                         dispbkgndx |= SCALER_DISPBKGND_GAMMA;
 747                 } else {
 748                         /* Unsetting DISPBKGND_GAMMA skips the gamma lut step
 749                          * in hardware, which is the same as a linear lut that
 750                          * DRM expects us to use in absence of a user lut.
 751                          */
 752                         dispbkgndx &= ~SCALER_DISPBKGND_GAMMA;
 753                 }
 754                 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel), dispbkgndx);
 755         }
 756
 757         if (debug_dump_regs) {
 758                 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
 759                 vc4_hvs_dump_state(dev);
 760         }
 761 }
 762
 763 static int vc4_enable_vblank(struct drm_crtc *crtc)
 764 {
 765         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 766
 767         CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
 768
 769         return 0;
 770 }
 771
 772 static void vc4_disable_vblank(struct drm_crtc *crtc)
 773 {
 774         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 775
 776         CRTC_WRITE(PV_INTEN, 0);
 777 }
 778
 779 static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
 780 {
 781         struct drm_crtc *crtc = &vc4_crtc->base;
 782         struct drm_device *dev = crtc->dev;
 783         struct vc4_dev *vc4 = to_vc4_dev(dev);
 784         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 785         u32 chan = vc4_crtc->channel;
 786         unsigned long flags;
 787
 788         spin_lock_irqsave(&dev->event_lock, flags);
 789         if (vc4_crtc->event &&
 790             (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)) ||
 791              vc4_state->feed_txp)) {
 792                 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
 793                 vc4_crtc->event = NULL;
 794                 drm_crtc_vblank_put(crtc);
 795         }
 796         spin_unlock_irqrestore(&dev->event_lock, flags);
 797 }
 798
 799 void vc4_crtc_handle_vblank(struct vc4_crtc *crtc)
 800 {
 801         crtc->t_vblank = ktime_get();
 802         drm_crtc_handle_vblank(&crtc->base);
 803         vc4_crtc_handle_page_flip(crtc);
 804 }
 805
 806 static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
 807 {
 808         struct vc4_crtc *vc4_crtc = data;
 809         u32 stat = CRTC_READ(PV_INTSTAT);
 810         irqreturn_t ret = IRQ_NONE;
 811
 812         if (stat & PV_INT_VFP_START) {
 813                 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
 814                 vc4_crtc_handle_vblank(vc4_crtc);
 815                 ret = IRQ_HANDLED;
 816         }
 817
 818         return ret;
 819 }
 820
 821 struct vc4_async_flip_state {
 822         struct drm_crtc *crtc;
 823         struct drm_framebuffer *fb;
 824         struct drm_framebuffer *old_fb;
 825         struct drm_pending_vblank_event *event;
 826
 827         struct vc4_seqno_cb cb;
 828 };
 829
 830 /* Called when the V3D execution for the BO being flipped to is done, so that
 831  * we can actually update the plane's address to point to it.
 832  */
 833 static void
 834 vc4_async_page_flip_complete(struct vc4_seqno_cb *cb)
 835 {
 836         struct vc4_async_flip_state *flip_state =
 837                 container_of(cb, struct vc4_async_flip_state, cb);
 838         struct drm_crtc *crtc = flip_state->crtc;
 839         struct drm_device *dev = crtc->dev;
 840         struct vc4_dev *vc4 = to_vc4_dev(dev);
 841         struct drm_plane *plane = crtc->primary;
 842
 843         vc4_plane_async_set_fb(plane, flip_state->fb);
 844         if (flip_state->event) {
 845                 unsigned long flags;
 846
 847                 spin_lock_irqsave(&dev->event_lock, flags);
 848                 drm_crtc_send_vblank_event(crtc, flip_state->event);
 849                 spin_unlock_irqrestore(&dev->event_lock, flags);
 850         }
 851
 852         drm_crtc_vblank_put(crtc);
 853         drm_framebuffer_put(flip_state->fb);
 854
 855         /* Decrement the BO usecnt in order to keep the inc/dec calls balanced
 856          * when the planes are updated through the async update path.
 857          * FIXME: we should move to generic async-page-flip when it's
 858          * available, so that we can get rid of this hand-made cleanup_fb()
 859          * logic.
 860          */
 861         if (flip_state->old_fb) {
 862                 struct drm_gem_cma_object *cma_bo;
 863                 struct vc4_bo *bo;
 864
 865                 cma_bo = drm_fb_cma_get_gem_obj(flip_state->old_fb, 0);
 866                 bo = to_vc4_bo(&cma_bo->base);
 867                 vc4_bo_dec_usecnt(bo);
 868                 drm_framebuffer_put(flip_state->old_fb);
 869         }
 870
 871         kfree(flip_state);
 872
 873         up(&vc4->async_modeset);
 874 }
 875
 876 /* Implements async (non-vblank-synced) page flips.
 877  *
 878  * The page flip ioctl needs to return immediately, so we grab the
 879  * modeset semaphore on the pipe, and queue the address update for
 880  * when V3D is done with the BO being flipped to.
 881  */
 882 static int vc4_async_page_flip(struct drm_crtc *crtc,
 883                                struct drm_framebuffer *fb,
 884                                struct drm_pending_vblank_event *event,
 885                                uint32_t flags)
 886 {
 887         struct drm_device *dev = crtc->dev;
 888         struct vc4_dev *vc4 = to_vc4_dev(dev);
 889         struct drm_plane *plane = crtc->primary;
 890         int ret = 0;
 891         struct vc4_async_flip_state *flip_state;
 892         struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
 893         struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
 894
 895         /* Increment the BO usecnt here, so that we never end up with an
 896          * unbalanced number of vc4_bo_{dec,inc}_usecnt() calls when the
 897          * plane is later updated through the non-async path.
 898          * FIXME: we should move to generic async-page-flip when it's
 899          * available, so that we can get rid of this hand-made prepare_fb()
 900          * logic.
 901          */
 902         ret = vc4_bo_inc_usecnt(bo);
 903         if (ret)
 904                 return ret;
 905
 906         flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
 907         if (!flip_state) {
 908                 vc4_bo_dec_usecnt(bo);
 909                 return -ENOMEM;
 910         }
 911
 912         drm_framebuffer_get(fb);
 913         flip_state->fb = fb;
 914         flip_state->crtc = crtc;
 915         flip_state->event = event;
 916
 917         /* Make sure all other async modesetes have landed. */
 918         ret = down_interruptible(&vc4->async_modeset);
 919         if (ret) {
 920                 drm_framebuffer_put(fb);
 921                 vc4_bo_dec_usecnt(bo);
 922                 kfree(flip_state);
 923                 return ret;
 924         }
 925
 926         /* Save the current FB before it's replaced by the new one in
 927          * drm_atomic_set_fb_for_plane(). We'll need the old FB in
 928          * vc4_async_page_flip_complete() to decrement the BO usecnt and keep
 929          * it consistent.
 930          * FIXME: we should move to generic async-page-flip when it's
 931          * available, so that we can get rid of this hand-made cleanup_fb()
 932          * logic.
 933          */
 934         flip_state->old_fb = plane->state->fb;
 935         if (flip_state->old_fb)
 936                 drm_framebuffer_get(flip_state->old_fb);
 937
 938         WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 939
 940         /* Immediately update the plane's legacy fb pointer, so that later
 941          * modeset prep sees the state that will be present when the semaphore
 942          * is released.
 943          */
 944         drm_atomic_set_fb_for_plane(plane->state, fb);
 945
 946         vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno,
 947                            vc4_async_page_flip_complete);
 948
 949         /* Driver takes ownership of state on successful async commit. */
 950         return 0;
 951 }
 952
 953 static int vc4_page_flip(struct drm_crtc *crtc,
 954                          struct drm_framebuffer *fb,
 955                          struct drm_pending_vblank_event *event,
 956                          uint32_t flags,
 957                          struct drm_modeset_acquire_ctx *ctx)
 958 {
 959         if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
 960                 return vc4_async_page_flip(crtc, fb, event, flags);
 961         else
 962                 return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx);
 963 }
 964
 965 static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
 966 {
 967         struct vc4_crtc_state *vc4_state, *old_vc4_state;
 968
 969         vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
 970         if (!vc4_state)
 971                 return NULL;
 972
 973         old_vc4_state = to_vc4_crtc_state(crtc->state);
 974         vc4_state->feed_txp = old_vc4_state->feed_txp;
 975
 976         __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
 977         return &vc4_state->base;
 978 }
 979
 980 static void vc4_crtc_destroy_state(struct drm_crtc *crtc,
 981                                    struct drm_crtc_state *state)
 982 {
 983         struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
 984         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 985
 986         if (vc4_state->mm.allocated) {
 987                 unsigned long flags;
 988
 989                 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
 990                 drm_mm_remove_node(&vc4_state->mm);
 991                 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
 992
 993         }
 994
 995         drm_atomic_helper_crtc_destroy_state(crtc, state);
 996 }
 997
 998 static void
 999 vc4_crtc_reset(struct drm_crtc *crtc)
1000 {
1001         if (crtc->state)
1002                 __drm_atomic_helper_crtc_destroy_state(crtc->state);
1003
1004         crtc->state = kzalloc(sizeof(struct vc4_crtc_state), GFP_KERNEL);
1005         if (crtc->state)
1006                 crtc->state->crtc = crtc;
1007 }
1008
1009 static const struct drm_crtc_funcs vc4_crtc_funcs = {
1010         .set_config = drm_atomic_helper_set_config,
1011         .destroy = vc4_crtc_destroy,
1012         .page_flip = vc4_page_flip,
1013         .set_property = NULL,
1014         .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
1015         .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
1016         .reset = vc4_crtc_reset,
1017         .atomic_duplicate_state = vc4_crtc_duplicate_state,
1018         .atomic_destroy_state = vc4_crtc_destroy_state,
1019         .gamma_set = drm_atomic_helper_legacy_gamma_set,
1020         .enable_vblank = vc4_enable_vblank,
1021         .disable_vblank = vc4_disable_vblank,
1022 };
1023
1024 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
1025         .mode_set_nofb = vc4_crtc_mode_set_nofb,
1026         .mode_valid = vc4_crtc_mode_valid,
1027         .atomic_check = vc4_crtc_atomic_check,
1028         .atomic_flush = vc4_crtc_atomic_flush,
1029         .atomic_enable = vc4_crtc_atomic_enable,
1030         .atomic_disable = vc4_crtc_atomic_disable,
1031 };
1032
1033 static const struct vc4_crtc_data pv0_data = {
1034         .hvs_channel = 0,
1035         .encoder_types = {
1036                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
1037                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
1038         },
1039 };
1040
1041 static const struct vc4_crtc_data pv1_data = {
1042         .hvs_channel = 2,
1043         .encoder_types = {
1044                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
1045                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
1046         },
1047 };
1048
1049 static const struct vc4_crtc_data pv2_data = {
1050         .hvs_channel = 1,
1051         .encoder_types = {
1052                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI,
1053                 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
1054         },
1055 };
1056
1057 static const struct of_device_id vc4_crtc_dt_match[] = {
1058         { .compatible = "brcm,bcm2835-pixelvalve0", .data = &pv0_data },
1059         { .compatible = "brcm,bcm2835-pixelvalve1", .data = &pv1_data },
1060         { .compatible = "brcm,bcm2835-pixelvalve2", .data = &pv2_data },
1061         {}
1062 };
1063
1064 static void vc4_set_crtc_possible_masks(struct drm_device *drm,
1065                                         struct drm_crtc *crtc)
1066 {
1067         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
1068         const struct vc4_crtc_data *crtc_data = vc4_crtc->data;
1069         const enum vc4_encoder_type *encoder_types = crtc_data->encoder_types;
1070         struct drm_encoder *encoder;
1071
1072         drm_for_each_encoder(encoder, drm) {
1073                 struct vc4_encoder *vc4_encoder;
1074                 int i;
1075
1076                 /* HVS FIFO2 can feed the TXP IP. */
1077                 if (crtc_data->hvs_channel == 2 &&
1078                     encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL) {
1079                         encoder->possible_crtcs |= drm_crtc_mask(crtc);
1080                         continue;
1081                 }
1082
1083                 vc4_encoder = to_vc4_encoder(encoder);
1084                 for (i = 0; i < ARRAY_SIZE(crtc_data->encoder_types); i++) {
1085                         if (vc4_encoder->type == encoder_types[i]) {
1086                                 vc4_encoder->clock_select = i;
1087                                 encoder->possible_crtcs |= drm_crtc_mask(crtc);
1088                                 break;
1089                         }
1090                 }
1091         }
1092 }
1093
1094 static void
1095 vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc)
1096 {
1097         struct drm_device *drm = vc4_crtc->base.dev;
1098         struct vc4_dev *vc4 = to_vc4_dev(drm);
1099         u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel));
1100         /* Top/base are supposed to be 4-pixel aligned, but the
1101          * Raspberry Pi firmware fills the low bits (which are
1102          * presumably ignored).
1103          */
1104         u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
1105         u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
1106
1107         vc4_crtc->cob_size = top - base + 4;
1108 }
1109
1110 static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
1111 {
1112         struct platform_device *pdev = to_platform_device(dev);
1113         struct drm_device *drm = dev_get_drvdata(master);
1114         struct vc4_crtc *vc4_crtc;
1115         struct drm_crtc *crtc;
1116         struct drm_plane *primary_plane, *cursor_plane, *destroy_plane, *temp;
1117         const struct of_device_id *match;
1118         int ret, i;
1119
1120         vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
1121         if (!vc4_crtc)
1122                 return -ENOMEM;
1123         crtc = &vc4_crtc->base;
1124
1125         match = of_match_device(vc4_crtc_dt_match, dev);
1126         if (!match)
1127                 return -ENODEV;
1128         vc4_crtc->data = match->data;
1129
1130         vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
1131         if (IS_ERR(vc4_crtc->regs))
1132                 return PTR_ERR(vc4_crtc->regs);
1133
1134         /* For now, we create just the primary and the legacy cursor
1135          * planes.  We should be able to stack more planes on easily,
1136          * but to do that we would need to compute the bandwidth
1137          * requirement of the plane configuration, and reject ones
1138          * that will take too much.
1139          */
1140         primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
1141         if (IS_ERR(primary_plane)) {
1142                 dev_err(dev, "failed to construct primary plane\n");
1143                 ret = PTR_ERR(primary_plane);
1144                 goto err;
1145         }
1146
1147         drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
1148                                   &vc4_crtc_funcs, NULL);
1149         drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);
1150         vc4_crtc->channel = vc4_crtc->data->hvs_channel;
1151         drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
1152         drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);
1153
1154         /* We support CTM, but only for one CRTC at a time. It's therefore
1155          * implemented as private driver state in vc4_kms, not here.
1156          */
1157         drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size);
1158
1159         /* Set up some arbitrary number of planes.  We're not limited
1160          * by a set number of physical registers, just the space in
1161          * the HVS (16k) and how small an plane can be (28 bytes).
1162          * However, each plane we set up takes up some memory, and
1163          * increases the cost of looping over planes, which atomic
1164          * modesetting does quite a bit.  As a result, we pick a
1165          * modest number of planes to expose, that should hopefully
1166          * still cover any sane usecase.
1167          */
1168         for (i = 0; i < 8; i++) {
1169                 struct drm_plane *plane =
1170                         vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY);
1171
1172                 if (IS_ERR(plane))
1173                         continue;
1174
1175                 plane->possible_crtcs = drm_crtc_mask(crtc);
1176         }
1177
1178         /* Set up the legacy cursor after overlay initialization,
1179          * since we overlay planes on the CRTC in the order they were
1180          * initialized.
1181          */
1182         cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR);
1183         if (!IS_ERR(cursor_plane)) {
1184                 cursor_plane->possible_crtcs = drm_crtc_mask(crtc);
1185                 crtc->cursor = cursor_plane;
1186         }
1187
1188         vc4_crtc_get_cob_allocation(vc4_crtc);
1189
1190         CRTC_WRITE(PV_INTEN, 0);
1191         CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
1192         ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1193                                vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc);
1194         if (ret)
1195                 goto err_destroy_planes;
1196
1197         vc4_set_crtc_possible_masks(drm, crtc);
1198
1199         for (i = 0; i < crtc->gamma_size; i++) {
1200                 vc4_crtc->lut_r[i] = i;
1201                 vc4_crtc->lut_g[i] = i;
1202                 vc4_crtc->lut_b[i] = i;
1203         }
1204
1205         platform_set_drvdata(pdev, vc4_crtc);
1206
1207         return 0;
1208
1209 err_destroy_planes:
1210         list_for_each_entry_safe(destroy_plane, temp,
1211                                  &drm->mode_config.plane_list, head) {
1212                 if (destroy_plane->possible_crtcs == drm_crtc_mask(crtc))
1213                     destroy_plane->funcs->destroy(destroy_plane);
1214         }
1215 err:
1216         return ret;
1217 }
1218
1219 static void vc4_crtc_unbind(struct device *dev, struct device *master,
1220                             void *data)
1221 {
1222         struct platform_device *pdev = to_platform_device(dev);
1223         struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
1224
1225         vc4_crtc_destroy(&vc4_crtc->base);
1226
1227         CRTC_WRITE(PV_INTEN, 0);
1228
1229         platform_set_drvdata(pdev, NULL);
1230 }
1231
1232 static const struct component_ops vc4_crtc_ops = {
1233         .bind   = vc4_crtc_bind,
1234         .unbind = vc4_crtc_unbind,
1235 };
1236
1237 static int vc4_crtc_dev_probe(struct platform_device *pdev)
1238 {
1239         return component_add(&pdev->dev, &vc4_crtc_ops);
1240 }
1241
1242 static int vc4_crtc_dev_remove(struct platform_device *pdev)
1243 {
1244         component_del(&pdev->dev, &vc4_crtc_ops);
1245         return 0;
1246 }
1247
1248 struct platform_driver vc4_crtc_driver = {
1249         .probe = vc4_crtc_dev_probe,
1250         .remove = vc4_crtc_dev_remove,
1251         .driver = {
1252                 .name = "vc4_crtc",
1253                 .of_match_table = vc4_crtc_dt_match,
1254         },
1255 };