drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29
  30 #include "sdma0/sdma0_4_0_offset.h"
  31 #include "sdma0/sdma0_4_0_sh_mask.h"
  32 #include "sdma1/sdma1_4_0_offset.h"
  33 #include "sdma1/sdma1_4_0_sh_mask.h"
  34 #include "hdp/hdp_4_0_offset.h"
  35 #include "sdma0/sdma0_4_1_default.h"
  36
  37 #include "soc15_common.h"
  38 #include "soc15.h"
  39 #include "vega10_sdma_pkt_open.h"
  40
  41 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin");
  42 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin");
  43 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin");
  44 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin");
  45 MODULE_FIRMWARE("amdgpu/raven_sdma.bin");
  46
  47 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK  0x000000F8L
  48 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
  49
  50 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev);
  51 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev);
  52 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  53 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev);
  54
  55 static const struct soc15_reg_golden golden_settings_sdma_4[] = {
  56         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
  57         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),
  58         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100),
  59         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  60         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
  61         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  62         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000),
  63         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
  64         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  65         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
  66         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  67         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
  68         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
  69         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
  70         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100),
  71         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  72         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
  73         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  74         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000),
  75         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
  76         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  77         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
  78         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  79         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0)
  80 };
  81
  82 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = {
  83         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
  84         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
  85         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
  86         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002)
  87 };
  88
  89 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = {
  90         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
  91         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001),
  92         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
  93         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001)
  94 };
  95
  96 static const struct soc15_reg_golden golden_settings_sdma_4_1[] =
  97 {
  98         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
  99         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
 100         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100),
 101         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 102         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051),
 103         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100),
 104         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 105         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100),
 106         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 107         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0)
 108 };
 109
 110 static const struct soc15_reg_golden golden_settings_sdma_rv1[] =
 111 {
 112         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
 113         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002)
 114 };
 115
 116 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
 117                 u32 instance, u32 offset)
 118 {
 119         return ( 0 == instance ? (adev->reg_offset[SDMA0_HWIP][0][0] + offset) :
 120                         (adev->reg_offset[SDMA1_HWIP][0][0] + offset));
 121 }
 122
 123 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
 124 {
 125         switch (adev->asic_type) {
 126         case CHIP_VEGA10:
 127                 soc15_program_register_sequence(adev,
 128                                                  golden_settings_sdma_4,
 129                                                  ARRAY_SIZE(golden_settings_sdma_4));
 130                 soc15_program_register_sequence(adev,
 131                                                  golden_settings_sdma_vg10,
 132                                                  ARRAY_SIZE(golden_settings_sdma_vg10));
 133                 break;
 134         case CHIP_VEGA12:
 135                 soc15_program_register_sequence(adev,
 136                                                 golden_settings_sdma_4,
 137                                                 ARRAY_SIZE(golden_settings_sdma_4));
 138                 soc15_program_register_sequence(adev,
 139                                                 golden_settings_sdma_vg12,
 140                                                 ARRAY_SIZE(golden_settings_sdma_vg12));
 141                 break;
 142         case CHIP_RAVEN:
 143                 soc15_program_register_sequence(adev,
 144                                                  golden_settings_sdma_4_1,
 145                                                  ARRAY_SIZE(golden_settings_sdma_4_1));
 146                 soc15_program_register_sequence(adev,
 147                                                  golden_settings_sdma_rv1,
 148                                                  ARRAY_SIZE(golden_settings_sdma_rv1));
 149                 break;
 150         default:
 151                 break;
 152         }
 153 }
 154
 155 /**
 156  * sdma_v4_0_init_microcode - load ucode images from disk
 157  *
 158  * @adev: amdgpu_device pointer
 159  *
 160  * Use the firmware interface to load the ucode images into
 161  * the driver (not loaded into hw).
 162  * Returns 0 on success, error on failure.
 163  */
 164
 165 // emulation only, won't work on real chip
 166 // vega10 real chip need to use PSP to load firmware
 167 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
 168 {
 169         const char *chip_name;
 170         char fw_name[30];
 171         int err = 0, i;
 172         struct amdgpu_firmware_info *info = NULL;
 173         const struct common_firmware_header *header = NULL;
 174         const struct sdma_firmware_header_v1_0 *hdr;
 175
 176         DRM_DEBUG("\n");
 177
 178         switch (adev->asic_type) {
 179         case CHIP_VEGA10:
 180                 chip_name = "vega10";
 181                 break;
 182         case CHIP_VEGA12:
 183                 chip_name = "vega12";
 184                 break;
 185         case CHIP_RAVEN:
 186                 chip_name = "raven";
 187                 break;
 188         default:
 189                 BUG();
 190         }
 191
 192         for (i = 0; i < adev->sdma.num_instances; i++) {
 193                 if (i == 0)
 194                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 195                 else
 196                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 197                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 198                 if (err)
 199                         goto out;
 200                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 201                 if (err)
 202                         goto out;
 203                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 204                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 205                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 206                 if (adev->sdma.instance[i].feature_version >= 20)
 207                         adev->sdma.instance[i].burst_nop = true;
 208                 DRM_DEBUG("psp_load == '%s'\n",
 209                                 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
 210
 211                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 212                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 213                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 214                         info->fw = adev->sdma.instance[i].fw;
 215                         header = (const struct common_firmware_header *)info->fw->data;
 216                         adev->firmware.fw_size +=
 217                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 218                 }
 219         }
 220 out:
 221         if (err) {
 222                 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name);
 223                 for (i = 0; i < adev->sdma.num_instances; i++) {
 224                         release_firmware(adev->sdma.instance[i].fw);
 225                         adev->sdma.instance[i].fw = NULL;
 226                 }
 227         }
 228         return err;
 229 }
 230
 231 /**
 232  * sdma_v4_0_ring_get_rptr - get the current read pointer
 233  *
 234  * @ring: amdgpu ring pointer
 235  *
 236  * Get the current rptr from the hardware (VEGA10+).
 237  */
 238 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring)
 239 {
 240         u64 *rptr;
 241
 242         /* XXX check if swapping is necessary on BE */
 243         rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
 244
 245         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 246         return ((*rptr) >> 2);
 247 }
 248
 249 /**
 250  * sdma_v4_0_ring_get_wptr - get the current write pointer
 251  *
 252  * @ring: amdgpu ring pointer
 253  *
 254  * Get the current wptr from the hardware (VEGA10+).
 255  */
 256 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
 257 {
 258         struct amdgpu_device *adev = ring->adev;
 259         u64 wptr;
 260
 261         if (ring->use_doorbell) {
 262                 /* XXX check if swapping is necessary on BE */
 263                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 264                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 265         } else {
 266                 u32 lowbit, highbit;
 267                 int me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
 268
 269                 lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR)) >> 2;
 270                 highbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
 271
 272                 DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",
 273                                 me, highbit, lowbit);
 274                 wptr = highbit;
 275                 wptr = wptr << 32;
 276                 wptr |= lowbit;
 277         }
 278
 279         return wptr >> 2;
 280 }
 281
 282 /**
 283  * sdma_v4_0_ring_set_wptr - commit the write pointer
 284  *
 285  * @ring: amdgpu ring pointer
 286  *
 287  * Write the wptr back to the hardware (VEGA10+).
 288  */
 289 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
 290 {
 291         struct amdgpu_device *adev = ring->adev;
 292
 293         DRM_DEBUG("Setting write pointer\n");
 294         if (ring->use_doorbell) {
 295                 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
 296
 297                 DRM_DEBUG("Using doorbell -- "
 298                                 "wptr_offs == 0x%08x "
 299                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 300                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 301                                 ring->wptr_offs,
 302                                 lower_32_bits(ring->wptr << 2),
 303                                 upper_32_bits(ring->wptr << 2));
 304                 /* XXX check if swapping is necessary on BE */
 305                 WRITE_ONCE(*wb, (ring->wptr << 2));
 306                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 307                                 ring->doorbell_index, ring->wptr << 2);
 308                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 309         } else {
 310                 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 311
 312                 DRM_DEBUG("Not using doorbell -- "
 313                                 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 314                                 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 315                                 me,
 316                                 lower_32_bits(ring->wptr << 2),
 317                                 me,
 318                                 upper_32_bits(ring->wptr << 2));
 319                 WREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
 320                 WREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
 321         }
 322 }
 323
 324 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 325 {
 326         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 327         int i;
 328
 329         for (i = 0; i < count; i++)
 330                 if (sdma && sdma->burst_nop && (i == 0))
 331                         amdgpu_ring_write(ring, ring->funcs->nop |
 332                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 333                 else
 334                         amdgpu_ring_write(ring, ring->funcs->nop);
 335 }
 336
 337 /**
 338  * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine
 339  *
 340  * @ring: amdgpu ring pointer
 341  * @ib: IB object to schedule
 342  *
 343  * Schedule an IB in the DMA ring (VEGA10).
 344  */
 345 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
 346                                         struct amdgpu_ib *ib,
 347                                         unsigned vmid, bool ctx_switch)
 348 {
 349         /* IB packet must end on a 8 DW boundary */
 350         sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
 351
 352         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 353                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 354         /* base must be 32 byte aligned */
 355         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 356         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 357         amdgpu_ring_write(ring, ib->length_dw);
 358         amdgpu_ring_write(ring, 0);
 359         amdgpu_ring_write(ring, 0);
 360
 361 }
 362
 363 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring,
 364                                    int mem_space, int hdp,
 365                                    uint32_t addr0, uint32_t addr1,
 366                                    uint32_t ref, uint32_t mask,
 367                                    uint32_t inv)
 368 {
 369         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 370                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) |
 371                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) |
 372                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 373         if (mem_space) {
 374                 /* memory */
 375                 amdgpu_ring_write(ring, addr0);
 376                 amdgpu_ring_write(ring, addr1);
 377         } else {
 378                 /* registers */
 379                 amdgpu_ring_write(ring, addr0 << 2);
 380                 amdgpu_ring_write(ring, addr1 << 2);
 381         }
 382         amdgpu_ring_write(ring, ref); /* reference */
 383         amdgpu_ring_write(ring, mask); /* mask */
 384         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 385                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */
 386 }
 387
 388 /**
 389  * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 390  *
 391  * @ring: amdgpu ring pointer
 392  *
 393  * Emit an hdp flush packet on the requested DMA ring.
 394  */
 395 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 396 {
 397         struct amdgpu_device *adev = ring->adev;
 398         u32 ref_and_mask = 0;
 399         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
 400
 401         if (ring == &ring->adev->sdma.instance[0].ring)
 402                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
 403         else
 404                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
 405
 406         sdma_v4_0_wait_reg_mem(ring, 0, 1,
 407                                adev->nbio_funcs->get_hdp_flush_done_offset(adev),
 408                                adev->nbio_funcs->get_hdp_flush_req_offset(adev),
 409                                ref_and_mask, ref_and_mask, 10);
 410 }
 411
 412 /**
 413  * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring
 414  *
 415  * @ring: amdgpu ring pointer
 416  * @fence: amdgpu fence object
 417  *
 418  * Add a DMA fence packet to the ring to write
 419  * the fence seq number and DMA trap packet to generate
 420  * an interrupt if needed (VEGA10).
 421  */
 422 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 423                                       unsigned flags)
 424 {
 425         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 426         /* write the fence */
 427         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 428         /* zero in first two bits */
 429         BUG_ON(addr & 0x3);
 430         amdgpu_ring_write(ring, lower_32_bits(addr));
 431         amdgpu_ring_write(ring, upper_32_bits(addr));
 432         amdgpu_ring_write(ring, lower_32_bits(seq));
 433
 434         /* optionally write high bits as well */
 435         if (write64bit) {
 436                 addr += 4;
 437                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 438                 /* zero in first two bits */
 439                 BUG_ON(addr & 0x3);
 440                 amdgpu_ring_write(ring, lower_32_bits(addr));
 441                 amdgpu_ring_write(ring, upper_32_bits(addr));
 442                 amdgpu_ring_write(ring, upper_32_bits(seq));
 443         }
 444
 445         /* generate an interrupt */
 446         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 447         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 448 }
 449
 450
 451 /**
 452  * sdma_v4_0_gfx_stop - stop the gfx async dma engines
 453  *
 454  * @adev: amdgpu_device pointer
 455  *
 456  * Stop the gfx async dma ring buffers (VEGA10).
 457  */
 458 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev)
 459 {
 460         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 461         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 462         u32 rb_cntl, ib_cntl;
 463         int i;
 464
 465         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 466             (adev->mman.buffer_funcs_ring == sdma1))
 467                         amdgpu_ttm_set_buffer_funcs_status(adev, false);
 468
 469         for (i = 0; i < adev->sdma.num_instances; i++) {
 470                 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 471                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 472                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 473                 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 474                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 475                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 476         }
 477
 478         sdma0->ready = false;
 479         sdma1->ready = false;
 480 }
 481
 482 /**
 483  * sdma_v4_0_rlc_stop - stop the compute async dma engines
 484  *
 485  * @adev: amdgpu_device pointer
 486  *
 487  * Stop the compute async dma queues (VEGA10).
 488  */
 489 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev)
 490 {
 491         /* XXX todo */
 492 }
 493
 494 /**
 495  * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
 496  *
 497  * @adev: amdgpu_device pointer
 498  * @enable: enable/disable the DMA MEs context switch.
 499  *
 500  * Halt or unhalt the async dma engines context switch (VEGA10).
 501  */
 502 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 503 {
 504         u32 f32_cntl, phase_quantum = 0;
 505         int i;
 506
 507         if (amdgpu_sdma_phase_quantum) {
 508                 unsigned value = amdgpu_sdma_phase_quantum;
 509                 unsigned unit = 0;
 510
 511                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 512                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 513                         value = (value + 1) >> 1;
 514                         unit++;
 515                 }
 516                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 517                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 518                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 519                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 520                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 521                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 522                         WARN_ONCE(1,
 523                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 524                                   value << unit);
 525                 }
 526                 phase_quantum =
 527                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 528                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 529         }
 530
 531         for (i = 0; i < adev->sdma.num_instances; i++) {
 532                 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
 533                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 534                                 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 535                 if (enable && amdgpu_sdma_phase_quantum) {
 536                         WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
 537                                phase_quantum);
 538                         WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
 539                                phase_quantum);
 540                         WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
 541                                phase_quantum);
 542                 }
 543                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
 544         }
 545
 546 }
 547
 548 /**
 549  * sdma_v4_0_enable - stop the async dma engines
 550  *
 551  * @adev: amdgpu_device pointer
 552  * @enable: enable/disable the DMA MEs.
 553  *
 554  * Halt or unhalt the async dma engines (VEGA10).
 555  */
 556 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable)
 557 {
 558         u32 f32_cntl;
 559         int i;
 560
 561         if (enable == false) {
 562                 sdma_v4_0_gfx_stop(adev);
 563                 sdma_v4_0_rlc_stop(adev);
 564         }
 565
 566         for (i = 0; i < adev->sdma.num_instances; i++) {
 567                 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 568                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 569                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
 570         }
 571 }
 572
 573 /**
 574  * sdma_v4_0_gfx_resume - setup and start the async dma engines
 575  *
 576  * @adev: amdgpu_device pointer
 577  *
 578  * Set up the gfx DMA ring buffers and enable them (VEGA10).
 579  * Returns 0 for success, error for failure.
 580  */
 581 static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
 582 {
 583         struct amdgpu_ring *ring;
 584         u32 rb_cntl, ib_cntl, wptr_poll_cntl;
 585         u32 rb_bufsz;
 586         u32 wb_offset;
 587         u32 doorbell;
 588         u32 doorbell_offset;
 589         u32 temp;
 590         u64 wptr_gpu_addr;
 591         int i, r;
 592
 593         for (i = 0; i < adev->sdma.num_instances; i++) {
 594                 ring = &adev->sdma.instance[i].ring;
 595                 wb_offset = (ring->rptr_offs * 4);
 596
 597                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 598
 599                 /* Set ring buffer size in dwords */
 600                 rb_bufsz = order_base_2(ring->ring_size / 4);
 601                 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 602                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 603 #ifdef __BIG_ENDIAN
 604                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 605                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 606                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 607 #endif
 608                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 609
 610                 /* Initialize the ring buffer's read and write pointers */
 611                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
 612                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
 613                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
 614                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 615
 616                 /* set the wb address whether it's enabled or not */
 617                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
 618                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 619                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
 620                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 621
 622                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 623
 624                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
 625                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
 626
 627                 ring->wptr = 0;
 628
 629                 /* before programing wptr to a less value, need set minor_ptr_update first */
 630                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
 631
 632                 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 633                         WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
 634                         WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
 635                 }
 636
 637                 doorbell = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
 638                 doorbell_offset = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
 639
 640                 if (ring->use_doorbell) {
 641                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 642                         doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
 643                                         OFFSET, ring->doorbell_index);
 644                 } else {
 645                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 646                 }
 647                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
 648                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
 649                 adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 650                                                       ring->doorbell_index);
 651
 652                 if (amdgpu_sriov_vf(adev))
 653                         sdma_v4_0_ring_set_wptr(ring);
 654
 655                 /* set minor_ptr_update to 0 after wptr programed */
 656                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
 657
 658                 /* set utc l1 enable flag always to 1 */
 659                 temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
 660                 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
 661                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
 662
 663                 if (!amdgpu_sriov_vf(adev)) {
 664                         /* unhalt engine */
 665                         temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 666                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
 667                         WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
 668                 }
 669
 670                 /* setup the wptr shadow polling */
 671                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 672                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
 673                        lower_32_bits(wptr_gpu_addr));
 674                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
 675                        upper_32_bits(wptr_gpu_addr));
 676                 wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 677                 if (amdgpu_sriov_vf(adev))
 678                         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1);
 679                 else
 680                         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0);
 681                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl);
 682
 683                 /* enable DMA RB */
 684                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 685                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 686
 687                 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 688                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 689 #ifdef __BIG_ENDIAN
 690                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 691 #endif
 692                 /* enable DMA IBs */
 693                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 694
 695                 ring->ready = true;
 696
 697                 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
 698                         sdma_v4_0_ctx_switch_enable(adev, true);
 699                         sdma_v4_0_enable(adev, true);
 700                 }
 701
 702                 r = amdgpu_ring_test_ring(ring);
 703                 if (r) {
 704                         ring->ready = false;
 705                         return r;
 706                 }
 707
 708                 if (adev->mman.buffer_funcs_ring == ring)
 709                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 710
 711         }
 712
 713         return 0;
 714 }
 715
 716 static void
 717 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable)
 718 {
 719         uint32_t def, data;
 720
 721         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) {
 722                 /* disable idle interrupt */
 723                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
 724                 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
 725
 726                 if (data != def)
 727                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
 728         } else {
 729                 /* disable idle interrupt */
 730                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
 731                 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
 732                 if (data != def)
 733                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
 734         }
 735 }
 736
 737 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev)
 738 {
 739         uint32_t def, data;
 740
 741         /* Enable HW based PG. */
 742         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
 743         data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK;
 744         if (data != def)
 745                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
 746
 747         /* enable interrupt */
 748         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
 749         data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
 750         if (data != def)
 751                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
 752
 753         /* Configure hold time to filter in-valid power on/off request. Use default right now */
 754         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
 755         data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK;
 756         data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK);
 757         /* Configure switch time for hysteresis purpose. Use default right now */
 758         data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK;
 759         data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK);
 760         if(data != def)
 761                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
 762 }
 763
 764 static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
 765 {
 766         if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA))
 767                 return;
 768
 769         switch (adev->asic_type) {
 770         case CHIP_RAVEN:
 771                 sdma_v4_1_init_power_gating(adev);
 772                 sdma_v4_1_update_power_gating(adev, true);
 773                 break;
 774         default:
 775                 break;
 776         }
 777 }
 778
 779 /**
 780  * sdma_v4_0_rlc_resume - setup and start the async dma engines
 781  *
 782  * @adev: amdgpu_device pointer
 783  *
 784  * Set up the compute DMA queues and enable them (VEGA10).
 785  * Returns 0 for success, error for failure.
 786  */
 787 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev)
 788 {
 789         sdma_v4_0_init_pg(adev);
 790
 791         return 0;
 792 }
 793
 794 /**
 795  * sdma_v4_0_load_microcode - load the sDMA ME ucode
 796  *
 797  * @adev: amdgpu_device pointer
 798  *
 799  * Loads the sDMA0/1 ucode.
 800  * Returns 0 for success, -EINVAL if the ucode is not available.
 801  */
 802 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev)
 803 {
 804         const struct sdma_firmware_header_v1_0 *hdr;
 805         const __le32 *fw_data;
 806         u32 fw_size;
 807         int i, j;
 808
 809         /* halt the MEs */
 810         sdma_v4_0_enable(adev, false);
 811
 812         for (i = 0; i < adev->sdma.num_instances; i++) {
 813                 if (!adev->sdma.instance[i].fw)
 814                         return -EINVAL;
 815
 816                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 817                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 818                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 819
 820                 fw_data = (const __le32 *)
 821                         (adev->sdma.instance[i].fw->data +
 822                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 823
 824                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
 825
 826                 for (j = 0; j < fw_size; j++)
 827                         WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 828
 829                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
 830         }
 831
 832         return 0;
 833 }
 834
 835 /**
 836  * sdma_v4_0_start - setup and start the async dma engines
 837  *
 838  * @adev: amdgpu_device pointer
 839  *
 840  * Set up the DMA engines and enable them (VEGA10).
 841  * Returns 0 for success, error for failure.
 842  */
 843 static int sdma_v4_0_start(struct amdgpu_device *adev)
 844 {
 845         int r = 0;
 846
 847         if (amdgpu_sriov_vf(adev)) {
 848                 sdma_v4_0_ctx_switch_enable(adev, false);
 849                 sdma_v4_0_enable(adev, false);
 850
 851                 /* set RB registers */
 852                 r = sdma_v4_0_gfx_resume(adev);
 853                 return r;
 854         }
 855
 856         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 857                 r = sdma_v4_0_load_microcode(adev);
 858                 if (r)
 859                         return r;
 860         }
 861
 862         /* unhalt the MEs */
 863         sdma_v4_0_enable(adev, true);
 864         /* enable sdma ring preemption */
 865         sdma_v4_0_ctx_switch_enable(adev, true);
 866
 867         /* start the gfx rings and rlc compute queues */
 868         r = sdma_v4_0_gfx_resume(adev);
 869         if (r)
 870                 return r;
 871         r = sdma_v4_0_rlc_resume(adev);
 872
 873         return r;
 874 }
 875
 876 /**
 877  * sdma_v4_0_ring_test_ring - simple async dma engine test
 878  *
 879  * @ring: amdgpu_ring structure holding ring information
 880  *
 881  * Test the DMA engine by writing using it to write an
 882  * value to memory. (VEGA10).
 883  * Returns 0 for success, error for failure.
 884  */
 885 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring)
 886 {
 887         struct amdgpu_device *adev = ring->adev;
 888         unsigned i;
 889         unsigned index;
 890         int r;
 891         u32 tmp;
 892         u64 gpu_addr;
 893
 894         r = amdgpu_device_wb_get(adev, &index);
 895         if (r) {
 896                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 897                 return r;
 898         }
 899
 900         gpu_addr = adev->wb.gpu_addr + (index * 4);
 901         tmp = 0xCAFEDEAD;
 902         adev->wb.wb[index] = cpu_to_le32(tmp);
 903
 904         r = amdgpu_ring_alloc(ring, 5);
 905         if (r) {
 906                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 907                 amdgpu_device_wb_free(adev, index);
 908                 return r;
 909         }
 910
 911         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 912                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 913         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 914         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 915         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 916         amdgpu_ring_write(ring, 0xDEADBEEF);
 917         amdgpu_ring_commit(ring);
 918
 919         for (i = 0; i < adev->usec_timeout; i++) {
 920                 tmp = le32_to_cpu(adev->wb.wb[index]);
 921                 if (tmp == 0xDEADBEEF)
 922                         break;
 923                 DRM_UDELAY(1);
 924         }
 925
 926         if (i < adev->usec_timeout) {
 927                 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 928         } else {
 929                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 930                           ring->idx, tmp);
 931                 r = -EINVAL;
 932         }
 933         amdgpu_device_wb_free(adev, index);
 934
 935         return r;
 936 }
 937
 938 /**
 939  * sdma_v4_0_ring_test_ib - test an IB on the DMA engine
 940  *
 941  * @ring: amdgpu_ring structure holding ring information
 942  *
 943  * Test a simple IB in the DMA ring (VEGA10).
 944  * Returns 0 on success, error on failure.
 945  */
 946 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 947 {
 948         struct amdgpu_device *adev = ring->adev;
 949         struct amdgpu_ib ib;
 950         struct dma_fence *f = NULL;
 951         unsigned index;
 952         long r;
 953         u32 tmp = 0;
 954         u64 gpu_addr;
 955
 956         r = amdgpu_device_wb_get(adev, &index);
 957         if (r) {
 958                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 959                 return r;
 960         }
 961
 962         gpu_addr = adev->wb.gpu_addr + (index * 4);
 963         tmp = 0xCAFEDEAD;
 964         adev->wb.wb[index] = cpu_to_le32(tmp);
 965         memset(&ib, 0, sizeof(ib));
 966         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 967         if (r) {
 968                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 969                 goto err0;
 970         }
 971
 972         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 973                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 974         ib.ptr[1] = lower_32_bits(gpu_addr);
 975         ib.ptr[2] = upper_32_bits(gpu_addr);
 976         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
 977         ib.ptr[4] = 0xDEADBEEF;
 978         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 979         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 980         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 981         ib.length_dw = 8;
 982
 983         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 984         if (r)
 985                 goto err1;
 986
 987         r = dma_fence_wait_timeout(f, false, timeout);
 988         if (r == 0) {
 989                 DRM_ERROR("amdgpu: IB test timed out\n");
 990                 r = -ETIMEDOUT;
 991                 goto err1;
 992         } else if (r < 0) {
 993                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 994                 goto err1;
 995         }
 996         tmp = le32_to_cpu(adev->wb.wb[index]);
 997         if (tmp == 0xDEADBEEF) {
 998                 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
 999                 r = 0;
1000         } else {
1001                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
1002                 r = -EINVAL;
1003         }
1004 err1:
1005         amdgpu_ib_free(adev, &ib, NULL);
1006         dma_fence_put(f);
1007 err0:
1008         amdgpu_device_wb_free(adev, index);
1009         return r;
1010 }
1011
1012
1013 /**
1014  * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART
1015  *
1016  * @ib: indirect buffer to fill with commands
1017  * @pe: addr of the page entry
1018  * @src: src addr to copy from
1019  * @count: number of page entries to update
1020  *
1021  * Update PTEs by copying them from the GART using sDMA (VEGA10).
1022  */
1023 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib,
1024                                   uint64_t pe, uint64_t src,
1025                                   unsigned count)
1026 {
1027         unsigned bytes = count * 8;
1028
1029         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1030                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1031         ib->ptr[ib->length_dw++] = bytes - 1;
1032         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1033         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1034         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1035         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1036         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1037
1038 }
1039
1040 /**
1041  * sdma_v4_0_vm_write_pte - update PTEs by writing them manually
1042  *
1043  * @ib: indirect buffer to fill with commands
1044  * @pe: addr of the page entry
1045  * @addr: dst addr to write into pe
1046  * @count: number of page entries to update
1047  * @incr: increase next addr by incr bytes
1048  * @flags: access flags
1049  *
1050  * Update PTEs by writing them manually using sDMA (VEGA10).
1051  */
1052 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1053                                    uint64_t value, unsigned count,
1054                                    uint32_t incr)
1055 {
1056         unsigned ndw = count * 2;
1057
1058         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1059                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1060         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1061         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1062         ib->ptr[ib->length_dw++] = ndw - 1;
1063         for (; ndw > 0; ndw -= 2) {
1064                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1065                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1066                 value += incr;
1067         }
1068 }
1069
1070 /**
1071  * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA
1072  *
1073  * @ib: indirect buffer to fill with commands
1074  * @pe: addr of the page entry
1075  * @addr: dst addr to write into pe
1076  * @count: number of page entries to update
1077  * @incr: increase next addr by incr bytes
1078  * @flags: access flags
1079  *
1080  * Update the page tables using sDMA (VEGA10).
1081  */
1082 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1083                                      uint64_t pe,
1084                                      uint64_t addr, unsigned count,
1085                                      uint32_t incr, uint64_t flags)
1086 {
1087         /* for physically contiguous pages (vram) */
1088         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1089         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1090         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1091         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1092         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1093         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1094         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1095         ib->ptr[ib->length_dw++] = incr; /* increment size */
1096         ib->ptr[ib->length_dw++] = 0;
1097         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1098 }
1099
1100 /**
1101  * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw
1102  *
1103  * @ib: indirect buffer to fill with padding
1104  *
1105  */
1106 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1107 {
1108         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
1109         u32 pad_count;
1110         int i;
1111
1112         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
1113         for (i = 0; i < pad_count; i++)
1114                 if (sdma && sdma->burst_nop && (i == 0))
1115                         ib->ptr[ib->length_dw++] =
1116                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1117                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1118                 else
1119                         ib->ptr[ib->length_dw++] =
1120                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1121 }
1122
1123
1124 /**
1125  * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline
1126  *
1127  * @ring: amdgpu_ring pointer
1128  *
1129  * Make sure all previous operations are completed (CIK).
1130  */
1131 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1132 {
1133         uint32_t seq = ring->fence_drv.sync_seq;
1134         uint64_t addr = ring->fence_drv.gpu_addr;
1135
1136         /* wait for idle */
1137         sdma_v4_0_wait_reg_mem(ring, 1, 0,
1138                                addr & 0xfffffffc,
1139                                upper_32_bits(addr) & 0xffffffff,
1140                                seq, 0xffffffff, 4);
1141 }
1142
1143
1144 /**
1145  * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA
1146  *
1147  * @ring: amdgpu_ring pointer
1148  * @vm: amdgpu_vm pointer
1149  *
1150  * Update the page table base and flush the VM TLB
1151  * using sDMA (VEGA10).
1152  */
1153 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1154                                          unsigned vmid, uint64_t pd_addr)
1155 {
1156         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1157 }
1158
1159 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring,
1160                                      uint32_t reg, uint32_t val)
1161 {
1162         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1163                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1164         amdgpu_ring_write(ring, reg);
1165         amdgpu_ring_write(ring, val);
1166 }
1167
1168 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1169                                          uint32_t val, uint32_t mask)
1170 {
1171         sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);
1172 }
1173
1174 static int sdma_v4_0_early_init(void *handle)
1175 {
1176         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1177
1178         if (adev->asic_type == CHIP_RAVEN)
1179                 adev->sdma.num_instances = 1;
1180         else
1181                 adev->sdma.num_instances = 2;
1182
1183         sdma_v4_0_set_ring_funcs(adev);
1184         sdma_v4_0_set_buffer_funcs(adev);
1185         sdma_v4_0_set_vm_pte_funcs(adev);
1186         sdma_v4_0_set_irq_funcs(adev);
1187
1188         return 0;
1189 }
1190
1191
1192 static int sdma_v4_0_sw_init(void *handle)
1193 {
1194         struct amdgpu_ring *ring;
1195         int r, i;
1196         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1197
1198         /* SDMA trap event */
1199         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, 224,
1200                               &adev->sdma.trap_irq);
1201         if (r)
1202                 return r;
1203
1204         /* SDMA trap event */
1205         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, 224,
1206                               &adev->sdma.trap_irq);
1207         if (r)
1208                 return r;
1209
1210         r = sdma_v4_0_init_microcode(adev);
1211         if (r) {
1212                 DRM_ERROR("Failed to load sdma firmware!\n");
1213                 return r;
1214         }
1215
1216         for (i = 0; i < adev->sdma.num_instances; i++) {
1217                 ring = &adev->sdma.instance[i].ring;
1218                 ring->ring_obj = NULL;
1219                 ring->use_doorbell = true;
1220
1221                 DRM_INFO("use_doorbell being set to: [%s]\n",
1222                                 ring->use_doorbell?"true":"false");
1223
1224                 ring->doorbell_index = (i == 0) ?
1225                         (AMDGPU_DOORBELL64_sDMA_ENGINE0 << 1) //get DWORD offset
1226                         : (AMDGPU_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD offset
1227
1228                 sprintf(ring->name, "sdma%d", i);
1229                 r = amdgpu_ring_init(adev, ring, 1024,
1230                                      &adev->sdma.trap_irq,
1231                                      (i == 0) ?
1232                                      AMDGPU_SDMA_IRQ_TRAP0 :
1233                                      AMDGPU_SDMA_IRQ_TRAP1);
1234                 if (r)
1235                         return r;
1236         }
1237
1238         return r;
1239 }
1240
1241 static int sdma_v4_0_sw_fini(void *handle)
1242 {
1243         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1244         int i;
1245
1246         for (i = 0; i < adev->sdma.num_instances; i++)
1247                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1248
1249         for (i = 0; i < adev->sdma.num_instances; i++) {
1250                 release_firmware(adev->sdma.instance[i].fw);
1251                 adev->sdma.instance[i].fw = NULL;
1252         }
1253
1254         return 0;
1255 }
1256
1257 static int sdma_v4_0_hw_init(void *handle)
1258 {
1259         int r;
1260         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1261
1262         sdma_v4_0_init_golden_registers(adev);
1263
1264         r = sdma_v4_0_start(adev);
1265
1266         return r;
1267 }
1268
1269 static int sdma_v4_0_hw_fini(void *handle)
1270 {
1271         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1272
1273         if (amdgpu_sriov_vf(adev))
1274                 return 0;
1275
1276         sdma_v4_0_ctx_switch_enable(adev, false);
1277         sdma_v4_0_enable(adev, false);
1278
1279         return 0;
1280 }
1281
1282 static int sdma_v4_0_suspend(void *handle)
1283 {
1284         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1285
1286         return sdma_v4_0_hw_fini(adev);
1287 }
1288
1289 static int sdma_v4_0_resume(void *handle)
1290 {
1291         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1292
1293         return sdma_v4_0_hw_init(adev);
1294 }
1295
1296 static bool sdma_v4_0_is_idle(void *handle)
1297 {
1298         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1299         u32 i;
1300
1301         for (i = 0; i < adev->sdma.num_instances; i++) {
1302                 u32 tmp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1303
1304                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1305                         return false;
1306         }
1307
1308         return true;
1309 }
1310
1311 static int sdma_v4_0_wait_for_idle(void *handle)
1312 {
1313         unsigned i;
1314         u32 sdma0, sdma1;
1315         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1316
1317         for (i = 0; i < adev->usec_timeout; i++) {
1318                 sdma0 = RREG32(sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1319                 sdma1 = RREG32(sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1320
1321                 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1322                         return 0;
1323                 udelay(1);
1324         }
1325         return -ETIMEDOUT;
1326 }
1327
1328 static int sdma_v4_0_soft_reset(void *handle)
1329 {
1330         /* todo */
1331
1332         return 0;
1333 }
1334
1335 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev,
1336                                         struct amdgpu_irq_src *source,
1337                                         unsigned type,
1338                                         enum amdgpu_interrupt_state state)
1339 {
1340         u32 sdma_cntl;
1341
1342         u32 reg_offset = (type == AMDGPU_SDMA_IRQ_TRAP0) ?
1343                 sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :
1344                 sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_CNTL);
1345
1346         sdma_cntl = RREG32(reg_offset);
1347         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1348                        state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1349         WREG32(reg_offset, sdma_cntl);
1350
1351         return 0;
1352 }
1353
1354 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
1355                                       struct amdgpu_irq_src *source,
1356                                       struct amdgpu_iv_entry *entry)
1357 {
1358         DRM_DEBUG("IH: SDMA trap\n");
1359         switch (entry->client_id) {
1360         case SOC15_IH_CLIENTID_SDMA0:
1361                 switch (entry->ring_id) {
1362                 case 0:
1363                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1364                         break;
1365                 case 1:
1366                         /* XXX compute */
1367                         break;
1368                 case 2:
1369                         /* XXX compute */
1370                         break;
1371                 case 3:
1372                         /* XXX page queue*/
1373                         break;
1374                 }
1375                 break;
1376         case SOC15_IH_CLIENTID_SDMA1:
1377                 switch (entry->ring_id) {
1378                 case 0:
1379                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1380                         break;
1381                 case 1:
1382                         /* XXX compute */
1383                         break;
1384                 case 2:
1385                         /* XXX compute */
1386                         break;
1387                 case 3:
1388                         /* XXX page queue*/
1389                         break;
1390                 }
1391                 break;
1392         }
1393         return 0;
1394 }
1395
1396 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1397                                               struct amdgpu_irq_src *source,
1398                                               struct amdgpu_iv_entry *entry)
1399 {
1400         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1401         schedule_work(&adev->reset_work);
1402         return 0;
1403 }
1404
1405
1406 static void sdma_v4_0_update_medium_grain_clock_gating(
1407                 struct amdgpu_device *adev,
1408                 bool enable)
1409 {
1410         uint32_t data, def;
1411
1412         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1413                 /* enable sdma0 clock gating */
1414                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
1415                 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1416                           SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1417                           SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1418                           SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1419                           SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1420                           SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1421                           SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1422                           SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1423                 if (def != data)
1424                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);
1425
1426                 if (adev->sdma.num_instances > 1) {
1427                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));
1428                         data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1429                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1430                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1431                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1432                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1433                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1434                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1435                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1436                         if (def != data)
1437                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);
1438                 }
1439         } else {
1440                 /* disable sdma0 clock gating */
1441                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
1442                 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1443                          SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1444                          SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1445                          SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1446                          SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1447                          SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1448                          SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1449                          SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1450
1451                 if (def != data)
1452                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);
1453
1454                 if (adev->sdma.num_instances > 1) {
1455                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));
1456                         data |= (SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1457                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1458                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1459                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1460                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1461                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1462                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1463                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1464                         if (def != data)
1465                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);
1466                 }
1467         }
1468 }
1469
1470
1471 static void sdma_v4_0_update_medium_grain_light_sleep(
1472                 struct amdgpu_device *adev,
1473                 bool enable)
1474 {
1475         uint32_t data, def;
1476
1477         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1478                 /* 1-not override: enable sdma0 mem light sleep */
1479                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1480                 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1481                 if (def != data)
1482                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1483
1484                 /* 1-not override: enable sdma1 mem light sleep */
1485                 if (adev->sdma.num_instances > 1) {
1486                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));
1487                         data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1488                         if (def != data)
1489                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);
1490                 }
1491         } else {
1492                 /* 0-override:disable sdma0 mem light sleep */
1493                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1494                 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1495                 if (def != data)
1496                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1497
1498                 /* 0-override:disable sdma1 mem light sleep */
1499                 if (adev->sdma.num_instances > 1) {
1500                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));
1501                         data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1502                         if (def != data)
1503                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);
1504                 }
1505         }
1506 }
1507
1508 static int sdma_v4_0_set_clockgating_state(void *handle,
1509                                           enum amd_clockgating_state state)
1510 {
1511         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1512
1513         if (amdgpu_sriov_vf(adev))
1514                 return 0;
1515
1516         switch (adev->asic_type) {
1517         case CHIP_VEGA10:
1518         case CHIP_VEGA12:
1519         case CHIP_RAVEN:
1520                 sdma_v4_0_update_medium_grain_clock_gating(adev,
1521                                 state == AMD_CG_STATE_GATE ? true : false);
1522                 sdma_v4_0_update_medium_grain_light_sleep(adev,
1523                                 state == AMD_CG_STATE_GATE ? true : false);
1524                 break;
1525         default:
1526                 break;
1527         }
1528         return 0;
1529 }
1530
1531 static int sdma_v4_0_set_powergating_state(void *handle,
1532                                           enum amd_powergating_state state)
1533 {
1534         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1535
1536         switch (adev->asic_type) {
1537         case CHIP_RAVEN:
1538                 sdma_v4_1_update_power_gating(adev,
1539                                 state == AMD_PG_STATE_GATE ? true : false);
1540                 break;
1541         default:
1542                 break;
1543         }
1544
1545         return 0;
1546 }
1547
1548 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags)
1549 {
1550         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1551         int data;
1552
1553         if (amdgpu_sriov_vf(adev))
1554                 *flags = 0;
1555
1556         /* AMD_CG_SUPPORT_SDMA_MGCG */
1557         data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
1558         if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
1559                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1560
1561         /* AMD_CG_SUPPORT_SDMA_LS */
1562         data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1563         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1564                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1565 }
1566
1567 const struct amd_ip_funcs sdma_v4_0_ip_funcs = {
1568         .name = "sdma_v4_0",
1569         .early_init = sdma_v4_0_early_init,
1570         .late_init = NULL,
1571         .sw_init = sdma_v4_0_sw_init,
1572         .sw_fini = sdma_v4_0_sw_fini,
1573         .hw_init = sdma_v4_0_hw_init,
1574         .hw_fini = sdma_v4_0_hw_fini,
1575         .suspend = sdma_v4_0_suspend,
1576         .resume = sdma_v4_0_resume,
1577         .is_idle = sdma_v4_0_is_idle,
1578         .wait_for_idle = sdma_v4_0_wait_for_idle,
1579         .soft_reset = sdma_v4_0_soft_reset,
1580         .set_clockgating_state = sdma_v4_0_set_clockgating_state,
1581         .set_powergating_state = sdma_v4_0_set_powergating_state,
1582         .get_clockgating_state = sdma_v4_0_get_clockgating_state,
1583 };
1584
1585 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
1586         .type = AMDGPU_RING_TYPE_SDMA,
1587         .align_mask = 0xf,
1588         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1589         .support_64bit_ptrs = true,
1590         .vmhub = AMDGPU_MMHUB,
1591         .get_rptr = sdma_v4_0_ring_get_rptr,
1592         .get_wptr = sdma_v4_0_ring_get_wptr,
1593         .set_wptr = sdma_v4_0_ring_set_wptr,
1594         .emit_frame_size =
1595                 6 + /* sdma_v4_0_ring_emit_hdp_flush */
1596                 3 + /* hdp invalidate */
1597                 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
1598                 /* sdma_v4_0_ring_emit_vm_flush */
1599                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1600                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1601                 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
1602         .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
1603         .emit_ib = sdma_v4_0_ring_emit_ib,
1604         .emit_fence = sdma_v4_0_ring_emit_fence,
1605         .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
1606         .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
1607         .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
1608         .test_ring = sdma_v4_0_ring_test_ring,
1609         .test_ib = sdma_v4_0_ring_test_ib,
1610         .insert_nop = sdma_v4_0_ring_insert_nop,
1611         .pad_ib = sdma_v4_0_ring_pad_ib,
1612         .emit_wreg = sdma_v4_0_ring_emit_wreg,
1613         .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
1614         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1615 };
1616
1617 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
1618 {
1619         int i;
1620
1621         for (i = 0; i < adev->sdma.num_instances; i++)
1622                 adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs;
1623 }
1624
1625 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = {
1626         .set = sdma_v4_0_set_trap_irq_state,
1627         .process = sdma_v4_0_process_trap_irq,
1628 };
1629
1630 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = {
1631         .process = sdma_v4_0_process_illegal_inst_irq,
1632 };
1633
1634 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev)
1635 {
1636         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1637         adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs;
1638         adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs;
1639 }
1640
1641 /**
1642  * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine
1643  *
1644  * @ring: amdgpu_ring structure holding ring information
1645  * @src_offset: src GPU address
1646  * @dst_offset: dst GPU address
1647  * @byte_count: number of bytes to xfer
1648  *
1649  * Copy GPU buffers using the DMA engine (VEGA10/12).
1650  * Used by the amdgpu ttm implementation to move pages if
1651  * registered as the asic copy callback.
1652  */
1653 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib,
1654                                        uint64_t src_offset,
1655                                        uint64_t dst_offset,
1656                                        uint32_t byte_count)
1657 {
1658         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1659                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1660         ib->ptr[ib->length_dw++] = byte_count - 1;
1661         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1662         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1663         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1664         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1665         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1666 }
1667
1668 /**
1669  * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine
1670  *
1671  * @ring: amdgpu_ring structure holding ring information
1672  * @src_data: value to write to buffer
1673  * @dst_offset: dst GPU address
1674  * @byte_count: number of bytes to xfer
1675  *
1676  * Fill GPU buffers using the DMA engine (VEGA10/12).
1677  */
1678 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib,
1679                                        uint32_t src_data,
1680                                        uint64_t dst_offset,
1681                                        uint32_t byte_count)
1682 {
1683         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1684         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1685         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1686         ib->ptr[ib->length_dw++] = src_data;
1687         ib->ptr[ib->length_dw++] = byte_count - 1;
1688 }
1689
1690 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = {
1691         .copy_max_bytes = 0x400000,
1692         .copy_num_dw = 7,
1693         .emit_copy_buffer = sdma_v4_0_emit_copy_buffer,
1694
1695         .fill_max_bytes = 0x400000,
1696         .fill_num_dw = 5,
1697         .emit_fill_buffer = sdma_v4_0_emit_fill_buffer,
1698 };
1699
1700 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev)
1701 {
1702         if (adev->mman.buffer_funcs == NULL) {
1703                 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
1704                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1705         }
1706 }
1707
1708 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = {
1709         .copy_pte_num_dw = 7,
1710         .copy_pte = sdma_v4_0_vm_copy_pte,
1711
1712         .write_pte = sdma_v4_0_vm_write_pte,
1713         .set_pte_pde = sdma_v4_0_vm_set_pte_pde,
1714 };
1715
1716 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1717 {
1718         unsigned i;
1719
1720         if (adev->vm_manager.vm_pte_funcs == NULL) {
1721                 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
1722                 for (i = 0; i < adev->sdma.num_instances; i++)
1723                         adev->vm_manager.vm_pte_rings[i] =
1724                                 &adev->sdma.instance[i].ring;
1725
1726                 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1727         }
1728 }
1729
1730 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = {
1731         .type = AMD_IP_BLOCK_TYPE_SDMA,
1732         .major = 4,
1733         .minor = 0,
1734         .rev = 0,
1735         .funcs = &sdma_v4_0_ip_funcs,
1736 };