drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <[email protected]>
  23  *          Alex Deucher <[email protected]>
  24  */
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_drv.h"
  28 #include "amdgpu_pm.h"
  29 #include "amdgpu_dpm.h"
  30 #include "atom.h"
  31 #include <linux/power_supply.h>
  32 #include <linux/hwmon.h>
  33 #include <linux/hwmon-sysfs.h>
  34
  35
  36 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
  37
  38 static const struct cg_flag_name clocks[] = {
  39         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  40         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  41         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  42         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  43         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  44         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  45         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  46         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  47         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
  48         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
  49         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  50         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  51         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  52         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  53         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
  54         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  55         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  56         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  57         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  58         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  59         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
  60         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
  61         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  62         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
  63         {0, NULL},
  64 };
  65
  66 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  67 {
  68         if (adev->pm.dpm_enabled) {
  69                 mutex_lock(&adev->pm.mutex);
  70                 if (power_supply_is_system_supplied() > 0)
  71                         adev->pm.dpm.ac_power = true;
  72                 else
  73                         adev->pm.dpm.ac_power = false;
  74                 if (adev->powerplay.pp_funcs->enable_bapm)
  75                         amdgpu_dpm_enable_bapm(adev, adev->pm.dpm.ac_power);
  76                 mutex_unlock(&adev->pm.mutex);
  77         }
  78 }
  79
  80 /**
  81  * DOC: power_dpm_state
  82  *
  83  * This is a legacy interface and is only provided for backwards compatibility.
  84  * The amdgpu driver provides a sysfs API for adjusting certain power
  85  * related parameters.  The file power_dpm_state is used for this.
  86  * It accepts the following arguments:
  87  * - battery
  88  * - balanced
  89  * - performance
  90  *
  91  * battery
  92  *
  93  * On older GPUs, the vbios provided a special power state for battery
  94  * operation.  Selecting battery switched to this state.  This is no
  95  * longer provided on newer GPUs so the option does nothing in that case.
  96  *
  97  * balanced
  98  *
  99  * On older GPUs, the vbios provided a special power state for balanced
 100  * operation.  Selecting balanced switched to this state.  This is no
 101  * longer provided on newer GPUs so the option does nothing in that case.
 102  *
 103  * performance
 104  *
 105  * On older GPUs, the vbios provided a special power state for performance
 106  * operation.  Selecting performance switched to this state.  This is no
 107  * longer provided on newer GPUs so the option does nothing in that case.
 108  *
 109  */
 110
 111 static ssize_t amdgpu_get_dpm_state(struct device *dev,
 112                                     struct device_attribute *attr,
 113                                     char *buf)
 114 {
 115         struct drm_device *ddev = dev_get_drvdata(dev);
 116         struct amdgpu_device *adev = ddev->dev_private;
 117         enum amd_pm_state_type pm;
 118
 119         if (adev->powerplay.pp_funcs->get_current_power_state)
 120                 pm = amdgpu_dpm_get_current_power_state(adev);
 121         else
 122                 pm = adev->pm.dpm.user_state;
 123
 124         return snprintf(buf, PAGE_SIZE, "%s\n",
 125                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 126                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 127 }
 128
 129 static ssize_t amdgpu_set_dpm_state(struct device *dev,
 130                                     struct device_attribute *attr,
 131                                     const char *buf,
 132                                     size_t count)
 133 {
 134         struct drm_device *ddev = dev_get_drvdata(dev);
 135         struct amdgpu_device *adev = ddev->dev_private;
 136         enum amd_pm_state_type  state;
 137
 138         if (strncmp("battery", buf, strlen("battery")) == 0)
 139                 state = POWER_STATE_TYPE_BATTERY;
 140         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 141                 state = POWER_STATE_TYPE_BALANCED;
 142         else if (strncmp("performance", buf, strlen("performance")) == 0)
 143                 state = POWER_STATE_TYPE_PERFORMANCE;
 144         else {
 145                 count = -EINVAL;
 146                 goto fail;
 147         }
 148
 149         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 150                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);
 151         } else {
 152                 mutex_lock(&adev->pm.mutex);
 153                 adev->pm.dpm.user_state = state;
 154                 mutex_unlock(&adev->pm.mutex);
 155
 156                 /* Can't set dpm state when the card is off */
 157                 if (!(adev->flags & AMD_IS_PX) ||
 158                     (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
 159                         amdgpu_pm_compute_clocks(adev);
 160         }
 161 fail:
 162         return count;
 163 }
 164
 165
 166 /**
 167  * DOC: power_dpm_force_performance_level
 168  *
 169  * The amdgpu driver provides a sysfs API for adjusting certain power
 170  * related parameters.  The file power_dpm_force_performance_level is
 171  * used for this.  It accepts the following arguments:
 172  * - auto
 173  * - low
 174  * - high
 175  * - manual
 176  * - GPU fan
 177  * - profile_standard
 178  * - profile_min_sclk
 179  * - profile_min_mclk
 180  * - profile_peak
 181  *
 182  * auto
 183  *
 184  * When auto is selected, the driver will attempt to dynamically select
 185  * the optimal power profile for current conditions in the driver.
 186  *
 187  * low
 188  *
 189  * When low is selected, the clocks are forced to the lowest power state.
 190  *
 191  * high
 192  *
 193  * When high is selected, the clocks are forced to the highest power state.
 194  *
 195  * manual
 196  *
 197  * When manual is selected, the user can manually adjust which power states
 198  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 199  * and pp_dpm_pcie files and adjust the power state transition heuristics
 200  * via the pp_power_profile_mode sysfs file.
 201  *
 202  * profile_standard
 203  * profile_min_sclk
 204  * profile_min_mclk
 205  * profile_peak
 206  *
 207  * When the profiling modes are selected, clock and power gating are
 208  * disabled and the clocks are set for different profiling cases. This
 209  * mode is recommended for profiling specific work loads where you do
 210  * not want clock or power gating for clock fluctuation to interfere
 211  * with your results. profile_standard sets the clocks to a fixed clock
 212  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 213  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 214  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 215  *
 216  */
 217
 218 static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
 219                                                 struct device_attribute *attr,
 220                                                                 char *buf)
 221 {
 222         struct drm_device *ddev = dev_get_drvdata(dev);
 223         struct amdgpu_device *adev = ddev->dev_private;
 224         enum amd_dpm_forced_level level = 0xff;
 225
 226         if  ((adev->flags & AMD_IS_PX) &&
 227              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 228                 return snprintf(buf, PAGE_SIZE, "off\n");
 229
 230         if (adev->powerplay.pp_funcs->get_performance_level)
 231                 level = amdgpu_dpm_get_performance_level(adev);
 232         else
 233                 level = adev->pm.dpm.forced_level;
 234
 235         return snprintf(buf, PAGE_SIZE, "%s\n",
 236                         (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 237                         (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 238                         (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 239                         (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 240                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 241                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 242                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 243                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 244                         "unknown");
 245 }
 246
 247 static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
 248                                                        struct device_attribute *attr,
 249                                                        const char *buf,
 250                                                        size_t count)
 251 {
 252         struct drm_device *ddev = dev_get_drvdata(dev);
 253         struct amdgpu_device *adev = ddev->dev_private;
 254         enum amd_dpm_forced_level level;
 255         enum amd_dpm_forced_level current_level = 0xff;
 256         int ret = 0;
 257
 258         /* Can't force performance level when the card is off */
 259         if  ((adev->flags & AMD_IS_PX) &&
 260              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 261                 return -EINVAL;
 262
 263         if (adev->powerplay.pp_funcs->get_performance_level)
 264                 current_level = amdgpu_dpm_get_performance_level(adev);
 265
 266         if (strncmp("low", buf, strlen("low")) == 0) {
 267                 level = AMD_DPM_FORCED_LEVEL_LOW;
 268         } else if (strncmp("high", buf, strlen("high")) == 0) {
 269                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 270         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 271                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 272         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 273                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 274         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 275                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 276         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 277                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 278         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 279                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 280         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 281                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 282         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 283                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 284         }  else {
 285                 count = -EINVAL;
 286                 goto fail;
 287         }
 288
 289         if (current_level == level)
 290                 return count;
 291
 292         if (adev->powerplay.pp_funcs->force_performance_level) {
 293                 mutex_lock(&adev->pm.mutex);
 294                 if (adev->pm.dpm.thermal_active) {
 295                         count = -EINVAL;
 296                         mutex_unlock(&adev->pm.mutex);
 297                         goto fail;
 298                 }
 299                 ret = amdgpu_dpm_force_performance_level(adev, level);
 300                 if (ret)
 301                         count = -EINVAL;
 302                 else
 303                         adev->pm.dpm.forced_level = level;
 304                 mutex_unlock(&adev->pm.mutex);
 305         }
 306
 307 fail:
 308         return count;
 309 }
 310
 311 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 312                 struct device_attribute *attr,
 313                 char *buf)
 314 {
 315         struct drm_device *ddev = dev_get_drvdata(dev);
 316         struct amdgpu_device *adev = ddev->dev_private;
 317         struct pp_states_info data;
 318         int i, buf_len;
 319
 320         if (adev->powerplay.pp_funcs->get_pp_num_states)
 321                 amdgpu_dpm_get_pp_num_states(adev, &data);
 322
 323         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 324         for (i = 0; i < data.nums; i++)
 325                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 326                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 327                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 328                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 329                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 330
 331         return buf_len;
 332 }
 333
 334 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 335                 struct device_attribute *attr,
 336                 char *buf)
 337 {
 338         struct drm_device *ddev = dev_get_drvdata(dev);
 339         struct amdgpu_device *adev = ddev->dev_private;
 340         struct pp_states_info data;
 341         enum amd_pm_state_type pm = 0;
 342         int i = 0;
 343
 344         if (adev->powerplay.pp_funcs->get_current_power_state
 345                  && adev->powerplay.pp_funcs->get_pp_num_states) {
 346                 pm = amdgpu_dpm_get_current_power_state(adev);
 347                 amdgpu_dpm_get_pp_num_states(adev, &data);
 348
 349                 for (i = 0; i < data.nums; i++) {
 350                         if (pm == data.states[i])
 351                                 break;
 352                 }
 353
 354                 if (i == data.nums)
 355                         i = -EINVAL;
 356         }
 357
 358         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 359 }
 360
 361 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 362                 struct device_attribute *attr,
 363                 char *buf)
 364 {
 365         struct drm_device *ddev = dev_get_drvdata(dev);
 366         struct amdgpu_device *adev = ddev->dev_private;
 367
 368         if (adev->pp_force_state_enabled)
 369                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 370         else
 371                 return snprintf(buf, PAGE_SIZE, "\n");
 372 }
 373
 374 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 375                 struct device_attribute *attr,
 376                 const char *buf,
 377                 size_t count)
 378 {
 379         struct drm_device *ddev = dev_get_drvdata(dev);
 380         struct amdgpu_device *adev = ddev->dev_private;
 381         enum amd_pm_state_type state = 0;
 382         unsigned long idx;
 383         int ret;
 384
 385         if (strlen(buf) == 1)
 386                 adev->pp_force_state_enabled = false;
 387         else if (adev->powerplay.pp_funcs->dispatch_tasks &&
 388                         adev->powerplay.pp_funcs->get_pp_num_states) {
 389                 struct pp_states_info data;
 390
 391                 ret = kstrtoul(buf, 0, &idx);
 392                 if (ret || idx >= ARRAY_SIZE(data.states)) {
 393                         count = -EINVAL;
 394                         goto fail;
 395                 }
 396
 397                 amdgpu_dpm_get_pp_num_states(adev, &data);
 398                 state = data.states[idx];
 399                 /* only set user selected power states */
 400                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 401                     state != POWER_STATE_TYPE_DEFAULT) {
 402                         amdgpu_dpm_dispatch_task(adev,
 403                                         AMD_PP_TASK_ENABLE_USER_STATE, &state);
 404                         adev->pp_force_state_enabled = true;
 405                 }
 406         }
 407 fail:
 408         return count;
 409 }
 410
 411 /**
 412  * DOC: pp_table
 413  *
 414  * The amdgpu driver provides a sysfs API for uploading new powerplay
 415  * tables.  The file pp_table is used for this.  Reading the file
 416  * will dump the current power play table.  Writing to the file
 417  * will attempt to upload a new powerplay table and re-initialize
 418  * powerplay using that new table.
 419  *
 420  */
 421
 422 static ssize_t amdgpu_get_pp_table(struct device *dev,
 423                 struct device_attribute *attr,
 424                 char *buf)
 425 {
 426         struct drm_device *ddev = dev_get_drvdata(dev);
 427         struct amdgpu_device *adev = ddev->dev_private;
 428         char *table = NULL;
 429         int size;
 430
 431         if (adev->powerplay.pp_funcs->get_pp_table)
 432                 size = amdgpu_dpm_get_pp_table(adev, &table);
 433         else
 434                 return 0;
 435
 436         if (size >= PAGE_SIZE)
 437                 size = PAGE_SIZE - 1;
 438
 439         memcpy(buf, table, size);
 440
 441         return size;
 442 }
 443
 444 static ssize_t amdgpu_set_pp_table(struct device *dev,
 445                 struct device_attribute *attr,
 446                 const char *buf,
 447                 size_t count)
 448 {
 449         struct drm_device *ddev = dev_get_drvdata(dev);
 450         struct amdgpu_device *adev = ddev->dev_private;
 451
 452         if (adev->powerplay.pp_funcs->set_pp_table)
 453                 amdgpu_dpm_set_pp_table(adev, buf, count);
 454
 455         return count;
 456 }
 457
 458 /**
 459  * DOC: pp_od_clk_voltage
 460  *
 461  * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
 462  * in each power level within a power state.  The pp_od_clk_voltage is used for
 463  * this.
 464  *
 465  * Reading the file will display:
 466  * - a list of engine clock levels and voltages labeled OD_SCLK
 467  * - a list of memory clock levels and voltages labeled OD_MCLK
 468  * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
 469  *
 470  * To manually adjust these settings, first select manual using
 471  * power_dpm_force_performance_level. Enter a new value for each
 472  * level by writing a string that contains "s/m level clock voltage" to
 473  * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
 474  * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
 475  * 810 mV.  When you have edited all of the states as needed, write
 476  * "c" (commit) to the file to commit your changes.  If you want to reset to the
 477  * default power levels, write "r" (reset) to the file to reset them.
 478  *
 479  */
 480
 481 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 482                 struct device_attribute *attr,
 483                 const char *buf,
 484                 size_t count)
 485 {
 486         struct drm_device *ddev = dev_get_drvdata(dev);
 487         struct amdgpu_device *adev = ddev->dev_private;
 488         int ret;
 489         uint32_t parameter_size = 0;
 490         long parameter[64];
 491         char buf_cpy[128];
 492         char *tmp_str;
 493         char *sub_str;
 494         const char delimiter[3] = {' ', '\n', '\0'};
 495         uint32_t type;
 496
 497         if (count > 127)
 498                 return -EINVAL;
 499
 500         if (*buf == 's')
 501                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 502         else if (*buf == 'm')
 503                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 504         else if(*buf == 'r')
 505                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 506         else if (*buf == 'c')
 507                 type = PP_OD_COMMIT_DPM_TABLE;
 508         else
 509                 return -EINVAL;
 510
 511         memcpy(buf_cpy, buf, count+1);
 512
 513         tmp_str = buf_cpy;
 514
 515         while (isspace(*++tmp_str));
 516
 517         while (tmp_str[0]) {
 518                 sub_str = strsep(&tmp_str, delimiter);
 519                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 520                 if (ret)
 521                         return -EINVAL;
 522                 parameter_size++;
 523
 524                 while (isspace(*tmp_str))
 525                         tmp_str++;
 526         }
 527
 528         if (adev->powerplay.pp_funcs->odn_edit_dpm_table)
 529                 ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
 530                                                 parameter, parameter_size);
 531
 532         if (ret)
 533                 return -EINVAL;
 534
 535         if (type == PP_OD_COMMIT_DPM_TABLE) {
 536                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
 537                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
 538                         return count;
 539                 } else {
 540                         return -EINVAL;
 541                 }
 542         }
 543
 544         return count;
 545 }
 546
 547 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 548                 struct device_attribute *attr,
 549                 char *buf)
 550 {
 551         struct drm_device *ddev = dev_get_drvdata(dev);
 552         struct amdgpu_device *adev = ddev->dev_private;
 553         uint32_t size = 0;
 554
 555         if (adev->powerplay.pp_funcs->print_clock_levels) {
 556                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 557                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
 558                 return size;
 559         } else {
 560                 return snprintf(buf, PAGE_SIZE, "\n");
 561         }
 562
 563 }
 564
 565 /**
 566  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_pcie
 567  *
 568  * The amdgpu driver provides a sysfs API for adjusting what power levels
 569  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
 570  * and pp_dpm_pcie are used for this.
 571  *
 572  * Reading back the files will show you the available power levels within
 573  * the power state and the clock information for those levels.
 574  *
 575  * To manually adjust these states, first select manual using
 576  * power_dpm_force_performance_level.  Writing a string of the level
 577  * numbers to the file will select which levels you want to enable.
 578  * E.g., writing 456 to the file will enable levels 4, 5, and 6.
 579  *
 580  */
 581
 582 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
 583                 struct device_attribute *attr,
 584                 char *buf)
 585 {
 586         struct drm_device *ddev = dev_get_drvdata(dev);
 587         struct amdgpu_device *adev = ddev->dev_private;
 588
 589         if (adev->powerplay.pp_funcs->print_clock_levels)
 590                 return amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
 591         else
 592                 return snprintf(buf, PAGE_SIZE, "\n");
 593 }
 594
 595 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
 596                 struct device_attribute *attr,
 597                 const char *buf,
 598                 size_t count)
 599 {
 600         struct drm_device *ddev = dev_get_drvdata(dev);
 601         struct amdgpu_device *adev = ddev->dev_private;
 602         int ret;
 603         long level;
 604         uint32_t i, mask = 0;
 605         char sub_str[2];
 606
 607         for (i = 0; i < strlen(buf); i++) {
 608                 if (*(buf + i) == '\n')
 609                         continue;
 610                 sub_str[0] = *(buf + i);
 611                 sub_str[1] = '\0';
 612                 ret = kstrtol(sub_str, 0, &level);
 613
 614                 if (ret) {
 615                         count = -EINVAL;
 616                         goto fail;
 617                 }
 618                 mask |= 1 << level;
 619         }
 620
 621         if (adev->powerplay.pp_funcs->force_clock_level)
 622                 amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
 623
 624 fail:
 625         return count;
 626 }
 627
 628 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
 629                 struct device_attribute *attr,
 630                 char *buf)
 631 {
 632         struct drm_device *ddev = dev_get_drvdata(dev);
 633         struct amdgpu_device *adev = ddev->dev_private;
 634
 635         if (adev->powerplay.pp_funcs->print_clock_levels)
 636                 return amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
 637         else
 638                 return snprintf(buf, PAGE_SIZE, "\n");
 639 }
 640
 641 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
 642                 struct device_attribute *attr,
 643                 const char *buf,
 644                 size_t count)
 645 {
 646         struct drm_device *ddev = dev_get_drvdata(dev);
 647         struct amdgpu_device *adev = ddev->dev_private;
 648         int ret;
 649         long level;
 650         uint32_t i, mask = 0;
 651         char sub_str[2];
 652
 653         for (i = 0; i < strlen(buf); i++) {
 654                 if (*(buf + i) == '\n')
 655                         continue;
 656                 sub_str[0] = *(buf + i);
 657                 sub_str[1] = '\0';
 658                 ret = kstrtol(sub_str, 0, &level);
 659
 660                 if (ret) {
 661                         count = -EINVAL;
 662                         goto fail;
 663                 }
 664                 mask |= 1 << level;
 665         }
 666         if (adev->powerplay.pp_funcs->force_clock_level)
 667                 amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
 668
 669 fail:
 670         return count;
 671 }
 672
 673 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
 674                 struct device_attribute *attr,
 675                 char *buf)
 676 {
 677         struct drm_device *ddev = dev_get_drvdata(dev);
 678         struct amdgpu_device *adev = ddev->dev_private;
 679
 680         if (adev->powerplay.pp_funcs->print_clock_levels)
 681                 return amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
 682         else
 683                 return snprintf(buf, PAGE_SIZE, "\n");
 684 }
 685
 686 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
 687                 struct device_attribute *attr,
 688                 const char *buf,
 689                 size_t count)
 690 {
 691         struct drm_device *ddev = dev_get_drvdata(dev);
 692         struct amdgpu_device *adev = ddev->dev_private;
 693         int ret;
 694         long level;
 695         uint32_t i, mask = 0;
 696         char sub_str[2];
 697
 698         for (i = 0; i < strlen(buf); i++) {
 699                 if (*(buf + i) == '\n')
 700                         continue;
 701                 sub_str[0] = *(buf + i);
 702                 sub_str[1] = '\0';
 703                 ret = kstrtol(sub_str, 0, &level);
 704
 705                 if (ret) {
 706                         count = -EINVAL;
 707                         goto fail;
 708                 }
 709                 mask |= 1 << level;
 710         }
 711         if (adev->powerplay.pp_funcs->force_clock_level)
 712                 amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
 713
 714 fail:
 715         return count;
 716 }
 717
 718 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
 719                 struct device_attribute *attr,
 720                 char *buf)
 721 {
 722         struct drm_device *ddev = dev_get_drvdata(dev);
 723         struct amdgpu_device *adev = ddev->dev_private;
 724         uint32_t value = 0;
 725
 726         if (adev->powerplay.pp_funcs->get_sclk_od)
 727                 value = amdgpu_dpm_get_sclk_od(adev);
 728
 729         return snprintf(buf, PAGE_SIZE, "%d\n", value);
 730 }
 731
 732 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
 733                 struct device_attribute *attr,
 734                 const char *buf,
 735                 size_t count)
 736 {
 737         struct drm_device *ddev = dev_get_drvdata(dev);
 738         struct amdgpu_device *adev = ddev->dev_private;
 739         int ret;
 740         long int value;
 741
 742         ret = kstrtol(buf, 0, &value);
 743
 744         if (ret) {
 745                 count = -EINVAL;
 746                 goto fail;
 747         }
 748         if (adev->powerplay.pp_funcs->set_sclk_od)
 749                 amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
 750
 751         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 752                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
 753         } else {
 754                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
 755                 amdgpu_pm_compute_clocks(adev);
 756         }
 757
 758 fail:
 759         return count;
 760 }
 761
 762 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
 763                 struct device_attribute *attr,
 764                 char *buf)
 765 {
 766         struct drm_device *ddev = dev_get_drvdata(dev);
 767         struct amdgpu_device *adev = ddev->dev_private;
 768         uint32_t value = 0;
 769
 770         if (adev->powerplay.pp_funcs->get_mclk_od)
 771                 value = amdgpu_dpm_get_mclk_od(adev);
 772
 773         return snprintf(buf, PAGE_SIZE, "%d\n", value);
 774 }
 775
 776 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
 777                 struct device_attribute *attr,
 778                 const char *buf,
 779                 size_t count)
 780 {
 781         struct drm_device *ddev = dev_get_drvdata(dev);
 782         struct amdgpu_device *adev = ddev->dev_private;
 783         int ret;
 784         long int value;
 785
 786         ret = kstrtol(buf, 0, &value);
 787
 788         if (ret) {
 789                 count = -EINVAL;
 790                 goto fail;
 791         }
 792         if (adev->powerplay.pp_funcs->set_mclk_od)
 793                 amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
 794
 795         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 796                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
 797         } else {
 798                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
 799                 amdgpu_pm_compute_clocks(adev);
 800         }
 801
 802 fail:
 803         return count;
 804 }
 805
 806 /**
 807  * DOC: pp_power_profile_mode
 808  *
 809  * The amdgpu driver provides a sysfs API for adjusting the heuristics
 810  * related to switching between power levels in a power state.  The file
 811  * pp_power_profile_mode is used for this.
 812  *
 813  * Reading this file outputs a list of all of the predefined power profiles
 814  * and the relevant heuristics settings for that profile.
 815  *
 816  * To select a profile or create a custom profile, first select manual using
 817  * power_dpm_force_performance_level.  Writing the number of a predefined
 818  * profile to pp_power_profile_mode will enable those heuristics.  To
 819  * create a custom set of heuristics, write a string of numbers to the file
 820  * starting with the number of the custom profile along with a setting
 821  * for each heuristic parameter.  Due to differences across asic families
 822  * the heuristic parameters vary from family to family.
 823  *
 824  */
 825
 826 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
 827                 struct device_attribute *attr,
 828                 char *buf)
 829 {
 830         struct drm_device *ddev = dev_get_drvdata(dev);
 831         struct amdgpu_device *adev = ddev->dev_private;
 832
 833         if (adev->powerplay.pp_funcs->get_power_profile_mode)
 834                 return amdgpu_dpm_get_power_profile_mode(adev, buf);
 835
 836         return snprintf(buf, PAGE_SIZE, "\n");
 837 }
 838
 839
 840 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
 841                 struct device_attribute *attr,
 842                 const char *buf,
 843                 size_t count)
 844 {
 845         int ret = 0xff;
 846         struct drm_device *ddev = dev_get_drvdata(dev);
 847         struct amdgpu_device *adev = ddev->dev_private;
 848         uint32_t parameter_size = 0;
 849         long parameter[64];
 850         char *sub_str, buf_cpy[128];
 851         char *tmp_str;
 852         uint32_t i = 0;
 853         char tmp[2];
 854         long int profile_mode = 0;
 855         const char delimiter[3] = {' ', '\n', '\0'};
 856
 857         tmp[0] = *(buf);
 858         tmp[1] = '\0';
 859         ret = kstrtol(tmp, 0, &profile_mode);
 860         if (ret)
 861                 goto fail;
 862
 863         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
 864                 if (count < 2 || count > 127)
 865                         return -EINVAL;
 866                 while (isspace(*++buf))
 867                         i++;
 868                 memcpy(buf_cpy, buf, count-i);
 869                 tmp_str = buf_cpy;
 870                 while (tmp_str[0]) {
 871                         sub_str = strsep(&tmp_str, delimiter);
 872                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 873                         if (ret) {
 874                                 count = -EINVAL;
 875                                 goto fail;
 876                         }
 877                         parameter_size++;
 878                         while (isspace(*tmp_str))
 879                                 tmp_str++;
 880                 }
 881         }
 882         parameter[parameter_size] = profile_mode;
 883         if (adev->powerplay.pp_funcs->set_power_profile_mode)
 884                 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
 885
 886         if (!ret)
 887                 return count;
 888 fail:
 889         return -EINVAL;
 890 }
 891
 892 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
 893 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
 894                    amdgpu_get_dpm_forced_performance_level,
 895                    amdgpu_set_dpm_forced_performance_level);
 896 static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
 897 static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
 898 static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
 899                 amdgpu_get_pp_force_state,
 900                 amdgpu_set_pp_force_state);
 901 static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
 902                 amdgpu_get_pp_table,
 903                 amdgpu_set_pp_table);
 904 static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
 905                 amdgpu_get_pp_dpm_sclk,
 906                 amdgpu_set_pp_dpm_sclk);
 907 static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
 908                 amdgpu_get_pp_dpm_mclk,
 909                 amdgpu_set_pp_dpm_mclk);
 910 static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
 911                 amdgpu_get_pp_dpm_pcie,
 912                 amdgpu_set_pp_dpm_pcie);
 913 static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR,
 914                 amdgpu_get_pp_sclk_od,
 915                 amdgpu_set_pp_sclk_od);
 916 static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR,
 917                 amdgpu_get_pp_mclk_od,
 918                 amdgpu_set_pp_mclk_od);
 919 static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
 920                 amdgpu_get_pp_power_profile_mode,
 921                 amdgpu_set_pp_power_profile_mode);
 922 static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
 923                 amdgpu_get_pp_od_clk_voltage,
 924                 amdgpu_set_pp_od_clk_voltage);
 925
 926 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
 927                                       struct device_attribute *attr,
 928                                       char *buf)
 929 {
 930         struct amdgpu_device *adev = dev_get_drvdata(dev);
 931         struct drm_device *ddev = adev->ddev;
 932         int r, temp, size = sizeof(temp);
 933
 934         /* Can't get temperature when the card is off */
 935         if  ((adev->flags & AMD_IS_PX) &&
 936              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 937                 return -EINVAL;
 938
 939         /* sanity check PP is enabled */
 940         if (!(adev->powerplay.pp_funcs &&
 941               adev->powerplay.pp_funcs->read_sensor))
 942                 return -EINVAL;
 943
 944         /* get the temperature */
 945         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
 946                                    (void *)&temp, &size);
 947         if (r)
 948                 return r;
 949
 950         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 951 }
 952
 953 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
 954                                              struct device_attribute *attr,
 955                                              char *buf)
 956 {
 957         struct amdgpu_device *adev = dev_get_drvdata(dev);
 958         int hyst = to_sensor_dev_attr(attr)->index;
 959         int temp;
 960
 961         if (hyst)
 962                 temp = adev->pm.dpm.thermal.min_temp;
 963         else
 964                 temp = adev->pm.dpm.thermal.max_temp;
 965
 966         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 967 }
 968
 969 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
 970                                             struct device_attribute *attr,
 971                                             char *buf)
 972 {
 973         struct amdgpu_device *adev = dev_get_drvdata(dev);
 974         u32 pwm_mode = 0;
 975
 976         if (!adev->powerplay.pp_funcs->get_fan_control_mode)
 977                 return -EINVAL;
 978
 979         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
 980
 981         return sprintf(buf, "%i\n", pwm_mode);
 982 }
 983
 984 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
 985                                             struct device_attribute *attr,
 986                                             const char *buf,
 987                                             size_t count)
 988 {
 989         struct amdgpu_device *adev = dev_get_drvdata(dev);
 990         int err;
 991         int value;
 992
 993         /* Can't adjust fan when the card is off */
 994         if  ((adev->flags & AMD_IS_PX) &&
 995              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 996                 return -EINVAL;
 997
 998         if (!adev->powerplay.pp_funcs->set_fan_control_mode)
 999                 return -EINVAL;
1000
1001         err = kstrtoint(buf, 10, &value);
1002         if (err)
1003                 return err;
1004
1005         amdgpu_dpm_set_fan_control_mode(adev, value);
1006
1007         return count;
1008 }
1009
1010 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
1011                                          struct device_attribute *attr,
1012                                          char *buf)
1013 {
1014         return sprintf(buf, "%i\n", 0);
1015 }
1016
1017 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
1018                                          struct device_attribute *attr,
1019                                          char *buf)
1020 {
1021         return sprintf(buf, "%i\n", 255);
1022 }
1023
1024 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
1025                                      struct device_attribute *attr,
1026                                      const char *buf, size_t count)
1027 {
1028         struct amdgpu_device *adev = dev_get_drvdata(dev);
1029         int err;
1030         u32 value;
1031
1032         /* Can't adjust fan when the card is off */
1033         if  ((adev->flags & AMD_IS_PX) &&
1034              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1035                 return -EINVAL;
1036
1037         err = kstrtou32(buf, 10, &value);
1038         if (err)
1039                 return err;
1040
1041         value = (value * 100) / 255;
1042
1043         if (adev->powerplay.pp_funcs->set_fan_speed_percent) {
1044                 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
1045                 if (err)
1046                         return err;
1047         }
1048
1049         return count;
1050 }
1051
1052 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
1053                                      struct device_attribute *attr,
1054                                      char *buf)
1055 {
1056         struct amdgpu_device *adev = dev_get_drvdata(dev);
1057         int err;
1058         u32 speed = 0;
1059
1060         /* Can't adjust fan when the card is off */
1061         if  ((adev->flags & AMD_IS_PX) &&
1062              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1063                 return -EINVAL;
1064
1065         if (adev->powerplay.pp_funcs->get_fan_speed_percent) {
1066                 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
1067                 if (err)
1068                         return err;
1069         }
1070
1071         speed = (speed * 255) / 100;
1072
1073         return sprintf(buf, "%i\n", speed);
1074 }
1075
1076 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
1077                                            struct device_attribute *attr,
1078                                            char *buf)
1079 {
1080         struct amdgpu_device *adev = dev_get_drvdata(dev);
1081         int err;
1082         u32 speed = 0;
1083
1084         /* Can't adjust fan when the card is off */
1085         if  ((adev->flags & AMD_IS_PX) &&
1086              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1087                 return -EINVAL;
1088
1089         if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
1090                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
1091                 if (err)
1092                         return err;
1093         }
1094
1095         return sprintf(buf, "%i\n", speed);
1096 }
1097
1098 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
1099                                         struct device_attribute *attr,
1100                                         char *buf)
1101 {
1102         struct amdgpu_device *adev = dev_get_drvdata(dev);
1103         struct drm_device *ddev = adev->ddev;
1104         u32 vddgfx;
1105         int r, size = sizeof(vddgfx);
1106
1107         /* Can't get voltage when the card is off */
1108         if  ((adev->flags & AMD_IS_PX) &&
1109              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1110                 return -EINVAL;
1111
1112         /* sanity check PP is enabled */
1113         if (!(adev->powerplay.pp_funcs &&
1114               adev->powerplay.pp_funcs->read_sensor))
1115               return -EINVAL;
1116
1117         /* get the voltage */
1118         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
1119                                    (void *)&vddgfx, &size);
1120         if (r)
1121                 return r;
1122
1123         return snprintf(buf, PAGE_SIZE, "%d\n", vddgfx);
1124 }
1125
1126 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
1127                                               struct device_attribute *attr,
1128                                               char *buf)
1129 {
1130         return snprintf(buf, PAGE_SIZE, "vddgfx\n");
1131 }
1132
1133 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
1134                                        struct device_attribute *attr,
1135                                        char *buf)
1136 {
1137         struct amdgpu_device *adev = dev_get_drvdata(dev);
1138         struct drm_device *ddev = adev->ddev;
1139         u32 vddnb;
1140         int r, size = sizeof(vddnb);
1141
1142         /* only APUs have vddnb */
1143         if  (adev->flags & AMD_IS_APU)
1144                 return -EINVAL;
1145
1146         /* Can't get voltage when the card is off */
1147         if  ((adev->flags & AMD_IS_PX) &&
1148              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1149                 return -EINVAL;
1150
1151         /* sanity check PP is enabled */
1152         if (!(adev->powerplay.pp_funcs &&
1153               adev->powerplay.pp_funcs->read_sensor))
1154               return -EINVAL;
1155
1156         /* get the voltage */
1157         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
1158                                    (void *)&vddnb, &size);
1159         if (r)
1160                 return r;
1161
1162         return snprintf(buf, PAGE_SIZE, "%d\n", vddnb);
1163 }
1164
1165 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
1166                                               struct device_attribute *attr,
1167                                               char *buf)
1168 {
1169         return snprintf(buf, PAGE_SIZE, "vddnb\n");
1170 }
1171
1172 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
1173                                            struct device_attribute *attr,
1174                                            char *buf)
1175 {
1176         struct amdgpu_device *adev = dev_get_drvdata(dev);
1177         struct drm_device *ddev = adev->ddev;
1178         u32 query = 0;
1179         int r, size = sizeof(u32);
1180         unsigned uw;
1181
1182         /* Can't get power when the card is off */
1183         if  ((adev->flags & AMD_IS_PX) &&
1184              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1185                 return -EINVAL;
1186
1187         /* sanity check PP is enabled */
1188         if (!(adev->powerplay.pp_funcs &&
1189               adev->powerplay.pp_funcs->read_sensor))
1190               return -EINVAL;
1191
1192         /* get the voltage */
1193         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
1194                                    (void *)&query, &size);
1195         if (r)
1196                 return r;
1197
1198         /* convert to microwatts */
1199         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
1200
1201         return snprintf(buf, PAGE_SIZE, "%u\n", uw);
1202 }
1203
1204 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
1205                                          struct device_attribute *attr,
1206                                          char *buf)
1207 {
1208         return sprintf(buf, "%i\n", 0);
1209 }
1210
1211 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
1212                                          struct device_attribute *attr,
1213                                          char *buf)
1214 {
1215         struct amdgpu_device *adev = dev_get_drvdata(dev);
1216         uint32_t limit = 0;
1217
1218         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
1219                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
1220                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1221         } else {
1222                 return snprintf(buf, PAGE_SIZE, "\n");
1223         }
1224 }
1225
1226 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
1227                                          struct device_attribute *attr,
1228                                          char *buf)
1229 {
1230         struct amdgpu_device *adev = dev_get_drvdata(dev);
1231         uint32_t limit = 0;
1232
1233         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
1234                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
1235                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1236         } else {
1237                 return snprintf(buf, PAGE_SIZE, "\n");
1238         }
1239 }
1240
1241
1242 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
1243                 struct device_attribute *attr,
1244                 const char *buf,
1245                 size_t count)
1246 {
1247         struct amdgpu_device *adev = dev_get_drvdata(dev);
1248         int err;
1249         u32 value;
1250
1251         err = kstrtou32(buf, 10, &value);
1252         if (err)
1253                 return err;
1254
1255         value = value / 1000000; /* convert to Watt */
1256         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) {
1257                 err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
1258                 if (err)
1259                         return err;
1260         } else {
1261                 return -EINVAL;
1262         }
1263
1264         return count;
1265 }
1266
1267
1268 /**
1269  * DOC: hwmon
1270  *
1271  * The amdgpu driver exposes the following sensor interfaces:
1272  * - GPU temperature (via the on-die sensor)
1273  * - GPU voltage
1274  * - Northbridge voltage (APUs only)
1275  * - GPU power
1276  * - GPU fan
1277  *
1278  * hwmon interfaces for GPU temperature:
1279  * - temp1_input: the on die GPU temperature in millidegrees Celsius
1280  * - temp1_crit: temperature critical max value in millidegrees Celsius
1281  * - temp1_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
1282  *
1283  * hwmon interfaces for GPU voltage:
1284  * - in0_input: the voltage on the GPU in millivolts
1285  * - in1_input: the voltage on the Northbridge in millivolts
1286  *
1287  * hwmon interfaces for GPU power:
1288  * - power1_average: average power used by the GPU in microWatts
1289  * - power1_cap_min: minimum cap supported in microWatts
1290  * - power1_cap_max: maximum cap supported in microWatts
1291  * - power1_cap: selected power cap in microWatts
1292  *
1293  * hwmon interfaces for GPU fan:
1294  * - pwm1: pulse width modulation fan level (0-255)
1295  * - pwm1_enable: pulse width modulation fan control method
1296  *                0: no fan speed control
1297  *                1: manual fan speed control using pwm interface
1298  *                2: automatic fan speed control
1299  * - pwm1_min: pulse width modulation fan control minimum level (0)
1300  * - pwm1_max: pulse width modulation fan control maximum level (255)
1301  * - fan1_input: fan speed in RPM
1302  *
1303  * You can use hwmon tools like sensors to view this information on your system.
1304  *
1305  */
1306
1307 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0);
1308 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
1309 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
1310 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
1311 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
1312 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
1313 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
1314 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
1315 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
1316 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
1317 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
1318 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
1319 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
1320 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
1321 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
1322 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
1323
1324 static struct attribute *hwmon_attributes[] = {
1325         &sensor_dev_attr_temp1_input.dev_attr.attr,
1326         &sensor_dev_attr_temp1_crit.dev_attr.attr,
1327         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
1328         &sensor_dev_attr_pwm1.dev_attr.attr,
1329         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
1330         &sensor_dev_attr_pwm1_min.dev_attr.attr,
1331         &sensor_dev_attr_pwm1_max.dev_attr.attr,
1332         &sensor_dev_attr_fan1_input.dev_attr.attr,
1333         &sensor_dev_attr_in0_input.dev_attr.attr,
1334         &sensor_dev_attr_in0_label.dev_attr.attr,
1335         &sensor_dev_attr_in1_input.dev_attr.attr,
1336         &sensor_dev_attr_in1_label.dev_attr.attr,
1337         &sensor_dev_attr_power1_average.dev_attr.attr,
1338         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
1339         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
1340         &sensor_dev_attr_power1_cap.dev_attr.attr,
1341         NULL
1342 };
1343
1344 static umode_t hwmon_attributes_visible(struct kobject *kobj,
1345                                         struct attribute *attr, int index)
1346 {
1347         struct device *dev = kobj_to_dev(kobj);
1348         struct amdgpu_device *adev = dev_get_drvdata(dev);
1349         umode_t effective_mode = attr->mode;
1350
1351         /* handle non-powerplay limitations */
1352         if (!adev->powerplay.pp_handle) {
1353                 /* Skip fan attributes if fan is not present */
1354                 if (adev->pm.no_fan &&
1355                     (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
1356                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
1357                      attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1358                      attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
1359                         return 0;
1360                 /* requires powerplay */
1361                 if (attr == &sensor_dev_attr_fan1_input.dev_attr.attr)
1362                         return 0;
1363         }
1364
1365         /* Skip limit attributes if DPM is not enabled */
1366         if (!adev->pm.dpm_enabled &&
1367             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
1368              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
1369              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
1370              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
1371              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1372              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
1373                 return 0;
1374
1375         /* mask fan attributes if we have no bindings for this asic to expose */
1376         if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
1377              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
1378             (!adev->powerplay.pp_funcs->get_fan_control_mode &&
1379              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
1380                 effective_mode &= ~S_IRUGO;
1381
1382         if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
1383              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
1384             (!adev->powerplay.pp_funcs->set_fan_control_mode &&
1385              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
1386                 effective_mode &= ~S_IWUSR;
1387
1388         if ((adev->flags & AMD_IS_APU) &&
1389             (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
1390              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
1391              attr == &sensor_dev_attr_power1_cap.dev_attr.attr))
1392                 return 0;
1393
1394         /* hide max/min values if we can't both query and manage the fan */
1395         if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
1396              !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
1397             (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1398              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
1399                 return 0;
1400
1401         /* only APUs have vddnb */
1402         if (!(adev->flags & AMD_IS_APU) &&
1403             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
1404              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
1405                 return 0;
1406
1407         return effective_mode;
1408 }
1409
1410 static const struct attribute_group hwmon_attrgroup = {
1411         .attrs = hwmon_attributes,
1412         .is_visible = hwmon_attributes_visible,
1413 };
1414
1415 static const struct attribute_group *hwmon_groups[] = {
1416         &hwmon_attrgroup,
1417         NULL
1418 };
1419
1420 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
1421 {
1422         struct amdgpu_device *adev =
1423                 container_of(work, struct amdgpu_device,
1424                              pm.dpm.thermal.work);
1425         /* switch to the thermal state */
1426         enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
1427         int temp, size = sizeof(temp);
1428
1429         if (!adev->pm.dpm_enabled)
1430                 return;
1431
1432         if (adev->powerplay.pp_funcs &&
1433             adev->powerplay.pp_funcs->read_sensor &&
1434             !amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
1435                                     (void *)&temp, &size)) {
1436                 if (temp < adev->pm.dpm.thermal.min_temp)
1437                         /* switch back the user state */
1438                         dpm_state = adev->pm.dpm.user_state;
1439         } else {
1440                 if (adev->pm.dpm.thermal.high_to_low)
1441                         /* switch back the user state */
1442                         dpm_state = adev->pm.dpm.user_state;
1443         }
1444         mutex_lock(&adev->pm.mutex);
1445         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
1446                 adev->pm.dpm.thermal_active = true;
1447         else
1448                 adev->pm.dpm.thermal_active = false;
1449         adev->pm.dpm.state = dpm_state;
1450         mutex_unlock(&adev->pm.mutex);
1451
1452         amdgpu_pm_compute_clocks(adev);
1453 }
1454
1455 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
1456                                                      enum amd_pm_state_type dpm_state)
1457 {
1458         int i;
1459         struct amdgpu_ps *ps;
1460         u32 ui_class;
1461         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
1462                 true : false;
1463
1464         /* check if the vblank period is too short to adjust the mclk */
1465         if (single_display && adev->powerplay.pp_funcs->vblank_too_short) {
1466                 if (amdgpu_dpm_vblank_too_short(adev))
1467                         single_display = false;
1468         }
1469
1470         /* certain older asics have a separare 3D performance state,
1471          * so try that first if the user selected performance
1472          */
1473         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
1474                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
1475         /* balanced states don't exist at the moment */
1476         if (dpm_state == POWER_STATE_TYPE_BALANCED)
1477                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1478
1479 restart_search:
1480         /* Pick the best power state based on current conditions */
1481         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
1482                 ps = &adev->pm.dpm.ps[i];
1483                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
1484                 switch (dpm_state) {
1485                 /* user states */
1486                 case POWER_STATE_TYPE_BATTERY:
1487                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
1488                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1489                                         if (single_display)
1490                                                 return ps;
1491                                 } else
1492                                         return ps;
1493                         }
1494                         break;
1495                 case POWER_STATE_TYPE_BALANCED:
1496                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
1497                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1498                                         if (single_display)
1499                                                 return ps;
1500                                 } else
1501                                         return ps;
1502                         }
1503                         break;
1504                 case POWER_STATE_TYPE_PERFORMANCE:
1505                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
1506                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1507                                         if (single_display)
1508                                                 return ps;
1509                                 } else
1510                                         return ps;
1511                         }
1512                         break;
1513                 /* internal states */
1514                 case POWER_STATE_TYPE_INTERNAL_UVD:
1515                         if (adev->pm.dpm.uvd_ps)
1516                                 return adev->pm.dpm.uvd_ps;
1517                         else
1518                                 break;
1519                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1520                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
1521                                 return ps;
1522                         break;
1523                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1524                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
1525                                 return ps;
1526                         break;
1527                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1528                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
1529                                 return ps;
1530                         break;
1531                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1532                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
1533                                 return ps;
1534                         break;
1535                 case POWER_STATE_TYPE_INTERNAL_BOOT:
1536                         return adev->pm.dpm.boot_ps;
1537                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
1538                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
1539                                 return ps;
1540                         break;
1541                 case POWER_STATE_TYPE_INTERNAL_ACPI:
1542                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
1543                                 return ps;
1544                         break;
1545                 case POWER_STATE_TYPE_INTERNAL_ULV:
1546                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
1547                                 return ps;
1548                         break;
1549                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
1550                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
1551                                 return ps;
1552                         break;
1553                 default:
1554                         break;
1555                 }
1556         }
1557         /* use a fallback state if we didn't match */
1558         switch (dpm_state) {
1559         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1560                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1561                 goto restart_search;
1562         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1563         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1564         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1565                 if (adev->pm.dpm.uvd_ps) {
1566                         return adev->pm.dpm.uvd_ps;
1567                 } else {
1568                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1569                         goto restart_search;
1570                 }
1571         case POWER_STATE_TYPE_INTERNAL_THERMAL:
1572                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
1573                 goto restart_search;
1574         case POWER_STATE_TYPE_INTERNAL_ACPI:
1575                 dpm_state = POWER_STATE_TYPE_BATTERY;
1576                 goto restart_search;
1577         case POWER_STATE_TYPE_BATTERY:
1578         case POWER_STATE_TYPE_BALANCED:
1579         case POWER_STATE_TYPE_INTERNAL_3DPERF:
1580                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1581                 goto restart_search;
1582         default:
1583                 break;
1584         }
1585
1586         return NULL;
1587 }
1588
1589 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
1590 {
1591         struct amdgpu_ps *ps;
1592         enum amd_pm_state_type dpm_state;
1593         int ret;
1594         bool equal = false;
1595
1596         /* if dpm init failed */
1597         if (!adev->pm.dpm_enabled)
1598                 return;
1599
1600         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
1601                 /* add other state override checks here */
1602                 if ((!adev->pm.dpm.thermal_active) &&
1603                     (!adev->pm.dpm.uvd_active))
1604                         adev->pm.dpm.state = adev->pm.dpm.user_state;
1605         }
1606         dpm_state = adev->pm.dpm.state;
1607
1608         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
1609         if (ps)
1610                 adev->pm.dpm.requested_ps = ps;
1611         else
1612                 return;
1613
1614         if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) {
1615                 printk("switching from power state:\n");
1616                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
1617                 printk("switching to power state:\n");
1618                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
1619         }
1620
1621         /* update whether vce is active */
1622         ps->vce_active = adev->pm.dpm.vce_active;
1623         if (adev->powerplay.pp_funcs->display_configuration_changed)
1624                 amdgpu_dpm_display_configuration_changed(adev);
1625
1626         ret = amdgpu_dpm_pre_set_power_state(adev);
1627         if (ret)
1628                 return;
1629
1630         if (adev->powerplay.pp_funcs->check_state_equal) {
1631                 if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
1632                         equal = false;
1633         }
1634
1635         if (equal)
1636                 return;
1637
1638         amdgpu_dpm_set_power_state(adev);
1639         amdgpu_dpm_post_set_power_state(adev);
1640
1641         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
1642         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
1643
1644         if (adev->powerplay.pp_funcs->force_performance_level) {
1645                 if (adev->pm.dpm.thermal_active) {
1646                         enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
1647                         /* force low perf level for thermal */
1648                         amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
1649                         /* save the user's level */
1650                         adev->pm.dpm.forced_level = level;
1651                 } else {
1652                         /* otherwise, user selected level */
1653                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
1654                 }
1655         }
1656 }
1657
1658 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
1659 {
1660         if (adev->powerplay.pp_funcs->powergate_uvd) {
1661                 /* enable/disable UVD */
1662                 mutex_lock(&adev->pm.mutex);
1663                 amdgpu_dpm_powergate_uvd(adev, !enable);
1664                 mutex_unlock(&adev->pm.mutex);
1665         } else {
1666                 if (enable) {
1667                         mutex_lock(&adev->pm.mutex);
1668                         adev->pm.dpm.uvd_active = true;
1669                         adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
1670                         mutex_unlock(&adev->pm.mutex);
1671                 } else {
1672                         mutex_lock(&adev->pm.mutex);
1673                         adev->pm.dpm.uvd_active = false;
1674                         mutex_unlock(&adev->pm.mutex);
1675                 }
1676                 amdgpu_pm_compute_clocks(adev);
1677         }
1678 }
1679
1680 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
1681 {
1682         if (adev->powerplay.pp_funcs->powergate_vce) {
1683                 /* enable/disable VCE */
1684                 mutex_lock(&adev->pm.mutex);
1685                 amdgpu_dpm_powergate_vce(adev, !enable);
1686                 mutex_unlock(&adev->pm.mutex);
1687         } else {
1688                 if (enable) {
1689                         mutex_lock(&adev->pm.mutex);
1690                         adev->pm.dpm.vce_active = true;
1691                         /* XXX select vce level based on ring/task */
1692                         adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;
1693                         mutex_unlock(&adev->pm.mutex);
1694                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1695                                                                AMD_CG_STATE_UNGATE);
1696                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1697                                                                AMD_PG_STATE_UNGATE);
1698                         amdgpu_pm_compute_clocks(adev);
1699                 } else {
1700                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1701                                                                AMD_PG_STATE_GATE);
1702                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1703                                                                AMD_CG_STATE_GATE);
1704                         mutex_lock(&adev->pm.mutex);
1705                         adev->pm.dpm.vce_active = false;
1706                         mutex_unlock(&adev->pm.mutex);
1707                         amdgpu_pm_compute_clocks(adev);
1708                 }
1709
1710         }
1711 }
1712
1713 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
1714 {
1715         int i;
1716
1717         if (adev->powerplay.pp_funcs->print_power_state == NULL)
1718                 return;
1719
1720         for (i = 0; i < adev->pm.dpm.num_ps; i++)
1721                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
1722
1723 }
1724
1725 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
1726 {
1727         int ret;
1728
1729         if (adev->pm.sysfs_initialized)
1730                 return 0;
1731
1732         if (adev->pm.dpm_enabled == 0)
1733                 return 0;
1734
1735         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
1736                                                                    DRIVER_NAME, adev,
1737                                                                    hwmon_groups);
1738         if (IS_ERR(adev->pm.int_hwmon_dev)) {
1739                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
1740                 dev_err(adev->dev,
1741                         "Unable to register hwmon device: %d\n", ret);
1742                 return ret;
1743         }
1744
1745         ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
1746         if (ret) {
1747                 DRM_ERROR("failed to create device file for dpm state\n");
1748                 return ret;
1749         }
1750         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1751         if (ret) {
1752                 DRM_ERROR("failed to create device file for dpm state\n");
1753                 return ret;
1754         }
1755
1756
1757         ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
1758         if (ret) {
1759                 DRM_ERROR("failed to create device file pp_num_states\n");
1760                 return ret;
1761         }
1762         ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
1763         if (ret) {
1764                 DRM_ERROR("failed to create device file pp_cur_state\n");
1765                 return ret;
1766         }
1767         ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
1768         if (ret) {
1769                 DRM_ERROR("failed to create device file pp_force_state\n");
1770                 return ret;
1771         }
1772         ret = device_create_file(adev->dev, &dev_attr_pp_table);
1773         if (ret) {
1774                 DRM_ERROR("failed to create device file pp_table\n");
1775                 return ret;
1776         }
1777
1778         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
1779         if (ret) {
1780                 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
1781                 return ret;
1782         }
1783         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
1784         if (ret) {
1785                 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
1786                 return ret;
1787         }
1788         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
1789         if (ret) {
1790                 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
1791                 return ret;
1792         }
1793         ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
1794         if (ret) {
1795                 DRM_ERROR("failed to create device file pp_sclk_od\n");
1796                 return ret;
1797         }
1798         ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od);
1799         if (ret) {
1800                 DRM_ERROR("failed to create device file pp_mclk_od\n");
1801                 return ret;
1802         }
1803         ret = device_create_file(adev->dev,
1804                         &dev_attr_pp_power_profile_mode);
1805         if (ret) {
1806                 DRM_ERROR("failed to create device file "
1807                                 "pp_power_profile_mode\n");
1808                 return ret;
1809         }
1810         ret = device_create_file(adev->dev,
1811                         &dev_attr_pp_od_clk_voltage);
1812         if (ret) {
1813                 DRM_ERROR("failed to create device file "
1814                                 "pp_od_clk_voltage\n");
1815                 return ret;
1816         }
1817         ret = amdgpu_debugfs_pm_init(adev);
1818         if (ret) {
1819                 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1820                 return ret;
1821         }
1822
1823         adev->pm.sysfs_initialized = true;
1824
1825         return 0;
1826 }
1827
1828 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
1829 {
1830         if (adev->pm.dpm_enabled == 0)
1831                 return;
1832
1833         if (adev->pm.int_hwmon_dev)
1834                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
1835         device_remove_file(adev->dev, &dev_attr_power_dpm_state);
1836         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1837
1838         device_remove_file(adev->dev, &dev_attr_pp_num_states);
1839         device_remove_file(adev->dev, &dev_attr_pp_cur_state);
1840         device_remove_file(adev->dev, &dev_attr_pp_force_state);
1841         device_remove_file(adev->dev, &dev_attr_pp_table);
1842
1843         device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
1844         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
1845         device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
1846         device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
1847         device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
1848         device_remove_file(adev->dev,
1849                         &dev_attr_pp_power_profile_mode);
1850         device_remove_file(adev->dev,
1851                         &dev_attr_pp_od_clk_voltage);
1852 }
1853
1854 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
1855 {
1856         int i = 0;
1857
1858         if (!adev->pm.dpm_enabled)
1859                 return;
1860
1861         if (adev->mode_info.num_crtc)
1862                 amdgpu_display_bandwidth_update(adev);
1863
1864         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1865                 struct amdgpu_ring *ring = adev->rings[i];
1866                 if (ring && ring->ready)
1867                         amdgpu_fence_wait_empty(ring);
1868         }
1869
1870         if (!amdgpu_device_has_dc_support(adev)) {
1871                 mutex_lock(&adev->pm.mutex);
1872                 amdgpu_dpm_get_active_displays(adev);
1873                 adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtcs;
1874                 adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
1875                 adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
1876                 /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
1877                 if (adev->pm.pm_display_cfg.vrefresh > 120)
1878                         adev->pm.pm_display_cfg.min_vblank_time = 0;
1879                 if (adev->powerplay.pp_funcs->display_configuration_change)
1880                         adev->powerplay.pp_funcs->display_configuration_change(
1881                                                         adev->powerplay.pp_handle,
1882                                                         &adev->pm.pm_display_cfg);
1883                 mutex_unlock(&adev->pm.mutex);
1884         }
1885
1886         if (adev->powerplay.pp_funcs->dispatch_tasks) {
1887                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
1888         } else {
1889                 mutex_lock(&adev->pm.mutex);
1890                 /* update battery/ac status */
1891                 if (power_supply_is_system_supplied() > 0)
1892                         adev->pm.dpm.ac_power = true;
1893                 else
1894                         adev->pm.dpm.ac_power = false;
1895
1896                 amdgpu_dpm_change_power_state_locked(adev);
1897
1898                 mutex_unlock(&adev->pm.mutex);
1899         }
1900 }
1901
1902 /*
1903  * Debugfs info
1904  */
1905 #if defined(CONFIG_DEBUG_FS)
1906
1907 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
1908 {
1909         uint32_t value;
1910         uint32_t query = 0;
1911         int size;
1912
1913         /* sanity check PP is enabled */
1914         if (!(adev->powerplay.pp_funcs &&
1915               adev->powerplay.pp_funcs->read_sensor))
1916               return -EINVAL;
1917
1918         /* GPU Clocks */
1919         size = sizeof(value);
1920         seq_printf(m, "GFX Clocks and Power:\n");
1921         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
1922                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
1923         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
1924                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
1925         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
1926                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
1927         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
1928                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
1929         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
1930                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
1931         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
1932                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
1933         size = sizeof(uint32_t);
1934         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
1935                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
1936         size = sizeof(value);
1937         seq_printf(m, "\n");
1938
1939         /* GPU Temp */
1940         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
1941                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
1942
1943         /* GPU Load */
1944         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
1945                 seq_printf(m, "GPU Load: %u %%\n", value);
1946         seq_printf(m, "\n");
1947
1948         /* UVD clocks */
1949         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
1950                 if (!value) {
1951                         seq_printf(m, "UVD: Disabled\n");
1952                 } else {
1953                         seq_printf(m, "UVD: Enabled\n");
1954                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
1955                                 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
1956                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
1957                                 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
1958                 }
1959         }
1960         seq_printf(m, "\n");
1961
1962         /* VCE clocks */
1963         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
1964                 if (!value) {
1965                         seq_printf(m, "VCE: Disabled\n");
1966                 } else {
1967                         seq_printf(m, "VCE: Enabled\n");
1968                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
1969                                 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
1970                 }
1971         }
1972
1973         return 0;
1974 }
1975
1976 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
1977 {
1978         int i;
1979
1980         for (i = 0; clocks[i].flag; i++)
1981                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
1982                            (flags & clocks[i].flag) ? "On" : "Off");
1983 }
1984
1985 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
1986 {
1987         struct drm_info_node *node = (struct drm_info_node *) m->private;
1988         struct drm_device *dev = node->minor->dev;
1989         struct amdgpu_device *adev = dev->dev_private;
1990         struct drm_device *ddev = adev->ddev;
1991         u32 flags = 0;
1992
1993         amdgpu_device_ip_get_clockgating_state(adev, &flags);
1994         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
1995         amdgpu_parse_cg_state(m, flags);
1996         seq_printf(m, "\n");
1997
1998         if (!adev->pm.dpm_enabled) {
1999                 seq_printf(m, "dpm not enabled\n");
2000                 return 0;
2001         }
2002         if  ((adev->flags & AMD_IS_PX) &&
2003              (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
2004                 seq_printf(m, "PX asic powered off\n");
2005         } else if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
2006                 mutex_lock(&adev->pm.mutex);
2007                 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
2008                         adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
2009                 else
2010                         seq_printf(m, "Debugfs support not implemented for this asic\n");
2011                 mutex_unlock(&adev->pm.mutex);
2012         } else {
2013                 return amdgpu_debugfs_pm_info_pp(m, adev);
2014         }
2015
2016         return 0;
2017 }
2018
2019 static const struct drm_info_list amdgpu_pm_info_list[] = {
2020         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
2021 };
2022 #endif
2023
2024 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
2025 {
2026 #if defined(CONFIG_DEBUG_FS)
2027         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
2028 #else
2029         return 0;
2030 #endif
2031 }