drivers/gpu/drm/i915/i915_gpu_error.c

   1 /*
   2  * Copyright (c) 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <[email protected]>
  25  *    Keith Packard <[email protected]>
  26  *    Mika Kuoppala <[email protected]>
  27  *
  28  */
  29
  30 #include <linux/ascii85.h>
  31 #include <linux/nmi.h>
  32 #include <linux/pagevec.h>
  33 #include <linux/scatterlist.h>
  34 #include <linux/utsname.h>
  35 #include <linux/zlib.h>
  36
  37 #include <drm/drm_print.h>
  38
  39 #include "display/intel_atomic.h"
  40 #include "display/intel_csr.h"
  41 #include "display/intel_overlay.h"
  42
  43 #include "gem/i915_gem_context.h"
  44 #include "gem/i915_gem_lmem.h"
  45 #include "gt/intel_gt_pm.h"
  46
  47 #include "i915_drv.h"
  48 #include "i915_gpu_error.h"
  49 #include "i915_memcpy.h"
  50 #include "i915_scatterlist.h"
  51
  52 #define ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN)
  53 #define ATOMIC_MAYFAIL (GFP_ATOMIC | __GFP_NOWARN)
  54
  55 static void __sg_set_buf(struct scatterlist *sg,
  56                          void *addr, unsigned int len, loff_t it)
  57 {
  58         sg->page_link = (unsigned long)virt_to_page(addr);
  59         sg->offset = offset_in_page(addr);
  60         sg->length = len;
  61         sg->dma_address = it;
  62 }
  63
  64 static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len)
  65 {
  66         if (!len)
  67                 return false;
  68
  69         if (e->bytes + len + 1 <= e->size)
  70                 return true;
  71
  72         if (e->bytes) {
  73                 __sg_set_buf(e->cur++, e->buf, e->bytes, e->iter);
  74                 e->iter += e->bytes;
  75                 e->buf = NULL;
  76                 e->bytes = 0;
  77         }
  78
  79         if (e->cur == e->end) {
  80                 struct scatterlist *sgl;
  81
  82                 sgl = (typeof(sgl))__get_free_page(ALLOW_FAIL);
  83                 if (!sgl) {
  84                         e->err = -ENOMEM;
  85                         return false;
  86                 }
  87
  88                 if (e->cur) {
  89                         e->cur->offset = 0;
  90                         e->cur->length = 0;
  91                         e->cur->page_link =
  92                                 (unsigned long)sgl | SG_CHAIN;
  93                 } else {
  94                         e->sgl = sgl;
  95                 }
  96
  97                 e->cur = sgl;
  98                 e->end = sgl + SG_MAX_SINGLE_ALLOC - 1;
  99         }
 100
 101         e->size = ALIGN(len + 1, SZ_64K);
 102         e->buf = kmalloc(e->size, ALLOW_FAIL);
 103         if (!e->buf) {
 104                 e->size = PAGE_ALIGN(len + 1);
 105                 e->buf = kmalloc(e->size, GFP_KERNEL);
 106         }
 107         if (!e->buf) {
 108                 e->err = -ENOMEM;
 109                 return false;
 110         }
 111
 112         return true;
 113 }
 114
 115 __printf(2, 0)
 116 static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
 117                                const char *fmt, va_list args)
 118 {
 119         va_list ap;
 120         int len;
 121
 122         if (e->err)
 123                 return;
 124
 125         va_copy(ap, args);
 126         len = vsnprintf(NULL, 0, fmt, ap);
 127         va_end(ap);
 128         if (len <= 0) {
 129                 e->err = len;
 130                 return;
 131         }
 132
 133         if (!__i915_error_grow(e, len))
 134                 return;
 135
 136         GEM_BUG_ON(e->bytes >= e->size);
 137         len = vscnprintf(e->buf + e->bytes, e->size - e->bytes, fmt, args);
 138         if (len < 0) {
 139                 e->err = len;
 140                 return;
 141         }
 142         e->bytes += len;
 143 }
 144
 145 static void i915_error_puts(struct drm_i915_error_state_buf *e, const char *str)
 146 {
 147         unsigned len;
 148
 149         if (e->err || !str)
 150                 return;
 151
 152         len = strlen(str);
 153         if (!__i915_error_grow(e, len))
 154                 return;
 155
 156         GEM_BUG_ON(e->bytes + len > e->size);
 157         memcpy(e->buf + e->bytes, str, len);
 158         e->bytes += len;
 159 }
 160
 161 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
 162 #define err_puts(e, s) i915_error_puts(e, s)
 163
 164 static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf)
 165 {
 166         i915_error_vprintf(p->arg, vaf->fmt, *vaf->va);
 167 }
 168
 169 static inline struct drm_printer
 170 i915_error_printer(struct drm_i915_error_state_buf *e)
 171 {
 172         struct drm_printer p = {
 173                 .printfn = __i915_printfn_error,
 174                 .arg = e,
 175         };
 176         return p;
 177 }
 178
 179 /* single threaded page allocator with a reserved stash for emergencies */
 180 static void pool_fini(struct pagevec *pv)
 181 {
 182         pagevec_release(pv);
 183 }
 184
 185 static int pool_refill(struct pagevec *pv, gfp_t gfp)
 186 {
 187         while (pagevec_space(pv)) {
 188                 struct page *p;
 189
 190                 p = alloc_page(gfp);
 191                 if (!p)
 192                         return -ENOMEM;
 193
 194                 pagevec_add(pv, p);
 195         }
 196
 197         return 0;
 198 }
 199
 200 static int pool_init(struct pagevec *pv, gfp_t gfp)
 201 {
 202         int err;
 203
 204         pagevec_init(pv);
 205
 206         err = pool_refill(pv, gfp);
 207         if (err)
 208                 pool_fini(pv);
 209
 210         return err;
 211 }
 212
 213 static void *pool_alloc(struct pagevec *pv, gfp_t gfp)
 214 {
 215         struct page *p;
 216
 217         p = alloc_page(gfp);
 218         if (!p && pagevec_count(pv))
 219                 p = pv->pages[--pv->nr];
 220
 221         return p ? page_address(p) : NULL;
 222 }
 223
 224 static void pool_free(struct pagevec *pv, void *addr)
 225 {
 226         struct page *p = virt_to_page(addr);
 227
 228         if (pagevec_space(pv))
 229                 pagevec_add(pv, p);
 230         else
 231                 __free_page(p);
 232 }
 233
 234 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR
 235
 236 struct i915_vma_compress {
 237         struct pagevec pool;
 238         struct z_stream_s zstream;
 239         void *tmp;
 240 };
 241
 242 static bool compress_init(struct i915_vma_compress *c)
 243 {
 244         struct z_stream_s *zstream = &c->zstream;
 245
 246         if (pool_init(&c->pool, ALLOW_FAIL))
 247                 return false;
 248
 249         zstream->workspace =
 250                 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL),
 251                         ALLOW_FAIL);
 252         if (!zstream->workspace) {
 253                 pool_fini(&c->pool);
 254                 return false;
 255         }
 256
 257         c->tmp = NULL;
 258         if (i915_has_memcpy_from_wc())
 259                 c->tmp = pool_alloc(&c->pool, ALLOW_FAIL);
 260
 261         return true;
 262 }
 263
 264 static bool compress_start(struct i915_vma_compress *c)
 265 {
 266         struct z_stream_s *zstream = &c->zstream;
 267         void *workspace = zstream->workspace;
 268
 269         memset(zstream, 0, sizeof(*zstream));
 270         zstream->workspace = workspace;
 271
 272         return zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) == Z_OK;
 273 }
 274
 275 static void *compress_next_page(struct i915_vma_compress *c,
 276                                 struct i915_vma_coredump *dst)
 277 {
 278         void *page;
 279
 280         if (dst->page_count >= dst->num_pages)
 281                 return ERR_PTR(-ENOSPC);
 282
 283         page = pool_alloc(&c->pool, ALLOW_FAIL);
 284         if (!page)
 285                 return ERR_PTR(-ENOMEM);
 286
 287         return dst->pages[dst->page_count++] = page;
 288 }
 289
 290 static int compress_page(struct i915_vma_compress *c,
 291                          void *src,
 292                          struct i915_vma_coredump *dst,
 293                          bool wc)
 294 {
 295         struct z_stream_s *zstream = &c->zstream;
 296
 297         zstream->next_in = src;
 298         if (wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
 299                 zstream->next_in = c->tmp;
 300         zstream->avail_in = PAGE_SIZE;
 301
 302         do {
 303                 if (zstream->avail_out == 0) {
 304                         zstream->next_out = compress_next_page(c, dst);
 305                         if (IS_ERR(zstream->next_out))
 306                                 return PTR_ERR(zstream->next_out);
 307
 308                         zstream->avail_out = PAGE_SIZE;
 309                 }
 310
 311                 if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK)
 312                         return -EIO;
 313         } while (zstream->avail_in);
 314
 315         /* Fallback to uncompressed if we increase size? */
 316         if (0 && zstream->total_out > zstream->total_in)
 317                 return -E2BIG;
 318
 319         return 0;
 320 }
 321
 322 static int compress_flush(struct i915_vma_compress *c,
 323                           struct i915_vma_coredump *dst)
 324 {
 325         struct z_stream_s *zstream = &c->zstream;
 326
 327         do {
 328                 switch (zlib_deflate(zstream, Z_FINISH)) {
 329                 case Z_OK: /* more space requested */
 330                         zstream->next_out = compress_next_page(c, dst);
 331                         if (IS_ERR(zstream->next_out))
 332                                 return PTR_ERR(zstream->next_out);
 333
 334                         zstream->avail_out = PAGE_SIZE;
 335                         break;
 336
 337                 case Z_STREAM_END:
 338                         goto end;
 339
 340                 default: /* any error */
 341                         return -EIO;
 342                 }
 343         } while (1);
 344
 345 end:
 346         memset(zstream->next_out, 0, zstream->avail_out);
 347         dst->unused = zstream->avail_out;
 348         return 0;
 349 }
 350
 351 static void compress_finish(struct i915_vma_compress *c)
 352 {
 353         zlib_deflateEnd(&c->zstream);
 354 }
 355
 356 static void compress_fini(struct i915_vma_compress *c)
 357 {
 358         kfree(c->zstream.workspace);
 359         if (c->tmp)
 360                 pool_free(&c->pool, c->tmp);
 361         pool_fini(&c->pool);
 362 }
 363
 364 static void err_compression_marker(struct drm_i915_error_state_buf *m)
 365 {
 366         err_puts(m, ":");
 367 }
 368
 369 #else
 370
 371 struct i915_vma_compress {
 372         struct pagevec pool;
 373 };
 374
 375 static bool compress_init(struct i915_vma_compress *c)
 376 {
 377         return pool_init(&c->pool, ALLOW_FAIL) == 0;
 378 }
 379
 380 static bool compress_start(struct i915_vma_compress *c)
 381 {
 382         return true;
 383 }
 384
 385 static int compress_page(struct i915_vma_compress *c,
 386                          void *src,
 387                          struct i915_vma_coredump *dst,
 388                          bool wc)
 389 {
 390         void *ptr;
 391
 392         ptr = pool_alloc(&c->pool, ALLOW_FAIL);
 393         if (!ptr)
 394                 return -ENOMEM;
 395
 396         if (!(wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE)))
 397                 memcpy(ptr, src, PAGE_SIZE);
 398         dst->pages[dst->page_count++] = ptr;
 399
 400         return 0;
 401 }
 402
 403 static int compress_flush(struct i915_vma_compress *c,
 404                           struct i915_vma_coredump *dst)
 405 {
 406         return 0;
 407 }
 408
 409 static void compress_finish(struct i915_vma_compress *c)
 410 {
 411 }
 412
 413 static void compress_fini(struct i915_vma_compress *c)
 414 {
 415         pool_fini(&c->pool);
 416 }
 417
 418 static void err_compression_marker(struct drm_i915_error_state_buf *m)
 419 {
 420         err_puts(m, "~");
 421 }
 422
 423 #endif
 424
 425 static void error_print_instdone(struct drm_i915_error_state_buf *m,
 426                                  const struct intel_engine_coredump *ee)
 427 {
 428         const struct sseu_dev_info *sseu = &RUNTIME_INFO(m->i915)->sseu;
 429         int slice;
 430         int subslice;
 431
 432         err_printf(m, "  INSTDONE: 0x%08x\n",
 433                    ee->instdone.instdone);
 434
 435         if (ee->engine->class != RENDER_CLASS || INTEL_GEN(m->i915) <= 3)
 436                 return;
 437
 438         err_printf(m, "  SC_INSTDONE: 0x%08x\n",
 439                    ee->instdone.slice_common);
 440
 441         if (INTEL_GEN(m->i915) <= 6)
 442                 return;
 443
 444         for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice)
 445                 err_printf(m, "  SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
 446                            slice, subslice,
 447                            ee->instdone.sampler[slice][subslice]);
 448
 449         for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice)
 450                 err_printf(m, "  ROW_INSTDONE[%d][%d]: 0x%08x\n",
 451                            slice, subslice,
 452                            ee->instdone.row[slice][subslice]);
 453
 454         if (INTEL_GEN(m->i915) < 12)
 455                 return;
 456
 457         err_printf(m, "  SC_INSTDONE_EXTRA: 0x%08x\n",
 458                    ee->instdone.slice_common_extra[0]);
 459         err_printf(m, "  SC_INSTDONE_EXTRA2: 0x%08x\n",
 460                    ee->instdone.slice_common_extra[1]);
 461 }
 462
 463 static void error_print_request(struct drm_i915_error_state_buf *m,
 464                                 const char *prefix,
 465                                 const struct i915_request_coredump *erq)
 466 {
 467         if (!erq->seqno)
 468                 return;
 469
 470         err_printf(m, "%s pid %d, seqno %8x:%08x%s%s, prio %d, head %08x, tail %08x\n",
 471                    prefix, erq->pid, erq->context, erq->seqno,
 472                    test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
 473                             &erq->flags) ? "!" : "",
 474                    test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
 475                             &erq->flags) ? "+" : "",
 476                    erq->sched_attr.priority,
 477                    erq->head, erq->tail);
 478 }
 479
 480 static void error_print_context(struct drm_i915_error_state_buf *m,
 481                                 const char *header,
 482                                 const struct i915_gem_context_coredump *ctx)
 483 {
 484         const u32 period = RUNTIME_INFO(m->i915)->cs_timestamp_period_ns;
 485
 486         err_printf(m, "%s%s[%d] prio %d, guilty %d active %d, runtime total %lluns, avg %lluns\n",
 487                    header, ctx->comm, ctx->pid, ctx->sched_attr.priority,
 488                    ctx->guilty, ctx->active,
 489                    ctx->total_runtime * period,
 490                    mul_u32_u32(ctx->avg_runtime, period));
 491 }
 492
 493 static struct i915_vma_coredump *
 494 __find_vma(struct i915_vma_coredump *vma, const char *name)
 495 {
 496         while (vma) {
 497                 if (strcmp(vma->name, name) == 0)
 498                         return vma;
 499                 vma = vma->next;
 500         }
 501
 502         return NULL;
 503 }
 504
 505 static struct i915_vma_coredump *
 506 find_batch(const struct intel_engine_coredump *ee)
 507 {
 508         return __find_vma(ee->vma, "batch");
 509 }
 510
 511 static void error_print_engine(struct drm_i915_error_state_buf *m,
 512                                const struct intel_engine_coredump *ee)
 513 {
 514         struct i915_vma_coredump *batch;
 515         int n;
 516
 517         err_printf(m, "%s command stream:\n", ee->engine->name);
 518         err_printf(m, "  CCID:  0x%08x\n", ee->ccid);
 519         err_printf(m, "  START: 0x%08x\n", ee->start);
 520         err_printf(m, "  HEAD:  0x%08x [0x%08x]\n", ee->head, ee->rq_head);
 521         err_printf(m, "  TAIL:  0x%08x [0x%08x, 0x%08x]\n",
 522                    ee->tail, ee->rq_post, ee->rq_tail);
 523         err_printf(m, "  CTL:   0x%08x\n", ee->ctl);
 524         err_printf(m, "  MODE:  0x%08x\n", ee->mode);
 525         err_printf(m, "  HWS:   0x%08x\n", ee->hws);
 526         err_printf(m, "  ACTHD: 0x%08x %08x\n",
 527                    (u32)(ee->acthd>>32), (u32)ee->acthd);
 528         err_printf(m, "  IPEIR: 0x%08x\n", ee->ipeir);
 529         err_printf(m, "  IPEHR: 0x%08x\n", ee->ipehr);
 530         err_printf(m, "  ESR:   0x%08x\n", ee->esr);
 531
 532         error_print_instdone(m, ee);
 533
 534         batch = find_batch(ee);
 535         if (batch) {
 536                 u64 start = batch->gtt_offset;
 537                 u64 end = start + batch->gtt_size;
 538
 539                 err_printf(m, "  batch: [0x%08x_%08x, 0x%08x_%08x]\n",
 540                            upper_32_bits(start), lower_32_bits(start),
 541                            upper_32_bits(end), lower_32_bits(end));
 542         }
 543         if (INTEL_GEN(m->i915) >= 4) {
 544                 err_printf(m, "  BBADDR: 0x%08x_%08x\n",
 545                            (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);
 546                 err_printf(m, "  BB_STATE: 0x%08x\n", ee->bbstate);
 547                 err_printf(m, "  INSTPS: 0x%08x\n", ee->instps);
 548         }
 549         err_printf(m, "  INSTPM: 0x%08x\n", ee->instpm);
 550         err_printf(m, "  FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),
 551                    lower_32_bits(ee->faddr));
 552         if (INTEL_GEN(m->i915) >= 6) {
 553                 err_printf(m, "  RC PSMI: 0x%08x\n", ee->rc_psmi);
 554                 err_printf(m, "  FAULT_REG: 0x%08x\n", ee->fault_reg);
 555         }
 556         if (HAS_PPGTT(m->i915)) {
 557                 err_printf(m, "  GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
 558
 559                 if (INTEL_GEN(m->i915) >= 8) {
 560                         int i;
 561                         for (i = 0; i < 4; i++)
 562                                 err_printf(m, "  PDP%d: 0x%016llx\n",
 563                                            i, ee->vm_info.pdp[i]);
 564                 } else {
 565                         err_printf(m, "  PP_DIR_BASE: 0x%08x\n",
 566                                    ee->vm_info.pp_dir_base);
 567                 }
 568         }
 569         err_printf(m, "  engine reset count: %u\n", ee->reset_count);
 570
 571         for (n = 0; n < ee->num_ports; n++) {
 572                 err_printf(m, "  ELSP[%d]:", n);
 573                 error_print_request(m, " ", &ee->execlist[n]);
 574         }
 575
 576         error_print_context(m, "  Active context: ", &ee->context);
 577 }
 578
 579 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
 580 {
 581         va_list args;
 582
 583         va_start(args, f);
 584         i915_error_vprintf(e, f, args);
 585         va_end(args);
 586 }
 587
 588 static void print_error_vma(struct drm_i915_error_state_buf *m,
 589                             const struct intel_engine_cs *engine,
 590                             const struct i915_vma_coredump *vma)
 591 {
 592         char out[ASCII85_BUFSZ];
 593         int page;
 594
 595         if (!vma)
 596                 return;
 597
 598         err_printf(m, "%s --- %s = 0x%08x %08x\n",
 599                    engine ? engine->name : "global", vma->name,
 600                    upper_32_bits(vma->gtt_offset),
 601                    lower_32_bits(vma->gtt_offset));
 602
 603         if (vma->gtt_page_sizes > I915_GTT_PAGE_SIZE_4K)
 604                 err_printf(m, "gtt_page_sizes = 0x%08x\n", vma->gtt_page_sizes);
 605
 606         err_compression_marker(m);
 607         for (page = 0; page < vma->page_count; page++) {
 608                 int i, len;
 609
 610                 len = PAGE_SIZE;
 611                 if (page == vma->page_count - 1)
 612                         len -= vma->unused;
 613                 len = ascii85_encode_len(len);
 614
 615                 for (i = 0; i < len; i++)
 616                         err_puts(m, ascii85_encode(vma->pages[page][i], out));
 617         }
 618         err_puts(m, "\n");
 619 }
 620
 621 static void err_print_capabilities(struct drm_i915_error_state_buf *m,
 622                                    const struct intel_device_info *info,
 623                                    const struct intel_runtime_info *runtime,
 624                                    const struct intel_driver_caps *caps)
 625 {
 626         struct drm_printer p = i915_error_printer(m);
 627
 628         intel_device_info_print_static(info, &p);
 629         intel_device_info_print_runtime(runtime, &p);
 630         intel_device_info_print_topology(&runtime->sseu, &p);
 631         intel_driver_caps_print(caps, &p);
 632 }
 633
 634 static void err_print_params(struct drm_i915_error_state_buf *m,
 635                              const struct i915_params *params)
 636 {
 637         struct drm_printer p = i915_error_printer(m);
 638
 639         i915_params_dump(params, &p);
 640 }
 641
 642 static void err_print_pciid(struct drm_i915_error_state_buf *m,
 643                             struct drm_i915_private *i915)
 644 {
 645         struct pci_dev *pdev = i915->drm.pdev;
 646
 647         err_printf(m, "PCI ID: 0x%04x\n", pdev->device);
 648         err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision);
 649         err_printf(m, "PCI Subsystem: %04x:%04x\n",
 650                    pdev->subsystem_vendor,
 651                    pdev->subsystem_device);
 652 }
 653
 654 static void err_print_uc(struct drm_i915_error_state_buf *m,
 655                          const struct intel_uc_coredump *error_uc)
 656 {
 657         struct drm_printer p = i915_error_printer(m);
 658
 659         intel_uc_fw_dump(&error_uc->guc_fw, &p);
 660         intel_uc_fw_dump(&error_uc->huc_fw, &p);
 661         print_error_vma(m, NULL, error_uc->guc_log);
 662 }
 663
 664 static void err_free_sgl(struct scatterlist *sgl)
 665 {
 666         while (sgl) {
 667                 struct scatterlist *sg;
 668
 669                 for (sg = sgl; !sg_is_chain(sg); sg++) {
 670                         kfree(sg_virt(sg));
 671                         if (sg_is_last(sg))
 672                                 break;
 673                 }
 674
 675                 sg = sg_is_last(sg) ? NULL : sg_chain_ptr(sg);
 676                 free_page((unsigned long)sgl);
 677                 sgl = sg;
 678         }
 679 }
 680
 681 static void err_print_gt(struct drm_i915_error_state_buf *m,
 682                          struct intel_gt_coredump *gt)
 683 {
 684         const struct intel_engine_coredump *ee;
 685         int i;
 686
 687         err_printf(m, "GT awake: %s\n", yesno(gt->awake));
 688         err_printf(m, "EIR: 0x%08x\n", gt->eir);
 689         err_printf(m, "IER: 0x%08x\n", gt->ier);
 690         for (i = 0; i < gt->ngtier; i++)
 691                 err_printf(m, "GTIER[%d]: 0x%08x\n", i, gt->gtier[i]);
 692         err_printf(m, "PGTBL_ER: 0x%08x\n", gt->pgtbl_er);
 693         err_printf(m, "FORCEWAKE: 0x%08x\n", gt->forcewake);
 694         err_printf(m, "DERRMR: 0x%08x\n", gt->derrmr);
 695
 696         for (i = 0; i < gt->nfence; i++)
 697                 err_printf(m, "  fence[%d] = %08llx\n", i, gt->fence[i]);
 698
 699         if (IS_GEN_RANGE(m->i915, 6, 11)) {
 700                 err_printf(m, "ERROR: 0x%08x\n", gt->error);
 701                 err_printf(m, "DONE_REG: 0x%08x\n", gt->done_reg);
 702         }
 703
 704         if (INTEL_GEN(m->i915) >= 8)
 705                 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
 706                            gt->fault_data1, gt->fault_data0);
 707
 708         if (IS_GEN(m->i915, 7))
 709                 err_printf(m, "ERR_INT: 0x%08x\n", gt->err_int);
 710
 711         if (IS_GEN_RANGE(m->i915, 8, 11))
 712                 err_printf(m, "GTT_CACHE_EN: 0x%08x\n", gt->gtt_cache);
 713
 714         if (IS_GEN(m->i915, 12))
 715                 err_printf(m, "AUX_ERR_DBG: 0x%08x\n", gt->aux_err);
 716
 717         if (INTEL_GEN(m->i915) >= 12) {
 718                 int i;
 719
 720                 for (i = 0; i < GEN12_SFC_DONE_MAX; i++)
 721                         err_printf(m, "  SFC_DONE[%d]: 0x%08x\n", i,
 722                                    gt->sfc_done[i]);
 723
 724                 err_printf(m, "  GAM_DONE: 0x%08x\n", gt->gam_done);
 725         }
 726
 727         for (ee = gt->engine; ee; ee = ee->next) {
 728                 const struct i915_vma_coredump *vma;
 729
 730                 error_print_engine(m, ee);
 731                 for (vma = ee->vma; vma; vma = vma->next)
 732                         print_error_vma(m, ee->engine, vma);
 733         }
 734
 735         if (gt->uc)
 736                 err_print_uc(m, gt->uc);
 737 }
 738
 739 static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
 740                                struct i915_gpu_coredump *error)
 741 {
 742         const struct intel_engine_coredump *ee;
 743         struct timespec64 ts;
 744
 745         if (*error->error_msg)
 746                 err_printf(m, "%s\n", error->error_msg);
 747         err_printf(m, "Kernel: %s %s\n",
 748                    init_utsname()->release,
 749                    init_utsname()->machine);
 750         err_printf(m, "Driver: %s\n", DRIVER_DATE);
 751         ts = ktime_to_timespec64(error->time);
 752         err_printf(m, "Time: %lld s %ld us\n",
 753                    (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
 754         ts = ktime_to_timespec64(error->boottime);
 755         err_printf(m, "Boottime: %lld s %ld us\n",
 756                    (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
 757         ts = ktime_to_timespec64(error->uptime);
 758         err_printf(m, "Uptime: %lld s %ld us\n",
 759                    (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
 760         err_printf(m, "Capture: %lu jiffies; %d ms ago\n",
 761                    error->capture, jiffies_to_msecs(jiffies - error->capture));
 762
 763         for (ee = error->gt ? error->gt->engine : NULL; ee; ee = ee->next)
 764                 err_printf(m, "Active process (on ring %s): %s [%d]\n",
 765                            ee->engine->name,
 766                            ee->context.comm,
 767                            ee->context.pid);
 768
 769         err_printf(m, "Reset count: %u\n", error->reset_count);
 770         err_printf(m, "Suspend count: %u\n", error->suspend_count);
 771         err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform));
 772         err_printf(m, "Subplatform: 0x%x\n",
 773                    intel_subplatform(&error->runtime_info,
 774                                      error->device_info.platform));
 775         err_print_pciid(m, m->i915);
 776
 777         err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
 778
 779         if (HAS_CSR(m->i915)) {
 780                 struct intel_csr *csr = &m->i915->csr;
 781
 782                 err_printf(m, "DMC loaded: %s\n",
 783                            yesno(csr->dmc_payload != NULL));
 784                 err_printf(m, "DMC fw version: %d.%d\n",
 785                            CSR_VERSION_MAJOR(csr->version),
 786                            CSR_VERSION_MINOR(csr->version));
 787         }
 788
 789         err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock));
 790         err_printf(m, "PM suspended: %s\n", yesno(error->suspended));
 791
 792         if (error->gt)
 793                 err_print_gt(m, error->gt);
 794
 795         if (error->overlay)
 796                 intel_overlay_print_error_state(m, error->overlay);
 797
 798         if (error->display)
 799                 intel_display_print_error_state(m, error->display);
 800
 801         err_print_capabilities(m, &error->device_info, &error->runtime_info,
 802                                &error->driver_caps);
 803         err_print_params(m, &error->params);
 804 }
 805
 806 static int err_print_to_sgl(struct i915_gpu_coredump *error)
 807 {
 808         struct drm_i915_error_state_buf m;
 809
 810         if (IS_ERR(error))
 811                 return PTR_ERR(error);
 812
 813         if (READ_ONCE(error->sgl))
 814                 return 0;
 815
 816         memset(&m, 0, sizeof(m));
 817         m.i915 = error->i915;
 818
 819         __err_print_to_sgl(&m, error);
 820
 821         if (m.buf) {
 822                 __sg_set_buf(m.cur++, m.buf, m.bytes, m.iter);
 823                 m.bytes = 0;
 824                 m.buf = NULL;
 825         }
 826         if (m.cur) {
 827                 GEM_BUG_ON(m.end < m.cur);
 828                 sg_mark_end(m.cur - 1);
 829         }
 830         GEM_BUG_ON(m.sgl && !m.cur);
 831
 832         if (m.err) {
 833                 err_free_sgl(m.sgl);
 834                 return m.err;
 835         }
 836
 837         if (cmpxchg(&error->sgl, NULL, m.sgl))
 838                 err_free_sgl(m.sgl);
 839
 840         return 0;
 841 }
 842
 843 ssize_t i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error,
 844                                          char *buf, loff_t off, size_t rem)
 845 {
 846         struct scatterlist *sg;
 847         size_t count;
 848         loff_t pos;
 849         int err;
 850
 851         if (!error || !rem)
 852                 return 0;
 853
 854         err = err_print_to_sgl(error);
 855         if (err)
 856                 return err;
 857
 858         sg = READ_ONCE(error->fit);
 859         if (!sg || off < sg->dma_address)
 860                 sg = error->sgl;
 861         if (!sg)
 862                 return 0;
 863
 864         pos = sg->dma_address;
 865         count = 0;
 866         do {
 867                 size_t len, start;
 868
 869                 if (sg_is_chain(sg)) {
 870                         sg = sg_chain_ptr(sg);
 871                         GEM_BUG_ON(sg_is_chain(sg));
 872                 }
 873
 874                 len = sg->length;
 875                 if (pos + len <= off) {
 876                         pos += len;
 877                         continue;
 878                 }
 879
 880                 start = sg->offset;
 881                 if (pos < off) {
 882                         GEM_BUG_ON(off - pos > len);
 883                         len -= off - pos;
 884                         start += off - pos;
 885                         pos = off;
 886                 }
 887
 888                 len = min(len, rem);
 889                 GEM_BUG_ON(!len || len > sg->length);
 890
 891                 memcpy(buf, page_address(sg_page(sg)) + start, len);
 892
 893                 count += len;
 894                 pos += len;
 895
 896                 buf += len;
 897                 rem -= len;
 898                 if (!rem) {
 899                         WRITE_ONCE(error->fit, sg);
 900                         break;
 901                 }
 902         } while (!sg_is_last(sg++));
 903
 904         return count;
 905 }
 906
 907 static void i915_vma_coredump_free(struct i915_vma_coredump *vma)
 908 {
 909         while (vma) {
 910                 struct i915_vma_coredump *next = vma->next;
 911                 int page;
 912
 913                 for (page = 0; page < vma->page_count; page++)
 914                         free_page((unsigned long)vma->pages[page]);
 915
 916                 kfree(vma);
 917                 vma = next;
 918         }
 919 }
 920
 921 static void cleanup_params(struct i915_gpu_coredump *error)
 922 {
 923         i915_params_free(&error->params);
 924 }
 925
 926 static void cleanup_uc(struct intel_uc_coredump *uc)
 927 {
 928         kfree(uc->guc_fw.path);
 929         kfree(uc->huc_fw.path);
 930         i915_vma_coredump_free(uc->guc_log);
 931
 932         kfree(uc);
 933 }
 934
 935 static void cleanup_gt(struct intel_gt_coredump *gt)
 936 {
 937         while (gt->engine) {
 938                 struct intel_engine_coredump *ee = gt->engine;
 939
 940                 gt->engine = ee->next;
 941
 942                 i915_vma_coredump_free(ee->vma);
 943                 kfree(ee);
 944         }
 945
 946         if (gt->uc)
 947                 cleanup_uc(gt->uc);
 948
 949         kfree(gt);
 950 }
 951
 952 void __i915_gpu_coredump_free(struct kref *error_ref)
 953 {
 954         struct i915_gpu_coredump *error =
 955                 container_of(error_ref, typeof(*error), ref);
 956
 957         while (error->gt) {
 958                 struct intel_gt_coredump *gt = error->gt;
 959
 960                 error->gt = gt->next;
 961                 cleanup_gt(gt);
 962         }
 963
 964         kfree(error->overlay);
 965         kfree(error->display);
 966
 967         cleanup_params(error);
 968
 969         err_free_sgl(error->sgl);
 970         kfree(error);
 971 }
 972
 973 static struct i915_vma_coredump *
 974 i915_vma_coredump_create(const struct intel_gt *gt,
 975                          const struct i915_vma *vma,
 976                          const char *name,
 977                          struct i915_vma_compress *compress)
 978 {
 979         struct i915_ggtt *ggtt = gt->ggtt;
 980         const u64 slot = ggtt->error_capture.start;
 981         struct i915_vma_coredump *dst;
 982         unsigned long num_pages;
 983         struct sgt_iter iter;
 984         int ret;
 985
 986         might_sleep();
 987
 988         if (!vma || !vma->pages || !compress)
 989                 return NULL;
 990
 991         num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT;
 992         num_pages = DIV_ROUND_UP(10 * num_pages, 8); /* worstcase zlib growth */
 993         dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), ALLOW_FAIL);
 994         if (!dst)
 995                 return NULL;
 996
 997         if (!compress_start(compress)) {
 998                 kfree(dst);
 999                 return NULL;
1000         }
1001
1002         strcpy(dst->name, name);
1003         dst->next = NULL;
1004
1005         dst->gtt_offset = vma->node.start;
1006         dst->gtt_size = vma->node.size;
1007         dst->gtt_page_sizes = vma->page_sizes.gtt;
1008         dst->num_pages = num_pages;
1009         dst->page_count = 0;
1010         dst->unused = 0;
1011
1012         ret = -EINVAL;
1013         if (drm_mm_node_allocated(&ggtt->error_capture)) {
1014                 void __iomem *s;
1015                 dma_addr_t dma;
1016
1017                 for_each_sgt_daddr(dma, iter, vma->pages) {
1018                         ggtt->vm.insert_page(&ggtt->vm, dma, slot,
1019                                              I915_CACHE_NONE, 0);
1020                         mb();
1021
1022                         s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE);
1023                         ret = compress_page(compress,
1024                                             (void  __force *)s, dst,
1025                                             true);
1026                         io_mapping_unmap(s);
1027                         if (ret)
1028                                 break;
1029                 }
1030         } else if (i915_gem_object_is_lmem(vma->obj)) {
1031                 struct intel_memory_region *mem = vma->obj->mm.region;
1032                 dma_addr_t dma;
1033
1034                 for_each_sgt_daddr(dma, iter, vma->pages) {
1035                         void __iomem *s;
1036
1037                         s = io_mapping_map_wc(&mem->iomap, dma, PAGE_SIZE);
1038                         ret = compress_page(compress,
1039                                             (void __force *)s, dst,
1040                                             true);
1041                         io_mapping_unmap(s);
1042                         if (ret)
1043                                 break;
1044                 }
1045         } else {
1046                 struct page *page;
1047
1048                 for_each_sgt_page(page, iter, vma->pages) {
1049                         void *s;
1050
1051                         drm_clflush_pages(&page, 1);
1052
1053                         s = kmap(page);
1054                         ret = compress_page(compress, s, dst, false);
1055                         kunmap(page);
1056
1057                         drm_clflush_pages(&page, 1);
1058
1059                         if (ret)
1060                                 break;
1061                 }
1062         }
1063
1064         if (ret || compress_flush(compress, dst)) {
1065                 while (dst->page_count--)
1066                         pool_free(&compress->pool, dst->pages[dst->page_count]);
1067                 kfree(dst);
1068                 dst = NULL;
1069         }
1070         compress_finish(compress);
1071
1072         return dst;
1073 }
1074
1075 static void gt_record_fences(struct intel_gt_coredump *gt)
1076 {
1077         struct i915_ggtt *ggtt = gt->_gt->ggtt;
1078         struct intel_uncore *uncore = gt->_gt->uncore;
1079         int i;
1080
1081         if (INTEL_GEN(uncore->i915) >= 6) {
1082                 for (i = 0; i < ggtt->num_fences; i++)
1083                         gt->fence[i] =
1084                                 intel_uncore_read64(uncore,
1085                                                     FENCE_REG_GEN6_LO(i));
1086         } else if (INTEL_GEN(uncore->i915) >= 4) {
1087                 for (i = 0; i < ggtt->num_fences; i++)
1088                         gt->fence[i] =
1089                                 intel_uncore_read64(uncore,
1090                                                     FENCE_REG_965_LO(i));
1091         } else {
1092                 for (i = 0; i < ggtt->num_fences; i++)
1093                         gt->fence[i] =
1094                                 intel_uncore_read(uncore, FENCE_REG(i));
1095         }
1096         gt->nfence = i;
1097 }
1098
1099 static void engine_record_registers(struct intel_engine_coredump *ee)
1100 {
1101         const struct intel_engine_cs *engine = ee->engine;
1102         struct drm_i915_private *i915 = engine->i915;
1103
1104         if (INTEL_GEN(i915) >= 6) {
1105                 ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL);
1106
1107                 if (INTEL_GEN(i915) >= 12)
1108                         ee->fault_reg = intel_uncore_read(engine->uncore,
1109                                                           GEN12_RING_FAULT_REG);
1110                 else if (INTEL_GEN(i915) >= 8)
1111                         ee->fault_reg = intel_uncore_read(engine->uncore,
1112                                                           GEN8_RING_FAULT_REG);
1113                 else
1114                         ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine);
1115         }
1116
1117         if (INTEL_GEN(i915) >= 4) {
1118                 ee->esr = ENGINE_READ(engine, RING_ESR);
1119                 ee->faddr = ENGINE_READ(engine, RING_DMA_FADD);
1120                 ee->ipeir = ENGINE_READ(engine, RING_IPEIR);
1121                 ee->ipehr = ENGINE_READ(engine, RING_IPEHR);
1122                 ee->instps = ENGINE_READ(engine, RING_INSTPS);
1123                 ee->bbaddr = ENGINE_READ(engine, RING_BBADDR);
1124                 ee->ccid = ENGINE_READ(engine, CCID);
1125                 if (INTEL_GEN(i915) >= 8) {
1126                         ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32;
1127                         ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32;
1128                 }
1129                 ee->bbstate = ENGINE_READ(engine, RING_BBSTATE);
1130         } else {
1131                 ee->faddr = ENGINE_READ(engine, DMA_FADD_I8XX);
1132                 ee->ipeir = ENGINE_READ(engine, IPEIR);
1133                 ee->ipehr = ENGINE_READ(engine, IPEHR);
1134         }
1135
1136         intel_engine_get_instdone(engine, &ee->instdone);
1137
1138         ee->instpm = ENGINE_READ(engine, RING_INSTPM);
1139         ee->acthd = intel_engine_get_active_head(engine);
1140         ee->start = ENGINE_READ(engine, RING_START);
1141         ee->head = ENGINE_READ(engine, RING_HEAD);
1142         ee->tail = ENGINE_READ(engine, RING_TAIL);
1143         ee->ctl = ENGINE_READ(engine, RING_CTL);
1144         if (INTEL_GEN(i915) > 2)
1145                 ee->mode = ENGINE_READ(engine, RING_MI_MODE);
1146
1147         if (!HWS_NEEDS_PHYSICAL(i915)) {
1148                 i915_reg_t mmio;
1149
1150                 if (IS_GEN(i915, 7)) {
1151                         switch (engine->id) {
1152                         default:
1153                                 MISSING_CASE(engine->id);
1154                                 /* fall through */
1155                         case RCS0:
1156                                 mmio = RENDER_HWS_PGA_GEN7;
1157                                 break;
1158                         case BCS0:
1159                                 mmio = BLT_HWS_PGA_GEN7;
1160                                 break;
1161                         case VCS0:
1162                                 mmio = BSD_HWS_PGA_GEN7;
1163                                 break;
1164                         case VECS0:
1165                                 mmio = VEBOX_HWS_PGA_GEN7;
1166                                 break;
1167                         }
1168                 } else if (IS_GEN(engine->i915, 6)) {
1169                         mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
1170                 } else {
1171                         /* XXX: gen8 returns to sanity */
1172                         mmio = RING_HWS_PGA(engine->mmio_base);
1173                 }
1174
1175                 ee->hws = intel_uncore_read(engine->uncore, mmio);
1176         }
1177
1178         ee->reset_count = i915_reset_engine_count(&i915->gpu_error, engine);
1179
1180         if (HAS_PPGTT(i915)) {
1181                 int i;
1182
1183                 ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7);
1184
1185                 if (IS_GEN(i915, 6)) {
1186                         ee->vm_info.pp_dir_base =
1187                                 ENGINE_READ(engine, RING_PP_DIR_BASE_READ);
1188                 } else if (IS_GEN(i915, 7)) {
1189                         ee->vm_info.pp_dir_base =
1190                                 ENGINE_READ(engine, RING_PP_DIR_BASE);
1191                 } else if (INTEL_GEN(i915) >= 8) {
1192                         u32 base = engine->mmio_base;
1193
1194                         for (i = 0; i < 4; i++) {
1195                                 ee->vm_info.pdp[i] =
1196                                         intel_uncore_read(engine->uncore,
1197                                                           GEN8_RING_PDP_UDW(base, i));
1198                                 ee->vm_info.pdp[i] <<= 32;
1199                                 ee->vm_info.pdp[i] |=
1200                                         intel_uncore_read(engine->uncore,
1201                                                           GEN8_RING_PDP_LDW(base, i));
1202                         }
1203                 }
1204         }
1205 }
1206
1207 static void record_request(const struct i915_request *request,
1208                            struct i915_request_coredump *erq)
1209 {
1210         erq->flags = request->fence.flags;
1211         erq->context = request->fence.context;
1212         erq->seqno = request->fence.seqno;
1213         erq->sched_attr = request->sched.attr;
1214         erq->head = request->head;
1215         erq->tail = request->tail;
1216
1217         erq->pid = 0;
1218         rcu_read_lock();
1219         if (!intel_context_is_closed(request->context)) {
1220                 const struct i915_gem_context *ctx;
1221
1222                 ctx = rcu_dereference(request->context->gem_context);
1223                 if (ctx)
1224                         erq->pid = pid_nr(ctx->pid);
1225         }
1226         rcu_read_unlock();
1227 }
1228
1229 static void engine_record_execlists(struct intel_engine_coredump *ee)
1230 {
1231         const struct intel_engine_execlists * const el = &ee->engine->execlists;
1232         struct i915_request * const *port = el->active;
1233         unsigned int n = 0;
1234
1235         while (*port)
1236                 record_request(*port++, &ee->execlist[n++]);
1237
1238         ee->num_ports = n;
1239 }
1240
1241 static bool record_context(struct i915_gem_context_coredump *e,
1242                            const struct i915_request *rq)
1243 {
1244         struct i915_gem_context *ctx;
1245         struct task_struct *task;
1246         bool simulated;
1247
1248         rcu_read_lock();
1249         ctx = rcu_dereference(rq->context->gem_context);
1250         if (ctx && !kref_get_unless_zero(&ctx->ref))
1251                 ctx = NULL;
1252         rcu_read_unlock();
1253         if (!ctx)
1254                 return true;
1255
1256         rcu_read_lock();
1257         task = pid_task(ctx->pid, PIDTYPE_PID);
1258         if (task) {
1259                 strcpy(e->comm, task->comm);
1260                 e->pid = task->pid;
1261         }
1262         rcu_read_unlock();
1263
1264         e->sched_attr = ctx->sched;
1265         e->guilty = atomic_read(&ctx->guilty_count);
1266         e->active = atomic_read(&ctx->active_count);
1267
1268         e->total_runtime = rq->context->runtime.total;
1269         e->avg_runtime = ewma_runtime_read(&rq->context->runtime.avg);
1270
1271         simulated = i915_gem_context_no_error_capture(ctx);
1272
1273         i915_gem_context_put(ctx);
1274         return simulated;
1275 }
1276
1277 struct intel_engine_capture_vma {
1278         struct intel_engine_capture_vma *next;
1279         struct i915_vma *vma;
1280         char name[16];
1281 };
1282
1283 static struct intel_engine_capture_vma *
1284 capture_vma(struct intel_engine_capture_vma *next,
1285             struct i915_vma *vma,
1286             const char *name,
1287             gfp_t gfp)
1288 {
1289         struct intel_engine_capture_vma *c;
1290
1291         if (!vma)
1292                 return next;
1293
1294         c = kmalloc(sizeof(*c), gfp);
1295         if (!c)
1296                 return next;
1297
1298         if (!i915_active_acquire_if_busy(&vma->active)) {
1299                 kfree(c);
1300                 return next;
1301         }
1302
1303         strcpy(c->name, name);
1304         c->vma = i915_vma_get(vma);
1305
1306         c->next = next;
1307         return c;
1308 }
1309
1310 static struct intel_engine_capture_vma *
1311 capture_user(struct intel_engine_capture_vma *capture,
1312              const struct i915_request *rq,
1313              gfp_t gfp)
1314 {
1315         struct i915_capture_list *c;
1316
1317         for (c = rq->capture_list; c; c = c->next)
1318                 capture = capture_vma(capture, c->vma, "user", gfp);
1319
1320         return capture;
1321 }
1322
1323 static void add_vma(struct intel_engine_coredump *ee,
1324                     struct i915_vma_coredump *vma)
1325 {
1326         if (vma) {
1327                 vma->next = ee->vma;
1328                 ee->vma = vma;
1329         }
1330 }
1331
1332 struct intel_engine_coredump *
1333 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp)
1334 {
1335         struct intel_engine_coredump *ee;
1336
1337         ee = kzalloc(sizeof(*ee), gfp);
1338         if (!ee)
1339                 return NULL;
1340
1341         ee->engine = engine;
1342
1343         engine_record_registers(ee);
1344         engine_record_execlists(ee);
1345
1346         return ee;
1347 }
1348
1349 struct intel_engine_capture_vma *
1350 intel_engine_coredump_add_request(struct intel_engine_coredump *ee,
1351                                   struct i915_request *rq,
1352                                   gfp_t gfp)
1353 {
1354         struct intel_engine_capture_vma *vma = NULL;
1355
1356         ee->simulated |= record_context(&ee->context, rq);
1357         if (ee->simulated)
1358                 return NULL;
1359
1360         /*
1361          * We need to copy these to an anonymous buffer
1362          * as the simplest method to avoid being overwritten
1363          * by userspace.
1364          */
1365         vma = capture_vma(vma, rq->batch, "batch", gfp);
1366         vma = capture_user(vma, rq, gfp);
1367         vma = capture_vma(vma, rq->ring->vma, "ring", gfp);
1368         vma = capture_vma(vma, rq->context->state, "HW context", gfp);
1369
1370         ee->rq_head = rq->head;
1371         ee->rq_post = rq->postfix;
1372         ee->rq_tail = rq->tail;
1373
1374         return vma;
1375 }
1376
1377 void
1378 intel_engine_coredump_add_vma(struct intel_engine_coredump *ee,
1379                               struct intel_engine_capture_vma *capture,
1380                               struct i915_vma_compress *compress)
1381 {
1382         const struct intel_engine_cs *engine = ee->engine;
1383
1384         while (capture) {
1385                 struct intel_engine_capture_vma *this = capture;
1386                 struct i915_vma *vma = this->vma;
1387
1388                 add_vma(ee,
1389                         i915_vma_coredump_create(engine->gt,
1390                                                  vma, this->name,
1391                                                  compress));
1392
1393                 i915_active_release(&vma->active);
1394                 i915_vma_put(vma);
1395
1396                 capture = this->next;
1397                 kfree(this);
1398         }
1399
1400         add_vma(ee,
1401                 i915_vma_coredump_create(engine->gt,
1402                                          engine->status_page.vma,
1403                                          "HW Status",
1404                                          compress));
1405
1406         add_vma(ee,
1407                 i915_vma_coredump_create(engine->gt,
1408                                          engine->wa_ctx.vma,
1409                                          "WA context",
1410                                          compress));
1411 }
1412
1413 static struct intel_engine_coredump *
1414 capture_engine(struct intel_engine_cs *engine,
1415                struct i915_vma_compress *compress)
1416 {
1417         struct intel_engine_capture_vma *capture = NULL;
1418         struct intel_engine_coredump *ee;
1419         struct i915_request *rq;
1420         unsigned long flags;
1421
1422         ee = intel_engine_coredump_alloc(engine, GFP_KERNEL);
1423         if (!ee)
1424                 return NULL;
1425
1426         spin_lock_irqsave(&engine->active.lock, flags);
1427         rq = intel_engine_find_active_request(engine);
1428         if (rq)
1429                 capture = intel_engine_coredump_add_request(ee, rq,
1430                                                             ATOMIC_MAYFAIL);
1431         spin_unlock_irqrestore(&engine->active.lock, flags);
1432         if (!capture) {
1433                 kfree(ee);
1434                 return NULL;
1435         }
1436
1437         intel_engine_coredump_add_vma(ee, capture, compress);
1438
1439         return ee;
1440 }
1441
1442 static void
1443 gt_record_engines(struct intel_gt_coredump *gt,
1444                   struct i915_vma_compress *compress)
1445 {
1446         struct intel_engine_cs *engine;
1447         enum intel_engine_id id;
1448
1449         for_each_engine(engine, gt->_gt, id) {
1450                 struct intel_engine_coredump *ee;
1451
1452                 /* Refill our page pool before entering atomic section */
1453                 pool_refill(&compress->pool, ALLOW_FAIL);
1454
1455                 ee = capture_engine(engine, compress);
1456                 if (!ee)
1457                         continue;
1458
1459                 gt->simulated |= ee->simulated;
1460                 if (ee->simulated) {
1461                         kfree(ee);
1462                         continue;
1463                 }
1464
1465                 ee->next = gt->engine;
1466                 gt->engine = ee;
1467         }
1468 }
1469
1470 static struct intel_uc_coredump *
1471 gt_record_uc(struct intel_gt_coredump *gt,
1472              struct i915_vma_compress *compress)
1473 {
1474         const struct intel_uc *uc = &gt->_gt->uc;
1475         struct intel_uc_coredump *error_uc;
1476
1477         error_uc = kzalloc(sizeof(*error_uc), ALLOW_FAIL);
1478         if (!error_uc)
1479                 return NULL;
1480
1481         memcpy(&error_uc->guc_fw, &uc->guc.fw, sizeof(uc->guc.fw));
1482         memcpy(&error_uc->huc_fw, &uc->huc.fw, sizeof(uc->huc.fw));
1483
1484         /* Non-default firmware paths will be specified by the modparam.
1485          * As modparams are generally accesible from the userspace make
1486          * explicit copies of the firmware paths.
1487          */
1488         error_uc->guc_fw.path = kstrdup(uc->guc.fw.path, ALLOW_FAIL);
1489         error_uc->huc_fw.path = kstrdup(uc->huc.fw.path, ALLOW_FAIL);
1490         error_uc->guc_log =
1491                 i915_vma_coredump_create(gt->_gt,
1492                                          uc->guc.log.vma, "GuC log buffer",
1493                                          compress);
1494
1495         return error_uc;
1496 }
1497
1498 static void gt_capture_prepare(struct intel_gt_coredump *gt)
1499 {
1500         struct i915_ggtt *ggtt = gt->_gt->ggtt;
1501
1502         mutex_lock(&ggtt->error_mutex);
1503 }
1504
1505 static void gt_capture_finish(struct intel_gt_coredump *gt)
1506 {
1507         struct i915_ggtt *ggtt = gt->_gt->ggtt;
1508
1509         if (drm_mm_node_allocated(&ggtt->error_capture))
1510                 ggtt->vm.clear_range(&ggtt->vm,
1511                                      ggtt->error_capture.start,
1512                                      PAGE_SIZE);
1513
1514         mutex_unlock(&ggtt->error_mutex);
1515 }
1516
1517 /* Capture all registers which don't fit into another category. */
1518 static void gt_record_regs(struct intel_gt_coredump *gt)
1519 {
1520         struct intel_uncore *uncore = gt->_gt->uncore;
1521         struct drm_i915_private *i915 = uncore->i915;
1522         int i;
1523
1524         /*
1525          * General organization
1526          * 1. Registers specific to a single generation
1527          * 2. Registers which belong to multiple generations
1528          * 3. Feature specific registers.
1529          * 4. Everything else
1530          * Please try to follow the order.
1531          */
1532
1533         /* 1: Registers specific to a single generation */
1534         if (IS_VALLEYVIEW(i915)) {
1535                 gt->gtier[0] = intel_uncore_read(uncore, GTIER);
1536                 gt->ier = intel_uncore_read(uncore, VLV_IER);
1537                 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_VLV);
1538         }
1539
1540         if (IS_GEN(i915, 7))
1541                 gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT);
1542
1543         if (INTEL_GEN(i915) >= 12) {
1544                 gt->fault_data0 = intel_uncore_read(uncore,
1545                                                     GEN12_FAULT_TLB_DATA0);
1546                 gt->fault_data1 = intel_uncore_read(uncore,
1547                                                     GEN12_FAULT_TLB_DATA1);
1548         } else if (INTEL_GEN(i915) >= 8) {
1549                 gt->fault_data0 = intel_uncore_read(uncore,
1550                                                     GEN8_FAULT_TLB_DATA0);
1551                 gt->fault_data1 = intel_uncore_read(uncore,
1552                                                     GEN8_FAULT_TLB_DATA1);
1553         }
1554
1555         if (IS_GEN(i915, 6)) {
1556                 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE);
1557                 gt->gab_ctl = intel_uncore_read(uncore, GAB_CTL);
1558                 gt->gfx_mode = intel_uncore_read(uncore, GFX_MODE);
1559         }
1560
1561         /* 2: Registers which belong to multiple generations */
1562         if (INTEL_GEN(i915) >= 7)
1563                 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_MT);
1564
1565         if (INTEL_GEN(i915) >= 6) {
1566                 gt->derrmr = intel_uncore_read(uncore, DERRMR);
1567                 if (INTEL_GEN(i915) < 12) {
1568                         gt->error = intel_uncore_read(uncore, ERROR_GEN6);
1569                         gt->done_reg = intel_uncore_read(uncore, DONE_REG);
1570                 }
1571         }
1572
1573         /* 3: Feature specific registers */
1574         if (IS_GEN_RANGE(i915, 6, 7)) {
1575                 gt->gam_ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
1576                 gt->gac_eco = intel_uncore_read(uncore, GAC_ECO_BITS);
1577         }
1578
1579         if (IS_GEN_RANGE(i915, 8, 11))
1580                 gt->gtt_cache = intel_uncore_read(uncore, HSW_GTT_CACHE_EN);
1581
1582         if (IS_GEN(i915, 12))
1583                 gt->aux_err = intel_uncore_read(uncore, GEN12_AUX_ERR_DBG);
1584
1585         if (INTEL_GEN(i915) >= 12) {
1586                 for (i = 0; i < GEN12_SFC_DONE_MAX; i++) {
1587                         gt->sfc_done[i] =
1588                                 intel_uncore_read(uncore, GEN12_SFC_DONE(i));
1589                 }
1590
1591                 gt->gam_done = intel_uncore_read(uncore, GEN12_GAM_DONE);
1592         }
1593
1594         /* 4: Everything else */
1595         if (INTEL_GEN(i915) >= 11) {
1596                 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER);
1597                 gt->gtier[0] =
1598                         intel_uncore_read(uncore,
1599                                           GEN11_RENDER_COPY_INTR_ENABLE);
1600                 gt->gtier[1] =
1601                         intel_uncore_read(uncore, GEN11_VCS_VECS_INTR_ENABLE);
1602                 gt->gtier[2] =
1603                         intel_uncore_read(uncore, GEN11_GUC_SG_INTR_ENABLE);
1604                 gt->gtier[3] =
1605                         intel_uncore_read(uncore,
1606                                           GEN11_GPM_WGBOXPERF_INTR_ENABLE);
1607                 gt->gtier[4] =
1608                         intel_uncore_read(uncore,
1609                                           GEN11_CRYPTO_RSVD_INTR_ENABLE);
1610                 gt->gtier[5] =
1611                         intel_uncore_read(uncore,
1612                                           GEN11_GUNIT_CSME_INTR_ENABLE);
1613                 gt->ngtier = 6;
1614         } else if (INTEL_GEN(i915) >= 8) {
1615                 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER);
1616                 for (i = 0; i < 4; i++)
1617                         gt->gtier[i] =
1618                                 intel_uncore_read(uncore, GEN8_GT_IER(i));
1619                 gt->ngtier = 4;
1620         } else if (HAS_PCH_SPLIT(i915)) {
1621                 gt->ier = intel_uncore_read(uncore, DEIER);
1622                 gt->gtier[0] = intel_uncore_read(uncore, GTIER);
1623                 gt->ngtier = 1;
1624         } else if (IS_GEN(i915, 2)) {
1625                 gt->ier = intel_uncore_read16(uncore, GEN2_IER);
1626         } else if (!IS_VALLEYVIEW(i915)) {
1627                 gt->ier = intel_uncore_read(uncore, GEN2_IER);
1628         }
1629         gt->eir = intel_uncore_read(uncore, EIR);
1630         gt->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER);
1631 }
1632
1633 /*
1634  * Generate a semi-unique error code. The code is not meant to have meaning, The
1635  * code's only purpose is to try to prevent false duplicated bug reports by
1636  * grossly estimating a GPU error state.
1637  *
1638  * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
1639  * the hang if we could strip the GTT offset information from it.
1640  *
1641  * It's only a small step better than a random number in its current form.
1642  */
1643 static u32 generate_ecode(const struct intel_engine_coredump *ee)
1644 {
1645         /*
1646          * IPEHR would be an ideal way to detect errors, as it's the gross
1647          * measure of "the command that hung." However, has some very common
1648          * synchronization commands which almost always appear in the case
1649          * strictly a client bug. Use instdone to differentiate those some.
1650          */
1651         return ee ? ee->ipehr ^ ee->instdone.instdone : 0;
1652 }
1653
1654 static const char *error_msg(struct i915_gpu_coredump *error)
1655 {
1656         struct intel_engine_coredump *first = NULL;
1657         struct intel_gt_coredump *gt;
1658         intel_engine_mask_t engines;
1659         int len;
1660
1661         engines = 0;
1662         for (gt = error->gt; gt; gt = gt->next) {
1663                 struct intel_engine_coredump *cs;
1664
1665                 if (gt->engine && !first)
1666                         first = gt->engine;
1667
1668                 for (cs = gt->engine; cs; cs = cs->next)
1669                         engines |= cs->engine->mask;
1670         }
1671
1672         len = scnprintf(error->error_msg, sizeof(error->error_msg),
1673                         "GPU HANG: ecode %d:%x:%08x",
1674                         INTEL_GEN(error->i915), engines,
1675                         generate_ecode(first));
1676         if (first && first->context.pid) {
1677                 /* Just show the first executing process, more is confusing */
1678                 len += scnprintf(error->error_msg + len,
1679                                  sizeof(error->error_msg) - len,
1680                                  ", in %s [%d]",
1681                                  first->context.comm, first->context.pid);
1682         }
1683
1684         return error->error_msg;
1685 }
1686
1687 static void capture_gen(struct i915_gpu_coredump *error)
1688 {
1689         struct drm_i915_private *i915 = error->i915;
1690
1691         error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count);
1692         error->suspended = i915->runtime_pm.suspended;
1693
1694         error->iommu = -1;
1695 #ifdef CONFIG_INTEL_IOMMU
1696         error->iommu = intel_iommu_gfx_mapped;
1697 #endif
1698         error->reset_count = i915_reset_count(&i915->gpu_error);
1699         error->suspend_count = i915->suspend_count;
1700
1701         i915_params_copy(&error->params, &i915_modparams);
1702         memcpy(&error->device_info,
1703                INTEL_INFO(i915),
1704                sizeof(error->device_info));
1705         memcpy(&error->runtime_info,
1706                RUNTIME_INFO(i915),
1707                sizeof(error->runtime_info));
1708         error->driver_caps = i915->caps;
1709 }
1710
1711 struct i915_gpu_coredump *
1712 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp)
1713 {
1714         struct i915_gpu_coredump *error;
1715
1716         if (!i915_modparams.error_capture)
1717                 return NULL;
1718
1719         error = kzalloc(sizeof(*error), gfp);
1720         if (!error)
1721                 return NULL;
1722
1723         kref_init(&error->ref);
1724         error->i915 = i915;
1725
1726         error->time = ktime_get_real();
1727         error->boottime = ktime_get_boottime();
1728         error->uptime = ktime_sub(ktime_get(), i915->gt.last_init_time);
1729         error->capture = jiffies;
1730
1731         capture_gen(error);
1732
1733         return error;
1734 }
1735
1736 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x))
1737
1738 struct intel_gt_coredump *
1739 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp)
1740 {
1741         struct intel_gt_coredump *gc;
1742
1743         gc = kzalloc(sizeof(*gc), gfp);
1744         if (!gc)
1745                 return NULL;
1746
1747         gc->_gt = gt;
1748         gc->awake = intel_gt_pm_is_awake(gt);
1749
1750         gt_record_regs(gc);
1751         gt_record_fences(gc);
1752
1753         return gc;
1754 }
1755
1756 struct i915_vma_compress *
1757 i915_vma_capture_prepare(struct intel_gt_coredump *gt)
1758 {
1759         struct i915_vma_compress *compress;
1760
1761         compress = kmalloc(sizeof(*compress), ALLOW_FAIL);
1762         if (!compress)
1763                 return NULL;
1764
1765         if (!compress_init(compress)) {
1766                 kfree(compress);
1767                 return NULL;
1768         }
1769
1770         gt_capture_prepare(gt);
1771
1772         return compress;
1773 }
1774
1775 void i915_vma_capture_finish(struct intel_gt_coredump *gt,
1776                              struct i915_vma_compress *compress)
1777 {
1778         if (!compress)
1779                 return;
1780
1781         gt_capture_finish(gt);
1782
1783         compress_fini(compress);
1784         kfree(compress);
1785 }
1786
1787 struct i915_gpu_coredump *i915_gpu_coredump(struct drm_i915_private *i915)
1788 {
1789         struct i915_gpu_coredump *error;
1790
1791         /* Check if GPU capture has been disabled */
1792         error = READ_ONCE(i915->gpu_error.first_error);
1793         if (IS_ERR(error))
1794                 return error;
1795
1796         error = i915_gpu_coredump_alloc(i915, ALLOW_FAIL);
1797         if (!error)
1798                 return ERR_PTR(-ENOMEM);
1799
1800         error->gt = intel_gt_coredump_alloc(&i915->gt, ALLOW_FAIL);
1801         if (error->gt) {
1802                 struct i915_vma_compress *compress;
1803
1804                 compress = i915_vma_capture_prepare(error->gt);
1805                 if (!compress) {
1806                         kfree(error->gt);
1807                         kfree(error);
1808                         return ERR_PTR(-ENOMEM);
1809                 }
1810
1811                 gt_record_engines(error->gt, compress);
1812
1813                 if (INTEL_INFO(i915)->has_gt_uc)
1814                         error->gt->uc = gt_record_uc(error->gt, compress);
1815
1816                 i915_vma_capture_finish(error->gt, compress);
1817
1818                 error->simulated |= error->gt->simulated;
1819         }
1820
1821         error->overlay = intel_overlay_capture_error_state(i915);
1822         error->display = intel_display_capture_error_state(i915);
1823
1824         return error;
1825 }
1826
1827 void i915_error_state_store(struct i915_gpu_coredump *error)
1828 {
1829         struct drm_i915_private *i915;
1830         static bool warned;
1831
1832         if (IS_ERR_OR_NULL(error))
1833                 return;
1834
1835         i915 = error->i915;
1836         drm_info(&i915->drm, "%s\n", error_msg(error));
1837
1838         if (error->simulated ||
1839             cmpxchg(&i915->gpu_error.first_error, NULL, error))
1840                 return;
1841
1842         i915_gpu_coredump_get(error);
1843
1844         if (!xchg(&warned, true) &&
1845             ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) {
1846                 pr_info("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1847                 pr_info("Please file a _new_ bug report at https://gitlab.freedesktop.org/drm/intel/issues/new.\n");
1848                 pr_info("Please see https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs for details.\n");
1849                 pr_info("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1850                 pr_info("The GPU crash dump is required to analyze GPU hangs, so please always attach it.\n");
1851                 pr_info("GPU crash dump saved to /sys/class/drm/card%d/error\n",
1852                         i915->drm.primary->index);
1853         }
1854 }
1855
1856 /**
1857  * i915_capture_error_state - capture an error record for later analysis
1858  * @i915: i915 device
1859  *
1860  * Should be called when an error is detected (either a hang or an error
1861  * interrupt) to capture error state from the time of the error.  Fills
1862  * out a structure which becomes available in debugfs for user level tools
1863  * to pick up.
1864  */
1865 void i915_capture_error_state(struct drm_i915_private *i915)
1866 {
1867         struct i915_gpu_coredump *error;
1868
1869         error = i915_gpu_coredump(i915);
1870         if (IS_ERR(error)) {
1871                 cmpxchg(&i915->gpu_error.first_error, NULL, error);
1872                 return;
1873         }
1874
1875         i915_error_state_store(error);
1876         i915_gpu_coredump_put(error);
1877 }
1878
1879 struct i915_gpu_coredump *
1880 i915_first_error_state(struct drm_i915_private *i915)
1881 {
1882         struct i915_gpu_coredump *error;
1883
1884         spin_lock_irq(&i915->gpu_error.lock);
1885         error = i915->gpu_error.first_error;
1886         if (!IS_ERR_OR_NULL(error))
1887                 i915_gpu_coredump_get(error);
1888         spin_unlock_irq(&i915->gpu_error.lock);
1889
1890         return error;
1891 }
1892
1893 void i915_reset_error_state(struct drm_i915_private *i915)
1894 {
1895         struct i915_gpu_coredump *error;
1896
1897         spin_lock_irq(&i915->gpu_error.lock);
1898         error = i915->gpu_error.first_error;
1899         if (error != ERR_PTR(-ENODEV)) /* if disabled, always disabled */
1900                 i915->gpu_error.first_error = NULL;
1901         spin_unlock_irq(&i915->gpu_error.lock);
1902
1903         if (!IS_ERR_OR_NULL(error))
1904                 i915_gpu_coredump_put(error);
1905 }
1906
1907 void i915_disable_error_state(struct drm_i915_private *i915, int err)
1908 {
1909         spin_lock_irq(&i915->gpu_error.lock);
1910         if (!i915->gpu_error.first_error)
1911                 i915->gpu_error.first_error = ERR_PTR(err);
1912         spin_unlock_irq(&i915->gpu_error.lock);
1913 }