drivers/gpu/drm/bridge/tc358767.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * tc358767 eDP bridge driver
   4  *
   5  * Copyright (C) 2016 CogentEmbedded Inc
   6  * Author: Andrey Gusakov <[email protected]>
   7  *
   8  * Copyright (C) 2016 Pengutronix, Philipp Zabel <[email protected]>
   9  *
  10  * Copyright (C) 2016 Zodiac Inflight Innovations
  11  *
  12  * Initially based on: drivers/gpu/drm/i2c/tda998x_drv.c
  13  *
  14  * Copyright (C) 2012 Texas Instruments
  15  * Author: Rob Clark <[email protected]>
  16  */
  17
  18 #include <linux/bitfield.h>
  19 #include <linux/clk.h>
  20 #include <linux/device.h>
  21 #include <linux/gpio/consumer.h>
  22 #include <linux/i2c.h>
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/regmap.h>
  26 #include <linux/slab.h>
  27
  28 #include <drm/drm_atomic_helper.h>
  29 #include <drm/drm_bridge.h>
  30 #include <drm/drm_dp_helper.h>
  31 #include <drm/drm_edid.h>
  32 #include <drm/drm_of.h>
  33 #include <drm/drm_panel.h>
  34 #include <drm/drm_print.h>
  35 #include <drm/drm_probe_helper.h>
  36
  37 /* Registers */
  38
  39 /* Display Parallel Interface */
  40 #define DPIPXLFMT               0x0440
  41 #define VS_POL_ACTIVE_LOW               (1 << 10)
  42 #define HS_POL_ACTIVE_LOW               (1 << 9)
  43 #define DE_POL_ACTIVE_HIGH              (0 << 8)
  44 #define SUB_CFG_TYPE_CONFIG1            (0 << 2) /* LSB aligned */
  45 #define SUB_CFG_TYPE_CONFIG2            (1 << 2) /* Loosely Packed */
  46 #define SUB_CFG_TYPE_CONFIG3            (2 << 2) /* LSB aligned 8-bit */
  47 #define DPI_BPP_RGB888                  (0 << 0)
  48 #define DPI_BPP_RGB666                  (1 << 0)
  49 #define DPI_BPP_RGB565                  (2 << 0)
  50
  51 /* Video Path */
  52 #define VPCTRL0                 0x0450
  53 #define VSDELAY                 GENMASK(31, 20)
  54 #define OPXLFMT_RGB666                  (0 << 8)
  55 #define OPXLFMT_RGB888                  (1 << 8)
  56 #define FRMSYNC_DISABLED                (0 << 4) /* Video Timing Gen Disabled */
  57 #define FRMSYNC_ENABLED                 (1 << 4) /* Video Timing Gen Enabled */
  58 #define MSF_DISABLED                    (0 << 0) /* Magic Square FRC disabled */
  59 #define MSF_ENABLED                     (1 << 0) /* Magic Square FRC enabled */
  60 #define HTIM01                  0x0454
  61 #define HPW                     GENMASK(8, 0)
  62 #define HBPR                    GENMASK(24, 16)
  63 #define HTIM02                  0x0458
  64 #define HDISPR                  GENMASK(10, 0)
  65 #define HFPR                    GENMASK(24, 16)
  66 #define VTIM01                  0x045c
  67 #define VSPR                    GENMASK(7, 0)
  68 #define VBPR                    GENMASK(23, 16)
  69 #define VTIM02                  0x0460
  70 #define VFPR                    GENMASK(23, 16)
  71 #define VDISPR                  GENMASK(10, 0)
  72 #define VFUEN0                  0x0464
  73 #define VFUEN                           BIT(0)   /* Video Frame Timing Upload */
  74
  75 /* System */
  76 #define TC_IDREG                0x0500
  77 #define SYSSTAT                 0x0508
  78 #define SYSCTRL                 0x0510
  79 #define DP0_AUDSRC_NO_INPUT             (0 << 3)
  80 #define DP0_AUDSRC_I2S_RX               (1 << 3)
  81 #define DP0_VIDSRC_NO_INPUT             (0 << 0)
  82 #define DP0_VIDSRC_DSI_RX               (1 << 0)
  83 #define DP0_VIDSRC_DPI_RX               (2 << 0)
  84 #define DP0_VIDSRC_COLOR_BAR            (3 << 0)
  85 #define SYSRSTENB               0x050c
  86 #define ENBI2C                          (1 << 0)
  87 #define ENBLCD0                         (1 << 2)
  88 #define ENBBM                           (1 << 3)
  89 #define ENBDSIRX                        (1 << 4)
  90 #define ENBREG                          (1 << 5)
  91 #define ENBHDCP                         (1 << 8)
  92 #define GPIOM                   0x0540
  93 #define GPIOC                   0x0544
  94 #define GPIOO                   0x0548
  95 #define GPIOI                   0x054c
  96 #define INTCTL_G                0x0560
  97 #define INTSTS_G                0x0564
  98
  99 #define INT_SYSERR              BIT(16)
 100 #define INT_GPIO_H(x)           (1 << (x == 0 ? 2 : 10))
 101 #define INT_GPIO_LC(x)          (1 << (x == 0 ? 3 : 11))
 102
 103 #define INT_GP0_LCNT            0x0584
 104 #define INT_GP1_LCNT            0x0588
 105
 106 /* Control */
 107 #define DP0CTL                  0x0600
 108 #define VID_MN_GEN                      BIT(6)   /* Auto-generate M/N values */
 109 #define EF_EN                           BIT(5)   /* Enable Enhanced Framing */
 110 #define VID_EN                          BIT(1)   /* Video transmission enable */
 111 #define DP_EN                           BIT(0)   /* Enable DPTX function */
 112
 113 /* Clocks */
 114 #define DP0_VIDMNGEN0           0x0610
 115 #define DP0_VIDMNGEN1           0x0614
 116 #define DP0_VMNGENSTATUS        0x0618
 117
 118 /* Main Channel */
 119 #define DP0_SECSAMPLE           0x0640
 120 #define DP0_VIDSYNCDELAY        0x0644
 121 #define VID_SYNC_DLY            GENMASK(15, 0)
 122 #define THRESH_DLY              GENMASK(31, 16)
 123
 124 #define DP0_TOTALVAL            0x0648
 125 #define H_TOTAL                 GENMASK(15, 0)
 126 #define V_TOTAL                 GENMASK(31, 16)
 127 #define DP0_STARTVAL            0x064c
 128 #define H_START                 GENMASK(15, 0)
 129 #define V_START                 GENMASK(31, 16)
 130 #define DP0_ACTIVEVAL           0x0650
 131 #define H_ACT                   GENMASK(15, 0)
 132 #define V_ACT                   GENMASK(31, 16)
 133
 134 #define DP0_SYNCVAL             0x0654
 135 #define VS_WIDTH                GENMASK(30, 16)
 136 #define HS_WIDTH                GENMASK(14, 0)
 137 #define SYNCVAL_HS_POL_ACTIVE_LOW       (1 << 15)
 138 #define SYNCVAL_VS_POL_ACTIVE_LOW       (1 << 31)
 139 #define DP0_MISC                0x0658
 140 #define TU_SIZE_RECOMMENDED             (63) /* LSCLK cycles per TU */
 141 #define MAX_TU_SYMBOL           GENMASK(28, 23)
 142 #define TU_SIZE                 GENMASK(21, 16)
 143 #define BPC_6                           (0 << 5)
 144 #define BPC_8                           (1 << 5)
 145
 146 /* AUX channel */
 147 #define DP0_AUXCFG0             0x0660
 148 #define DP0_AUXCFG0_BSIZE       GENMASK(11, 8)
 149 #define DP0_AUXCFG0_ADDR_ONLY   BIT(4)
 150 #define DP0_AUXCFG1             0x0664
 151 #define AUX_RX_FILTER_EN                BIT(16)
 152
 153 #define DP0_AUXADDR             0x0668
 154 #define DP0_AUXWDATA(i)         (0x066c + (i) * 4)
 155 #define DP0_AUXRDATA(i)         (0x067c + (i) * 4)
 156 #define DP0_AUXSTATUS           0x068c
 157 #define AUX_BYTES               GENMASK(15, 8)
 158 #define AUX_STATUS              GENMASK(7, 4)
 159 #define AUX_TIMEOUT             BIT(1)
 160 #define AUX_BUSY                BIT(0)
 161 #define DP0_AUXI2CADR           0x0698
 162
 163 /* Link Training */
 164 #define DP0_SRCCTRL             0x06a0
 165 #define DP0_SRCCTRL_SCRMBLDIS           BIT(13)
 166 #define DP0_SRCCTRL_EN810B              BIT(12)
 167 #define DP0_SRCCTRL_NOTP                (0 << 8)
 168 #define DP0_SRCCTRL_TP1                 (1 << 8)
 169 #define DP0_SRCCTRL_TP2                 (2 << 8)
 170 #define DP0_SRCCTRL_LANESKEW            BIT(7)
 171 #define DP0_SRCCTRL_SSCG                BIT(3)
 172 #define DP0_SRCCTRL_LANES_1             (0 << 2)
 173 #define DP0_SRCCTRL_LANES_2             (1 << 2)
 174 #define DP0_SRCCTRL_BW27                (1 << 1)
 175 #define DP0_SRCCTRL_BW162               (0 << 1)
 176 #define DP0_SRCCTRL_AUTOCORRECT         BIT(0)
 177 #define DP0_LTSTAT              0x06d0
 178 #define LT_LOOPDONE                     BIT(13)
 179 #define LT_STATUS_MASK                  (0x1f << 8)
 180 #define LT_CHANNEL1_EQ_BITS             (DP_CHANNEL_EQ_BITS << 4)
 181 #define LT_INTERLANE_ALIGN_DONE         BIT(3)
 182 #define LT_CHANNEL0_EQ_BITS             (DP_CHANNEL_EQ_BITS)
 183 #define DP0_SNKLTCHGREQ         0x06d4
 184 #define DP0_LTLOOPCTRL          0x06d8
 185 #define DP0_SNKLTCTRL           0x06e4
 186
 187 #define DP1_SRCCTRL             0x07a0
 188
 189 /* PHY */
 190 #define DP_PHY_CTRL             0x0800
 191 #define DP_PHY_RST                      BIT(28)  /* DP PHY Global Soft Reset */
 192 #define BGREN                           BIT(25)  /* AUX PHY BGR Enable */
 193 #define PWR_SW_EN                       BIT(24)  /* PHY Power Switch Enable */
 194 #define PHY_M1_RST                      BIT(12)  /* Reset PHY1 Main Channel */
 195 #define PHY_RDY                         BIT(16)  /* PHY Main Channels Ready */
 196 #define PHY_M0_RST                      BIT(8)   /* Reset PHY0 Main Channel */
 197 #define PHY_2LANE                       BIT(2)   /* PHY Enable 2 lanes */
 198 #define PHY_A0_EN                       BIT(1)   /* PHY Aux Channel0 Enable */
 199 #define PHY_M0_EN                       BIT(0)   /* PHY Main Channel0 Enable */
 200
 201 /* PLL */
 202 #define DP0_PLLCTRL             0x0900
 203 #define DP1_PLLCTRL             0x0904  /* not defined in DS */
 204 #define PXL_PLLCTRL             0x0908
 205 #define PLLUPDATE                       BIT(2)
 206 #define PLLBYP                          BIT(1)
 207 #define PLLEN                           BIT(0)
 208 #define PXL_PLLPARAM            0x0914
 209 #define IN_SEL_REFCLK                   (0 << 14)
 210 #define SYS_PLLPARAM            0x0918
 211 #define REF_FREQ_38M4                   (0 << 8) /* 38.4 MHz */
 212 #define REF_FREQ_19M2                   (1 << 8) /* 19.2 MHz */
 213 #define REF_FREQ_26M                    (2 << 8) /* 26 MHz */
 214 #define REF_FREQ_13M                    (3 << 8) /* 13 MHz */
 215 #define SYSCLK_SEL_LSCLK                (0 << 4)
 216 #define LSCLK_DIV_1                     (0 << 0)
 217 #define LSCLK_DIV_2                     (1 << 0)
 218
 219 /* Test & Debug */
 220 #define TSTCTL                  0x0a00
 221 #define COLOR_R                 GENMASK(31, 24)
 222 #define COLOR_G                 GENMASK(23, 16)
 223 #define COLOR_B                 GENMASK(15, 8)
 224 #define ENI2CFILTER             BIT(4)
 225 #define COLOR_BAR_MODE          GENMASK(1, 0)
 226 #define COLOR_BAR_MODE_BARS     2
 227 #define PLL_DBG                 0x0a04
 228
 229 static bool tc_test_pattern;
 230 module_param_named(test, tc_test_pattern, bool, 0644);
 231
 232 struct tc_edp_link {
 233         u8                      dpcd[DP_RECEIVER_CAP_SIZE];
 234         unsigned int            rate;
 235         u8                      num_lanes;
 236         u8                      assr;
 237         bool                    scrambler_dis;
 238         bool                    spread;
 239 };
 240
 241 struct tc_data {
 242         struct device           *dev;
 243         struct regmap           *regmap;
 244         struct drm_dp_aux       aux;
 245
 246         struct drm_bridge       bridge;
 247         struct drm_connector    connector;
 248         struct drm_panel        *panel;
 249
 250         /* link settings */
 251         struct tc_edp_link      link;
 252
 253         /* display edid */
 254         struct edid             *edid;
 255         /* current mode */
 256         struct drm_display_mode mode;
 257
 258         u32                     rev;
 259         u8                      assr;
 260
 261         struct gpio_desc        *sd_gpio;
 262         struct gpio_desc        *reset_gpio;
 263         struct clk              *refclk;
 264
 265         /* do we have IRQ */
 266         bool                    have_irq;
 267
 268         /* HPD pin number (0 or 1) or -ENODEV */
 269         int                     hpd_pin;
 270 };
 271
 272 static inline struct tc_data *aux_to_tc(struct drm_dp_aux *a)
 273 {
 274         return container_of(a, struct tc_data, aux);
 275 }
 276
 277 static inline struct tc_data *bridge_to_tc(struct drm_bridge *b)
 278 {
 279         return container_of(b, struct tc_data, bridge);
 280 }
 281
 282 static inline struct tc_data *connector_to_tc(struct drm_connector *c)
 283 {
 284         return container_of(c, struct tc_data, connector);
 285 }
 286
 287 static inline int tc_poll_timeout(struct tc_data *tc, unsigned int addr,
 288                                   unsigned int cond_mask,
 289                                   unsigned int cond_value,
 290                                   unsigned long sleep_us, u64 timeout_us)
 291 {
 292         unsigned int val;
 293
 294         return regmap_read_poll_timeout(tc->regmap, addr, val,
 295                                         (val & cond_mask) == cond_value,
 296                                         sleep_us, timeout_us);
 297 }
 298
 299 static int tc_aux_wait_busy(struct tc_data *tc)
 300 {
 301         return tc_poll_timeout(tc, DP0_AUXSTATUS, AUX_BUSY, 0, 100, 100000);
 302 }
 303
 304 static int tc_aux_write_data(struct tc_data *tc, const void *data,
 305                              size_t size)
 306 {
 307         u32 auxwdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)] = { 0 };
 308         int ret, count = ALIGN(size, sizeof(u32));
 309
 310         memcpy(auxwdata, data, size);
 311
 312         ret = regmap_raw_write(tc->regmap, DP0_AUXWDATA(0), auxwdata, count);
 313         if (ret)
 314                 return ret;
 315
 316         return size;
 317 }
 318
 319 static int tc_aux_read_data(struct tc_data *tc, void *data, size_t size)
 320 {
 321         u32 auxrdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)];
 322         int ret, count = ALIGN(size, sizeof(u32));
 323
 324         ret = regmap_raw_read(tc->regmap, DP0_AUXRDATA(0), auxrdata, count);
 325         if (ret)
 326                 return ret;
 327
 328         memcpy(data, auxrdata, size);
 329
 330         return size;
 331 }
 332
 333 static u32 tc_auxcfg0(struct drm_dp_aux_msg *msg, size_t size)
 334 {
 335         u32 auxcfg0 = msg->request;
 336
 337         if (size)
 338                 auxcfg0 |= FIELD_PREP(DP0_AUXCFG0_BSIZE, size - 1);
 339         else
 340                 auxcfg0 |= DP0_AUXCFG0_ADDR_ONLY;
 341
 342         return auxcfg0;
 343 }
 344
 345 static ssize_t tc_aux_transfer(struct drm_dp_aux *aux,
 346                                struct drm_dp_aux_msg *msg)
 347 {
 348         struct tc_data *tc = aux_to_tc(aux);
 349         size_t size = min_t(size_t, DP_AUX_MAX_PAYLOAD_BYTES - 1, msg->size);
 350         u8 request = msg->request & ~DP_AUX_I2C_MOT;
 351         u32 auxstatus;
 352         int ret;
 353
 354         ret = tc_aux_wait_busy(tc);
 355         if (ret)
 356                 return ret;
 357
 358         switch (request) {
 359         case DP_AUX_NATIVE_READ:
 360         case DP_AUX_I2C_READ:
 361                 break;
 362         case DP_AUX_NATIVE_WRITE:
 363         case DP_AUX_I2C_WRITE:
 364                 if (size) {
 365                         ret = tc_aux_write_data(tc, msg->buffer, size);
 366                         if (ret < 0)
 367                                 return ret;
 368                 }
 369                 break;
 370         default:
 371                 return -EINVAL;
 372         }
 373
 374         /* Store address */
 375         ret = regmap_write(tc->regmap, DP0_AUXADDR, msg->address);
 376         if (ret)
 377                 return ret;
 378         /* Start transfer */
 379         ret = regmap_write(tc->regmap, DP0_AUXCFG0, tc_auxcfg0(msg, size));
 380         if (ret)
 381                 return ret;
 382
 383         ret = tc_aux_wait_busy(tc);
 384         if (ret)
 385                 return ret;
 386
 387         ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &auxstatus);
 388         if (ret)
 389                 return ret;
 390
 391         if (auxstatus & AUX_TIMEOUT)
 392                 return -ETIMEDOUT;
 393         /*
 394          * For some reason address-only DP_AUX_I2C_WRITE (MOT), still
 395          * reports 1 byte transferred in its status. To deal we that
 396          * we ignore aux_bytes field if we know that this was an
 397          * address-only transfer
 398          */
 399         if (size)
 400                 size = FIELD_GET(AUX_BYTES, auxstatus);
 401         msg->reply = FIELD_GET(AUX_STATUS, auxstatus);
 402
 403         switch (request) {
 404         case DP_AUX_NATIVE_READ:
 405         case DP_AUX_I2C_READ:
 406                 if (size)
 407                         return tc_aux_read_data(tc, msg->buffer, size);
 408                 break;
 409         }
 410
 411         return size;
 412 }
 413
 414 static const char * const training_pattern1_errors[] = {
 415         "No errors",
 416         "Aux write error",
 417         "Aux read error",
 418         "Max voltage reached error",
 419         "Loop counter expired error",
 420         "res", "res", "res"
 421 };
 422
 423 static const char * const training_pattern2_errors[] = {
 424         "No errors",
 425         "Aux write error",
 426         "Aux read error",
 427         "Clock recovery failed error",
 428         "Loop counter expired error",
 429         "res", "res", "res"
 430 };
 431
 432 static u32 tc_srcctrl(struct tc_data *tc)
 433 {
 434         /*
 435          * No training pattern, skew lane 1 data by two LSCLK cycles with
 436          * respect to lane 0 data, AutoCorrect Mode = 0
 437          */
 438         u32 reg = DP0_SRCCTRL_NOTP | DP0_SRCCTRL_LANESKEW | DP0_SRCCTRL_EN810B;
 439
 440         if (tc->link.scrambler_dis)
 441                 reg |= DP0_SRCCTRL_SCRMBLDIS;   /* Scrambler Disabled */
 442         if (tc->link.spread)
 443                 reg |= DP0_SRCCTRL_SSCG;        /* Spread Spectrum Enable */
 444         if (tc->link.num_lanes == 2)
 445                 reg |= DP0_SRCCTRL_LANES_2;     /* Two Main Channel Lanes */
 446         if (tc->link.rate != 162000)
 447                 reg |= DP0_SRCCTRL_BW27;        /* 2.7 Gbps link */
 448         return reg;
 449 }
 450
 451 static int tc_pllupdate(struct tc_data *tc, unsigned int pllctrl)
 452 {
 453         int ret;
 454
 455         ret = regmap_write(tc->regmap, pllctrl, PLLUPDATE | PLLEN);
 456         if (ret)
 457                 return ret;
 458
 459         /* Wait for PLL to lock: up to 2.09 ms, depending on refclk */
 460         usleep_range(3000, 6000);
 461
 462         return 0;
 463 }
 464
 465 static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
 466 {
 467         int ret;
 468         int i_pre, best_pre = 1;
 469         int i_post, best_post = 1;
 470         int div, best_div = 1;
 471         int mul, best_mul = 1;
 472         int delta, best_delta;
 473         int ext_div[] = {1, 2, 3, 5, 7};
 474         int best_pixelclock = 0;
 475         int vco_hi = 0;
 476         u32 pxl_pllparam;
 477
 478         dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock,
 479                 refclk);
 480         best_delta = pixelclock;
 481         /* Loop over all possible ext_divs, skipping invalid configurations */
 482         for (i_pre = 0; i_pre < ARRAY_SIZE(ext_div); i_pre++) {
 483                 /*
 484                  * refclk / ext_pre_div should be in the 1 to 200 MHz range.
 485                  * We don't allow any refclk > 200 MHz, only check lower bounds.
 486                  */
 487                 if (refclk / ext_div[i_pre] < 1000000)
 488                         continue;
 489                 for (i_post = 0; i_post < ARRAY_SIZE(ext_div); i_post++) {
 490                         for (div = 1; div <= 16; div++) {
 491                                 u32 clk;
 492                                 u64 tmp;
 493
 494                                 tmp = pixelclock * ext_div[i_pre] *
 495                                       ext_div[i_post] * div;
 496                                 do_div(tmp, refclk);
 497                                 mul = tmp;
 498
 499                                 /* Check limits */
 500                                 if ((mul < 1) || (mul > 128))
 501                                         continue;
 502
 503                                 clk = (refclk / ext_div[i_pre] / div) * mul;
 504                                 /*
 505                                  * refclk * mul / (ext_pre_div * pre_div)
 506                                  * should be in the 150 to 650 MHz range
 507                                  */
 508                                 if ((clk > 650000000) || (clk < 150000000))
 509                                         continue;
 510
 511                                 clk = clk / ext_div[i_post];
 512                                 delta = clk - pixelclock;
 513
 514                                 if (abs(delta) < abs(best_delta)) {
 515                                         best_pre = i_pre;
 516                                         best_post = i_post;
 517                                         best_div = div;
 518                                         best_mul = mul;
 519                                         best_delta = delta;
 520                                         best_pixelclock = clk;
 521                                 }
 522                         }
 523                 }
 524         }
 525         if (best_pixelclock == 0) {
 526                 dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n",
 527                         pixelclock);
 528                 return -EINVAL;
 529         }
 530
 531         dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock,
 532                 best_delta);
 533         dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk,
 534                 ext_div[best_pre], best_div, best_mul, ext_div[best_post]);
 535
 536         /* if VCO >= 300 MHz */
 537         if (refclk / ext_div[best_pre] / best_div * best_mul >= 300000000)
 538                 vco_hi = 1;
 539         /* see DS */
 540         if (best_div == 16)
 541                 best_div = 0;
 542         if (best_mul == 128)
 543                 best_mul = 0;
 544
 545         /* Power up PLL and switch to bypass */
 546         ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP | PLLEN);
 547         if (ret)
 548                 return ret;
 549
 550         pxl_pllparam  = vco_hi << 24; /* For PLL VCO >= 300 MHz = 1 */
 551         pxl_pllparam |= ext_div[best_pre] << 20; /* External Pre-divider */
 552         pxl_pllparam |= ext_div[best_post] << 16; /* External Post-divider */
 553         pxl_pllparam |= IN_SEL_REFCLK; /* Use RefClk as PLL input */
 554         pxl_pllparam |= best_div << 8; /* Divider for PLL RefClk */
 555         pxl_pllparam |= best_mul; /* Multiplier for PLL */
 556
 557         ret = regmap_write(tc->regmap, PXL_PLLPARAM, pxl_pllparam);
 558         if (ret)
 559                 return ret;
 560
 561         /* Force PLL parameter update and disable bypass */
 562         return tc_pllupdate(tc, PXL_PLLCTRL);
 563 }
 564
 565 static int tc_pxl_pll_dis(struct tc_data *tc)
 566 {
 567         /* Enable PLL bypass, power down PLL */
 568         return regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP);
 569 }
 570
 571 static int tc_stream_clock_calc(struct tc_data *tc)
 572 {
 573         /*
 574          * If the Stream clock and Link Symbol clock are
 575          * asynchronous with each other, the value of M changes over
 576          * time. This way of generating link clock and stream
 577          * clock is called Asynchronous Clock mode. The value M
 578          * must change while the value N stays constant. The
 579          * value of N in this Asynchronous Clock mode must be set
 580          * to 2^15 or 32,768.
 581          *
 582          * LSCLK = 1/10 of high speed link clock
 583          *
 584          * f_STRMCLK = M/N * f_LSCLK
 585          * M/N = f_STRMCLK / f_LSCLK
 586          *
 587          */
 588         return regmap_write(tc->regmap, DP0_VIDMNGEN1, 32768);
 589 }
 590
 591 static int tc_set_syspllparam(struct tc_data *tc)
 592 {
 593         unsigned long rate;
 594         u32 pllparam = SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
 595
 596         rate = clk_get_rate(tc->refclk);
 597         switch (rate) {
 598         case 38400000:
 599                 pllparam |= REF_FREQ_38M4;
 600                 break;
 601         case 26000000:
 602                 pllparam |= REF_FREQ_26M;
 603                 break;
 604         case 19200000:
 605                 pllparam |= REF_FREQ_19M2;
 606                 break;
 607         case 13000000:
 608                 pllparam |= REF_FREQ_13M;
 609                 break;
 610         default:
 611                 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate);
 612                 return -EINVAL;
 613         }
 614
 615         return regmap_write(tc->regmap, SYS_PLLPARAM, pllparam);
 616 }
 617
 618 static int tc_aux_link_setup(struct tc_data *tc)
 619 {
 620         int ret;
 621         u32 dp0_auxcfg1;
 622
 623         /* Setup DP-PHY / PLL */
 624         ret = tc_set_syspllparam(tc);
 625         if (ret)
 626                 goto err;
 627
 628         ret = regmap_write(tc->regmap, DP_PHY_CTRL,
 629                            BGREN | PWR_SW_EN | PHY_A0_EN);
 630         if (ret)
 631                 goto err;
 632         /*
 633          * Initially PLLs are in bypass. Force PLL parameter update,
 634          * disable PLL bypass, enable PLL
 635          */
 636         ret = tc_pllupdate(tc, DP0_PLLCTRL);
 637         if (ret)
 638                 goto err;
 639
 640         ret = tc_pllupdate(tc, DP1_PLLCTRL);
 641         if (ret)
 642                 goto err;
 643
 644         ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 100, 100000);
 645         if (ret == -ETIMEDOUT) {
 646                 dev_err(tc->dev, "Timeout waiting for PHY to become ready");
 647                 return ret;
 648         } else if (ret) {
 649                 goto err;
 650         }
 651
 652         /* Setup AUX link */
 653         dp0_auxcfg1  = AUX_RX_FILTER_EN;
 654         dp0_auxcfg1 |= 0x06 << 8; /* Aux Bit Period Calculator Threshold */
 655         dp0_auxcfg1 |= 0x3f << 0; /* Aux Response Timeout Timer */
 656
 657         ret = regmap_write(tc->regmap, DP0_AUXCFG1, dp0_auxcfg1);
 658         if (ret)
 659                 goto err;
 660
 661         return 0;
 662 err:
 663         dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret);
 664         return ret;
 665 }
 666
 667 static int tc_get_display_props(struct tc_data *tc)
 668 {
 669         u8 revision, num_lanes;
 670         unsigned int rate;
 671         int ret;
 672         u8 reg;
 673
 674         /* Read DP Rx Link Capability */
 675         ret = drm_dp_dpcd_read(&tc->aux, DP_DPCD_REV, tc->link.dpcd,
 676                                DP_RECEIVER_CAP_SIZE);
 677         if (ret < 0)
 678                 goto err_dpcd_read;
 679
 680         revision = tc->link.dpcd[DP_DPCD_REV];
 681         rate = drm_dp_max_link_rate(tc->link.dpcd);
 682         num_lanes = drm_dp_max_lane_count(tc->link.dpcd);
 683
 684         if (rate != 162000 && rate != 270000) {
 685                 dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n");
 686                 rate = 270000;
 687         }
 688
 689         tc->link.rate = rate;
 690
 691         if (num_lanes > 2) {
 692                 dev_dbg(tc->dev, "Falling to 2 lanes\n");
 693                 num_lanes = 2;
 694         }
 695
 696         tc->link.num_lanes = num_lanes;
 697
 698         ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, &reg);
 699         if (ret < 0)
 700                 goto err_dpcd_read;
 701         tc->link.spread = reg & DP_MAX_DOWNSPREAD_0_5;
 702
 703         ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, &reg);
 704         if (ret < 0)
 705                 goto err_dpcd_read;
 706
 707         tc->link.scrambler_dis = false;
 708         /* read assr */
 709         ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, &reg);
 710         if (ret < 0)
 711                 goto err_dpcd_read;
 712         tc->link.assr = reg & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;
 713
 714         dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n",
 715                 revision >> 4, revision & 0x0f,
 716                 (tc->link.rate == 162000) ? "1.62Gbps" : "2.7Gbps",
 717                 tc->link.num_lanes,
 718                 drm_dp_enhanced_frame_cap(tc->link.dpcd) ?
 719                 "enhanced" : "default");
 720         dev_dbg(tc->dev, "Downspread: %s, scrambler: %s\n",
 721                 tc->link.spread ? "0.5%" : "0.0%",
 722                 tc->link.scrambler_dis ? "disabled" : "enabled");
 723         dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n",
 724                 tc->link.assr, tc->assr);
 725
 726         return 0;
 727
 728 err_dpcd_read:
 729         dev_err(tc->dev, "failed to read DPCD: %d\n", ret);
 730         return ret;
 731 }
 732
 733 static int tc_set_video_mode(struct tc_data *tc,
 734                              const struct drm_display_mode *mode)
 735 {
 736         int ret;
 737         int vid_sync_dly;
 738         int max_tu_symbol;
 739
 740         int left_margin = mode->htotal - mode->hsync_end;
 741         int right_margin = mode->hsync_start - mode->hdisplay;
 742         int hsync_len = mode->hsync_end - mode->hsync_start;
 743         int upper_margin = mode->vtotal - mode->vsync_end;
 744         int lower_margin = mode->vsync_start - mode->vdisplay;
 745         int vsync_len = mode->vsync_end - mode->vsync_start;
 746         u32 dp0_syncval;
 747         u32 bits_per_pixel = 24;
 748         u32 in_bw, out_bw;
 749
 750         /*
 751          * Recommended maximum number of symbols transferred in a transfer unit:
 752          * DIV_ROUND_UP((input active video bandwidth in bytes) * tu_size,
 753          *              (output active video bandwidth in bytes))
 754          * Must be less than tu_size.
 755          */
 756
 757         in_bw = mode->clock * bits_per_pixel / 8;
 758         out_bw = tc->link.num_lanes * tc->link.rate;
 759         max_tu_symbol = DIV_ROUND_UP(in_bw * TU_SIZE_RECOMMENDED, out_bw);
 760
 761         dev_dbg(tc->dev, "set mode %dx%d\n",
 762                 mode->hdisplay, mode->vdisplay);
 763         dev_dbg(tc->dev, "H margin %d,%d sync %d\n",
 764                 left_margin, right_margin, hsync_len);
 765         dev_dbg(tc->dev, "V margin %d,%d sync %d\n",
 766                 upper_margin, lower_margin, vsync_len);
 767         dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal);
 768
 769
 770         /*
 771          * LCD Ctl Frame Size
 772          * datasheet is not clear of vsdelay in case of DPI
 773          * assume we do not need any delay when DPI is a source of
 774          * sync signals
 775          */
 776         ret = regmap_write(tc->regmap, VPCTRL0,
 777                            FIELD_PREP(VSDELAY, 0) |
 778                            OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED);
 779         if (ret)
 780                 return ret;
 781
 782         ret = regmap_write(tc->regmap, HTIM01,
 783                            FIELD_PREP(HBPR, ALIGN(left_margin, 2)) |
 784                            FIELD_PREP(HPW, ALIGN(hsync_len, 2)));
 785         if (ret)
 786                 return ret;
 787
 788         ret = regmap_write(tc->regmap, HTIM02,
 789                            FIELD_PREP(HDISPR, ALIGN(mode->hdisplay, 2)) |
 790                            FIELD_PREP(HFPR, ALIGN(right_margin, 2)));
 791         if (ret)
 792                 return ret;
 793
 794         ret = regmap_write(tc->regmap, VTIM01,
 795                            FIELD_PREP(VBPR, upper_margin) |
 796                            FIELD_PREP(VSPR, vsync_len));
 797         if (ret)
 798                 return ret;
 799
 800         ret = regmap_write(tc->regmap, VTIM02,
 801                            FIELD_PREP(VFPR, lower_margin) |
 802                            FIELD_PREP(VDISPR, mode->vdisplay));
 803         if (ret)
 804                 return ret;
 805
 806         ret = regmap_write(tc->regmap, VFUEN0, VFUEN); /* update settings */
 807         if (ret)
 808                 return ret;
 809
 810         /* Test pattern settings */
 811         ret = regmap_write(tc->regmap, TSTCTL,
 812                            FIELD_PREP(COLOR_R, 120) |
 813                            FIELD_PREP(COLOR_G, 20) |
 814                            FIELD_PREP(COLOR_B, 99) |
 815                            ENI2CFILTER |
 816                            FIELD_PREP(COLOR_BAR_MODE, COLOR_BAR_MODE_BARS));
 817         if (ret)
 818                 return ret;
 819
 820         /* DP Main Stream Attributes */
 821         vid_sync_dly = hsync_len + left_margin + mode->hdisplay;
 822         ret = regmap_write(tc->regmap, DP0_VIDSYNCDELAY,
 823                  FIELD_PREP(THRESH_DLY, max_tu_symbol) |
 824                  FIELD_PREP(VID_SYNC_DLY, vid_sync_dly));
 825
 826         ret = regmap_write(tc->regmap, DP0_TOTALVAL,
 827                            FIELD_PREP(H_TOTAL, mode->htotal) |
 828                            FIELD_PREP(V_TOTAL, mode->vtotal));
 829         if (ret)
 830                 return ret;
 831
 832         ret = regmap_write(tc->regmap, DP0_STARTVAL,
 833                            FIELD_PREP(H_START, left_margin + hsync_len) |
 834                            FIELD_PREP(V_START, upper_margin + vsync_len));
 835         if (ret)
 836                 return ret;
 837
 838         ret = regmap_write(tc->regmap, DP0_ACTIVEVAL,
 839                            FIELD_PREP(V_ACT, mode->vdisplay) |
 840                            FIELD_PREP(H_ACT, mode->hdisplay));
 841         if (ret)
 842                 return ret;
 843
 844         dp0_syncval = FIELD_PREP(VS_WIDTH, vsync_len) |
 845                       FIELD_PREP(HS_WIDTH, hsync_len);
 846
 847         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 848                 dp0_syncval |= SYNCVAL_VS_POL_ACTIVE_LOW;
 849
 850         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 851                 dp0_syncval |= SYNCVAL_HS_POL_ACTIVE_LOW;
 852
 853         ret = regmap_write(tc->regmap, DP0_SYNCVAL, dp0_syncval);
 854         if (ret)
 855                 return ret;
 856
 857         ret = regmap_write(tc->regmap, DPIPXLFMT,
 858                            VS_POL_ACTIVE_LOW | HS_POL_ACTIVE_LOW |
 859                            DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 |
 860                            DPI_BPP_RGB888);
 861         if (ret)
 862                 return ret;
 863
 864         ret = regmap_write(tc->regmap, DP0_MISC,
 865                            FIELD_PREP(MAX_TU_SYMBOL, max_tu_symbol) |
 866                            FIELD_PREP(TU_SIZE, TU_SIZE_RECOMMENDED) |
 867                            BPC_8);
 868         if (ret)
 869                 return ret;
 870
 871         return 0;
 872 }
 873
 874 static int tc_wait_link_training(struct tc_data *tc)
 875 {
 876         u32 value;
 877         int ret;
 878
 879         ret = tc_poll_timeout(tc, DP0_LTSTAT, LT_LOOPDONE,
 880                               LT_LOOPDONE, 500, 100000);
 881         if (ret) {
 882                 dev_err(tc->dev, "Link training timeout waiting for LT_LOOPDONE!\n");
 883                 return ret;
 884         }
 885
 886         ret = regmap_read(tc->regmap, DP0_LTSTAT, &value);
 887         if (ret)
 888                 return ret;
 889
 890         return (value >> 8) & 0x7;
 891 }
 892
 893 static int tc_main_link_enable(struct tc_data *tc)
 894 {
 895         struct drm_dp_aux *aux = &tc->aux;
 896         struct device *dev = tc->dev;
 897         u32 dp_phy_ctrl;
 898         u32 value;
 899         int ret;
 900         u8 tmp[DP_LINK_STATUS_SIZE];
 901
 902         dev_dbg(tc->dev, "link enable\n");
 903
 904         ret = regmap_read(tc->regmap, DP0CTL, &value);
 905         if (ret)
 906                 return ret;
 907
 908         if (WARN_ON(value & DP_EN)) {
 909                 ret = regmap_write(tc->regmap, DP0CTL, 0);
 910                 if (ret)
 911                         return ret;
 912         }
 913
 914         ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc));
 915         if (ret)
 916                 return ret;
 917         /* SSCG and BW27 on DP1 must be set to the same as on DP0 */
 918         ret = regmap_write(tc->regmap, DP1_SRCCTRL,
 919                  (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) |
 920                  ((tc->link.rate != 162000) ? DP0_SRCCTRL_BW27 : 0));
 921         if (ret)
 922                 return ret;
 923
 924         ret = tc_set_syspllparam(tc);
 925         if (ret)
 926                 return ret;
 927
 928         /* Setup Main Link */
 929         dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN | PHY_M0_EN;
 930         if (tc->link.num_lanes == 2)
 931                 dp_phy_ctrl |= PHY_2LANE;
 932
 933         ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
 934         if (ret)
 935                 return ret;
 936
 937         /* PLL setup */
 938         ret = tc_pllupdate(tc, DP0_PLLCTRL);
 939         if (ret)
 940                 return ret;
 941
 942         ret = tc_pllupdate(tc, DP1_PLLCTRL);
 943         if (ret)
 944                 return ret;
 945
 946         /* Reset/Enable Main Links */
 947         dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST;
 948         ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
 949         usleep_range(100, 200);
 950         dp_phy_ctrl &= ~(DP_PHY_RST | PHY_M1_RST | PHY_M0_RST);
 951         ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
 952
 953         ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 500, 100000);
 954         if (ret) {
 955                 dev_err(dev, "timeout waiting for phy become ready");
 956                 return ret;
 957         }
 958
 959         /* Set misc: 8 bits per color */
 960         ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8);
 961         if (ret)
 962                 return ret;
 963
 964         /*
 965          * ASSR mode
 966          * on TC358767 side ASSR configured through strap pin
 967          * seems there is no way to change this setting from SW
 968          *
 969          * check is tc configured for same mode
 970          */
 971         if (tc->assr != tc->link.assr) {
 972                 dev_dbg(dev, "Trying to set display to ASSR: %d\n",
 973                         tc->assr);
 974                 /* try to set ASSR on display side */
 975                 tmp[0] = tc->assr;
 976                 ret = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, tmp[0]);
 977                 if (ret < 0)
 978                         goto err_dpcd_read;
 979                 /* read back */
 980                 ret = drm_dp_dpcd_readb(aux, DP_EDP_CONFIGURATION_SET, tmp);
 981                 if (ret < 0)
 982                         goto err_dpcd_read;
 983
 984                 if (tmp[0] != tc->assr) {
 985                         dev_dbg(dev, "Failed to switch display ASSR to %d, falling back to unscrambled mode\n",
 986                                 tc->assr);
 987                         /* trying with disabled scrambler */
 988                         tc->link.scrambler_dis = true;
 989                 }
 990         }
 991
 992         /* Setup Link & DPRx Config for Training */
 993         tmp[0] = drm_dp_link_rate_to_bw_code(tc->link.rate);
 994         tmp[1] = tc->link.num_lanes;
 995
 996         if (drm_dp_enhanced_frame_cap(tc->link.dpcd))
 997                 tmp[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 998
 999         ret = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, tmp, 2);
1000         if (ret < 0)
1001                 goto err_dpcd_write;
1002
1003         /* DOWNSPREAD_CTRL */
1004         tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00;
1005         /* MAIN_LINK_CHANNEL_CODING_SET */
1006         tmp[1] =  DP_SET_ANSI_8B10B;
1007         ret = drm_dp_dpcd_write(aux, DP_DOWNSPREAD_CTRL, tmp, 2);
1008         if (ret < 0)
1009                 goto err_dpcd_write;
1010
1011         /* Reset voltage-swing & pre-emphasis */
1012         tmp[0] = tmp[1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 |
1013                           DP_TRAIN_PRE_EMPH_LEVEL_0;
1014         ret = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, tmp, 2);
1015         if (ret < 0)
1016                 goto err_dpcd_write;
1017
1018         /* Clock-Recovery */
1019
1020         /* Set DPCD 0x102 for Training Pattern 1 */
1021         ret = regmap_write(tc->regmap, DP0_SNKLTCTRL,
1022                            DP_LINK_SCRAMBLING_DISABLE |
1023                            DP_TRAINING_PATTERN_1);
1024         if (ret)
1025                 return ret;
1026
1027         ret = regmap_write(tc->regmap, DP0_LTLOOPCTRL,
1028                            (15 << 28) | /* Defer Iteration Count */
1029                            (15 << 24) | /* Loop Iteration Count */
1030                            (0xd << 0)); /* Loop Timer Delay */
1031         if (ret)
1032                 return ret;
1033
1034         ret = regmap_write(tc->regmap, DP0_SRCCTRL,
1035                            tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
1036                            DP0_SRCCTRL_AUTOCORRECT |
1037                            DP0_SRCCTRL_TP1);
1038         if (ret)
1039                 return ret;
1040
1041         /* Enable DP0 to start Link Training */
1042         ret = regmap_write(tc->regmap, DP0CTL,
1043                            (drm_dp_enhanced_frame_cap(tc->link.dpcd) ?
1044                                 EF_EN : 0) | DP_EN);
1045         if (ret)
1046                 return ret;
1047
1048         /* wait */
1049
1050         ret = tc_wait_link_training(tc);
1051         if (ret < 0)
1052                 return ret;
1053
1054         if (ret) {
1055                 dev_err(tc->dev, "Link training phase 1 failed: %s\n",
1056                         training_pattern1_errors[ret]);
1057                 return -ENODEV;
1058         }
1059
1060         /* Channel Equalization */
1061
1062         /* Set DPCD 0x102 for Training Pattern 2 */
1063         ret = regmap_write(tc->regmap, DP0_SNKLTCTRL,
1064                            DP_LINK_SCRAMBLING_DISABLE |
1065                            DP_TRAINING_PATTERN_2);
1066         if (ret)
1067                 return ret;
1068
1069         ret = regmap_write(tc->regmap, DP0_SRCCTRL,
1070                            tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
1071                            DP0_SRCCTRL_AUTOCORRECT |
1072                            DP0_SRCCTRL_TP2);
1073         if (ret)
1074                 return ret;
1075
1076         /* wait */
1077         ret = tc_wait_link_training(tc);
1078         if (ret < 0)
1079                 return ret;
1080
1081         if (ret) {
1082                 dev_err(tc->dev, "Link training phase 2 failed: %s\n",
1083                         training_pattern2_errors[ret]);
1084                 return -ENODEV;
1085         }
1086
1087         /*
1088          * Toshiba's documentation suggests to first clear DPCD 0x102, then
1089          * clear the training pattern bit in DP0_SRCCTRL. Testing shows
1090          * that the link sometimes drops if those steps are done in that order,
1091          * but if the steps are done in reverse order, the link stays up.
1092          *
1093          * So we do the steps differently than documented here.
1094          */
1095
1096         /* Clear Training Pattern, set AutoCorrect Mode = 1 */
1097         ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc) |
1098                            DP0_SRCCTRL_AUTOCORRECT);
1099         if (ret)
1100                 return ret;
1101
1102         /* Clear DPCD 0x102 */
1103         /* Note: Can Not use DP0_SNKLTCTRL (0x06E4) short cut */
1104         tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00;
1105         ret = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, tmp[0]);
1106         if (ret < 0)
1107                 goto err_dpcd_write;
1108
1109         /* Check link status */
1110         ret = drm_dp_dpcd_read_link_status(aux, tmp);
1111         if (ret < 0)
1112                 goto err_dpcd_read;
1113
1114         ret = 0;
1115
1116         value = tmp[0] & DP_CHANNEL_EQ_BITS;
1117
1118         if (value != DP_CHANNEL_EQ_BITS) {
1119                 dev_err(tc->dev, "Lane 0 failed: %x\n", value);
1120                 ret = -ENODEV;
1121         }
1122
1123         if (tc->link.num_lanes == 2) {
1124                 value = (tmp[0] >> 4) & DP_CHANNEL_EQ_BITS;
1125
1126                 if (value != DP_CHANNEL_EQ_BITS) {
1127                         dev_err(tc->dev, "Lane 1 failed: %x\n", value);
1128                         ret = -ENODEV;
1129                 }
1130
1131                 if (!(tmp[2] & DP_INTERLANE_ALIGN_DONE)) {
1132                         dev_err(tc->dev, "Interlane align failed\n");
1133                         ret = -ENODEV;
1134                 }
1135         }
1136
1137         if (ret) {
1138                 dev_err(dev, "0x0202 LANE0_1_STATUS:            0x%02x\n", tmp[0]);
1139                 dev_err(dev, "0x0203 LANE2_3_STATUS             0x%02x\n", tmp[1]);
1140                 dev_err(dev, "0x0204 LANE_ALIGN_STATUS_UPDATED: 0x%02x\n", tmp[2]);
1141                 dev_err(dev, "0x0205 SINK_STATUS:               0x%02x\n", tmp[3]);
1142                 dev_err(dev, "0x0206 ADJUST_REQUEST_LANE0_1:    0x%02x\n", tmp[4]);
1143                 dev_err(dev, "0x0207 ADJUST_REQUEST_LANE2_3:    0x%02x\n", tmp[5]);
1144                 return ret;
1145         }
1146
1147         return 0;
1148 err_dpcd_read:
1149         dev_err(tc->dev, "Failed to read DPCD: %d\n", ret);
1150         return ret;
1151 err_dpcd_write:
1152         dev_err(tc->dev, "Failed to write DPCD: %d\n", ret);
1153         return ret;
1154 }
1155
1156 static int tc_main_link_disable(struct tc_data *tc)
1157 {
1158         int ret;
1159
1160         dev_dbg(tc->dev, "link disable\n");
1161
1162         ret = regmap_write(tc->regmap, DP0_SRCCTRL, 0);
1163         if (ret)
1164                 return ret;
1165
1166         return regmap_write(tc->regmap, DP0CTL, 0);
1167 }
1168
1169 static int tc_stream_enable(struct tc_data *tc)
1170 {
1171         int ret;
1172         u32 value;
1173
1174         dev_dbg(tc->dev, "enable video stream\n");
1175
1176         /* PXL PLL setup */
1177         if (tc_test_pattern) {
1178                 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk),
1179                                     1000 * tc->mode.clock);
1180                 if (ret)
1181                         return ret;
1182         }
1183
1184         ret = tc_set_video_mode(tc, &tc->mode);
1185         if (ret)
1186                 return ret;
1187
1188         /* Set M/N */
1189         ret = tc_stream_clock_calc(tc);
1190         if (ret)
1191                 return ret;
1192
1193         value = VID_MN_GEN | DP_EN;
1194         if (drm_dp_enhanced_frame_cap(tc->link.dpcd))
1195                 value |= EF_EN;
1196         ret = regmap_write(tc->regmap, DP0CTL, value);
1197         if (ret)
1198                 return ret;
1199         /*
1200          * VID_EN assertion should be delayed by at least N * LSCLK
1201          * cycles from the time VID_MN_GEN is enabled in order to
1202          * generate stable values for VID_M. LSCLK is 270 MHz or
1203          * 162 MHz, VID_N is set to 32768 in  tc_stream_clock_calc(),
1204          * so a delay of at least 203 us should suffice.
1205          */
1206         usleep_range(500, 1000);
1207         value |= VID_EN;
1208         ret = regmap_write(tc->regmap, DP0CTL, value);
1209         if (ret)
1210                 return ret;
1211         /* Set input interface */
1212         value = DP0_AUDSRC_NO_INPUT;
1213         if (tc_test_pattern)
1214                 value |= DP0_VIDSRC_COLOR_BAR;
1215         else
1216                 value |= DP0_VIDSRC_DPI_RX;
1217         ret = regmap_write(tc->regmap, SYSCTRL, value);
1218         if (ret)
1219                 return ret;
1220
1221         return 0;
1222 }
1223
1224 static int tc_stream_disable(struct tc_data *tc)
1225 {
1226         int ret;
1227
1228         dev_dbg(tc->dev, "disable video stream\n");
1229
1230         ret = regmap_update_bits(tc->regmap, DP0CTL, VID_EN, 0);
1231         if (ret)
1232                 return ret;
1233
1234         tc_pxl_pll_dis(tc);
1235
1236         return 0;
1237 }
1238
1239 static void tc_bridge_pre_enable(struct drm_bridge *bridge)
1240 {
1241         struct tc_data *tc = bridge_to_tc(bridge);
1242
1243         drm_panel_prepare(tc->panel);
1244 }
1245
1246 static void tc_bridge_enable(struct drm_bridge *bridge)
1247 {
1248         struct tc_data *tc = bridge_to_tc(bridge);
1249         int ret;
1250
1251         ret = tc_get_display_props(tc);
1252         if (ret < 0) {
1253                 dev_err(tc->dev, "failed to read display props: %d\n", ret);
1254                 return;
1255         }
1256
1257         ret = tc_main_link_enable(tc);
1258         if (ret < 0) {
1259                 dev_err(tc->dev, "main link enable error: %d\n", ret);
1260                 return;
1261         }
1262
1263         ret = tc_stream_enable(tc);
1264         if (ret < 0) {
1265                 dev_err(tc->dev, "main link stream start error: %d\n", ret);
1266                 tc_main_link_disable(tc);
1267                 return;
1268         }
1269
1270         drm_panel_enable(tc->panel);
1271 }
1272
1273 static void tc_bridge_disable(struct drm_bridge *bridge)
1274 {
1275         struct tc_data *tc = bridge_to_tc(bridge);
1276         int ret;
1277
1278         drm_panel_disable(tc->panel);
1279
1280         ret = tc_stream_disable(tc);
1281         if (ret < 0)
1282                 dev_err(tc->dev, "main link stream stop error: %d\n", ret);
1283
1284         ret = tc_main_link_disable(tc);
1285         if (ret < 0)
1286                 dev_err(tc->dev, "main link disable error: %d\n", ret);
1287 }
1288
1289 static void tc_bridge_post_disable(struct drm_bridge *bridge)
1290 {
1291         struct tc_data *tc = bridge_to_tc(bridge);
1292
1293         drm_panel_unprepare(tc->panel);
1294 }
1295
1296 static bool tc_bridge_mode_fixup(struct drm_bridge *bridge,
1297                                  const struct drm_display_mode *mode,
1298                                  struct drm_display_mode *adj)
1299 {
1300         /* Fixup sync polarities, both hsync and vsync are active low */
1301         adj->flags = mode->flags;
1302         adj->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
1303         adj->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
1304
1305         return true;
1306 }
1307
1308 static enum drm_mode_status tc_mode_valid(struct drm_bridge *bridge,
1309                                           const struct drm_display_mode *mode)
1310 {
1311         struct tc_data *tc = bridge_to_tc(bridge);
1312         u32 req, avail;
1313         u32 bits_per_pixel = 24;
1314
1315         /* DPI interface clock limitation: upto 154 MHz */
1316         if (mode->clock > 154000)
1317                 return MODE_CLOCK_HIGH;
1318
1319         req = mode->clock * bits_per_pixel / 8;
1320         avail = tc->link.num_lanes * tc->link.rate;
1321
1322         if (req > avail)
1323                 return MODE_BAD;
1324
1325         return MODE_OK;
1326 }
1327
1328 static void tc_bridge_mode_set(struct drm_bridge *bridge,
1329                                const struct drm_display_mode *mode,
1330                                const struct drm_display_mode *adj)
1331 {
1332         struct tc_data *tc = bridge_to_tc(bridge);
1333
1334         tc->mode = *mode;
1335 }
1336
1337 static int tc_connector_get_modes(struct drm_connector *connector)
1338 {
1339         struct tc_data *tc = connector_to_tc(connector);
1340         struct edid *edid;
1341         int count;
1342         int ret;
1343
1344         ret = tc_get_display_props(tc);
1345         if (ret < 0) {
1346                 dev_err(tc->dev, "failed to read display props: %d\n", ret);
1347                 return 0;
1348         }
1349
1350         count = drm_panel_get_modes(tc->panel, connector);
1351         if (count > 0)
1352                 return count;
1353
1354         edid = drm_get_edid(connector, &tc->aux.ddc);
1355
1356         kfree(tc->edid);
1357         tc->edid = edid;
1358         if (!edid)
1359                 return 0;
1360
1361         drm_connector_update_edid_property(connector, edid);
1362         count = drm_add_edid_modes(connector, edid);
1363
1364         return count;
1365 }
1366
1367 static const struct drm_connector_helper_funcs tc_connector_helper_funcs = {
1368         .get_modes = tc_connector_get_modes,
1369 };
1370
1371 static enum drm_connector_status tc_connector_detect(struct drm_connector *connector,
1372                                                      bool force)
1373 {
1374         struct tc_data *tc = connector_to_tc(connector);
1375         bool conn;
1376         u32 val;
1377         int ret;
1378
1379         if (tc->hpd_pin < 0) {
1380                 if (tc->panel)
1381                         return connector_status_connected;
1382                 else
1383                         return connector_status_unknown;
1384         }
1385
1386         ret = regmap_read(tc->regmap, GPIOI, &val);
1387         if (ret)
1388                 return connector_status_unknown;
1389
1390         conn = val & BIT(tc->hpd_pin);
1391
1392         if (conn)
1393                 return connector_status_connected;
1394         else
1395                 return connector_status_disconnected;
1396 }
1397
1398 static const struct drm_connector_funcs tc_connector_funcs = {
1399         .detect = tc_connector_detect,
1400         .fill_modes = drm_helper_probe_single_connector_modes,
1401         .destroy = drm_connector_cleanup,
1402         .reset = drm_atomic_helper_connector_reset,
1403         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1404         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1405 };
1406
1407 static int tc_bridge_attach(struct drm_bridge *bridge,
1408                             enum drm_bridge_attach_flags flags)
1409 {
1410         u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1411         struct tc_data *tc = bridge_to_tc(bridge);
1412         struct drm_device *drm = bridge->dev;
1413         int ret;
1414
1415         if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {
1416                 DRM_ERROR("Fix bridge driver to make connector optional!");
1417                 return -EINVAL;
1418         }
1419
1420         /* Create DP/eDP connector */
1421         drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs);
1422         ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs,
1423                                  tc->panel ? DRM_MODE_CONNECTOR_eDP :
1424                                  DRM_MODE_CONNECTOR_DisplayPort);
1425         if (ret)
1426                 return ret;
1427
1428         /* Don't poll if don't have HPD connected */
1429         if (tc->hpd_pin >= 0) {
1430                 if (tc->have_irq)
1431                         tc->connector.polled = DRM_CONNECTOR_POLL_HPD;
1432                 else
1433                         tc->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
1434                                                DRM_CONNECTOR_POLL_DISCONNECT;
1435         }
1436
1437         if (tc->panel)
1438                 drm_panel_attach(tc->panel, &tc->connector);
1439
1440         drm_display_info_set_bus_formats(&tc->connector.display_info,
1441                                          &bus_format, 1);
1442         tc->connector.display_info.bus_flags =
1443                 DRM_BUS_FLAG_DE_HIGH |
1444                 DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE |
1445                 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE;
1446         drm_connector_attach_encoder(&tc->connector, tc->bridge.encoder);
1447
1448         return 0;
1449 }
1450
1451 static const struct drm_bridge_funcs tc_bridge_funcs = {
1452         .attach = tc_bridge_attach,
1453         .mode_valid = tc_mode_valid,
1454         .mode_set = tc_bridge_mode_set,
1455         .pre_enable = tc_bridge_pre_enable,
1456         .enable = tc_bridge_enable,
1457         .disable = tc_bridge_disable,
1458         .post_disable = tc_bridge_post_disable,
1459         .mode_fixup = tc_bridge_mode_fixup,
1460 };
1461
1462 static bool tc_readable_reg(struct device *dev, unsigned int reg)
1463 {
1464         return reg != SYSCTRL;
1465 }
1466
1467 static const struct regmap_range tc_volatile_ranges[] = {
1468         regmap_reg_range(DP0_AUXWDATA(0), DP0_AUXSTATUS),
1469         regmap_reg_range(DP0_LTSTAT, DP0_SNKLTCHGREQ),
1470         regmap_reg_range(DP_PHY_CTRL, DP_PHY_CTRL),
1471         regmap_reg_range(DP0_PLLCTRL, PXL_PLLCTRL),
1472         regmap_reg_range(VFUEN0, VFUEN0),
1473         regmap_reg_range(INTSTS_G, INTSTS_G),
1474         regmap_reg_range(GPIOI, GPIOI),
1475 };
1476
1477 static const struct regmap_access_table tc_volatile_table = {
1478         .yes_ranges = tc_volatile_ranges,
1479         .n_yes_ranges = ARRAY_SIZE(tc_volatile_ranges),
1480 };
1481
1482 static bool tc_writeable_reg(struct device *dev, unsigned int reg)
1483 {
1484         return (reg != TC_IDREG) &&
1485                (reg != DP0_LTSTAT) &&
1486                (reg != DP0_SNKLTCHGREQ);
1487 }
1488
1489 static const struct regmap_config tc_regmap_config = {
1490         .name = "tc358767",
1491         .reg_bits = 16,
1492         .val_bits = 32,
1493         .reg_stride = 4,
1494         .max_register = PLL_DBG,
1495         .cache_type = REGCACHE_RBTREE,
1496         .readable_reg = tc_readable_reg,
1497         .volatile_table = &tc_volatile_table,
1498         .writeable_reg = tc_writeable_reg,
1499         .reg_format_endian = REGMAP_ENDIAN_BIG,
1500         .val_format_endian = REGMAP_ENDIAN_LITTLE,
1501 };
1502
1503 static irqreturn_t tc_irq_handler(int irq, void *arg)
1504 {
1505         struct tc_data *tc = arg;
1506         u32 val;
1507         int r;
1508
1509         r = regmap_read(tc->regmap, INTSTS_G, &val);
1510         if (r)
1511                 return IRQ_NONE;
1512
1513         if (!val)
1514                 return IRQ_NONE;
1515
1516         if (val & INT_SYSERR) {
1517                 u32 stat = 0;
1518
1519                 regmap_read(tc->regmap, SYSSTAT, &stat);
1520
1521                 dev_err(tc->dev, "syserr %x\n", stat);
1522         }
1523
1524         if (tc->hpd_pin >= 0 && tc->bridge.dev) {
1525                 /*
1526                  * H is triggered when the GPIO goes high.
1527                  *
1528                  * LC is triggered when the GPIO goes low and stays low for
1529                  * the duration of LCNT
1530                  */
1531                 bool h = val & INT_GPIO_H(tc->hpd_pin);
1532                 bool lc = val & INT_GPIO_LC(tc->hpd_pin);
1533
1534                 dev_dbg(tc->dev, "GPIO%d: %s %s\n", tc->hpd_pin,
1535                         h ? "H" : "", lc ? "LC" : "");
1536
1537                 if (h || lc)
1538                         drm_kms_helper_hotplug_event(tc->bridge.dev);
1539         }
1540
1541         regmap_write(tc->regmap, INTSTS_G, val);
1542
1543         return IRQ_HANDLED;
1544 }
1545
1546 static int tc_probe(struct i2c_client *client, const struct i2c_device_id *id)
1547 {
1548         struct device *dev = &client->dev;
1549         struct tc_data *tc;
1550         int ret;
1551
1552         tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL);
1553         if (!tc)
1554                 return -ENOMEM;
1555
1556         tc->dev = dev;
1557
1558         /* port@2 is the output port */
1559         ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &tc->panel, NULL);
1560         if (ret && ret != -ENODEV)
1561                 return ret;
1562
1563         /* Shut down GPIO is optional */
1564         tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH);
1565         if (IS_ERR(tc->sd_gpio))
1566                 return PTR_ERR(tc->sd_gpio);
1567
1568         if (tc->sd_gpio) {
1569                 gpiod_set_value_cansleep(tc->sd_gpio, 0);
1570                 usleep_range(5000, 10000);
1571         }
1572
1573         /* Reset GPIO is optional */
1574         tc->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
1575         if (IS_ERR(tc->reset_gpio))
1576                 return PTR_ERR(tc->reset_gpio);
1577
1578         if (tc->reset_gpio) {
1579                 gpiod_set_value_cansleep(tc->reset_gpio, 1);
1580                 usleep_range(5000, 10000);
1581         }
1582
1583         tc->refclk = devm_clk_get(dev, "ref");
1584         if (IS_ERR(tc->refclk)) {
1585                 ret = PTR_ERR(tc->refclk);
1586                 dev_err(dev, "Failed to get refclk: %d\n", ret);
1587                 return ret;
1588         }
1589
1590         tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config);
1591         if (IS_ERR(tc->regmap)) {
1592                 ret = PTR_ERR(tc->regmap);
1593                 dev_err(dev, "Failed to initialize regmap: %d\n", ret);
1594                 return ret;
1595         }
1596
1597         ret = of_property_read_u32(dev->of_node, "toshiba,hpd-pin",
1598                                    &tc->hpd_pin);
1599         if (ret) {
1600                 tc->hpd_pin = -ENODEV;
1601         } else {
1602                 if (tc->hpd_pin < 0 || tc->hpd_pin > 1) {
1603                         dev_err(dev, "failed to parse HPD number\n");
1604                         return ret;
1605                 }
1606         }
1607
1608         if (client->irq > 0) {
1609                 /* enable SysErr */
1610                 regmap_write(tc->regmap, INTCTL_G, INT_SYSERR);
1611
1612                 ret = devm_request_threaded_irq(dev, client->irq,
1613                                                 NULL, tc_irq_handler,
1614                                                 IRQF_ONESHOT,
1615                                                 "tc358767-irq", tc);
1616                 if (ret) {
1617                         dev_err(dev, "failed to register dp interrupt\n");
1618                         return ret;
1619                 }
1620
1621                 tc->have_irq = true;
1622         }
1623
1624         ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev);
1625         if (ret) {
1626                 dev_err(tc->dev, "can not read device ID: %d\n", ret);
1627                 return ret;
1628         }
1629
1630         if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) {
1631                 dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev);
1632                 return -EINVAL;
1633         }
1634
1635         tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */
1636
1637         if (!tc->reset_gpio) {
1638                 /*
1639                  * If the reset pin isn't present, do a software reset. It isn't
1640                  * as thorough as the hardware reset, as we can't reset the I2C
1641                  * communication block for obvious reasons, but it's getting the
1642                  * chip into a defined state.
1643                  */
1644                 regmap_update_bits(tc->regmap, SYSRSTENB,
1645                                 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP,
1646                                 0);
1647                 regmap_update_bits(tc->regmap, SYSRSTENB,
1648                                 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP,
1649                                 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP);
1650                 usleep_range(5000, 10000);
1651         }
1652
1653         if (tc->hpd_pin >= 0) {
1654                 u32 lcnt_reg = tc->hpd_pin == 0 ? INT_GP0_LCNT : INT_GP1_LCNT;
1655                 u32 h_lc = INT_GPIO_H(tc->hpd_pin) | INT_GPIO_LC(tc->hpd_pin);
1656
1657                 /* Set LCNT to 2ms */
1658                 regmap_write(tc->regmap, lcnt_reg,
1659                              clk_get_rate(tc->refclk) * 2 / 1000);
1660                 /* We need the "alternate" mode for HPD */
1661                 regmap_write(tc->regmap, GPIOM, BIT(tc->hpd_pin));
1662
1663                 if (tc->have_irq) {
1664                         /* enable H & LC */
1665                         regmap_update_bits(tc->regmap, INTCTL_G, h_lc, h_lc);
1666                 }
1667         }
1668
1669         ret = tc_aux_link_setup(tc);
1670         if (ret)
1671                 return ret;
1672
1673         /* Register DP AUX channel */
1674         tc->aux.name = "TC358767 AUX i2c adapter";
1675         tc->aux.dev = tc->dev;
1676         tc->aux.transfer = tc_aux_transfer;
1677         ret = drm_dp_aux_register(&tc->aux);
1678         if (ret)
1679                 return ret;
1680
1681         tc->bridge.funcs = &tc_bridge_funcs;
1682         tc->bridge.of_node = dev->of_node;
1683         drm_bridge_add(&tc->bridge);
1684
1685         i2c_set_clientdata(client, tc);
1686
1687         return 0;
1688 }
1689
1690 static int tc_remove(struct i2c_client *client)
1691 {
1692         struct tc_data *tc = i2c_get_clientdata(client);
1693
1694         drm_bridge_remove(&tc->bridge);
1695         drm_dp_aux_unregister(&tc->aux);
1696
1697         return 0;
1698 }
1699
1700 static const struct i2c_device_id tc358767_i2c_ids[] = {
1701         { "tc358767", 0 },
1702         { }
1703 };
1704 MODULE_DEVICE_TABLE(i2c, tc358767_i2c_ids);
1705
1706 static const struct of_device_id tc358767_of_ids[] = {
1707         { .compatible = "toshiba,tc358767", },
1708         { }
1709 };
1710 MODULE_DEVICE_TABLE(of, tc358767_of_ids);
1711
1712 static struct i2c_driver tc358767_driver = {
1713         .driver = {
1714                 .name = "tc358767",
1715                 .of_match_table = tc358767_of_ids,
1716         },
1717         .id_table = tc358767_i2c_ids,
1718         .probe = tc_probe,
1719         .remove = tc_remove,
1720 };
1721 module_i2c_driver(tc358767_driver);
1722
1723 MODULE_AUTHOR("Andrey Gusakov <[email protected]>");
1724 MODULE_DESCRIPTION("tc358767 eDP encoder driver");
1725 MODULE_LICENSE("GPL");