drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <[email protected]>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <[email protected]>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <linux/sched/clock.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_encoder.h>
  37 #include <drm/drm_fb_helper.h>
  38 #include <drm/drm_dp_dual_mode_helper.h>
  39 #include <drm/drm_dp_mst_helper.h>
  40 #include <drm/drm_rect.h>
  41 #include <drm/drm_atomic.h>
  42 #include <media/cec-notifier.h>
  43
  44 /**
  45  * __wait_for - magic wait macro
  46  *
  47  * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
  48  * important that we check the condition again after having timed out, since the
  49  * timeout could be due to preemption or similar and we've never had a chance to
  50  * check the condition before the timeout.
  51  */
  52 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
  53         const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
  54         long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
  55         int ret__;                                                      \
  56         might_sleep();                                                  \
  57         for (;;) {                                                      \
  58                 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
  59                 OP;                                                     \
  60                 /* Guarantee COND check prior to timeout */             \
  61                 barrier();                                              \
  62                 if (COND) {                                             \
  63                         ret__ = 0;                                      \
  64                         break;                                          \
  65                 }                                                       \
  66                 if (expired__) {                                        \
  67                         ret__ = -ETIMEDOUT;                             \
  68                         break;                                          \
  69                 }                                                       \
  70                 usleep_range(wait__, wait__ * 2);                       \
  71                 if (wait__ < (Wmax))                                    \
  72                         wait__ <<= 1;                                   \
  73         }                                                               \
  74         ret__;                                                          \
  75 })
  76
  77 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
  78                                                    (Wmax))
  79 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 10, 1000)
  80
  81 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  82 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  83 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  84 #else
  85 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  86 #endif
  87
  88 #define _wait_for_atomic(COND, US, ATOMIC) \
  89 ({ \
  90         int cpu, ret, timeout = (US) * 1000; \
  91         u64 base; \
  92         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  93         if (!(ATOMIC)) { \
  94                 preempt_disable(); \
  95                 cpu = smp_processor_id(); \
  96         } \
  97         base = local_clock(); \
  98         for (;;) { \
  99                 u64 now = local_clock(); \
 100                 if (!(ATOMIC)) \
 101                         preempt_enable(); \
 102                 /* Guarantee COND check prior to timeout */ \
 103                 barrier(); \
 104                 if (COND) { \
 105                         ret = 0; \
 106                         break; \
 107                 } \
 108                 if (now - base >= timeout) { \
 109                         ret = -ETIMEDOUT; \
 110                         break; \
 111                 } \
 112                 cpu_relax(); \
 113                 if (!(ATOMIC)) { \
 114                         preempt_disable(); \
 115                         if (unlikely(cpu != smp_processor_id())) { \
 116                                 timeout -= now - base; \
 117                                 cpu = smp_processor_id(); \
 118                                 base = local_clock(); \
 119                         } \
 120                 } \
 121         } \
 122         ret; \
 123 })
 124
 125 #define wait_for_us(COND, US) \
 126 ({ \
 127         int ret__; \
 128         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 129         if ((US) > 10) \
 130                 ret__ = _wait_for((COND), (US), 10, 10); \
 131         else \
 132                 ret__ = _wait_for_atomic((COND), (US), 0); \
 133         ret__; \
 134 })
 135
 136 #define wait_for_atomic_us(COND, US) \
 137 ({ \
 138         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 139         BUILD_BUG_ON((US) > 50000); \
 140         _wait_for_atomic((COND), (US), 1); \
 141 })
 142
 143 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
 144
 145 #define KHz(x) (1000 * (x))
 146 #define MHz(x) KHz(1000 * (x))
 147
 148 #define KBps(x) (1000 * (x))
 149 #define MBps(x) KBps(1000 * (x))
 150 #define GBps(x) ((u64)1000 * MBps((x)))
 151
 152 /*
 153  * Display related stuff
 154  */
 155
 156 /* store information about an Ixxx DVO */
 157 /* The i830->i865 use multiple DVOs with multiple i2cs */
 158 /* the i915, i945 have a single sDVO i2c bus - which is different */
 159 #define MAX_OUTPUTS 6
 160 /* maximum connectors per crtcs in the mode set */
 161
 162 #define INTEL_I2C_BUS_DVO 1
 163 #define INTEL_I2C_BUS_SDVO 2
 164
 165 /* these are outputs from the chip - integrated only
 166    external chips are via DVO or SDVO output */
 167 enum intel_output_type {
 168         INTEL_OUTPUT_UNUSED = 0,
 169         INTEL_OUTPUT_ANALOG = 1,
 170         INTEL_OUTPUT_DVO = 2,
 171         INTEL_OUTPUT_SDVO = 3,
 172         INTEL_OUTPUT_LVDS = 4,
 173         INTEL_OUTPUT_TVOUT = 5,
 174         INTEL_OUTPUT_HDMI = 6,
 175         INTEL_OUTPUT_DP = 7,
 176         INTEL_OUTPUT_EDP = 8,
 177         INTEL_OUTPUT_DSI = 9,
 178         INTEL_OUTPUT_DDI = 10,
 179         INTEL_OUTPUT_DP_MST = 11,
 180 };
 181
 182 #define INTEL_DVO_CHIP_NONE 0
 183 #define INTEL_DVO_CHIP_LVDS 1
 184 #define INTEL_DVO_CHIP_TMDS 2
 185 #define INTEL_DVO_CHIP_TVOUT 4
 186
 187 #define INTEL_DSI_VIDEO_MODE    0
 188 #define INTEL_DSI_COMMAND_MODE  1
 189
 190 struct intel_framebuffer {
 191         struct drm_framebuffer base;
 192         struct intel_rotation_info rot_info;
 193
 194         /* for each plane in the normal GTT view */
 195         struct {
 196                 unsigned int x, y;
 197         } normal[2];
 198         /* for each plane in the rotated GTT view */
 199         struct {
 200                 unsigned int x, y;
 201                 unsigned int pitch; /* pixels */
 202         } rotated[2];
 203 };
 204
 205 struct intel_fbdev {
 206         struct drm_fb_helper helper;
 207         struct intel_framebuffer *fb;
 208         struct i915_vma *vma;
 209         unsigned long vma_flags;
 210         async_cookie_t cookie;
 211         int preferred_bpp;
 212 };
 213
 214 struct intel_encoder {
 215         struct drm_encoder base;
 216
 217         enum intel_output_type type;
 218         enum port port;
 219         unsigned int cloneable;
 220         bool (*hotplug)(struct intel_encoder *encoder,
 221                         struct intel_connector *connector);
 222         enum intel_output_type (*compute_output_type)(struct intel_encoder *,
 223                                                       struct intel_crtc_state *,
 224                                                       struct drm_connector_state *);
 225         bool (*compute_config)(struct intel_encoder *,
 226                                struct intel_crtc_state *,
 227                                struct drm_connector_state *);
 228         void (*pre_pll_enable)(struct intel_encoder *,
 229                                const struct intel_crtc_state *,
 230                                const struct drm_connector_state *);
 231         void (*pre_enable)(struct intel_encoder *,
 232                            const struct intel_crtc_state *,
 233                            const struct drm_connector_state *);
 234         void (*enable)(struct intel_encoder *,
 235                        const struct intel_crtc_state *,
 236                        const struct drm_connector_state *);
 237         void (*disable)(struct intel_encoder *,
 238                         const struct intel_crtc_state *,
 239                         const struct drm_connector_state *);
 240         void (*post_disable)(struct intel_encoder *,
 241                              const struct intel_crtc_state *,
 242                              const struct drm_connector_state *);
 243         void (*post_pll_disable)(struct intel_encoder *,
 244                                  const struct intel_crtc_state *,
 245                                  const struct drm_connector_state *);
 246         /* Read out the current hw state of this connector, returning true if
 247          * the encoder is active. If the encoder is enabled it also set the pipe
 248          * it is connected to in the pipe parameter. */
 249         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 250         /* Reconstructs the equivalent mode flags for the current hardware
 251          * state. This must be called _after_ display->get_pipe_config has
 252          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 253          * be set correctly before calling this function. */
 254         void (*get_config)(struct intel_encoder *,
 255                            struct intel_crtc_state *pipe_config);
 256         /* Returns a mask of power domains that need to be referenced as part
 257          * of the hardware state readout code. */
 258         u64 (*get_power_domains)(struct intel_encoder *encoder,
 259                                  struct intel_crtc_state *crtc_state);
 260         /*
 261          * Called during system suspend after all pending requests for the
 262          * encoder are flushed (for example for DP AUX transactions) and
 263          * device interrupts are disabled.
 264          */
 265         void (*suspend)(struct intel_encoder *);
 266         int crtc_mask;
 267         enum hpd_pin hpd_pin;
 268         enum intel_display_power_domain power_domain;
 269         /* for communication with audio component; protected by av_mutex */
 270         const struct drm_connector *audio_connector;
 271 };
 272
 273 struct intel_panel {
 274         struct drm_display_mode *fixed_mode;
 275         struct drm_display_mode *downclock_mode;
 276
 277         /* backlight */
 278         struct {
 279                 bool present;
 280                 u32 level;
 281                 u32 min;
 282                 u32 max;
 283                 bool enabled;
 284                 bool combination_mode;  /* gen 2/4 only */
 285                 bool active_low_pwm;
 286                 bool alternate_pwm_increment;   /* lpt+ */
 287
 288                 /* PWM chip */
 289                 bool util_pin_active_low;       /* bxt+ */
 290                 u8 controller;          /* bxt+ only */
 291                 struct pwm_device *pwm;
 292
 293                 struct backlight_device *device;
 294
 295                 /* Connector and platform specific backlight functions */
 296                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 297                 uint32_t (*get)(struct intel_connector *connector);
 298                 void (*set)(const struct drm_connector_state *conn_state, uint32_t level);
 299                 void (*disable)(const struct drm_connector_state *conn_state);
 300                 void (*enable)(const struct intel_crtc_state *crtc_state,
 301                                const struct drm_connector_state *conn_state);
 302                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 303                                       uint32_t hz);
 304                 void (*power)(struct intel_connector *, bool enable);
 305         } backlight;
 306 };
 307
 308 struct intel_digital_port;
 309
 310 /*
 311  * This structure serves as a translation layer between the generic HDCP code
 312  * and the bus-specific code. What that means is that HDCP over HDMI differs
 313  * from HDCP over DP, so to account for these differences, we need to
 314  * communicate with the receiver through this shim.
 315  *
 316  * For completeness, the 2 buses differ in the following ways:
 317  *      - DP AUX vs. DDC
 318  *              HDCP registers on the receiver are set via DP AUX for DP, and
 319  *              they are set via DDC for HDMI.
 320  *      - Receiver register offsets
 321  *              The offsets of the registers are different for DP vs. HDMI
 322  *      - Receiver register masks/offsets
 323  *              For instance, the ready bit for the KSV fifo is in a different
 324  *              place on DP vs HDMI
 325  *      - Receiver register names
 326  *              Seriously. In the DP spec, the 16-bit register containing
 327  *              downstream information is called BINFO, on HDMI it's called
 328  *              BSTATUS. To confuse matters further, DP has a BSTATUS register
 329  *              with a completely different definition.
 330  *      - KSV FIFO
 331  *              On HDMI, the ksv fifo is read all at once, whereas on DP it must
 332  *              be read 3 keys at a time
 333  *      - Aksv output
 334  *              Since Aksv is hidden in hardware, there's different procedures
 335  *              to send it over DP AUX vs DDC
 336  */
 337 struct intel_hdcp_shim {
 338         /* Outputs the transmitter's An and Aksv values to the receiver. */
 339         int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
 340
 341         /* Reads the receiver's key selection vector */
 342         int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
 343
 344         /*
 345          * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
 346          * definitions are the same in the respective specs, but the names are
 347          * different. Call it BSTATUS since that's the name the HDMI spec
 348          * uses and it was there first.
 349          */
 350         int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
 351                             u8 *bstatus);
 352
 353         /* Determines whether a repeater is present downstream */
 354         int (*repeater_present)(struct intel_digital_port *intel_dig_port,
 355                                 bool *repeater_present);
 356
 357         /* Reads the receiver's Ri' value */
 358         int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
 359
 360         /* Determines if the receiver's KSV FIFO is ready for consumption */
 361         int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
 362                               bool *ksv_ready);
 363
 364         /* Reads the ksv fifo for num_downstream devices */
 365         int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
 366                              int num_downstream, u8 *ksv_fifo);
 367
 368         /* Reads a 32-bit part of V' from the receiver */
 369         int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
 370                                  int i, u32 *part);
 371
 372         /* Enables HDCP signalling on the port */
 373         int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
 374                                  bool enable);
 375
 376         /* Ensures the link is still protected */
 377         bool (*check_link)(struct intel_digital_port *intel_dig_port);
 378
 379         /* Detects panel's hdcp capability. This is optional for HDMI. */
 380         int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
 381                             bool *hdcp_capable);
 382 };
 383
 384 struct intel_connector {
 385         struct drm_connector base;
 386         /*
 387          * The fixed encoder this connector is connected to.
 388          */
 389         struct intel_encoder *encoder;
 390
 391         /* ACPI device id for ACPI and driver cooperation */
 392         u32 acpi_device_id;
 393
 394         /* Reads out the current hw, returning true if the connector is enabled
 395          * and active (i.e. dpms ON state). */
 396         bool (*get_hw_state)(struct intel_connector *);
 397
 398         /* Panel info for eDP and LVDS */
 399         struct intel_panel panel;
 400
 401         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 402         struct edid *edid;
 403         struct edid *detect_edid;
 404
 405         /* since POLL and HPD connectors may use the same HPD line keep the native
 406            state of connector->polled in case hotplug storm detection changes it */
 407         u8 polled;
 408
 409         void *port; /* store this opaque as its illegal to dereference it */
 410
 411         struct intel_dp *mst_port;
 412
 413         /* Work struct to schedule a uevent on link train failure */
 414         struct work_struct modeset_retry_work;
 415
 416         const struct intel_hdcp_shim *hdcp_shim;
 417         struct mutex hdcp_mutex;
 418         uint64_t hdcp_value; /* protected by hdcp_mutex */
 419         struct delayed_work hdcp_check_work;
 420         struct work_struct hdcp_prop_work;
 421 };
 422
 423 struct intel_digital_connector_state {
 424         struct drm_connector_state base;
 425
 426         enum hdmi_force_audio force_audio;
 427         int broadcast_rgb;
 428 };
 429
 430 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
 431
 432 struct dpll {
 433         /* given values */
 434         int n;
 435         int m1, m2;
 436         int p1, p2;
 437         /* derived values */
 438         int     dot;
 439         int     vco;
 440         int     m;
 441         int     p;
 442 };
 443
 444 struct intel_atomic_state {
 445         struct drm_atomic_state base;
 446
 447         struct {
 448                 /*
 449                  * Logical state of cdclk (used for all scaling, watermark,
 450                  * etc. calculations and checks). This is computed as if all
 451                  * enabled crtcs were active.
 452                  */
 453                 struct intel_cdclk_state logical;
 454
 455                 /*
 456                  * Actual state of cdclk, can be different from the logical
 457                  * state only when all crtc's are DPMS off.
 458                  */
 459                 struct intel_cdclk_state actual;
 460         } cdclk;
 461
 462         bool dpll_set, modeset;
 463
 464         /*
 465          * Does this transaction change the pipes that are active?  This mask
 466          * tracks which CRTC's have changed their active state at the end of
 467          * the transaction (not counting the temporary disable during modesets).
 468          * This mask should only be non-zero when intel_state->modeset is true,
 469          * but the converse is not necessarily true; simply changing a mode may
 470          * not flip the final active status of any CRTC's
 471          */
 472         unsigned int active_pipe_changes;
 473
 474         unsigned int active_crtcs;
 475         /* minimum acceptable cdclk for each pipe */
 476         int min_cdclk[I915_MAX_PIPES];
 477         /* minimum acceptable voltage level for each pipe */
 478         u8 min_voltage_level[I915_MAX_PIPES];
 479
 480         struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
 481
 482         /*
 483          * Current watermarks can't be trusted during hardware readout, so
 484          * don't bother calculating intermediate watermarks.
 485          */
 486         bool skip_intermediate_wm;
 487
 488         bool rps_interactive;
 489
 490         /* Gen9+ only */
 491         struct skl_ddb_values wm_results;
 492
 493         struct i915_sw_fence commit_ready;
 494
 495         struct llist_node freed;
 496 };
 497
 498 struct intel_plane_state {
 499         struct drm_plane_state base;
 500         struct i915_ggtt_view view;
 501         struct i915_vma *vma;
 502         unsigned long flags;
 503 #define PLANE_HAS_FENCE BIT(0)
 504
 505         struct {
 506                 u32 offset;
 507                 /*
 508                  * Plane stride in:
 509                  * bytes for 0/180 degree rotation
 510                  * pixels for 90/270 degree rotation
 511                  */
 512                 u32 stride;
 513                 int x, y;
 514         } color_plane[2];
 515
 516         /* plane control register */
 517         u32 ctl;
 518
 519         /* plane color control register */
 520         u32 color_ctl;
 521
 522         /*
 523          * scaler_id
 524          *    = -1 : not using a scaler
 525          *    >=  0 : using a scalers
 526          *
 527          * plane requiring a scaler:
 528          *   - During check_plane, its bit is set in
 529          *     crtc_state->scaler_state.scaler_users by calling helper function
 530          *     update_scaler_plane.
 531          *   - scaler_id indicates the scaler it got assigned.
 532          *
 533          * plane doesn't require a scaler:
 534          *   - this can happen when scaling is no more required or plane simply
 535          *     got disabled.
 536          *   - During check_plane, corresponding bit is reset in
 537          *     crtc_state->scaler_state.scaler_users by calling helper function
 538          *     update_scaler_plane.
 539          */
 540         int scaler_id;
 541
 542         struct drm_intel_sprite_colorkey ckey;
 543 };
 544
 545 struct intel_initial_plane_config {
 546         struct intel_framebuffer *fb;
 547         unsigned int tiling;
 548         int size;
 549         u32 base;
 550         u8 rotation;
 551 };
 552
 553 #define SKL_MIN_SRC_W 8
 554 #define SKL_MAX_SRC_W 4096
 555 #define SKL_MIN_SRC_H 8
 556 #define SKL_MAX_SRC_H 4096
 557 #define SKL_MIN_DST_W 8
 558 #define SKL_MAX_DST_W 4096
 559 #define SKL_MIN_DST_H 8
 560 #define SKL_MAX_DST_H 4096
 561 #define ICL_MAX_SRC_W 5120
 562 #define ICL_MAX_SRC_H 4096
 563 #define ICL_MAX_DST_W 5120
 564 #define ICL_MAX_DST_H 4096
 565 #define SKL_MIN_YUV_420_SRC_W 16
 566 #define SKL_MIN_YUV_420_SRC_H 16
 567
 568 struct intel_scaler {
 569         int in_use;
 570         uint32_t mode;
 571 };
 572
 573 struct intel_crtc_scaler_state {
 574 #define SKL_NUM_SCALERS 2
 575         struct intel_scaler scalers[SKL_NUM_SCALERS];
 576
 577         /*
 578          * scaler_users: keeps track of users requesting scalers on this crtc.
 579          *
 580          *     If a bit is set, a user is using a scaler.
 581          *     Here user can be a plane or crtc as defined below:
 582          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 583          *       bit 31    - crtc
 584          *
 585          * Instead of creating a new index to cover planes and crtc, using
 586          * existing drm_plane_index for planes which is well less than 31
 587          * planes and bit 31 for crtc. This should be fine to cover all
 588          * our platforms.
 589          *
 590          * intel_atomic_setup_scalers will setup available scalers to users
 591          * requesting scalers. It will gracefully fail if request exceeds
 592          * avilability.
 593          */
 594 #define SKL_CRTC_INDEX 31
 595         unsigned scaler_users;
 596
 597         /* scaler used by crtc for panel fitting purpose */
 598         int scaler_id;
 599 };
 600
 601 /* drm_mode->private_flags */
 602 #define I915_MODE_FLAG_INHERITED 1
 603 /* Flag to get scanline using frame time stamps */
 604 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
 605
 606 struct intel_pipe_wm {
 607         struct intel_wm_level wm[5];
 608         uint32_t linetime;
 609         bool fbc_wm_enabled;
 610         bool pipe_enabled;
 611         bool sprites_enabled;
 612         bool sprites_scaled;
 613 };
 614
 615 struct skl_plane_wm {
 616         struct skl_wm_level wm[8];
 617         struct skl_wm_level uv_wm[8];
 618         struct skl_wm_level trans_wm;
 619         bool is_planar;
 620 };
 621
 622 struct skl_pipe_wm {
 623         struct skl_plane_wm planes[I915_MAX_PLANES];
 624         uint32_t linetime;
 625 };
 626
 627 enum vlv_wm_level {
 628         VLV_WM_LEVEL_PM2,
 629         VLV_WM_LEVEL_PM5,
 630         VLV_WM_LEVEL_DDR_DVFS,
 631         NUM_VLV_WM_LEVELS,
 632 };
 633
 634 struct vlv_wm_state {
 635         struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
 636         struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
 637         uint8_t num_levels;
 638         bool cxsr;
 639 };
 640
 641 struct vlv_fifo_state {
 642         u16 plane[I915_MAX_PLANES];
 643 };
 644
 645 enum g4x_wm_level {
 646         G4X_WM_LEVEL_NORMAL,
 647         G4X_WM_LEVEL_SR,
 648         G4X_WM_LEVEL_HPLL,
 649         NUM_G4X_WM_LEVELS,
 650 };
 651
 652 struct g4x_wm_state {
 653         struct g4x_pipe_wm wm;
 654         struct g4x_sr_wm sr;
 655         struct g4x_sr_wm hpll;
 656         bool cxsr;
 657         bool hpll_en;
 658         bool fbc_en;
 659 };
 660
 661 struct intel_crtc_wm_state {
 662         union {
 663                 struct {
 664                         /*
 665                          * Intermediate watermarks; these can be
 666                          * programmed immediately since they satisfy
 667                          * both the current configuration we're
 668                          * switching away from and the new
 669                          * configuration we're switching to.
 670                          */
 671                         struct intel_pipe_wm intermediate;
 672
 673                         /*
 674                          * Optimal watermarks, programmed post-vblank
 675                          * when this state is committed.
 676                          */
 677                         struct intel_pipe_wm optimal;
 678                 } ilk;
 679
 680                 struct {
 681                         /* gen9+ only needs 1-step wm programming */
 682                         struct skl_pipe_wm optimal;
 683                         struct skl_ddb_entry ddb;
 684                 } skl;
 685
 686                 struct {
 687                         /* "raw" watermarks (not inverted) */
 688                         struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
 689                         /* intermediate watermarks (inverted) */
 690                         struct vlv_wm_state intermediate;
 691                         /* optimal watermarks (inverted) */
 692                         struct vlv_wm_state optimal;
 693                         /* display FIFO split */
 694                         struct vlv_fifo_state fifo_state;
 695                 } vlv;
 696
 697                 struct {
 698                         /* "raw" watermarks */
 699                         struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
 700                         /* intermediate watermarks */
 701                         struct g4x_wm_state intermediate;
 702                         /* optimal watermarks */
 703                         struct g4x_wm_state optimal;
 704                 } g4x;
 705         };
 706
 707         /*
 708          * Platforms with two-step watermark programming will need to
 709          * update watermark programming post-vblank to switch from the
 710          * safe intermediate watermarks to the optimal final
 711          * watermarks.
 712          */
 713         bool need_postvbl_update;
 714 };
 715
 716 struct intel_crtc_state {
 717         struct drm_crtc_state base;
 718
 719         /**
 720          * quirks - bitfield with hw state readout quirks
 721          *
 722          * For various reasons the hw state readout code might not be able to
 723          * completely faithfully read out the current state. These cases are
 724          * tracked with quirk flags so that fastboot and state checker can act
 725          * accordingly.
 726          */
 727 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 728         unsigned long quirks;
 729
 730         unsigned fb_bits; /* framebuffers to flip */
 731         bool update_pipe; /* can a fast modeset be performed? */
 732         bool disable_cxsr;
 733         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 734         bool fb_changed; /* fb on any of the planes is changed */
 735         bool fifo_changed; /* FIFO split is changed */
 736
 737         /* Pipe source size (ie. panel fitter input size)
 738          * All planes will be positioned inside this space,
 739          * and get clipped at the edges. */
 740         int pipe_src_w, pipe_src_h;
 741
 742         /*
 743          * Pipe pixel rate, adjusted for
 744          * panel fitter/pipe scaler downscaling.
 745          */
 746         unsigned int pixel_rate;
 747
 748         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 749          * between pch encoders and cpu encoders. */
 750         bool has_pch_encoder;
 751
 752         /* Are we sending infoframes on the attached port */
 753         bool has_infoframe;
 754
 755         /* CPU Transcoder for the pipe. Currently this can only differ from the
 756          * pipe on Haswell and later (where we have a special eDP transcoder)
 757          * and Broxton (where we have special DSI transcoders). */
 758         enum transcoder cpu_transcoder;
 759
 760         /*
 761          * Use reduced/limited/broadcast rbg range, compressing from the full
 762          * range fed into the crtcs.
 763          */
 764         bool limited_color_range;
 765
 766         /* Bitmask of encoder types (enum intel_output_type)
 767          * driven by the pipe.
 768          */
 769         unsigned int output_types;
 770
 771         /* Whether we should send NULL infoframes. Required for audio. */
 772         bool has_hdmi_sink;
 773
 774         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 775          * has_dp_encoder is set. */
 776         bool has_audio;
 777
 778         /*
 779          * Enable dithering, used when the selected pipe bpp doesn't match the
 780          * plane bpp.
 781          */
 782         bool dither;
 783
 784         /*
 785          * Dither gets enabled for 18bpp which causes CRC mismatch errors for
 786          * compliance video pattern tests.
 787          * Disable dither only if it is a compliance test request for
 788          * 18bpp.
 789          */
 790         bool dither_force_disable;
 791
 792         /* Controls for the clock computation, to override various stages. */
 793         bool clock_set;
 794
 795         /* SDVO TV has a bunch of special case. To make multifunction encoders
 796          * work correctly, we need to track this at runtime.*/
 797         bool sdvo_tv_clock;
 798
 799         /*
 800          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 801          * required. This is set in the 2nd loop of calling encoder's
 802          * ->compute_config if the first pick doesn't work out.
 803          */
 804         bool bw_constrained;
 805
 806         /* Settings for the intel dpll used on pretty much everything but
 807          * haswell. */
 808         struct dpll dpll;
 809
 810         /* Selected dpll when shared or NULL. */
 811         struct intel_shared_dpll *shared_dpll;
 812
 813         /* Actual register state of the dpll, for shared dpll cross-checking. */
 814         struct intel_dpll_hw_state dpll_hw_state;
 815
 816         /* DSI PLL registers */
 817         struct {
 818                 u32 ctrl, div;
 819         } dsi_pll;
 820
 821         int pipe_bpp;
 822         struct intel_link_m_n dp_m_n;
 823
 824         /* m2_n2 for eDP downclock */
 825         struct intel_link_m_n dp_m2_n2;
 826         bool has_drrs;
 827
 828         bool has_psr;
 829         bool has_psr2;
 830
 831         /*
 832          * Frequence the dpll for the port should run at. Differs from the
 833          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 834          * already multiplied by pixel_multiplier.
 835          */
 836         int port_clock;
 837
 838         /* Used by SDVO (and if we ever fix it, HDMI). */
 839         unsigned pixel_multiplier;
 840
 841         uint8_t lane_count;
 842
 843         /*
 844          * Used by platforms having DP/HDMI PHY with programmable lane
 845          * latency optimization.
 846          */
 847         uint8_t lane_lat_optim_mask;
 848
 849         /* minimum acceptable voltage level */
 850         u8 min_voltage_level;
 851
 852         /* Panel fitter controls for gen2-gen4 + VLV */
 853         struct {
 854                 u32 control;
 855                 u32 pgm_ratios;
 856                 u32 lvds_border_bits;
 857         } gmch_pfit;
 858
 859         /* Panel fitter placement and size for Ironlake+ */
 860         struct {
 861                 u32 pos;
 862                 u32 size;
 863                 bool enabled;
 864                 bool force_thru;
 865         } pch_pfit;
 866
 867         /* FDI configuration, only valid if has_pch_encoder is set. */
 868         int fdi_lanes;
 869         struct intel_link_m_n fdi_m_n;
 870
 871         bool ips_enabled;
 872         bool ips_force_disable;
 873
 874         bool enable_fbc;
 875
 876         bool double_wide;
 877
 878         int pbn;
 879
 880         struct intel_crtc_scaler_state scaler_state;
 881
 882         /* w/a for waiting 2 vblanks during crtc enable */
 883         enum pipe hsw_workaround_pipe;
 884
 885         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 886         bool disable_lp_wm;
 887
 888         struct intel_crtc_wm_state wm;
 889
 890         /* Gamma mode programmed on the pipe */
 891         uint32_t gamma_mode;
 892
 893         /* bitmask of visible planes (enum plane_id) */
 894         u8 active_planes;
 895         u8 nv12_planes;
 896
 897         /* HDMI scrambling status */
 898         bool hdmi_scrambling;
 899
 900         /* HDMI High TMDS char rate ratio */
 901         bool hdmi_high_tmds_clock_ratio;
 902
 903         /* output format is YCBCR 4:2:0 */
 904         bool ycbcr420;
 905 };
 906
 907 struct intel_crtc {
 908         struct drm_crtc base;
 909         enum pipe pipe;
 910         /*
 911          * Whether the crtc and the connected output pipeline is active. Implies
 912          * that crtc->enabled is set, i.e. the current mode configuration has
 913          * some outputs connected to this crtc.
 914          */
 915         bool active;
 916         u8 plane_ids_mask;
 917         unsigned long long enabled_power_domains;
 918         struct intel_overlay *overlay;
 919
 920         struct intel_crtc_state *config;
 921
 922         /* global reset count when the last flip was submitted */
 923         unsigned int reset_count;
 924
 925         /* Access to these should be protected by dev_priv->irq_lock. */
 926         bool cpu_fifo_underrun_disabled;
 927         bool pch_fifo_underrun_disabled;
 928
 929         /* per-pipe watermark state */
 930         struct {
 931                 /* watermarks currently being used  */
 932                 union {
 933                         struct intel_pipe_wm ilk;
 934                         struct vlv_wm_state vlv;
 935                         struct g4x_wm_state g4x;
 936                 } active;
 937         } wm;
 938
 939         int scanline_offset;
 940
 941         struct {
 942                 unsigned start_vbl_count;
 943                 ktime_t start_vbl_time;
 944                 int min_vbl, max_vbl;
 945                 int scanline_start;
 946         } debug;
 947
 948         /* scalers available on this crtc */
 949         int num_scalers;
 950 };
 951
 952 struct intel_plane {
 953         struct drm_plane base;
 954         enum i9xx_plane_id i9xx_plane;
 955         enum plane_id id;
 956         enum pipe pipe;
 957         bool has_fbc;
 958         bool has_ccs;
 959         uint32_t frontbuffer_bit;
 960
 961         struct {
 962                 u32 base, cntl, size;
 963         } cursor;
 964
 965         /*
 966          * NOTE: Do not place new plane state fields here (e.g., when adding
 967          * new plane properties).  New runtime state should now be placed in
 968          * the intel_plane_state structure and accessed via plane_state.
 969          */
 970
 971         unsigned int (*max_stride)(struct intel_plane *plane,
 972                                    u32 pixel_format, u64 modifier,
 973                                    unsigned int rotation);
 974         void (*update_plane)(struct intel_plane *plane,
 975                              const struct intel_crtc_state *crtc_state,
 976                              const struct intel_plane_state *plane_state);
 977         void (*disable_plane)(struct intel_plane *plane,
 978                               struct intel_crtc *crtc);
 979         bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
 980         int (*check_plane)(struct intel_crtc_state *crtc_state,
 981                            struct intel_plane_state *plane_state);
 982 };
 983
 984 struct intel_watermark_params {
 985         u16 fifo_size;
 986         u16 max_wm;
 987         u8 default_wm;
 988         u8 guard_size;
 989         u8 cacheline_size;
 990 };
 991
 992 struct cxsr_latency {
 993         bool is_desktop : 1;
 994         bool is_ddr3 : 1;
 995         u16 fsb_freq;
 996         u16 mem_freq;
 997         u16 display_sr;
 998         u16 display_hpll_disable;
 999         u16 cursor_sr;
1000         u16 cursor_hpll_disable;
1001 };
1002
1003 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1004 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1005 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
1006 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1007 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1008 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1009 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1010 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
1011 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1012
1013 struct intel_hdmi {
1014         i915_reg_t hdmi_reg;
1015         int ddc_bus;
1016         struct {
1017                 enum drm_dp_dual_mode_type type;
1018                 int max_tmds_clock;
1019         } dp_dual_mode;
1020         bool has_hdmi_sink;
1021         bool has_audio;
1022         bool rgb_quant_range_selectable;
1023         struct intel_connector *attached_connector;
1024         struct cec_notifier *cec_notifier;
1025 };
1026
1027 struct intel_dp_mst_encoder;
1028 #define DP_MAX_DOWNSTREAM_PORTS         0x10
1029
1030 /*
1031  * enum link_m_n_set:
1032  *      When platform provides two set of M_N registers for dp, we can
1033  *      program them and switch between them incase of DRRS.
1034  *      But When only one such register is provided, we have to program the
1035  *      required divider value on that registers itself based on the DRRS state.
1036  *
1037  * M1_N1        : Program dp_m_n on M1_N1 registers
1038  *                        dp_m2_n2 on M2_N2 registers (If supported)
1039  *
1040  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
1041  *                        M2_N2 registers are not supported
1042  */
1043
1044 enum link_m_n_set {
1045         /* Sets the m1_n1 and m2_n2 */
1046         M1_N1 = 0,
1047         M2_N2
1048 };
1049
1050 struct intel_dp_compliance_data {
1051         unsigned long edid;
1052         uint8_t video_pattern;
1053         uint16_t hdisplay, vdisplay;
1054         uint8_t bpc;
1055 };
1056
1057 struct intel_dp_compliance {
1058         unsigned long test_type;
1059         struct intel_dp_compliance_data test_data;
1060         bool test_active;
1061         int test_link_rate;
1062         u8 test_lane_count;
1063 };
1064
1065 struct intel_dp {
1066         i915_reg_t output_reg;
1067         uint32_t DP;
1068         int link_rate;
1069         uint8_t lane_count;
1070         uint8_t sink_count;
1071         bool link_mst;
1072         bool link_trained;
1073         bool has_audio;
1074         bool detect_done;
1075         bool reset_link_params;
1076         enum aux_ch aux_ch;
1077         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
1078         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1079         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1080         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1081         /* source rates */
1082         int num_source_rates;
1083         const int *source_rates;
1084         /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1085         int num_sink_rates;
1086         int sink_rates[DP_MAX_SUPPORTED_RATES];
1087         bool use_rate_select;
1088         /* intersection of source and sink rates */
1089         int num_common_rates;
1090         int common_rates[DP_MAX_SUPPORTED_RATES];
1091         /* Max lane count for the current link */
1092         int max_link_lane_count;
1093         /* Max rate for the current link */
1094         int max_link_rate;
1095         /* sink or branch descriptor */
1096         struct drm_dp_desc desc;
1097         struct drm_dp_aux aux;
1098         enum intel_display_power_domain aux_power_domain;
1099         uint8_t train_set[4];
1100         int panel_power_up_delay;
1101         int panel_power_down_delay;
1102         int panel_power_cycle_delay;
1103         int backlight_on_delay;
1104         int backlight_off_delay;
1105         struct delayed_work panel_vdd_work;
1106         bool want_panel_vdd;
1107         unsigned long last_power_on;
1108         unsigned long last_backlight_off;
1109         ktime_t panel_power_off_time;
1110
1111         struct notifier_block edp_notifier;
1112
1113         /*
1114          * Pipe whose power sequencer is currently locked into
1115          * this port. Only relevant on VLV/CHV.
1116          */
1117         enum pipe pps_pipe;
1118         /*
1119          * Pipe currently driving the port. Used for preventing
1120          * the use of the PPS for any pipe currentrly driving
1121          * external DP as that will mess things up on VLV.
1122          */
1123         enum pipe active_pipe;
1124         /*
1125          * Set if the sequencer may be reset due to a power transition,
1126          * requiring a reinitialization. Only relevant on BXT.
1127          */
1128         bool pps_reset;
1129         struct edp_power_seq pps_delays;
1130
1131         bool can_mst; /* this port supports mst */
1132         bool is_mst;
1133         int active_mst_links;
1134         /* connector directly attached - won't be use for modeset in mst world */
1135         struct intel_connector *attached_connector;
1136
1137         /* mst connector list */
1138         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1139         struct drm_dp_mst_topology_mgr mst_mgr;
1140
1141         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1142         /*
1143          * This function returns the value we have to program the AUX_CTL
1144          * register with to kick off an AUX transaction.
1145          */
1146         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
1147                                      int send_bytes,
1148                                      uint32_t aux_clock_divider);
1149
1150         i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1151         i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1152
1153         /* This is called before a link training is starterd */
1154         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1155
1156         /* Displayport compliance testing */
1157         struct intel_dp_compliance compliance;
1158 };
1159
1160 struct intel_lspcon {
1161         bool active;
1162         enum drm_lspcon_mode mode;
1163 };
1164
1165 struct intel_digital_port {
1166         struct intel_encoder base;
1167         u32 saved_port_bits;
1168         struct intel_dp dp;
1169         struct intel_hdmi hdmi;
1170         struct intel_lspcon lspcon;
1171         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1172         bool release_cl2_override;
1173         uint8_t max_lanes;
1174         enum intel_display_power_domain ddi_io_power_domain;
1175         enum tc_port_type tc_type;
1176
1177         void (*write_infoframe)(struct drm_encoder *encoder,
1178                                 const struct intel_crtc_state *crtc_state,
1179                                 unsigned int type,
1180                                 const void *frame, ssize_t len);
1181         void (*set_infoframes)(struct drm_encoder *encoder,
1182                                bool enable,
1183                                const struct intel_crtc_state *crtc_state,
1184                                const struct drm_connector_state *conn_state);
1185         bool (*infoframe_enabled)(struct drm_encoder *encoder,
1186                                   const struct intel_crtc_state *pipe_config);
1187 };
1188
1189 struct intel_dp_mst_encoder {
1190         struct intel_encoder base;
1191         enum pipe pipe;
1192         struct intel_digital_port *primary;
1193         struct intel_connector *connector;
1194 };
1195
1196 static inline enum dpio_channel
1197 vlv_dport_to_channel(struct intel_digital_port *dport)
1198 {
1199         switch (dport->base.port) {
1200         case PORT_B:
1201         case PORT_D:
1202                 return DPIO_CH0;
1203         case PORT_C:
1204                 return DPIO_CH1;
1205         default:
1206                 BUG();
1207         }
1208 }
1209
1210 static inline enum dpio_phy
1211 vlv_dport_to_phy(struct intel_digital_port *dport)
1212 {
1213         switch (dport->base.port) {
1214         case PORT_B:
1215         case PORT_C:
1216                 return DPIO_PHY0;
1217         case PORT_D:
1218                 return DPIO_PHY1;
1219         default:
1220                 BUG();
1221         }
1222 }
1223
1224 static inline enum dpio_channel
1225 vlv_pipe_to_channel(enum pipe pipe)
1226 {
1227         switch (pipe) {
1228         case PIPE_A:
1229         case PIPE_C:
1230                 return DPIO_CH0;
1231         case PIPE_B:
1232                 return DPIO_CH1;
1233         default:
1234                 BUG();
1235         }
1236 }
1237
1238 static inline struct intel_crtc *
1239 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1240 {
1241         return dev_priv->pipe_to_crtc_mapping[pipe];
1242 }
1243
1244 static inline struct intel_crtc *
1245 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1246 {
1247         return dev_priv->plane_to_crtc_mapping[plane];
1248 }
1249
1250 struct intel_load_detect_pipe {
1251         struct drm_atomic_state *restore_state;
1252 };
1253
1254 static inline struct intel_encoder *
1255 intel_attached_encoder(struct drm_connector *connector)
1256 {
1257         return to_intel_connector(connector)->encoder;
1258 }
1259
1260 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1261 {
1262         switch (encoder->type) {
1263         case INTEL_OUTPUT_DDI:
1264         case INTEL_OUTPUT_DP:
1265         case INTEL_OUTPUT_EDP:
1266         case INTEL_OUTPUT_HDMI:
1267                 return true;
1268         default:
1269                 return false;
1270         }
1271 }
1272
1273 static inline struct intel_digital_port *
1274 enc_to_dig_port(struct drm_encoder *encoder)
1275 {
1276         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1277
1278         if (intel_encoder_is_dig_port(intel_encoder))
1279                 return container_of(encoder, struct intel_digital_port,
1280                                     base.base);
1281         else
1282                 return NULL;
1283 }
1284
1285 static inline struct intel_dp_mst_encoder *
1286 enc_to_mst(struct drm_encoder *encoder)
1287 {
1288         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1289 }
1290
1291 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1292 {
1293         return &enc_to_dig_port(encoder)->dp;
1294 }
1295
1296 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1297 {
1298         switch (encoder->type) {
1299         case INTEL_OUTPUT_DP:
1300         case INTEL_OUTPUT_EDP:
1301                 return true;
1302         case INTEL_OUTPUT_DDI:
1303                 /* Skip pure HDMI/DVI DDI encoders */
1304                 return i915_mmio_reg_valid(enc_to_intel_dp(&encoder->base)->output_reg);
1305         default:
1306                 return false;
1307         }
1308 }
1309
1310 static inline struct intel_digital_port *
1311 dp_to_dig_port(struct intel_dp *intel_dp)
1312 {
1313         return container_of(intel_dp, struct intel_digital_port, dp);
1314 }
1315
1316 static inline struct intel_lspcon *
1317 dp_to_lspcon(struct intel_dp *intel_dp)
1318 {
1319         return &dp_to_dig_port(intel_dp)->lspcon;
1320 }
1321
1322 static inline struct drm_i915_private *
1323 dp_to_i915(struct intel_dp *intel_dp)
1324 {
1325         return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
1326 }
1327
1328 static inline struct intel_digital_port *
1329 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1330 {
1331         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1332 }
1333
1334 static inline struct intel_plane_state *
1335 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1336                                  struct intel_plane *plane)
1337 {
1338         return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1339                                                                    &plane->base));
1340 }
1341
1342 static inline struct intel_crtc_state *
1343 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1344                                 struct intel_crtc *crtc)
1345 {
1346         return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1347                                                                  &crtc->base));
1348 }
1349
1350 static inline struct intel_crtc_state *
1351 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1352                                 struct intel_crtc *crtc)
1353 {
1354         return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1355                                                                  &crtc->base));
1356 }
1357
1358 /* intel_fifo_underrun.c */
1359 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1360                                            enum pipe pipe, bool enable);
1361 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1362                                            enum pipe pch_transcoder,
1363                                            bool enable);
1364 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1365                                          enum pipe pipe);
1366 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1367                                          enum pipe pch_transcoder);
1368 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1369 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1370
1371 /* i915_irq.c */
1372 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1373 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1374 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1375 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1376 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1377 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1378 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1379 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1380
1381 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1382                                             u32 mask)
1383 {
1384         return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
1385 }
1386
1387 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1388 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1389 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1390 {
1391         /*
1392          * We only use drm_irq_uninstall() at unload and VT switch, so
1393          * this is the only thing we need to check.
1394          */
1395         return dev_priv->runtime_pm.irqs_enabled;
1396 }
1397
1398 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1399 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1400                                      u8 pipe_mask);
1401 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1402                                      u8 pipe_mask);
1403 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1404 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1405 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1406
1407 /* intel_crt.c */
1408 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
1409                             i915_reg_t adpa_reg, enum pipe *pipe);
1410 void intel_crt_init(struct drm_i915_private *dev_priv);
1411 void intel_crt_reset(struct drm_encoder *encoder);
1412
1413 /* intel_ddi.c */
1414 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1415                                 const struct intel_crtc_state *old_crtc_state,
1416                                 const struct drm_connector_state *old_conn_state);
1417 void hsw_fdi_link_train(struct intel_crtc *crtc,
1418                         const struct intel_crtc_state *crtc_state);
1419 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1420 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1421 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1422 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state);
1423 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1424 void intel_ddi_disable_pipe_clock(const  struct intel_crtc_state *crtc_state);
1425 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1426 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1427 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1428 void intel_ddi_get_config(struct intel_encoder *encoder,
1429                           struct intel_crtc_state *pipe_config);
1430
1431 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1432                                     bool state);
1433 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
1434                                          struct intel_crtc_state *crtc_state);
1435 u32 bxt_signal_levels(struct intel_dp *intel_dp);
1436 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1437 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1438 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,
1439                                  u8 voltage_swing);
1440 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1441                                      bool enable);
1442 void icl_map_plls_to_ports(struct drm_crtc *crtc,
1443                            struct intel_crtc_state *crtc_state,
1444                            struct drm_atomic_state *old_state);
1445 void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
1446                              struct intel_crtc_state *crtc_state,
1447                              struct drm_atomic_state *old_state);
1448
1449 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1450                                    int color_plane, unsigned int height);
1451
1452 /* intel_audio.c */
1453 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1454 void intel_audio_codec_enable(struct intel_encoder *encoder,
1455                               const struct intel_crtc_state *crtc_state,
1456                               const struct drm_connector_state *conn_state);
1457 void intel_audio_codec_disable(struct intel_encoder *encoder,
1458                                const struct intel_crtc_state *old_crtc_state,
1459                                const struct drm_connector_state *old_conn_state);
1460 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1461 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1462 void intel_audio_init(struct drm_i915_private *dev_priv);
1463 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1464
1465 /* intel_cdclk.c */
1466 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
1467 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1468 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1469 void cnl_init_cdclk(struct drm_i915_private *dev_priv);
1470 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
1471 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1472 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1473 void icl_init_cdclk(struct drm_i915_private *dev_priv);
1474 void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
1475 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1476 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1477 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1478 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1479 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
1480                                const struct intel_cdclk_state *b);
1481 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
1482                          const struct intel_cdclk_state *b);
1483 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1484                      const struct intel_cdclk_state *cdclk_state);
1485 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
1486                             const char *context);
1487
1488 /* intel_display.c */
1489 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1490 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1491 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1492 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1493 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1494 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1495                       const char *name, u32 reg, int ref_freq);
1496 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1497                            const char *name, u32 reg);
1498 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1499 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1500 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1501 unsigned int intel_fb_xy_to_linear(int x, int y,
1502                                    const struct intel_plane_state *state,
1503                                    int plane);
1504 void intel_add_fb_offsets(int *x, int *y,
1505                           const struct intel_plane_state *state, int plane);
1506 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1507 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1508 void intel_mark_busy(struct drm_i915_private *dev_priv);
1509 void intel_mark_idle(struct drm_i915_private *dev_priv);
1510 int intel_display_suspend(struct drm_device *dev);
1511 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1512 void intel_encoder_destroy(struct drm_encoder *encoder);
1513 int intel_connector_init(struct intel_connector *);
1514 struct intel_connector *intel_connector_alloc(void);
1515 void intel_connector_free(struct intel_connector *connector);
1516 bool intel_connector_get_hw_state(struct intel_connector *connector);
1517 void intel_connector_attach_encoder(struct intel_connector *connector,
1518                                     struct intel_encoder *encoder);
1519 struct drm_display_mode *
1520 intel_encoder_current_mode(struct intel_encoder *encoder);
1521 bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
1522 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
1523 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
1524                               enum port port);
1525
1526 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1527 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
1528                                       struct drm_file *file_priv);
1529 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1530                                              enum pipe pipe);
1531 static inline bool
1532 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1533                     enum intel_output_type type)
1534 {
1535         return crtc_state->output_types & (1 << type);
1536 }
1537 static inline bool
1538 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1539 {
1540         return crtc_state->output_types &
1541                 ((1 << INTEL_OUTPUT_DP) |
1542                  (1 << INTEL_OUTPUT_DP_MST) |
1543                  (1 << INTEL_OUTPUT_EDP));
1544 }
1545 static inline void
1546 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1547 {
1548         drm_wait_one_vblank(&dev_priv->drm, pipe);
1549 }
1550 static inline void
1551 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1552 {
1553         const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1554
1555         if (crtc->active)
1556                 intel_wait_for_vblank(dev_priv, pipe);
1557 }
1558
1559 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1560
1561 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1562 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1563                          struct intel_digital_port *dport,
1564                          unsigned int expected_mask);
1565 int intel_get_load_detect_pipe(struct drm_connector *connector,
1566                                const struct drm_display_mode *mode,
1567                                struct intel_load_detect_pipe *old,
1568                                struct drm_modeset_acquire_ctx *ctx);
1569 void intel_release_load_detect_pipe(struct drm_connector *connector,
1570                                     struct intel_load_detect_pipe *old,
1571                                     struct drm_modeset_acquire_ctx *ctx);
1572 struct i915_vma *
1573 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1574                            const struct i915_ggtt_view *view,
1575                            bool uses_fence,
1576                            unsigned long *out_flags);
1577 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
1578 struct drm_framebuffer *
1579 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1580                          struct drm_mode_fb_cmd2 *mode_cmd);
1581 int intel_prepare_plane_fb(struct drm_plane *plane,
1582                            struct drm_plane_state *new_state);
1583 void intel_cleanup_plane_fb(struct drm_plane *plane,
1584                             struct drm_plane_state *old_state);
1585 int intel_plane_atomic_get_property(struct drm_plane *plane,
1586                                     const struct drm_plane_state *state,
1587                                     struct drm_property *property,
1588                                     uint64_t *val);
1589 int intel_plane_atomic_set_property(struct drm_plane *plane,
1590                                     struct drm_plane_state *state,
1591                                     struct drm_property *property,
1592                                     uint64_t val);
1593 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
1594                                     struct drm_crtc_state *crtc_state,
1595                                     const struct intel_plane_state *old_plane_state,
1596                                     struct drm_plane_state *plane_state);
1597
1598 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1599                                     enum pipe pipe);
1600
1601 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1602                      const struct dpll *dpll);
1603 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1604 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1605
1606 /* modesetting asserts */
1607 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1608                            enum pipe pipe);
1609 void assert_pll(struct drm_i915_private *dev_priv,
1610                 enum pipe pipe, bool state);
1611 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1612 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1613 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1614 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1615 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1616 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1617                        enum pipe pipe, bool state);
1618 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1619 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1620 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1621 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1622 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1623 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1624 void intel_finish_reset(struct drm_i915_private *dev_priv);
1625 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1626 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1627 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1628 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1629 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1630 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1631 unsigned int skl_cdclk_get_vco(unsigned int freq);
1632 void intel_dp_get_m_n(struct intel_crtc *crtc,
1633                       struct intel_crtc_state *pipe_config);
1634 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1635 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1636 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1637                         struct dpll *best_clock);
1638 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1639
1640 bool intel_crtc_active(struct intel_crtc *crtc);
1641 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
1642 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
1643 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
1644 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1645 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1646                                  struct intel_crtc_state *pipe_config);
1647 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
1648                                   struct intel_crtc_state *crtc_state);
1649
1650 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
1651 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1652 int skl_max_scale(const struct intel_crtc_state *crtc_state,
1653                   u32 pixel_format);
1654
1655 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1656 {
1657         return i915_ggtt_offset(state->vma);
1658 }
1659
1660 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
1661                         const struct intel_plane_state *plane_state);
1662 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1663                   const struct intel_plane_state *plane_state);
1664 u32 glk_color_ctl(const struct intel_plane_state *plane_state);
1665 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
1666                      int plane);
1667 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1668 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1669 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
1670 unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
1671                                    u32 pixel_format, u64 modifier,
1672                                    unsigned int rotation);
1673
1674 /* intel_csr.c */
1675 void intel_csr_ucode_init(struct drm_i915_private *);
1676 void intel_csr_load_program(struct drm_i915_private *);
1677 void intel_csr_ucode_fini(struct drm_i915_private *);
1678 void intel_csr_ucode_suspend(struct drm_i915_private *);
1679 void intel_csr_ucode_resume(struct drm_i915_private *);
1680
1681 /* intel_dp.c */
1682 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
1683                            i915_reg_t dp_reg, enum port port,
1684                            enum pipe *pipe);
1685 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1686                    enum port port);
1687 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1688                              struct intel_connector *intel_connector);
1689 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1690                               int link_rate, uint8_t lane_count,
1691                               bool link_mst);
1692 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1693                                             int link_rate, uint8_t lane_count);
1694 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1695 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1696 int intel_dp_retrain_link(struct intel_encoder *encoder,
1697                           struct drm_modeset_acquire_ctx *ctx);
1698 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1699 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1700 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1701 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1702 bool intel_dp_compute_config(struct intel_encoder *encoder,
1703                              struct intel_crtc_state *pipe_config,
1704                              struct drm_connector_state *conn_state);
1705 bool intel_dp_is_edp(struct intel_dp *intel_dp);
1706 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
1707 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1708                                   bool long_hpd);
1709 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1710                             const struct drm_connector_state *conn_state);
1711 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
1712 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1713 void intel_edp_panel_on(struct intel_dp *intel_dp);
1714 void intel_edp_panel_off(struct intel_dp *intel_dp);
1715 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
1716 void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
1717 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1718 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1719 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1720 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1721 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1722 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1723 void intel_plane_destroy(struct drm_plane *plane);
1724 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1725                            const struct intel_crtc_state *crtc_state);
1726 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1727                             const struct intel_crtc_state *crtc_state);
1728 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1729                                unsigned int frontbuffer_bits);
1730 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1731                           unsigned int frontbuffer_bits);
1732 void icl_program_mg_dp_mode(struct intel_dp *intel_dp);
1733 void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port);
1734 void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port);
1735
1736 void
1737 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1738                                        uint8_t dp_train_pat);
1739 void
1740 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1741 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1742 uint8_t
1743 intel_dp_voltage_max(struct intel_dp *intel_dp);
1744 uint8_t
1745 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1746 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1747                            uint8_t *link_bw, uint8_t *rate_select);
1748 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1749 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
1750 bool
1751 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1752
1753 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1754 {
1755         return ~((1 << lane_count) - 1) & 0xf;
1756 }
1757
1758 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1759 int intel_dp_link_required(int pixel_clock, int bpp);
1760 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1761 bool intel_digital_port_connected(struct intel_encoder *encoder);
1762
1763 /* intel_dp_aux_backlight.c */
1764 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1765
1766 /* intel_dp_mst.c */
1767 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1768 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1769 /* vlv_dsi.c */
1770 void vlv_dsi_init(struct drm_i915_private *dev_priv);
1771
1772 /* intel_dsi_dcs_backlight.c */
1773 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1774
1775 /* intel_dvo.c */
1776 void intel_dvo_init(struct drm_i915_private *dev_priv);
1777 /* intel_hotplug.c */
1778 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1779 bool intel_encoder_hotplug(struct intel_encoder *encoder,
1780                            struct intel_connector *connector);
1781
1782 /* legacy fbdev emulation in intel_fbdev.c */
1783 #ifdef CONFIG_DRM_FBDEV_EMULATION
1784 extern int intel_fbdev_init(struct drm_device *dev);
1785 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1786 extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv);
1787 extern void intel_fbdev_fini(struct drm_i915_private *dev_priv);
1788 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1789 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1790 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1791 #else
1792 static inline int intel_fbdev_init(struct drm_device *dev)
1793 {
1794         return 0;
1795 }
1796
1797 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1798 {
1799 }
1800
1801 static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
1802 {
1803 }
1804
1805 static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv)
1806 {
1807 }
1808
1809 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1810 {
1811 }
1812
1813 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1814 {
1815 }
1816
1817 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1818 {
1819 }
1820 #endif
1821
1822 /* intel_fbc.c */
1823 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1824                            struct intel_atomic_state *state);
1825 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1826 void intel_fbc_pre_update(struct intel_crtc *crtc,
1827                           struct intel_crtc_state *crtc_state,
1828                           struct intel_plane_state *plane_state);
1829 void intel_fbc_post_update(struct intel_crtc *crtc);
1830 void intel_fbc_init(struct drm_i915_private *dev_priv);
1831 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1832 void intel_fbc_enable(struct intel_crtc *crtc,
1833                       struct intel_crtc_state *crtc_state,
1834                       struct intel_plane_state *plane_state);
1835 void intel_fbc_disable(struct intel_crtc *crtc);
1836 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1837 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1838                           unsigned int frontbuffer_bits,
1839                           enum fb_op_origin origin);
1840 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1841                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1842 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1843 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1844 int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv);
1845
1846 /* intel_hdmi.c */
1847 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1848                      enum port port);
1849 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1850                                struct intel_connector *intel_connector);
1851 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1852 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1853                                struct intel_crtc_state *pipe_config,
1854                                struct drm_connector_state *conn_state);
1855 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
1856                                        struct drm_connector *connector,
1857                                        bool high_tmds_clock_ratio,
1858                                        bool scrambling);
1859 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1860 void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
1861
1862
1863 /* intel_lvds.c */
1864 bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,
1865                              i915_reg_t lvds_reg, enum pipe *pipe);
1866 void intel_lvds_init(struct drm_i915_private *dev_priv);
1867 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1868 bool intel_is_dual_link_lvds(struct drm_device *dev);
1869
1870
1871 /* intel_modes.c */
1872 int intel_connector_update_modes(struct drm_connector *connector,
1873                                  struct edid *edid);
1874 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1875 void intel_attach_force_audio_property(struct drm_connector *connector);
1876 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1877 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1878
1879
1880 /* intel_overlay.c */
1881 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1882 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1883 int intel_overlay_switch_off(struct intel_overlay *overlay);
1884 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1885                                   struct drm_file *file_priv);
1886 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1887                               struct drm_file *file_priv);
1888 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1889
1890
1891 /* intel_panel.c */
1892 int intel_panel_init(struct intel_panel *panel,
1893                      struct drm_display_mode *fixed_mode,
1894                      struct drm_display_mode *downclock_mode);
1895 void intel_panel_fini(struct intel_panel *panel);
1896 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1897                             struct drm_display_mode *adjusted_mode);
1898 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1899                              struct intel_crtc_state *pipe_config,
1900                              int fitting_mode);
1901 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1902                               struct intel_crtc_state *pipe_config,
1903                               int fitting_mode);
1904 void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
1905                                     u32 level, u32 max);
1906 int intel_panel_setup_backlight(struct drm_connector *connector,
1907                                 enum pipe pipe);
1908 void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
1909                                   const struct drm_connector_state *conn_state);
1910 void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state);
1911 void intel_panel_destroy_backlight(struct drm_connector *connector);
1912 extern struct drm_display_mode *intel_find_panel_downclock(
1913                                 struct drm_i915_private *dev_priv,
1914                                 struct drm_display_mode *fixed_mode,
1915                                 struct drm_connector *connector);
1916
1917 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1918 int intel_backlight_device_register(struct intel_connector *connector);
1919 void intel_backlight_device_unregister(struct intel_connector *connector);
1920 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1921 static inline int intel_backlight_device_register(struct intel_connector *connector)
1922 {
1923         return 0;
1924 }
1925 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1926 {
1927 }
1928 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1929
1930 /* intel_hdcp.c */
1931 void intel_hdcp_atomic_check(struct drm_connector *connector,
1932                              struct drm_connector_state *old_state,
1933                              struct drm_connector_state *new_state);
1934 int intel_hdcp_init(struct intel_connector *connector,
1935                     const struct intel_hdcp_shim *hdcp_shim);
1936 int intel_hdcp_enable(struct intel_connector *connector);
1937 int intel_hdcp_disable(struct intel_connector *connector);
1938 int intel_hdcp_check_link(struct intel_connector *connector);
1939 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
1940
1941 /* intel_psr.c */
1942 #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
1943 void intel_psr_init_dpcd(struct intel_dp *intel_dp);
1944 void intel_psr_enable(struct intel_dp *intel_dp,
1945                       const struct intel_crtc_state *crtc_state);
1946 void intel_psr_disable(struct intel_dp *intel_dp,
1947                       const struct intel_crtc_state *old_crtc_state);
1948 int intel_psr_set_debugfs_mode(struct drm_i915_private *dev_priv,
1949                                struct drm_modeset_acquire_ctx *ctx,
1950                                u64 value);
1951 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1952                           unsigned frontbuffer_bits,
1953                           enum fb_op_origin origin);
1954 void intel_psr_flush(struct drm_i915_private *dev_priv,
1955                      unsigned frontbuffer_bits,
1956                      enum fb_op_origin origin);
1957 void intel_psr_init(struct drm_i915_private *dev_priv);
1958 void intel_psr_compute_config(struct intel_dp *intel_dp,
1959                               struct intel_crtc_state *crtc_state);
1960 void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug);
1961 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
1962 void intel_psr_short_pulse(struct intel_dp *intel_dp);
1963 int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
1964                             u32 *out_value);
1965
1966 /* intel_runtime_pm.c */
1967 int intel_power_domains_init(struct drm_i915_private *);
1968 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
1969 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1970 void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
1971 void intel_power_domains_enable(struct drm_i915_private *dev_priv);
1972 void intel_power_domains_disable(struct drm_i915_private *dev_priv);
1973
1974 enum i915_drm_suspend_mode {
1975         I915_DRM_SUSPEND_IDLE,
1976         I915_DRM_SUSPEND_MEM,
1977         I915_DRM_SUSPEND_HIBERNATE,
1978 };
1979
1980 void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
1981                                  enum i915_drm_suspend_mode);
1982 void intel_power_domains_resume(struct drm_i915_private *dev_priv);
1983 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1984 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1985 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1986 void intel_runtime_pm_disable(struct drm_i915_private *dev_priv);
1987 const char *
1988 intel_display_power_domain_str(enum intel_display_power_domain domain);
1989
1990 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1991                                     enum intel_display_power_domain domain);
1992 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1993                                       enum intel_display_power_domain domain);
1994 void intel_display_power_get(struct drm_i915_private *dev_priv,
1995                              enum intel_display_power_domain domain);
1996 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1997                                         enum intel_display_power_domain domain);
1998 void intel_display_power_put(struct drm_i915_private *dev_priv,
1999                              enum intel_display_power_domain domain);
2000 void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
2001                             u8 req_slices);
2002
2003 static inline void
2004 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
2005 {
2006         WARN_ONCE(dev_priv->runtime_pm.suspended,
2007                   "Device suspended during HW access\n");
2008 }
2009
2010 static inline void
2011 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
2012 {
2013         assert_rpm_device_not_suspended(dev_priv);
2014         WARN_ONCE(!atomic_read(&dev_priv->runtime_pm.wakeref_count),
2015                   "RPM wakelock ref not held during HW access");
2016 }
2017
2018 /**
2019  * disable_rpm_wakeref_asserts - disable the RPM assert checks
2020  * @dev_priv: i915 device instance
2021  *
2022  * This function disable asserts that check if we hold an RPM wakelock
2023  * reference, while keeping the device-not-suspended checks still enabled.
2024  * It's meant to be used only in special circumstances where our rule about
2025  * the wakelock refcount wrt. the device power state doesn't hold. According
2026  * to this rule at any point where we access the HW or want to keep the HW in
2027  * an active state we must hold an RPM wakelock reference acquired via one of
2028  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
2029  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
2030  * forcewake release timer, and the GPU RPS and hangcheck works. All other
2031  * users should avoid using this function.
2032  *
2033  * Any calls to this function must have a symmetric call to
2034  * enable_rpm_wakeref_asserts().
2035  */
2036 static inline void
2037 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
2038 {
2039         atomic_inc(&dev_priv->runtime_pm.wakeref_count);
2040 }
2041
2042 /**
2043  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
2044  * @dev_priv: i915 device instance
2045  *
2046  * This function re-enables the RPM assert checks after disabling them with
2047  * disable_rpm_wakeref_asserts. It's meant to be used only in special
2048  * circumstances otherwise its use should be avoided.
2049  *
2050  * Any calls to this function must have a symmetric call to
2051  * disable_rpm_wakeref_asserts().
2052  */
2053 static inline void
2054 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
2055 {
2056         atomic_dec(&dev_priv->runtime_pm.wakeref_count);
2057 }
2058
2059 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
2060 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
2061 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
2062 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
2063
2064 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
2065                              bool override, unsigned int mask);
2066 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
2067                           enum dpio_channel ch, bool override);
2068
2069
2070 /* intel_pm.c */
2071 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
2072 void intel_suspend_hw(struct drm_i915_private *dev_priv);
2073 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
2074 void intel_update_watermarks(struct intel_crtc *crtc);
2075 void intel_init_pm(struct drm_i915_private *dev_priv);
2076 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
2077 void intel_pm_setup(struct drm_i915_private *dev_priv);
2078 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
2079 void intel_gpu_ips_teardown(void);
2080 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
2081 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
2082 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
2083 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
2084 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
2085 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
2086 void gen6_rps_busy(struct drm_i915_private *dev_priv);
2087 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
2088 void gen6_rps_idle(struct drm_i915_private *dev_priv);
2089 void gen6_rps_boost(struct i915_request *rq, struct intel_rps_client *rps);
2090 void g4x_wm_get_hw_state(struct drm_device *dev);
2091 void vlv_wm_get_hw_state(struct drm_device *dev);
2092 void ilk_wm_get_hw_state(struct drm_device *dev);
2093 void skl_wm_get_hw_state(struct drm_device *dev);
2094 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2095                           struct skl_ddb_allocation *ddb /* out */);
2096 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
2097                               struct skl_pipe_wm *out);
2098 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
2099 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
2100 bool intel_can_enable_sagv(struct drm_atomic_state *state);
2101 int intel_enable_sagv(struct drm_i915_private *dev_priv);
2102 int intel_disable_sagv(struct drm_i915_private *dev_priv);
2103 bool skl_wm_level_equals(const struct skl_wm_level *l1,
2104                          const struct skl_wm_level *l2);
2105 bool skl_ddb_allocation_overlaps(struct drm_i915_private *dev_priv,
2106                                  const struct skl_ddb_entry **entries,
2107                                  const struct skl_ddb_entry *ddb,
2108                                  int ignore);
2109 bool ilk_disable_lp_wm(struct drm_device *dev);
2110 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
2111                                   struct intel_crtc_state *cstate);
2112 void intel_init_ipc(struct drm_i915_private *dev_priv);
2113 void intel_enable_ipc(struct drm_i915_private *dev_priv);
2114
2115 /* intel_sdvo.c */
2116 bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
2117                              i915_reg_t sdvo_reg, enum pipe *pipe);
2118 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
2119                      i915_reg_t reg, enum port port);
2120
2121
2122 /* intel_sprite.c */
2123 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
2124                              int usecs);
2125 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
2126                                               enum pipe pipe, int plane);
2127 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
2128                                     struct drm_file *file_priv);
2129 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
2130 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
2131 void skl_update_plane(struct intel_plane *plane,
2132                       const struct intel_crtc_state *crtc_state,
2133                       const struct intel_plane_state *plane_state);
2134 void skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc);
2135 bool skl_plane_get_hw_state(struct intel_plane *plane, enum pipe *pipe);
2136 bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
2137                        enum pipe pipe, enum plane_id plane_id);
2138 bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
2139                           enum pipe pipe, enum plane_id plane_id);
2140 unsigned int skl_plane_max_stride(struct intel_plane *plane,
2141                                   u32 pixel_format, u64 modifier,
2142                                   unsigned int rotation);
2143 int skl_plane_check(struct intel_crtc_state *crtc_state,
2144                     struct intel_plane_state *plane_state);
2145 int intel_plane_check_stride(const struct intel_plane_state *plane_state);
2146 int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state);
2147 int chv_plane_check_rotation(const struct intel_plane_state *plane_state);
2148
2149 /* intel_tv.c */
2150 void intel_tv_init(struct drm_i915_private *dev_priv);
2151
2152 /* intel_atomic.c */
2153 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
2154                                                 const struct drm_connector_state *state,
2155                                                 struct drm_property *property,
2156                                                 uint64_t *val);
2157 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
2158                                                 struct drm_connector_state *state,
2159                                                 struct drm_property *property,
2160                                                 uint64_t val);
2161 int intel_digital_connector_atomic_check(struct drm_connector *conn,
2162                                          struct drm_connector_state *new_state);
2163 struct drm_connector_state *
2164 intel_digital_connector_duplicate_state(struct drm_connector *connector);
2165
2166 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
2167 void intel_crtc_destroy_state(struct drm_crtc *crtc,
2168                                struct drm_crtc_state *state);
2169 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
2170 void intel_atomic_state_clear(struct drm_atomic_state *);
2171
2172 static inline struct intel_crtc_state *
2173 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
2174                             struct intel_crtc *crtc)
2175 {
2176         struct drm_crtc_state *crtc_state;
2177         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
2178         if (IS_ERR(crtc_state))
2179                 return ERR_CAST(crtc_state);
2180
2181         return to_intel_crtc_state(crtc_state);
2182 }
2183
2184 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
2185                                struct intel_crtc *intel_crtc,
2186                                struct intel_crtc_state *crtc_state);
2187
2188 /* intel_atomic_plane.c */
2189 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
2190 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
2191 void intel_plane_destroy_state(struct drm_plane *plane,
2192                                struct drm_plane_state *state);
2193 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
2194 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
2195                                         struct intel_crtc_state *crtc_state,
2196                                         const struct intel_plane_state *old_plane_state,
2197                                         struct intel_plane_state *intel_state);
2198
2199 /* intel_color.c */
2200 void intel_color_init(struct drm_crtc *crtc);
2201 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
2202 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
2203 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
2204
2205 /* intel_lspcon.c */
2206 bool lspcon_init(struct intel_digital_port *intel_dig_port);
2207 void lspcon_resume(struct intel_lspcon *lspcon);
2208 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
2209
2210 /* intel_pipe_crc.c */
2211 #ifdef CONFIG_DEBUG_FS
2212 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name);
2213 int intel_crtc_verify_crc_source(struct drm_crtc *crtc,
2214                                  const char *source_name, size_t *values_cnt);
2215 const char *const *intel_crtc_get_crc_sources(struct drm_crtc *crtc,
2216                                               size_t *count);
2217 void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc);
2218 void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc);
2219 #else
2220 #define intel_crtc_set_crc_source NULL
2221 #define intel_crtc_verify_crc_source NULL
2222 #define intel_crtc_get_crc_sources NULL
2223 static inline void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
2224 {
2225 }
2226
2227 static inline void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc)
2228 {
2229 }
2230 #endif
2231 #endif /* __INTEL_DRV_H__ */