drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <[email protected]>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/types.h>
  32 #include <linux/notifier.h>
  33 #include <linux/reboot.h>
  34 #include <asm/byteorder.h>
  35 #include <drm/drmP.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_crtc_helper.h>
  39 #include <drm/drm_dp_helper.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/drm_hdcp.h>
  42 #include "intel_drv.h"
  43 #include <drm/i915_drm.h>
  44 #include "i915_drv.h"
  45
  46 #define DP_DPRX_ESI_LEN 14
  47
  48 /* Compliance test status bits  */
  49 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  50 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  51 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  52 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  53
  54 struct dp_link_dpll {
  55         int clock;
  56         struct dpll dpll;
  57 };
  58
  59 static const struct dp_link_dpll g4x_dpll[] = {
  60         { 162000,
  61                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  62         { 270000,
  63                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  64 };
  65
  66 static const struct dp_link_dpll pch_dpll[] = {
  67         { 162000,
  68                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  69         { 270000,
  70                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  71 };
  72
  73 static const struct dp_link_dpll vlv_dpll[] = {
  74         { 162000,
  75                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  76         { 270000,
  77                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  78 };
  79
  80 /*
  81  * CHV supports eDP 1.4 that have  more link rates.
  82  * Below only provides the fixed rate but exclude variable rate.
  83  */
  84 static const struct dp_link_dpll chv_dpll[] = {
  85         /*
  86          * CHV requires to program fractional division for m2.
  87          * m2 is stored in fixed point format using formula below
  88          * (m2_int << 22) | m2_fraction
  89          */
  90         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
  91                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  92         { 270000,       /* m2_int = 27, m2_fraction = 0 */
  93                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  94 };
  95
  96 /**
  97  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  98  * @intel_dp: DP struct
  99  *
 100  * If a CPU or PCH DP output is attached to an eDP panel, this function
 101  * will return true, and false otherwise.
 102  */
 103 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 104 {
 105         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 106
 107         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 108 }
 109
 110 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 111 {
 112         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 113 }
 114
 115 static void intel_dp_link_down(struct intel_encoder *encoder,
 116                                const struct intel_crtc_state *old_crtc_state);
 117 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 118 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 119 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
 120                                            const struct intel_crtc_state *crtc_state);
 121 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 122                                       enum pipe pipe);
 123 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 124
 125 /* update sink rates from dpcd */
 126 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 127 {
 128         static const int dp_rates[] = {
 129                 162000, 270000, 540000, 810000
 130         };
 131         int i, max_rate;
 132
 133         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 134
 135         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 136                 if (dp_rates[i] > max_rate)
 137                         break;
 138                 intel_dp->sink_rates[i] = dp_rates[i];
 139         }
 140
 141         intel_dp->num_sink_rates = i;
 142 }
 143
 144 /* Get length of rates array potentially limited by max_rate. */
 145 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 146 {
 147         int i;
 148
 149         /* Limit results by potentially reduced max rate */
 150         for (i = 0; i < len; i++) {
 151                 if (rates[len - i - 1] <= max_rate)
 152                         return len - i;
 153         }
 154
 155         return 0;
 156 }
 157
 158 /* Get length of common rates array potentially limited by max_rate. */
 159 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 160                                           int max_rate)
 161 {
 162         return intel_dp_rate_limit_len(intel_dp->common_rates,
 163                                        intel_dp->num_common_rates, max_rate);
 164 }
 165
 166 /* Theoretical max between source and sink */
 167 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 168 {
 169         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 170 }
 171
 172 static int intel_dp_get_fia_supported_lane_count(struct intel_dp *intel_dp)
 173 {
 174         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 175         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 176         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
 177         u32 lane_info;
 178
 179         if (tc_port == PORT_TC_NONE || dig_port->tc_type != TC_PORT_TYPEC)
 180                 return 4;
 181
 182         lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
 183                      DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
 184                     DP_LANE_ASSIGNMENT_SHIFT(tc_port);
 185
 186         switch (lane_info) {
 187         default:
 188                 MISSING_CASE(lane_info);
 189         case 1:
 190         case 2:
 191         case 4:
 192         case 8:
 193                 return 1;
 194         case 3:
 195         case 12:
 196                 return 2;
 197         case 15:
 198                 return 4;
 199         }
 200 }
 201
 202 /* Theoretical max between source and sink */
 203 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 204 {
 205         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 206         int source_max = intel_dig_port->max_lanes;
 207         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 208         int fia_max = intel_dp_get_fia_supported_lane_count(intel_dp);
 209
 210         return min3(source_max, sink_max, fia_max);
 211 }
 212
 213 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 214 {
 215         return intel_dp->max_link_lane_count;
 216 }
 217
 218 int
 219 intel_dp_link_required(int pixel_clock, int bpp)
 220 {
 221         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 222         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 223 }
 224
 225 void icl_program_mg_dp_mode(struct intel_dp *intel_dp)
 226 {
 227         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 228         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 229         enum port port = intel_dig_port->base.port;
 230         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
 231         u32 ln0, ln1, lane_info;
 232
 233         if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type == TC_PORT_TBT)
 234                 return;
 235
 236         ln0 = I915_READ(MG_DP_MODE(port, 0));
 237         ln1 = I915_READ(MG_DP_MODE(port, 1));
 238
 239         switch (intel_dig_port->tc_type) {
 240         case TC_PORT_TYPEC:
 241                 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
 242                 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
 243
 244                 lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
 245                              DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
 246                             DP_LANE_ASSIGNMENT_SHIFT(tc_port);
 247
 248                 switch (lane_info) {
 249                 case 0x1:
 250                 case 0x4:
 251                         break;
 252                 case 0x2:
 253                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
 254                         break;
 255                 case 0x3:
 256                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
 257                                MG_DP_MODE_CFG_DP_X2_MODE;
 258                         break;
 259                 case 0x8:
 260                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
 261                         break;
 262                 case 0xC:
 263                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
 264                                MG_DP_MODE_CFG_DP_X2_MODE;
 265                         break;
 266                 case 0xF:
 267                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
 268                                MG_DP_MODE_CFG_DP_X2_MODE;
 269                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
 270                                MG_DP_MODE_CFG_DP_X2_MODE;
 271                         break;
 272                 default:
 273                         MISSING_CASE(lane_info);
 274                 }
 275                 break;
 276
 277         case TC_PORT_LEGACY:
 278                 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
 279                 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
 280                 break;
 281
 282         default:
 283                 MISSING_CASE(intel_dig_port->tc_type);
 284                 return;
 285         }
 286
 287         I915_WRITE(MG_DP_MODE(port, 0), ln0);
 288         I915_WRITE(MG_DP_MODE(port, 1), ln1);
 289 }
 290
 291 void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
 292 {
 293         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 294         enum port port = dig_port->base.port;
 295         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
 296         i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
 297         u32 val;
 298         int i;
 299
 300         if (tc_port == PORT_TC_NONE)
 301                 return;
 302
 303         for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
 304                 val = I915_READ(mg_regs[i]);
 305                 val |= MG_DP_MODE_CFG_TR2PWR_GATING |
 306                        MG_DP_MODE_CFG_TRPWR_GATING |
 307                        MG_DP_MODE_CFG_CLNPWR_GATING |
 308                        MG_DP_MODE_CFG_DIGPWR_GATING |
 309                        MG_DP_MODE_CFG_GAONPWR_GATING;
 310                 I915_WRITE(mg_regs[i], val);
 311         }
 312
 313         val = I915_READ(MG_MISC_SUS0(tc_port));
 314         val |= MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3) |
 315                MG_MISC_SUS0_CFG_TR2PWR_GATING |
 316                MG_MISC_SUS0_CFG_CL2PWR_GATING |
 317                MG_MISC_SUS0_CFG_GAONPWR_GATING |
 318                MG_MISC_SUS0_CFG_TRPWR_GATING |
 319                MG_MISC_SUS0_CFG_CL1PWR_GATING |
 320                MG_MISC_SUS0_CFG_DGPWR_GATING;
 321         I915_WRITE(MG_MISC_SUS0(tc_port), val);
 322 }
 323
 324 void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
 325 {
 326         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 327         enum port port = dig_port->base.port;
 328         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
 329         i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
 330         u32 val;
 331         int i;
 332
 333         if (tc_port == PORT_TC_NONE)
 334                 return;
 335
 336         for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
 337                 val = I915_READ(mg_regs[i]);
 338                 val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
 339                          MG_DP_MODE_CFG_TRPWR_GATING |
 340                          MG_DP_MODE_CFG_CLNPWR_GATING |
 341                          MG_DP_MODE_CFG_DIGPWR_GATING |
 342                          MG_DP_MODE_CFG_GAONPWR_GATING);
 343                 I915_WRITE(mg_regs[i], val);
 344         }
 345
 346         val = I915_READ(MG_MISC_SUS0(tc_port));
 347         val &= ~(MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK |
 348                  MG_MISC_SUS0_CFG_TR2PWR_GATING |
 349                  MG_MISC_SUS0_CFG_CL2PWR_GATING |
 350                  MG_MISC_SUS0_CFG_GAONPWR_GATING |
 351                  MG_MISC_SUS0_CFG_TRPWR_GATING |
 352                  MG_MISC_SUS0_CFG_CL1PWR_GATING |
 353                  MG_MISC_SUS0_CFG_DGPWR_GATING);
 354         I915_WRITE(MG_MISC_SUS0(tc_port), val);
 355 }
 356
 357 int
 358 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 359 {
 360         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 361          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 362          * is transmitted every LS_Clk per lane, there is no need to account for
 363          * the channel encoding that is done in the PHY layer here.
 364          */
 365
 366         return max_link_clock * max_lanes;
 367 }
 368
 369 static int
 370 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 371 {
 372         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 373         struct intel_encoder *encoder = &intel_dig_port->base;
 374         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 375         int max_dotclk = dev_priv->max_dotclk_freq;
 376         int ds_max_dotclk;
 377
 378         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
 379
 380         if (type != DP_DS_PORT_TYPE_VGA)
 381                 return max_dotclk;
 382
 383         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
 384                                                     intel_dp->downstream_ports);
 385
 386         if (ds_max_dotclk != 0)
 387                 max_dotclk = min(max_dotclk, ds_max_dotclk);
 388
 389         return max_dotclk;
 390 }
 391
 392 static int cnl_max_source_rate(struct intel_dp *intel_dp)
 393 {
 394         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 395         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 396         enum port port = dig_port->base.port;
 397
 398         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 399
 400         /* Low voltage SKUs are limited to max of 5.4G */
 401         if (voltage == VOLTAGE_INFO_0_85V)
 402                 return 540000;
 403
 404         /* For this SKU 8.1G is supported in all ports */
 405         if (IS_CNL_WITH_PORT_F(dev_priv))
 406                 return 810000;
 407
 408         /* For other SKUs, max rate on ports A and D is 5.4G */
 409         if (port == PORT_A || port == PORT_D)
 410                 return 540000;
 411
 412         return 810000;
 413 }
 414
 415 static int icl_max_source_rate(struct intel_dp *intel_dp)
 416 {
 417         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 418         enum port port = dig_port->base.port;
 419
 420         if (port == PORT_B)
 421                 return 540000;
 422
 423         return 810000;
 424 }
 425
 426 static void
 427 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 428 {
 429         /* The values must be in increasing order */
 430         static const int cnl_rates[] = {
 431                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
 432         };
 433         static const int bxt_rates[] = {
 434                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 435         };
 436         static const int skl_rates[] = {
 437                 162000, 216000, 270000, 324000, 432000, 540000
 438         };
 439         static const int hsw_rates[] = {
 440                 162000, 270000, 540000
 441         };
 442         static const int g4x_rates[] = {
 443                 162000, 270000
 444         };
 445         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 446         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 447         const struct ddi_vbt_port_info *info =
 448                 &dev_priv->vbt.ddi_port_info[dig_port->base.port];
 449         const int *source_rates;
 450         int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
 451
 452         /* This should only be done once */
 453         WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
 454
 455         if (INTEL_GEN(dev_priv) >= 10) {
 456                 source_rates = cnl_rates;
 457                 size = ARRAY_SIZE(cnl_rates);
 458                 if (INTEL_GEN(dev_priv) == 10)
 459                         max_rate = cnl_max_source_rate(intel_dp);
 460                 else
 461                         max_rate = icl_max_source_rate(intel_dp);
 462         } else if (IS_GEN9_LP(dev_priv)) {
 463                 source_rates = bxt_rates;
 464                 size = ARRAY_SIZE(bxt_rates);
 465         } else if (IS_GEN9_BC(dev_priv)) {
 466                 source_rates = skl_rates;
 467                 size = ARRAY_SIZE(skl_rates);
 468         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 469                    IS_BROADWELL(dev_priv)) {
 470                 source_rates = hsw_rates;
 471                 size = ARRAY_SIZE(hsw_rates);
 472         } else {
 473                 source_rates = g4x_rates;
 474                 size = ARRAY_SIZE(g4x_rates);
 475         }
 476
 477         if (max_rate && vbt_max_rate)
 478                 max_rate = min(max_rate, vbt_max_rate);
 479         else if (vbt_max_rate)
 480                 max_rate = vbt_max_rate;
 481
 482         if (max_rate)
 483                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 484
 485         intel_dp->source_rates = source_rates;
 486         intel_dp->num_source_rates = size;
 487 }
 488
 489 static int intersect_rates(const int *source_rates, int source_len,
 490                            const int *sink_rates, int sink_len,
 491                            int *common_rates)
 492 {
 493         int i = 0, j = 0, k = 0;
 494
 495         while (i < source_len && j < sink_len) {
 496                 if (source_rates[i] == sink_rates[j]) {
 497                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 498                                 return k;
 499                         common_rates[k] = source_rates[i];
 500                         ++k;
 501                         ++i;
 502                         ++j;
 503                 } else if (source_rates[i] < sink_rates[j]) {
 504                         ++i;
 505                 } else {
 506                         ++j;
 507                 }
 508         }
 509         return k;
 510 }
 511
 512 /* return index of rate in rates array, or -1 if not found */
 513 static int intel_dp_rate_index(const int *rates, int len, int rate)
 514 {
 515         int i;
 516
 517         for (i = 0; i < len; i++)
 518                 if (rate == rates[i])
 519                         return i;
 520
 521         return -1;
 522 }
 523
 524 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 525 {
 526         WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 527
 528         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 529                                                      intel_dp->num_source_rates,
 530                                                      intel_dp->sink_rates,
 531                                                      intel_dp->num_sink_rates,
 532                                                      intel_dp->common_rates);
 533
 534         /* Paranoia, there should always be something in common. */
 535         if (WARN_ON(intel_dp->num_common_rates == 0)) {
 536                 intel_dp->common_rates[0] = 162000;
 537                 intel_dp->num_common_rates = 1;
 538         }
 539 }
 540
 541 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 542                                        uint8_t lane_count)
 543 {
 544         /*
 545          * FIXME: we need to synchronize the current link parameters with
 546          * hardware readout. Currently fast link training doesn't work on
 547          * boot-up.
 548          */
 549         if (link_rate == 0 ||
 550             link_rate > intel_dp->max_link_rate)
 551                 return false;
 552
 553         if (lane_count == 0 ||
 554             lane_count > intel_dp_max_lane_count(intel_dp))
 555                 return false;
 556
 557         return true;
 558 }
 559
 560 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 561                                                      int link_rate,
 562                                                      uint8_t lane_count)
 563 {
 564         const struct drm_display_mode *fixed_mode =
 565                 intel_dp->attached_connector->panel.fixed_mode;
 566         int mode_rate, max_rate;
 567
 568         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 569         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 570         if (mode_rate > max_rate)
 571                 return false;
 572
 573         return true;
 574 }
 575
 576 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 577                                             int link_rate, uint8_t lane_count)
 578 {
 579         int index;
 580
 581         index = intel_dp_rate_index(intel_dp->common_rates,
 582                                     intel_dp->num_common_rates,
 583                                     link_rate);
 584         if (index > 0) {
 585                 if (intel_dp_is_edp(intel_dp) &&
 586                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 587                                                               intel_dp->common_rates[index - 1],
 588                                                               lane_count)) {
 589                         DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
 590                         return 0;
 591                 }
 592                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 593                 intel_dp->max_link_lane_count = lane_count;
 594         } else if (lane_count > 1) {
 595                 if (intel_dp_is_edp(intel_dp) &&
 596                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 597                                                               intel_dp_max_common_rate(intel_dp),
 598                                                               lane_count >> 1)) {
 599                         DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
 600                         return 0;
 601                 }
 602                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 603                 intel_dp->max_link_lane_count = lane_count >> 1;
 604         } else {
 605                 DRM_ERROR("Link Training Unsuccessful\n");
 606                 return -1;
 607         }
 608
 609         return 0;
 610 }
 611
 612 static enum drm_mode_status
 613 intel_dp_mode_valid(struct drm_connector *connector,
 614                     struct drm_display_mode *mode)
 615 {
 616         struct intel_dp *intel_dp = intel_attached_dp(connector);
 617         struct intel_connector *intel_connector = to_intel_connector(connector);
 618         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 619         int target_clock = mode->clock;
 620         int max_rate, mode_rate, max_lanes, max_link_clock;
 621         int max_dotclk;
 622
 623         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 624                 return MODE_NO_DBLESCAN;
 625
 626         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 627
 628         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 629                 if (mode->hdisplay > fixed_mode->hdisplay)
 630                         return MODE_PANEL;
 631
 632                 if (mode->vdisplay > fixed_mode->vdisplay)
 633                         return MODE_PANEL;
 634
 635                 target_clock = fixed_mode->clock;
 636         }
 637
 638         max_link_clock = intel_dp_max_link_rate(intel_dp);
 639         max_lanes = intel_dp_max_lane_count(intel_dp);
 640
 641         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 642         mode_rate = intel_dp_link_required(target_clock, 18);
 643
 644         if (mode_rate > max_rate || target_clock > max_dotclk)
 645                 return MODE_CLOCK_HIGH;
 646
 647         if (mode->clock < 10000)
 648                 return MODE_CLOCK_LOW;
 649
 650         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 651                 return MODE_H_ILLEGAL;
 652
 653         return MODE_OK;
 654 }
 655
 656 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 657 {
 658         int     i;
 659         uint32_t v = 0;
 660
 661         if (src_bytes > 4)
 662                 src_bytes = 4;
 663         for (i = 0; i < src_bytes; i++)
 664                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 665         return v;
 666 }
 667
 668 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 669 {
 670         int i;
 671         if (dst_bytes > 4)
 672                 dst_bytes = 4;
 673         for (i = 0; i < dst_bytes; i++)
 674                 dst[i] = src >> ((3-i) * 8);
 675 }
 676
 677 static void
 678 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
 679 static void
 680 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
 681                                               bool force_disable_vdd);
 682 static void
 683 intel_dp_pps_init(struct intel_dp *intel_dp);
 684
 685 static void pps_lock(struct intel_dp *intel_dp)
 686 {
 687         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 688
 689         /*
 690          * See intel_power_sequencer_reset() why we need
 691          * a power domain reference here.
 692          */
 693         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
 694
 695         mutex_lock(&dev_priv->pps_mutex);
 696 }
 697
 698 static void pps_unlock(struct intel_dp *intel_dp)
 699 {
 700         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 701
 702         mutex_unlock(&dev_priv->pps_mutex);
 703
 704         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
 705 }
 706
 707 static void
 708 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 709 {
 710         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 711         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 712         enum pipe pipe = intel_dp->pps_pipe;
 713         bool pll_enabled, release_cl_override = false;
 714         enum dpio_phy phy = DPIO_PHY(pipe);
 715         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 716         uint32_t DP;
 717
 718         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 719                  "skipping pipe %c power sequencer kick due to port %c being active\n",
 720                  pipe_name(pipe), port_name(intel_dig_port->base.port)))
 721                 return;
 722
 723         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 724                       pipe_name(pipe), port_name(intel_dig_port->base.port));
 725
 726         /* Preserve the BIOS-computed detected bit. This is
 727          * supposed to be read-only.
 728          */
 729         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 730         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 731         DP |= DP_PORT_WIDTH(1);
 732         DP |= DP_LINK_TRAIN_PAT_1;
 733
 734         if (IS_CHERRYVIEW(dev_priv))
 735                 DP |= DP_PIPE_SEL_CHV(pipe);
 736         else
 737                 DP |= DP_PIPE_SEL(pipe);
 738
 739         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 740
 741         /*
 742          * The DPLL for the pipe must be enabled for this to work.
 743          * So enable temporarily it if it's not already enabled.
 744          */
 745         if (!pll_enabled) {
 746                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 747                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 748
 749                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 750                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 751                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 752                                   pipe_name(pipe));
 753                         return;
 754                 }
 755         }
 756
 757         /*
 758          * Similar magic as in intel_dp_enable_port().
 759          * We _must_ do this port enable + disable trick
 760          * to make this power sequencer lock onto the port.
 761          * Otherwise even VDD force bit won't work.
 762          */
 763         I915_WRITE(intel_dp->output_reg, DP);
 764         POSTING_READ(intel_dp->output_reg);
 765
 766         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 767         POSTING_READ(intel_dp->output_reg);
 768
 769         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 770         POSTING_READ(intel_dp->output_reg);
 771
 772         if (!pll_enabled) {
 773                 vlv_force_pll_off(dev_priv, pipe);
 774
 775                 if (release_cl_override)
 776                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 777         }
 778 }
 779
 780 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 781 {
 782         struct intel_encoder *encoder;
 783         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 784
 785         /*
 786          * We don't have power sequencer currently.
 787          * Pick one that's not used by other ports.
 788          */
 789         for_each_intel_dp(&dev_priv->drm, encoder) {
 790                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 791
 792                 if (encoder->type == INTEL_OUTPUT_EDP) {
 793                         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 794                                 intel_dp->active_pipe != intel_dp->pps_pipe);
 795
 796                         if (intel_dp->pps_pipe != INVALID_PIPE)
 797                                 pipes &= ~(1 << intel_dp->pps_pipe);
 798                 } else {
 799                         WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
 800
 801                         if (intel_dp->active_pipe != INVALID_PIPE)
 802                                 pipes &= ~(1 << intel_dp->active_pipe);
 803                 }
 804         }
 805
 806         if (pipes == 0)
 807                 return INVALID_PIPE;
 808
 809         return ffs(pipes) - 1;
 810 }
 811
 812 static enum pipe
 813 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 814 {
 815         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 816         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 817         enum pipe pipe;
 818
 819         lockdep_assert_held(&dev_priv->pps_mutex);
 820
 821         /* We should never land here with regular DP ports */
 822         WARN_ON(!intel_dp_is_edp(intel_dp));
 823
 824         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 825                 intel_dp->active_pipe != intel_dp->pps_pipe);
 826
 827         if (intel_dp->pps_pipe != INVALID_PIPE)
 828                 return intel_dp->pps_pipe;
 829
 830         pipe = vlv_find_free_pps(dev_priv);
 831
 832         /*
 833          * Didn't find one. This should not happen since there
 834          * are two power sequencers and up to two eDP ports.
 835          */
 836         if (WARN_ON(pipe == INVALID_PIPE))
 837                 pipe = PIPE_A;
 838
 839         vlv_steal_power_sequencer(dev_priv, pipe);
 840         intel_dp->pps_pipe = pipe;
 841
 842         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 843                       pipe_name(intel_dp->pps_pipe),
 844                       port_name(intel_dig_port->base.port));
 845
 846         /* init power sequencer on this pipe and port */
 847         intel_dp_init_panel_power_sequencer(intel_dp);
 848         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
 849
 850         /*
 851          * Even vdd force doesn't work until we've made
 852          * the power sequencer lock in on the port.
 853          */
 854         vlv_power_sequencer_kick(intel_dp);
 855
 856         return intel_dp->pps_pipe;
 857 }
 858
 859 static int
 860 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 861 {
 862         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 863         int backlight_controller = dev_priv->vbt.backlight.controller;
 864
 865         lockdep_assert_held(&dev_priv->pps_mutex);
 866
 867         /* We should never land here with regular DP ports */
 868         WARN_ON(!intel_dp_is_edp(intel_dp));
 869
 870         if (!intel_dp->pps_reset)
 871                 return backlight_controller;
 872
 873         intel_dp->pps_reset = false;
 874
 875         /*
 876          * Only the HW needs to be reprogrammed, the SW state is fixed and
 877          * has been setup during connector init.
 878          */
 879         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 880
 881         return backlight_controller;
 882 }
 883
 884 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 885                                enum pipe pipe);
 886
 887 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 888                                enum pipe pipe)
 889 {
 890         return I915_READ(PP_STATUS(pipe)) & PP_ON;
 891 }
 892
 893 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 894                                 enum pipe pipe)
 895 {
 896         return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 897 }
 898
 899 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 900                          enum pipe pipe)
 901 {
 902         return true;
 903 }
 904
 905 static enum pipe
 906 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 907                      enum port port,
 908                      vlv_pipe_check pipe_check)
 909 {
 910         enum pipe pipe;
 911
 912         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 913                 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
 914                         PANEL_PORT_SELECT_MASK;
 915
 916                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 917                         continue;
 918
 919                 if (!pipe_check(dev_priv, pipe))
 920                         continue;
 921
 922                 return pipe;
 923         }
 924
 925         return INVALID_PIPE;
 926 }
 927
 928 static void
 929 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 930 {
 931         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 932         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 933         enum port port = intel_dig_port->base.port;
 934
 935         lockdep_assert_held(&dev_priv->pps_mutex);
 936
 937         /* try to find a pipe with this port selected */
 938         /* first pick one where the panel is on */
 939         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 940                                                   vlv_pipe_has_pp_on);
 941         /* didn't find one? pick one where vdd is on */
 942         if (intel_dp->pps_pipe == INVALID_PIPE)
 943                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 944                                                           vlv_pipe_has_vdd_on);
 945         /* didn't find one? pick one with just the correct port */
 946         if (intel_dp->pps_pipe == INVALID_PIPE)
 947                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 948                                                           vlv_pipe_any);
 949
 950         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 951         if (intel_dp->pps_pipe == INVALID_PIPE) {
 952                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 953                               port_name(port));
 954                 return;
 955         }
 956
 957         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 958                       port_name(port), pipe_name(intel_dp->pps_pipe));
 959
 960         intel_dp_init_panel_power_sequencer(intel_dp);
 961         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 962 }
 963
 964 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
 965 {
 966         struct intel_encoder *encoder;
 967
 968         if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 969                     !IS_GEN9_LP(dev_priv)))
 970                 return;
 971
 972         /*
 973          * We can't grab pps_mutex here due to deadlock with power_domain
 974          * mutex when power_domain functions are called while holding pps_mutex.
 975          * That also means that in order to use pps_pipe the code needs to
 976          * hold both a power domain reference and pps_mutex, and the power domain
 977          * reference get/put must be done while _not_ holding pps_mutex.
 978          * pps_{lock,unlock}() do these steps in the correct order, so one
 979          * should use them always.
 980          */
 981
 982         for_each_intel_dp(&dev_priv->drm, encoder) {
 983                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 984
 985                 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
 986
 987                 if (encoder->type != INTEL_OUTPUT_EDP)
 988                         continue;
 989
 990                 if (IS_GEN9_LP(dev_priv))
 991                         intel_dp->pps_reset = true;
 992                 else
 993                         intel_dp->pps_pipe = INVALID_PIPE;
 994         }
 995 }
 996
 997 struct pps_registers {
 998         i915_reg_t pp_ctrl;
 999         i915_reg_t pp_stat;
1000         i915_reg_t pp_on;
1001         i915_reg_t pp_off;
1002         i915_reg_t pp_div;
1003 };
1004
1005 static void intel_pps_get_registers(struct intel_dp *intel_dp,
1006                                     struct pps_registers *regs)
1007 {
1008         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1009         int pps_idx = 0;
1010
1011         memset(regs, 0, sizeof(*regs));
1012
1013         if (IS_GEN9_LP(dev_priv))
1014                 pps_idx = bxt_power_sequencer_idx(intel_dp);
1015         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1016                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
1017
1018         regs->pp_ctrl = PP_CONTROL(pps_idx);
1019         regs->pp_stat = PP_STATUS(pps_idx);
1020         regs->pp_on = PP_ON_DELAYS(pps_idx);
1021         regs->pp_off = PP_OFF_DELAYS(pps_idx);
1022         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
1023             !HAS_PCH_ICP(dev_priv))
1024                 regs->pp_div = PP_DIVISOR(pps_idx);
1025 }
1026
1027 static i915_reg_t
1028 _pp_ctrl_reg(struct intel_dp *intel_dp)
1029 {
1030         struct pps_registers regs;
1031
1032         intel_pps_get_registers(intel_dp, &regs);
1033
1034         return regs.pp_ctrl;
1035 }
1036
1037 static i915_reg_t
1038 _pp_stat_reg(struct intel_dp *intel_dp)
1039 {
1040         struct pps_registers regs;
1041
1042         intel_pps_get_registers(intel_dp, &regs);
1043
1044         return regs.pp_stat;
1045 }
1046
1047 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
1048    This function only applicable when panel PM state is not to be tracked */
1049 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
1050                               void *unused)
1051 {
1052         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
1053                                                  edp_notifier);
1054         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1055
1056         if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
1057                 return 0;
1058
1059         pps_lock(intel_dp);
1060
1061         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1062                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
1063                 i915_reg_t pp_ctrl_reg, pp_div_reg;
1064                 u32 pp_div;
1065
1066                 pp_ctrl_reg = PP_CONTROL(pipe);
1067                 pp_div_reg  = PP_DIVISOR(pipe);
1068                 pp_div = I915_READ(pp_div_reg);
1069                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
1070
1071                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
1072                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
1073                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
1074                 msleep(intel_dp->panel_power_cycle_delay);
1075         }
1076
1077         pps_unlock(intel_dp);
1078
1079         return 0;
1080 }
1081
1082 static bool edp_have_panel_power(struct intel_dp *intel_dp)
1083 {
1084         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1085
1086         lockdep_assert_held(&dev_priv->pps_mutex);
1087
1088         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1089             intel_dp->pps_pipe == INVALID_PIPE)
1090                 return false;
1091
1092         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
1093 }
1094
1095 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
1096 {
1097         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1098
1099         lockdep_assert_held(&dev_priv->pps_mutex);
1100
1101         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1102             intel_dp->pps_pipe == INVALID_PIPE)
1103                 return false;
1104
1105         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
1106 }
1107
1108 static void
1109 intel_dp_check_edp(struct intel_dp *intel_dp)
1110 {
1111         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1112
1113         if (!intel_dp_is_edp(intel_dp))
1114                 return;
1115
1116         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
1117                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
1118                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
1119                               I915_READ(_pp_stat_reg(intel_dp)),
1120                               I915_READ(_pp_ctrl_reg(intel_dp)));
1121         }
1122 }
1123
1124 static uint32_t
1125 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
1126 {
1127         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1128         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1129         uint32_t status;
1130         bool done;
1131
1132 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1133         done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
1134                                   msecs_to_jiffies_timeout(10));
1135         if (!done)
1136                 DRM_ERROR("dp aux hw did not signal timeout!\n");
1137 #undef C
1138
1139         return status;
1140 }
1141
1142 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1143 {
1144         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1145
1146         if (index)
1147                 return 0;
1148
1149         /*
1150          * The clock divider is based off the hrawclk, and would like to run at
1151          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
1152          */
1153         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1154 }
1155
1156 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1157 {
1158         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1159
1160         if (index)
1161                 return 0;
1162
1163         /*
1164          * The clock divider is based off the cdclk or PCH rawclk, and would
1165          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
1166          * divide by 2000 and use that
1167          */
1168         if (intel_dp->aux_ch == AUX_CH_A)
1169                 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
1170         else
1171                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1172 }
1173
1174 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1175 {
1176         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1177
1178         if (intel_dp->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1179                 /* Workaround for non-ULT HSW */
1180                 switch (index) {
1181                 case 0: return 63;
1182                 case 1: return 72;
1183                 default: return 0;
1184                 }
1185         }
1186
1187         return ilk_get_aux_clock_divider(intel_dp, index);
1188 }
1189
1190 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1191 {
1192         /*
1193          * SKL doesn't need us to program the AUX clock divider (Hardware will
1194          * derive the clock from CDCLK automatically). We still implement the
1195          * get_aux_clock_divider vfunc to plug-in into the existing code.
1196          */
1197         return index ? 0 : 1;
1198 }
1199
1200 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1201                                      int send_bytes,
1202                                      uint32_t aux_clock_divider)
1203 {
1204         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1205         struct drm_i915_private *dev_priv =
1206                         to_i915(intel_dig_port->base.base.dev);
1207         uint32_t precharge, timeout;
1208
1209         if (IS_GEN6(dev_priv))
1210                 precharge = 3;
1211         else
1212                 precharge = 5;
1213
1214         if (IS_BROADWELL(dev_priv))
1215                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1216         else
1217                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1218
1219         return DP_AUX_CH_CTL_SEND_BUSY |
1220                DP_AUX_CH_CTL_DONE |
1221                DP_AUX_CH_CTL_INTERRUPT |
1222                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1223                timeout |
1224                DP_AUX_CH_CTL_RECEIVE_ERROR |
1225                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1226                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1227                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1228 }
1229
1230 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1231                                       int send_bytes,
1232                                       uint32_t unused)
1233 {
1234         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1235         uint32_t ret;
1236
1237         ret = DP_AUX_CH_CTL_SEND_BUSY |
1238               DP_AUX_CH_CTL_DONE |
1239               DP_AUX_CH_CTL_INTERRUPT |
1240               DP_AUX_CH_CTL_TIME_OUT_ERROR |
1241               DP_AUX_CH_CTL_TIME_OUT_MAX |
1242               DP_AUX_CH_CTL_RECEIVE_ERROR |
1243               (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1244               DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1245               DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1246
1247         if (intel_dig_port->tc_type == TC_PORT_TBT)
1248                 ret |= DP_AUX_CH_CTL_TBT_IO;
1249
1250         return ret;
1251 }
1252
1253 static int
1254 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1255                   const uint8_t *send, int send_bytes,
1256                   uint8_t *recv, int recv_size,
1257                   u32 aux_send_ctl_flags)
1258 {
1259         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1260         struct drm_i915_private *dev_priv =
1261                         to_i915(intel_dig_port->base.base.dev);
1262         i915_reg_t ch_ctl, ch_data[5];
1263         uint32_t aux_clock_divider;
1264         int i, ret, recv_bytes;
1265         uint32_t status;
1266         int try, clock = 0;
1267         bool vdd;
1268
1269         ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1270         for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1271                 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1272
1273         pps_lock(intel_dp);
1274
1275         /*
1276          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1277          * In such cases we want to leave VDD enabled and it's up to upper layers
1278          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1279          * ourselves.
1280          */
1281         vdd = edp_panel_vdd_on(intel_dp);
1282
1283         /* dp aux is extremely sensitive to irq latency, hence request the
1284          * lowest possible wakeup latency and so prevent the cpu from going into
1285          * deep sleep states.
1286          */
1287         pm_qos_update_request(&dev_priv->pm_qos, 0);
1288
1289         intel_dp_check_edp(intel_dp);
1290
1291         /* Try to wait for any previous AUX channel activity */
1292         for (try = 0; try < 3; try++) {
1293                 status = I915_READ_NOTRACE(ch_ctl);
1294                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1295                         break;
1296                 msleep(1);
1297         }
1298
1299         if (try == 3) {
1300                 static u32 last_status = -1;
1301                 const u32 status = I915_READ(ch_ctl);
1302
1303                 if (status != last_status) {
1304                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
1305                              status);
1306                         last_status = status;
1307                 }
1308
1309                 ret = -EBUSY;
1310                 goto out;
1311         }
1312
1313         /* Only 5 data registers! */
1314         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1315                 ret = -E2BIG;
1316                 goto out;
1317         }
1318
1319         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1320                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1321                                                           send_bytes,
1322                                                           aux_clock_divider);
1323
1324                 send_ctl |= aux_send_ctl_flags;
1325
1326                 /* Must try at least 3 times according to DP spec */
1327                 for (try = 0; try < 5; try++) {
1328                         /* Load the send data into the aux channel data registers */
1329                         for (i = 0; i < send_bytes; i += 4)
1330                                 I915_WRITE(ch_data[i >> 2],
1331                                            intel_dp_pack_aux(send + i,
1332                                                              send_bytes - i));
1333
1334                         /* Send the command and wait for it to complete */
1335                         I915_WRITE(ch_ctl, send_ctl);
1336
1337                         status = intel_dp_aux_wait_done(intel_dp);
1338
1339                         /* Clear done status and any errors */
1340                         I915_WRITE(ch_ctl,
1341                                    status |
1342                                    DP_AUX_CH_CTL_DONE |
1343                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
1344                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
1345
1346                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1347                          *   400us delay required for errors and timeouts
1348                          *   Timeout errors from the HW already meet this
1349                          *   requirement so skip to next iteration
1350                          */
1351                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1352                                 continue;
1353
1354                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1355                                 usleep_range(400, 500);
1356                                 continue;
1357                         }
1358                         if (status & DP_AUX_CH_CTL_DONE)
1359                                 goto done;
1360                 }
1361         }
1362
1363         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1364                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1365                 ret = -EBUSY;
1366                 goto out;
1367         }
1368
1369 done:
1370         /* Check for timeout or receive error.
1371          * Timeouts occur when the sink is not connected
1372          */
1373         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1374                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1375                 ret = -EIO;
1376                 goto out;
1377         }
1378
1379         /* Timeouts occur when the device isn't connected, so they're
1380          * "normal" -- don't fill the kernel log with these */
1381         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1382                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1383                 ret = -ETIMEDOUT;
1384                 goto out;
1385         }
1386
1387         /* Unload any bytes sent back from the other side */
1388         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1389                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1390
1391         /*
1392          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1393          * We have no idea of what happened so we return -EBUSY so
1394          * drm layer takes care for the necessary retries.
1395          */
1396         if (recv_bytes == 0 || recv_bytes > 20) {
1397                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1398                               recv_bytes);
1399                 ret = -EBUSY;
1400                 goto out;
1401         }
1402
1403         if (recv_bytes > recv_size)
1404                 recv_bytes = recv_size;
1405
1406         for (i = 0; i < recv_bytes; i += 4)
1407                 intel_dp_unpack_aux(I915_READ(ch_data[i >> 2]),
1408                                     recv + i, recv_bytes - i);
1409
1410         ret = recv_bytes;
1411 out:
1412         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1413
1414         if (vdd)
1415                 edp_panel_vdd_off(intel_dp, false);
1416
1417         pps_unlock(intel_dp);
1418
1419         return ret;
1420 }
1421
1422 #define BARE_ADDRESS_SIZE       3
1423 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1424
1425 static void
1426 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1427                     const struct drm_dp_aux_msg *msg)
1428 {
1429         txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1430         txbuf[1] = (msg->address >> 8) & 0xff;
1431         txbuf[2] = msg->address & 0xff;
1432         txbuf[3] = msg->size - 1;
1433 }
1434
1435 static ssize_t
1436 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1437 {
1438         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1439         uint8_t txbuf[20], rxbuf[20];
1440         size_t txsize, rxsize;
1441         int ret;
1442
1443         intel_dp_aux_header(txbuf, msg);
1444
1445         switch (msg->request & ~DP_AUX_I2C_MOT) {
1446         case DP_AUX_NATIVE_WRITE:
1447         case DP_AUX_I2C_WRITE:
1448         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1449                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1450                 rxsize = 2; /* 0 or 1 data bytes */
1451
1452                 if (WARN_ON(txsize > 20))
1453                         return -E2BIG;
1454
1455                 WARN_ON(!msg->buffer != !msg->size);
1456
1457                 if (msg->buffer)
1458                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1459
1460                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1461                                         rxbuf, rxsize, 0);
1462                 if (ret > 0) {
1463                         msg->reply = rxbuf[0] >> 4;
1464
1465                         if (ret > 1) {
1466                                 /* Number of bytes written in a short write. */
1467                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1468                         } else {
1469                                 /* Return payload size. */
1470                                 ret = msg->size;
1471                         }
1472                 }
1473                 break;
1474
1475         case DP_AUX_NATIVE_READ:
1476         case DP_AUX_I2C_READ:
1477                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1478                 rxsize = msg->size + 1;
1479
1480                 if (WARN_ON(rxsize > 20))
1481                         return -E2BIG;
1482
1483                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1484                                         rxbuf, rxsize, 0);
1485                 if (ret > 0) {
1486                         msg->reply = rxbuf[0] >> 4;
1487                         /*
1488                          * Assume happy day, and copy the data. The caller is
1489                          * expected to check msg->reply before touching it.
1490                          *
1491                          * Return payload size.
1492                          */
1493                         ret--;
1494                         memcpy(msg->buffer, rxbuf + 1, ret);
1495                 }
1496                 break;
1497
1498         default:
1499                 ret = -EINVAL;
1500                 break;
1501         }
1502
1503         return ret;
1504 }
1505
1506 static enum aux_ch intel_aux_ch(struct intel_dp *intel_dp)
1507 {
1508         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1509         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1510         enum port port = encoder->port;
1511         const struct ddi_vbt_port_info *info =
1512                 &dev_priv->vbt.ddi_port_info[port];
1513         enum aux_ch aux_ch;
1514
1515         if (!info->alternate_aux_channel) {
1516                 aux_ch = (enum aux_ch) port;
1517
1518                 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1519                               aux_ch_name(aux_ch), port_name(port));
1520                 return aux_ch;
1521         }
1522
1523         switch (info->alternate_aux_channel) {
1524         case DP_AUX_A:
1525                 aux_ch = AUX_CH_A;
1526                 break;
1527         case DP_AUX_B:
1528                 aux_ch = AUX_CH_B;
1529                 break;
1530         case DP_AUX_C:
1531                 aux_ch = AUX_CH_C;
1532                 break;
1533         case DP_AUX_D:
1534                 aux_ch = AUX_CH_D;
1535                 break;
1536         case DP_AUX_E:
1537                 aux_ch = AUX_CH_E;
1538                 break;
1539         case DP_AUX_F:
1540                 aux_ch = AUX_CH_F;
1541                 break;
1542         default:
1543                 MISSING_CASE(info->alternate_aux_channel);
1544                 aux_ch = AUX_CH_A;
1545                 break;
1546         }
1547
1548         DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1549                       aux_ch_name(aux_ch), port_name(port));
1550
1551         return aux_ch;
1552 }
1553
1554 static enum intel_display_power_domain
1555 intel_aux_power_domain(struct intel_dp *intel_dp)
1556 {
1557         switch (intel_dp->aux_ch) {
1558         case AUX_CH_A:
1559                 return POWER_DOMAIN_AUX_A;
1560         case AUX_CH_B:
1561                 return POWER_DOMAIN_AUX_B;
1562         case AUX_CH_C:
1563                 return POWER_DOMAIN_AUX_C;
1564         case AUX_CH_D:
1565                 return POWER_DOMAIN_AUX_D;
1566         case AUX_CH_E:
1567                 return POWER_DOMAIN_AUX_E;
1568         case AUX_CH_F:
1569                 return POWER_DOMAIN_AUX_F;
1570         default:
1571                 MISSING_CASE(intel_dp->aux_ch);
1572                 return POWER_DOMAIN_AUX_A;
1573         }
1574 }
1575
1576 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1577 {
1578         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1579         enum aux_ch aux_ch = intel_dp->aux_ch;
1580
1581         switch (aux_ch) {
1582         case AUX_CH_B:
1583         case AUX_CH_C:
1584         case AUX_CH_D:
1585                 return DP_AUX_CH_CTL(aux_ch);
1586         default:
1587                 MISSING_CASE(aux_ch);
1588                 return DP_AUX_CH_CTL(AUX_CH_B);
1589         }
1590 }
1591
1592 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1593 {
1594         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1595         enum aux_ch aux_ch = intel_dp->aux_ch;
1596
1597         switch (aux_ch) {
1598         case AUX_CH_B:
1599         case AUX_CH_C:
1600         case AUX_CH_D:
1601                 return DP_AUX_CH_DATA(aux_ch, index);
1602         default:
1603                 MISSING_CASE(aux_ch);
1604                 return DP_AUX_CH_DATA(AUX_CH_B, index);
1605         }
1606 }
1607
1608 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1609 {
1610         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1611         enum aux_ch aux_ch = intel_dp->aux_ch;
1612
1613         switch (aux_ch) {
1614         case AUX_CH_A:
1615                 return DP_AUX_CH_CTL(aux_ch);
1616         case AUX_CH_B:
1617         case AUX_CH_C:
1618         case AUX_CH_D:
1619                 return PCH_DP_AUX_CH_CTL(aux_ch);
1620         default:
1621                 MISSING_CASE(aux_ch);
1622                 return DP_AUX_CH_CTL(AUX_CH_A);
1623         }
1624 }
1625
1626 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1627 {
1628         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1629         enum aux_ch aux_ch = intel_dp->aux_ch;
1630
1631         switch (aux_ch) {
1632         case AUX_CH_A:
1633                 return DP_AUX_CH_DATA(aux_ch, index);
1634         case AUX_CH_B:
1635         case AUX_CH_C:
1636         case AUX_CH_D:
1637                 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1638         default:
1639                 MISSING_CASE(aux_ch);
1640                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1641         }
1642 }
1643
1644 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1645 {
1646         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1647         enum aux_ch aux_ch = intel_dp->aux_ch;
1648
1649         switch (aux_ch) {
1650         case AUX_CH_A:
1651         case AUX_CH_B:
1652         case AUX_CH_C:
1653         case AUX_CH_D:
1654         case AUX_CH_E:
1655         case AUX_CH_F:
1656                 return DP_AUX_CH_CTL(aux_ch);
1657         default:
1658                 MISSING_CASE(aux_ch);
1659                 return DP_AUX_CH_CTL(AUX_CH_A);
1660         }
1661 }
1662
1663 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1664 {
1665         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1666         enum aux_ch aux_ch = intel_dp->aux_ch;
1667
1668         switch (aux_ch) {
1669         case AUX_CH_A:
1670         case AUX_CH_B:
1671         case AUX_CH_C:
1672         case AUX_CH_D:
1673         case AUX_CH_E:
1674         case AUX_CH_F:
1675                 return DP_AUX_CH_DATA(aux_ch, index);
1676         default:
1677                 MISSING_CASE(aux_ch);
1678                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1679         }
1680 }
1681
1682 static void
1683 intel_dp_aux_fini(struct intel_dp *intel_dp)
1684 {
1685         kfree(intel_dp->aux.name);
1686 }
1687
1688 static void
1689 intel_dp_aux_init(struct intel_dp *intel_dp)
1690 {
1691         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1692         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1693
1694         intel_dp->aux_ch = intel_aux_ch(intel_dp);
1695         intel_dp->aux_power_domain = intel_aux_power_domain(intel_dp);
1696
1697         if (INTEL_GEN(dev_priv) >= 9) {
1698                 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1699                 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1700         } else if (HAS_PCH_SPLIT(dev_priv)) {
1701                 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1702                 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1703         } else {
1704                 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1705                 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1706         }
1707
1708         if (INTEL_GEN(dev_priv) >= 9)
1709                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1710         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1711                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1712         else if (HAS_PCH_SPLIT(dev_priv))
1713                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1714         else
1715                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1716
1717         if (INTEL_GEN(dev_priv) >= 9)
1718                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1719         else
1720                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1721
1722         drm_dp_aux_init(&intel_dp->aux);
1723
1724         /* Failure to allocate our preferred name is not critical */
1725         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c",
1726                                        port_name(encoder->port));
1727         intel_dp->aux.transfer = intel_dp_aux_transfer;
1728 }
1729
1730 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1731 {
1732         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1733
1734         return max_rate >= 540000;
1735 }
1736
1737 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1738 {
1739         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1740
1741         return max_rate >= 810000;
1742 }
1743
1744 static void
1745 intel_dp_set_clock(struct intel_encoder *encoder,
1746                    struct intel_crtc_state *pipe_config)
1747 {
1748         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1749         const struct dp_link_dpll *divisor = NULL;
1750         int i, count = 0;
1751
1752         if (IS_G4X(dev_priv)) {
1753                 divisor = g4x_dpll;
1754                 count = ARRAY_SIZE(g4x_dpll);
1755         } else if (HAS_PCH_SPLIT(dev_priv)) {
1756                 divisor = pch_dpll;
1757                 count = ARRAY_SIZE(pch_dpll);
1758         } else if (IS_CHERRYVIEW(dev_priv)) {
1759                 divisor = chv_dpll;
1760                 count = ARRAY_SIZE(chv_dpll);
1761         } else if (IS_VALLEYVIEW(dev_priv)) {
1762                 divisor = vlv_dpll;
1763                 count = ARRAY_SIZE(vlv_dpll);
1764         }
1765
1766         if (divisor && count) {
1767                 for (i = 0; i < count; i++) {
1768                         if (pipe_config->port_clock == divisor[i].clock) {
1769                                 pipe_config->dpll = divisor[i].dpll;
1770                                 pipe_config->clock_set = true;
1771                                 break;
1772                         }
1773                 }
1774         }
1775 }
1776
1777 static void snprintf_int_array(char *str, size_t len,
1778                                const int *array, int nelem)
1779 {
1780         int i;
1781
1782         str[0] = '\0';
1783
1784         for (i = 0; i < nelem; i++) {
1785                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1786                 if (r >= len)
1787                         return;
1788                 str += r;
1789                 len -= r;
1790         }
1791 }
1792
1793 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1794 {
1795         char str[128]; /* FIXME: too big for stack? */
1796
1797         if ((drm_debug & DRM_UT_KMS) == 0)
1798                 return;
1799
1800         snprintf_int_array(str, sizeof(str),
1801                            intel_dp->source_rates, intel_dp->num_source_rates);
1802         DRM_DEBUG_KMS("source rates: %s\n", str);
1803
1804         snprintf_int_array(str, sizeof(str),
1805                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1806         DRM_DEBUG_KMS("sink rates: %s\n", str);
1807
1808         snprintf_int_array(str, sizeof(str),
1809                            intel_dp->common_rates, intel_dp->num_common_rates);
1810         DRM_DEBUG_KMS("common rates: %s\n", str);
1811 }
1812
1813 int
1814 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1815 {
1816         int len;
1817
1818         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1819         if (WARN_ON(len <= 0))
1820                 return 162000;
1821
1822         return intel_dp->common_rates[len - 1];
1823 }
1824
1825 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1826 {
1827         int i = intel_dp_rate_index(intel_dp->sink_rates,
1828                                     intel_dp->num_sink_rates, rate);
1829
1830         if (WARN_ON(i < 0))
1831                 i = 0;
1832
1833         return i;
1834 }
1835
1836 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1837                            uint8_t *link_bw, uint8_t *rate_select)
1838 {
1839         /* eDP 1.4 rate select method. */
1840         if (intel_dp->use_rate_select) {
1841                 *link_bw = 0;
1842                 *rate_select =
1843                         intel_dp_rate_select(intel_dp, port_clock);
1844         } else {
1845                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1846                 *rate_select = 0;
1847         }
1848 }
1849
1850 struct link_config_limits {
1851         int min_clock, max_clock;
1852         int min_lane_count, max_lane_count;
1853         int min_bpp, max_bpp;
1854 };
1855
1856 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1857                                 struct intel_crtc_state *pipe_config)
1858 {
1859         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1860         struct intel_connector *intel_connector = intel_dp->attached_connector;
1861         int bpp, bpc;
1862
1863         bpp = pipe_config->pipe_bpp;
1864         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1865
1866         if (bpc > 0)
1867                 bpp = min(bpp, 3*bpc);
1868
1869         if (intel_dp_is_edp(intel_dp)) {
1870                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1871                 if (intel_connector->base.display_info.bpc == 0 &&
1872                     dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1873                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1874                                       dev_priv->vbt.edp.bpp);
1875                         bpp = dev_priv->vbt.edp.bpp;
1876                 }
1877         }
1878
1879         return bpp;
1880 }
1881
1882 /* Adjust link config limits based on compliance test requests. */
1883 static void
1884 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1885                                   struct intel_crtc_state *pipe_config,
1886                                   struct link_config_limits *limits)
1887 {
1888         /* For DP Compliance we override the computed bpp for the pipe */
1889         if (intel_dp->compliance.test_data.bpc != 0) {
1890                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1891
1892                 limits->min_bpp = limits->max_bpp = bpp;
1893                 pipe_config->dither_force_disable = bpp == 6 * 3;
1894
1895                 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
1896         }
1897
1898         /* Use values requested by Compliance Test Request */
1899         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1900                 int index;
1901
1902                 /* Validate the compliance test data since max values
1903                  * might have changed due to link train fallback.
1904                  */
1905                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1906                                                intel_dp->compliance.test_lane_count)) {
1907                         index = intel_dp_rate_index(intel_dp->common_rates,
1908                                                     intel_dp->num_common_rates,
1909                                                     intel_dp->compliance.test_link_rate);
1910                         if (index >= 0)
1911                                 limits->min_clock = limits->max_clock = index;
1912                         limits->min_lane_count = limits->max_lane_count =
1913                                 intel_dp->compliance.test_lane_count;
1914                 }
1915         }
1916 }
1917
1918 /* Optimize link config in order: max bpp, min clock, min lanes */
1919 static bool
1920 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1921                                   struct intel_crtc_state *pipe_config,
1922                                   const struct link_config_limits *limits)
1923 {
1924         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1925         int bpp, clock, lane_count;
1926         int mode_rate, link_clock, link_avail;
1927
1928         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1929                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1930                                                    bpp);
1931
1932                 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1933                         for (lane_count = limits->min_lane_count;
1934                              lane_count <= limits->max_lane_count;
1935                              lane_count <<= 1) {
1936                                 link_clock = intel_dp->common_rates[clock];
1937                                 link_avail = intel_dp_max_data_rate(link_clock,
1938                                                                     lane_count);
1939
1940                                 if (mode_rate <= link_avail) {
1941                                         pipe_config->lane_count = lane_count;
1942                                         pipe_config->pipe_bpp = bpp;
1943                                         pipe_config->port_clock = link_clock;
1944
1945                                         return true;
1946                                 }
1947                         }
1948                 }
1949         }
1950
1951         return false;
1952 }
1953
1954 static bool
1955 intel_dp_compute_link_config(struct intel_encoder *encoder,
1956                              struct intel_crtc_state *pipe_config)
1957 {
1958         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1959         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1960         struct link_config_limits limits;
1961         int common_len;
1962
1963         common_len = intel_dp_common_len_rate_limit(intel_dp,
1964                                                     intel_dp->max_link_rate);
1965
1966         /* No common link rates between source and sink */
1967         WARN_ON(common_len <= 0);
1968
1969         limits.min_clock = 0;
1970         limits.max_clock = common_len - 1;
1971
1972         limits.min_lane_count = 1;
1973         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
1974
1975         limits.min_bpp = 6 * 3;
1976         limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
1977
1978         if (intel_dp_is_edp(intel_dp)) {
1979                 /*
1980                  * Use the maximum clock and number of lanes the eDP panel
1981                  * advertizes being capable of. The panels are generally
1982                  * designed to support only a single clock and lane
1983                  * configuration, and typically these values correspond to the
1984                  * native resolution of the panel.
1985                  */
1986                 limits.min_lane_count = limits.max_lane_count;
1987                 limits.min_clock = limits.max_clock;
1988         }
1989
1990         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
1991
1992         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1993                       "max rate %d max bpp %d pixel clock %iKHz\n",
1994                       limits.max_lane_count,
1995                       intel_dp->common_rates[limits.max_clock],
1996                       limits.max_bpp, adjusted_mode->crtc_clock);
1997
1998         /*
1999          * Optimize for slow and wide. This is the place to add alternative
2000          * optimization policy.
2001          */
2002         if (!intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits))
2003                 return false;
2004
2005         DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
2006                       pipe_config->lane_count, pipe_config->port_clock,
2007                       pipe_config->pipe_bpp);
2008
2009         DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2010                       intel_dp_link_required(adjusted_mode->crtc_clock,
2011                                              pipe_config->pipe_bpp),
2012                       intel_dp_max_data_rate(pipe_config->port_clock,
2013                                              pipe_config->lane_count));
2014
2015         return true;
2016 }
2017
2018 bool
2019 intel_dp_compute_config(struct intel_encoder *encoder,
2020                         struct intel_crtc_state *pipe_config,
2021                         struct drm_connector_state *conn_state)
2022 {
2023         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2024         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2025         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2026         enum port port = encoder->port;
2027         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
2028         struct intel_connector *intel_connector = intel_dp->attached_connector;
2029         struct intel_digital_connector_state *intel_conn_state =
2030                 to_intel_digital_connector_state(conn_state);
2031         bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
2032                                            DP_DPCD_QUIRK_CONSTANT_N);
2033
2034         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
2035                 pipe_config->has_pch_encoder = true;
2036
2037         pipe_config->has_drrs = false;
2038         if (IS_G4X(dev_priv) || port == PORT_A)
2039                 pipe_config->has_audio = false;
2040         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2041                 pipe_config->has_audio = intel_dp->has_audio;
2042         else
2043                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
2044
2045         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2046                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
2047                                        adjusted_mode);
2048
2049                 if (INTEL_GEN(dev_priv) >= 9) {
2050                         int ret;
2051
2052                         ret = skl_update_scaler_crtc(pipe_config);
2053                         if (ret)
2054                                 return ret;
2055                 }
2056
2057                 if (HAS_GMCH_DISPLAY(dev_priv))
2058                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
2059                                                  conn_state->scaling_mode);
2060                 else
2061                         intel_pch_panel_fitting(intel_crtc, pipe_config,
2062                                                 conn_state->scaling_mode);
2063         }
2064
2065         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2066                 return false;
2067
2068         if (HAS_GMCH_DISPLAY(dev_priv) &&
2069             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2070                 return false;
2071
2072         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2073                 return false;
2074
2075         if (!intel_dp_compute_link_config(encoder, pipe_config))
2076                 return false;
2077
2078         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2079                 /*
2080                  * See:
2081                  * CEA-861-E - 5.1 Default Encoding Parameters
2082                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2083                  */
2084                 pipe_config->limited_color_range =
2085                         pipe_config->pipe_bpp != 18 &&
2086                         drm_default_rgb_quant_range(adjusted_mode) ==
2087                         HDMI_QUANTIZATION_RANGE_LIMITED;
2088         } else {
2089                 pipe_config->limited_color_range =
2090                         intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2091         }
2092
2093         intel_link_compute_m_n(pipe_config->pipe_bpp, pipe_config->lane_count,
2094                                adjusted_mode->crtc_clock,
2095                                pipe_config->port_clock,
2096                                &pipe_config->dp_m_n,
2097                                constant_n);
2098
2099         if (intel_connector->panel.downclock_mode != NULL &&
2100                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
2101                         pipe_config->has_drrs = true;
2102                         intel_link_compute_m_n(pipe_config->pipe_bpp,
2103                                                pipe_config->lane_count,
2104                                                intel_connector->panel.downclock_mode->clock,
2105                                                pipe_config->port_clock,
2106                                                &pipe_config->dp_m2_n2,
2107                                                constant_n);
2108         }
2109
2110         if (!HAS_DDI(dev_priv))
2111                 intel_dp_set_clock(encoder, pipe_config);
2112
2113         intel_psr_compute_config(intel_dp, pipe_config);
2114
2115         return true;
2116 }
2117
2118 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2119                               int link_rate, uint8_t lane_count,
2120                               bool link_mst)
2121 {
2122         intel_dp->link_trained = false;
2123         intel_dp->link_rate = link_rate;
2124         intel_dp->lane_count = lane_count;
2125         intel_dp->link_mst = link_mst;
2126 }
2127
2128 static void intel_dp_prepare(struct intel_encoder *encoder,
2129                              const struct intel_crtc_state *pipe_config)
2130 {
2131         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2132         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2133         enum port port = encoder->port;
2134         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2135         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2136
2137         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
2138                                  pipe_config->lane_count,
2139                                  intel_crtc_has_type(pipe_config,
2140                                                      INTEL_OUTPUT_DP_MST));
2141
2142         /*
2143          * There are four kinds of DP registers:
2144          *
2145          *      IBX PCH
2146          *      SNB CPU
2147          *      IVB CPU
2148          *      CPT PCH
2149          *
2150          * IBX PCH and CPU are the same for almost everything,
2151          * except that the CPU DP PLL is configured in this
2152          * register
2153          *
2154          * CPT PCH is quite different, having many bits moved
2155          * to the TRANS_DP_CTL register instead. That
2156          * configuration happens (oddly) in ironlake_pch_enable
2157          */
2158
2159         /* Preserve the BIOS-computed detected bit. This is
2160          * supposed to be read-only.
2161          */
2162         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
2163
2164         /* Handle DP bits in common between all three register formats */
2165         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
2166         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
2167
2168         /* Split out the IBX/CPU vs CPT settings */
2169
2170         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
2171                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2172                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2173                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2174                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2175                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2176
2177                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2178                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2179
2180                 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
2181         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2182                 u32 trans_dp;
2183
2184                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2185
2186                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2187                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2188                         trans_dp |= TRANS_DP_ENH_FRAMING;
2189                 else
2190                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
2191                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
2192         } else {
2193                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2194                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
2195
2196                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2197                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2198                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2199                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2200                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2201
2202                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2203                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2204
2205                 if (IS_CHERRYVIEW(dev_priv))
2206                         intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2207                 else
2208                         intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2209         }
2210 }
2211
2212 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
2213 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
2214
2215 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
2216 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
2217
2218 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2219 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
2220
2221 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2222
2223 static void wait_panel_status(struct intel_dp *intel_dp,
2224                                        u32 mask,
2225                                        u32 value)
2226 {
2227         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2228         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2229
2230         lockdep_assert_held(&dev_priv->pps_mutex);
2231
2232         intel_pps_verify_state(intel_dp);
2233
2234         pp_stat_reg = _pp_stat_reg(intel_dp);
2235         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2236
2237         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
2238                         mask, value,
2239                         I915_READ(pp_stat_reg),
2240                         I915_READ(pp_ctrl_reg));
2241
2242         if (intel_wait_for_register(dev_priv,
2243                                     pp_stat_reg, mask, value,
2244                                     5000))
2245                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
2246                                 I915_READ(pp_stat_reg),
2247                                 I915_READ(pp_ctrl_reg));
2248
2249         DRM_DEBUG_KMS("Wait complete\n");
2250 }
2251
2252 static void wait_panel_on(struct intel_dp *intel_dp)
2253 {
2254         DRM_DEBUG_KMS("Wait for panel power on\n");
2255         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2256 }
2257
2258 static void wait_panel_off(struct intel_dp *intel_dp)
2259 {
2260         DRM_DEBUG_KMS("Wait for panel power off time\n");
2261         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2262 }
2263
2264 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2265 {
2266         ktime_t panel_power_on_time;
2267         s64 panel_power_off_duration;
2268
2269         DRM_DEBUG_KMS("Wait for panel power cycle\n");
2270
2271         /* take the difference of currrent time and panel power off time
2272          * and then make panel wait for t11_t12 if needed. */
2273         panel_power_on_time = ktime_get_boottime();
2274         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2275
2276         /* When we disable the VDD override bit last we have to do the manual
2277          * wait. */
2278         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2279                 wait_remaining_ms_from_jiffies(jiffies,
2280                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2281
2282         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2283 }
2284
2285 static void wait_backlight_on(struct intel_dp *intel_dp)
2286 {
2287         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2288                                        intel_dp->backlight_on_delay);
2289 }
2290
2291 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2292 {
2293         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2294                                        intel_dp->backlight_off_delay);
2295 }
2296
2297 /* Read the current pp_control value, unlocking the register if it
2298  * is locked
2299  */
2300
2301 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2302 {
2303         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2304         u32 control;
2305
2306         lockdep_assert_held(&dev_priv->pps_mutex);
2307
2308         control = I915_READ(_pp_ctrl_reg(intel_dp));
2309         if (WARN_ON(!HAS_DDI(dev_priv) &&
2310                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2311                 control &= ~PANEL_UNLOCK_MASK;
2312                 control |= PANEL_UNLOCK_REGS;
2313         }
2314         return control;
2315 }
2316
2317 /*
2318  * Must be paired with edp_panel_vdd_off().
2319  * Must hold pps_mutex around the whole on/off sequence.
2320  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2321  */
2322 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2323 {
2324         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2325         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2326         u32 pp;
2327         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2328         bool need_to_disable = !intel_dp->want_panel_vdd;
2329
2330         lockdep_assert_held(&dev_priv->pps_mutex);
2331
2332         if (!intel_dp_is_edp(intel_dp))
2333                 return false;
2334
2335         cancel_delayed_work(&intel_dp->panel_vdd_work);
2336         intel_dp->want_panel_vdd = true;
2337
2338         if (edp_have_panel_vdd(intel_dp))
2339                 return need_to_disable;
2340
2341         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
2342
2343         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2344                       port_name(intel_dig_port->base.port));
2345
2346         if (!edp_have_panel_power(intel_dp))
2347                 wait_panel_power_cycle(intel_dp);
2348
2349         pp = ironlake_get_pp_control(intel_dp);
2350         pp |= EDP_FORCE_VDD;
2351
2352         pp_stat_reg = _pp_stat_reg(intel_dp);
2353         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2354
2355         I915_WRITE(pp_ctrl_reg, pp);
2356         POSTING_READ(pp_ctrl_reg);
2357         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2358                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2359         /*
2360          * If the panel wasn't on, delay before accessing aux channel
2361          */
2362         if (!edp_have_panel_power(intel_dp)) {
2363                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2364                               port_name(intel_dig_port->base.port));
2365                 msleep(intel_dp->panel_power_up_delay);
2366         }
2367
2368         return need_to_disable;
2369 }
2370
2371 /*
2372  * Must be paired with intel_edp_panel_vdd_off() or
2373  * intel_edp_panel_off().
2374  * Nested calls to these functions are not allowed since
2375  * we drop the lock. Caller must use some higher level
2376  * locking to prevent nested calls from other threads.
2377  */
2378 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2379 {
2380         bool vdd;
2381
2382         if (!intel_dp_is_edp(intel_dp))
2383                 return;
2384
2385         pps_lock(intel_dp);
2386         vdd = edp_panel_vdd_on(intel_dp);
2387         pps_unlock(intel_dp);
2388
2389         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2390              port_name(dp_to_dig_port(intel_dp)->base.port));
2391 }
2392
2393 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2394 {
2395         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2396         struct intel_digital_port *intel_dig_port =
2397                 dp_to_dig_port(intel_dp);
2398         u32 pp;
2399         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2400
2401         lockdep_assert_held(&dev_priv->pps_mutex);
2402
2403         WARN_ON(intel_dp->want_panel_vdd);
2404
2405         if (!edp_have_panel_vdd(intel_dp))
2406                 return;
2407
2408         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2409                       port_name(intel_dig_port->base.port));
2410
2411         pp = ironlake_get_pp_control(intel_dp);
2412         pp &= ~EDP_FORCE_VDD;
2413
2414         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2415         pp_stat_reg = _pp_stat_reg(intel_dp);
2416
2417         I915_WRITE(pp_ctrl_reg, pp);
2418         POSTING_READ(pp_ctrl_reg);
2419
2420         /* Make sure sequencer is idle before allowing subsequent activity */
2421         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2422         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2423
2424         if ((pp & PANEL_POWER_ON) == 0)
2425                 intel_dp->panel_power_off_time = ktime_get_boottime();
2426
2427         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2428 }
2429
2430 static void edp_panel_vdd_work(struct work_struct *__work)
2431 {
2432         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2433                                                  struct intel_dp, panel_vdd_work);
2434
2435         pps_lock(intel_dp);
2436         if (!intel_dp->want_panel_vdd)
2437                 edp_panel_vdd_off_sync(intel_dp);
2438         pps_unlock(intel_dp);
2439 }
2440
2441 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2442 {
2443         unsigned long delay;
2444
2445         /*
2446          * Queue the timer to fire a long time from now (relative to the power
2447          * down delay) to keep the panel power up across a sequence of
2448          * operations.
2449          */
2450         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2451         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2452 }
2453
2454 /*
2455  * Must be paired with edp_panel_vdd_on().
2456  * Must hold pps_mutex around the whole on/off sequence.
2457  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2458  */
2459 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2460 {
2461         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2462
2463         lockdep_assert_held(&dev_priv->pps_mutex);
2464
2465         if (!intel_dp_is_edp(intel_dp))
2466                 return;
2467
2468         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2469              port_name(dp_to_dig_port(intel_dp)->base.port));
2470
2471         intel_dp->want_panel_vdd = false;
2472
2473         if (sync)
2474                 edp_panel_vdd_off_sync(intel_dp);
2475         else
2476                 edp_panel_vdd_schedule_off(intel_dp);
2477 }
2478
2479 static void edp_panel_on(struct intel_dp *intel_dp)
2480 {
2481         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2482         u32 pp;
2483         i915_reg_t pp_ctrl_reg;
2484
2485         lockdep_assert_held(&dev_priv->pps_mutex);
2486
2487         if (!intel_dp_is_edp(intel_dp))
2488                 return;
2489
2490         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2491                       port_name(dp_to_dig_port(intel_dp)->base.port));
2492
2493         if (WARN(edp_have_panel_power(intel_dp),
2494                  "eDP port %c panel power already on\n",
2495                  port_name(dp_to_dig_port(intel_dp)->base.port)))
2496                 return;
2497
2498         wait_panel_power_cycle(intel_dp);
2499
2500         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2501         pp = ironlake_get_pp_control(intel_dp);
2502         if (IS_GEN5(dev_priv)) {
2503                 /* ILK workaround: disable reset around power sequence */
2504                 pp &= ~PANEL_POWER_RESET;
2505                 I915_WRITE(pp_ctrl_reg, pp);
2506                 POSTING_READ(pp_ctrl_reg);
2507         }
2508
2509         pp |= PANEL_POWER_ON;
2510         if (!IS_GEN5(dev_priv))
2511                 pp |= PANEL_POWER_RESET;
2512
2513         I915_WRITE(pp_ctrl_reg, pp);
2514         POSTING_READ(pp_ctrl_reg);
2515
2516         wait_panel_on(intel_dp);
2517         intel_dp->last_power_on = jiffies;
2518
2519         if (IS_GEN5(dev_priv)) {
2520                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2521                 I915_WRITE(pp_ctrl_reg, pp);
2522                 POSTING_READ(pp_ctrl_reg);
2523         }
2524 }
2525
2526 void intel_edp_panel_on(struct intel_dp *intel_dp)
2527 {
2528         if (!intel_dp_is_edp(intel_dp))
2529                 return;
2530
2531         pps_lock(intel_dp);
2532         edp_panel_on(intel_dp);
2533         pps_unlock(intel_dp);
2534 }
2535
2536
2537 static void edp_panel_off(struct intel_dp *intel_dp)
2538 {
2539         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2540         u32 pp;
2541         i915_reg_t pp_ctrl_reg;
2542
2543         lockdep_assert_held(&dev_priv->pps_mutex);
2544
2545         if (!intel_dp_is_edp(intel_dp))
2546                 return;
2547
2548         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2549                       port_name(dp_to_dig_port(intel_dp)->base.port));
2550
2551         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2552              port_name(dp_to_dig_port(intel_dp)->base.port));
2553
2554         pp = ironlake_get_pp_control(intel_dp);
2555         /* We need to switch off panel power _and_ force vdd, for otherwise some
2556          * panels get very unhappy and cease to work. */
2557         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2558                 EDP_BLC_ENABLE);
2559
2560         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2561
2562         intel_dp->want_panel_vdd = false;
2563
2564         I915_WRITE(pp_ctrl_reg, pp);
2565         POSTING_READ(pp_ctrl_reg);
2566
2567         wait_panel_off(intel_dp);
2568         intel_dp->panel_power_off_time = ktime_get_boottime();
2569
2570         /* We got a reference when we enabled the VDD. */
2571         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2572 }
2573
2574 void intel_edp_panel_off(struct intel_dp *intel_dp)
2575 {
2576         if (!intel_dp_is_edp(intel_dp))
2577                 return;
2578
2579         pps_lock(intel_dp);
2580         edp_panel_off(intel_dp);
2581         pps_unlock(intel_dp);
2582 }
2583
2584 /* Enable backlight in the panel power control. */
2585 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2586 {
2587         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2588         u32 pp;
2589         i915_reg_t pp_ctrl_reg;
2590
2591         /*
2592          * If we enable the backlight right away following a panel power
2593          * on, we may see slight flicker as the panel syncs with the eDP
2594          * link.  So delay a bit to make sure the image is solid before
2595          * allowing it to appear.
2596          */
2597         wait_backlight_on(intel_dp);
2598
2599         pps_lock(intel_dp);
2600
2601         pp = ironlake_get_pp_control(intel_dp);
2602         pp |= EDP_BLC_ENABLE;
2603
2604         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2605
2606         I915_WRITE(pp_ctrl_reg, pp);
2607         POSTING_READ(pp_ctrl_reg);
2608
2609         pps_unlock(intel_dp);
2610 }
2611
2612 /* Enable backlight PWM and backlight PP control. */
2613 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2614                             const struct drm_connector_state *conn_state)
2615 {
2616         struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2617
2618         if (!intel_dp_is_edp(intel_dp))
2619                 return;
2620
2621         DRM_DEBUG_KMS("\n");
2622
2623         intel_panel_enable_backlight(crtc_state, conn_state);
2624         _intel_edp_backlight_on(intel_dp);
2625 }
2626
2627 /* Disable backlight in the panel power control. */
2628 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2629 {
2630         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2631         u32 pp;
2632         i915_reg_t pp_ctrl_reg;
2633
2634         if (!intel_dp_is_edp(intel_dp))
2635                 return;
2636
2637         pps_lock(intel_dp);
2638
2639         pp = ironlake_get_pp_control(intel_dp);
2640         pp &= ~EDP_BLC_ENABLE;
2641
2642         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2643
2644         I915_WRITE(pp_ctrl_reg, pp);
2645         POSTING_READ(pp_ctrl_reg);
2646
2647         pps_unlock(intel_dp);
2648
2649         intel_dp->last_backlight_off = jiffies;
2650         edp_wait_backlight_off(intel_dp);
2651 }
2652
2653 /* Disable backlight PP control and backlight PWM. */
2654 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2655 {
2656         struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2657
2658         if (!intel_dp_is_edp(intel_dp))
2659                 return;
2660
2661         DRM_DEBUG_KMS("\n");
2662
2663         _intel_edp_backlight_off(intel_dp);
2664         intel_panel_disable_backlight(old_conn_state);
2665 }
2666
2667 /*
2668  * Hook for controlling the panel power control backlight through the bl_power
2669  * sysfs attribute. Take care to handle multiple calls.
2670  */
2671 static void intel_edp_backlight_power(struct intel_connector *connector,
2672                                       bool enable)
2673 {
2674         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2675         bool is_enabled;
2676
2677         pps_lock(intel_dp);
2678         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2679         pps_unlock(intel_dp);
2680
2681         if (is_enabled == enable)
2682                 return;
2683
2684         DRM_DEBUG_KMS("panel power control backlight %s\n",
2685                       enable ? "enable" : "disable");
2686
2687         if (enable)
2688                 _intel_edp_backlight_on(intel_dp);
2689         else
2690                 _intel_edp_backlight_off(intel_dp);
2691 }
2692
2693 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2694 {
2695         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2696         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2697         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2698
2699         I915_STATE_WARN(cur_state != state,
2700                         "DP port %c state assertion failure (expected %s, current %s)\n",
2701                         port_name(dig_port->base.port),
2702                         onoff(state), onoff(cur_state));
2703 }
2704 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2705
2706 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2707 {
2708         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2709
2710         I915_STATE_WARN(cur_state != state,
2711                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2712                         onoff(state), onoff(cur_state));
2713 }
2714 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2715 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2716
2717 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2718                                 const struct intel_crtc_state *pipe_config)
2719 {
2720         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2721         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2722
2723         assert_pipe_disabled(dev_priv, crtc->pipe);
2724         assert_dp_port_disabled(intel_dp);
2725         assert_edp_pll_disabled(dev_priv);
2726
2727         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2728                       pipe_config->port_clock);
2729
2730         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2731
2732         if (pipe_config->port_clock == 162000)
2733                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2734         else
2735                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2736
2737         I915_WRITE(DP_A, intel_dp->DP);
2738         POSTING_READ(DP_A);
2739         udelay(500);
2740
2741         /*
2742          * [DevILK] Work around required when enabling DP PLL
2743          * while a pipe is enabled going to FDI:
2744          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2745          * 2. Program DP PLL enable
2746          */
2747         if (IS_GEN5(dev_priv))
2748                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2749
2750         intel_dp->DP |= DP_PLL_ENABLE;
2751
2752         I915_WRITE(DP_A, intel_dp->DP);
2753         POSTING_READ(DP_A);
2754         udelay(200);
2755 }
2756
2757 static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
2758                                  const struct intel_crtc_state *old_crtc_state)
2759 {
2760         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
2761         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2762
2763         assert_pipe_disabled(dev_priv, crtc->pipe);
2764         assert_dp_port_disabled(intel_dp);
2765         assert_edp_pll_enabled(dev_priv);
2766
2767         DRM_DEBUG_KMS("disabling eDP PLL\n");
2768
2769         intel_dp->DP &= ~DP_PLL_ENABLE;
2770
2771         I915_WRITE(DP_A, intel_dp->DP);
2772         POSTING_READ(DP_A);
2773         udelay(200);
2774 }
2775
2776 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2777 {
2778         /*
2779          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2780          * be capable of signalling downstream hpd with a long pulse.
2781          * Whether or not that means D3 is safe to use is not clear,
2782          * but let's assume so until proven otherwise.
2783          *
2784          * FIXME should really check all downstream ports...
2785          */
2786         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2787                 intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
2788                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2789 }
2790
2791 /* If the sink supports it, try to set the power state appropriately */
2792 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2793 {
2794         int ret, i;
2795
2796         /* Should have a valid DPCD by this point */
2797         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2798                 return;
2799
2800         if (mode != DRM_MODE_DPMS_ON) {
2801                 if (downstream_hpd_needs_d0(intel_dp))
2802                         return;
2803
2804                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2805                                          DP_SET_POWER_D3);
2806         } else {
2807                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2808
2809                 /*
2810                  * When turning on, we need to retry for 1ms to give the sink
2811                  * time to wake up.
2812                  */
2813                 for (i = 0; i < 3; i++) {
2814                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2815                                                  DP_SET_POWER_D0);
2816                         if (ret == 1)
2817                                 break;
2818                         msleep(1);
2819                 }
2820
2821                 if (ret == 1 && lspcon->active)
2822                         lspcon_wait_pcon_mode(lspcon);
2823         }
2824
2825         if (ret != 1)
2826                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2827                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2828 }
2829
2830 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
2831                                  enum port port, enum pipe *pipe)
2832 {
2833         enum pipe p;
2834
2835         for_each_pipe(dev_priv, p) {
2836                 u32 val = I915_READ(TRANS_DP_CTL(p));
2837
2838                 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
2839                         *pipe = p;
2840                         return true;
2841                 }
2842         }
2843
2844         DRM_DEBUG_KMS("No pipe for DP port %c found\n", port_name(port));
2845
2846         /* must initialize pipe to something for the asserts */
2847         *pipe = PIPE_A;
2848
2849         return false;
2850 }
2851
2852 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
2853                            i915_reg_t dp_reg, enum port port,
2854                            enum pipe *pipe)
2855 {
2856         bool ret;
2857         u32 val;
2858
2859         val = I915_READ(dp_reg);
2860
2861         ret = val & DP_PORT_EN;
2862
2863         /* asserts want to know the pipe even if the port is disabled */
2864         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
2865                 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
2866         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
2867                 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
2868         else if (IS_CHERRYVIEW(dev_priv))
2869                 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
2870         else
2871                 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
2872
2873         return ret;
2874 }
2875
2876 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2877                                   enum pipe *pipe)
2878 {
2879         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2880         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2881         bool ret;
2882
2883         if (!intel_display_power_get_if_enabled(dev_priv,
2884                                                 encoder->power_domain))
2885                 return false;
2886
2887         ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
2888                                     encoder->port, pipe);
2889
2890         intel_display_power_put(dev_priv, encoder->power_domain);
2891
2892         return ret;
2893 }
2894
2895 static void intel_dp_get_config(struct intel_encoder *encoder,
2896                                 struct intel_crtc_state *pipe_config)
2897 {
2898         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2899         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2900         u32 tmp, flags = 0;
2901         enum port port = encoder->port;
2902         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2903
2904         if (encoder->type == INTEL_OUTPUT_EDP)
2905                 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
2906         else
2907                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
2908
2909         tmp = I915_READ(intel_dp->output_reg);
2910
2911         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2912
2913         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2914                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2915
2916                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2917                         flags |= DRM_MODE_FLAG_PHSYNC;
2918                 else
2919                         flags |= DRM_MODE_FLAG_NHSYNC;
2920
2921                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2922                         flags |= DRM_MODE_FLAG_PVSYNC;
2923                 else
2924                         flags |= DRM_MODE_FLAG_NVSYNC;
2925         } else {
2926                 if (tmp & DP_SYNC_HS_HIGH)
2927                         flags |= DRM_MODE_FLAG_PHSYNC;
2928                 else
2929                         flags |= DRM_MODE_FLAG_NHSYNC;
2930
2931                 if (tmp & DP_SYNC_VS_HIGH)
2932                         flags |= DRM_MODE_FLAG_PVSYNC;
2933                 else
2934                         flags |= DRM_MODE_FLAG_NVSYNC;
2935         }
2936
2937         pipe_config->base.adjusted_mode.flags |= flags;
2938
2939         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
2940                 pipe_config->limited_color_range = true;
2941
2942         pipe_config->lane_count =
2943                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2944
2945         intel_dp_get_m_n(crtc, pipe_config);
2946
2947         if (port == PORT_A) {
2948                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2949                         pipe_config->port_clock = 162000;
2950                 else
2951                         pipe_config->port_clock = 270000;
2952         }
2953
2954         pipe_config->base.adjusted_mode.crtc_clock =
2955                 intel_dotclock_calculate(pipe_config->port_clock,
2956                                          &pipe_config->dp_m_n);
2957
2958         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2959             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2960                 /*
2961                  * This is a big fat ugly hack.
2962                  *
2963                  * Some machines in UEFI boot mode provide us a VBT that has 18
2964                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2965                  * unknown we fail to light up. Yet the same BIOS boots up with
2966                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2967                  * max, not what it tells us to use.
2968                  *
2969                  * Note: This will still be broken if the eDP panel is not lit
2970                  * up by the BIOS, and thus we can't get the mode at module
2971                  * load.
2972                  */
2973                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2974                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2975                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2976         }
2977 }
2978
2979 static void intel_disable_dp(struct intel_encoder *encoder,
2980                              const struct intel_crtc_state *old_crtc_state,
2981                              const struct drm_connector_state *old_conn_state)
2982 {
2983         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2984
2985         intel_dp->link_trained = false;
2986
2987         if (old_crtc_state->has_audio)
2988                 intel_audio_codec_disable(encoder,
2989                                           old_crtc_state, old_conn_state);
2990
2991         /* Make sure the panel is off before trying to change the mode. But also
2992          * ensure that we have vdd while we switch off the panel. */
2993         intel_edp_panel_vdd_on(intel_dp);
2994         intel_edp_backlight_off(old_conn_state);
2995         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2996         intel_edp_panel_off(intel_dp);
2997 }
2998
2999 static void g4x_disable_dp(struct intel_encoder *encoder,
3000                            const struct intel_crtc_state *old_crtc_state,
3001                            const struct drm_connector_state *old_conn_state)
3002 {
3003         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3004 }
3005
3006 static void vlv_disable_dp(struct intel_encoder *encoder,
3007                            const struct intel_crtc_state *old_crtc_state,
3008                            const struct drm_connector_state *old_conn_state)
3009 {
3010         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3011 }
3012
3013 static void g4x_post_disable_dp(struct intel_encoder *encoder,
3014                                 const struct intel_crtc_state *old_crtc_state,
3015                                 const struct drm_connector_state *old_conn_state)
3016 {
3017         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3018         enum port port = encoder->port;
3019
3020         /*
3021          * Bspec does not list a specific disable sequence for g4x DP.
3022          * Follow the ilk+ sequence (disable pipe before the port) for
3023          * g4x DP as it does not suffer from underruns like the normal
3024          * g4x modeset sequence (disable pipe after the port).
3025          */
3026         intel_dp_link_down(encoder, old_crtc_state);
3027
3028         /* Only ilk+ has port A */
3029         if (port == PORT_A)
3030                 ironlake_edp_pll_off(intel_dp, old_crtc_state);
3031 }
3032
3033 static void vlv_post_disable_dp(struct intel_encoder *encoder,
3034                                 const struct intel_crtc_state *old_crtc_state,
3035                                 const struct drm_connector_state *old_conn_state)
3036 {
3037         intel_dp_link_down(encoder, old_crtc_state);
3038 }
3039
3040 static void chv_post_disable_dp(struct intel_encoder *encoder,
3041                                 const struct intel_crtc_state *old_crtc_state,
3042                                 const struct drm_connector_state *old_conn_state)
3043 {
3044         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3045
3046         intel_dp_link_down(encoder, old_crtc_state);
3047
3048         mutex_lock(&dev_priv->sb_lock);
3049
3050         /* Assert data lane reset */
3051         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
3052
3053         mutex_unlock(&dev_priv->sb_lock);
3054 }
3055
3056 static void
3057 _intel_dp_set_link_train(struct intel_dp *intel_dp,
3058                          uint32_t *DP,
3059                          uint8_t dp_train_pat)
3060 {
3061         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3062         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3063         enum port port = intel_dig_port->base.port;
3064         uint8_t train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
3065
3066         if (dp_train_pat & train_pat_mask)
3067                 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
3068                               dp_train_pat & train_pat_mask);
3069
3070         if (HAS_DDI(dev_priv)) {
3071                 uint32_t temp = I915_READ(DP_TP_CTL(port));
3072
3073                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
3074                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
3075                 else
3076                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
3077
3078                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3079                 switch (dp_train_pat & train_pat_mask) {
3080                 case DP_TRAINING_PATTERN_DISABLE:
3081                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3082
3083                         break;
3084                 case DP_TRAINING_PATTERN_1:
3085                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3086                         break;
3087                 case DP_TRAINING_PATTERN_2:
3088                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3089                         break;
3090                 case DP_TRAINING_PATTERN_3:
3091                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3092                         break;
3093                 case DP_TRAINING_PATTERN_4:
3094                         temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3095                         break;
3096                 }
3097                 I915_WRITE(DP_TP_CTL(port), temp);
3098
3099         } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3100                    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3101                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
3102
3103                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3104                 case DP_TRAINING_PATTERN_DISABLE:
3105                         *DP |= DP_LINK_TRAIN_OFF_CPT;
3106                         break;
3107                 case DP_TRAINING_PATTERN_1:
3108                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
3109                         break;
3110                 case DP_TRAINING_PATTERN_2:
3111                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3112                         break;
3113                 case DP_TRAINING_PATTERN_3:
3114                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3115                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3116                         break;
3117                 }
3118
3119         } else {
3120                 *DP &= ~DP_LINK_TRAIN_MASK;
3121
3122                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3123                 case DP_TRAINING_PATTERN_DISABLE:
3124                         *DP |= DP_LINK_TRAIN_OFF;
3125                         break;
3126                 case DP_TRAINING_PATTERN_1:
3127                         *DP |= DP_LINK_TRAIN_PAT_1;
3128                         break;
3129                 case DP_TRAINING_PATTERN_2:
3130                         *DP |= DP_LINK_TRAIN_PAT_2;
3131                         break;
3132                 case DP_TRAINING_PATTERN_3:
3133                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3134                         *DP |= DP_LINK_TRAIN_PAT_2;
3135                         break;
3136                 }
3137         }
3138 }
3139
3140 static void intel_dp_enable_port(struct intel_dp *intel_dp,
3141                                  const struct intel_crtc_state *old_crtc_state)
3142 {
3143         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3144
3145         /* enable with pattern 1 (as per spec) */
3146
3147         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
3148
3149         /*
3150          * Magic for VLV/CHV. We _must_ first set up the register
3151          * without actually enabling the port, and then do another
3152          * write to enable the port. Otherwise link training will
3153          * fail when the power sequencer is freshly used for this port.
3154          */
3155         intel_dp->DP |= DP_PORT_EN;
3156         if (old_crtc_state->has_audio)
3157                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
3158
3159         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3160         POSTING_READ(intel_dp->output_reg);
3161 }
3162
3163 static void intel_enable_dp(struct intel_encoder *encoder,
3164                             const struct intel_crtc_state *pipe_config,
3165                             const struct drm_connector_state *conn_state)
3166 {
3167         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3168         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3169         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3170         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
3171         enum pipe pipe = crtc->pipe;
3172
3173         if (WARN_ON(dp_reg & DP_PORT_EN))
3174                 return;
3175
3176         pps_lock(intel_dp);
3177
3178         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3179                 vlv_init_panel_power_sequencer(encoder, pipe_config);
3180
3181         intel_dp_enable_port(intel_dp, pipe_config);
3182
3183         edp_panel_vdd_on(intel_dp);
3184         edp_panel_on(intel_dp);
3185         edp_panel_vdd_off(intel_dp, true);
3186
3187         pps_unlock(intel_dp);
3188
3189         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3190                 unsigned int lane_mask = 0x0;
3191
3192                 if (IS_CHERRYVIEW(dev_priv))
3193                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
3194
3195                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
3196                                     lane_mask);
3197         }
3198
3199         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3200         intel_dp_start_link_train(intel_dp);
3201         intel_dp_stop_link_train(intel_dp);
3202
3203         if (pipe_config->has_audio) {
3204                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
3205                                  pipe_name(pipe));
3206                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
3207         }
3208 }
3209
3210 static void g4x_enable_dp(struct intel_encoder *encoder,
3211                           const struct intel_crtc_state *pipe_config,
3212                           const struct drm_connector_state *conn_state)
3213 {
3214         intel_enable_dp(encoder, pipe_config, conn_state);
3215         intel_edp_backlight_on(pipe_config, conn_state);
3216 }
3217
3218 static void vlv_enable_dp(struct intel_encoder *encoder,
3219                           const struct intel_crtc_state *pipe_config,
3220                           const struct drm_connector_state *conn_state)
3221 {
3222         intel_edp_backlight_on(pipe_config, conn_state);
3223 }
3224
3225 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
3226                               const struct intel_crtc_state *pipe_config,
3227                               const struct drm_connector_state *conn_state)
3228 {
3229         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3230         enum port port = encoder->port;
3231
3232         intel_dp_prepare(encoder, pipe_config);
3233
3234         /* Only ilk+ has port A */
3235         if (port == PORT_A)
3236                 ironlake_edp_pll_on(intel_dp, pipe_config);
3237 }
3238
3239 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
3240 {
3241         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3242         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3243         enum pipe pipe = intel_dp->pps_pipe;
3244         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
3245
3246         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3247
3248         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
3249                 return;
3250
3251         edp_panel_vdd_off_sync(intel_dp);
3252
3253         /*
3254          * VLV seems to get confused when multiple power sequencers
3255          * have the same port selected (even if only one has power/vdd
3256          * enabled). The failure manifests as vlv_wait_port_ready() failing
3257          * CHV on the other hand doesn't seem to mind having the same port
3258          * selected in multiple power sequencers, but let's clear the
3259          * port select always when logically disconnecting a power sequencer
3260          * from a port.
3261          */
3262         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
3263                       pipe_name(pipe), port_name(intel_dig_port->base.port));
3264         I915_WRITE(pp_on_reg, 0);
3265         POSTING_READ(pp_on_reg);
3266
3267         intel_dp->pps_pipe = INVALID_PIPE;
3268 }
3269
3270 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
3271                                       enum pipe pipe)
3272 {
3273         struct intel_encoder *encoder;
3274
3275         lockdep_assert_held(&dev_priv->pps_mutex);
3276
3277         for_each_intel_dp(&dev_priv->drm, encoder) {
3278                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3279                 enum port port = encoder->port;
3280
3281                 WARN(intel_dp->active_pipe == pipe,
3282                      "stealing pipe %c power sequencer from active (e)DP port %c\n",
3283                      pipe_name(pipe), port_name(port));
3284
3285                 if (intel_dp->pps_pipe != pipe)
3286                         continue;
3287
3288                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
3289                               pipe_name(pipe), port_name(port));
3290
3291                 /* make sure vdd is off before we steal it */
3292                 vlv_detach_power_sequencer(intel_dp);
3293         }
3294 }
3295
3296 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3297                                            const struct intel_crtc_state *crtc_state)
3298 {
3299         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3300         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3301         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3302
3303         lockdep_assert_held(&dev_priv->pps_mutex);
3304
3305         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3306
3307         if (intel_dp->pps_pipe != INVALID_PIPE &&
3308             intel_dp->pps_pipe != crtc->pipe) {
3309                 /*
3310                  * If another power sequencer was being used on this
3311                  * port previously make sure to turn off vdd there while
3312                  * we still have control of it.
3313                  */
3314                 vlv_detach_power_sequencer(intel_dp);
3315         }
3316
3317         /*
3318          * We may be stealing the power
3319          * sequencer from another port.
3320          */
3321         vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3322
3323         intel_dp->active_pipe = crtc->pipe;
3324
3325         if (!intel_dp_is_edp(intel_dp))
3326                 return;
3327
3328         /* now it's all ours */
3329         intel_dp->pps_pipe = crtc->pipe;
3330
3331         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3332                       pipe_name(intel_dp->pps_pipe), port_name(encoder->port));
3333
3334         /* init power sequencer on this pipe and port */
3335         intel_dp_init_panel_power_sequencer(intel_dp);
3336         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
3337 }
3338
3339 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3340                               const struct intel_crtc_state *pipe_config,
3341                               const struct drm_connector_state *conn_state)
3342 {
3343         vlv_phy_pre_encoder_enable(encoder, pipe_config);
3344
3345         intel_enable_dp(encoder, pipe_config, conn_state);
3346 }
3347
3348 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3349                                   const struct intel_crtc_state *pipe_config,
3350                                   const struct drm_connector_state *conn_state)
3351 {
3352         intel_dp_prepare(encoder, pipe_config);
3353
3354         vlv_phy_pre_pll_enable(encoder, pipe_config);
3355 }
3356
3357 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3358                               const struct intel_crtc_state *pipe_config,
3359                               const struct drm_connector_state *conn_state)
3360 {
3361         chv_phy_pre_encoder_enable(encoder, pipe_config);
3362
3363         intel_enable_dp(encoder, pipe_config, conn_state);
3364
3365         /* Second common lane will stay alive on its own now */
3366         chv_phy_release_cl2_override(encoder);
3367 }
3368
3369 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3370                                   const struct intel_crtc_state *pipe_config,
3371                                   const struct drm_connector_state *conn_state)
3372 {
3373         intel_dp_prepare(encoder, pipe_config);
3374
3375         chv_phy_pre_pll_enable(encoder, pipe_config);
3376 }
3377
3378 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3379                                     const struct intel_crtc_state *old_crtc_state,
3380                                     const struct drm_connector_state *old_conn_state)
3381 {
3382         chv_phy_post_pll_disable(encoder, old_crtc_state);
3383 }
3384
3385 /*
3386  * Fetch AUX CH registers 0x202 - 0x207 which contain
3387  * link status information
3388  */
3389 bool
3390 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3391 {
3392         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3393                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3394 }
3395
3396 /* These are source-specific values. */
3397 uint8_t
3398 intel_dp_voltage_max(struct intel_dp *intel_dp)
3399 {
3400         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3401         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3402         enum port port = encoder->port;
3403
3404         if (HAS_DDI(dev_priv))
3405                 return intel_ddi_dp_voltage_max(encoder);
3406         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3407                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3408         else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3409                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3410         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3411                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3412         else
3413                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3414 }
3415
3416 uint8_t
3417 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3418 {
3419         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3420         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3421         enum port port = encoder->port;
3422
3423         if (HAS_DDI(dev_priv)) {
3424                 return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
3425         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3426                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3427                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3428                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3429                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3430                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3431                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3432                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3433                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3434                 default:
3435                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3436                 }
3437         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3438                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3439                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3440                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3441                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3442                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3443                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3444                 default:
3445                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3446                 }
3447         } else {
3448                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3449                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3450                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3451                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3452                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3453                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3454                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3455                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3456                 default:
3457                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3458                 }
3459         }
3460 }
3461
3462 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3463 {
3464         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3465         unsigned long demph_reg_value, preemph_reg_value,
3466                 uniqtranscale_reg_value;
3467         uint8_t train_set = intel_dp->train_set[0];
3468
3469         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3470         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3471                 preemph_reg_value = 0x0004000;
3472                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3473                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3474                         demph_reg_value = 0x2B405555;
3475                         uniqtranscale_reg_value = 0x552AB83A;
3476                         break;
3477                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3478                         demph_reg_value = 0x2B404040;
3479                         uniqtranscale_reg_value = 0x5548B83A;
3480                         break;
3481                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3482                         demph_reg_value = 0x2B245555;
3483                         uniqtranscale_reg_value = 0x5560B83A;
3484                         break;
3485                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3486                         demph_reg_value = 0x2B405555;
3487                         uniqtranscale_reg_value = 0x5598DA3A;
3488                         break;
3489                 default:
3490                         return 0;
3491                 }
3492                 break;
3493         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3494                 preemph_reg_value = 0x0002000;
3495                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3496                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3497                         demph_reg_value = 0x2B404040;
3498                         uniqtranscale_reg_value = 0x5552B83A;
3499                         break;
3500                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3501                         demph_reg_value = 0x2B404848;
3502                         uniqtranscale_reg_value = 0x5580B83A;
3503                         break;
3504                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3505                         demph_reg_value = 0x2B404040;
3506                         uniqtranscale_reg_value = 0x55ADDA3A;
3507                         break;
3508                 default:
3509                         return 0;
3510                 }
3511                 break;
3512         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3513                 preemph_reg_value = 0x0000000;
3514                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3515                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3516                         demph_reg_value = 0x2B305555;
3517                         uniqtranscale_reg_value = 0x5570B83A;
3518                         break;
3519                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3520                         demph_reg_value = 0x2B2B4040;
3521                         uniqtranscale_reg_value = 0x55ADDA3A;
3522                         break;
3523                 default:
3524                         return 0;
3525                 }
3526                 break;
3527         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3528                 preemph_reg_value = 0x0006000;
3529                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3530                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3531                         demph_reg_value = 0x1B405555;
3532                         uniqtranscale_reg_value = 0x55ADDA3A;
3533                         break;
3534                 default:
3535                         return 0;
3536                 }
3537                 break;
3538         default:
3539                 return 0;
3540         }
3541
3542         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3543                                  uniqtranscale_reg_value, 0);
3544
3545         return 0;
3546 }
3547
3548 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3549 {
3550         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3551         u32 deemph_reg_value, margin_reg_value;
3552         bool uniq_trans_scale = false;
3553         uint8_t train_set = intel_dp->train_set[0];
3554
3555         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3556         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3557                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3558                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3559                         deemph_reg_value = 128;
3560                         margin_reg_value = 52;
3561                         break;
3562                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3563                         deemph_reg_value = 128;
3564                         margin_reg_value = 77;
3565                         break;
3566                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3567                         deemph_reg_value = 128;
3568                         margin_reg_value = 102;
3569                         break;
3570                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3571                         deemph_reg_value = 128;
3572                         margin_reg_value = 154;
3573                         uniq_trans_scale = true;
3574                         break;
3575                 default:
3576                         return 0;
3577                 }
3578                 break;
3579         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3580                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3581                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3582                         deemph_reg_value = 85;
3583                         margin_reg_value = 78;
3584                         break;
3585                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3586                         deemph_reg_value = 85;
3587                         margin_reg_value = 116;
3588                         break;
3589                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3590                         deemph_reg_value = 85;
3591                         margin_reg_value = 154;
3592                         break;
3593                 default:
3594                         return 0;
3595                 }
3596                 break;
3597         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3598                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3599                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3600                         deemph_reg_value = 64;
3601                         margin_reg_value = 104;
3602                         break;
3603                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3604                         deemph_reg_value = 64;
3605                         margin_reg_value = 154;
3606                         break;
3607                 default:
3608                         return 0;
3609                 }
3610                 break;
3611         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3612                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3613                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3614                         deemph_reg_value = 43;
3615                         margin_reg_value = 154;
3616                         break;
3617                 default:
3618                         return 0;
3619                 }
3620                 break;
3621         default:
3622                 return 0;
3623         }
3624
3625         chv_set_phy_signal_level(encoder, deemph_reg_value,
3626                                  margin_reg_value, uniq_trans_scale);
3627
3628         return 0;
3629 }
3630
3631 static uint32_t
3632 g4x_signal_levels(uint8_t train_set)
3633 {
3634         uint32_t        signal_levels = 0;
3635
3636         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3637         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3638         default:
3639                 signal_levels |= DP_VOLTAGE_0_4;
3640                 break;
3641         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3642                 signal_levels |= DP_VOLTAGE_0_6;
3643                 break;
3644         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3645                 signal_levels |= DP_VOLTAGE_0_8;
3646                 break;
3647         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3648                 signal_levels |= DP_VOLTAGE_1_2;
3649                 break;
3650         }
3651         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3652         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3653         default:
3654                 signal_levels |= DP_PRE_EMPHASIS_0;
3655                 break;
3656         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3657                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3658                 break;
3659         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3660                 signal_levels |= DP_PRE_EMPHASIS_6;
3661                 break;
3662         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3663                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3664                 break;
3665         }
3666         return signal_levels;
3667 }
3668
3669 /* SNB CPU eDP voltage swing and pre-emphasis control */
3670 static uint32_t
3671 snb_cpu_edp_signal_levels(uint8_t train_set)
3672 {
3673         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3674                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3675         switch (signal_levels) {
3676         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3677         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3678                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3679         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3680                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3681         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3682         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3683                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3684         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3685         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3686                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3687         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3688         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3689                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3690         default:
3691                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3692                               "0x%x\n", signal_levels);
3693                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3694         }
3695 }
3696
3697 /* IVB CPU eDP voltage swing and pre-emphasis control */
3698 static uint32_t
3699 ivb_cpu_edp_signal_levels(uint8_t train_set)
3700 {
3701         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3702                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3703         switch (signal_levels) {
3704         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3705                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3706         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3707                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3708         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3709                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3710
3711         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3712                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3713         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3714                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3715
3716         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3717                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3718         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3719                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3720
3721         default:
3722                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3723                               "0x%x\n", signal_levels);
3724                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3725         }
3726 }
3727
3728 void
3729 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3730 {
3731         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3732         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3733         enum port port = intel_dig_port->base.port;
3734         uint32_t signal_levels, mask = 0;
3735         uint8_t train_set = intel_dp->train_set[0];
3736
3737         if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
3738                 signal_levels = bxt_signal_levels(intel_dp);
3739         } else if (HAS_DDI(dev_priv)) {
3740                 signal_levels = ddi_signal_levels(intel_dp);
3741                 mask = DDI_BUF_EMP_MASK;
3742         } else if (IS_CHERRYVIEW(dev_priv)) {
3743                 signal_levels = chv_signal_levels(intel_dp);
3744         } else if (IS_VALLEYVIEW(dev_priv)) {
3745                 signal_levels = vlv_signal_levels(intel_dp);
3746         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3747                 signal_levels = ivb_cpu_edp_signal_levels(train_set);
3748                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3749         } else if (IS_GEN6(dev_priv) && port == PORT_A) {
3750                 signal_levels = snb_cpu_edp_signal_levels(train_set);
3751                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3752         } else {
3753                 signal_levels = g4x_signal_levels(train_set);
3754                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3755         }
3756
3757         if (mask)
3758                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3759
3760         DRM_DEBUG_KMS("Using vswing level %d\n",
3761                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3762         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3763                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3764                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3765
3766         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3767
3768         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3769         POSTING_READ(intel_dp->output_reg);
3770 }
3771
3772 void
3773 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3774                                        uint8_t dp_train_pat)
3775 {
3776         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3777         struct drm_i915_private *dev_priv =
3778                 to_i915(intel_dig_port->base.base.dev);
3779
3780         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3781
3782         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3783         POSTING_READ(intel_dp->output_reg);
3784 }
3785
3786 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3787 {
3788         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3789         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3790         enum port port = intel_dig_port->base.port;
3791         uint32_t val;
3792
3793         if (!HAS_DDI(dev_priv))
3794                 return;
3795
3796         val = I915_READ(DP_TP_CTL(port));
3797         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3798         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3799         I915_WRITE(DP_TP_CTL(port), val);
3800
3801         /*
3802          * On PORT_A we can have only eDP in SST mode. There the only reason
3803          * we need to set idle transmission mode is to work around a HW issue
3804          * where we enable the pipe while not in idle link-training mode.
3805          * In this case there is requirement to wait for a minimum number of
3806          * idle patterns to be sent.
3807          */
3808         if (port == PORT_A)
3809                 return;
3810
3811         if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3812                                     DP_TP_STATUS_IDLE_DONE,
3813                                     DP_TP_STATUS_IDLE_DONE,
3814                                     1))
3815                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3816 }
3817
3818 static void
3819 intel_dp_link_down(struct intel_encoder *encoder,
3820                    const struct intel_crtc_state *old_crtc_state)
3821 {
3822         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3823         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3824         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
3825         enum port port = encoder->port;
3826         uint32_t DP = intel_dp->DP;
3827
3828         if (WARN_ON(HAS_DDI(dev_priv)))
3829                 return;
3830
3831         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3832                 return;
3833
3834         DRM_DEBUG_KMS("\n");
3835
3836         if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3837             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3838                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3839                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3840         } else {
3841                 DP &= ~DP_LINK_TRAIN_MASK;
3842                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3843         }
3844         I915_WRITE(intel_dp->output_reg, DP);
3845         POSTING_READ(intel_dp->output_reg);
3846
3847         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3848         I915_WRITE(intel_dp->output_reg, DP);
3849         POSTING_READ(intel_dp->output_reg);
3850
3851         /*
3852          * HW workaround for IBX, we need to move the port
3853          * to transcoder A after disabling it to allow the
3854          * matching HDMI port to be enabled on transcoder A.
3855          */
3856         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3857                 /*
3858                  * We get CPU/PCH FIFO underruns on the other pipe when
3859                  * doing the workaround. Sweep them under the rug.
3860                  */
3861                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3862                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3863
3864                 /* always enable with pattern 1 (as per spec) */
3865                 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
3866                 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
3867                         DP_LINK_TRAIN_PAT_1;
3868                 I915_WRITE(intel_dp->output_reg, DP);
3869                 POSTING_READ(intel_dp->output_reg);
3870
3871                 DP &= ~DP_PORT_EN;
3872                 I915_WRITE(intel_dp->output_reg, DP);
3873                 POSTING_READ(intel_dp->output_reg);
3874
3875                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
3876                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3877                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3878         }
3879
3880         msleep(intel_dp->panel_power_down_delay);
3881
3882         intel_dp->DP = DP;
3883
3884         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3885                 pps_lock(intel_dp);
3886                 intel_dp->active_pipe = INVALID_PIPE;
3887                 pps_unlock(intel_dp);
3888         }
3889 }
3890
3891 bool
3892 intel_dp_read_dpcd(struct intel_dp *intel_dp)
3893 {
3894         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3895                              sizeof(intel_dp->dpcd)) < 0)
3896                 return false; /* aux transfer failed */
3897
3898         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3899
3900         return intel_dp->dpcd[DP_DPCD_REV] != 0;
3901 }
3902
3903 static bool
3904 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3905 {
3906         struct drm_i915_private *dev_priv =
3907                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3908
3909         /* this function is meant to be called only once */
3910         WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
3911
3912         if (!intel_dp_read_dpcd(intel_dp))
3913                 return false;
3914
3915         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3916                          drm_dp_is_branch(intel_dp->dpcd));
3917
3918         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3919                 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3920                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3921
3922         /*
3923          * Read the eDP display control registers.
3924          *
3925          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
3926          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
3927          * set, but require eDP 1.4+ detection (e.g. for supported link rates
3928          * method). The display control registers should read zero if they're
3929          * not supported anyway.
3930          */
3931         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3932                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3933                              sizeof(intel_dp->edp_dpcd))
3934                 DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3935                               intel_dp->edp_dpcd);
3936
3937         /*
3938          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
3939          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
3940          */
3941         intel_psr_init_dpcd(intel_dp);
3942
3943         /* Read the eDP 1.4+ supported link rates. */
3944         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
3945                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3946                 int i;
3947
3948                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3949                                 sink_rates, sizeof(sink_rates));
3950
3951                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3952                         int val = le16_to_cpu(sink_rates[i]);
3953
3954                         if (val == 0)
3955                                 break;
3956
3957                         /* Value read multiplied by 200kHz gives the per-lane
3958                          * link rate in kHz. The source rates are, however,
3959                          * stored in terms of LS_Clk kHz. The full conversion
3960                          * back to symbols is
3961                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3962                          */
3963                         intel_dp->sink_rates[i] = (val * 200) / 10;
3964                 }
3965                 intel_dp->num_sink_rates = i;
3966         }
3967
3968         /*
3969          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
3970          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
3971          */
3972         if (intel_dp->num_sink_rates)
3973                 intel_dp->use_rate_select = true;
3974         else
3975                 intel_dp_set_sink_rates(intel_dp);
3976
3977         intel_dp_set_common_rates(intel_dp);
3978
3979         return true;
3980 }
3981
3982
3983 static bool
3984 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3985 {
3986         u8 sink_count;
3987
3988         if (!intel_dp_read_dpcd(intel_dp))
3989                 return false;
3990
3991         /* Don't clobber cached eDP rates. */
3992         if (!intel_dp_is_edp(intel_dp)) {
3993                 intel_dp_set_sink_rates(intel_dp);
3994                 intel_dp_set_common_rates(intel_dp);
3995         }
3996
3997         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &sink_count) <= 0)
3998                 return false;
3999
4000         /*
4001          * Sink count can change between short pulse hpd hence
4002          * a member variable in intel_dp will track any changes
4003          * between short pulse interrupts.
4004          */
4005         intel_dp->sink_count = DP_GET_SINK_COUNT(sink_count);
4006
4007         /*
4008          * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4009          * a dongle is present but no display. Unless we require to know
4010          * if a dongle is present or not, we don't need to update
4011          * downstream port information. So, an early return here saves
4012          * time from performing other operations which are not required.
4013          */
4014         if (!intel_dp_is_edp(intel_dp) && !intel_dp->sink_count)
4015                 return false;
4016
4017         if (!drm_dp_is_branch(intel_dp->dpcd))
4018                 return true; /* native DP sink */
4019
4020         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
4021                 return true; /* no per-port downstream info */
4022
4023         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
4024                              intel_dp->downstream_ports,
4025                              DP_MAX_DOWNSTREAM_PORTS) < 0)
4026                 return false; /* downstream port status fetch failed */
4027
4028         return true;
4029 }
4030
4031 static bool
4032 intel_dp_can_mst(struct intel_dp *intel_dp)
4033 {
4034         u8 mstm_cap;
4035
4036         if (!i915_modparams.enable_dp_mst)
4037                 return false;
4038
4039         if (!intel_dp->can_mst)
4040                 return false;
4041
4042         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
4043                 return false;
4044
4045         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
4046                 return false;
4047
4048         return mstm_cap & DP_MST_CAP;
4049 }
4050
4051 static void
4052 intel_dp_configure_mst(struct intel_dp *intel_dp)
4053 {
4054         if (!i915_modparams.enable_dp_mst)
4055                 return;
4056
4057         if (!intel_dp->can_mst)
4058                 return;
4059
4060         intel_dp->is_mst = intel_dp_can_mst(intel_dp);
4061
4062         if (intel_dp->is_mst)
4063                 DRM_DEBUG_KMS("Sink is MST capable\n");
4064         else
4065                 DRM_DEBUG_KMS("Sink is not MST capable\n");
4066
4067         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4068                                         intel_dp->is_mst);
4069 }
4070
4071 static bool
4072 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4073 {
4074         return drm_dp_dpcd_readb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
4075                                  sink_irq_vector) == 1;
4076 }
4077
4078 static bool
4079 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4080 {
4081         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4082                                 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4083                 DP_DPRX_ESI_LEN;
4084 }
4085
4086 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4087 {
4088         int status = 0;
4089         int test_link_rate;
4090         uint8_t test_lane_count, test_link_bw;
4091         /* (DP CTS 1.2)
4092          * 4.3.1.11
4093          */
4094         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4095         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4096                                    &test_lane_count);
4097
4098         if (status <= 0) {
4099                 DRM_DEBUG_KMS("Lane count read failed\n");
4100                 return DP_TEST_NAK;
4101         }
4102         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4103
4104         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4105                                    &test_link_bw);
4106         if (status <= 0) {
4107                 DRM_DEBUG_KMS("Link Rate read failed\n");
4108                 return DP_TEST_NAK;
4109         }
4110         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4111
4112         /* Validate the requested link rate and lane count */
4113         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4114                                         test_lane_count))
4115                 return DP_TEST_NAK;
4116
4117         intel_dp->compliance.test_lane_count = test_lane_count;
4118         intel_dp->compliance.test_link_rate = test_link_rate;
4119
4120         return DP_TEST_ACK;
4121 }
4122
4123 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4124 {
4125         uint8_t test_pattern;
4126         uint8_t test_misc;
4127         __be16 h_width, v_height;
4128         int status = 0;
4129
4130         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4131         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4132                                    &test_pattern);
4133         if (status <= 0) {
4134                 DRM_DEBUG_KMS("Test pattern read failed\n");
4135                 return DP_TEST_NAK;
4136         }
4137         if (test_pattern != DP_COLOR_RAMP)
4138                 return DP_TEST_NAK;
4139
4140         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4141                                   &h_width, 2);
4142         if (status <= 0) {
4143                 DRM_DEBUG_KMS("H Width read failed\n");
4144                 return DP_TEST_NAK;
4145         }
4146
4147         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4148                                   &v_height, 2);
4149         if (status <= 0) {
4150                 DRM_DEBUG_KMS("V Height read failed\n");
4151                 return DP_TEST_NAK;
4152         }
4153
4154         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4155                                    &test_misc);
4156         if (status <= 0) {
4157                 DRM_DEBUG_KMS("TEST MISC read failed\n");
4158                 return DP_TEST_NAK;
4159         }
4160         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4161                 return DP_TEST_NAK;
4162         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4163                 return DP_TEST_NAK;
4164         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4165         case DP_TEST_BIT_DEPTH_6:
4166                 intel_dp->compliance.test_data.bpc = 6;
4167                 break;
4168         case DP_TEST_BIT_DEPTH_8:
4169                 intel_dp->compliance.test_data.bpc = 8;
4170                 break;
4171         default:
4172                 return DP_TEST_NAK;
4173         }
4174
4175         intel_dp->compliance.test_data.video_pattern = test_pattern;
4176         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4177         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4178         /* Set test active flag here so userspace doesn't interrupt things */
4179         intel_dp->compliance.test_active = 1;
4180
4181         return DP_TEST_ACK;
4182 }
4183
4184 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4185 {
4186         uint8_t test_result = DP_TEST_ACK;
4187         struct intel_connector *intel_connector = intel_dp->attached_connector;
4188         struct drm_connector *connector = &intel_connector->base;
4189
4190         if (intel_connector->detect_edid == NULL ||
4191             connector->edid_corrupt ||
4192             intel_dp->aux.i2c_defer_count > 6) {
4193                 /* Check EDID read for NACKs, DEFERs and corruption
4194                  * (DP CTS 1.2 Core r1.1)
4195                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4196                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4197                  *    4.2.2.6 : EDID corruption detected
4198                  * Use failsafe mode for all cases
4199                  */
4200                 if (intel_dp->aux.i2c_nack_count > 0 ||
4201                         intel_dp->aux.i2c_defer_count > 0)
4202                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4203                                       intel_dp->aux.i2c_nack_count,
4204                                       intel_dp->aux.i2c_defer_count);
4205                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4206         } else {
4207                 struct edid *block = intel_connector->detect_edid;
4208
4209                 /* We have to write the checksum
4210                  * of the last block read
4211                  */
4212                 block += intel_connector->detect_edid->extensions;
4213
4214                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4215                                        block->checksum) <= 0)
4216                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4217
4218                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4219                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4220         }
4221
4222         /* Set test active flag here so userspace doesn't interrupt things */
4223         intel_dp->compliance.test_active = 1;
4224
4225         return test_result;
4226 }
4227
4228 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4229 {
4230         uint8_t test_result = DP_TEST_NAK;
4231         return test_result;
4232 }
4233
4234 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4235 {
4236         uint8_t response = DP_TEST_NAK;
4237         uint8_t request = 0;
4238         int status;
4239
4240         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4241         if (status <= 0) {
4242                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4243                 goto update_status;
4244         }
4245
4246         switch (request) {
4247         case DP_TEST_LINK_TRAINING:
4248                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4249                 response = intel_dp_autotest_link_training(intel_dp);
4250                 break;
4251         case DP_TEST_LINK_VIDEO_PATTERN:
4252                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4253                 response = intel_dp_autotest_video_pattern(intel_dp);
4254                 break;
4255         case DP_TEST_LINK_EDID_READ:
4256                 DRM_DEBUG_KMS("EDID test requested\n");
4257                 response = intel_dp_autotest_edid(intel_dp);
4258                 break;
4259         case DP_TEST_LINK_PHY_TEST_PATTERN:
4260                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4261                 response = intel_dp_autotest_phy_pattern(intel_dp);
4262                 break;
4263         default:
4264                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4265                 break;
4266         }
4267
4268         if (response & DP_TEST_ACK)
4269                 intel_dp->compliance.test_type = request;
4270
4271 update_status:
4272         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4273         if (status <= 0)
4274                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4275 }
4276
4277 static int
4278 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4279 {
4280         bool bret;
4281
4282         if (intel_dp->is_mst) {
4283                 u8 esi[DP_DPRX_ESI_LEN] = { 0 };
4284                 int ret = 0;
4285                 int retry;
4286                 bool handled;
4287
4288                 WARN_ON_ONCE(intel_dp->active_mst_links < 0);
4289                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4290 go_again:
4291                 if (bret == true) {
4292
4293                         /* check link status - esi[10] = 0x200c */
4294                         if (intel_dp->active_mst_links > 0 &&
4295                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4296                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4297                                 intel_dp_start_link_train(intel_dp);
4298                                 intel_dp_stop_link_train(intel_dp);
4299                         }
4300
4301                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4302                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4303
4304                         if (handled) {
4305                                 for (retry = 0; retry < 3; retry++) {
4306                                         int wret;
4307                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4308                                                                  DP_SINK_COUNT_ESI+1,
4309                                                                  &esi[1], 3);
4310                                         if (wret == 3) {
4311                                                 break;
4312                                         }
4313                                 }
4314
4315                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4316                                 if (bret == true) {
4317                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4318                                         goto go_again;
4319                                 }
4320                         } else
4321                                 ret = 0;
4322
4323                         return ret;
4324                 } else {
4325                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4326                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4327                         intel_dp->is_mst = false;
4328                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4329                         /* send a hotplug event */
4330                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4331                 }
4332         }
4333         return -EINVAL;
4334 }
4335
4336 static bool
4337 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4338 {
4339         u8 link_status[DP_LINK_STATUS_SIZE];
4340
4341         if (!intel_dp->link_trained)
4342                 return false;
4343
4344         if (!intel_dp_get_link_status(intel_dp, link_status))
4345                 return false;
4346
4347         /*
4348          * Validate the cached values of intel_dp->link_rate and
4349          * intel_dp->lane_count before attempting to retrain.
4350          */
4351         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4352                                         intel_dp->lane_count))
4353                 return false;
4354
4355         /* Retrain if Channel EQ or CR not ok */
4356         return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4357 }
4358
4359 int intel_dp_retrain_link(struct intel_encoder *encoder,
4360                           struct drm_modeset_acquire_ctx *ctx)
4361 {
4362         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4363         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4364         struct intel_connector *connector = intel_dp->attached_connector;
4365         struct drm_connector_state *conn_state;
4366         struct intel_crtc_state *crtc_state;
4367         struct intel_crtc *crtc;
4368         int ret;
4369
4370         /* FIXME handle the MST connectors as well */
4371
4372         if (!connector || connector->base.status != connector_status_connected)
4373                 return 0;
4374
4375         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4376                                ctx);
4377         if (ret)
4378                 return ret;
4379
4380         conn_state = connector->base.state;
4381
4382         crtc = to_intel_crtc(conn_state->crtc);
4383         if (!crtc)
4384                 return 0;
4385
4386         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4387         if (ret)
4388                 return ret;
4389
4390         crtc_state = to_intel_crtc_state(crtc->base.state);
4391
4392         WARN_ON(!intel_crtc_has_dp_encoder(crtc_state));
4393
4394         if (!crtc_state->base.active)
4395                 return 0;
4396
4397         if (conn_state->commit &&
4398             !try_wait_for_completion(&conn_state->commit->hw_done))
4399                 return 0;
4400
4401         if (!intel_dp_needs_link_retrain(intel_dp))
4402                 return 0;
4403
4404         /* Suppress underruns caused by re-training */
4405         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4406         if (crtc->config->has_pch_encoder)
4407                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4408                                                       intel_crtc_pch_transcoder(crtc), false);
4409
4410         intel_dp_start_link_train(intel_dp);
4411         intel_dp_stop_link_train(intel_dp);
4412
4413         /* Keep underrun reporting disabled until things are stable */
4414         intel_wait_for_vblank(dev_priv, crtc->pipe);
4415
4416         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4417         if (crtc->config->has_pch_encoder)
4418                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4419                                                       intel_crtc_pch_transcoder(crtc), true);
4420
4421         return 0;
4422 }
4423
4424 /*
4425  * If display is now connected check links status,
4426  * there has been known issues of link loss triggering
4427  * long pulse.
4428  *
4429  * Some sinks (eg. ASUS PB287Q) seem to perform some
4430  * weird HPD ping pong during modesets. So we can apparently
4431  * end up with HPD going low during a modeset, and then
4432  * going back up soon after. And once that happens we must
4433  * retrain the link to get a picture. That's in case no
4434  * userspace component reacted to intermittent HPD dip.
4435  */
4436 static bool intel_dp_hotplug(struct intel_encoder *encoder,
4437                              struct intel_connector *connector)
4438 {
4439         struct drm_modeset_acquire_ctx ctx;
4440         bool changed;
4441         int ret;
4442
4443         changed = intel_encoder_hotplug(encoder, connector);
4444
4445         drm_modeset_acquire_init(&ctx, 0);
4446
4447         for (;;) {
4448                 ret = intel_dp_retrain_link(encoder, &ctx);
4449
4450                 if (ret == -EDEADLK) {
4451                         drm_modeset_backoff(&ctx);
4452                         continue;
4453                 }
4454
4455                 break;
4456         }
4457
4458         drm_modeset_drop_locks(&ctx);
4459         drm_modeset_acquire_fini(&ctx);
4460         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4461
4462         return changed;
4463 }
4464
4465 /*
4466  * According to DP spec
4467  * 5.1.2:
4468  *  1. Read DPCD
4469  *  2. Configure link according to Receiver Capabilities
4470  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4471  *  4. Check link status on receipt of hot-plug interrupt
4472  *
4473  * intel_dp_short_pulse -  handles short pulse interrupts
4474  * when full detection is not required.
4475  * Returns %true if short pulse is handled and full detection
4476  * is NOT required and %false otherwise.
4477  */
4478 static bool
4479 intel_dp_short_pulse(struct intel_dp *intel_dp)
4480 {
4481         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4482         u8 sink_irq_vector = 0;
4483         u8 old_sink_count = intel_dp->sink_count;
4484         bool ret;
4485
4486         /*
4487          * Clearing compliance test variables to allow capturing
4488          * of values for next automated test request.
4489          */
4490         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4491
4492         /*
4493          * Now read the DPCD to see if it's actually running
4494          * If the current value of sink count doesn't match with
4495          * the value that was stored earlier or dpcd read failed
4496          * we need to do full detection
4497          */
4498         ret = intel_dp_get_dpcd(intel_dp);
4499
4500         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4501                 /* No need to proceed if we are going to do full detect */
4502                 return false;
4503         }
4504
4505         /* Try to read the source of the interrupt */
4506         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4507             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4508             sink_irq_vector != 0) {
4509                 /* Clear interrupt source */
4510                 drm_dp_dpcd_writeb(&intel_dp->aux,
4511                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4512                                    sink_irq_vector);
4513
4514                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4515                         intel_dp_handle_test_request(intel_dp);
4516                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4517                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4518         }
4519
4520         /* Handle CEC interrupts, if any */
4521         drm_dp_cec_irq(&intel_dp->aux);
4522
4523         /* defer to the hotplug work for link retraining if needed */
4524         if (intel_dp_needs_link_retrain(intel_dp))
4525                 return false;
4526
4527         intel_psr_short_pulse(intel_dp);
4528
4529         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
4530                 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4531                 /* Send a Hotplug Uevent to userspace to start modeset */
4532                 drm_kms_helper_hotplug_event(&dev_priv->drm);
4533         }
4534
4535         return true;
4536 }
4537
4538 /* XXX this is probably wrong for multiple downstream ports */
4539 static enum drm_connector_status
4540 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4541 {
4542         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4543         uint8_t *dpcd = intel_dp->dpcd;
4544         uint8_t type;
4545
4546         if (lspcon->active)
4547                 lspcon_resume(lspcon);
4548
4549         if (!intel_dp_get_dpcd(intel_dp))
4550                 return connector_status_disconnected;
4551
4552         if (intel_dp_is_edp(intel_dp))
4553                 return connector_status_connected;
4554
4555         /* if there's no downstream port, we're done */
4556         if (!drm_dp_is_branch(dpcd))
4557                 return connector_status_connected;
4558
4559         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4560         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4561             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4562
4563                 return intel_dp->sink_count ?
4564                 connector_status_connected : connector_status_disconnected;
4565         }
4566
4567         if (intel_dp_can_mst(intel_dp))
4568                 return connector_status_connected;
4569
4570         /* If no HPD, poke DDC gently */
4571         if (drm_probe_ddc(&intel_dp->aux.ddc))
4572                 return connector_status_connected;
4573
4574         /* Well we tried, say unknown for unreliable port types */
4575         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4576                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4577                 if (type == DP_DS_PORT_TYPE_VGA ||
4578                     type == DP_DS_PORT_TYPE_NON_EDID)
4579                         return connector_status_unknown;
4580         } else {
4581                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4582                         DP_DWN_STRM_PORT_TYPE_MASK;
4583                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4584                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4585                         return connector_status_unknown;
4586         }
4587
4588         /* Anything else is out of spec, warn and ignore */
4589         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4590         return connector_status_disconnected;
4591 }
4592
4593 static enum drm_connector_status
4594 edp_detect(struct intel_dp *intel_dp)
4595 {
4596         return connector_status_connected;
4597 }
4598
4599 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
4600 {
4601         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4602         u32 bit;
4603
4604         switch (encoder->hpd_pin) {
4605         case HPD_PORT_B:
4606                 bit = SDE_PORTB_HOTPLUG;
4607                 break;
4608         case HPD_PORT_C:
4609                 bit = SDE_PORTC_HOTPLUG;
4610                 break;
4611         case HPD_PORT_D:
4612                 bit = SDE_PORTD_HOTPLUG;
4613                 break;
4614         default:
4615                 MISSING_CASE(encoder->hpd_pin);
4616                 return false;
4617         }
4618
4619         return I915_READ(SDEISR) & bit;
4620 }
4621
4622 static bool cpt_digital_port_connected(struct intel_encoder *encoder)
4623 {
4624         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4625         u32 bit;
4626
4627         switch (encoder->hpd_pin) {
4628         case HPD_PORT_B:
4629                 bit = SDE_PORTB_HOTPLUG_CPT;
4630                 break;
4631         case HPD_PORT_C:
4632                 bit = SDE_PORTC_HOTPLUG_CPT;
4633                 break;
4634         case HPD_PORT_D:
4635                 bit = SDE_PORTD_HOTPLUG_CPT;
4636                 break;
4637         default:
4638                 MISSING_CASE(encoder->hpd_pin);
4639                 return false;
4640         }
4641
4642         return I915_READ(SDEISR) & bit;
4643 }
4644
4645 static bool spt_digital_port_connected(struct intel_encoder *encoder)
4646 {
4647         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4648         u32 bit;
4649
4650         switch (encoder->hpd_pin) {
4651         case HPD_PORT_A:
4652                 bit = SDE_PORTA_HOTPLUG_SPT;
4653                 break;
4654         case HPD_PORT_E:
4655                 bit = SDE_PORTE_HOTPLUG_SPT;
4656                 break;
4657         default:
4658                 return cpt_digital_port_connected(encoder);
4659         }
4660
4661         return I915_READ(SDEISR) & bit;
4662 }
4663
4664 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
4665 {
4666         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4667         u32 bit;
4668
4669         switch (encoder->hpd_pin) {
4670         case HPD_PORT_B:
4671                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4672                 break;
4673         case HPD_PORT_C:
4674                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4675                 break;
4676         case HPD_PORT_D:
4677                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4678                 break;
4679         default:
4680                 MISSING_CASE(encoder->hpd_pin);
4681                 return false;
4682         }
4683
4684         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4685 }
4686
4687 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
4688 {
4689         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4690         u32 bit;
4691
4692         switch (encoder->hpd_pin) {
4693         case HPD_PORT_B:
4694                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4695                 break;
4696         case HPD_PORT_C:
4697                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4698                 break;
4699         case HPD_PORT_D:
4700                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4701                 break;
4702         default:
4703                 MISSING_CASE(encoder->hpd_pin);
4704                 return false;
4705         }
4706
4707         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4708 }
4709
4710 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
4711 {
4712         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4713
4714         if (encoder->hpd_pin == HPD_PORT_A)
4715                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4716         else
4717                 return ibx_digital_port_connected(encoder);
4718 }
4719
4720 static bool snb_digital_port_connected(struct intel_encoder *encoder)
4721 {
4722         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4723
4724         if (encoder->hpd_pin == HPD_PORT_A)
4725                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4726         else
4727                 return cpt_digital_port_connected(encoder);
4728 }
4729
4730 static bool ivb_digital_port_connected(struct intel_encoder *encoder)
4731 {
4732         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4733
4734         if (encoder->hpd_pin == HPD_PORT_A)
4735                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
4736         else
4737                 return cpt_digital_port_connected(encoder);
4738 }
4739
4740 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
4741 {
4742         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4743
4744         if (encoder->hpd_pin == HPD_PORT_A)
4745                 return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
4746         else
4747                 return cpt_digital_port_connected(encoder);
4748 }
4749
4750 static bool bxt_digital_port_connected(struct intel_encoder *encoder)
4751 {
4752         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4753         u32 bit;
4754
4755         switch (encoder->hpd_pin) {
4756         case HPD_PORT_A:
4757                 bit = BXT_DE_PORT_HP_DDIA;
4758                 break;
4759         case HPD_PORT_B:
4760                 bit = BXT_DE_PORT_HP_DDIB;
4761                 break;
4762         case HPD_PORT_C:
4763                 bit = BXT_DE_PORT_HP_DDIC;
4764                 break;
4765         default:
4766                 MISSING_CASE(encoder->hpd_pin);
4767                 return false;
4768         }
4769
4770         return I915_READ(GEN8_DE_PORT_ISR) & bit;
4771 }
4772
4773 static bool icl_combo_port_connected(struct drm_i915_private *dev_priv,
4774                                      struct intel_digital_port *intel_dig_port)
4775 {
4776         enum port port = intel_dig_port->base.port;
4777
4778         return I915_READ(SDEISR) & SDE_DDI_HOTPLUG_ICP(port);
4779 }
4780
4781 static void icl_update_tc_port_type(struct drm_i915_private *dev_priv,
4782                                     struct intel_digital_port *intel_dig_port,
4783                                     bool is_legacy, bool is_typec, bool is_tbt)
4784 {
4785         enum port port = intel_dig_port->base.port;
4786         enum tc_port_type old_type = intel_dig_port->tc_type;
4787         const char *type_str;
4788
4789         WARN_ON(is_legacy + is_typec + is_tbt != 1);
4790
4791         if (is_legacy) {
4792                 intel_dig_port->tc_type = TC_PORT_LEGACY;
4793                 type_str = "legacy";
4794         } else if (is_typec) {
4795                 intel_dig_port->tc_type = TC_PORT_TYPEC;
4796                 type_str = "typec";
4797         } else if (is_tbt) {
4798                 intel_dig_port->tc_type = TC_PORT_TBT;
4799                 type_str = "tbt";
4800         } else {
4801                 return;
4802         }
4803
4804         /* Types are not supposed to be changed at runtime. */
4805         WARN_ON(old_type != TC_PORT_UNKNOWN &&
4806                 old_type != intel_dig_port->tc_type);
4807
4808         if (old_type != intel_dig_port->tc_type)
4809                 DRM_DEBUG_KMS("Port %c has TC type %s\n", port_name(port),
4810                               type_str);
4811 }
4812
4813 /*
4814  * This function implements the first part of the Connect Flow described by our
4815  * specification, Gen11 TypeC Programming chapter. The rest of the flow (reading
4816  * lanes, EDID, etc) is done as needed in the typical places.
4817  *
4818  * Unlike the other ports, type-C ports are not available to use as soon as we
4819  * get a hotplug. The type-C PHYs can be shared between multiple controllers:
4820  * display, USB, etc. As a result, handshaking through FIA is required around
4821  * connect and disconnect to cleanly transfer ownership with the controller and
4822  * set the type-C power state.
4823  *
4824  * We could opt to only do the connect flow when we actually try to use the AUX
4825  * channels or do a modeset, then immediately run the disconnect flow after
4826  * usage, but there are some implications on this for a dynamic environment:
4827  * things may go away or change behind our backs. So for now our driver is
4828  * always trying to acquire ownership of the controller as soon as it gets an
4829  * interrupt (or polls state and sees a port is connected) and only gives it
4830  * back when it sees a disconnect. Implementation of a more fine-grained model
4831  * will require a lot of coordination with user space and thorough testing for
4832  * the extra possible cases.
4833  */
4834 static bool icl_tc_phy_connect(struct drm_i915_private *dev_priv,
4835                                struct intel_digital_port *dig_port)
4836 {
4837         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
4838         u32 val;
4839
4840         if (dig_port->tc_type != TC_PORT_LEGACY &&
4841             dig_port->tc_type != TC_PORT_TYPEC)
4842                 return true;
4843
4844         val = I915_READ(PORT_TX_DFLEXDPPMS);
4845         if (!(val & DP_PHY_MODE_STATUS_COMPLETED(tc_port))) {
4846                 DRM_DEBUG_KMS("DP PHY for TC port %d not ready\n", tc_port);
4847                 return false;
4848         }
4849
4850         /*
4851          * This function may be called many times in a row without an HPD event
4852          * in between, so try to avoid the write when we can.
4853          */
4854         val = I915_READ(PORT_TX_DFLEXDPCSSS);
4855         if (!(val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port))) {
4856                 val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
4857                 I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
4858         }
4859
4860         /*
4861          * Now we have to re-check the live state, in case the port recently
4862          * became disconnected. Not necessary for legacy mode.
4863          */
4864         if (dig_port->tc_type == TC_PORT_TYPEC &&
4865             !(I915_READ(PORT_TX_DFLEXDPSP) & TC_LIVE_STATE_TC(tc_port))) {
4866                 DRM_DEBUG_KMS("TC PHY %d sudden disconnect.\n", tc_port);
4867                 val = I915_READ(PORT_TX_DFLEXDPCSSS);
4868                 val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
4869                 I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
4870                 return false;
4871         }
4872
4873         return true;
4874 }
4875
4876 /*
4877  * See the comment at the connect function. This implements the Disconnect
4878  * Flow.
4879  */
4880 static void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
4881                                   struct intel_digital_port *dig_port)
4882 {
4883         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
4884         u32 val;
4885
4886         if (dig_port->tc_type != TC_PORT_LEGACY &&
4887             dig_port->tc_type != TC_PORT_TYPEC)
4888                 return;
4889
4890         /*
4891          * This function may be called many times in a row without an HPD event
4892          * in between, so try to avoid the write when we can.
4893          */
4894         val = I915_READ(PORT_TX_DFLEXDPCSSS);
4895         if (val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port)) {
4896                 val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
4897                 I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
4898         }
4899 }
4900
4901 /*
4902  * The type-C ports are different because even when they are connected, they may
4903  * not be available/usable by the graphics driver: see the comment on
4904  * icl_tc_phy_connect(). So in our driver instead of adding the additional
4905  * concept of "usable" and make everything check for "connected and usable" we
4906  * define a port as "connected" when it is not only connected, but also when it
4907  * is usable by the rest of the driver. That maintains the old assumption that
4908  * connected ports are usable, and avoids exposing to the users objects they
4909  * can't really use.
4910  */
4911 static bool icl_tc_port_connected(struct drm_i915_private *dev_priv,
4912                                   struct intel_digital_port *intel_dig_port)
4913 {
4914         enum port port = intel_dig_port->base.port;
4915         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
4916         bool is_legacy, is_typec, is_tbt;
4917         u32 dpsp;
4918
4919         is_legacy = I915_READ(SDEISR) & SDE_TC_HOTPLUG_ICP(tc_port);
4920
4921         /*
4922          * The spec says we shouldn't be using the ISR bits for detecting
4923          * between TC and TBT. We should use DFLEXDPSP.
4924          */
4925         dpsp = I915_READ(PORT_TX_DFLEXDPSP);
4926         is_typec = dpsp & TC_LIVE_STATE_TC(tc_port);
4927         is_tbt = dpsp & TC_LIVE_STATE_TBT(tc_port);
4928
4929         if (!is_legacy && !is_typec && !is_tbt) {
4930                 icl_tc_phy_disconnect(dev_priv, intel_dig_port);
4931                 return false;
4932         }
4933
4934         icl_update_tc_port_type(dev_priv, intel_dig_port, is_legacy, is_typec,
4935                                 is_tbt);
4936
4937         if (!icl_tc_phy_connect(dev_priv, intel_dig_port))
4938                 return false;
4939
4940         return true;
4941 }
4942
4943 static bool icl_digital_port_connected(struct intel_encoder *encoder)
4944 {
4945         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4946         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
4947
4948         switch (encoder->hpd_pin) {
4949         case HPD_PORT_A:
4950         case HPD_PORT_B:
4951                 return icl_combo_port_connected(dev_priv, dig_port);
4952         case HPD_PORT_C:
4953         case HPD_PORT_D:
4954         case HPD_PORT_E:
4955         case HPD_PORT_F:
4956                 return icl_tc_port_connected(dev_priv, dig_port);
4957         default:
4958                 MISSING_CASE(encoder->hpd_pin);
4959                 return false;
4960         }
4961 }
4962
4963 /*
4964  * intel_digital_port_connected - is the specified port connected?
4965  * @encoder: intel_encoder
4966  *
4967  * In cases where there's a connector physically connected but it can't be used
4968  * by our hardware we also return false, since the rest of the driver should
4969  * pretty much treat the port as disconnected. This is relevant for type-C
4970  * (starting on ICL) where there's ownership involved.
4971  *
4972  * Return %true if port is connected, %false otherwise.
4973  */
4974 bool intel_digital_port_connected(struct intel_encoder *encoder)
4975 {
4976         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4977
4978         if (HAS_GMCH_DISPLAY(dev_priv)) {
4979                 if (IS_GM45(dev_priv))
4980                         return gm45_digital_port_connected(encoder);
4981                 else
4982                         return g4x_digital_port_connected(encoder);
4983         }
4984
4985         if (IS_GEN5(dev_priv))
4986                 return ilk_digital_port_connected(encoder);
4987         else if (IS_GEN6(dev_priv))
4988                 return snb_digital_port_connected(encoder);
4989         else if (IS_GEN7(dev_priv))
4990                 return ivb_digital_port_connected(encoder);
4991         else if (IS_GEN8(dev_priv))
4992                 return bdw_digital_port_connected(encoder);
4993         else if (IS_GEN9_LP(dev_priv))
4994                 return bxt_digital_port_connected(encoder);
4995         else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
4996                 return spt_digital_port_connected(encoder);
4997         else
4998                 return icl_digital_port_connected(encoder);
4999 }
5000
5001 static struct edid *
5002 intel_dp_get_edid(struct intel_dp *intel_dp)
5003 {
5004         struct intel_connector *intel_connector = intel_dp->attached_connector;
5005
5006         /* use cached edid if we have one */
5007         if (intel_connector->edid) {
5008                 /* invalid edid */
5009                 if (IS_ERR(intel_connector->edid))
5010                         return NULL;
5011
5012                 return drm_edid_duplicate(intel_connector->edid);
5013         } else
5014                 return drm_get_edid(&intel_connector->base,
5015                                     &intel_dp->aux.ddc);
5016 }
5017
5018 static void
5019 intel_dp_set_edid(struct intel_dp *intel_dp)
5020 {
5021         struct intel_connector *intel_connector = intel_dp->attached_connector;
5022         struct edid *edid;
5023
5024         intel_dp_unset_edid(intel_dp);
5025         edid = intel_dp_get_edid(intel_dp);
5026         intel_connector->detect_edid = edid;
5027
5028         intel_dp->has_audio = drm_detect_monitor_audio(edid);
5029         drm_dp_cec_set_edid(&intel_dp->aux, edid);
5030 }
5031
5032 static void
5033 intel_dp_unset_edid(struct intel_dp *intel_dp)
5034 {
5035         struct intel_connector *intel_connector = intel_dp->attached_connector;
5036
5037         drm_dp_cec_unset_edid(&intel_dp->aux);
5038         kfree(intel_connector->detect_edid);
5039         intel_connector->detect_edid = NULL;
5040
5041         intel_dp->has_audio = false;
5042 }
5043
5044 static int
5045 intel_dp_long_pulse(struct intel_connector *connector,
5046                     struct drm_modeset_acquire_ctx *ctx)
5047 {
5048         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
5049         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
5050         enum drm_connector_status status;
5051         u8 sink_irq_vector = 0;
5052
5053         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
5054
5055         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5056
5057         /* Can't disconnect eDP */
5058         if (intel_dp_is_edp(intel_dp))
5059                 status = edp_detect(intel_dp);
5060         else if (intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base))
5061                 status = intel_dp_detect_dpcd(intel_dp);
5062         else
5063                 status = connector_status_disconnected;
5064
5065         if (status == connector_status_disconnected) {
5066                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5067
5068                 if (intel_dp->is_mst) {
5069                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5070                                       intel_dp->is_mst,
5071                                       intel_dp->mst_mgr.mst_state);
5072                         intel_dp->is_mst = false;
5073                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5074                                                         intel_dp->is_mst);
5075                 }
5076
5077                 goto out;
5078         }
5079
5080         if (intel_dp->reset_link_params) {
5081                 /* Initial max link lane count */
5082                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
5083
5084                 /* Initial max link rate */
5085                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
5086
5087                 intel_dp->reset_link_params = false;
5088         }
5089
5090         intel_dp_print_rates(intel_dp);
5091
5092         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
5093                          drm_dp_is_branch(intel_dp->dpcd));
5094
5095         intel_dp_configure_mst(intel_dp);
5096
5097         if (intel_dp->is_mst) {
5098                 /*
5099                  * If we are in MST mode then this connector
5100                  * won't appear connected or have anything
5101                  * with EDID on it
5102                  */
5103                 status = connector_status_disconnected;
5104                 goto out;
5105         }
5106
5107         /*
5108          * Some external monitors do not signal loss of link synchronization
5109          * with an IRQ_HPD, so force a link status check.
5110          */
5111         if (!intel_dp_is_edp(intel_dp)) {
5112                 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
5113
5114                 intel_dp_retrain_link(encoder, ctx);
5115         }
5116
5117         /*
5118          * Clearing NACK and defer counts to get their exact values
5119          * while reading EDID which are required by Compliance tests
5120          * 4.2.2.4 and 4.2.2.5
5121          */
5122         intel_dp->aux.i2c_nack_count = 0;
5123         intel_dp->aux.i2c_defer_count = 0;
5124
5125         intel_dp_set_edid(intel_dp);
5126         if (intel_dp_is_edp(intel_dp) || connector->detect_edid)
5127                 status = connector_status_connected;
5128         intel_dp->detect_done = true;
5129
5130         /* Try to read the source of the interrupt */
5131         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
5132             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
5133             sink_irq_vector != 0) {
5134                 /* Clear interrupt source */
5135                 drm_dp_dpcd_writeb(&intel_dp->aux,
5136                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
5137                                    sink_irq_vector);
5138
5139                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
5140                         intel_dp_handle_test_request(intel_dp);
5141                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
5142                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
5143         }
5144
5145 out:
5146         if (status != connector_status_connected && !intel_dp->is_mst)
5147                 intel_dp_unset_edid(intel_dp);
5148
5149         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
5150         return status;
5151 }
5152
5153 static int
5154 intel_dp_detect(struct drm_connector *connector,
5155                 struct drm_modeset_acquire_ctx *ctx,
5156                 bool force)
5157 {
5158         struct intel_dp *intel_dp = intel_attached_dp(connector);
5159         int status = connector->status;
5160
5161         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5162                       connector->base.id, connector->name);
5163
5164         /* If full detect is not performed yet, do a full detect */
5165         if (!intel_dp->detect_done) {
5166                 struct drm_crtc *crtc;
5167                 int ret;
5168
5169                 crtc = connector->state->crtc;
5170                 if (crtc) {
5171                         ret = drm_modeset_lock(&crtc->mutex, ctx);
5172                         if (ret)
5173                                 return ret;
5174                 }
5175
5176                 status = intel_dp_long_pulse(intel_dp->attached_connector, ctx);
5177         }
5178
5179         intel_dp->detect_done = false;
5180
5181         return status;
5182 }
5183
5184 static void
5185 intel_dp_force(struct drm_connector *connector)
5186 {
5187         struct intel_dp *intel_dp = intel_attached_dp(connector);
5188         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
5189         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5190
5191         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5192                       connector->base.id, connector->name);
5193         intel_dp_unset_edid(intel_dp);
5194
5195         if (connector->status != connector_status_connected)
5196                 return;
5197
5198         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5199
5200         intel_dp_set_edid(intel_dp);
5201
5202         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
5203 }
5204
5205 static int intel_dp_get_modes(struct drm_connector *connector)
5206 {
5207         struct intel_connector *intel_connector = to_intel_connector(connector);
5208         struct edid *edid;
5209
5210         edid = intel_connector->detect_edid;
5211         if (edid) {
5212                 int ret = intel_connector_update_modes(connector, edid);
5213                 if (ret)
5214                         return ret;
5215         }
5216
5217         /* if eDP has no EDID, fall back to fixed mode */
5218         if (intel_dp_is_edp(intel_attached_dp(connector)) &&
5219             intel_connector->panel.fixed_mode) {
5220                 struct drm_display_mode *mode;
5221
5222                 mode = drm_mode_duplicate(connector->dev,
5223                                           intel_connector->panel.fixed_mode);
5224                 if (mode) {
5225                         drm_mode_probed_add(connector, mode);
5226                         return 1;
5227                 }
5228         }
5229
5230         return 0;
5231 }
5232
5233 static int
5234 intel_dp_connector_register(struct drm_connector *connector)
5235 {
5236         struct intel_dp *intel_dp = intel_attached_dp(connector);
5237         struct drm_device *dev = connector->dev;
5238         int ret;
5239
5240         ret = intel_connector_register(connector);
5241         if (ret)
5242                 return ret;
5243
5244         i915_debugfs_connector_add(connector);
5245
5246         DRM_DEBUG_KMS("registering %s bus for %s\n",
5247                       intel_dp->aux.name, connector->kdev->kobj.name);
5248
5249         intel_dp->aux.dev = connector->kdev;
5250         ret = drm_dp_aux_register(&intel_dp->aux);
5251         if (!ret)
5252                 drm_dp_cec_register_connector(&intel_dp->aux,
5253                                               connector->name, dev->dev);
5254         return ret;
5255 }
5256
5257 static void
5258 intel_dp_connector_unregister(struct drm_connector *connector)
5259 {
5260         struct intel_dp *intel_dp = intel_attached_dp(connector);
5261
5262         drm_dp_cec_unregister_connector(&intel_dp->aux);
5263         drm_dp_aux_unregister(&intel_dp->aux);
5264         intel_connector_unregister(connector);
5265 }
5266
5267 static void
5268 intel_dp_connector_destroy(struct drm_connector *connector)
5269 {
5270         struct intel_connector *intel_connector = to_intel_connector(connector);
5271
5272         kfree(intel_connector->detect_edid);
5273
5274         if (!IS_ERR_OR_NULL(intel_connector->edid))
5275                 kfree(intel_connector->edid);
5276
5277         /*
5278          * Can't call intel_dp_is_edp() since the encoder may have been
5279          * destroyed already.
5280          */
5281         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5282                 intel_panel_fini(&intel_connector->panel);
5283
5284         drm_connector_cleanup(connector);
5285         kfree(connector);
5286 }
5287
5288 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
5289 {
5290         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
5291         struct intel_dp *intel_dp = &intel_dig_port->dp;
5292
5293         intel_dp_mst_encoder_cleanup(intel_dig_port);
5294         if (intel_dp_is_edp(intel_dp)) {
5295                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5296                 /*
5297                  * vdd might still be enabled do to the delayed vdd off.
5298                  * Make sure vdd is actually turned off here.
5299                  */
5300                 pps_lock(intel_dp);
5301                 edp_panel_vdd_off_sync(intel_dp);
5302                 pps_unlock(intel_dp);
5303
5304                 if (intel_dp->edp_notifier.notifier_call) {
5305                         unregister_reboot_notifier(&intel_dp->edp_notifier);
5306                         intel_dp->edp_notifier.notifier_call = NULL;
5307                 }
5308         }
5309
5310         intel_dp_aux_fini(intel_dp);
5311
5312         drm_encoder_cleanup(encoder);
5313         kfree(intel_dig_port);
5314 }
5315
5316 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5317 {
5318         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
5319
5320         if (!intel_dp_is_edp(intel_dp))
5321                 return;
5322
5323         /*
5324          * vdd might still be enabled do to the delayed vdd off.
5325          * Make sure vdd is actually turned off here.
5326          */
5327         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5328         pps_lock(intel_dp);
5329         edp_panel_vdd_off_sync(intel_dp);
5330         pps_unlock(intel_dp);
5331 }
5332
5333 static
5334 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
5335                                 u8 *an)
5336 {
5337         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_dig_port->base.base);
5338         static const struct drm_dp_aux_msg msg = {
5339                 .request = DP_AUX_NATIVE_WRITE,
5340                 .address = DP_AUX_HDCP_AKSV,
5341                 .size = DRM_HDCP_KSV_LEN,
5342         };
5343         uint8_t txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
5344         ssize_t dpcd_ret;
5345         int ret;
5346
5347         /* Output An first, that's easy */
5348         dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN,
5349                                      an, DRM_HDCP_AN_LEN);
5350         if (dpcd_ret != DRM_HDCP_AN_LEN) {
5351                 DRM_ERROR("Failed to write An over DP/AUX (%zd)\n", dpcd_ret);
5352                 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
5353         }
5354
5355         /*
5356          * Since Aksv is Oh-So-Secret, we can't access it in software. So in
5357          * order to get it on the wire, we need to create the AUX header as if
5358          * we were writing the data, and then tickle the hardware to output the
5359          * data once the header is sent out.
5360          */
5361         intel_dp_aux_header(txbuf, &msg);
5362
5363         ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size,
5364                                 rxbuf, sizeof(rxbuf),
5365                                 DP_AUX_CH_CTL_AUX_AKSV_SELECT);
5366         if (ret < 0) {
5367                 DRM_ERROR("Write Aksv over DP/AUX failed (%d)\n", ret);
5368                 return ret;
5369         } else if (ret == 0) {
5370                 DRM_ERROR("Aksv write over DP/AUX was empty\n");
5371                 return -EIO;
5372         }
5373
5374         reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK;
5375         return reply == DP_AUX_NATIVE_REPLY_ACK ? 0 : -EIO;
5376 }
5377
5378 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
5379                                    u8 *bksv)
5380 {
5381         ssize_t ret;
5382         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
5383                                DRM_HDCP_KSV_LEN);
5384         if (ret != DRM_HDCP_KSV_LEN) {
5385                 DRM_ERROR("Read Bksv from DP/AUX failed (%zd)\n", ret);
5386                 return ret >= 0 ? -EIO : ret;
5387         }
5388         return 0;
5389 }
5390
5391 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
5392                                       u8 *bstatus)
5393 {
5394         ssize_t ret;
5395         /*
5396          * For some reason the HDMI and DP HDCP specs call this register
5397          * definition by different names. In the HDMI spec, it's called BSTATUS,
5398          * but in DP it's called BINFO.
5399          */
5400         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO,
5401                                bstatus, DRM_HDCP_BSTATUS_LEN);
5402         if (ret != DRM_HDCP_BSTATUS_LEN) {
5403                 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret);
5404                 return ret >= 0 ? -EIO : ret;
5405         }
5406         return 0;
5407 }
5408
5409 static
5410 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,
5411                              u8 *bcaps)
5412 {
5413         ssize_t ret;
5414
5415         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
5416                                bcaps, 1);
5417         if (ret != 1) {
5418                 DRM_ERROR("Read bcaps from DP/AUX failed (%zd)\n", ret);
5419                 return ret >= 0 ? -EIO : ret;
5420         }
5421
5422         return 0;
5423 }
5424
5425 static
5426 int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
5427                                    bool *repeater_present)
5428 {
5429         ssize_t ret;
5430         u8 bcaps;
5431
5432         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5433         if (ret)
5434                 return ret;
5435
5436         *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
5437         return 0;
5438 }
5439
5440 static
5441 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
5442                                 u8 *ri_prime)
5443 {
5444         ssize_t ret;
5445         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
5446                                ri_prime, DRM_HDCP_RI_LEN);
5447         if (ret != DRM_HDCP_RI_LEN) {
5448                 DRM_ERROR("Read Ri' from DP/AUX failed (%zd)\n", ret);
5449                 return ret >= 0 ? -EIO : ret;
5450         }
5451         return 0;
5452 }
5453
5454 static
5455 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
5456                                  bool *ksv_ready)
5457 {
5458         ssize_t ret;
5459         u8 bstatus;
5460         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5461                                &bstatus, 1);
5462         if (ret != 1) {
5463                 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret);
5464                 return ret >= 0 ? -EIO : ret;
5465         }
5466         *ksv_ready = bstatus & DP_BSTATUS_READY;
5467         return 0;
5468 }
5469
5470 static
5471 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
5472                                 int num_downstream, u8 *ksv_fifo)
5473 {
5474         ssize_t ret;
5475         int i;
5476
5477         /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
5478         for (i = 0; i < num_downstream; i += 3) {
5479                 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
5480                 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5481                                        DP_AUX_HDCP_KSV_FIFO,
5482                                        ksv_fifo + i * DRM_HDCP_KSV_LEN,
5483                                        len);
5484                 if (ret != len) {
5485                         DRM_ERROR("Read ksv[%d] from DP/AUX failed (%zd)\n", i,
5486                                   ret);
5487                         return ret >= 0 ? -EIO : ret;
5488                 }
5489         }
5490         return 0;
5491 }
5492
5493 static
5494 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
5495                                     int i, u32 *part)
5496 {
5497         ssize_t ret;
5498
5499         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
5500                 return -EINVAL;
5501
5502         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5503                                DP_AUX_HDCP_V_PRIME(i), part,
5504                                DRM_HDCP_V_PRIME_PART_LEN);
5505         if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
5506                 DRM_ERROR("Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
5507                 return ret >= 0 ? -EIO : ret;
5508         }
5509         return 0;
5510 }
5511
5512 static
5513 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
5514                                     bool enable)
5515 {
5516         /* Not used for single stream DisplayPort setups */
5517         return 0;
5518 }
5519
5520 static
5521 bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port)
5522 {
5523         ssize_t ret;
5524         u8 bstatus;
5525
5526         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5527                                &bstatus, 1);
5528         if (ret != 1) {
5529                 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret);
5530                 return false;
5531         }
5532
5533         return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
5534 }
5535
5536 static
5537 int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port,
5538                           bool *hdcp_capable)
5539 {
5540         ssize_t ret;
5541         u8 bcaps;
5542
5543         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5544         if (ret)
5545                 return ret;
5546
5547         *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
5548         return 0;
5549 }
5550
5551 static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
5552         .write_an_aksv = intel_dp_hdcp_write_an_aksv,
5553         .read_bksv = intel_dp_hdcp_read_bksv,
5554         .read_bstatus = intel_dp_hdcp_read_bstatus,
5555         .repeater_present = intel_dp_hdcp_repeater_present,
5556         .read_ri_prime = intel_dp_hdcp_read_ri_prime,
5557         .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
5558         .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
5559         .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
5560         .toggle_signalling = intel_dp_hdcp_toggle_signalling,
5561         .check_link = intel_dp_hdcp_check_link,
5562         .hdcp_capable = intel_dp_hdcp_capable,
5563 };
5564
5565 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
5566 {
5567         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5568
5569         lockdep_assert_held(&dev_priv->pps_mutex);
5570
5571         if (!edp_have_panel_vdd(intel_dp))
5572                 return;
5573
5574         /*
5575          * The VDD bit needs a power domain reference, so if the bit is
5576          * already enabled when we boot or resume, grab this reference and
5577          * schedule a vdd off, so we don't hold on to the reference
5578          * indefinitely.
5579          */
5580         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5581         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5582
5583         edp_panel_vdd_schedule_off(intel_dp);
5584 }
5585
5586 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
5587 {
5588         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5589         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
5590         enum pipe pipe;
5591
5592         if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
5593                                   encoder->port, &pipe))
5594                 return pipe;
5595
5596         return INVALID_PIPE;
5597 }
5598
5599 void intel_dp_encoder_reset(struct drm_encoder *encoder)
5600 {
5601         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
5602         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5603         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5604
5605         if (!HAS_DDI(dev_priv))
5606                 intel_dp->DP = I915_READ(intel_dp->output_reg);
5607
5608         if (lspcon->active)
5609                 lspcon_resume(lspcon);
5610
5611         intel_dp->reset_link_params = true;
5612
5613         pps_lock(intel_dp);
5614
5615         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5616                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
5617
5618         if (intel_dp_is_edp(intel_dp)) {
5619                 /* Reinit the power sequencer, in case BIOS did something with it. */
5620                 intel_dp_pps_init(intel_dp);
5621                 intel_edp_panel_vdd_sanitize(intel_dp);
5622         }
5623
5624         pps_unlock(intel_dp);
5625 }
5626
5627 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5628         .force = intel_dp_force,
5629         .fill_modes = drm_helper_probe_single_connector_modes,
5630         .atomic_get_property = intel_digital_connector_atomic_get_property,
5631         .atomic_set_property = intel_digital_connector_atomic_set_property,
5632         .late_register = intel_dp_connector_register,
5633         .early_unregister = intel_dp_connector_unregister,
5634         .destroy = intel_dp_connector_destroy,
5635         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5636         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
5637 };
5638
5639 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5640         .detect_ctx = intel_dp_detect,
5641         .get_modes = intel_dp_get_modes,
5642         .mode_valid = intel_dp_mode_valid,
5643         .atomic_check = intel_digital_connector_atomic_check,
5644 };
5645
5646 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
5647         .reset = intel_dp_encoder_reset,
5648         .destroy = intel_dp_encoder_destroy,
5649 };
5650
5651 enum irqreturn
5652 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
5653 {
5654         struct intel_dp *intel_dp = &intel_dig_port->dp;
5655         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5656         enum irqreturn ret = IRQ_NONE;
5657
5658         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
5659                 /*
5660                  * vdd off can generate a long pulse on eDP which
5661                  * would require vdd on to handle it, and thus we
5662                  * would end up in an endless cycle of
5663                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5664                  */
5665                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5666                               port_name(intel_dig_port->base.port));
5667                 return IRQ_HANDLED;
5668         }
5669
5670         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5671                       port_name(intel_dig_port->base.port),
5672                       long_hpd ? "long" : "short");
5673
5674         if (long_hpd) {
5675                 intel_dp->reset_link_params = true;
5676                 intel_dp->detect_done = false;
5677                 return IRQ_NONE;
5678         }
5679
5680         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5681
5682         if (intel_dp->is_mst) {
5683                 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
5684                         /*
5685                          * If we were in MST mode, and device is not
5686                          * there, get out of MST mode
5687                          */
5688                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5689                                       intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5690                         intel_dp->is_mst = false;
5691                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5692                                                         intel_dp->is_mst);
5693                         intel_dp->detect_done = false;
5694                         goto put_power;
5695                 }
5696         }
5697
5698         if (!intel_dp->is_mst) {
5699                 bool handled;
5700
5701                 handled = intel_dp_short_pulse(intel_dp);
5702
5703                 /* Short pulse can signify loss of hdcp authentication */
5704                 intel_hdcp_check_link(intel_dp->attached_connector);
5705
5706                 if (!handled) {
5707                         intel_dp->detect_done = false;
5708                         goto put_power;
5709                 }
5710         }
5711
5712         ret = IRQ_HANDLED;
5713
5714 put_power:
5715         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
5716
5717         return ret;
5718 }
5719
5720 /* check the VBT to see whether the eDP is on another port */
5721 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
5722 {
5723         /*
5724          * eDP not supported on g4x. so bail out early just
5725          * for a bit extra safety in case the VBT is bonkers.
5726          */
5727         if (INTEL_GEN(dev_priv) < 5)
5728                 return false;
5729
5730         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
5731                 return true;
5732
5733         return intel_bios_is_port_edp(dev_priv, port);
5734 }
5735
5736 static void
5737 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5738 {
5739         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5740         enum port port = dp_to_dig_port(intel_dp)->base.port;
5741
5742         if (!IS_G4X(dev_priv) && port != PORT_A)
5743                 intel_attach_force_audio_property(connector);
5744
5745         intel_attach_broadcast_rgb_property(connector);
5746
5747         if (intel_dp_is_edp(intel_dp)) {
5748                 u32 allowed_scalers;
5749
5750                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
5751                 if (!HAS_GMCH_DISPLAY(dev_priv))
5752                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
5753
5754                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
5755
5756                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
5757
5758         }
5759 }
5760
5761 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5762 {
5763         intel_dp->panel_power_off_time = ktime_get_boottime();
5764         intel_dp->last_power_on = jiffies;
5765         intel_dp->last_backlight_off = jiffies;
5766 }
5767
5768 static void
5769 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
5770 {
5771         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5772         u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5773         struct pps_registers regs;
5774
5775         intel_pps_get_registers(intel_dp, &regs);
5776
5777         /* Workaround: Need to write PP_CONTROL with the unlock key as
5778          * the very first thing. */
5779         pp_ctl = ironlake_get_pp_control(intel_dp);
5780
5781         pp_on = I915_READ(regs.pp_on);
5782         pp_off = I915_READ(regs.pp_off);
5783         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
5784             !HAS_PCH_ICP(dev_priv)) {
5785                 I915_WRITE(regs.pp_ctrl, pp_ctl);
5786                 pp_div = I915_READ(regs.pp_div);
5787         }
5788
5789         /* Pull timing values out of registers */
5790         seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5791                      PANEL_POWER_UP_DELAY_SHIFT;
5792
5793         seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5794                   PANEL_LIGHT_ON_DELAY_SHIFT;
5795
5796         seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5797                   PANEL_LIGHT_OFF_DELAY_SHIFT;
5798
5799         seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5800                    PANEL_POWER_DOWN_DELAY_SHIFT;
5801
5802         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
5803             HAS_PCH_ICP(dev_priv)) {
5804                 seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5805                                 BXT_POWER_CYCLE_DELAY_SHIFT) * 1000;
5806         } else {
5807                 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5808                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5809         }
5810 }
5811
5812 static void
5813 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
5814 {
5815         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5816                       state_name,
5817                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
5818 }
5819
5820 static void
5821 intel_pps_verify_state(struct intel_dp *intel_dp)
5822 {
5823         struct edp_power_seq hw;
5824         struct edp_power_seq *sw = &intel_dp->pps_delays;
5825
5826         intel_pps_readout_hw_state(intel_dp, &hw);
5827
5828         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
5829             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
5830                 DRM_ERROR("PPS state mismatch\n");
5831                 intel_pps_dump_state("sw", sw);
5832                 intel_pps_dump_state("hw", &hw);
5833         }
5834 }
5835
5836 static void
5837 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
5838 {
5839         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5840         struct edp_power_seq cur, vbt, spec,
5841                 *final = &intel_dp->pps_delays;
5842
5843         lockdep_assert_held(&dev_priv->pps_mutex);
5844
5845         /* already initialized? */
5846         if (final->t11_t12 != 0)
5847                 return;
5848
5849         intel_pps_readout_hw_state(intel_dp, &cur);
5850
5851         intel_pps_dump_state("cur", &cur);
5852
5853         vbt = dev_priv->vbt.edp.pps;
5854         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
5855          * of 500ms appears to be too short. Ocassionally the panel
5856          * just fails to power back on. Increasing the delay to 800ms
5857          * seems sufficient to avoid this problem.
5858          */
5859         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
5860                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
5861                 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
5862                               vbt.t11_t12);
5863         }
5864         /* T11_T12 delay is special and actually in units of 100ms, but zero
5865          * based in the hw (so we need to add 100 ms). But the sw vbt
5866          * table multiplies it with 1000 to make it in units of 100usec,
5867          * too. */
5868         vbt.t11_t12 += 100 * 10;
5869
5870         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5871          * our hw here, which are all in 100usec. */
5872         spec.t1_t3 = 210 * 10;
5873         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5874         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5875         spec.t10 = 500 * 10;
5876         /* This one is special and actually in units of 100ms, but zero
5877          * based in the hw (so we need to add 100 ms). But the sw vbt
5878          * table multiplies it with 1000 to make it in units of 100usec,
5879          * too. */
5880         spec.t11_t12 = (510 + 100) * 10;
5881
5882         intel_pps_dump_state("vbt", &vbt);
5883
5884         /* Use the max of the register settings and vbt. If both are
5885          * unset, fall back to the spec limits. */
5886 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
5887                                        spec.field : \
5888                                        max(cur.field, vbt.field))
5889         assign_final(t1_t3);
5890         assign_final(t8);
5891         assign_final(t9);
5892         assign_final(t10);
5893         assign_final(t11_t12);
5894 #undef assign_final
5895
5896 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
5897         intel_dp->panel_power_up_delay = get_delay(t1_t3);
5898         intel_dp->backlight_on_delay = get_delay(t8);
5899         intel_dp->backlight_off_delay = get_delay(t9);
5900         intel_dp->panel_power_down_delay = get_delay(t10);
5901         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5902 #undef get_delay
5903
5904         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5905                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5906                       intel_dp->panel_power_cycle_delay);
5907
5908         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5909                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5910
5911         /*
5912          * We override the HW backlight delays to 1 because we do manual waits
5913          * on them. For T8, even BSpec recommends doing it. For T9, if we
5914          * don't do this, we'll end up waiting for the backlight off delay
5915          * twice: once when we do the manual sleep, and once when we disable
5916          * the panel and wait for the PP_STATUS bit to become zero.
5917          */
5918         final->t8 = 1;
5919         final->t9 = 1;
5920
5921         /*
5922          * HW has only a 100msec granularity for t11_t12 so round it up
5923          * accordingly.
5924          */
5925         final->t11_t12 = roundup(final->t11_t12, 100 * 10);
5926 }
5927
5928 static void
5929 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
5930                                               bool force_disable_vdd)
5931 {
5932         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5933         u32 pp_on, pp_off, pp_div, port_sel = 0;
5934         int div = dev_priv->rawclk_freq / 1000;
5935         struct pps_registers regs;
5936         enum port port = dp_to_dig_port(intel_dp)->base.port;
5937         const struct edp_power_seq *seq = &intel_dp->pps_delays;
5938
5939         lockdep_assert_held(&dev_priv->pps_mutex);
5940
5941         intel_pps_get_registers(intel_dp, &regs);
5942
5943         /*
5944          * On some VLV machines the BIOS can leave the VDD
5945          * enabled even on power sequencers which aren't
5946          * hooked up to any port. This would mess up the
5947          * power domain tracking the first time we pick
5948          * one of these power sequencers for use since
5949          * edp_panel_vdd_on() would notice that the VDD was
5950          * already on and therefore wouldn't grab the power
5951          * domain reference. Disable VDD first to avoid this.
5952          * This also avoids spuriously turning the VDD on as
5953          * soon as the new power sequencer gets initialized.
5954          */
5955         if (force_disable_vdd) {
5956                 u32 pp = ironlake_get_pp_control(intel_dp);
5957
5958                 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
5959
5960                 if (pp & EDP_FORCE_VDD)
5961                         DRM_DEBUG_KMS("VDD already on, disabling first\n");
5962
5963                 pp &= ~EDP_FORCE_VDD;
5964
5965                 I915_WRITE(regs.pp_ctrl, pp);
5966         }
5967
5968         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5969                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
5970         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5971                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5972         /* Compute the divisor for the pp clock, simply match the Bspec
5973          * formula. */
5974         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
5975             HAS_PCH_ICP(dev_priv)) {
5976                 pp_div = I915_READ(regs.pp_ctrl);
5977                 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5978                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5979                                 << BXT_POWER_CYCLE_DELAY_SHIFT);
5980         } else {
5981                 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5982                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5983                                 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5984         }
5985
5986         /* Haswell doesn't have any port selection bits for the panel
5987          * power sequencer any more. */
5988         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5989                 port_sel = PANEL_PORT_SELECT_VLV(port);
5990         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
5991                 switch (port) {
5992                 case PORT_A:
5993                         port_sel = PANEL_PORT_SELECT_DPA;
5994                         break;
5995                 case PORT_C:
5996                         port_sel = PANEL_PORT_SELECT_DPC;
5997                         break;
5998                 case PORT_D:
5999                         port_sel = PANEL_PORT_SELECT_DPD;
6000                         break;
6001                 default:
6002                         MISSING_CASE(port);
6003                         break;
6004                 }
6005         }
6006
6007         pp_on |= port_sel;
6008
6009         I915_WRITE(regs.pp_on, pp_on);
6010         I915_WRITE(regs.pp_off, pp_off);
6011         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
6012             HAS_PCH_ICP(dev_priv))
6013                 I915_WRITE(regs.pp_ctrl, pp_div);
6014         else
6015                 I915_WRITE(regs.pp_div, pp_div);
6016
6017         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
6018                       I915_READ(regs.pp_on),
6019                       I915_READ(regs.pp_off),
6020                       (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)  ||
6021                        HAS_PCH_ICP(dev_priv)) ?
6022                       (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
6023                       I915_READ(regs.pp_div));
6024 }
6025
6026 static void intel_dp_pps_init(struct intel_dp *intel_dp)
6027 {
6028         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6029
6030         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6031                 vlv_initial_power_sequencer_setup(intel_dp);
6032         } else {
6033                 intel_dp_init_panel_power_sequencer(intel_dp);
6034                 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
6035         }
6036 }
6037
6038 /**
6039  * intel_dp_set_drrs_state - program registers for RR switch to take effect
6040  * @dev_priv: i915 device
6041  * @crtc_state: a pointer to the active intel_crtc_state
6042  * @refresh_rate: RR to be programmed
6043  *
6044  * This function gets called when refresh rate (RR) has to be changed from
6045  * one frequency to another. Switches can be between high and low RR
6046  * supported by the panel or to any other RR based on media playback (in
6047  * this case, RR value needs to be passed from user space).
6048  *
6049  * The caller of this function needs to take a lock on dev_priv->drrs.
6050  */
6051 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
6052                                     const struct intel_crtc_state *crtc_state,
6053                                     int refresh_rate)
6054 {
6055         struct intel_encoder *encoder;
6056         struct intel_digital_port *dig_port = NULL;
6057         struct intel_dp *intel_dp = dev_priv->drrs.dp;
6058         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
6059         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
6060
6061         if (refresh_rate <= 0) {
6062                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
6063                 return;
6064         }
6065
6066         if (intel_dp == NULL) {
6067                 DRM_DEBUG_KMS("DRRS not supported.\n");
6068                 return;
6069         }
6070
6071         dig_port = dp_to_dig_port(intel_dp);
6072         encoder = &dig_port->base;
6073
6074         if (!intel_crtc) {
6075                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
6076                 return;
6077         }
6078
6079         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
6080                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
6081                 return;
6082         }
6083
6084         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
6085                         refresh_rate)
6086                 index = DRRS_LOW_RR;
6087
6088         if (index == dev_priv->drrs.refresh_rate_type) {
6089                 DRM_DEBUG_KMS(
6090                         "DRRS requested for previously set RR...ignoring\n");
6091                 return;
6092         }
6093
6094         if (!crtc_state->base.active) {
6095                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
6096                 return;
6097         }
6098
6099         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
6100                 switch (index) {
6101                 case DRRS_HIGH_RR:
6102                         intel_dp_set_m_n(intel_crtc, M1_N1);
6103                         break;
6104                 case DRRS_LOW_RR:
6105                         intel_dp_set_m_n(intel_crtc, M2_N2);
6106                         break;
6107                 case DRRS_MAX_RR:
6108                 default:
6109                         DRM_ERROR("Unsupported refreshrate type\n");
6110                 }
6111         } else if (INTEL_GEN(dev_priv) > 6) {
6112                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
6113                 u32 val;
6114
6115                 val = I915_READ(reg);
6116                 if (index > DRRS_HIGH_RR) {
6117                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6118                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6119                         else
6120                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
6121                 } else {
6122                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6123                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6124                         else
6125                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
6126                 }
6127                 I915_WRITE(reg, val);
6128         }
6129
6130         dev_priv->drrs.refresh_rate_type = index;
6131
6132         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
6133 }
6134
6135 /**
6136  * intel_edp_drrs_enable - init drrs struct if supported
6137  * @intel_dp: DP struct
6138  * @crtc_state: A pointer to the active crtc state.
6139  *
6140  * Initializes frontbuffer_bits and drrs.dp
6141  */
6142 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
6143                            const struct intel_crtc_state *crtc_state)
6144 {
6145         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6146
6147         if (!crtc_state->has_drrs) {
6148                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
6149                 return;
6150         }
6151
6152         if (dev_priv->psr.enabled) {
6153                 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
6154                 return;
6155         }
6156
6157         mutex_lock(&dev_priv->drrs.mutex);
6158         if (WARN_ON(dev_priv->drrs.dp)) {
6159                 DRM_ERROR("DRRS already enabled\n");
6160                 goto unlock;
6161         }
6162
6163         dev_priv->drrs.busy_frontbuffer_bits = 0;
6164
6165         dev_priv->drrs.dp = intel_dp;
6166
6167 unlock:
6168         mutex_unlock(&dev_priv->drrs.mutex);
6169 }
6170
6171 /**
6172  * intel_edp_drrs_disable - Disable DRRS
6173  * @intel_dp: DP struct
6174  * @old_crtc_state: Pointer to old crtc_state.
6175  *
6176  */
6177 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
6178                             const struct intel_crtc_state *old_crtc_state)
6179 {
6180         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6181
6182         if (!old_crtc_state->has_drrs)
6183                 return;
6184
6185         mutex_lock(&dev_priv->drrs.mutex);
6186         if (!dev_priv->drrs.dp) {
6187                 mutex_unlock(&dev_priv->drrs.mutex);
6188                 return;
6189         }
6190
6191         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6192                 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
6193                         intel_dp->attached_connector->panel.fixed_mode->vrefresh);
6194
6195         dev_priv->drrs.dp = NULL;
6196         mutex_unlock(&dev_priv->drrs.mutex);
6197
6198         cancel_delayed_work_sync(&dev_priv->drrs.work);
6199 }
6200
6201 static void intel_edp_drrs_downclock_work(struct work_struct *work)
6202 {
6203         struct drm_i915_private *dev_priv =
6204                 container_of(work, typeof(*dev_priv), drrs.work.work);
6205         struct intel_dp *intel_dp;
6206
6207         mutex_lock(&dev_priv->drrs.mutex);
6208
6209         intel_dp = dev_priv->drrs.dp;
6210
6211         if (!intel_dp)
6212                 goto unlock;
6213
6214         /*
6215          * The delayed work can race with an invalidate hence we need to
6216          * recheck.
6217          */
6218
6219         if (dev_priv->drrs.busy_frontbuffer_bits)
6220                 goto unlock;
6221
6222         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
6223                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
6224
6225                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6226                         intel_dp->attached_connector->panel.downclock_mode->vrefresh);
6227         }
6228
6229 unlock:
6230         mutex_unlock(&dev_priv->drrs.mutex);
6231 }
6232
6233 /**
6234  * intel_edp_drrs_invalidate - Disable Idleness DRRS
6235  * @dev_priv: i915 device
6236  * @frontbuffer_bits: frontbuffer plane tracking bits
6237  *
6238  * This function gets called everytime rendering on the given planes start.
6239  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
6240  *
6241  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6242  */
6243 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
6244                                unsigned int frontbuffer_bits)
6245 {
6246         struct drm_crtc *crtc;
6247         enum pipe pipe;
6248
6249         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6250                 return;
6251
6252         cancel_delayed_work(&dev_priv->drrs.work);
6253
6254         mutex_lock(&dev_priv->drrs.mutex);
6255         if (!dev_priv->drrs.dp) {
6256                 mutex_unlock(&dev_priv->drrs.mutex);
6257                 return;
6258         }
6259
6260         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
6261         pipe = to_intel_crtc(crtc)->pipe;
6262
6263         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6264         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
6265
6266         /* invalidate means busy screen hence upclock */
6267         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6268                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6269                         dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
6270
6271         mutex_unlock(&dev_priv->drrs.mutex);
6272 }
6273
6274 /**
6275  * intel_edp_drrs_flush - Restart Idleness DRRS
6276  * @dev_priv: i915 device
6277  * @frontbuffer_bits: frontbuffer plane tracking bits
6278  *
6279  * This function gets called every time rendering on the given planes has
6280  * completed or flip on a crtc is completed. So DRRS should be upclocked
6281  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
6282  * if no other planes are dirty.
6283  *
6284  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6285  */
6286 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
6287                           unsigned int frontbuffer_bits)
6288 {
6289         struct drm_crtc *crtc;
6290         enum pipe pipe;
6291
6292         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6293                 return;
6294
6295         cancel_delayed_work(&dev_priv->drrs.work);
6296
6297         mutex_lock(&dev_priv->drrs.mutex);
6298         if (!dev_priv->drrs.dp) {
6299                 mutex_unlock(&dev_priv->drrs.mutex);
6300                 return;
6301         }
6302
6303         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
6304         pipe = to_intel_crtc(crtc)->pipe;
6305
6306         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6307         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
6308
6309         /* flush means busy screen hence upclock */
6310         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6311                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6312                                 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
6313
6314         /*
6315          * flush also means no more activity hence schedule downclock, if all
6316          * other fbs are quiescent too
6317          */
6318         if (!dev_priv->drrs.busy_frontbuffer_bits)
6319                 schedule_delayed_work(&dev_priv->drrs.work,
6320                                 msecs_to_jiffies(1000));
6321         mutex_unlock(&dev_priv->drrs.mutex);
6322 }
6323
6324 /**
6325  * DOC: Display Refresh Rate Switching (DRRS)
6326  *
6327  * Display Refresh Rate Switching (DRRS) is a power conservation feature
6328  * which enables swtching between low and high refresh rates,
6329  * dynamically, based on the usage scenario. This feature is applicable
6330  * for internal panels.
6331  *
6332  * Indication that the panel supports DRRS is given by the panel EDID, which
6333  * would list multiple refresh rates for one resolution.
6334  *
6335  * DRRS is of 2 types - static and seamless.
6336  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
6337  * (may appear as a blink on screen) and is used in dock-undock scenario.
6338  * Seamless DRRS involves changing RR without any visual effect to the user
6339  * and can be used during normal system usage. This is done by programming
6340  * certain registers.
6341  *
6342  * Support for static/seamless DRRS may be indicated in the VBT based on
6343  * inputs from the panel spec.
6344  *
6345  * DRRS saves power by switching to low RR based on usage scenarios.
6346  *
6347  * The implementation is based on frontbuffer tracking implementation.  When
6348  * there is a disturbance on the screen triggered by user activity or a periodic
6349  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
6350  * no movement on screen, after a timeout of 1 second, a switch to low RR is
6351  * made.
6352  *
6353  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
6354  * and intel_edp_drrs_flush() are called.
6355  *
6356  * DRRS can be further extended to support other internal panels and also
6357  * the scenario of video playback wherein RR is set based on the rate
6358  * requested by userspace.
6359  */
6360
6361 /**
6362  * intel_dp_drrs_init - Init basic DRRS work and mutex.
6363  * @connector: eDP connector
6364  * @fixed_mode: preferred mode of panel
6365  *
6366  * This function is  called only once at driver load to initialize basic
6367  * DRRS stuff.
6368  *
6369  * Returns:
6370  * Downclock mode if panel supports it, else return NULL.
6371  * DRRS support is determined by the presence of downclock mode (apart
6372  * from VBT setting).
6373  */
6374 static struct drm_display_mode *
6375 intel_dp_drrs_init(struct intel_connector *connector,
6376                    struct drm_display_mode *fixed_mode)
6377 {
6378         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
6379         struct drm_display_mode *downclock_mode = NULL;
6380
6381         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
6382         mutex_init(&dev_priv->drrs.mutex);
6383
6384         if (INTEL_GEN(dev_priv) <= 6) {
6385                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
6386                 return NULL;
6387         }
6388
6389         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
6390                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
6391                 return NULL;
6392         }
6393
6394         downclock_mode = intel_find_panel_downclock(dev_priv, fixed_mode,
6395                                                     &connector->base);
6396
6397         if (!downclock_mode) {
6398                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
6399                 return NULL;
6400         }
6401
6402         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
6403
6404         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
6405         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
6406         return downclock_mode;
6407 }
6408
6409 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
6410                                      struct intel_connector *intel_connector)
6411 {
6412         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6413         struct drm_device *dev = &dev_priv->drm;
6414         struct drm_connector *connector = &intel_connector->base;
6415         struct drm_display_mode *fixed_mode = NULL;
6416         struct drm_display_mode *downclock_mode = NULL;
6417         bool has_dpcd;
6418         struct drm_display_mode *scan;
6419         struct edid *edid;
6420         enum pipe pipe = INVALID_PIPE;
6421
6422         if (!intel_dp_is_edp(intel_dp))
6423                 return true;
6424
6425         /*
6426          * On IBX/CPT we may get here with LVDS already registered. Since the
6427          * driver uses the only internal power sequencer available for both
6428          * eDP and LVDS bail out early in this case to prevent interfering
6429          * with an already powered-on LVDS power sequencer.
6430          */
6431         if (intel_get_lvds_encoder(&dev_priv->drm)) {
6432                 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
6433                 DRM_INFO("LVDS was detected, not registering eDP\n");
6434
6435                 return false;
6436         }
6437
6438         pps_lock(intel_dp);
6439
6440         intel_dp_init_panel_power_timestamps(intel_dp);
6441         intel_dp_pps_init(intel_dp);
6442         intel_edp_panel_vdd_sanitize(intel_dp);
6443
6444         pps_unlock(intel_dp);
6445
6446         /* Cache DPCD and EDID for edp. */
6447         has_dpcd = intel_edp_init_dpcd(intel_dp);
6448
6449         if (!has_dpcd) {
6450                 /* if this fails, presume the device is a ghost */
6451                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
6452                 goto out_vdd_off;
6453         }
6454
6455         mutex_lock(&dev->mode_config.mutex);
6456         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
6457         if (edid) {
6458                 if (drm_add_edid_modes(connector, edid)) {
6459                         drm_connector_update_edid_property(connector,
6460                                                                 edid);
6461                 } else {
6462                         kfree(edid);
6463                         edid = ERR_PTR(-EINVAL);
6464                 }
6465         } else {
6466                 edid = ERR_PTR(-ENOENT);
6467         }
6468         intel_connector->edid = edid;
6469
6470         /* prefer fixed mode from EDID if available */
6471         list_for_each_entry(scan, &connector->probed_modes, head) {
6472                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
6473                         fixed_mode = drm_mode_duplicate(dev, scan);
6474                         downclock_mode = intel_dp_drrs_init(
6475                                                 intel_connector, fixed_mode);
6476                         break;
6477                 }
6478         }
6479
6480         /* fallback to VBT if available for eDP */
6481         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
6482                 fixed_mode = drm_mode_duplicate(dev,
6483                                         dev_priv->vbt.lfp_lvds_vbt_mode);
6484                 if (fixed_mode) {
6485                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
6486                         connector->display_info.width_mm = fixed_mode->width_mm;
6487                         connector->display_info.height_mm = fixed_mode->height_mm;
6488                 }
6489         }
6490         mutex_unlock(&dev->mode_config.mutex);
6491
6492         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6493                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
6494                 register_reboot_notifier(&intel_dp->edp_notifier);
6495
6496                 /*
6497                  * Figure out the current pipe for the initial backlight setup.
6498                  * If the current pipe isn't valid, try the PPS pipe, and if that
6499                  * fails just assume pipe A.
6500                  */
6501                 pipe = vlv_active_pipe(intel_dp);
6502
6503                 if (pipe != PIPE_A && pipe != PIPE_B)
6504                         pipe = intel_dp->pps_pipe;
6505
6506                 if (pipe != PIPE_A && pipe != PIPE_B)
6507                         pipe = PIPE_A;
6508
6509                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
6510                               pipe_name(pipe));
6511         }
6512
6513         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
6514         intel_connector->panel.backlight.power = intel_edp_backlight_power;
6515         intel_panel_setup_backlight(connector, pipe);
6516
6517         return true;
6518
6519 out_vdd_off:
6520         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
6521         /*
6522          * vdd might still be enabled do to the delayed vdd off.
6523          * Make sure vdd is actually turned off here.
6524          */
6525         pps_lock(intel_dp);
6526         edp_panel_vdd_off_sync(intel_dp);
6527         pps_unlock(intel_dp);
6528
6529         return false;
6530 }
6531
6532 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
6533 {
6534         struct intel_connector *intel_connector;
6535         struct drm_connector *connector;
6536
6537         intel_connector = container_of(work, typeof(*intel_connector),
6538                                        modeset_retry_work);
6539         connector = &intel_connector->base;
6540         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
6541                       connector->name);
6542
6543         /* Grab the locks before changing connector property*/
6544         mutex_lock(&connector->dev->mode_config.mutex);
6545         /* Set connector link status to BAD and send a Uevent to notify
6546          * userspace to do a modeset.
6547          */
6548         drm_connector_set_link_status_property(connector,
6549                                                DRM_MODE_LINK_STATUS_BAD);
6550         mutex_unlock(&connector->dev->mode_config.mutex);
6551         /* Send Hotplug uevent so userspace can reprobe */
6552         drm_kms_helper_hotplug_event(connector->dev);
6553 }
6554
6555 bool
6556 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
6557                         struct intel_connector *intel_connector)
6558 {
6559         struct drm_connector *connector = &intel_connector->base;
6560         struct intel_dp *intel_dp = &intel_dig_port->dp;
6561         struct intel_encoder *intel_encoder = &intel_dig_port->base;
6562         struct drm_device *dev = intel_encoder->base.dev;
6563         struct drm_i915_private *dev_priv = to_i915(dev);
6564         enum port port = intel_encoder->port;
6565         int type;
6566
6567         /* Initialize the work for modeset in case of link train failure */
6568         INIT_WORK(&intel_connector->modeset_retry_work,
6569                   intel_dp_modeset_retry_work_fn);
6570
6571         if (WARN(intel_dig_port->max_lanes < 1,
6572                  "Not enough lanes (%d) for DP on port %c\n",
6573                  intel_dig_port->max_lanes, port_name(port)))
6574                 return false;
6575
6576         intel_dp_set_source_rates(intel_dp);
6577
6578         intel_dp->reset_link_params = true;
6579         intel_dp->pps_pipe = INVALID_PIPE;
6580         intel_dp->active_pipe = INVALID_PIPE;
6581
6582         /* intel_dp vfuncs */
6583         if (HAS_DDI(dev_priv))
6584                 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
6585
6586         /* Preserve the current hw state. */
6587         intel_dp->DP = I915_READ(intel_dp->output_reg);
6588         intel_dp->attached_connector = intel_connector;
6589
6590         if (intel_dp_is_port_edp(dev_priv, port))
6591                 type = DRM_MODE_CONNECTOR_eDP;
6592         else
6593                 type = DRM_MODE_CONNECTOR_DisplayPort;
6594
6595         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6596                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6597
6598         /*
6599          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
6600          * for DP the encoder type can be set by the caller to
6601          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
6602          */
6603         if (type == DRM_MODE_CONNECTOR_eDP)
6604                 intel_encoder->type = INTEL_OUTPUT_EDP;
6605
6606         /* eDP only on port B and/or C on vlv/chv */
6607         if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
6608                     intel_dp_is_edp(intel_dp) &&
6609                     port != PORT_B && port != PORT_C))
6610                 return false;
6611
6612         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
6613                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6614                         port_name(port));
6615
6616         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
6617         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6618
6619         if (!HAS_GMCH_DISPLAY(dev_priv))
6620                 connector->interlace_allowed = true;
6621         connector->doublescan_allowed = 0;
6622
6623         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
6624
6625         intel_dp_aux_init(intel_dp);
6626
6627         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
6628                           edp_panel_vdd_work);
6629
6630         intel_connector_attach_encoder(intel_connector, intel_encoder);
6631
6632         if (HAS_DDI(dev_priv))
6633                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6634         else
6635                 intel_connector->get_hw_state = intel_connector_get_hw_state;
6636
6637         /* init MST on ports that can support it */
6638         if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) &&
6639             (port == PORT_B || port == PORT_C ||
6640              port == PORT_D || port == PORT_F))
6641                 intel_dp_mst_encoder_init(intel_dig_port,
6642                                           intel_connector->base.base.id);
6643
6644         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6645                 intel_dp_aux_fini(intel_dp);
6646                 intel_dp_mst_encoder_cleanup(intel_dig_port);
6647                 goto fail;
6648         }
6649
6650         intel_dp_add_properties(intel_dp, connector);
6651
6652         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
6653                 int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
6654                 if (ret)
6655                         DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
6656         }
6657
6658         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6659          * 0xd.  Failure to do so will result in spurious interrupts being
6660          * generated on the port when a cable is not attached.
6661          */
6662         if (IS_G45(dev_priv)) {
6663                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
6664                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
6665         }
6666
6667         return true;
6668
6669 fail:
6670         drm_connector_cleanup(connector);
6671
6672         return false;
6673 }
6674
6675 bool intel_dp_init(struct drm_i915_private *dev_priv,
6676                    i915_reg_t output_reg,
6677                    enum port port)
6678 {
6679         struct intel_digital_port *intel_dig_port;
6680         struct intel_encoder *intel_encoder;
6681         struct drm_encoder *encoder;
6682         struct intel_connector *intel_connector;
6683
6684         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
6685         if (!intel_dig_port)
6686                 return false;
6687
6688         intel_connector = intel_connector_alloc();
6689         if (!intel_connector)
6690                 goto err_connector_alloc;
6691
6692         intel_encoder = &intel_dig_port->base;
6693         encoder = &intel_encoder->base;
6694
6695         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
6696                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
6697                              "DP %c", port_name(port)))
6698                 goto err_encoder_init;
6699
6700         intel_encoder->hotplug = intel_dp_hotplug;
6701         intel_encoder->compute_config = intel_dp_compute_config;
6702         intel_encoder->get_hw_state = intel_dp_get_hw_state;
6703         intel_encoder->get_config = intel_dp_get_config;
6704         intel_encoder->suspend = intel_dp_encoder_suspend;
6705         if (IS_CHERRYVIEW(dev_priv)) {
6706                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
6707                 intel_encoder->pre_enable = chv_pre_enable_dp;
6708                 intel_encoder->enable = vlv_enable_dp;
6709                 intel_encoder->disable = vlv_disable_dp;
6710                 intel_encoder->post_disable = chv_post_disable_dp;
6711                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
6712         } else if (IS_VALLEYVIEW(dev_priv)) {
6713                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
6714                 intel_encoder->pre_enable = vlv_pre_enable_dp;
6715                 intel_encoder->enable = vlv_enable_dp;
6716                 intel_encoder->disable = vlv_disable_dp;
6717                 intel_encoder->post_disable = vlv_post_disable_dp;
6718         } else {
6719                 intel_encoder->pre_enable = g4x_pre_enable_dp;
6720                 intel_encoder->enable = g4x_enable_dp;
6721                 intel_encoder->disable = g4x_disable_dp;
6722                 intel_encoder->post_disable = g4x_post_disable_dp;
6723         }
6724
6725         intel_dig_port->dp.output_reg = output_reg;
6726         intel_dig_port->max_lanes = 4;
6727
6728         intel_encoder->type = INTEL_OUTPUT_DP;
6729         intel_encoder->power_domain = intel_port_to_power_domain(port);
6730         if (IS_CHERRYVIEW(dev_priv)) {
6731                 if (port == PORT_D)
6732                         intel_encoder->crtc_mask = 1 << 2;
6733                 else
6734                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
6735         } else {
6736                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
6737         }
6738         intel_encoder->cloneable = 0;
6739         intel_encoder->port = port;
6740
6741         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6742
6743         if (port != PORT_A)
6744                 intel_infoframe_init(intel_dig_port);
6745
6746         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
6747                 goto err_init_connector;
6748
6749         return true;
6750
6751 err_init_connector:
6752         drm_encoder_cleanup(encoder);
6753 err_encoder_init:
6754         kfree(intel_connector);
6755 err_connector_alloc:
6756         kfree(intel_dig_port);
6757         return false;
6758 }
6759
6760 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
6761 {
6762         struct intel_encoder *encoder;
6763
6764         for_each_intel_encoder(&dev_priv->drm, encoder) {
6765                 struct intel_dp *intel_dp;
6766
6767                 if (encoder->type != INTEL_OUTPUT_DDI)
6768                         continue;
6769
6770                 intel_dp = enc_to_intel_dp(&encoder->base);
6771
6772                 if (!intel_dp->can_mst)
6773                         continue;
6774
6775                 if (intel_dp->is_mst)
6776                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
6777         }
6778 }
6779
6780 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
6781 {
6782         struct intel_encoder *encoder;
6783
6784         for_each_intel_encoder(&dev_priv->drm, encoder) {
6785                 struct intel_dp *intel_dp;
6786                 int ret;
6787
6788                 if (encoder->type != INTEL_OUTPUT_DDI)
6789                         continue;
6790
6791                 intel_dp = enc_to_intel_dp(&encoder->base);
6792
6793                 if (!intel_dp->can_mst)
6794                         continue;
6795
6796                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr);
6797                 if (ret)
6798                         intel_dp_check_mst_status(intel_dp);
6799         }
6800 }