drivers/gpu/drm/i915/intel_display.h

   1 /*
   2  * Copyright © 2006-2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #ifndef _INTEL_DISPLAY_H_
  26 #define _INTEL_DISPLAY_H_
  27
  28 #include <drm/drm_util.h>
  29
  30 enum i915_gpio {
  31         GPIOA,
  32         GPIOB,
  33         GPIOC,
  34         GPIOD,
  35         GPIOE,
  36         GPIOF,
  37         GPIOG,
  38         GPIOH,
  39         __GPIOI_UNUSED,
  40         GPIOJ,
  41         GPIOK,
  42         GPIOL,
  43         GPIOM,
  44 };
  45
  46 enum pipe {
  47         INVALID_PIPE = -1,
  48
  49         PIPE_A = 0,
  50         PIPE_B,
  51         PIPE_C,
  52         _PIPE_EDP,
  53
  54         I915_MAX_PIPES = _PIPE_EDP
  55 };
  56
  57 #define pipe_name(p) ((p) + 'A')
  58
  59 enum transcoder {
  60         TRANSCODER_A = 0,
  61         TRANSCODER_B,
  62         TRANSCODER_C,
  63         TRANSCODER_EDP,
  64         TRANSCODER_DSI_A,
  65         TRANSCODER_DSI_C,
  66
  67         I915_MAX_TRANSCODERS
  68 };
  69
  70 static inline const char *transcoder_name(enum transcoder transcoder)
  71 {
  72         switch (transcoder) {
  73         case TRANSCODER_A:
  74                 return "A";
  75         case TRANSCODER_B:
  76                 return "B";
  77         case TRANSCODER_C:
  78                 return "C";
  79         case TRANSCODER_EDP:
  80                 return "EDP";
  81         case TRANSCODER_DSI_A:
  82                 return "DSI A";
  83         case TRANSCODER_DSI_C:
  84                 return "DSI C";
  85         default:
  86                 return "<invalid>";
  87         }
  88 }
  89
  90 static inline bool transcoder_is_dsi(enum transcoder transcoder)
  91 {
  92         return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
  93 }
  94
  95 /*
  96  * Global legacy plane identifier. Valid only for primary/sprite
  97  * planes on pre-g4x, and only for primary planes on g4x-bdw.
  98  */
  99 enum i9xx_plane_id {
 100         PLANE_A,
 101         PLANE_B,
 102         PLANE_C,
 103 };
 104
 105 #define plane_name(p) ((p) + 'A')
 106 #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
 107
 108 /*
 109  * Per-pipe plane identifier.
 110  * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
 111  * number of planes per CRTC.  Not all platforms really have this many planes,
 112  * which means some arrays of size I915_MAX_PLANES may have unused entries
 113  * between the topmost sprite plane and the cursor plane.
 114  *
 115  * This is expected to be passed to various register macros
 116  * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
 117  */
 118 enum plane_id {
 119         PLANE_PRIMARY,
 120         PLANE_SPRITE0,
 121         PLANE_SPRITE1,
 122         PLANE_SPRITE2,
 123         PLANE_CURSOR,
 124
 125         I915_MAX_PLANES,
 126 };
 127
 128 #define for_each_plane_id_on_crtc(__crtc, __p) \
 129         for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
 130                 for_each_if((__crtc)->plane_ids_mask & BIT(__p))
 131
 132 enum port {
 133         PORT_NONE = -1,
 134
 135         PORT_A = 0,
 136         PORT_B,
 137         PORT_C,
 138         PORT_D,
 139         PORT_E,
 140         PORT_F,
 141
 142         I915_MAX_PORTS
 143 };
 144
 145 #define port_name(p) ((p) + 'A')
 146
 147 /*
 148  * Ports identifier referenced from other drivers.
 149  * Expected to remain stable over time
 150  */
 151 static inline const char *port_identifier(enum port port)
 152 {
 153         switch (port) {
 154         case PORT_A:
 155                 return "Port A";
 156         case PORT_B:
 157                 return "Port B";
 158         case PORT_C:
 159                 return "Port C";
 160         case PORT_D:
 161                 return "Port D";
 162         case PORT_E:
 163                 return "Port E";
 164         case PORT_F:
 165                 return "Port F";
 166         default:
 167                 return "<invalid>";
 168         }
 169 }
 170
 171 enum tc_port {
 172         PORT_TC_NONE = -1,
 173
 174         PORT_TC1 = 0,
 175         PORT_TC2,
 176         PORT_TC3,
 177         PORT_TC4,
 178
 179         I915_MAX_TC_PORTS
 180 };
 181
 182 enum tc_port_type {
 183         TC_PORT_UNKNOWN = 0,
 184         TC_PORT_TYPEC,
 185         TC_PORT_TBT,
 186         TC_PORT_LEGACY,
 187 };
 188
 189 enum dpio_channel {
 190         DPIO_CH0,
 191         DPIO_CH1
 192 };
 193
 194 enum dpio_phy {
 195         DPIO_PHY0,
 196         DPIO_PHY1,
 197         DPIO_PHY2,
 198 };
 199
 200 #define I915_NUM_PHYS_VLV 2
 201
 202 enum aux_ch {
 203         AUX_CH_A,
 204         AUX_CH_B,
 205         AUX_CH_C,
 206         AUX_CH_D,
 207         AUX_CH_E, /* ICL+ */
 208         AUX_CH_F,
 209 };
 210
 211 #define aux_ch_name(a) ((a) + 'A')
 212
 213 enum intel_display_power_domain {
 214         POWER_DOMAIN_PIPE_A,
 215         POWER_DOMAIN_PIPE_B,
 216         POWER_DOMAIN_PIPE_C,
 217         POWER_DOMAIN_PIPE_A_PANEL_FITTER,
 218         POWER_DOMAIN_PIPE_B_PANEL_FITTER,
 219         POWER_DOMAIN_PIPE_C_PANEL_FITTER,
 220         POWER_DOMAIN_TRANSCODER_A,
 221         POWER_DOMAIN_TRANSCODER_B,
 222         POWER_DOMAIN_TRANSCODER_C,
 223         POWER_DOMAIN_TRANSCODER_EDP,
 224         POWER_DOMAIN_TRANSCODER_DSI_A,
 225         POWER_DOMAIN_TRANSCODER_DSI_C,
 226         POWER_DOMAIN_PORT_DDI_A_LANES,
 227         POWER_DOMAIN_PORT_DDI_B_LANES,
 228         POWER_DOMAIN_PORT_DDI_C_LANES,
 229         POWER_DOMAIN_PORT_DDI_D_LANES,
 230         POWER_DOMAIN_PORT_DDI_E_LANES,
 231         POWER_DOMAIN_PORT_DDI_F_LANES,
 232         POWER_DOMAIN_PORT_DDI_A_IO,
 233         POWER_DOMAIN_PORT_DDI_B_IO,
 234         POWER_DOMAIN_PORT_DDI_C_IO,
 235         POWER_DOMAIN_PORT_DDI_D_IO,
 236         POWER_DOMAIN_PORT_DDI_E_IO,
 237         POWER_DOMAIN_PORT_DDI_F_IO,
 238         POWER_DOMAIN_PORT_DSI,
 239         POWER_DOMAIN_PORT_CRT,
 240         POWER_DOMAIN_PORT_OTHER,
 241         POWER_DOMAIN_VGA,
 242         POWER_DOMAIN_AUDIO,
 243         POWER_DOMAIN_PLLS,
 244         POWER_DOMAIN_AUX_A,
 245         POWER_DOMAIN_AUX_B,
 246         POWER_DOMAIN_AUX_C,
 247         POWER_DOMAIN_AUX_D,
 248         POWER_DOMAIN_AUX_E,
 249         POWER_DOMAIN_AUX_F,
 250         POWER_DOMAIN_AUX_IO_A,
 251         POWER_DOMAIN_AUX_TBT1,
 252         POWER_DOMAIN_AUX_TBT2,
 253         POWER_DOMAIN_AUX_TBT3,
 254         POWER_DOMAIN_AUX_TBT4,
 255         POWER_DOMAIN_GMBUS,
 256         POWER_DOMAIN_MODESET,
 257         POWER_DOMAIN_GT_IRQ,
 258         POWER_DOMAIN_INIT,
 259
 260         POWER_DOMAIN_NUM,
 261 };
 262
 263 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
 264 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
 265                 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
 266 #define POWER_DOMAIN_TRANSCODER(tran) \
 267         ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
 268          (tran) + POWER_DOMAIN_TRANSCODER_A)
 269
 270 /* Used by dp and fdi links */
 271 struct intel_link_m_n {
 272         u32 tu;
 273         u32 gmch_m;
 274         u32 gmch_n;
 275         u32 link_m;
 276         u32 link_n;
 277 };
 278
 279 #define for_each_pipe(__dev_priv, __p) \
 280         for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
 281
 282 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
 283         for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
 284                 for_each_if((__mask) & BIT(__p))
 285
 286 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
 287         for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++)  \
 288                 for_each_if ((__mask) & (1 << (__t)))
 289
 290 #define for_each_universal_plane(__dev_priv, __pipe, __p)               \
 291         for ((__p) = 0;                                                 \
 292              (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
 293              (__p)++)
 294
 295 #define for_each_sprite(__dev_priv, __p, __s)                           \
 296         for ((__s) = 0;                                                 \
 297              (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)];        \
 298              (__s)++)
 299
 300 #define for_each_port_masked(__port, __ports_mask) \
 301         for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)  \
 302                 for_each_if((__ports_mask) & BIT(__port))
 303
 304 #define for_each_crtc(dev, crtc) \
 305         list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
 306
 307 #define for_each_intel_plane(dev, intel_plane) \
 308         list_for_each_entry(intel_plane,                        \
 309                             &(dev)->mode_config.plane_list,     \
 310                             base.head)
 311
 312 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask)         \
 313         list_for_each_entry(intel_plane,                                \
 314                             &(dev)->mode_config.plane_list,             \
 315                             base.head)                                  \
 316                 for_each_if((plane_mask) &                              \
 317                             drm_plane_mask(&intel_plane->base)))
 318
 319 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)      \
 320         list_for_each_entry(intel_plane,                                \
 321                             &(dev)->mode_config.plane_list,             \
 322                             base.head)                                  \
 323                 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)
 324
 325 #define for_each_intel_crtc(dev, intel_crtc)                            \
 326         list_for_each_entry(intel_crtc,                                 \
 327                             &(dev)->mode_config.crtc_list,              \
 328                             base.head)
 329
 330 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask)            \
 331         list_for_each_entry(intel_crtc,                                 \
 332                             &(dev)->mode_config.crtc_list,              \
 333                             base.head)                                  \
 334                 for_each_if((crtc_mask) & drm_crtc_mask(&intel_crtc->base))
 335
 336 #define for_each_intel_encoder(dev, intel_encoder)              \
 337         list_for_each_entry(intel_encoder,                      \
 338                             &(dev)->mode_config.encoder_list,   \
 339                             base.head)
 340
 341 #define for_each_intel_dp(dev, intel_encoder)                   \
 342         for_each_intel_encoder(dev, intel_encoder)              \
 343                 for_each_if(intel_encoder_is_dp(intel_encoder))
 344
 345 #define for_each_intel_connector_iter(intel_connector, iter) \
 346         while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
 347
 348 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
 349         list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
 350                 for_each_if((intel_encoder)->base.crtc == (__crtc))
 351
 352 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
 353         list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
 354                 for_each_if((intel_connector)->base.encoder == (__encoder))
 355
 356 #define for_each_power_domain(domain, mask)                             \
 357         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
 358                 for_each_if(BIT_ULL(domain) & (mask))
 359
 360 #define for_each_power_well(__dev_priv, __power_well)                           \
 361         for ((__power_well) = (__dev_priv)->power_domains.power_wells;  \
 362              (__power_well) - (__dev_priv)->power_domains.power_wells < \
 363                 (__dev_priv)->power_domains.power_well_count;           \
 364              (__power_well)++)
 365
 366 #define for_each_power_well_rev(__dev_priv, __power_well)                       \
 367         for ((__power_well) = (__dev_priv)->power_domains.power_wells +         \
 368                               (__dev_priv)->power_domains.power_well_count - 1; \
 369              (__power_well) - (__dev_priv)->power_domains.power_wells >= 0;     \
 370              (__power_well)--)
 371
 372 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask)     \
 373         for_each_power_well(__dev_priv, __power_well)                           \
 374                 for_each_if((__power_well)->desc->domains & (__domain_mask))
 375
 376 #define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \
 377         for_each_power_well_rev(__dev_priv, __power_well)                       \
 378                 for_each_if((__power_well)->desc->domains & (__domain_mask))
 379
 380 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
 381         for ((__i) = 0; \
 382              (__i) < (__state)->base.dev->mode_config.num_total_plane && \
 383                      ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
 384                       (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
 385              (__i)++) \
 386                 for_each_if(plane)
 387
 388 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
 389         for ((__i) = 0; \
 390              (__i) < (__state)->base.dev->mode_config.num_crtc && \
 391                      ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
 392                       (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
 393              (__i)++) \
 394                 for_each_if(crtc)
 395
 396 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
 397         for ((__i) = 0; \
 398              (__i) < (__state)->base.dev->mode_config.num_total_plane && \
 399                      ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
 400                       (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
 401                       (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
 402              (__i)++) \
 403                 for_each_if(plane)
 404
 405 void intel_link_compute_m_n(int bpp, int nlanes,
 406                             int pixel_clock, int link_clock,
 407                             struct intel_link_m_n *m_n,
 408                             bool constant_n);
 409
 410 bool is_ccs_modifier(u64 modifier);
 411 #endif