drivers/gpu/drm/i915/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <[email protected]>
  25  *
  26  */
  27
  28 #include <drm/drm_scdc_helper.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31
  32 struct ddi_buf_trans {
  33         u32 trans1;     /* balance leg enable, de-emph level */
  34         u32 trans2;     /* vref sel, vswing */
  35         u8 i_boost;     /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
  36 };
  37
  38 static const u8 index_to_dp_signal_levels[] = {
  39         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  40         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  41         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  42         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  43         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  44         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  45         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  46         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  47         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  48         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  49 };
  50
  51 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  52  * them for both DP and FDI transports, allowing those ports to
  53  * automatically adapt to HDMI connections as well
  54  */
  55 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  56         { 0x00FFFFFF, 0x0006000E, 0x0 },
  57         { 0x00D75FFF, 0x0005000A, 0x0 },
  58         { 0x00C30FFF, 0x00040006, 0x0 },
  59         { 0x80AAAFFF, 0x000B0000, 0x0 },
  60         { 0x00FFFFFF, 0x0005000A, 0x0 },
  61         { 0x00D75FFF, 0x000C0004, 0x0 },
  62         { 0x80C30FFF, 0x000B0000, 0x0 },
  63         { 0x00FFFFFF, 0x00040006, 0x0 },
  64         { 0x80D75FFF, 0x000B0000, 0x0 },
  65 };
  66
  67 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  68         { 0x00FFFFFF, 0x0007000E, 0x0 },
  69         { 0x00D75FFF, 0x000F000A, 0x0 },
  70         { 0x00C30FFF, 0x00060006, 0x0 },
  71         { 0x00AAAFFF, 0x001E0000, 0x0 },
  72         { 0x00FFFFFF, 0x000F000A, 0x0 },
  73         { 0x00D75FFF, 0x00160004, 0x0 },
  74         { 0x00C30FFF, 0x001E0000, 0x0 },
  75         { 0x00FFFFFF, 0x00060006, 0x0 },
  76         { 0x00D75FFF, 0x001E0000, 0x0 },
  77 };
  78
  79 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
  80                                         /* Idx  NT mV d T mV d  db      */
  81         { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:   400     400     0       */
  82         { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400     500     2       */
  83         { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400     600     3.5     */
  84         { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:   600     600     0       */
  85         { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600     750     2       */
  86         { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600     900     3.5     */
  87         { 0x00FFFFFF, 0x00040006, 0x0 },/* 6:   800     800     0       */
  88         { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800     1000    2       */
  89         { 0x00FFFFFF, 0x00140005, 0x0 },/* 8:   850     850     0       */
  90         { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:   900     900     0       */
  91         { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:  950     950     0       */
  92         { 0x80FFFFFF, 0x00030002, 0x0 },/* 11:  1000    1000    0       */
  93 };
  94
  95 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
  96         { 0x00FFFFFF, 0x00000012, 0x0 },
  97         { 0x00EBAFFF, 0x00020011, 0x0 },
  98         { 0x00C71FFF, 0x0006000F, 0x0 },
  99         { 0x00AAAFFF, 0x000E000A, 0x0 },
 100         { 0x00FFFFFF, 0x00020011, 0x0 },
 101         { 0x00DB6FFF, 0x0005000F, 0x0 },
 102         { 0x00BEEFFF, 0x000A000C, 0x0 },
 103         { 0x00FFFFFF, 0x0005000F, 0x0 },
 104         { 0x00DB6FFF, 0x000A000C, 0x0 },
 105 };
 106
 107 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
 108         { 0x00FFFFFF, 0x0007000E, 0x0 },
 109         { 0x00D75FFF, 0x000E000A, 0x0 },
 110         { 0x00BEFFFF, 0x00140006, 0x0 },
 111         { 0x80B2CFFF, 0x001B0002, 0x0 },
 112         { 0x00FFFFFF, 0x000E000A, 0x0 },
 113         { 0x00DB6FFF, 0x00160005, 0x0 },
 114         { 0x80C71FFF, 0x001A0002, 0x0 },
 115         { 0x00F7DFFF, 0x00180004, 0x0 },
 116         { 0x80D75FFF, 0x001B0002, 0x0 },
 117 };
 118
 119 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 120         { 0x00FFFFFF, 0x0001000E, 0x0 },
 121         { 0x00D75FFF, 0x0004000A, 0x0 },
 122         { 0x00C30FFF, 0x00070006, 0x0 },
 123         { 0x00AAAFFF, 0x000C0000, 0x0 },
 124         { 0x00FFFFFF, 0x0004000A, 0x0 },
 125         { 0x00D75FFF, 0x00090004, 0x0 },
 126         { 0x00C30FFF, 0x000C0000, 0x0 },
 127         { 0x00FFFFFF, 0x00070006, 0x0 },
 128         { 0x00D75FFF, 0x000C0000, 0x0 },
 129 };
 130
 131 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 132                                         /* Idx  NT mV d T mV df db      */
 133         { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:   400     400     0       */
 134         { 0x00D75FFF, 0x000E000A, 0x0 },/* 1:   400     600     3.5     */
 135         { 0x00BEFFFF, 0x00140006, 0x0 },/* 2:   400     800     6       */
 136         { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:   450     450     0       */
 137         { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:   600     600     0       */
 138         { 0x00D7FFFF, 0x00140006, 0x0 },/* 5:   600     800     2.5     */
 139         { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:   600     1000    4.5     */
 140         { 0x00FFFFFF, 0x00140006, 0x0 },/* 7:   800     800     0       */
 141         { 0x80E79FFF, 0x001B0002, 0x0 },/* 8:   800     1000    2       */
 142         { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:   1000    1000    0       */
 143 };
 144
 145 /* Skylake H and S */
 146 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 147         { 0x00002016, 0x000000A0, 0x0 },
 148         { 0x00005012, 0x0000009B, 0x0 },
 149         { 0x00007011, 0x00000088, 0x0 },
 150         { 0x80009010, 0x000000C0, 0x1 },
 151         { 0x00002016, 0x0000009B, 0x0 },
 152         { 0x00005012, 0x00000088, 0x0 },
 153         { 0x80007011, 0x000000C0, 0x1 },
 154         { 0x00002016, 0x000000DF, 0x0 },
 155         { 0x80005012, 0x000000C0, 0x1 },
 156 };
 157
 158 /* Skylake U */
 159 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 160         { 0x0000201B, 0x000000A2, 0x0 },
 161         { 0x00005012, 0x00000088, 0x0 },
 162         { 0x80007011, 0x000000CD, 0x1 },
 163         { 0x80009010, 0x000000C0, 0x1 },
 164         { 0x0000201B, 0x0000009D, 0x0 },
 165         { 0x80005012, 0x000000C0, 0x1 },
 166         { 0x80007011, 0x000000C0, 0x1 },
 167         { 0x00002016, 0x00000088, 0x0 },
 168         { 0x80005012, 0x000000C0, 0x1 },
 169 };
 170
 171 /* Skylake Y */
 172 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 173         { 0x00000018, 0x000000A2, 0x0 },
 174         { 0x00005012, 0x00000088, 0x0 },
 175         { 0x80007011, 0x000000CD, 0x3 },
 176         { 0x80009010, 0x000000C0, 0x3 },
 177         { 0x00000018, 0x0000009D, 0x0 },
 178         { 0x80005012, 0x000000C0, 0x3 },
 179         { 0x80007011, 0x000000C0, 0x3 },
 180         { 0x00000018, 0x00000088, 0x0 },
 181         { 0x80005012, 0x000000C0, 0x3 },
 182 };
 183
 184 /* Kabylake H and S */
 185 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
 186         { 0x00002016, 0x000000A0, 0x0 },
 187         { 0x00005012, 0x0000009B, 0x0 },
 188         { 0x00007011, 0x00000088, 0x0 },
 189         { 0x80009010, 0x000000C0, 0x1 },
 190         { 0x00002016, 0x0000009B, 0x0 },
 191         { 0x00005012, 0x00000088, 0x0 },
 192         { 0x80007011, 0x000000C0, 0x1 },
 193         { 0x00002016, 0x00000097, 0x0 },
 194         { 0x80005012, 0x000000C0, 0x1 },
 195 };
 196
 197 /* Kabylake U */
 198 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
 199         { 0x0000201B, 0x000000A1, 0x0 },
 200         { 0x00005012, 0x00000088, 0x0 },
 201         { 0x80007011, 0x000000CD, 0x3 },
 202         { 0x80009010, 0x000000C0, 0x3 },
 203         { 0x0000201B, 0x0000009D, 0x0 },
 204         { 0x80005012, 0x000000C0, 0x3 },
 205         { 0x80007011, 0x000000C0, 0x3 },
 206         { 0x00002016, 0x0000004F, 0x0 },
 207         { 0x80005012, 0x000000C0, 0x3 },
 208 };
 209
 210 /* Kabylake Y */
 211 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
 212         { 0x00001017, 0x000000A1, 0x0 },
 213         { 0x00005012, 0x00000088, 0x0 },
 214         { 0x80007011, 0x000000CD, 0x3 },
 215         { 0x8000800F, 0x000000C0, 0x3 },
 216         { 0x00001017, 0x0000009D, 0x0 },
 217         { 0x80005012, 0x000000C0, 0x3 },
 218         { 0x80007011, 0x000000C0, 0x3 },
 219         { 0x00001017, 0x0000004C, 0x0 },
 220         { 0x80005012, 0x000000C0, 0x3 },
 221 };
 222
 223 /*
 224  * Skylake/Kabylake H and S
 225  * eDP 1.4 low vswing translation parameters
 226  */
 227 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 228         { 0x00000018, 0x000000A8, 0x0 },
 229         { 0x00004013, 0x000000A9, 0x0 },
 230         { 0x00007011, 0x000000A2, 0x0 },
 231         { 0x00009010, 0x0000009C, 0x0 },
 232         { 0x00000018, 0x000000A9, 0x0 },
 233         { 0x00006013, 0x000000A2, 0x0 },
 234         { 0x00007011, 0x000000A6, 0x0 },
 235         { 0x00000018, 0x000000AB, 0x0 },
 236         { 0x00007013, 0x0000009F, 0x0 },
 237         { 0x00000018, 0x000000DF, 0x0 },
 238 };
 239
 240 /*
 241  * Skylake/Kabylake U
 242  * eDP 1.4 low vswing translation parameters
 243  */
 244 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
 245         { 0x00000018, 0x000000A8, 0x0 },
 246         { 0x00004013, 0x000000A9, 0x0 },
 247         { 0x00007011, 0x000000A2, 0x0 },
 248         { 0x00009010, 0x0000009C, 0x0 },
 249         { 0x00000018, 0x000000A9, 0x0 },
 250         { 0x00006013, 0x000000A2, 0x0 },
 251         { 0x00007011, 0x000000A6, 0x0 },
 252         { 0x00002016, 0x000000AB, 0x0 },
 253         { 0x00005013, 0x0000009F, 0x0 },
 254         { 0x00000018, 0x000000DF, 0x0 },
 255 };
 256
 257 /*
 258  * Skylake/Kabylake Y
 259  * eDP 1.4 low vswing translation parameters
 260  */
 261 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
 262         { 0x00000018, 0x000000A8, 0x0 },
 263         { 0x00004013, 0x000000AB, 0x0 },
 264         { 0x00007011, 0x000000A4, 0x0 },
 265         { 0x00009010, 0x000000DF, 0x0 },
 266         { 0x00000018, 0x000000AA, 0x0 },
 267         { 0x00006013, 0x000000A4, 0x0 },
 268         { 0x00007011, 0x0000009D, 0x0 },
 269         { 0x00000018, 0x000000A0, 0x0 },
 270         { 0x00006012, 0x000000DF, 0x0 },
 271         { 0x00000018, 0x0000008A, 0x0 },
 272 };
 273
 274 /* Skylake/Kabylake U, H and S */
 275 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 276         { 0x00000018, 0x000000AC, 0x0 },
 277         { 0x00005012, 0x0000009D, 0x0 },
 278         { 0x00007011, 0x00000088, 0x0 },
 279         { 0x00000018, 0x000000A1, 0x0 },
 280         { 0x00000018, 0x00000098, 0x0 },
 281         { 0x00004013, 0x00000088, 0x0 },
 282         { 0x80006012, 0x000000CD, 0x1 },
 283         { 0x00000018, 0x000000DF, 0x0 },
 284         { 0x80003015, 0x000000CD, 0x1 },        /* Default */
 285         { 0x80003015, 0x000000C0, 0x1 },
 286         { 0x80000018, 0x000000C0, 0x1 },
 287 };
 288
 289 /* Skylake/Kabylake Y */
 290 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 291         { 0x00000018, 0x000000A1, 0x0 },
 292         { 0x00005012, 0x000000DF, 0x0 },
 293         { 0x80007011, 0x000000CB, 0x3 },
 294         { 0x00000018, 0x000000A4, 0x0 },
 295         { 0x00000018, 0x0000009D, 0x0 },
 296         { 0x00004013, 0x00000080, 0x0 },
 297         { 0x80006013, 0x000000C0, 0x3 },
 298         { 0x00000018, 0x0000008A, 0x0 },
 299         { 0x80003015, 0x000000C0, 0x3 },        /* Default */
 300         { 0x80003015, 0x000000C0, 0x3 },
 301         { 0x80000018, 0x000000C0, 0x3 },
 302 };
 303
 304 struct bxt_ddi_buf_trans {
 305         u8 margin;      /* swing value */
 306         u8 scale;       /* scale value */
 307         u8 enable;      /* scale enable */
 308         u8 deemphasis;
 309 };
 310
 311 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 312                                         /* Idx  NT mV diff      db  */
 313         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 314         { 78,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 315         { 104, 0x9A, 0, 64,  }, /* 2:   400             6   */
 316         { 154, 0x9A, 0, 43,  }, /* 3:   400             9.5 */
 317         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 318         { 116, 0x9A, 0, 85,  }, /* 5:   600             3.5 */
 319         { 154, 0x9A, 0, 64,  }, /* 6:   600             6   */
 320         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 321         { 154, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 322         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 323 };
 324
 325 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
 326                                         /* Idx  NT mV diff      db  */
 327         { 26, 0, 0, 128, },     /* 0:   200             0   */
 328         { 38, 0, 0, 112, },     /* 1:   200             1.5 */
 329         { 48, 0, 0, 96,  },     /* 2:   200             4   */
 330         { 54, 0, 0, 69,  },     /* 3:   200             6   */
 331         { 32, 0, 0, 128, },     /* 4:   250             0   */
 332         { 48, 0, 0, 104, },     /* 5:   250             1.5 */
 333         { 54, 0, 0, 85,  },     /* 6:   250             4   */
 334         { 43, 0, 0, 128, },     /* 7:   300             0   */
 335         { 54, 0, 0, 101, },     /* 8:   300             1.5 */
 336         { 48, 0, 0, 128, },     /* 9:   300             0   */
 337 };
 338
 339 /* BSpec has 2 recommended values - entries 0 and 8.
 340  * Using the entry with higher vswing.
 341  */
 342 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 343                                         /* Idx  NT mV diff      db  */
 344         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 345         { 52,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 346         { 52,  0x9A, 0, 64,  }, /* 2:   400             6   */
 347         { 42,  0x9A, 0, 43,  }, /* 3:   400             9.5 */
 348         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 349         { 77,  0x9A, 0, 85,  }, /* 5:   600             3.5 */
 350         { 77,  0x9A, 0, 64,  }, /* 6:   600             6   */
 351         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 352         { 102, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 353         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 354 };
 355
 356 struct cnl_ddi_buf_trans {
 357         u8 dw2_swing_sel;
 358         u8 dw7_n_scalar;
 359         u8 dw4_cursor_coeff;
 360         u8 dw4_post_cursor_2;
 361         u8 dw4_post_cursor_1;
 362 };
 363
 364 /* Voltage Swing Programming for VccIO 0.85V for DP */
 365 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
 366                                                 /* NT mV Trans mV db    */
 367         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 368         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 369         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 370         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 371         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 372         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 373         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 374         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 375         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 376         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 377 };
 378
 379 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
 380 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
 381                                                 /* NT mV Trans mV db    */
 382         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 383         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 384         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 385         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   */
 386         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 387         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 388         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 389 };
 390
 391 /* Voltage Swing Programming for VccIO 0.85V for eDP */
 392 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
 393                                                 /* NT mV Trans mV db    */
 394         { 0xA, 0x66, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 395         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 396         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 397         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 398         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 399         { 0xA, 0x66, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 400         { 0xB, 0x70, 0x3C, 0x00, 0x03 },        /* 460   600      2.3   */
 401         { 0xC, 0x75, 0x3C, 0x00, 0x03 },        /* 537   700      2.3   */
 402         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 403 };
 404
 405 /* Voltage Swing Programming for VccIO 0.95V for DP */
 406 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
 407                                                 /* NT mV Trans mV db    */
 408         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 409         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 410         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 411         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 412         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 413         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 414         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 415         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 416         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 417         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 418 };
 419
 420 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
 421 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
 422                                                 /* NT mV Trans mV db    */
 423         { 0xA, 0x5C, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 424         { 0xB, 0x69, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 425         { 0x5, 0x76, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 426         { 0xA, 0x5E, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 427         { 0xB, 0x69, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 428         { 0xB, 0x79, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 429         { 0x6, 0x7D, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 430         { 0x5, 0x76, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 431         { 0x6, 0x7D, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 432         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 433         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 434 };
 435
 436 /* Voltage Swing Programming for VccIO 0.95V for eDP */
 437 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
 438                                                 /* NT mV Trans mV db    */
 439         { 0xA, 0x61, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 440         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 441         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 442         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 443         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 444         { 0xA, 0x61, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 445         { 0xB, 0x68, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 446         { 0xC, 0x6E, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 447         { 0x4, 0x7F, 0x3A, 0x00, 0x05 },        /* 460   600      2.3   */
 448         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 449 };
 450
 451 /* Voltage Swing Programming for VccIO 1.05V for DP */
 452 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
 453                                                 /* NT mV Trans mV db    */
 454         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 455         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 456         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 457         { 0x6, 0x7F, 0x2C, 0x00, 0x13 },        /* 400   1050     8.4   */
 458         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 459         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 460         { 0x6, 0x7F, 0x30, 0x00, 0x0F },        /* 550   1050     5.6   */
 461         { 0x5, 0x76, 0x3E, 0x00, 0x01 },        /* 850   900      0.5   */
 462         { 0x6, 0x7F, 0x36, 0x00, 0x09 },        /* 750   1050     2.9   */
 463         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 464 };
 465
 466 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
 467 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
 468                                                 /* NT mV Trans mV db    */
 469         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 470         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 471         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 472         { 0xA, 0x5B, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 473         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 474         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 475         { 0x6, 0x7C, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 476         { 0x5, 0x70, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 477         { 0x6, 0x7C, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 478         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 479         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 480 };
 481
 482 /* Voltage Swing Programming for VccIO 1.05V for eDP */
 483 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
 484                                                 /* NT mV Trans mV db    */
 485         { 0xA, 0x5E, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 486         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 487         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 488         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 489         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 490         { 0xA, 0x5E, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 491         { 0xB, 0x64, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 492         { 0xE, 0x6A, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 493         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 494 };
 495
 496 struct icl_combo_phy_ddi_buf_trans {
 497         u32 dw2_swing_select;
 498         u32 dw2_swing_scalar;
 499         u32 dw4_scaling;
 500 };
 501
 502 /* Voltage Swing Programming for VccIO 0.85V for DP */
 503 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
 504                                 /* Voltage mV  db    */
 505         { 0x2, 0x98, 0x0018 },  /* 400         0.0   */
 506         { 0x2, 0x98, 0x3015 },  /* 400         3.5   */
 507         { 0x2, 0x98, 0x6012 },  /* 400         6.0   */
 508         { 0x2, 0x98, 0x900F },  /* 400         9.5   */
 509         { 0xB, 0x70, 0x0018 },  /* 600         0.0   */
 510         { 0xB, 0x70, 0x3015 },  /* 600         3.5   */
 511         { 0xB, 0x70, 0x6012 },  /* 600         6.0   */
 512         { 0x5, 0x00, 0x0018 },  /* 800         0.0   */
 513         { 0x5, 0x00, 0x3015 },  /* 800         3.5   */
 514         { 0x6, 0x98, 0x0018 },  /* 1200        0.0   */
 515 };
 516
 517 /* FIXME - After table is updated in Bspec */
 518 /* Voltage Swing Programming for VccIO 0.85V for eDP */
 519 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = {
 520                                 /* Voltage mV  db    */
 521         { 0x0, 0x00, 0x00 },    /* 200         0.0   */
 522         { 0x0, 0x00, 0x00 },    /* 200         1.5   */
 523         { 0x0, 0x00, 0x00 },    /* 200         4.0   */
 524         { 0x0, 0x00, 0x00 },    /* 200         6.0   */
 525         { 0x0, 0x00, 0x00 },    /* 250         0.0   */
 526         { 0x0, 0x00, 0x00 },    /* 250         1.5   */
 527         { 0x0, 0x00, 0x00 },    /* 250         4.0   */
 528         { 0x0, 0x00, 0x00 },    /* 300         0.0   */
 529         { 0x0, 0x00, 0x00 },    /* 300         1.5   */
 530         { 0x0, 0x00, 0x00 },    /* 350         0.0   */
 531 };
 532
 533 /* Voltage Swing Programming for VccIO 0.95V for DP */
 534 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
 535                                 /* Voltage mV  db    */
 536         { 0x2, 0x98, 0x0018 },  /* 400         0.0   */
 537         { 0x2, 0x98, 0x3015 },  /* 400         3.5   */
 538         { 0x2, 0x98, 0x6012 },  /* 400         6.0   */
 539         { 0x2, 0x98, 0x900F },  /* 400         9.5   */
 540         { 0x4, 0x98, 0x0018 },  /* 600         0.0   */
 541         { 0x4, 0x98, 0x3015 },  /* 600         3.5   */
 542         { 0x4, 0x98, 0x6012 },  /* 600         6.0   */
 543         { 0x5, 0x76, 0x0018 },  /* 800         0.0   */
 544         { 0x5, 0x76, 0x3015 },  /* 800         3.5   */
 545         { 0x6, 0x98, 0x0018 },  /* 1200        0.0   */
 546 };
 547
 548 /* FIXME - After table is updated in Bspec */
 549 /* Voltage Swing Programming for VccIO 0.95V for eDP */
 550 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = {
 551                                 /* Voltage mV  db    */
 552         { 0x0, 0x00, 0x00 },    /* 200         0.0   */
 553         { 0x0, 0x00, 0x00 },    /* 200         1.5   */
 554         { 0x0, 0x00, 0x00 },    /* 200         4.0   */
 555         { 0x0, 0x00, 0x00 },    /* 200         6.0   */
 556         { 0x0, 0x00, 0x00 },    /* 250         0.0   */
 557         { 0x0, 0x00, 0x00 },    /* 250         1.5   */
 558         { 0x0, 0x00, 0x00 },    /* 250         4.0   */
 559         { 0x0, 0x00, 0x00 },    /* 300         0.0   */
 560         { 0x0, 0x00, 0x00 },    /* 300         1.5   */
 561         { 0x0, 0x00, 0x00 },    /* 350         0.0   */
 562 };
 563
 564 /* Voltage Swing Programming for VccIO 1.05V for DP */
 565 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = {
 566                                 /* Voltage mV  db    */
 567         { 0x2, 0x98, 0x0018 },  /* 400         0.0   */
 568         { 0x2, 0x98, 0x3015 },  /* 400         3.5   */
 569         { 0x2, 0x98, 0x6012 },  /* 400         6.0   */
 570         { 0x2, 0x98, 0x900F },  /* 400         9.5   */
 571         { 0x4, 0x98, 0x0018 },  /* 600         0.0   */
 572         { 0x4, 0x98, 0x3015 },  /* 600         3.5   */
 573         { 0x4, 0x98, 0x6012 },  /* 600         6.0   */
 574         { 0x5, 0x71, 0x0018 },  /* 800         0.0   */
 575         { 0x5, 0x71, 0x3015 },  /* 800         3.5   */
 576         { 0x6, 0x98, 0x0018 },  /* 1200        0.0   */
 577 };
 578
 579 /* FIXME - After table is updated in Bspec */
 580 /* Voltage Swing Programming for VccIO 1.05V for eDP */
 581 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = {
 582                                 /* Voltage mV  db    */
 583         { 0x0, 0x00, 0x00 },    /* 200         0.0   */
 584         { 0x0, 0x00, 0x00 },    /* 200         1.5   */
 585         { 0x0, 0x00, 0x00 },    /* 200         4.0   */
 586         { 0x0, 0x00, 0x00 },    /* 200         6.0   */
 587         { 0x0, 0x00, 0x00 },    /* 250         0.0   */
 588         { 0x0, 0x00, 0x00 },    /* 250         1.5   */
 589         { 0x0, 0x00, 0x00 },    /* 250         4.0   */
 590         { 0x0, 0x00, 0x00 },    /* 300         0.0   */
 591         { 0x0, 0x00, 0x00 },    /* 300         1.5   */
 592         { 0x0, 0x00, 0x00 },    /* 350         0.0   */
 593 };
 594
 595 struct icl_mg_phy_ddi_buf_trans {
 596         u32 cri_txdeemph_override_5_0;
 597         u32 cri_txdeemph_override_11_6;
 598         u32 cri_txdeemph_override_17_12;
 599 };
 600
 601 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
 602                                 /* Voltage swing  pre-emphasis */
 603         { 0x0, 0x1B, 0x00 },    /* 0              0   */
 604         { 0x0, 0x23, 0x08 },    /* 0              1   */
 605         { 0x0, 0x2D, 0x12 },    /* 0              2   */
 606         { 0x0, 0x00, 0x00 },    /* 0              3   */
 607         { 0x0, 0x23, 0x00 },    /* 1              0   */
 608         { 0x0, 0x2B, 0x09 },    /* 1              1   */
 609         { 0x0, 0x2E, 0x11 },    /* 1              2   */
 610         { 0x0, 0x2F, 0x00 },    /* 2              0   */
 611         { 0x0, 0x33, 0x0C },    /* 2              1   */
 612         { 0x0, 0x00, 0x00 },    /* 3              0   */
 613 };
 614
 615 static const struct ddi_buf_trans *
 616 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 617 {
 618         if (dev_priv->vbt.edp.low_vswing) {
 619                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 620                 return bdw_ddi_translations_edp;
 621         } else {
 622                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 623                 return bdw_ddi_translations_dp;
 624         }
 625 }
 626
 627 static const struct ddi_buf_trans *
 628 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 629 {
 630         if (IS_SKL_ULX(dev_priv)) {
 631                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 632                 return skl_y_ddi_translations_dp;
 633         } else if (IS_SKL_ULT(dev_priv)) {
 634                 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 635                 return skl_u_ddi_translations_dp;
 636         } else {
 637                 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 638                 return skl_ddi_translations_dp;
 639         }
 640 }
 641
 642 static const struct ddi_buf_trans *
 643 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 644 {
 645         if (IS_KBL_ULX(dev_priv)) {
 646                 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
 647                 return kbl_y_ddi_translations_dp;
 648         } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
 649                 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
 650                 return kbl_u_ddi_translations_dp;
 651         } else {
 652                 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
 653                 return kbl_ddi_translations_dp;
 654         }
 655 }
 656
 657 static const struct ddi_buf_trans *
 658 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 659 {
 660         if (dev_priv->vbt.edp.low_vswing) {
 661                 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
 662                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
 663                         return skl_y_ddi_translations_edp;
 664                 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
 665                            IS_CFL_ULT(dev_priv)) {
 666                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
 667                         return skl_u_ddi_translations_edp;
 668                 } else {
 669                         *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 670                         return skl_ddi_translations_edp;
 671                 }
 672         }
 673
 674         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 675                 return kbl_get_buf_trans_dp(dev_priv, n_entries);
 676         else
 677                 return skl_get_buf_trans_dp(dev_priv, n_entries);
 678 }
 679
 680 static const struct ddi_buf_trans *
 681 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 682 {
 683         if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
 684                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 685                 return skl_y_ddi_translations_hdmi;
 686         } else {
 687                 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 688                 return skl_ddi_translations_hdmi;
 689         }
 690 }
 691
 692 static int skl_buf_trans_num_entries(enum port port, int n_entries)
 693 {
 694         /* Only DDIA and DDIE can select the 10th register with DP */
 695         if (port == PORT_A || port == PORT_E)
 696                 return min(n_entries, 10);
 697         else
 698                 return min(n_entries, 9);
 699 }
 700
 701 static const struct ddi_buf_trans *
 702 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
 703                            enum port port, int *n_entries)
 704 {
 705         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 706                 const struct ddi_buf_trans *ddi_translations =
 707                         kbl_get_buf_trans_dp(dev_priv, n_entries);
 708                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 709                 return ddi_translations;
 710         } else if (IS_SKYLAKE(dev_priv)) {
 711                 const struct ddi_buf_trans *ddi_translations =
 712                         skl_get_buf_trans_dp(dev_priv, n_entries);
 713                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 714                 return ddi_translations;
 715         } else if (IS_BROADWELL(dev_priv)) {
 716                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 717                 return  bdw_ddi_translations_dp;
 718         } else if (IS_HASWELL(dev_priv)) {
 719                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 720                 return hsw_ddi_translations_dp;
 721         }
 722
 723         *n_entries = 0;
 724         return NULL;
 725 }
 726
 727 static const struct ddi_buf_trans *
 728 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
 729                             enum port port, int *n_entries)
 730 {
 731         if (IS_GEN9_BC(dev_priv)) {
 732                 const struct ddi_buf_trans *ddi_translations =
 733                         skl_get_buf_trans_edp(dev_priv, n_entries);
 734                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 735                 return ddi_translations;
 736         } else if (IS_BROADWELL(dev_priv)) {
 737                 return bdw_get_buf_trans_edp(dev_priv, n_entries);
 738         } else if (IS_HASWELL(dev_priv)) {
 739                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 740                 return hsw_ddi_translations_dp;
 741         }
 742
 743         *n_entries = 0;
 744         return NULL;
 745 }
 746
 747 static const struct ddi_buf_trans *
 748 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
 749                             int *n_entries)
 750 {
 751         if (IS_BROADWELL(dev_priv)) {
 752                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
 753                 return bdw_ddi_translations_fdi;
 754         } else if (IS_HASWELL(dev_priv)) {
 755                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
 756                 return hsw_ddi_translations_fdi;
 757         }
 758
 759         *n_entries = 0;
 760         return NULL;
 761 }
 762
 763 static const struct ddi_buf_trans *
 764 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
 765                              int *n_entries)
 766 {
 767         if (IS_GEN9_BC(dev_priv)) {
 768                 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
 769         } else if (IS_BROADWELL(dev_priv)) {
 770                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 771                 return bdw_ddi_translations_hdmi;
 772         } else if (IS_HASWELL(dev_priv)) {
 773                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 774                 return hsw_ddi_translations_hdmi;
 775         }
 776
 777         *n_entries = 0;
 778         return NULL;
 779 }
 780
 781 static const struct bxt_ddi_buf_trans *
 782 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 783 {
 784         *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
 785         return bxt_ddi_translations_dp;
 786 }
 787
 788 static const struct bxt_ddi_buf_trans *
 789 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 790 {
 791         if (dev_priv->vbt.edp.low_vswing) {
 792                 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
 793                 return bxt_ddi_translations_edp;
 794         }
 795
 796         return bxt_get_buf_trans_dp(dev_priv, n_entries);
 797 }
 798
 799 static const struct bxt_ddi_buf_trans *
 800 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 801 {
 802         *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
 803         return bxt_ddi_translations_hdmi;
 804 }
 805
 806 static const struct cnl_ddi_buf_trans *
 807 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 808 {
 809         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 810
 811         if (voltage == VOLTAGE_INFO_0_85V) {
 812                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
 813                 return cnl_ddi_translations_hdmi_0_85V;
 814         } else if (voltage == VOLTAGE_INFO_0_95V) {
 815                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
 816                 return cnl_ddi_translations_hdmi_0_95V;
 817         } else if (voltage == VOLTAGE_INFO_1_05V) {
 818                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
 819                 return cnl_ddi_translations_hdmi_1_05V;
 820         } else {
 821                 *n_entries = 1; /* shut up gcc */
 822                 MISSING_CASE(voltage);
 823         }
 824         return NULL;
 825 }
 826
 827 static const struct cnl_ddi_buf_trans *
 828 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 829 {
 830         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 831
 832         if (voltage == VOLTAGE_INFO_0_85V) {
 833                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
 834                 return cnl_ddi_translations_dp_0_85V;
 835         } else if (voltage == VOLTAGE_INFO_0_95V) {
 836                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
 837                 return cnl_ddi_translations_dp_0_95V;
 838         } else if (voltage == VOLTAGE_INFO_1_05V) {
 839                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
 840                 return cnl_ddi_translations_dp_1_05V;
 841         } else {
 842                 *n_entries = 1; /* shut up gcc */
 843                 MISSING_CASE(voltage);
 844         }
 845         return NULL;
 846 }
 847
 848 static const struct cnl_ddi_buf_trans *
 849 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 850 {
 851         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 852
 853         if (dev_priv->vbt.edp.low_vswing) {
 854                 if (voltage == VOLTAGE_INFO_0_85V) {
 855                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
 856                         return cnl_ddi_translations_edp_0_85V;
 857                 } else if (voltage == VOLTAGE_INFO_0_95V) {
 858                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
 859                         return cnl_ddi_translations_edp_0_95V;
 860                 } else if (voltage == VOLTAGE_INFO_1_05V) {
 861                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
 862                         return cnl_ddi_translations_edp_1_05V;
 863                 } else {
 864                         *n_entries = 1; /* shut up gcc */
 865                         MISSING_CASE(voltage);
 866                 }
 867                 return NULL;
 868         } else {
 869                 return cnl_get_buf_trans_dp(dev_priv, n_entries);
 870         }
 871 }
 872
 873 static const struct icl_combo_phy_ddi_buf_trans *
 874 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
 875                         int type, int *n_entries)
 876 {
 877         u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK;
 878
 879         if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
 880                 switch (voltage) {
 881                 case VOLTAGE_INFO_0_85V:
 882                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V);
 883                         return icl_combo_phy_ddi_translations_edp_0_85V;
 884                 case VOLTAGE_INFO_0_95V:
 885                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V);
 886                         return icl_combo_phy_ddi_translations_edp_0_95V;
 887                 case VOLTAGE_INFO_1_05V:
 888                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V);
 889                         return icl_combo_phy_ddi_translations_edp_1_05V;
 890                 default:
 891                         MISSING_CASE(voltage);
 892                         return NULL;
 893                 }
 894         } else {
 895                 switch (voltage) {
 896                 case VOLTAGE_INFO_0_85V:
 897                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V);
 898                         return icl_combo_phy_ddi_translations_dp_hdmi_0_85V;
 899                 case VOLTAGE_INFO_0_95V:
 900                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V);
 901                         return icl_combo_phy_ddi_translations_dp_hdmi_0_95V;
 902                 case VOLTAGE_INFO_1_05V:
 903                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);
 904                         return icl_combo_phy_ddi_translations_dp_hdmi_1_05V;
 905                 default:
 906                         MISSING_CASE(voltage);
 907                         return NULL;
 908                 }
 909         }
 910 }
 911
 912 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
 913 {
 914         int n_entries, level, default_entry;
 915
 916         level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 917
 918         if (IS_ICELAKE(dev_priv)) {
 919                 if (intel_port_is_combophy(dev_priv, port))
 920                         icl_get_combo_buf_trans(dev_priv, port,
 921                                                 INTEL_OUTPUT_HDMI, &n_entries);
 922                 else
 923                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
 924                 default_entry = n_entries - 1;
 925         } else if (IS_CANNONLAKE(dev_priv)) {
 926                 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
 927                 default_entry = n_entries - 1;
 928         } else if (IS_GEN9_LP(dev_priv)) {
 929                 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
 930                 default_entry = n_entries - 1;
 931         } else if (IS_GEN9_BC(dev_priv)) {
 932                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 933                 default_entry = 8;
 934         } else if (IS_BROADWELL(dev_priv)) {
 935                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 936                 default_entry = 7;
 937         } else if (IS_HASWELL(dev_priv)) {
 938                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 939                 default_entry = 6;
 940         } else {
 941                 WARN(1, "ddi translation table missing\n");
 942                 return 0;
 943         }
 944
 945         /* Choose a good default if VBT is badly populated */
 946         if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
 947                 level = default_entry;
 948
 949         if (WARN_ON_ONCE(n_entries == 0))
 950                 return 0;
 951         if (WARN_ON_ONCE(level >= n_entries))
 952                 level = n_entries - 1;
 953
 954         return level;
 955 }
 956
 957 /*
 958  * Starting with Haswell, DDI port buffers must be programmed with correct
 959  * values in advance. This function programs the correct values for
 960  * DP/eDP/FDI use cases.
 961  */
 962 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
 963                                          const struct intel_crtc_state *crtc_state)
 964 {
 965         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 966         u32 iboost_bit = 0;
 967         int i, n_entries;
 968         enum port port = encoder->port;
 969         const struct ddi_buf_trans *ddi_translations;
 970
 971         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
 972                 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
 973                                                                &n_entries);
 974         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 975                 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
 976                                                                &n_entries);
 977         else
 978                 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
 979                                                               &n_entries);
 980
 981         /* If we're boosting the current, set bit 31 of trans1 */
 982         if (IS_GEN9_BC(dev_priv) &&
 983             dev_priv->vbt.ddi_port_info[port].dp_boost_level)
 984                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 985
 986         for (i = 0; i < n_entries; i++) {
 987                 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
 988                            ddi_translations[i].trans1 | iboost_bit);
 989                 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
 990                            ddi_translations[i].trans2);
 991         }
 992 }
 993
 994 /*
 995  * Starting with Haswell, DDI port buffers must be programmed with correct
 996  * values in advance. This function programs the correct values for
 997  * HDMI/DVI use cases.
 998  */
 999 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
1000                                            int level)
1001 {
1002         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1003         u32 iboost_bit = 0;
1004         int n_entries;
1005         enum port port = encoder->port;
1006         const struct ddi_buf_trans *ddi_translations;
1007
1008         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1009
1010         if (WARN_ON_ONCE(!ddi_translations))
1011                 return;
1012         if (WARN_ON_ONCE(level >= n_entries))
1013                 level = n_entries - 1;
1014
1015         /* If we're boosting the current, set bit 31 of trans1 */
1016         if (IS_GEN9_BC(dev_priv) &&
1017             dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
1018                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
1019
1020         /* Entry 9 is for HDMI: */
1021         I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
1022                    ddi_translations[level].trans1 | iboost_bit);
1023         I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
1024                    ddi_translations[level].trans2);
1025 }
1026
1027 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
1028                                     enum port port)
1029 {
1030         i915_reg_t reg = DDI_BUF_CTL(port);
1031         int i;
1032
1033         for (i = 0; i < 16; i++) {
1034                 udelay(1);
1035                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
1036                         return;
1037         }
1038         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
1039 }
1040
1041 static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
1042 {
1043         switch (pll->info->id) {
1044         case DPLL_ID_WRPLL1:
1045                 return PORT_CLK_SEL_WRPLL1;
1046         case DPLL_ID_WRPLL2:
1047                 return PORT_CLK_SEL_WRPLL2;
1048         case DPLL_ID_SPLL:
1049                 return PORT_CLK_SEL_SPLL;
1050         case DPLL_ID_LCPLL_810:
1051                 return PORT_CLK_SEL_LCPLL_810;
1052         case DPLL_ID_LCPLL_1350:
1053                 return PORT_CLK_SEL_LCPLL_1350;
1054         case DPLL_ID_LCPLL_2700:
1055                 return PORT_CLK_SEL_LCPLL_2700;
1056         default:
1057                 MISSING_CASE(pll->info->id);
1058                 return PORT_CLK_SEL_NONE;
1059         }
1060 }
1061
1062 static uint32_t icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
1063                                        const struct intel_shared_dpll *pll)
1064 {
1065         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1066         int clock = crtc->config->port_clock;
1067         const enum intel_dpll_id id = pll->info->id;
1068
1069         switch (id) {
1070         default:
1071                 MISSING_CASE(id);
1072                 /* fall through */
1073         case DPLL_ID_ICL_DPLL0:
1074         case DPLL_ID_ICL_DPLL1:
1075                 return DDI_CLK_SEL_NONE;
1076         case DPLL_ID_ICL_TBTPLL:
1077                 switch (clock) {
1078                 case 162000:
1079                         return DDI_CLK_SEL_TBT_162;
1080                 case 270000:
1081                         return DDI_CLK_SEL_TBT_270;
1082                 case 540000:
1083                         return DDI_CLK_SEL_TBT_540;
1084                 case 810000:
1085                         return DDI_CLK_SEL_TBT_810;
1086                 default:
1087                         MISSING_CASE(clock);
1088                         break;
1089                 }
1090         case DPLL_ID_ICL_MGPLL1:
1091         case DPLL_ID_ICL_MGPLL2:
1092         case DPLL_ID_ICL_MGPLL3:
1093         case DPLL_ID_ICL_MGPLL4:
1094                 return DDI_CLK_SEL_MG;
1095         }
1096 }
1097
1098 /* Starting with Haswell, different DDI ports can work in FDI mode for
1099  * connection to the PCH-located connectors. For this, it is necessary to train
1100  * both the DDI port and PCH receiver for the desired DDI buffer settings.
1101  *
1102  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1103  * please note that when FDI mode is active on DDI E, it shares 2 lines with
1104  * DDI A (which is used for eDP)
1105  */
1106
1107 void hsw_fdi_link_train(struct intel_crtc *crtc,
1108                         const struct intel_crtc_state *crtc_state)
1109 {
1110         struct drm_device *dev = crtc->base.dev;
1111         struct drm_i915_private *dev_priv = to_i915(dev);
1112         struct intel_encoder *encoder;
1113         u32 temp, i, rx_ctl_val, ddi_pll_sel;
1114
1115         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1116                 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
1117                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
1118         }
1119
1120         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1121          * mode set "sequence for CRT port" document:
1122          * - TP1 to TP2 time with the default value
1123          * - FDI delay to 90h
1124          *
1125          * WaFDIAutoLinkSetTimingOverrride:hsw
1126          */
1127         I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
1128                                   FDI_RX_PWRDN_LANE0_VAL(2) |
1129                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1130
1131         /* Enable the PCH Receiver FDI PLL */
1132         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
1133                      FDI_RX_PLL_ENABLE |
1134                      FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
1135         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1136         POSTING_READ(FDI_RX_CTL(PIPE_A));
1137         udelay(220);
1138
1139         /* Switch from Rawclk to PCDclk */
1140         rx_ctl_val |= FDI_PCDCLK;
1141         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1142
1143         /* Configure Port Clock Select */
1144         ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
1145         I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1146         WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
1147
1148         /* Start the training iterating through available voltages and emphasis,
1149          * testing each value twice. */
1150         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
1151                 /* Configure DP_TP_CTL with auto-training */
1152                 I915_WRITE(DP_TP_CTL(PORT_E),
1153                                         DP_TP_CTL_FDI_AUTOTRAIN |
1154                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1155                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
1156                                         DP_TP_CTL_ENABLE);
1157
1158                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1159                  * DDI E does not support port reversal, the functionality is
1160                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1161                  * port reversal bit */
1162                 I915_WRITE(DDI_BUF_CTL(PORT_E),
1163                            DDI_BUF_CTL_ENABLE |
1164                            ((crtc_state->fdi_lanes - 1) << 1) |
1165                            DDI_BUF_TRANS_SELECT(i / 2));
1166                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1167
1168                 udelay(600);
1169
1170                 /* Program PCH FDI Receiver TU */
1171                 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
1172
1173                 /* Enable PCH FDI Receiver with auto-training */
1174                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
1175                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1176                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1177
1178                 /* Wait for FDI receiver lane calibration */
1179                 udelay(30);
1180
1181                 /* Unset FDI_RX_MISC pwrdn lanes */
1182                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1183                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1184                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1185                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1186
1187                 /* Wait for FDI auto training time */
1188                 udelay(5);
1189
1190                 temp = I915_READ(DP_TP_STATUS(PORT_E));
1191                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1192                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
1193                         break;
1194                 }
1195
1196                 /*
1197                  * Leave things enabled even if we failed to train FDI.
1198                  * Results in less fireworks from the state checker.
1199                  */
1200                 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1201                         DRM_ERROR("FDI link training failed!\n");
1202                         break;
1203                 }
1204
1205                 rx_ctl_val &= ~FDI_RX_ENABLE;
1206                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1207                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1208
1209                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1210                 temp &= ~DDI_BUF_CTL_ENABLE;
1211                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1212                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1213
1214                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1215                 temp = I915_READ(DP_TP_CTL(PORT_E));
1216                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1217                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1218                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1219                 POSTING_READ(DP_TP_CTL(PORT_E));
1220
1221                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1222
1223                 /* Reset FDI_RX_MISC pwrdn lanes */
1224                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1225                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1226                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1227                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1228                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1229         }
1230
1231         /* Enable normal pixel sending for FDI */
1232         I915_WRITE(DP_TP_CTL(PORT_E),
1233                    DP_TP_CTL_FDI_AUTOTRAIN |
1234                    DP_TP_CTL_LINK_TRAIN_NORMAL |
1235                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1236                    DP_TP_CTL_ENABLE);
1237 }
1238
1239 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1240 {
1241         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1242         struct intel_digital_port *intel_dig_port =
1243                 enc_to_dig_port(&encoder->base);
1244
1245         intel_dp->DP = intel_dig_port->saved_port_bits |
1246                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1247         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1248 }
1249
1250 static struct intel_encoder *
1251 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
1252 {
1253         struct drm_device *dev = crtc->base.dev;
1254         struct intel_encoder *encoder, *ret = NULL;
1255         int num_encoders = 0;
1256
1257         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1258                 ret = encoder;
1259                 num_encoders++;
1260         }
1261
1262         if (num_encoders != 1)
1263                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
1264                      pipe_name(crtc->pipe));
1265
1266         BUG_ON(ret == NULL);
1267         return ret;
1268 }
1269
1270 #define LC_FREQ 2700
1271
1272 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1273                                    i915_reg_t reg)
1274 {
1275         int refclk = LC_FREQ;
1276         int n, p, r;
1277         u32 wrpll;
1278
1279         wrpll = I915_READ(reg);
1280         switch (wrpll & WRPLL_PLL_REF_MASK) {
1281         case WRPLL_PLL_SSC:
1282         case WRPLL_PLL_NON_SSC:
1283                 /*
1284                  * We could calculate spread here, but our checking
1285                  * code only cares about 5% accuracy, and spread is a max of
1286                  * 0.5% downspread.
1287                  */
1288                 refclk = 135;
1289                 break;
1290         case WRPLL_PLL_LCPLL:
1291                 refclk = LC_FREQ;
1292                 break;
1293         default:
1294                 WARN(1, "bad wrpll refclk\n");
1295                 return 0;
1296         }
1297
1298         r = wrpll & WRPLL_DIVIDER_REF_MASK;
1299         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1300         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1301
1302         /* Convert to KHz, p & r have a fixed point portion */
1303         return (refclk * n * 100) / (p * r);
1304 }
1305
1306 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1307                                enum intel_dpll_id pll_id)
1308 {
1309         i915_reg_t cfgcr1_reg, cfgcr2_reg;
1310         uint32_t cfgcr1_val, cfgcr2_val;
1311         uint32_t p0, p1, p2, dco_freq;
1312
1313         cfgcr1_reg = DPLL_CFGCR1(pll_id);
1314         cfgcr2_reg = DPLL_CFGCR2(pll_id);
1315
1316         cfgcr1_val = I915_READ(cfgcr1_reg);
1317         cfgcr2_val = I915_READ(cfgcr2_reg);
1318
1319         p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
1320         p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
1321
1322         if (cfgcr2_val &  DPLL_CFGCR2_QDIV_MODE(1))
1323                 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1324         else
1325                 p1 = 1;
1326
1327
1328         switch (p0) {
1329         case DPLL_CFGCR2_PDIV_1:
1330                 p0 = 1;
1331                 break;
1332         case DPLL_CFGCR2_PDIV_2:
1333                 p0 = 2;
1334                 break;
1335         case DPLL_CFGCR2_PDIV_3:
1336                 p0 = 3;
1337                 break;
1338         case DPLL_CFGCR2_PDIV_7:
1339                 p0 = 7;
1340                 break;
1341         }
1342
1343         switch (p2) {
1344         case DPLL_CFGCR2_KDIV_5:
1345                 p2 = 5;
1346                 break;
1347         case DPLL_CFGCR2_KDIV_2:
1348                 p2 = 2;
1349                 break;
1350         case DPLL_CFGCR2_KDIV_3:
1351                 p2 = 3;
1352                 break;
1353         case DPLL_CFGCR2_KDIV_1:
1354                 p2 = 1;
1355                 break;
1356         }
1357
1358         dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1359
1360         dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1361                 1000) / 0x8000;
1362
1363         return dco_freq / (p0 * p1 * p2 * 5);
1364 }
1365
1366 static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1367                                enum intel_dpll_id pll_id)
1368 {
1369         uint32_t cfgcr0, cfgcr1;
1370         uint32_t p0, p1, p2, dco_freq, ref_clock;
1371
1372         if (INTEL_GEN(dev_priv) >= 11) {
1373                 cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
1374                 cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
1375         } else {
1376                 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1377                 cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
1378         }
1379
1380         p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1381         p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1382
1383         if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1384                 p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1385                         DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1386         else
1387                 p1 = 1;
1388
1389
1390         switch (p0) {
1391         case DPLL_CFGCR1_PDIV_2:
1392                 p0 = 2;
1393                 break;
1394         case DPLL_CFGCR1_PDIV_3:
1395                 p0 = 3;
1396                 break;
1397         case DPLL_CFGCR1_PDIV_5:
1398                 p0 = 5;
1399                 break;
1400         case DPLL_CFGCR1_PDIV_7:
1401                 p0 = 7;
1402                 break;
1403         }
1404
1405         switch (p2) {
1406         case DPLL_CFGCR1_KDIV_1:
1407                 p2 = 1;
1408                 break;
1409         case DPLL_CFGCR1_KDIV_2:
1410                 p2 = 2;
1411                 break;
1412         case DPLL_CFGCR1_KDIV_4:
1413                 p2 = 4;
1414                 break;
1415         }
1416
1417         ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
1418
1419         dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
1420
1421         dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1422                       DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
1423
1424         if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1425                 return 0;
1426
1427         return dco_freq / (p0 * p1 * p2 * 5);
1428 }
1429
1430 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1431                                  enum port port)
1432 {
1433         u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1434
1435         switch (val) {
1436         case DDI_CLK_SEL_NONE:
1437                 return 0;
1438         case DDI_CLK_SEL_TBT_162:
1439                 return 162000;
1440         case DDI_CLK_SEL_TBT_270:
1441                 return 270000;
1442         case DDI_CLK_SEL_TBT_540:
1443                 return 540000;
1444         case DDI_CLK_SEL_TBT_810:
1445                 return 810000;
1446         default:
1447                 MISSING_CASE(val);
1448                 return 0;
1449         }
1450 }
1451
1452 static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
1453                                 enum port port)
1454 {
1455         u32 mg_pll_div0, mg_clktop_hsclkctl;
1456         u32 m1, m2_int, m2_frac, div1, div2, refclk;
1457         u64 tmp;
1458
1459         refclk = dev_priv->cdclk.hw.ref;
1460
1461         mg_pll_div0 = I915_READ(MG_PLL_DIV0(port));
1462         mg_clktop_hsclkctl = I915_READ(MG_CLKTOP2_HSCLKCTL(port));
1463
1464         m1 = I915_READ(MG_PLL_DIV1(port)) & MG_PLL_DIV1_FBPREDIV_MASK;
1465         m2_int = mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
1466         m2_frac = (mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ?
1467                   (mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >>
1468                   MG_PLL_DIV0_FBDIV_FRAC_SHIFT : 0;
1469
1470         switch (mg_clktop_hsclkctl & MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
1471         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
1472                 div1 = 2;
1473                 break;
1474         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
1475                 div1 = 3;
1476                 break;
1477         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
1478                 div1 = 5;
1479                 break;
1480         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
1481                 div1 = 7;
1482                 break;
1483         default:
1484                 MISSING_CASE(mg_clktop_hsclkctl);
1485                 return 0;
1486         }
1487
1488         div2 = (mg_clktop_hsclkctl & MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
1489                 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
1490         /* div2 value of 0 is same as 1 means no div */
1491         if (div2 == 0)
1492                 div2 = 1;
1493
1494         /*
1495          * Adjust the original formula to delay the division by 2^22 in order to
1496          * minimize possible rounding errors.
1497          */
1498         tmp = (u64)m1 * m2_int * refclk +
1499               (((u64)m1 * m2_frac * refclk) >> 22);
1500         tmp = div_u64(tmp, 5 * div1 * div2);
1501
1502         return tmp;
1503 }
1504
1505 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1506 {
1507         int dotclock;
1508
1509         if (pipe_config->has_pch_encoder)
1510                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1511                                                     &pipe_config->fdi_m_n);
1512         else if (intel_crtc_has_dp_encoder(pipe_config))
1513                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1514                                                     &pipe_config->dp_m_n);
1515         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1516                 dotclock = pipe_config->port_clock * 2 / 3;
1517         else
1518                 dotclock = pipe_config->port_clock;
1519
1520         if (pipe_config->ycbcr420)
1521                 dotclock *= 2;
1522
1523         if (pipe_config->pixel_multiplier)
1524                 dotclock /= pipe_config->pixel_multiplier;
1525
1526         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1527 }
1528
1529 static void icl_ddi_clock_get(struct intel_encoder *encoder,
1530                               struct intel_crtc_state *pipe_config)
1531 {
1532         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1533         enum port port = encoder->port;
1534         int link_clock = 0;
1535         uint32_t pll_id;
1536
1537         pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1538         if (intel_port_is_combophy(dev_priv, port)) {
1539                 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
1540                         link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1541                 else
1542                         link_clock = icl_calc_dp_combo_pll_link(dev_priv,
1543                                                                 pll_id);
1544         } else {
1545                 if (pll_id == DPLL_ID_ICL_TBTPLL)
1546                         link_clock = icl_calc_tbt_pll_link(dev_priv, port);
1547                 else
1548                         link_clock = icl_calc_mg_pll_link(dev_priv, port);
1549         }
1550
1551         pipe_config->port_clock = link_clock;
1552         ddi_dotclock_get(pipe_config);
1553 }
1554
1555 static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1556                               struct intel_crtc_state *pipe_config)
1557 {
1558         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1559         int link_clock = 0;
1560         uint32_t cfgcr0;
1561         enum intel_dpll_id pll_id;
1562
1563         pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1564
1565         cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1566
1567         if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1568                 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1569         } else {
1570                 link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1571
1572                 switch (link_clock) {
1573                 case DPLL_CFGCR0_LINK_RATE_810:
1574                         link_clock = 81000;
1575                         break;
1576                 case DPLL_CFGCR0_LINK_RATE_1080:
1577                         link_clock = 108000;
1578                         break;
1579                 case DPLL_CFGCR0_LINK_RATE_1350:
1580                         link_clock = 135000;
1581                         break;
1582                 case DPLL_CFGCR0_LINK_RATE_1620:
1583                         link_clock = 162000;
1584                         break;
1585                 case DPLL_CFGCR0_LINK_RATE_2160:
1586                         link_clock = 216000;
1587                         break;
1588                 case DPLL_CFGCR0_LINK_RATE_2700:
1589                         link_clock = 270000;
1590                         break;
1591                 case DPLL_CFGCR0_LINK_RATE_3240:
1592                         link_clock = 324000;
1593                         break;
1594                 case DPLL_CFGCR0_LINK_RATE_4050:
1595                         link_clock = 405000;
1596                         break;
1597                 default:
1598                         WARN(1, "Unsupported link rate\n");
1599                         break;
1600                 }
1601                 link_clock *= 2;
1602         }
1603
1604         pipe_config->port_clock = link_clock;
1605
1606         ddi_dotclock_get(pipe_config);
1607 }
1608
1609 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1610                                 struct intel_crtc_state *pipe_config)
1611 {
1612         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1613         int link_clock = 0;
1614         uint32_t dpll_ctl1;
1615         enum intel_dpll_id pll_id;
1616
1617         pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1618
1619         dpll_ctl1 = I915_READ(DPLL_CTRL1);
1620
1621         if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(pll_id)) {
1622                 link_clock = skl_calc_wrpll_link(dev_priv, pll_id);
1623         } else {
1624                 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(pll_id);
1625                 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(pll_id);
1626
1627                 switch (link_clock) {
1628                 case DPLL_CTRL1_LINK_RATE_810:
1629                         link_clock = 81000;
1630                         break;
1631                 case DPLL_CTRL1_LINK_RATE_1080:
1632                         link_clock = 108000;
1633                         break;
1634                 case DPLL_CTRL1_LINK_RATE_1350:
1635                         link_clock = 135000;
1636                         break;
1637                 case DPLL_CTRL1_LINK_RATE_1620:
1638                         link_clock = 162000;
1639                         break;
1640                 case DPLL_CTRL1_LINK_RATE_2160:
1641                         link_clock = 216000;
1642                         break;
1643                 case DPLL_CTRL1_LINK_RATE_2700:
1644                         link_clock = 270000;
1645                         break;
1646                 default:
1647                         WARN(1, "Unsupported link rate\n");
1648                         break;
1649                 }
1650                 link_clock *= 2;
1651         }
1652
1653         pipe_config->port_clock = link_clock;
1654
1655         ddi_dotclock_get(pipe_config);
1656 }
1657
1658 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1659                               struct intel_crtc_state *pipe_config)
1660 {
1661         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1662         int link_clock = 0;
1663         u32 val, pll;
1664
1665         val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1666         switch (val & PORT_CLK_SEL_MASK) {
1667         case PORT_CLK_SEL_LCPLL_810:
1668                 link_clock = 81000;
1669                 break;
1670         case PORT_CLK_SEL_LCPLL_1350:
1671                 link_clock = 135000;
1672                 break;
1673         case PORT_CLK_SEL_LCPLL_2700:
1674                 link_clock = 270000;
1675                 break;
1676         case PORT_CLK_SEL_WRPLL1:
1677                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1678                 break;
1679         case PORT_CLK_SEL_WRPLL2:
1680                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1681                 break;
1682         case PORT_CLK_SEL_SPLL:
1683                 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1684                 if (pll == SPLL_PLL_FREQ_810MHz)
1685                         link_clock = 81000;
1686                 else if (pll == SPLL_PLL_FREQ_1350MHz)
1687                         link_clock = 135000;
1688                 else if (pll == SPLL_PLL_FREQ_2700MHz)
1689                         link_clock = 270000;
1690                 else {
1691                         WARN(1, "bad spll freq\n");
1692                         return;
1693                 }
1694                 break;
1695         default:
1696                 WARN(1, "bad port clock sel\n");
1697                 return;
1698         }
1699
1700         pipe_config->port_clock = link_clock * 2;
1701
1702         ddi_dotclock_get(pipe_config);
1703 }
1704
1705 static int bxt_calc_pll_link(struct intel_crtc_state *crtc_state)
1706 {
1707         struct intel_dpll_hw_state *state;
1708         struct dpll clock;
1709
1710         /* For DDI ports we always use a shared PLL. */
1711         if (WARN_ON(!crtc_state->shared_dpll))
1712                 return 0;
1713
1714         state = &crtc_state->dpll_hw_state;
1715
1716         clock.m1 = 2;
1717         clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1718         if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1719                 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1720         clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1721         clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1722         clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1723
1724         return chv_calc_dpll_params(100000, &clock);
1725 }
1726
1727 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1728                               struct intel_crtc_state *pipe_config)
1729 {
1730         pipe_config->port_clock = bxt_calc_pll_link(pipe_config);
1731
1732         ddi_dotclock_get(pipe_config);
1733 }
1734
1735 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1736                                 struct intel_crtc_state *pipe_config)
1737 {
1738         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1739
1740         if (INTEL_GEN(dev_priv) <= 8)
1741                 hsw_ddi_clock_get(encoder, pipe_config);
1742         else if (IS_GEN9_BC(dev_priv))
1743                 skl_ddi_clock_get(encoder, pipe_config);
1744         else if (IS_GEN9_LP(dev_priv))
1745                 bxt_ddi_clock_get(encoder, pipe_config);
1746         else if (IS_CANNONLAKE(dev_priv))
1747                 cnl_ddi_clock_get(encoder, pipe_config);
1748         else if (IS_ICELAKE(dev_priv))
1749                 icl_ddi_clock_get(encoder, pipe_config);
1750 }
1751
1752 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
1753 {
1754         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1755         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1756         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1757         u32 temp;
1758
1759         if (!intel_crtc_has_dp_encoder(crtc_state))
1760                 return;
1761
1762         WARN_ON(transcoder_is_dsi(cpu_transcoder));
1763
1764         temp = TRANS_MSA_SYNC_CLK;
1765
1766         if (crtc_state->limited_color_range)
1767                 temp |= TRANS_MSA_CEA_RANGE;
1768
1769         switch (crtc_state->pipe_bpp) {
1770         case 18:
1771                 temp |= TRANS_MSA_6_BPC;
1772                 break;
1773         case 24:
1774                 temp |= TRANS_MSA_8_BPC;
1775                 break;
1776         case 30:
1777                 temp |= TRANS_MSA_10_BPC;
1778                 break;
1779         case 36:
1780                 temp |= TRANS_MSA_12_BPC;
1781                 break;
1782         default:
1783                 MISSING_CASE(crtc_state->pipe_bpp);
1784                 break;
1785         }
1786
1787         I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1788 }
1789
1790 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1791                                     bool state)
1792 {
1793         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1794         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1795         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1796         uint32_t temp;
1797
1798         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1799         if (state == true)
1800                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1801         else
1802                 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1803         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1804 }
1805
1806 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1807 {
1808         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1809         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1810         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1811         enum pipe pipe = crtc->pipe;
1812         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1813         enum port port = encoder->port;
1814         uint32_t temp;
1815
1816         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1817         temp = TRANS_DDI_FUNC_ENABLE;
1818         temp |= TRANS_DDI_SELECT_PORT(port);
1819
1820         switch (crtc_state->pipe_bpp) {
1821         case 18:
1822                 temp |= TRANS_DDI_BPC_6;
1823                 break;
1824         case 24:
1825                 temp |= TRANS_DDI_BPC_8;
1826                 break;
1827         case 30:
1828                 temp |= TRANS_DDI_BPC_10;
1829                 break;
1830         case 36:
1831                 temp |= TRANS_DDI_BPC_12;
1832                 break;
1833         default:
1834                 BUG();
1835         }
1836
1837         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1838                 temp |= TRANS_DDI_PVSYNC;
1839         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1840                 temp |= TRANS_DDI_PHSYNC;
1841
1842         if (cpu_transcoder == TRANSCODER_EDP) {
1843                 switch (pipe) {
1844                 case PIPE_A:
1845                         /* On Haswell, can only use the always-on power well for
1846                          * eDP when not using the panel fitter, and when not
1847                          * using motion blur mitigation (which we don't
1848                          * support). */
1849                         if (IS_HASWELL(dev_priv) &&
1850                             (crtc_state->pch_pfit.enabled ||
1851                              crtc_state->pch_pfit.force_thru))
1852                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1853                         else
1854                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1855                         break;
1856                 case PIPE_B:
1857                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1858                         break;
1859                 case PIPE_C:
1860                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1861                         break;
1862                 default:
1863                         BUG();
1864                         break;
1865                 }
1866         }
1867
1868         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1869                 if (crtc_state->has_hdmi_sink)
1870                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1871                 else
1872                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1873
1874                 if (crtc_state->hdmi_scrambling)
1875                         temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK;
1876                 if (crtc_state->hdmi_high_tmds_clock_ratio)
1877                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1878         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1879                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1880                 temp |= (crtc_state->fdi_lanes - 1) << 1;
1881         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1882                 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1883                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1884         } else {
1885                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1886                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1887         }
1888
1889         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1890 }
1891
1892 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
1893 {
1894         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1895         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1896         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1897         i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1898         uint32_t val = I915_READ(reg);
1899
1900         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1901         val |= TRANS_DDI_PORT_NONE;
1902         I915_WRITE(reg, val);
1903
1904         if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1905             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1906                 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
1907                 /* Quirk time at 100ms for reliable operation */
1908                 msleep(100);
1909         }
1910 }
1911
1912 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1913                                      bool enable)
1914 {
1915         struct drm_device *dev = intel_encoder->base.dev;
1916         struct drm_i915_private *dev_priv = to_i915(dev);
1917         enum pipe pipe = 0;
1918         int ret = 0;
1919         uint32_t tmp;
1920
1921         if (WARN_ON(!intel_display_power_get_if_enabled(dev_priv,
1922                                                 intel_encoder->power_domain)))
1923                 return -ENXIO;
1924
1925         if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1926                 ret = -EIO;
1927                 goto out;
1928         }
1929
1930         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1931         if (enable)
1932                 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1933         else
1934                 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1935         I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1936 out:
1937         intel_display_power_put(dev_priv, intel_encoder->power_domain);
1938         return ret;
1939 }
1940
1941 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1942 {
1943         struct drm_device *dev = intel_connector->base.dev;
1944         struct drm_i915_private *dev_priv = to_i915(dev);
1945         struct intel_encoder *encoder = intel_connector->encoder;
1946         int type = intel_connector->base.connector_type;
1947         enum port port = encoder->port;
1948         enum pipe pipe = 0;
1949         enum transcoder cpu_transcoder;
1950         uint32_t tmp;
1951         bool ret;
1952
1953         if (!intel_display_power_get_if_enabled(dev_priv,
1954                                                 encoder->power_domain))
1955                 return false;
1956
1957         if (!encoder->get_hw_state(encoder, &pipe)) {
1958                 ret = false;
1959                 goto out;
1960         }
1961
1962         if (port == PORT_A)
1963                 cpu_transcoder = TRANSCODER_EDP;
1964         else
1965                 cpu_transcoder = (enum transcoder) pipe;
1966
1967         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1968
1969         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1970         case TRANS_DDI_MODE_SELECT_HDMI:
1971         case TRANS_DDI_MODE_SELECT_DVI:
1972                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1973                 break;
1974
1975         case TRANS_DDI_MODE_SELECT_DP_SST:
1976                 ret = type == DRM_MODE_CONNECTOR_eDP ||
1977                       type == DRM_MODE_CONNECTOR_DisplayPort;
1978                 break;
1979
1980         case TRANS_DDI_MODE_SELECT_DP_MST:
1981                 /* if the transcoder is in MST state then
1982                  * connector isn't connected */
1983                 ret = false;
1984                 break;
1985
1986         case TRANS_DDI_MODE_SELECT_FDI:
1987                 ret = type == DRM_MODE_CONNECTOR_VGA;
1988                 break;
1989
1990         default:
1991                 ret = false;
1992                 break;
1993         }
1994
1995 out:
1996         intel_display_power_put(dev_priv, encoder->power_domain);
1997
1998         return ret;
1999 }
2000
2001 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2002                             enum pipe *pipe)
2003 {
2004         struct drm_device *dev = encoder->base.dev;
2005         struct drm_i915_private *dev_priv = to_i915(dev);
2006         enum port port = encoder->port;
2007         enum pipe p;
2008         u32 tmp;
2009         bool ret;
2010
2011         if (!intel_display_power_get_if_enabled(dev_priv,
2012                                                 encoder->power_domain))
2013                 return false;
2014
2015         ret = false;
2016
2017         tmp = I915_READ(DDI_BUF_CTL(port));
2018
2019         if (!(tmp & DDI_BUF_CTL_ENABLE))
2020                 goto out;
2021
2022         if (port == PORT_A) {
2023                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
2024
2025                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
2026                 case TRANS_DDI_EDP_INPUT_A_ON:
2027                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
2028                         *pipe = PIPE_A;
2029                         break;
2030                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
2031                         *pipe = PIPE_B;
2032                         break;
2033                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
2034                         *pipe = PIPE_C;
2035                         break;
2036                 }
2037
2038                 ret = true;
2039
2040                 goto out;
2041         }
2042
2043         for_each_pipe(dev_priv, p) {
2044                 enum transcoder cpu_transcoder = (enum transcoder) p;
2045
2046                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2047
2048                 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
2049                         if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
2050                             TRANS_DDI_MODE_SELECT_DP_MST)
2051                                 goto out;
2052
2053                         *pipe = p;
2054                         ret = true;
2055
2056                         goto out;
2057                 }
2058         }
2059
2060         DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
2061
2062 out:
2063         if (ret && IS_GEN9_LP(dev_priv)) {
2064                 tmp = I915_READ(BXT_PHY_CTL(port));
2065                 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2066                             BXT_PHY_LANE_POWERDOWN_ACK |
2067                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
2068                         DRM_ERROR("Port %c enabled but PHY powered down? "
2069                                   "(PHY_CTL %08x)\n", port_name(port), tmp);
2070         }
2071
2072         intel_display_power_put(dev_priv, encoder->power_domain);
2073
2074         return ret;
2075 }
2076
2077 static inline enum intel_display_power_domain
2078 intel_ddi_main_link_aux_domain(struct intel_dp *intel_dp)
2079 {
2080         /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
2081          * DC states enabled at the same time, while for driver initiated AUX
2082          * transfers we need the same AUX IOs to be powered but with DC states
2083          * disabled. Accordingly use the AUX power domain here which leaves DC
2084          * states enabled.
2085          * However, for non-A AUX ports the corresponding non-EDP transcoders
2086          * would have already enabled power well 2 and DC_OFF. This means we can
2087          * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2088          * specific AUX_IO reference without powering up any extra wells.
2089          * Note that PSR is enabled only on Port A even though this function
2090          * returns the correct domain for other ports too.
2091          */
2092         return intel_dp->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
2093                                               intel_dp->aux_power_domain;
2094 }
2095
2096 static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder,
2097                                        struct intel_crtc_state *crtc_state)
2098 {
2099         struct intel_digital_port *dig_port;
2100         u64 domains;
2101
2102         /*
2103          * TODO: Add support for MST encoders. Atm, the following should never
2104          * happen since fake-MST encoders don't set their get_power_domains()
2105          * hook.
2106          */
2107         if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
2108                 return 0;
2109
2110         dig_port = enc_to_dig_port(&encoder->base);
2111         domains = BIT_ULL(dig_port->ddi_io_power_domain);
2112
2113         /* AUX power is only needed for (e)DP mode, not for HDMI. */
2114         if (intel_crtc_has_dp_encoder(crtc_state)) {
2115                 struct intel_dp *intel_dp = &dig_port->dp;
2116
2117                 domains |= BIT_ULL(intel_ddi_main_link_aux_domain(intel_dp));
2118         }
2119
2120         return domains;
2121 }
2122
2123 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
2124 {
2125         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2126         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2127         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
2128         enum port port = encoder->port;
2129         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2130
2131         if (cpu_transcoder != TRANSCODER_EDP)
2132                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2133                            TRANS_CLK_SEL_PORT(port));
2134 }
2135
2136 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
2137 {
2138         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2139         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2140
2141         if (cpu_transcoder != TRANSCODER_EDP)
2142                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2143                            TRANS_CLK_SEL_DISABLED);
2144 }
2145
2146 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2147                                 enum port port, uint8_t iboost)
2148 {
2149         u32 tmp;
2150
2151         tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
2152         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2153         if (iboost)
2154                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2155         else
2156                 tmp |= BALANCE_LEG_DISABLE(port);
2157         I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
2158 }
2159
2160 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2161                                int level, enum intel_output_type type)
2162 {
2163         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2164         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2165         enum port port = encoder->port;
2166         uint8_t iboost;
2167
2168         if (type == INTEL_OUTPUT_HDMI)
2169                 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2170         else
2171                 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2172
2173         if (iboost == 0) {
2174                 const struct ddi_buf_trans *ddi_translations;
2175                 int n_entries;
2176
2177                 if (type == INTEL_OUTPUT_HDMI)
2178                         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2179                 else if (type == INTEL_OUTPUT_EDP)
2180                         ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2181                 else
2182                         ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2183
2184                 if (WARN_ON_ONCE(!ddi_translations))
2185                         return;
2186                 if (WARN_ON_ONCE(level >= n_entries))
2187                         level = n_entries - 1;
2188
2189                 iboost = ddi_translations[level].i_boost;
2190         }
2191
2192         /* Make sure that the requested I_boost is valid */
2193         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2194                 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2195                 return;
2196         }
2197
2198         _skl_ddi_set_iboost(dev_priv, port, iboost);
2199
2200         if (port == PORT_A && intel_dig_port->max_lanes == 4)
2201                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
2202 }
2203
2204 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2205                                     int level, enum intel_output_type type)
2206 {
2207         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2208         const struct bxt_ddi_buf_trans *ddi_translations;
2209         enum port port = encoder->port;
2210         int n_entries;
2211
2212         if (type == INTEL_OUTPUT_HDMI)
2213                 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2214         else if (type == INTEL_OUTPUT_EDP)
2215                 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2216         else
2217                 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
2218
2219         if (WARN_ON_ONCE(!ddi_translations))
2220                 return;
2221         if (WARN_ON_ONCE(level >= n_entries))
2222                 level = n_entries - 1;
2223
2224         bxt_ddi_phy_set_signal_level(dev_priv, port,
2225                                      ddi_translations[level].margin,
2226                                      ddi_translations[level].scale,
2227                                      ddi_translations[level].enable,
2228                                      ddi_translations[level].deemphasis);
2229 }
2230
2231 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2232 {
2233         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2234         enum port port = encoder->port;
2235         int n_entries;
2236
2237         if (IS_ICELAKE(dev_priv)) {
2238                 if (intel_port_is_combophy(dev_priv, port))
2239                         icl_get_combo_buf_trans(dev_priv, port, encoder->type,
2240                                                 &n_entries);
2241                 else
2242                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2243         } else if (IS_CANNONLAKE(dev_priv)) {
2244                 if (encoder->type == INTEL_OUTPUT_EDP)
2245                         cnl_get_buf_trans_edp(dev_priv, &n_entries);
2246                 else
2247                         cnl_get_buf_trans_dp(dev_priv, &n_entries);
2248         } else if (IS_GEN9_LP(dev_priv)) {
2249                 if (encoder->type == INTEL_OUTPUT_EDP)
2250                         bxt_get_buf_trans_edp(dev_priv, &n_entries);
2251                 else
2252                         bxt_get_buf_trans_dp(dev_priv, &n_entries);
2253         } else {
2254                 if (encoder->type == INTEL_OUTPUT_EDP)
2255                         intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2256                 else
2257                         intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2258         }
2259
2260         if (WARN_ON(n_entries < 1))
2261                 n_entries = 1;
2262         if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2263                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2264
2265         return index_to_dp_signal_levels[n_entries - 1] &
2266                 DP_TRAIN_VOLTAGE_SWING_MASK;
2267 }
2268
2269 /*
2270  * We assume that the full set of pre-emphasis values can be
2271  * used on all DDI platforms. Should that change we need to
2272  * rethink this code.
2273  */
2274 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2275 {
2276         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2277         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2278                 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2279         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2280                 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2281         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2282                 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2283         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2284         default:
2285                 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2286         }
2287 }
2288
2289 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2290                                    int level, enum intel_output_type type)
2291 {
2292         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2293         const struct cnl_ddi_buf_trans *ddi_translations;
2294         enum port port = encoder->port;
2295         int n_entries, ln;
2296         u32 val;
2297
2298         if (type == INTEL_OUTPUT_HDMI)
2299                 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
2300         else if (type == INTEL_OUTPUT_EDP)
2301                 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
2302         else
2303                 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
2304
2305         if (WARN_ON_ONCE(!ddi_translations))
2306                 return;
2307         if (WARN_ON_ONCE(level >= n_entries))
2308                 level = n_entries - 1;
2309
2310         /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2311         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2312         val &= ~SCALING_MODE_SEL_MASK;
2313         val |= SCALING_MODE_SEL(2);
2314         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2315
2316         /* Program PORT_TX_DW2 */
2317         val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
2318         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2319                  RCOMP_SCALAR_MASK);
2320         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2321         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2322         /* Rcomp scalar is fixed as 0x98 for every table entry */
2323         val |= RCOMP_SCALAR(0x98);
2324         I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
2325
2326         /* Program PORT_TX_DW4 */
2327         /* We cannot write to GRP. It would overrite individual loadgen */
2328         for (ln = 0; ln < 4; ln++) {
2329                 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2330                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2331                          CURSOR_COEFF_MASK);
2332                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2333                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2334                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2335                 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2336         }
2337
2338         /* Program PORT_TX_DW5 */
2339         /* All DW5 values are fixed for every table entry */
2340         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2341         val &= ~RTERM_SELECT_MASK;
2342         val |= RTERM_SELECT(6);
2343         val |= TAP3_DISABLE;
2344         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2345
2346         /* Program PORT_TX_DW7 */
2347         val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
2348         val &= ~N_SCALAR_MASK;
2349         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2350         I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2351 }
2352
2353 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2354                                     int level, enum intel_output_type type)
2355 {
2356         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2357         enum port port = encoder->port;
2358         int width, rate, ln;
2359         u32 val;
2360
2361         if (type == INTEL_OUTPUT_HDMI) {
2362                 width = 4;
2363                 rate = 0; /* Rate is always < than 6GHz for HDMI */
2364         } else {
2365                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2366
2367                 width = intel_dp->lane_count;
2368                 rate = intel_dp->link_rate;
2369         }
2370
2371         /*
2372          * 1. If port type is eDP or DP,
2373          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2374          * else clear to 0b.
2375          */
2376         val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
2377         if (type != INTEL_OUTPUT_HDMI)
2378                 val |= COMMON_KEEPER_EN;
2379         else
2380                 val &= ~COMMON_KEEPER_EN;
2381         I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2382
2383         /* 2. Program loadgen select */
2384         /*
2385          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2386          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2387          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2388          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2389          */
2390         for (ln = 0; ln <= 3; ln++) {
2391                 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2392                 val &= ~LOADGEN_SELECT;
2393
2394                 if ((rate <= 600000 && width == 4 && ln >= 1)  ||
2395                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2396                         val |= LOADGEN_SELECT;
2397                 }
2398                 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2399         }
2400
2401         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2402         val = I915_READ(CNL_PORT_CL1CM_DW5);
2403         val |= SUS_CLOCK_CONFIG;
2404         I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2405
2406         /* 4. Clear training enable to change swing values */
2407         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2408         val &= ~TX_TRAINING_EN;
2409         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2410
2411         /* 5. Program swing and de-emphasis */
2412         cnl_ddi_vswing_program(encoder, level, type);
2413
2414         /* 6. Set training enable to trigger update */
2415         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2416         val |= TX_TRAINING_EN;
2417         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2418 }
2419
2420 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
2421                                          u32 level, enum port port, int type)
2422 {
2423         const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL;
2424         u32 n_entries, val;
2425         int ln;
2426
2427         ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
2428                                                    &n_entries);
2429         if (!ddi_translations)
2430                 return;
2431
2432         if (level >= n_entries) {
2433                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
2434                 level = n_entries - 1;
2435         }
2436
2437         /* Set PORT_TX_DW5 Rterm Sel to 110b. */
2438         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2439         val &= ~RTERM_SELECT_MASK;
2440         val |= RTERM_SELECT(0x6);
2441         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2442
2443         /* Program PORT_TX_DW5 */
2444         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2445         /* Set DisableTap2 and DisableTap3 if MIPI DSI
2446          * Clear DisableTap2 and DisableTap3 for all other Ports
2447          */
2448         if (type == INTEL_OUTPUT_DSI) {
2449                 val |= TAP2_DISABLE;
2450                 val |= TAP3_DISABLE;
2451         } else {
2452                 val &= ~TAP2_DISABLE;
2453                 val &= ~TAP3_DISABLE;
2454         }
2455         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2456
2457         /* Program PORT_TX_DW2 */
2458         val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
2459         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2460                  RCOMP_SCALAR_MASK);
2461         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_select);
2462         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_select);
2463         /* Program Rcomp scalar for every table entry */
2464         val |= RCOMP_SCALAR(ddi_translations[level].dw2_swing_scalar);
2465         I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
2466
2467         /* Program PORT_TX_DW4 */
2468         /* We cannot write to GRP. It would overwrite individual loadgen. */
2469         for (ln = 0; ln <= 3; ln++) {
2470                 val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
2471                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2472                          CURSOR_COEFF_MASK);
2473                 val |= ddi_translations[level].dw4_scaling;
2474                 I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
2475         }
2476 }
2477
2478 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2479                                               u32 level,
2480                                               enum intel_output_type type)
2481 {
2482         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2483         enum port port = encoder->port;
2484         int width = 0;
2485         int rate = 0;
2486         u32 val;
2487         int ln = 0;
2488
2489         if (type == INTEL_OUTPUT_HDMI) {
2490                 width = 4;
2491                 /* Rate is always < than 6GHz for HDMI */
2492         } else {
2493                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2494
2495                 width = intel_dp->lane_count;
2496                 rate = intel_dp->link_rate;
2497         }
2498
2499         /*
2500          * 1. If port type is eDP or DP,
2501          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2502          * else clear to 0b.
2503          */
2504         val = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
2505         if (type == INTEL_OUTPUT_HDMI)
2506                 val &= ~COMMON_KEEPER_EN;
2507         else
2508                 val |= COMMON_KEEPER_EN;
2509         I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), val);
2510
2511         /* 2. Program loadgen select */
2512         /*
2513          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2514          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2515          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2516          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2517          */
2518         for (ln = 0; ln <= 3; ln++) {
2519                 val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
2520                 val &= ~LOADGEN_SELECT;
2521
2522                 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2523                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2524                         val |= LOADGEN_SELECT;
2525                 }
2526                 I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
2527         }
2528
2529         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2530         val = I915_READ(ICL_PORT_CL_DW5(port));
2531         val |= SUS_CLOCK_CONFIG;
2532         I915_WRITE(ICL_PORT_CL_DW5(port), val);
2533
2534         /* 4. Clear training enable to change swing values */
2535         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2536         val &= ~TX_TRAINING_EN;
2537         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2538
2539         /* 5. Program swing and de-emphasis */
2540         icl_ddi_combo_vswing_program(dev_priv, level, port, type);
2541
2542         /* 6. Set training enable to trigger update */
2543         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2544         val |= TX_TRAINING_EN;
2545         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2546 }
2547
2548 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2549                                            int link_clock,
2550                                            u32 level)
2551 {
2552         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2553         enum port port = encoder->port;
2554         const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2555         u32 n_entries, val;
2556         int ln;
2557
2558         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2559         ddi_translations = icl_mg_phy_ddi_translations;
2560         /* The table does not have values for level 3 and level 9. */
2561         if (level >= n_entries || level == 3 || level == 9) {
2562                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.",
2563                               level, n_entries - 2);
2564                 level = n_entries - 2;
2565         }
2566
2567         /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2568         for (ln = 0; ln < 2; ln++) {
2569                 val = I915_READ(MG_TX1_LINK_PARAMS(port, ln));
2570                 val &= ~CRI_USE_FS32;
2571                 I915_WRITE(MG_TX1_LINK_PARAMS(port, ln), val);
2572
2573                 val = I915_READ(MG_TX2_LINK_PARAMS(port, ln));
2574                 val &= ~CRI_USE_FS32;
2575                 I915_WRITE(MG_TX2_LINK_PARAMS(port, ln), val);
2576         }
2577
2578         /* Program MG_TX_SWINGCTRL with values from vswing table */
2579         for (ln = 0; ln < 2; ln++) {
2580                 val = I915_READ(MG_TX1_SWINGCTRL(port, ln));
2581                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2582                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2583                         ddi_translations[level].cri_txdeemph_override_17_12);
2584                 I915_WRITE(MG_TX1_SWINGCTRL(port, ln), val);
2585
2586                 val = I915_READ(MG_TX2_SWINGCTRL(port, ln));
2587                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2588                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2589                         ddi_translations[level].cri_txdeemph_override_17_12);
2590                 I915_WRITE(MG_TX2_SWINGCTRL(port, ln), val);
2591         }
2592
2593         /* Program MG_TX_DRVCTRL with values from vswing table */
2594         for (ln = 0; ln < 2; ln++) {
2595                 val = I915_READ(MG_TX1_DRVCTRL(port, ln));
2596                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2597                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2598                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2599                         ddi_translations[level].cri_txdeemph_override_5_0) |
2600                         CRI_TXDEEMPH_OVERRIDE_11_6(
2601                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2602                         CRI_TXDEEMPH_OVERRIDE_EN;
2603                 I915_WRITE(MG_TX1_DRVCTRL(port, ln), val);
2604
2605                 val = I915_READ(MG_TX2_DRVCTRL(port, ln));
2606                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2607                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2608                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2609                         ddi_translations[level].cri_txdeemph_override_5_0) |
2610                         CRI_TXDEEMPH_OVERRIDE_11_6(
2611                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2612                         CRI_TXDEEMPH_OVERRIDE_EN;
2613                 I915_WRITE(MG_TX2_DRVCTRL(port, ln), val);
2614
2615                 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2616         }
2617
2618         /*
2619          * Program MG_CLKHUB<LN, port being used> with value from frequency table
2620          * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2621          * values from table for which TX1 and TX2 enabled.
2622          */
2623         for (ln = 0; ln < 2; ln++) {
2624                 val = I915_READ(MG_CLKHUB(port, ln));
2625                 if (link_clock < 300000)
2626                         val |= CFG_LOW_RATE_LKREN_EN;
2627                 else
2628                         val &= ~CFG_LOW_RATE_LKREN_EN;
2629                 I915_WRITE(MG_CLKHUB(port, ln), val);
2630         }
2631
2632         /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2633         for (ln = 0; ln < 2; ln++) {
2634                 val = I915_READ(MG_TX1_DCC(port, ln));
2635                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2636                 if (link_clock <= 500000) {
2637                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2638                 } else {
2639                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2640                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2641                 }
2642                 I915_WRITE(MG_TX1_DCC(port, ln), val);
2643
2644                 val = I915_READ(MG_TX2_DCC(port, ln));
2645                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2646                 if (link_clock <= 500000) {
2647                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2648                 } else {
2649                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2650                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2651                 }
2652                 I915_WRITE(MG_TX2_DCC(port, ln), val);
2653         }
2654
2655         /* Program MG_TX_PISO_READLOAD with values from vswing table */
2656         for (ln = 0; ln < 2; ln++) {
2657                 val = I915_READ(MG_TX1_PISO_READLOAD(port, ln));
2658                 val |= CRI_CALCINIT;
2659                 I915_WRITE(MG_TX1_PISO_READLOAD(port, ln), val);
2660
2661                 val = I915_READ(MG_TX2_PISO_READLOAD(port, ln));
2662                 val |= CRI_CALCINIT;
2663                 I915_WRITE(MG_TX2_PISO_READLOAD(port, ln), val);
2664         }
2665 }
2666
2667 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2668                                     int link_clock,
2669                                     u32 level,
2670                                     enum intel_output_type type)
2671 {
2672         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2673         enum port port = encoder->port;
2674
2675         if (intel_port_is_combophy(dev_priv, port))
2676                 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2677         else
2678                 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
2679 }
2680
2681 static uint32_t translate_signal_level(int signal_levels)
2682 {
2683         int i;
2684
2685         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2686                 if (index_to_dp_signal_levels[i] == signal_levels)
2687                         return i;
2688         }
2689
2690         WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2691              signal_levels);
2692
2693         return 0;
2694 }
2695
2696 static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
2697 {
2698         uint8_t train_set = intel_dp->train_set[0];
2699         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2700                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2701
2702         return translate_signal_level(signal_levels);
2703 }
2704
2705 u32 bxt_signal_levels(struct intel_dp *intel_dp)
2706 {
2707         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2708         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2709         struct intel_encoder *encoder = &dport->base;
2710         int level = intel_ddi_dp_level(intel_dp);
2711
2712         if (IS_ICELAKE(dev_priv))
2713                 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2714                                         level, encoder->type);
2715         else if (IS_CANNONLAKE(dev_priv))
2716                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2717         else
2718                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2719
2720         return 0;
2721 }
2722
2723 uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2724 {
2725         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2726         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2727         struct intel_encoder *encoder = &dport->base;
2728         int level = intel_ddi_dp_level(intel_dp);
2729
2730         if (IS_GEN9_BC(dev_priv))
2731                 skl_ddi_set_iboost(encoder, level, encoder->type);
2732
2733         return DDI_BUF_TRANS_SELECT(level);
2734 }
2735
2736 static inline
2737 uint32_t icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2738                                    enum port port)
2739 {
2740         if (intel_port_is_combophy(dev_priv, port)) {
2741                 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2742         } else if (intel_port_is_tc(dev_priv, port)) {
2743                 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2744
2745                 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2746         }
2747
2748         return 0;
2749 }
2750
2751 void icl_map_plls_to_ports(struct drm_crtc *crtc,
2752                            struct intel_crtc_state *crtc_state,
2753                            struct drm_atomic_state *old_state)
2754 {
2755         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2756         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2757         struct drm_connector_state *conn_state;
2758         struct drm_connector *conn;
2759         int i;
2760
2761         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
2762                 struct intel_encoder *encoder =
2763                         to_intel_encoder(conn_state->best_encoder);
2764                 enum port port;
2765                 uint32_t val;
2766
2767                 if (conn_state->crtc != crtc)
2768                         continue;
2769
2770                 port = encoder->port;
2771                 mutex_lock(&dev_priv->dpll_lock);
2772
2773                 val = I915_READ(DPCLKA_CFGCR0_ICL);
2774                 WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
2775
2776                 if (intel_port_is_combophy(dev_priv, port)) {
2777                         val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2778                         val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2779                         I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2780                         POSTING_READ(DPCLKA_CFGCR0_ICL);
2781                 }
2782
2783                 val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2784                 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2785
2786                 mutex_unlock(&dev_priv->dpll_lock);
2787         }
2788 }
2789
2790 void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
2791                              struct intel_crtc_state *crtc_state,
2792                              struct drm_atomic_state *old_state)
2793 {
2794         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2795         struct drm_connector_state *old_conn_state;
2796         struct drm_connector *conn;
2797         int i;
2798
2799         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
2800                 struct intel_encoder *encoder =
2801                         to_intel_encoder(old_conn_state->best_encoder);
2802                 enum port port;
2803
2804                 if (old_conn_state->crtc != crtc)
2805                         continue;
2806
2807                 port = encoder->port;
2808                 mutex_lock(&dev_priv->dpll_lock);
2809                 I915_WRITE(DPCLKA_CFGCR0_ICL,
2810                            I915_READ(DPCLKA_CFGCR0_ICL) |
2811                            icl_dpclka_cfgcr0_clk_off(dev_priv, port));
2812                 mutex_unlock(&dev_priv->dpll_lock);
2813         }
2814 }
2815
2816 static void intel_ddi_clk_select(struct intel_encoder *encoder,
2817                                  const struct intel_shared_dpll *pll)
2818 {
2819         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2820         enum port port = encoder->port;
2821         uint32_t val;
2822
2823         if (WARN_ON(!pll))
2824                 return;
2825
2826         mutex_lock(&dev_priv->dpll_lock);
2827
2828         if (IS_ICELAKE(dev_priv)) {
2829                 if (!intel_port_is_combophy(dev_priv, port))
2830                         I915_WRITE(DDI_CLK_SEL(port),
2831                                    icl_pll_to_ddi_pll_sel(encoder, pll));
2832         } else if (IS_CANNONLAKE(dev_priv)) {
2833                 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2834                 val = I915_READ(DPCLKA_CFGCR0);
2835                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2836                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2837                 I915_WRITE(DPCLKA_CFGCR0, val);
2838
2839                 /*
2840                  * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2841                  * This step and the step before must be done with separate
2842                  * register writes.
2843                  */
2844                 val = I915_READ(DPCLKA_CFGCR0);
2845                 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2846                 I915_WRITE(DPCLKA_CFGCR0, val);
2847         } else if (IS_GEN9_BC(dev_priv)) {
2848                 /* DDI -> PLL mapping  */
2849                 val = I915_READ(DPLL_CTRL2);
2850
2851                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2852                          DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2853                 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
2854                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2855
2856                 I915_WRITE(DPLL_CTRL2, val);
2857
2858         } else if (INTEL_GEN(dev_priv) < 9) {
2859                 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
2860         }
2861
2862         mutex_unlock(&dev_priv->dpll_lock);
2863 }
2864
2865 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2866 {
2867         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2868         enum port port = encoder->port;
2869
2870         if (IS_ICELAKE(dev_priv)) {
2871                 if (!intel_port_is_combophy(dev_priv, port))
2872                         I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
2873         } else if (IS_CANNONLAKE(dev_priv)) {
2874                 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2875                            DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2876         } else if (IS_GEN9_BC(dev_priv)) {
2877                 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
2878                            DPLL_CTRL2_DDI_CLK_OFF(port));
2879         } else if (INTEL_GEN(dev_priv) < 9) {
2880                 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2881         }
2882 }
2883
2884 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
2885                                     const struct intel_crtc_state *crtc_state,
2886                                     const struct drm_connector_state *conn_state)
2887 {
2888         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2889         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2890         enum port port = encoder->port;
2891         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2892         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2893         int level = intel_ddi_dp_level(intel_dp);
2894
2895         WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
2896
2897         intel_display_power_get(dev_priv,
2898                                 intel_ddi_main_link_aux_domain(intel_dp));
2899
2900         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
2901                                  crtc_state->lane_count, is_mst);
2902
2903         intel_edp_panel_on(intel_dp);
2904
2905         intel_ddi_clk_select(encoder, crtc_state->shared_dpll);
2906
2907         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2908
2909         icl_program_mg_dp_mode(intel_dp);
2910         icl_disable_phy_clock_gating(dig_port);
2911
2912         if (IS_ICELAKE(dev_priv))
2913                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
2914                                         level, encoder->type);
2915         else if (IS_CANNONLAKE(dev_priv))
2916                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2917         else if (IS_GEN9_LP(dev_priv))
2918                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2919         else
2920                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
2921
2922         intel_ddi_init_dp_buf_reg(encoder);
2923         if (!is_mst)
2924                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2925         intel_dp_start_link_train(intel_dp);
2926         if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
2927                 intel_dp_stop_link_train(intel_dp);
2928
2929         icl_enable_phy_clock_gating(dig_port);
2930
2931         if (!is_mst)
2932                 intel_ddi_enable_pipe_clock(crtc_state);
2933 }
2934
2935 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
2936                                       const struct intel_crtc_state *crtc_state,
2937                                       const struct drm_connector_state *conn_state)
2938 {
2939         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2940         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2941         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2942         enum port port = encoder->port;
2943         int level = intel_ddi_hdmi_level(dev_priv, port);
2944         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2945
2946         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2947         intel_ddi_clk_select(encoder, crtc_state->shared_dpll);
2948
2949         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2950
2951         if (IS_ICELAKE(dev_priv))
2952                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
2953                                         level, INTEL_OUTPUT_HDMI);
2954         else if (IS_CANNONLAKE(dev_priv))
2955                 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2956         else if (IS_GEN9_LP(dev_priv))
2957                 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2958         else
2959                 intel_prepare_hdmi_ddi_buffers(encoder, level);
2960
2961         if (IS_GEN9_BC(dev_priv))
2962                 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
2963
2964         intel_ddi_enable_pipe_clock(crtc_state);
2965
2966         intel_dig_port->set_infoframes(&encoder->base,
2967                                        crtc_state->has_infoframe,
2968                                        crtc_state, conn_state);
2969 }
2970
2971 static void intel_ddi_pre_enable(struct intel_encoder *encoder,
2972                                  const struct intel_crtc_state *crtc_state,
2973                                  const struct drm_connector_state *conn_state)
2974 {
2975         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2976         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2977         enum pipe pipe = crtc->pipe;
2978
2979         /*
2980          * When called from DP MST code:
2981          * - conn_state will be NULL
2982          * - encoder will be the main encoder (ie. mst->primary)
2983          * - the main connector associated with this port
2984          *   won't be active or linked to a crtc
2985          * - crtc_state will be the state of the first stream to
2986          *   be activated on this port, and it may not be the same
2987          *   stream that will be deactivated last, but each stream
2988          *   should have a state that is identical when it comes to
2989          *   the DP link parameteres
2990          */
2991
2992         WARN_ON(crtc_state->has_pch_encoder);
2993
2994         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2995
2996         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2997                 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
2998         else
2999                 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3000 }
3001
3002 static void intel_disable_ddi_buf(struct intel_encoder *encoder)
3003 {
3004         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3005         enum port port = encoder->port;
3006         bool wait = false;
3007         u32 val;
3008
3009         val = I915_READ(DDI_BUF_CTL(port));
3010         if (val & DDI_BUF_CTL_ENABLE) {
3011                 val &= ~DDI_BUF_CTL_ENABLE;
3012                 I915_WRITE(DDI_BUF_CTL(port), val);
3013                 wait = true;
3014         }
3015
3016         val = I915_READ(DP_TP_CTL(port));
3017         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3018         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3019         I915_WRITE(DP_TP_CTL(port), val);
3020
3021         if (wait)
3022                 intel_wait_ddi_buf_idle(dev_priv, port);
3023 }
3024
3025 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
3026                                       const struct intel_crtc_state *old_crtc_state,
3027                                       const struct drm_connector_state *old_conn_state)
3028 {
3029         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3030         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3031         struct intel_dp *intel_dp = &dig_port->dp;
3032         bool is_mst = intel_crtc_has_type(old_crtc_state,
3033                                           INTEL_OUTPUT_DP_MST);
3034
3035         if (!is_mst) {
3036                 intel_ddi_disable_pipe_clock(old_crtc_state);
3037                 /*
3038                  * Power down sink before disabling the port, otherwise we end
3039                  * up getting interrupts from the sink on detecting link loss.
3040                  */
3041                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3042         }
3043
3044         intel_disable_ddi_buf(encoder);
3045
3046         intel_edp_panel_vdd_on(intel_dp);
3047         intel_edp_panel_off(intel_dp);
3048
3049         intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
3050
3051         intel_ddi_clk_disable(encoder);
3052
3053         intel_display_power_put(dev_priv,
3054                                 intel_ddi_main_link_aux_domain(intel_dp));
3055 }
3056
3057 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
3058                                         const struct intel_crtc_state *old_crtc_state,
3059                                         const struct drm_connector_state *old_conn_state)
3060 {
3061         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3062         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3063         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3064
3065         dig_port->set_infoframes(&encoder->base, false,
3066                                  old_crtc_state, old_conn_state);
3067
3068         intel_ddi_disable_pipe_clock(old_crtc_state);
3069
3070         intel_disable_ddi_buf(encoder);
3071
3072         intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
3073
3074         intel_ddi_clk_disable(encoder);
3075
3076         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3077 }
3078
3079 static void intel_ddi_post_disable(struct intel_encoder *encoder,
3080                                    const struct intel_crtc_state *old_crtc_state,
3081                                    const struct drm_connector_state *old_conn_state)
3082 {
3083         /*
3084          * When called from DP MST code:
3085          * - old_conn_state will be NULL
3086          * - encoder will be the main encoder (ie. mst->primary)
3087          * - the main connector associated with this port
3088          *   won't be active or linked to a crtc
3089          * - old_crtc_state will be the state of the last stream to
3090          *   be deactivated on this port, and it may not be the same
3091          *   stream that was activated last, but each stream
3092          *   should have a state that is identical when it comes to
3093          *   the DP link parameteres
3094          */
3095
3096         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3097                 intel_ddi_post_disable_hdmi(encoder,
3098                                             old_crtc_state, old_conn_state);
3099         else
3100                 intel_ddi_post_disable_dp(encoder,
3101                                           old_crtc_state, old_conn_state);
3102 }
3103
3104 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
3105                                 const struct intel_crtc_state *old_crtc_state,
3106                                 const struct drm_connector_state *old_conn_state)
3107 {
3108         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3109         uint32_t val;
3110
3111         /*
3112          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3113          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3114          * step 13 is the correct place for it. Step 18 is where it was
3115          * originally before the BUN.
3116          */
3117         val = I915_READ(FDI_RX_CTL(PIPE_A));
3118         val &= ~FDI_RX_ENABLE;
3119         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3120
3121         intel_disable_ddi_buf(encoder);
3122         intel_ddi_clk_disable(encoder);
3123
3124         val = I915_READ(FDI_RX_MISC(PIPE_A));
3125         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3126         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3127         I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3128
3129         val = I915_READ(FDI_RX_CTL(PIPE_A));
3130         val &= ~FDI_PCDCLK;
3131         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3132
3133         val = I915_READ(FDI_RX_CTL(PIPE_A));
3134         val &= ~FDI_RX_PLL_ENABLE;
3135         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3136 }
3137
3138 static void intel_enable_ddi_dp(struct intel_encoder *encoder,
3139                                 const struct intel_crtc_state *crtc_state,
3140                                 const struct drm_connector_state *conn_state)
3141 {
3142         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3143         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3144         enum port port = encoder->port;
3145
3146         if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3147                 intel_dp_stop_link_train(intel_dp);
3148
3149         intel_edp_backlight_on(crtc_state, conn_state);
3150         intel_psr_enable(intel_dp, crtc_state);
3151         intel_edp_drrs_enable(intel_dp, crtc_state);
3152
3153         if (crtc_state->has_audio)
3154                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3155 }
3156
3157 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
3158                                   const struct intel_crtc_state *crtc_state,
3159                                   const struct drm_connector_state *conn_state)
3160 {
3161         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3162         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3163         struct drm_connector *connector = conn_state->connector;
3164         enum port port = encoder->port;
3165
3166         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3167                                                crtc_state->hdmi_high_tmds_clock_ratio,
3168                                                crtc_state->hdmi_scrambling))
3169                 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3170                           connector->base.id, connector->name);
3171
3172         /* Display WA #1143: skl,kbl,cfl */
3173         if (IS_GEN9_BC(dev_priv)) {
3174                 /*
3175                  * For some reason these chicken bits have been
3176                  * stuffed into a transcoder register, event though
3177                  * the bits affect a specific DDI port rather than
3178                  * a specific transcoder.
3179                  */
3180                 static const enum transcoder port_to_transcoder[] = {
3181                         [PORT_A] = TRANSCODER_EDP,
3182                         [PORT_B] = TRANSCODER_A,
3183                         [PORT_C] = TRANSCODER_B,
3184                         [PORT_D] = TRANSCODER_C,
3185                         [PORT_E] = TRANSCODER_A,
3186                 };
3187                 enum transcoder transcoder = port_to_transcoder[port];
3188                 u32 val;
3189
3190                 val = I915_READ(CHICKEN_TRANS(transcoder));
3191
3192                 if (port == PORT_E)
3193                         val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3194                                 DDIE_TRAINING_OVERRIDE_VALUE;
3195                 else
3196                         val |= DDI_TRAINING_OVERRIDE_ENABLE |
3197                                 DDI_TRAINING_OVERRIDE_VALUE;
3198
3199                 I915_WRITE(CHICKEN_TRANS(transcoder), val);
3200                 POSTING_READ(CHICKEN_TRANS(transcoder));
3201
3202                 udelay(1);
3203
3204                 if (port == PORT_E)
3205                         val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3206                                  DDIE_TRAINING_OVERRIDE_VALUE);
3207                 else
3208                         val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3209                                  DDI_TRAINING_OVERRIDE_VALUE);
3210
3211                 I915_WRITE(CHICKEN_TRANS(transcoder), val);
3212         }
3213
3214         /* In HDMI/DVI mode, the port width, and swing/emphasis values
3215          * are ignored so nothing special needs to be done besides
3216          * enabling the port.
3217          */
3218         I915_WRITE(DDI_BUF_CTL(port),
3219                    dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
3220
3221         if (crtc_state->has_audio)
3222                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3223 }
3224
3225 static void intel_enable_ddi(struct intel_encoder *encoder,
3226                              const struct intel_crtc_state *crtc_state,
3227                              const struct drm_connector_state *conn_state)
3228 {
3229         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3230                 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
3231         else
3232                 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
3233
3234         /* Enable hdcp if it's desired */
3235         if (conn_state->content_protection ==
3236             DRM_MODE_CONTENT_PROTECTION_DESIRED)
3237                 intel_hdcp_enable(to_intel_connector(conn_state->connector));
3238 }
3239
3240 static void intel_disable_ddi_dp(struct intel_encoder *encoder,
3241                                  const struct intel_crtc_state *old_crtc_state,
3242                                  const struct drm_connector_state *old_conn_state)
3243 {
3244         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3245
3246         intel_dp->link_trained = false;
3247
3248         if (old_crtc_state->has_audio)
3249                 intel_audio_codec_disable(encoder,
3250                                           old_crtc_state, old_conn_state);
3251
3252         intel_edp_drrs_disable(intel_dp, old_crtc_state);
3253         intel_psr_disable(intel_dp, old_crtc_state);
3254         intel_edp_backlight_off(old_conn_state);
3255 }
3256
3257 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
3258                                    const struct intel_crtc_state *old_crtc_state,
3259                                    const struct drm_connector_state *old_conn_state)
3260 {
3261         struct drm_connector *connector = old_conn_state->connector;
3262
3263         if (old_crtc_state->has_audio)
3264                 intel_audio_codec_disable(encoder,
3265                                           old_crtc_state, old_conn_state);
3266
3267         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3268                                                false, false))
3269                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3270                               connector->base.id, connector->name);
3271 }
3272
3273 static void intel_disable_ddi(struct intel_encoder *encoder,
3274                               const struct intel_crtc_state *old_crtc_state,
3275                               const struct drm_connector_state *old_conn_state)
3276 {
3277         intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3278
3279         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3280                 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
3281         else
3282                 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
3283 }
3284
3285 static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
3286                                    const struct intel_crtc_state *pipe_config,
3287                                    const struct drm_connector_state *conn_state)
3288 {
3289         uint8_t mask = pipe_config->lane_lat_optim_mask;
3290
3291         bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
3292 }
3293
3294 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
3295 {
3296         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3297         struct drm_i915_private *dev_priv =
3298                 to_i915(intel_dig_port->base.base.dev);
3299         enum port port = intel_dig_port->base.port;
3300         uint32_t val;
3301         bool wait = false;
3302
3303         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
3304                 val = I915_READ(DDI_BUF_CTL(port));
3305                 if (val & DDI_BUF_CTL_ENABLE) {
3306                         val &= ~DDI_BUF_CTL_ENABLE;
3307                         I915_WRITE(DDI_BUF_CTL(port), val);
3308                         wait = true;
3309                 }
3310
3311                 val = I915_READ(DP_TP_CTL(port));
3312                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3313                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3314                 I915_WRITE(DP_TP_CTL(port), val);
3315                 POSTING_READ(DP_TP_CTL(port));
3316
3317                 if (wait)
3318                         intel_wait_ddi_buf_idle(dev_priv, port);
3319         }
3320
3321         val = DP_TP_CTL_ENABLE |
3322               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
3323         if (intel_dp->link_mst)
3324                 val |= DP_TP_CTL_MODE_MST;
3325         else {
3326                 val |= DP_TP_CTL_MODE_SST;
3327                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3328                         val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3329         }
3330         I915_WRITE(DP_TP_CTL(port), val);
3331         POSTING_READ(DP_TP_CTL(port));
3332
3333         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3334         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3335         POSTING_READ(DDI_BUF_CTL(port));
3336
3337         udelay(600);
3338 }
3339
3340 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3341                                        enum transcoder cpu_transcoder)
3342 {
3343         if (cpu_transcoder == TRANSCODER_EDP)
3344                 return false;
3345
3346         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
3347                 return false;
3348
3349         return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
3350                 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3351 }
3352
3353 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3354                                          struct intel_crtc_state *crtc_state)
3355 {
3356         if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
3357                 crtc_state->min_voltage_level = 2;
3358         else if (IS_ICELAKE(dev_priv) && crtc_state->port_clock > 594000)
3359                 crtc_state->min_voltage_level = 1;
3360 }
3361
3362 void intel_ddi_get_config(struct intel_encoder *encoder,
3363                           struct intel_crtc_state *pipe_config)
3364 {
3365         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3366         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
3367         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3368         struct intel_digital_port *intel_dig_port;
3369         u32 temp, flags = 0;
3370
3371         /* XXX: DSI transcoder paranoia */
3372         if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
3373                 return;
3374
3375         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3376         if (temp & TRANS_DDI_PHSYNC)
3377                 flags |= DRM_MODE_FLAG_PHSYNC;
3378         else
3379                 flags |= DRM_MODE_FLAG_NHSYNC;
3380         if (temp & TRANS_DDI_PVSYNC)
3381                 flags |= DRM_MODE_FLAG_PVSYNC;
3382         else
3383                 flags |= DRM_MODE_FLAG_NVSYNC;
3384
3385         pipe_config->base.adjusted_mode.flags |= flags;
3386
3387         switch (temp & TRANS_DDI_BPC_MASK) {
3388         case TRANS_DDI_BPC_6:
3389                 pipe_config->pipe_bpp = 18;
3390                 break;
3391         case TRANS_DDI_BPC_8:
3392                 pipe_config->pipe_bpp = 24;
3393                 break;
3394         case TRANS_DDI_BPC_10:
3395                 pipe_config->pipe_bpp = 30;
3396                 break;
3397         case TRANS_DDI_BPC_12:
3398                 pipe_config->pipe_bpp = 36;
3399                 break;
3400         default:
3401                 break;
3402         }
3403
3404         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3405         case TRANS_DDI_MODE_SELECT_HDMI:
3406                 pipe_config->has_hdmi_sink = true;
3407                 intel_dig_port = enc_to_dig_port(&encoder->base);
3408
3409                 if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config))
3410                         pipe_config->has_infoframe = true;
3411
3412                 if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
3413                         TRANS_DDI_HDMI_SCRAMBLING_MASK)
3414                         pipe_config->hdmi_scrambling = true;
3415                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3416                         pipe_config->hdmi_high_tmds_clock_ratio = true;
3417                 /* fall through */
3418         case TRANS_DDI_MODE_SELECT_DVI:
3419                 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
3420                 pipe_config->lane_count = 4;
3421                 break;
3422         case TRANS_DDI_MODE_SELECT_FDI:
3423                 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
3424                 break;
3425         case TRANS_DDI_MODE_SELECT_DP_SST:
3426                 if (encoder->type == INTEL_OUTPUT_EDP)
3427                         pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3428                 else
3429                         pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3430                 pipe_config->lane_count =
3431                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3432                 intel_dp_get_m_n(intel_crtc, pipe_config);
3433                 break;
3434         case TRANS_DDI_MODE_SELECT_DP_MST:
3435                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
3436                 pipe_config->lane_count =
3437                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3438                 intel_dp_get_m_n(intel_crtc, pipe_config);
3439                 break;
3440         default:
3441                 break;
3442         }
3443
3444         pipe_config->has_audio =
3445                 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
3446
3447         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
3448             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3449                 /*
3450                  * This is a big fat ugly hack.
3451                  *
3452                  * Some machines in UEFI boot mode provide us a VBT that has 18
3453                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3454                  * unknown we fail to light up. Yet the same BIOS boots up with
3455                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3456                  * max, not what it tells us to use.
3457                  *
3458                  * Note: This will still be broken if the eDP panel is not lit
3459                  * up by the BIOS, and thus we can't get the mode at module
3460                  * load.
3461                  */
3462                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3463                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3464                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3465         }
3466
3467         intel_ddi_clock_get(encoder, pipe_config);
3468
3469         if (IS_GEN9_LP(dev_priv))
3470                 pipe_config->lane_lat_optim_mask =
3471                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
3472
3473         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3474 }
3475
3476 static enum intel_output_type
3477 intel_ddi_compute_output_type(struct intel_encoder *encoder,
3478                               struct intel_crtc_state *crtc_state,
3479                               struct drm_connector_state *conn_state)
3480 {
3481         switch (conn_state->connector->connector_type) {
3482         case DRM_MODE_CONNECTOR_HDMIA:
3483                 return INTEL_OUTPUT_HDMI;
3484         case DRM_MODE_CONNECTOR_eDP:
3485                 return INTEL_OUTPUT_EDP;
3486         case DRM_MODE_CONNECTOR_DisplayPort:
3487                 return INTEL_OUTPUT_DP;
3488         default:
3489                 MISSING_CASE(conn_state->connector->connector_type);
3490                 return INTEL_OUTPUT_UNUSED;
3491         }
3492 }
3493
3494 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
3495                                      struct intel_crtc_state *pipe_config,
3496                                      struct drm_connector_state *conn_state)
3497 {
3498         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3499         enum port port = encoder->port;
3500         int ret;
3501
3502         if (port == PORT_A)
3503                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3504
3505         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
3506                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
3507         else
3508                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
3509
3510         if (IS_GEN9_LP(dev_priv) && ret)
3511                 pipe_config->lane_lat_optim_mask =
3512                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
3513
3514         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3515
3516         return ret;
3517
3518 }
3519
3520 static const struct drm_encoder_funcs intel_ddi_funcs = {
3521         .reset = intel_dp_encoder_reset,
3522         .destroy = intel_dp_encoder_destroy,
3523 };
3524
3525 static struct intel_connector *
3526 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3527 {
3528         struct intel_connector *connector;
3529         enum port port = intel_dig_port->base.port;
3530
3531         connector = intel_connector_alloc();
3532         if (!connector)
3533                 return NULL;
3534
3535         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3536         if (!intel_dp_init_connector(intel_dig_port, connector)) {
3537                 kfree(connector);
3538                 return NULL;
3539         }
3540
3541         return connector;
3542 }
3543
3544 static int modeset_pipe(struct drm_crtc *crtc,
3545                         struct drm_modeset_acquire_ctx *ctx)
3546 {
3547         struct drm_atomic_state *state;
3548         struct drm_crtc_state *crtc_state;
3549         int ret;
3550
3551         state = drm_atomic_state_alloc(crtc->dev);
3552         if (!state)
3553                 return -ENOMEM;
3554
3555         state->acquire_ctx = ctx;
3556
3557         crtc_state = drm_atomic_get_crtc_state(state, crtc);
3558         if (IS_ERR(crtc_state)) {
3559                 ret = PTR_ERR(crtc_state);
3560                 goto out;
3561         }
3562
3563         crtc_state->mode_changed = true;
3564
3565         ret = drm_atomic_add_affected_connectors(state, crtc);
3566         if (ret)
3567                 goto out;
3568
3569         ret = drm_atomic_add_affected_planes(state, crtc);
3570         if (ret)
3571                 goto out;
3572
3573         ret = drm_atomic_commit(state);
3574         if (ret)
3575                 goto out;
3576
3577         return 0;
3578
3579  out:
3580         drm_atomic_state_put(state);
3581
3582         return ret;
3583 }
3584
3585 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
3586                                  struct drm_modeset_acquire_ctx *ctx)
3587 {
3588         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3589         struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base);
3590         struct intel_connector *connector = hdmi->attached_connector;
3591         struct i2c_adapter *adapter =
3592                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
3593         struct drm_connector_state *conn_state;
3594         struct intel_crtc_state *crtc_state;
3595         struct intel_crtc *crtc;
3596         u8 config;
3597         int ret;
3598
3599         if (!connector || connector->base.status != connector_status_connected)
3600                 return 0;
3601
3602         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3603                                ctx);
3604         if (ret)
3605                 return ret;
3606
3607         conn_state = connector->base.state;
3608
3609         crtc = to_intel_crtc(conn_state->crtc);
3610         if (!crtc)
3611                 return 0;
3612
3613         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
3614         if (ret)
3615                 return ret;
3616
3617         crtc_state = to_intel_crtc_state(crtc->base.state);
3618
3619         WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
3620
3621         if (!crtc_state->base.active)
3622                 return 0;
3623
3624         if (!crtc_state->hdmi_high_tmds_clock_ratio &&
3625             !crtc_state->hdmi_scrambling)
3626                 return 0;
3627
3628         if (conn_state->commit &&
3629             !try_wait_for_completion(&conn_state->commit->hw_done))
3630                 return 0;
3631
3632         ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
3633         if (ret < 0) {
3634                 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
3635                 return 0;
3636         }
3637
3638         if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
3639             crtc_state->hdmi_high_tmds_clock_ratio &&
3640             !!(config & SCDC_SCRAMBLING_ENABLE) ==
3641             crtc_state->hdmi_scrambling)
3642                 return 0;
3643
3644         /*
3645          * HDMI 2.0 says that one should not send scrambled data
3646          * prior to configuring the sink scrambling, and that
3647          * TMDS clock/data transmission should be suspended when
3648          * changing the TMDS clock rate in the sink. So let's
3649          * just do a full modeset here, even though some sinks
3650          * would be perfectly happy if were to just reconfigure
3651          * the SCDC settings on the fly.
3652          */
3653         return modeset_pipe(&crtc->base, ctx);
3654 }
3655
3656 static bool intel_ddi_hotplug(struct intel_encoder *encoder,
3657                               struct intel_connector *connector)
3658 {
3659         struct drm_modeset_acquire_ctx ctx;
3660         bool changed;
3661         int ret;
3662
3663         changed = intel_encoder_hotplug(encoder, connector);
3664
3665         drm_modeset_acquire_init(&ctx, 0);
3666
3667         for (;;) {
3668                 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
3669                         ret = intel_hdmi_reset_link(encoder, &ctx);
3670                 else
3671                         ret = intel_dp_retrain_link(encoder, &ctx);
3672
3673                 if (ret == -EDEADLK) {
3674                         drm_modeset_backoff(&ctx);
3675                         continue;
3676                 }
3677
3678                 break;
3679         }
3680
3681         drm_modeset_drop_locks(&ctx);
3682         drm_modeset_acquire_fini(&ctx);
3683         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
3684
3685         return changed;
3686 }
3687
3688 static struct intel_connector *
3689 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
3690 {
3691         struct intel_connector *connector;
3692         enum port port = intel_dig_port->base.port;
3693
3694         connector = intel_connector_alloc();
3695         if (!connector)
3696                 return NULL;
3697
3698         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
3699         intel_hdmi_init_connector(intel_dig_port, connector);
3700
3701         return connector;
3702 }
3703
3704 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
3705 {
3706         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
3707
3708         if (dport->base.port != PORT_A)
3709                 return false;
3710
3711         if (dport->saved_port_bits & DDI_A_4_LANES)
3712                 return false;
3713
3714         /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
3715          *                     supported configuration
3716          */
3717         if (IS_GEN9_LP(dev_priv))
3718                 return true;
3719
3720         /* Cannonlake: Most of SKUs don't support DDI_E, and the only
3721          *             one who does also have a full A/E split called
3722          *             DDI_F what makes DDI_E useless. However for this
3723          *             case let's trust VBT info.
3724          */
3725         if (IS_CANNONLAKE(dev_priv) &&
3726             !intel_bios_is_port_present(dev_priv, PORT_E))
3727                 return true;
3728
3729         return false;
3730 }
3731
3732 static int
3733 intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
3734 {
3735         struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
3736         enum port port = intel_dport->base.port;
3737         int max_lanes = 4;
3738
3739         if (INTEL_GEN(dev_priv) >= 11)
3740                 return max_lanes;
3741
3742         if (port == PORT_A || port == PORT_E) {
3743                 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
3744                         max_lanes = port == PORT_A ? 4 : 0;
3745                 else
3746                         /* Both A and E share 2 lanes */
3747                         max_lanes = 2;
3748         }
3749
3750         /*
3751          * Some BIOS might fail to set this bit on port A if eDP
3752          * wasn't lit up at boot.  Force this bit set when needed
3753          * so we use the proper lane count for our calculations.
3754          */
3755         if (intel_ddi_a_force_4_lanes(intel_dport)) {
3756                 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
3757                 intel_dport->saved_port_bits |= DDI_A_4_LANES;
3758                 max_lanes = 4;
3759         }
3760
3761         return max_lanes;
3762 }
3763
3764 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
3765 {
3766         struct intel_digital_port *intel_dig_port;
3767         struct intel_encoder *intel_encoder;
3768         struct drm_encoder *encoder;
3769         bool init_hdmi, init_dp, init_lspcon = false;
3770
3771
3772         init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
3773                      dev_priv->vbt.ddi_port_info[port].supports_hdmi);
3774         init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
3775
3776         if (intel_bios_is_lspcon_present(dev_priv, port)) {
3777                 /*
3778                  * Lspcon device needs to be driven with DP connector
3779                  * with special detection sequence. So make sure DP
3780                  * is initialized before lspcon.
3781                  */
3782                 init_dp = true;
3783                 init_lspcon = true;
3784                 init_hdmi = false;
3785                 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
3786         }
3787
3788         if (!init_dp && !init_hdmi) {
3789                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
3790                               port_name(port));
3791                 return;
3792         }
3793
3794         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3795         if (!intel_dig_port)
3796                 return;
3797
3798         intel_encoder = &intel_dig_port->base;
3799         encoder = &intel_encoder->base;
3800
3801         drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
3802                          DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
3803
3804         intel_encoder->hotplug = intel_ddi_hotplug;
3805         intel_encoder->compute_output_type = intel_ddi_compute_output_type;
3806         intel_encoder->compute_config = intel_ddi_compute_config;
3807         intel_encoder->enable = intel_enable_ddi;
3808         if (IS_GEN9_LP(dev_priv))
3809                 intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
3810         intel_encoder->pre_enable = intel_ddi_pre_enable;
3811         intel_encoder->disable = intel_disable_ddi;
3812         intel_encoder->post_disable = intel_ddi_post_disable;
3813         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
3814         intel_encoder->get_config = intel_ddi_get_config;
3815         intel_encoder->suspend = intel_dp_encoder_suspend;
3816         intel_encoder->get_power_domains = intel_ddi_get_power_domains;
3817         intel_encoder->type = INTEL_OUTPUT_DDI;
3818         intel_encoder->power_domain = intel_port_to_power_domain(port);
3819         intel_encoder->port = port;
3820         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3821         intel_encoder->cloneable = 0;
3822
3823         if (INTEL_GEN(dev_priv) >= 11)
3824                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3825                         DDI_BUF_PORT_REVERSAL;
3826         else
3827                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3828                         (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
3829         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
3830         intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
3831
3832         switch (port) {
3833         case PORT_A:
3834                 intel_dig_port->ddi_io_power_domain =
3835                         POWER_DOMAIN_PORT_DDI_A_IO;
3836                 break;
3837         case PORT_B:
3838                 intel_dig_port->ddi_io_power_domain =
3839                         POWER_DOMAIN_PORT_DDI_B_IO;
3840                 break;
3841         case PORT_C:
3842                 intel_dig_port->ddi_io_power_domain =
3843                         POWER_DOMAIN_PORT_DDI_C_IO;
3844                 break;
3845         case PORT_D:
3846                 intel_dig_port->ddi_io_power_domain =
3847                         POWER_DOMAIN_PORT_DDI_D_IO;
3848                 break;
3849         case PORT_E:
3850                 intel_dig_port->ddi_io_power_domain =
3851                         POWER_DOMAIN_PORT_DDI_E_IO;
3852                 break;
3853         case PORT_F:
3854                 intel_dig_port->ddi_io_power_domain =
3855                         POWER_DOMAIN_PORT_DDI_F_IO;
3856                 break;
3857         default:
3858                 MISSING_CASE(port);
3859         }
3860
3861         intel_infoframe_init(intel_dig_port);
3862
3863         if (init_dp) {
3864                 if (!intel_ddi_init_dp_connector(intel_dig_port))
3865                         goto err;
3866
3867                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
3868         }
3869
3870         /* In theory we don't need the encoder->type check, but leave it just in
3871          * case we have some really bad VBTs... */
3872         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
3873                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
3874                         goto err;
3875         }
3876
3877         if (init_lspcon) {
3878                 if (lspcon_init(intel_dig_port))
3879                         /* TODO: handle hdmi info frame part */
3880                         DRM_DEBUG_KMS("LSPCON init success on port %c\n",
3881                                 port_name(port));
3882                 else
3883                         /*
3884                          * LSPCON init faied, but DP init was success, so
3885                          * lets try to drive as DP++ port.
3886                          */
3887                         DRM_ERROR("LSPCON init failed on port %c\n",
3888                                 port_name(port));
3889         }
3890
3891         return;
3892
3893 err:
3894         drm_encoder_cleanup(encoder);
3895         kfree(intel_dig_port);
3896 }