drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <drm/drmP.h>
  24 #include "amdgpu.h"
  25 #include "amdgpu_pm.h"
  26 #include "amdgpu_i2c.h"
  27 #include "atom.h"
  28 #include "amdgpu_atombios.h"
  29 #include "atombios_crtc.h"
  30 #include "atombios_encoders.h"
  31 #include "amdgpu_pll.h"
  32 #include "amdgpu_connectors.h"
  33
  34 #include "bif/bif_3_0_d.h"
  35 #include "bif/bif_3_0_sh_mask.h"
  36 #include "oss/oss_1_0_d.h"
  37 #include "oss/oss_1_0_sh_mask.h"
  38 #include "gca/gfx_6_0_d.h"
  39 #include "gca/gfx_6_0_sh_mask.h"
  40 #include "gmc/gmc_6_0_d.h"
  41 #include "gmc/gmc_6_0_sh_mask.h"
  42 #include "dce/dce_6_0_d.h"
  43 #include "dce/dce_6_0_sh_mask.h"
  44 #include "gca/gfx_7_2_enum.h"
  45 #include "dce_v6_0.h"
  46 #include "si_enums.h"
  47
  48 static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev);
  49 static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev);
  50
  51 static const u32 crtc_offsets[6] =
  52 {
  53         SI_CRTC0_REGISTER_OFFSET,
  54         SI_CRTC1_REGISTER_OFFSET,
  55         SI_CRTC2_REGISTER_OFFSET,
  56         SI_CRTC3_REGISTER_OFFSET,
  57         SI_CRTC4_REGISTER_OFFSET,
  58         SI_CRTC5_REGISTER_OFFSET
  59 };
  60
  61 static const u32 hpd_offsets[] =
  62 {
  63         mmDC_HPD1_INT_STATUS - mmDC_HPD1_INT_STATUS,
  64         mmDC_HPD2_INT_STATUS - mmDC_HPD1_INT_STATUS,
  65         mmDC_HPD3_INT_STATUS - mmDC_HPD1_INT_STATUS,
  66         mmDC_HPD4_INT_STATUS - mmDC_HPD1_INT_STATUS,
  67         mmDC_HPD5_INT_STATUS - mmDC_HPD1_INT_STATUS,
  68         mmDC_HPD6_INT_STATUS - mmDC_HPD1_INT_STATUS,
  69 };
  70
  71 static const uint32_t dig_offsets[] = {
  72         SI_CRTC0_REGISTER_OFFSET,
  73         SI_CRTC1_REGISTER_OFFSET,
  74         SI_CRTC2_REGISTER_OFFSET,
  75         SI_CRTC3_REGISTER_OFFSET,
  76         SI_CRTC4_REGISTER_OFFSET,
  77         SI_CRTC5_REGISTER_OFFSET,
  78         (0x13830 - 0x7030) >> 2,
  79 };
  80
  81 static const struct {
  82         uint32_t        reg;
  83         uint32_t        vblank;
  84         uint32_t        vline;
  85         uint32_t        hpd;
  86
  87 } interrupt_status_offsets[6] = { {
  88         .reg = mmDISP_INTERRUPT_STATUS,
  89         .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
  90         .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
  91         .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
  92 }, {
  93         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
  94         .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
  95         .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
  96         .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
  97 }, {
  98         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
  99         .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
 100         .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
 101         .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
 102 }, {
 103         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
 104         .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
 105         .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
 106         .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
 107 }, {
 108         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
 109         .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
 110         .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
 111         .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
 112 }, {
 113         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
 114         .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
 115         .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
 116         .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
 117 } };
 118
 119 static u32 dce_v6_0_audio_endpt_rreg(struct amdgpu_device *adev,
 120                                      u32 block_offset, u32 reg)
 121 {
 122         unsigned long flags;
 123         u32 r;
 124
 125         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 126         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 127         r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
 128         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 129
 130         return r;
 131 }
 132
 133 static void dce_v6_0_audio_endpt_wreg(struct amdgpu_device *adev,
 134                                       u32 block_offset, u32 reg, u32 v)
 135 {
 136         unsigned long flags;
 137
 138         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 139         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset,
 140                 reg | AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_WRITE_EN_MASK);
 141         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
 142         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 143 }
 144
 145 static u32 dce_v6_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 146 {
 147         if (crtc >= adev->mode_info.num_crtc)
 148                 return 0;
 149         else
 150                 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
 151 }
 152
 153 static void dce_v6_0_pageflip_interrupt_init(struct amdgpu_device *adev)
 154 {
 155         unsigned i;
 156
 157         /* Enable pflip interrupts */
 158         for (i = 0; i < adev->mode_info.num_crtc; i++)
 159                 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
 160 }
 161
 162 static void dce_v6_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
 163 {
 164         unsigned i;
 165
 166         /* Disable pflip interrupts */
 167         for (i = 0; i < adev->mode_info.num_crtc; i++)
 168                 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
 169 }
 170
 171 /**
 172  * dce_v6_0_page_flip - pageflip callback.
 173  *
 174  * @adev: amdgpu_device pointer
 175  * @crtc_id: crtc to cleanup pageflip on
 176  * @crtc_base: new address of the crtc (GPU MC address)
 177  *
 178  * Does the actual pageflip (evergreen+).
 179  * During vblank we take the crtc lock and wait for the update_pending
 180  * bit to go high, when it does, we release the lock, and allow the
 181  * double buffered update to take place.
 182  * Returns the current update pending status.
 183  */
 184 static void dce_v6_0_page_flip(struct amdgpu_device *adev,
 185                                int crtc_id, u64 crtc_base, bool async)
 186 {
 187         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 188
 189         /* flip at hsync for async, default is vsync */
 190         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
 191                GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
 192         /* update the scanout addresses */
 193         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
 194                upper_32_bits(crtc_base));
 195         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
 196                (u32)crtc_base);
 197
 198         /* post the write */
 199         RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
 200 }
 201
 202 static int dce_v6_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 203                                         u32 *vbl, u32 *position)
 204 {
 205         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 206                 return -EINVAL;
 207         *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
 208         *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 209
 210         return 0;
 211
 212 }
 213
 214 /**
 215  * dce_v6_0_hpd_sense - hpd sense callback.
 216  *
 217  * @adev: amdgpu_device pointer
 218  * @hpd: hpd (hotplug detect) pin
 219  *
 220  * Checks if a digital monitor is connected (evergreen+).
 221  * Returns true if connected, false if not connected.
 222  */
 223 static bool dce_v6_0_hpd_sense(struct amdgpu_device *adev,
 224                                enum amdgpu_hpd_id hpd)
 225 {
 226         bool connected = false;
 227
 228         if (hpd >= adev->mode_info.num_hpd)
 229                 return connected;
 230
 231         if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)
 232                 connected = true;
 233
 234         return connected;
 235 }
 236
 237 /**
 238  * dce_v6_0_hpd_set_polarity - hpd set polarity callback.
 239  *
 240  * @adev: amdgpu_device pointer
 241  * @hpd: hpd (hotplug detect) pin
 242  *
 243  * Set the polarity of the hpd pin (evergreen+).
 244  */
 245 static void dce_v6_0_hpd_set_polarity(struct amdgpu_device *adev,
 246                                       enum amdgpu_hpd_id hpd)
 247 {
 248         u32 tmp;
 249         bool connected = dce_v6_0_hpd_sense(adev, hpd);
 250
 251         if (hpd >= adev->mode_info.num_hpd)
 252                 return;
 253
 254         tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
 255         if (connected)
 256                 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
 257         else
 258                 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
 259         WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
 260 }
 261
 262 /**
 263  * dce_v6_0_hpd_init - hpd setup callback.
 264  *
 265  * @adev: amdgpu_device pointer
 266  *
 267  * Setup the hpd pins used by the card (evergreen+).
 268  * Enable the pin, set the polarity, and enable the hpd interrupts.
 269  */
 270 static void dce_v6_0_hpd_init(struct amdgpu_device *adev)
 271 {
 272         struct drm_device *dev = adev->ddev;
 273         struct drm_connector *connector;
 274         u32 tmp;
 275
 276         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 277                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 278
 279                 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
 280                         continue;
 281
 282                 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 283                 tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
 284                 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 285
 286                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 287                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 288                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 289                          * aux dp channel on imac and help (but not completely fix)
 290                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 291                          * also avoid interrupt storms during dpms.
 292                          */
 293                         tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 294                         tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
 295                         WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 296                         continue;
 297                 }
 298
 299                 dce_v6_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
 300                 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 301         }
 302
 303 }
 304
 305 /**
 306  * dce_v6_0_hpd_fini - hpd tear down callback.
 307  *
 308  * @adev: amdgpu_device pointer
 309  *
 310  * Tear down the hpd pins used by the card (evergreen+).
 311  * Disable the hpd interrupts.
 312  */
 313 static void dce_v6_0_hpd_fini(struct amdgpu_device *adev)
 314 {
 315         struct drm_device *dev = adev->ddev;
 316         struct drm_connector *connector;
 317         u32 tmp;
 318
 319         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 320                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 321
 322                 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
 323                         continue;
 324
 325                 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 326                 tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
 327                 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0);
 328
 329                 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 330         }
 331 }
 332
 333 static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
 334 {
 335         return mmDC_GPIO_HPD_A;
 336 }
 337
 338 static void dce_v6_0_set_vga_render_state(struct amdgpu_device *adev,
 339                                           bool render)
 340 {
 341         if (!render)
 342                 WREG32(mmVGA_RENDER_CONTROL,
 343                         RREG32(mmVGA_RENDER_CONTROL) & VGA_VSTATUS_CNTL);
 344
 345 }
 346
 347 static int dce_v6_0_get_num_crtc(struct amdgpu_device *adev)
 348 {
 349         switch (adev->asic_type) {
 350         case CHIP_TAHITI:
 351         case CHIP_PITCAIRN:
 352         case CHIP_VERDE:
 353                 return 6;
 354         case CHIP_OLAND:
 355                 return 2;
 356         default:
 357                 return 0;
 358         }
 359 }
 360
 361 void dce_v6_0_disable_dce(struct amdgpu_device *adev)
 362 {
 363         /*Disable VGA render and enabled crtc, if has DCE engine*/
 364         if (amdgpu_atombios_has_dce_engine_info(adev)) {
 365                 u32 tmp;
 366                 int crtc_enabled, i;
 367
 368                 dce_v6_0_set_vga_render_state(adev, false);
 369
 370                 /*Disable crtc*/
 371                 for (i = 0; i < dce_v6_0_get_num_crtc(adev); i++) {
 372                         crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) &
 373                                 CRTC_CONTROL__CRTC_MASTER_EN_MASK;
 374                         if (crtc_enabled) {
 375                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 376                                 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 377                                 tmp &= ~CRTC_CONTROL__CRTC_MASTER_EN_MASK;
 378                                 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
 379                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 380                         }
 381                 }
 382         }
 383 }
 384
 385 static void dce_v6_0_program_fmt(struct drm_encoder *encoder)
 386 {
 387
 388         struct drm_device *dev = encoder->dev;
 389         struct amdgpu_device *adev = dev->dev_private;
 390         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 391         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
 392         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
 393         int bpc = 0;
 394         u32 tmp = 0;
 395         enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
 396
 397         if (connector) {
 398                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 399                 bpc = amdgpu_connector_get_monitor_bpc(connector);
 400                 dither = amdgpu_connector->dither;
 401         }
 402
 403         /* LVDS FMT is set up by atom */
 404         if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 405                 return;
 406
 407         if (bpc == 0)
 408                 return;
 409
 410
 411         switch (bpc) {
 412         case 6:
 413                 if (dither == AMDGPU_FMT_DITHER_ENABLE)
 414                         /* XXX sort out optimal dither settings */
 415                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
 416                                 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
 417                                 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK);
 418                 else
 419                         tmp |= FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK;
 420                 break;
 421         case 8:
 422                 if (dither == AMDGPU_FMT_DITHER_ENABLE)
 423                         /* XXX sort out optimal dither settings */
 424                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
 425                                 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
 426                                 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
 427                                 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
 428                                 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK);
 429                 else
 430                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
 431                                 FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK);
 432                 break;
 433         case 10:
 434         default:
 435                 /* not needed */
 436                 break;
 437         }
 438
 439         WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 440 }
 441
 442 /**
 443  * cik_get_number_of_dram_channels - get the number of dram channels
 444  *
 445  * @adev: amdgpu_device pointer
 446  *
 447  * Look up the number of video ram channels (CIK).
 448  * Used for display watermark bandwidth calculations
 449  * Returns the number of dram channels
 450  */
 451 static u32 si_get_number_of_dram_channels(struct amdgpu_device *adev)
 452 {
 453         u32 tmp = RREG32(mmMC_SHARED_CHMAP);
 454
 455         switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
 456         case 0:
 457         default:
 458                 return 1;
 459         case 1:
 460                 return 2;
 461         case 2:
 462                 return 4;
 463         case 3:
 464                 return 8;
 465         case 4:
 466                 return 3;
 467         case 5:
 468                 return 6;
 469         case 6:
 470                 return 10;
 471         case 7:
 472                 return 12;
 473         case 8:
 474                 return 16;
 475         }
 476 }
 477
 478 struct dce6_wm_params {
 479         u32 dram_channels; /* number of dram channels */
 480         u32 yclk;          /* bandwidth per dram data pin in kHz */
 481         u32 sclk;          /* engine clock in kHz */
 482         u32 disp_clk;      /* display clock in kHz */
 483         u32 src_width;     /* viewport width */
 484         u32 active_time;   /* active display time in ns */
 485         u32 blank_time;    /* blank time in ns */
 486         bool interlaced;    /* mode is interlaced */
 487         fixed20_12 vsc;    /* vertical scale ratio */
 488         u32 num_heads;     /* number of active crtcs */
 489         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 490         u32 lb_size;       /* line buffer allocated to pipe */
 491         u32 vtaps;         /* vertical scaler taps */
 492 };
 493
 494 /**
 495  * dce_v6_0_dram_bandwidth - get the dram bandwidth
 496  *
 497  * @wm: watermark calculation data
 498  *
 499  * Calculate the raw dram bandwidth (CIK).
 500  * Used for display watermark bandwidth calculations
 501  * Returns the dram bandwidth in MBytes/s
 502  */
 503 static u32 dce_v6_0_dram_bandwidth(struct dce6_wm_params *wm)
 504 {
 505         /* Calculate raw DRAM Bandwidth */
 506         fixed20_12 dram_efficiency; /* 0.7 */
 507         fixed20_12 yclk, dram_channels, bandwidth;
 508         fixed20_12 a;
 509
 510         a.full = dfixed_const(1000);
 511         yclk.full = dfixed_const(wm->yclk);
 512         yclk.full = dfixed_div(yclk, a);
 513         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 514         a.full = dfixed_const(10);
 515         dram_efficiency.full = dfixed_const(7);
 516         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 517         bandwidth.full = dfixed_mul(dram_channels, yclk);
 518         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 519
 520         return dfixed_trunc(bandwidth);
 521 }
 522
 523 /**
 524  * dce_v6_0_dram_bandwidth_for_display - get the dram bandwidth for display
 525  *
 526  * @wm: watermark calculation data
 527  *
 528  * Calculate the dram bandwidth used for display (CIK).
 529  * Used for display watermark bandwidth calculations
 530  * Returns the dram bandwidth for display in MBytes/s
 531  */
 532 static u32 dce_v6_0_dram_bandwidth_for_display(struct dce6_wm_params *wm)
 533 {
 534         /* Calculate DRAM Bandwidth and the part allocated to display. */
 535         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 536         fixed20_12 yclk, dram_channels, bandwidth;
 537         fixed20_12 a;
 538
 539         a.full = dfixed_const(1000);
 540         yclk.full = dfixed_const(wm->yclk);
 541         yclk.full = dfixed_div(yclk, a);
 542         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 543         a.full = dfixed_const(10);
 544         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 545         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 546         bandwidth.full = dfixed_mul(dram_channels, yclk);
 547         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 548
 549         return dfixed_trunc(bandwidth);
 550 }
 551
 552 /**
 553  * dce_v6_0_data_return_bandwidth - get the data return bandwidth
 554  *
 555  * @wm: watermark calculation data
 556  *
 557  * Calculate the data return bandwidth used for display (CIK).
 558  * Used for display watermark bandwidth calculations
 559  * Returns the data return bandwidth in MBytes/s
 560  */
 561 static u32 dce_v6_0_data_return_bandwidth(struct dce6_wm_params *wm)
 562 {
 563         /* Calculate the display Data return Bandwidth */
 564         fixed20_12 return_efficiency; /* 0.8 */
 565         fixed20_12 sclk, bandwidth;
 566         fixed20_12 a;
 567
 568         a.full = dfixed_const(1000);
 569         sclk.full = dfixed_const(wm->sclk);
 570         sclk.full = dfixed_div(sclk, a);
 571         a.full = dfixed_const(10);
 572         return_efficiency.full = dfixed_const(8);
 573         return_efficiency.full = dfixed_div(return_efficiency, a);
 574         a.full = dfixed_const(32);
 575         bandwidth.full = dfixed_mul(a, sclk);
 576         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 577
 578         return dfixed_trunc(bandwidth);
 579 }
 580
 581 /**
 582  * dce_v6_0_dmif_request_bandwidth - get the dmif bandwidth
 583  *
 584  * @wm: watermark calculation data
 585  *
 586  * Calculate the dmif bandwidth used for display (CIK).
 587  * Used for display watermark bandwidth calculations
 588  * Returns the dmif bandwidth in MBytes/s
 589  */
 590 static u32 dce_v6_0_dmif_request_bandwidth(struct dce6_wm_params *wm)
 591 {
 592         /* Calculate the DMIF Request Bandwidth */
 593         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 594         fixed20_12 disp_clk, bandwidth;
 595         fixed20_12 a, b;
 596
 597         a.full = dfixed_const(1000);
 598         disp_clk.full = dfixed_const(wm->disp_clk);
 599         disp_clk.full = dfixed_div(disp_clk, a);
 600         a.full = dfixed_const(32);
 601         b.full = dfixed_mul(a, disp_clk);
 602
 603         a.full = dfixed_const(10);
 604         disp_clk_request_efficiency.full = dfixed_const(8);
 605         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
 606
 607         bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
 608
 609         return dfixed_trunc(bandwidth);
 610 }
 611
 612 /**
 613  * dce_v6_0_available_bandwidth - get the min available bandwidth
 614  *
 615  * @wm: watermark calculation data
 616  *
 617  * Calculate the min available bandwidth used for display (CIK).
 618  * Used for display watermark bandwidth calculations
 619  * Returns the min available bandwidth in MBytes/s
 620  */
 621 static u32 dce_v6_0_available_bandwidth(struct dce6_wm_params *wm)
 622 {
 623         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
 624         u32 dram_bandwidth = dce_v6_0_dram_bandwidth(wm);
 625         u32 data_return_bandwidth = dce_v6_0_data_return_bandwidth(wm);
 626         u32 dmif_req_bandwidth = dce_v6_0_dmif_request_bandwidth(wm);
 627
 628         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
 629 }
 630
 631 /**
 632  * dce_v6_0_average_bandwidth - get the average available bandwidth
 633  *
 634  * @wm: watermark calculation data
 635  *
 636  * Calculate the average available bandwidth used for display (CIK).
 637  * Used for display watermark bandwidth calculations
 638  * Returns the average available bandwidth in MBytes/s
 639  */
 640 static u32 dce_v6_0_average_bandwidth(struct dce6_wm_params *wm)
 641 {
 642         /* Calculate the display mode Average Bandwidth
 643          * DisplayMode should contain the source and destination dimensions,
 644          * timing, etc.
 645          */
 646         fixed20_12 bpp;
 647         fixed20_12 line_time;
 648         fixed20_12 src_width;
 649         fixed20_12 bandwidth;
 650         fixed20_12 a;
 651
 652         a.full = dfixed_const(1000);
 653         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
 654         line_time.full = dfixed_div(line_time, a);
 655         bpp.full = dfixed_const(wm->bytes_per_pixel);
 656         src_width.full = dfixed_const(wm->src_width);
 657         bandwidth.full = dfixed_mul(src_width, bpp);
 658         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
 659         bandwidth.full = dfixed_div(bandwidth, line_time);
 660
 661         return dfixed_trunc(bandwidth);
 662 }
 663
 664 /**
 665  * dce_v6_0_latency_watermark - get the latency watermark
 666  *
 667  * @wm: watermark calculation data
 668  *
 669  * Calculate the latency watermark (CIK).
 670  * Used for display watermark bandwidth calculations
 671  * Returns the latency watermark in ns
 672  */
 673 static u32 dce_v6_0_latency_watermark(struct dce6_wm_params *wm)
 674 {
 675         /* First calculate the latency in ns */
 676         u32 mc_latency = 2000; /* 2000 ns. */
 677         u32 available_bandwidth = dce_v6_0_available_bandwidth(wm);
 678         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
 679         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
 680         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
 681         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
 682                 (wm->num_heads * cursor_line_pair_return_time);
 683         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
 684         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
 685         u32 tmp, dmif_size = 12288;
 686         fixed20_12 a, b, c;
 687
 688         if (wm->num_heads == 0)
 689                 return 0;
 690
 691         a.full = dfixed_const(2);
 692         b.full = dfixed_const(1);
 693         if ((wm->vsc.full > a.full) ||
 694             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
 695             (wm->vtaps >= 5) ||
 696             ((wm->vsc.full >= a.full) && wm->interlaced))
 697                 max_src_lines_per_dst_line = 4;
 698         else
 699                 max_src_lines_per_dst_line = 2;
 700
 701         a.full = dfixed_const(available_bandwidth);
 702         b.full = dfixed_const(wm->num_heads);
 703         a.full = dfixed_div(a, b);
 704         tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
 705         tmp = min(dfixed_trunc(a), tmp);
 706
 707         lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
 708
 709         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
 710         b.full = dfixed_const(1000);
 711         c.full = dfixed_const(lb_fill_bw);
 712         b.full = dfixed_div(c, b);
 713         a.full = dfixed_div(a, b);
 714         line_fill_time = dfixed_trunc(a);
 715
 716         if (line_fill_time < wm->active_time)
 717                 return latency;
 718         else
 719                 return latency + (line_fill_time - wm->active_time);
 720
 721 }
 722
 723 /**
 724  * dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display - check
 725  * average and available dram bandwidth
 726  *
 727  * @wm: watermark calculation data
 728  *
 729  * Check if the display average bandwidth fits in the display
 730  * dram bandwidth (CIK).
 731  * Used for display watermark bandwidth calculations
 732  * Returns true if the display fits, false if not.
 733  */
 734 static bool dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm)
 735 {
 736         if (dce_v6_0_average_bandwidth(wm) <=
 737             (dce_v6_0_dram_bandwidth_for_display(wm) / wm->num_heads))
 738                 return true;
 739         else
 740                 return false;
 741 }
 742
 743 /**
 744  * dce_v6_0_average_bandwidth_vs_available_bandwidth - check
 745  * average and available bandwidth
 746  *
 747  * @wm: watermark calculation data
 748  *
 749  * Check if the display average bandwidth fits in the display
 750  * available bandwidth (CIK).
 751  * Used for display watermark bandwidth calculations
 752  * Returns true if the display fits, false if not.
 753  */
 754 static bool dce_v6_0_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm)
 755 {
 756         if (dce_v6_0_average_bandwidth(wm) <=
 757             (dce_v6_0_available_bandwidth(wm) / wm->num_heads))
 758                 return true;
 759         else
 760                 return false;
 761 }
 762
 763 /**
 764  * dce_v6_0_check_latency_hiding - check latency hiding
 765  *
 766  * @wm: watermark calculation data
 767  *
 768  * Check latency hiding (CIK).
 769  * Used for display watermark bandwidth calculations
 770  * Returns true if the display fits, false if not.
 771  */
 772 static bool dce_v6_0_check_latency_hiding(struct dce6_wm_params *wm)
 773 {
 774         u32 lb_partitions = wm->lb_size / wm->src_width;
 775         u32 line_time = wm->active_time + wm->blank_time;
 776         u32 latency_tolerant_lines;
 777         u32 latency_hiding;
 778         fixed20_12 a;
 779
 780         a.full = dfixed_const(1);
 781         if (wm->vsc.full > a.full)
 782                 latency_tolerant_lines = 1;
 783         else {
 784                 if (lb_partitions <= (wm->vtaps + 1))
 785                         latency_tolerant_lines = 1;
 786                 else
 787                         latency_tolerant_lines = 2;
 788         }
 789
 790         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
 791
 792         if (dce_v6_0_latency_watermark(wm) <= latency_hiding)
 793                 return true;
 794         else
 795                 return false;
 796 }
 797
 798 /**
 799  * dce_v6_0_program_watermarks - program display watermarks
 800  *
 801  * @adev: amdgpu_device pointer
 802  * @amdgpu_crtc: the selected display controller
 803  * @lb_size: line buffer size
 804  * @num_heads: number of display controllers in use
 805  *
 806  * Calculate and program the display watermarks for the
 807  * selected display controller (CIK).
 808  */
 809 static void dce_v6_0_program_watermarks(struct amdgpu_device *adev,
 810                                         struct amdgpu_crtc *amdgpu_crtc,
 811                                         u32 lb_size, u32 num_heads)
 812 {
 813         struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
 814         struct dce6_wm_params wm_low, wm_high;
 815         u32 dram_channels;
 816         u32 active_time;
 817         u32 line_time = 0;
 818         u32 latency_watermark_a = 0, latency_watermark_b = 0;
 819         u32 priority_a_mark = 0, priority_b_mark = 0;
 820         u32 priority_a_cnt = PRIORITY_OFF;
 821         u32 priority_b_cnt = PRIORITY_OFF;
 822         u32 tmp, arb_control3, lb_vblank_lead_lines = 0;
 823         fixed20_12 a, b, c;
 824
 825         if (amdgpu_crtc->base.enabled && num_heads && mode) {
 826                 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
 827                                             (u32)mode->clock);
 828                 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
 829                                           (u32)mode->clock);
 830                 line_time = min(line_time, (u32)65535);
 831                 priority_a_cnt = 0;
 832                 priority_b_cnt = 0;
 833
 834                 dram_channels = si_get_number_of_dram_channels(adev);
 835
 836                 /* watermark for high clocks */
 837                 if (adev->pm.dpm_enabled) {
 838                         wm_high.yclk =
 839                                 amdgpu_dpm_get_mclk(adev, false) * 10;
 840                         wm_high.sclk =
 841                                 amdgpu_dpm_get_sclk(adev, false) * 10;
 842                 } else {
 843                         wm_high.yclk = adev->pm.current_mclk * 10;
 844                         wm_high.sclk = adev->pm.current_sclk * 10;
 845                 }
 846
 847                 wm_high.disp_clk = mode->clock;
 848                 wm_high.src_width = mode->crtc_hdisplay;
 849                 wm_high.active_time = active_time;
 850                 wm_high.blank_time = line_time - wm_high.active_time;
 851                 wm_high.interlaced = false;
 852                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 853                         wm_high.interlaced = true;
 854                 wm_high.vsc = amdgpu_crtc->vsc;
 855                 wm_high.vtaps = 1;
 856                 if (amdgpu_crtc->rmx_type != RMX_OFF)
 857                         wm_high.vtaps = 2;
 858                 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
 859                 wm_high.lb_size = lb_size;
 860                 wm_high.dram_channels = dram_channels;
 861                 wm_high.num_heads = num_heads;
 862
 863                 if (adev->pm.dpm_enabled) {
 864                 /* watermark for low clocks */
 865                         wm_low.yclk =
 866                                 amdgpu_dpm_get_mclk(adev, true) * 10;
 867                         wm_low.sclk =
 868                                 amdgpu_dpm_get_sclk(adev, true) * 10;
 869                 } else {
 870                         wm_low.yclk = adev->pm.current_mclk * 10;
 871                         wm_low.sclk = adev->pm.current_sclk * 10;
 872                 }
 873
 874                 wm_low.disp_clk = mode->clock;
 875                 wm_low.src_width = mode->crtc_hdisplay;
 876                 wm_low.active_time = active_time;
 877                 wm_low.blank_time = line_time - wm_low.active_time;
 878                 wm_low.interlaced = false;
 879                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 880                         wm_low.interlaced = true;
 881                 wm_low.vsc = amdgpu_crtc->vsc;
 882                 wm_low.vtaps = 1;
 883                 if (amdgpu_crtc->rmx_type != RMX_OFF)
 884                         wm_low.vtaps = 2;
 885                 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
 886                 wm_low.lb_size = lb_size;
 887                 wm_low.dram_channels = dram_channels;
 888                 wm_low.num_heads = num_heads;
 889
 890                 /* set for high clocks */
 891                 latency_watermark_a = min(dce_v6_0_latency_watermark(&wm_high), (u32)65535);
 892                 /* set for low clocks */
 893                 latency_watermark_b = min(dce_v6_0_latency_watermark(&wm_low), (u32)65535);
 894
 895                 /* possibly force display priority to high */
 896                 /* should really do this at mode validation time... */
 897                 if (!dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
 898                     !dce_v6_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
 899                     !dce_v6_0_check_latency_hiding(&wm_high) ||
 900                     (adev->mode_info.disp_priority == 2)) {
 901                         DRM_DEBUG_KMS("force priority to high\n");
 902                         priority_a_cnt |= PRIORITY_ALWAYS_ON;
 903                         priority_b_cnt |= PRIORITY_ALWAYS_ON;
 904                 }
 905                 if (!dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
 906                     !dce_v6_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
 907                     !dce_v6_0_check_latency_hiding(&wm_low) ||
 908                     (adev->mode_info.disp_priority == 2)) {
 909                         DRM_DEBUG_KMS("force priority to high\n");
 910                         priority_a_cnt |= PRIORITY_ALWAYS_ON;
 911                         priority_b_cnt |= PRIORITY_ALWAYS_ON;
 912                 }
 913
 914                 a.full = dfixed_const(1000);
 915                 b.full = dfixed_const(mode->clock);
 916                 b.full = dfixed_div(b, a);
 917                 c.full = dfixed_const(latency_watermark_a);
 918                 c.full = dfixed_mul(c, b);
 919                 c.full = dfixed_mul(c, amdgpu_crtc->hsc);
 920                 c.full = dfixed_div(c, a);
 921                 a.full = dfixed_const(16);
 922                 c.full = dfixed_div(c, a);
 923                 priority_a_mark = dfixed_trunc(c);
 924                 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
 925
 926                 a.full = dfixed_const(1000);
 927                 b.full = dfixed_const(mode->clock);
 928                 b.full = dfixed_div(b, a);
 929                 c.full = dfixed_const(latency_watermark_b);
 930                 c.full = dfixed_mul(c, b);
 931                 c.full = dfixed_mul(c, amdgpu_crtc->hsc);
 932                 c.full = dfixed_div(c, a);
 933                 a.full = dfixed_const(16);
 934                 c.full = dfixed_div(c, a);
 935                 priority_b_mark = dfixed_trunc(c);
 936                 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
 937
 938                 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
 939         }
 940
 941         /* select wm A */
 942         arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);
 943         tmp = arb_control3;
 944         tmp &= ~LATENCY_WATERMARK_MASK(3);
 945         tmp |= LATENCY_WATERMARK_MASK(1);
 946         WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);
 947         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
 948                ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT)  |
 949                 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
 950         /* select wm B */
 951         tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);
 952         tmp &= ~LATENCY_WATERMARK_MASK(3);
 953         tmp |= LATENCY_WATERMARK_MASK(2);
 954         WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);
 955         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
 956                ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
 957                 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
 958         /* restore original selection */
 959         WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3);
 960
 961         /* write the priority marks */
 962         WREG32(mmPRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt);
 963         WREG32(mmPRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt);
 964
 965         /* save values for DPM */
 966         amdgpu_crtc->line_time = line_time;
 967         amdgpu_crtc->wm_high = latency_watermark_a;
 968
 969         /* Save number of lines the linebuffer leads before the scanout */
 970         amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
 971 }
 972
 973 /* watermark setup */
 974 static u32 dce_v6_0_line_buffer_adjust(struct amdgpu_device *adev,
 975                                    struct amdgpu_crtc *amdgpu_crtc,
 976                                    struct drm_display_mode *mode,
 977                                    struct drm_display_mode *other_mode)
 978 {
 979         u32 tmp, buffer_alloc, i;
 980         u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;
 981         /*
 982          * Line Buffer Setup
 983          * There are 3 line buffers, each one shared by 2 display controllers.
 984          * mmDC_LB_MEMORY_SPLIT controls how that line buffer is shared between
 985          * the display controllers.  The paritioning is done via one of four
 986          * preset allocations specified in bits 21:20:
 987          *  0 - half lb
 988          *  2 - whole lb, other crtc must be disabled
 989          */
 990         /* this can get tricky if we have two large displays on a paired group
 991          * of crtcs.  Ideally for multiple large displays we'd assign them to
 992          * non-linked crtcs for maximum line buffer allocation.
 993          */
 994         if (amdgpu_crtc->base.enabled && mode) {
 995                 if (other_mode) {
 996                         tmp = 0; /* 1/2 */
 997                         buffer_alloc = 1;
 998                 } else {
 999                         tmp = 2; /* whole */
1000                         buffer_alloc = 2;
1001                 }
1002         } else {
1003                 tmp = 0;
1004                 buffer_alloc = 0;
1005         }
1006
1007         WREG32(mmDC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset,
1008                DC_LB_MEMORY_CONFIG(tmp));
1009
1010         WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
1011                (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT));
1012         for (i = 0; i < adev->usec_timeout; i++) {
1013                 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
1014                     PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK)
1015                         break;
1016                 udelay(1);
1017         }
1018
1019         if (amdgpu_crtc->base.enabled && mode) {
1020                 switch (tmp) {
1021                 case 0:
1022                 default:
1023                         return 4096 * 2;
1024                 case 2:
1025                         return 8192 * 2;
1026                 }
1027         }
1028
1029         /* controller not enabled, so no lb used */
1030         return 0;
1031 }
1032
1033
1034 /**
1035  *
1036  * dce_v6_0_bandwidth_update - program display watermarks
1037  *
1038  * @adev: amdgpu_device pointer
1039  *
1040  * Calculate and program the display watermarks and line
1041  * buffer allocation (CIK).
1042  */
1043 static void dce_v6_0_bandwidth_update(struct amdgpu_device *adev)
1044 {
1045         struct drm_display_mode *mode0 = NULL;
1046         struct drm_display_mode *mode1 = NULL;
1047         u32 num_heads = 0, lb_size;
1048         int i;
1049
1050         if (!adev->mode_info.mode_config_initialized)
1051                 return;
1052
1053         amdgpu_display_update_priority(adev);
1054
1055         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1056                 if (adev->mode_info.crtcs[i]->base.enabled)
1057                         num_heads++;
1058         }
1059         for (i = 0; i < adev->mode_info.num_crtc; i += 2) {
1060                 mode0 = &adev->mode_info.crtcs[i]->base.mode;
1061                 mode1 = &adev->mode_info.crtcs[i+1]->base.mode;
1062                 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode0, mode1);
1063                 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i], lb_size, num_heads);
1064                 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i+1], mode1, mode0);
1065                 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i+1], lb_size, num_heads);
1066         }
1067 }
1068
1069 static void dce_v6_0_audio_get_connected_pins(struct amdgpu_device *adev)
1070 {
1071         int i;
1072         u32 tmp;
1073
1074         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1075                 tmp = RREG32_AUDIO_ENDPT(adev->mode_info.audio.pin[i].offset,
1076                                 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1077                 if (REG_GET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT,
1078                                         PORT_CONNECTIVITY))
1079                         adev->mode_info.audio.pin[i].connected = false;
1080                 else
1081                         adev->mode_info.audio.pin[i].connected = true;
1082         }
1083
1084 }
1085
1086 static struct amdgpu_audio_pin *dce_v6_0_audio_get_pin(struct amdgpu_device *adev)
1087 {
1088         int i;
1089
1090         dce_v6_0_audio_get_connected_pins(adev);
1091
1092         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1093                 if (adev->mode_info.audio.pin[i].connected)
1094                         return &adev->mode_info.audio.pin[i];
1095         }
1096         DRM_ERROR("No connected audio pins found!\n");
1097         return NULL;
1098 }
1099
1100 static void dce_v6_0_audio_select_pin(struct drm_encoder *encoder)
1101 {
1102         struct amdgpu_device *adev = encoder->dev->dev_private;
1103         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1104         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1105
1106         if (!dig || !dig->afmt || !dig->afmt->pin)
1107                 return;
1108
1109         WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset,
1110                REG_SET_FIELD(0, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT,
1111                              dig->afmt->pin->id));
1112 }
1113
1114 static void dce_v6_0_audio_write_latency_fields(struct drm_encoder *encoder,
1115                                                 struct drm_display_mode *mode)
1116 {
1117         struct amdgpu_device *adev = encoder->dev->dev_private;
1118         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1119         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1120         struct drm_connector *connector;
1121         struct amdgpu_connector *amdgpu_connector = NULL;
1122         int interlace = 0;
1123         u32 tmp;
1124
1125         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1126                 if (connector->encoder == encoder) {
1127                         amdgpu_connector = to_amdgpu_connector(connector);
1128                         break;
1129                 }
1130         }
1131
1132         if (!amdgpu_connector) {
1133                 DRM_ERROR("Couldn't find encoder's connector\n");
1134                 return;
1135         }
1136
1137         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1138                 interlace = 1;
1139
1140         if (connector->latency_present[interlace]) {
1141                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1142                                 VIDEO_LIPSYNC, connector->video_latency[interlace]);
1143                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1144                                 AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1145         } else {
1146                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1147                                 VIDEO_LIPSYNC, 0);
1148                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1149                                 AUDIO_LIPSYNC, 0);
1150         }
1151         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1152                            ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1153 }
1154
1155 static void dce_v6_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1156 {
1157         struct amdgpu_device *adev = encoder->dev->dev_private;
1158         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1159         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1160         struct drm_connector *connector;
1161         struct amdgpu_connector *amdgpu_connector = NULL;
1162         u8 *sadb = NULL;
1163         int sad_count;
1164         u32 tmp;
1165
1166         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1167                 if (connector->encoder == encoder) {
1168                         amdgpu_connector = to_amdgpu_connector(connector);
1169                         break;
1170                 }
1171         }
1172
1173         if (!amdgpu_connector) {
1174                 DRM_ERROR("Couldn't find encoder's connector\n");
1175                 return;
1176         }
1177
1178         sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1179         if (sad_count < 0) {
1180                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1181                 sad_count = 0;
1182         }
1183
1184         /* program the speaker allocation */
1185         tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1186                         ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1187         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1188                         HDMI_CONNECTION, 0);
1189         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1190                         DP_CONNECTION, 0);
1191
1192         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort)
1193                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1194                                 DP_CONNECTION, 1);
1195         else
1196                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1197                                 HDMI_CONNECTION, 1);
1198
1199         if (sad_count)
1200                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1201                                 SPEAKER_ALLOCATION, sadb[0]);
1202         else
1203                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1204                                 SPEAKER_ALLOCATION, 5); /* stereo */
1205
1206         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1207                         ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1208
1209         kfree(sadb);
1210 }
1211
1212 static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder)
1213 {
1214         struct amdgpu_device *adev = encoder->dev->dev_private;
1215         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1216         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1217         struct drm_connector *connector;
1218         struct amdgpu_connector *amdgpu_connector = NULL;
1219         struct cea_sad *sads;
1220         int i, sad_count;
1221
1222         static const u16 eld_reg_to_type[][2] = {
1223                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1224                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1225                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1226                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1227                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1228                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1229                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1230                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1231                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1232                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1233                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1234                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1235         };
1236
1237         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1238                 if (connector->encoder == encoder) {
1239                         amdgpu_connector = to_amdgpu_connector(connector);
1240                         break;
1241                 }
1242         }
1243
1244         if (!amdgpu_connector) {
1245                 DRM_ERROR("Couldn't find encoder's connector\n");
1246                 return;
1247         }
1248
1249         sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1250         if (sad_count <= 0) {
1251                 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1252                 return;
1253         }
1254
1255         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1256                 u32 tmp = 0;
1257                 u8 stereo_freqs = 0;
1258                 int max_channels = -1;
1259                 int j;
1260
1261                 for (j = 0; j < sad_count; j++) {
1262                         struct cea_sad *sad = &sads[j];
1263
1264                         if (sad->format == eld_reg_to_type[i][1]) {
1265                                 if (sad->channels > max_channels) {
1266                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1267                                                         MAX_CHANNELS, sad->channels);
1268                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1269                                                         DESCRIPTOR_BYTE_2, sad->byte2);
1270                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1271                                                         SUPPORTED_FREQUENCIES, sad->freq);
1272                                         max_channels = sad->channels;
1273                                 }
1274
1275                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1276                                         stereo_freqs |= sad->freq;
1277                                 else
1278                                         break;
1279                         }
1280                 }
1281
1282                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1283                                 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1284                 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1285         }
1286
1287         kfree(sads);
1288
1289 }
1290
1291 static void dce_v6_0_audio_enable(struct amdgpu_device *adev,
1292                                   struct amdgpu_audio_pin *pin,
1293                                   bool enable)
1294 {
1295         if (!pin)
1296                 return;
1297
1298         WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1299                         enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1300 }
1301
1302 static const u32 pin_offsets[7] =
1303 {
1304         (0x1780 - 0x1780),
1305         (0x1786 - 0x1780),
1306         (0x178c - 0x1780),
1307         (0x1792 - 0x1780),
1308         (0x1798 - 0x1780),
1309         (0x179d - 0x1780),
1310         (0x17a4 - 0x1780),
1311 };
1312
1313 static int dce_v6_0_audio_init(struct amdgpu_device *adev)
1314 {
1315         int i;
1316
1317         if (!amdgpu_audio)
1318                 return 0;
1319
1320         adev->mode_info.audio.enabled = true;
1321
1322         switch (adev->asic_type) {
1323         case CHIP_TAHITI:
1324         case CHIP_PITCAIRN:
1325         case CHIP_VERDE:
1326         default:
1327                 adev->mode_info.audio.num_pins = 6;
1328                 break;
1329         case CHIP_OLAND:
1330                 adev->mode_info.audio.num_pins = 2;
1331                 break;
1332         }
1333
1334         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1335                 adev->mode_info.audio.pin[i].channels = -1;
1336                 adev->mode_info.audio.pin[i].rate = -1;
1337                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1338                 adev->mode_info.audio.pin[i].status_bits = 0;
1339                 adev->mode_info.audio.pin[i].category_code = 0;
1340                 adev->mode_info.audio.pin[i].connected = false;
1341                 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1342                 adev->mode_info.audio.pin[i].id = i;
1343                 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1344         }
1345
1346         return 0;
1347 }
1348
1349 static void dce_v6_0_audio_fini(struct amdgpu_device *adev)
1350 {
1351         int i;
1352
1353         if (!amdgpu_audio)
1354                 return;
1355
1356         if (!adev->mode_info.audio.enabled)
1357                 return;
1358
1359         for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1360                 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1361
1362         adev->mode_info.audio.enabled = false;
1363 }
1364
1365 static void dce_v6_0_audio_set_vbi_packet(struct drm_encoder *encoder)
1366 {
1367         struct drm_device *dev = encoder->dev;
1368         struct amdgpu_device *adev = dev->dev_private;
1369         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1370         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1371         u32 tmp;
1372
1373         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1374         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1375         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1);
1376         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1);
1377         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1378 }
1379
1380 static void dce_v6_0_audio_set_acr(struct drm_encoder *encoder,
1381                                    uint32_t clock, int bpc)
1382 {
1383         struct drm_device *dev = encoder->dev;
1384         struct amdgpu_device *adev = dev->dev_private;
1385         struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1386         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1387         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1388         u32 tmp;
1389
1390         tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1391         tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1392         tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE,
1393                         bpc > 8 ? 0 : 1);
1394         WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1395
1396         tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1397         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1398         WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1399         tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1400         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1401         WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1402
1403         tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1404         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1405         WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1406         tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1407         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1408         WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1409
1410         tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1411         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1412         WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1413         tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1414         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1415         WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1416 }
1417
1418 static void dce_v6_0_audio_set_avi_infoframe(struct drm_encoder *encoder,
1419                                                struct drm_display_mode *mode)
1420 {
1421         struct drm_device *dev = encoder->dev;
1422         struct amdgpu_device *adev = dev->dev_private;
1423         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1424         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1425         struct hdmi_avi_infoframe frame;
1426         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1427         uint8_t *payload = buffer + 3;
1428         uint8_t *header = buffer;
1429         ssize_t err;
1430         u32 tmp;
1431
1432         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false);
1433         if (err < 0) {
1434                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1435                 return;
1436         }
1437
1438         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1439         if (err < 0) {
1440                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1441                 return;
1442         }
1443
1444         WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1445                payload[0x0] | (payload[0x1] << 8) | (payload[0x2] << 16) | (payload[0x3] << 24));
1446         WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1447                payload[0x4] | (payload[0x5] << 8) | (payload[0x6] << 16) | (payload[0x7] << 24));
1448         WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1449                payload[0x8] | (payload[0x9] << 8) | (payload[0xA] << 16) | (payload[0xB] << 24));
1450         WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1451                payload[0xC] | (payload[0xD] << 8) | (header[1] << 24));
1452
1453         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1454         /* anything other than 0 */
1455         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1,
1456                         HDMI_AUDIO_INFO_LINE, 2);
1457         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1458 }
1459
1460 static void dce_v6_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1461 {
1462         struct drm_device *dev = encoder->dev;
1463         struct amdgpu_device *adev = dev->dev_private;
1464         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1465         int em = amdgpu_atombios_encoder_get_encoder_mode(encoder);
1466         u32 tmp;
1467
1468         /*
1469          * Two dtos: generally use dto0 for hdmi, dto1 for dp.
1470          * Express [24MHz / target pixel clock] as an exact rational
1471          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
1472          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1473          */
1474         tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1475         tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
1476                         DCCG_AUDIO_DTO0_SOURCE_SEL, amdgpu_crtc->crtc_id);
1477         if (em == ATOM_ENCODER_MODE_HDMI) {
1478                 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
1479                                 DCCG_AUDIO_DTO_SEL, 0);
1480         } else if (ENCODER_MODE_IS_DP(em)) {
1481                 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
1482                                 DCCG_AUDIO_DTO_SEL, 1);
1483         }
1484         WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1485         if (em == ATOM_ENCODER_MODE_HDMI) {
1486                 WREG32(mmDCCG_AUDIO_DTO0_PHASE, 24000);
1487                 WREG32(mmDCCG_AUDIO_DTO0_MODULE, clock);
1488         } else if (ENCODER_MODE_IS_DP(em)) {
1489                 WREG32(mmDCCG_AUDIO_DTO1_PHASE, 24000);
1490                 WREG32(mmDCCG_AUDIO_DTO1_MODULE, clock);
1491         }
1492 }
1493
1494 static void dce_v6_0_audio_set_packet(struct drm_encoder *encoder)
1495 {
1496         struct drm_device *dev = encoder->dev;
1497         struct amdgpu_device *adev = dev->dev_private;
1498         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1499         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1500         u32 tmp;
1501
1502         tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1503         tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1504         WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1505
1506         tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1507         tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1508         WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1509
1510         tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1511         tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1512         WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1513
1514         tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1515         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1516         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1517         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1518         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1519         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1520         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1521         WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1522
1523         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset);
1524         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, 0xff);
1525         WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, tmp);
1526
1527         tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1528         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1529         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1530         WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1531
1532         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1533         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_RESET_FIFO_WHEN_AUDIO_DIS, 1);
1534         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1535         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1536 }
1537
1538 static void dce_v6_0_audio_set_mute(struct drm_encoder *encoder, bool mute)
1539 {
1540         struct drm_device *dev = encoder->dev;
1541         struct amdgpu_device *adev = dev->dev_private;
1542         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1543         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1544         u32 tmp;
1545
1546         tmp = RREG32(mmHDMI_GC + dig->afmt->offset);
1547         tmp = REG_SET_FIELD(tmp, HDMI_GC, HDMI_GC_AVMUTE, mute ? 1 : 0);
1548         WREG32(mmHDMI_GC + dig->afmt->offset, tmp);
1549 }
1550
1551 static void dce_v6_0_audio_hdmi_enable(struct drm_encoder *encoder, bool enable)
1552 {
1553         struct drm_device *dev = encoder->dev;
1554         struct amdgpu_device *adev = dev->dev_private;
1555         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1556         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1557         u32 tmp;
1558
1559         if (enable) {
1560                 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1561                 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1562                 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1563                 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1564                 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1565                 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1566
1567                 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1568                 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1569                 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1570
1571                 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1572                 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1573                 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1574         } else {
1575                 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1576                 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 0);
1577                 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 0);
1578                 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 0);
1579                 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 0);
1580                 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1581
1582                 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1583                 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 0);
1584                 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1585         }
1586 }
1587
1588 static void dce_v6_0_audio_dp_enable(struct drm_encoder *encoder, bool enable)
1589 {
1590         struct drm_device *dev = encoder->dev;
1591         struct amdgpu_device *adev = dev->dev_private;
1592         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1593         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1594         u32 tmp;
1595
1596         if (enable) {
1597                 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1598                 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1599                 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1600
1601                 tmp = RREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset);
1602                 tmp = REG_SET_FIELD(tmp, DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, 1);
1603                 WREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset, tmp);
1604
1605                 tmp = RREG32(mmDP_SEC_CNTL + dig->afmt->offset);
1606                 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
1607                 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ATP_ENABLE, 1);
1608                 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_AIP_ENABLE, 1);
1609                 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1610                 WREG32(mmDP_SEC_CNTL + dig->afmt->offset, tmp);
1611         } else {
1612                 WREG32(mmDP_SEC_CNTL + dig->afmt->offset, 0);
1613         }
1614 }
1615
1616 static void dce_v6_0_afmt_setmode(struct drm_encoder *encoder,
1617                                   struct drm_display_mode *mode)
1618 {
1619         struct drm_device *dev = encoder->dev;
1620         struct amdgpu_device *adev = dev->dev_private;
1621         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1622         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1623         struct drm_connector *connector;
1624         struct amdgpu_connector *amdgpu_connector = NULL;
1625         int em = amdgpu_atombios_encoder_get_encoder_mode(encoder);
1626         int bpc = 8;
1627
1628         if (!dig || !dig->afmt)
1629                 return;
1630
1631         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1632                 if (connector->encoder == encoder) {
1633                         amdgpu_connector = to_amdgpu_connector(connector);
1634                         break;
1635                 }
1636         }
1637
1638         if (!amdgpu_connector) {
1639                 DRM_ERROR("Couldn't find encoder's connector\n");
1640                 return;
1641         }
1642
1643         if (!dig->afmt->enabled)
1644                 return;
1645
1646         dig->afmt->pin = dce_v6_0_audio_get_pin(adev);
1647         if (!dig->afmt->pin)
1648                 return;
1649
1650         if (encoder->crtc) {
1651                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1652                 bpc = amdgpu_crtc->bpc;
1653         }
1654
1655         /* disable audio before setting up hw */
1656         dce_v6_0_audio_enable(adev, dig->afmt->pin, false);
1657
1658         dce_v6_0_audio_set_mute(encoder, true);
1659         dce_v6_0_audio_write_speaker_allocation(encoder);
1660         dce_v6_0_audio_write_sad_regs(encoder);
1661         dce_v6_0_audio_write_latency_fields(encoder, mode);
1662         if (em == ATOM_ENCODER_MODE_HDMI) {
1663                 dce_v6_0_audio_set_dto(encoder, mode->clock);
1664                 dce_v6_0_audio_set_vbi_packet(encoder);
1665                 dce_v6_0_audio_set_acr(encoder, mode->clock, bpc);
1666         } else if (ENCODER_MODE_IS_DP(em)) {
1667                 dce_v6_0_audio_set_dto(encoder, adev->clock.default_dispclk * 10);
1668         }
1669         dce_v6_0_audio_set_packet(encoder);
1670         dce_v6_0_audio_select_pin(encoder);
1671         dce_v6_0_audio_set_avi_infoframe(encoder, mode);
1672         dce_v6_0_audio_set_mute(encoder, false);
1673         if (em == ATOM_ENCODER_MODE_HDMI) {
1674                 dce_v6_0_audio_hdmi_enable(encoder, 1);
1675         } else if (ENCODER_MODE_IS_DP(em)) {
1676                 dce_v6_0_audio_dp_enable(encoder, 1);
1677         }
1678
1679         /* enable audio after setting up hw */
1680         dce_v6_0_audio_enable(adev, dig->afmt->pin, true);
1681 }
1682
1683 static void dce_v6_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1684 {
1685         struct drm_device *dev = encoder->dev;
1686         struct amdgpu_device *adev = dev->dev_private;
1687         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1688         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1689
1690         if (!dig || !dig->afmt)
1691                 return;
1692
1693         /* Silent, r600_hdmi_enable will raise WARN for us */
1694         if (enable && dig->afmt->enabled)
1695                 return;
1696
1697         if (!enable && !dig->afmt->enabled)
1698                 return;
1699
1700         if (!enable && dig->afmt->pin) {
1701                 dce_v6_0_audio_enable(adev, dig->afmt->pin, false);
1702                 dig->afmt->pin = NULL;
1703         }
1704
1705         dig->afmt->enabled = enable;
1706
1707         DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1708                   enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1709 }
1710
1711 static int dce_v6_0_afmt_init(struct amdgpu_device *adev)
1712 {
1713         int i, j;
1714
1715         for (i = 0; i < adev->mode_info.num_dig; i++)
1716                 adev->mode_info.afmt[i] = NULL;
1717
1718         /* DCE6 has audio blocks tied to DIG encoders */
1719         for (i = 0; i < adev->mode_info.num_dig; i++) {
1720                 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1721                 if (adev->mode_info.afmt[i]) {
1722                         adev->mode_info.afmt[i]->offset = dig_offsets[i];
1723                         adev->mode_info.afmt[i]->id = i;
1724                 } else {
1725                         for (j = 0; j < i; j++) {
1726                                 kfree(adev->mode_info.afmt[j]);
1727                                 adev->mode_info.afmt[j] = NULL;
1728                         }
1729                         DRM_ERROR("Out of memory allocating afmt table\n");
1730                         return -ENOMEM;
1731                 }
1732         }
1733         return 0;
1734 }
1735
1736 static void dce_v6_0_afmt_fini(struct amdgpu_device *adev)
1737 {
1738         int i;
1739
1740         for (i = 0; i < adev->mode_info.num_dig; i++) {
1741                 kfree(adev->mode_info.afmt[i]);
1742                 adev->mode_info.afmt[i] = NULL;
1743         }
1744 }
1745
1746 static const u32 vga_control_regs[6] =
1747 {
1748         mmD1VGA_CONTROL,
1749         mmD2VGA_CONTROL,
1750         mmD3VGA_CONTROL,
1751         mmD4VGA_CONTROL,
1752         mmD5VGA_CONTROL,
1753         mmD6VGA_CONTROL,
1754 };
1755
1756 static void dce_v6_0_vga_enable(struct drm_crtc *crtc, bool enable)
1757 {
1758         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1759         struct drm_device *dev = crtc->dev;
1760         struct amdgpu_device *adev = dev->dev_private;
1761         u32 vga_control;
1762
1763         vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1764         WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | (enable ? 1 : 0));
1765 }
1766
1767 static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable)
1768 {
1769         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1770         struct drm_device *dev = crtc->dev;
1771         struct amdgpu_device *adev = dev->dev_private;
1772
1773         WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0);
1774 }
1775
1776 static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
1777                                      struct drm_framebuffer *fb,
1778                                      int x, int y, int atomic)
1779 {
1780         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1781         struct drm_device *dev = crtc->dev;
1782         struct amdgpu_device *adev = dev->dev_private;
1783         struct drm_framebuffer *target_fb;
1784         struct drm_gem_object *obj;
1785         struct amdgpu_bo *abo;
1786         uint64_t fb_location, tiling_flags;
1787         uint32_t fb_format, fb_pitch_pixels, pipe_config;
1788         u32 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_NONE);
1789         u32 viewport_w, viewport_h;
1790         int r;
1791         bool bypass_lut = false;
1792         struct drm_format_name_buf format_name;
1793
1794         /* no fb bound */
1795         if (!atomic && !crtc->primary->fb) {
1796                 DRM_DEBUG_KMS("No FB bound\n");
1797                 return 0;
1798         }
1799
1800         if (atomic)
1801                 target_fb = fb;
1802         else
1803                 target_fb = crtc->primary->fb;
1804
1805         /* If atomic, assume fb object is pinned & idle & fenced and
1806          * just update base pointers
1807          */
1808         obj = target_fb->obj[0];
1809         abo = gem_to_amdgpu_bo(obj);
1810         r = amdgpu_bo_reserve(abo, false);
1811         if (unlikely(r != 0))
1812                 return r;
1813
1814         if (atomic) {
1815                 fb_location = amdgpu_bo_gpu_offset(abo);
1816         } else {
1817                 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
1818                 if (unlikely(r != 0)) {
1819                         amdgpu_bo_unreserve(abo);
1820                         return -EINVAL;
1821                 }
1822         }
1823
1824         amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1825         amdgpu_bo_unreserve(abo);
1826
1827         switch (target_fb->format->format) {
1828         case DRM_FORMAT_C8:
1829                 fb_format = (GRPH_DEPTH(GRPH_DEPTH_8BPP) |
1830                              GRPH_FORMAT(GRPH_FORMAT_INDEXED));
1831                 break;
1832         case DRM_FORMAT_XRGB4444:
1833         case DRM_FORMAT_ARGB4444:
1834                 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
1835                              GRPH_FORMAT(GRPH_FORMAT_ARGB4444));
1836 #ifdef __BIG_ENDIAN
1837                 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
1838 #endif
1839                 break;
1840         case DRM_FORMAT_XRGB1555:
1841         case DRM_FORMAT_ARGB1555:
1842                 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
1843                              GRPH_FORMAT(GRPH_FORMAT_ARGB1555));
1844 #ifdef __BIG_ENDIAN
1845                 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
1846 #endif
1847                 break;
1848         case DRM_FORMAT_BGRX5551:
1849         case DRM_FORMAT_BGRA5551:
1850                 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
1851                              GRPH_FORMAT(GRPH_FORMAT_BGRA5551));
1852 #ifdef __BIG_ENDIAN
1853                 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
1854 #endif
1855                 break;
1856         case DRM_FORMAT_RGB565:
1857                 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
1858                              GRPH_FORMAT(GRPH_FORMAT_ARGB565));
1859 #ifdef __BIG_ENDIAN
1860                 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
1861 #endif
1862                 break;
1863         case DRM_FORMAT_XRGB8888:
1864         case DRM_FORMAT_ARGB8888:
1865                 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
1866                              GRPH_FORMAT(GRPH_FORMAT_ARGB8888));
1867 #ifdef __BIG_ENDIAN
1868                 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
1869 #endif
1870                 break;
1871         case DRM_FORMAT_XRGB2101010:
1872         case DRM_FORMAT_ARGB2101010:
1873                 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
1874                              GRPH_FORMAT(GRPH_FORMAT_ARGB2101010));
1875 #ifdef __BIG_ENDIAN
1876                 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
1877 #endif
1878                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1879                 bypass_lut = true;
1880                 break;
1881         case DRM_FORMAT_BGRX1010102:
1882         case DRM_FORMAT_BGRA1010102:
1883                 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
1884                              GRPH_FORMAT(GRPH_FORMAT_BGRA1010102));
1885 #ifdef __BIG_ENDIAN
1886                 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
1887 #endif
1888                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1889                 bypass_lut = true;
1890                 break;
1891         default:
1892                 DRM_ERROR("Unsupported screen format %s\n",
1893                           drm_get_format_name(target_fb->format->format, &format_name));
1894                 return -EINVAL;
1895         }
1896
1897         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1898                 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
1899
1900                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1901                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1902                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1903                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1904                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1905
1906                 fb_format |= GRPH_NUM_BANKS(num_banks);
1907                 fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_2D_TILED_THIN1);
1908                 fb_format |= GRPH_TILE_SPLIT(tile_split);
1909                 fb_format |= GRPH_BANK_WIDTH(bankw);
1910                 fb_format |= GRPH_BANK_HEIGHT(bankh);
1911                 fb_format |= GRPH_MACRO_TILE_ASPECT(mtaspect);
1912         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
1913                 fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_1D_TILED_THIN1);
1914         }
1915
1916         pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1917         fb_format |= GRPH_PIPE_CONFIG(pipe_config);
1918
1919         dce_v6_0_vga_enable(crtc, false);
1920
1921         /* Make sure surface address is updated at vertical blank rather than
1922          * horizontal blank
1923          */
1924         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
1925
1926         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1927                upper_32_bits(fb_location));
1928         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1929                upper_32_bits(fb_location));
1930         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1931                (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
1932         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1933                (u32) fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
1934         WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
1935         WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
1936
1937         /*
1938          * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
1939          * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
1940          * retain the full precision throughout the pipeline.
1941          */
1942         WREG32_P(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset,
1943                  (bypass_lut ? GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK : 0),
1944                  ~GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK);
1945
1946         if (bypass_lut)
1947                 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1948
1949         WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
1950         WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
1951         WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
1952         WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
1953         WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
1954         WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
1955
1956         fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
1957         WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
1958
1959         dce_v6_0_grph_enable(crtc, true);
1960
1961         WREG32(mmDESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
1962                        target_fb->height);
1963         x &= ~3;
1964         y &= ~1;
1965         WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
1966                (x << 16) | y);
1967         viewport_w = crtc->mode.hdisplay;
1968         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1969
1970         WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
1971                (viewport_w << 16) | viewport_h);
1972
1973         /* set pageflip to happen anywhere in vblank interval */
1974         WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
1975
1976         if (!atomic && fb && fb != crtc->primary->fb) {
1977                 abo = gem_to_amdgpu_bo(fb->obj[0]);
1978                 r = amdgpu_bo_reserve(abo, true);
1979                 if (unlikely(r != 0))
1980                         return r;
1981                 amdgpu_bo_unpin(abo);
1982                 amdgpu_bo_unreserve(abo);
1983         }
1984
1985         /* Bytes per pixel may have changed */
1986         dce_v6_0_bandwidth_update(adev);
1987
1988         return 0;
1989
1990 }
1991
1992 static void dce_v6_0_set_interleave(struct drm_crtc *crtc,
1993                                     struct drm_display_mode *mode)
1994 {
1995         struct drm_device *dev = crtc->dev;
1996         struct amdgpu_device *adev = dev->dev_private;
1997         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1998
1999         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2000                 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset,
2001                        INTERLEAVE_EN);
2002         else
2003                 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
2004 }
2005
2006 static void dce_v6_0_crtc_load_lut(struct drm_crtc *crtc)
2007 {
2008
2009         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2010         struct drm_device *dev = crtc->dev;
2011         struct amdgpu_device *adev = dev->dev_private;
2012         u16 *r, *g, *b;
2013         int i;
2014
2015         DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2016
2017         WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2018                ((0 << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) |
2019                 (0 << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT)));
2020         WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
2021                PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK);
2022         WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
2023                PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK);
2024         WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2025                ((0 << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) |
2026                 (0 << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT)));
2027
2028         WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2029
2030         WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2031         WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2032         WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2033
2034         WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2035         WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2036         WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2037
2038         WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2039         WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2040
2041         WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2042         r = crtc->gamma_store;
2043         g = r + crtc->gamma_size;
2044         b = g + crtc->gamma_size;
2045         for (i = 0; i < 256; i++) {
2046                 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2047                        ((*r++ & 0xffc0) << 14) |
2048                        ((*g++ & 0xffc0) << 4) |
2049                        (*b++ >> 6));
2050         }
2051
2052         WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2053                ((0 << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) |
2054                 (0 << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) |
2055                 ICON_DEGAMMA_MODE(0) |
2056                 (0 << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT)));
2057         WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
2058                ((0 << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) |
2059                 (0 << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT)));
2060         WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2061                ((0 << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) |
2062                 (0 << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT)));
2063         WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2064                ((0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) |
2065                 (0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT)));
2066         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2067         WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
2068
2069
2070 }
2071
2072 static int dce_v6_0_pick_dig_encoder(struct drm_encoder *encoder)
2073 {
2074         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2075         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2076
2077         switch (amdgpu_encoder->encoder_id) {
2078         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2079                 return dig->linkb ? 1 : 0;
2080         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2081                 return dig->linkb ? 3 : 2;
2082         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2083                 return dig->linkb ? 5 : 4;
2084         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2085                 return 6;
2086         default:
2087                 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2088                 return 0;
2089         }
2090 }
2091
2092 /**
2093  * dce_v6_0_pick_pll - Allocate a PPLL for use by the crtc.
2094  *
2095  * @crtc: drm crtc
2096  *
2097  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
2098  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
2099  * monitors a dedicated PPLL must be used.  If a particular board has
2100  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2101  * as there is no need to program the PLL itself.  If we are not able to
2102  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2103  * avoid messing up an existing monitor.
2104  *
2105  *
2106  */
2107 static u32 dce_v6_0_pick_pll(struct drm_crtc *crtc)
2108 {
2109         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2110         struct drm_device *dev = crtc->dev;
2111         struct amdgpu_device *adev = dev->dev_private;
2112         u32 pll_in_use;
2113         int pll;
2114
2115         if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2116                 if (adev->clock.dp_extclk)
2117                         /* skip PPLL programming if using ext clock */
2118                         return ATOM_PPLL_INVALID;
2119                 else
2120                         return ATOM_PPLL0;
2121         } else {
2122                 /* use the same PPLL for all monitors with the same clock */
2123                 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2124                 if (pll != ATOM_PPLL_INVALID)
2125                         return pll;
2126         }
2127
2128         /*  PPLL1, and PPLL2 */
2129         pll_in_use = amdgpu_pll_get_use_mask(crtc);
2130         if (!(pll_in_use & (1 << ATOM_PPLL2)))
2131                 return ATOM_PPLL2;
2132         if (!(pll_in_use & (1 << ATOM_PPLL1)))
2133                 return ATOM_PPLL1;
2134         DRM_ERROR("unable to allocate a PPLL\n");
2135         return ATOM_PPLL_INVALID;
2136 }
2137
2138 static void dce_v6_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2139 {
2140         struct amdgpu_device *adev = crtc->dev->dev_private;
2141         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2142         uint32_t cur_lock;
2143
2144         cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2145         if (lock)
2146                 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2147         else
2148                 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2149         WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2150 }
2151
2152 static void dce_v6_0_hide_cursor(struct drm_crtc *crtc)
2153 {
2154         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2155         struct amdgpu_device *adev = crtc->dev->dev_private;
2156
2157         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2158                    (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2159                    (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2160
2161
2162 }
2163
2164 static void dce_v6_0_show_cursor(struct drm_crtc *crtc)
2165 {
2166         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2167         struct amdgpu_device *adev = crtc->dev->dev_private;
2168
2169         WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2170                upper_32_bits(amdgpu_crtc->cursor_addr));
2171         WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2172                lower_32_bits(amdgpu_crtc->cursor_addr));
2173
2174         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2175                    CUR_CONTROL__CURSOR_EN_MASK |
2176                    (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2177                    (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2178
2179 }
2180
2181 static int dce_v6_0_cursor_move_locked(struct drm_crtc *crtc,
2182                                        int x, int y)
2183 {
2184         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2185         struct amdgpu_device *adev = crtc->dev->dev_private;
2186         int xorigin = 0, yorigin = 0;
2187
2188         int w = amdgpu_crtc->cursor_width;
2189
2190         amdgpu_crtc->cursor_x = x;
2191         amdgpu_crtc->cursor_y = y;
2192
2193         /* avivo cursor are offset into the total surface */
2194         x += crtc->x;
2195         y += crtc->y;
2196         DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2197
2198         if (x < 0) {
2199                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2200                 x = 0;
2201         }
2202         if (y < 0) {
2203                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2204                 y = 0;
2205         }
2206
2207         WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2208         WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2209         WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2210                ((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2211
2212         return 0;
2213 }
2214
2215 static int dce_v6_0_crtc_cursor_move(struct drm_crtc *crtc,
2216                                      int x, int y)
2217 {
2218         int ret;
2219
2220         dce_v6_0_lock_cursor(crtc, true);
2221         ret = dce_v6_0_cursor_move_locked(crtc, x, y);
2222         dce_v6_0_lock_cursor(crtc, false);
2223
2224         return ret;
2225 }
2226
2227 static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc,
2228                                      struct drm_file *file_priv,
2229                                      uint32_t handle,
2230                                      uint32_t width,
2231                                      uint32_t height,
2232                                      int32_t hot_x,
2233                                      int32_t hot_y)
2234 {
2235         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2236         struct drm_gem_object *obj;
2237         struct amdgpu_bo *aobj;
2238         int ret;
2239
2240         if (!handle) {
2241                 /* turn off cursor */
2242                 dce_v6_0_hide_cursor(crtc);
2243                 obj = NULL;
2244                 goto unpin;
2245         }
2246
2247         if ((width > amdgpu_crtc->max_cursor_width) ||
2248             (height > amdgpu_crtc->max_cursor_height)) {
2249                 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2250                 return -EINVAL;
2251         }
2252
2253         obj = drm_gem_object_lookup(file_priv, handle);
2254         if (!obj) {
2255                 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2256                 return -ENOENT;
2257         }
2258
2259         aobj = gem_to_amdgpu_bo(obj);
2260         ret = amdgpu_bo_reserve(aobj, false);
2261         if (ret != 0) {
2262                 drm_gem_object_put_unlocked(obj);
2263                 return ret;
2264         }
2265
2266         ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2267         amdgpu_bo_unreserve(aobj);
2268         if (ret) {
2269                 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2270                 drm_gem_object_put_unlocked(obj);
2271                 return ret;
2272         }
2273
2274         dce_v6_0_lock_cursor(crtc, true);
2275
2276         if (width != amdgpu_crtc->cursor_width ||
2277             height != amdgpu_crtc->cursor_height ||
2278             hot_x != amdgpu_crtc->cursor_hot_x ||
2279             hot_y != amdgpu_crtc->cursor_hot_y) {
2280                 int x, y;
2281
2282                 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2283                 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2284
2285                 dce_v6_0_cursor_move_locked(crtc, x, y);
2286
2287                 amdgpu_crtc->cursor_width = width;
2288                 amdgpu_crtc->cursor_height = height;
2289                 amdgpu_crtc->cursor_hot_x = hot_x;
2290                 amdgpu_crtc->cursor_hot_y = hot_y;
2291         }
2292
2293         dce_v6_0_show_cursor(crtc);
2294         dce_v6_0_lock_cursor(crtc, false);
2295
2296 unpin:
2297         if (amdgpu_crtc->cursor_bo) {
2298                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2299                 ret = amdgpu_bo_reserve(aobj, true);
2300                 if (likely(ret == 0)) {
2301                         amdgpu_bo_unpin(aobj);
2302                         amdgpu_bo_unreserve(aobj);
2303                 }
2304                 drm_gem_object_put_unlocked(amdgpu_crtc->cursor_bo);
2305         }
2306
2307         amdgpu_crtc->cursor_bo = obj;
2308         return 0;
2309 }
2310
2311 static void dce_v6_0_cursor_reset(struct drm_crtc *crtc)
2312 {
2313         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2314
2315         if (amdgpu_crtc->cursor_bo) {
2316                 dce_v6_0_lock_cursor(crtc, true);
2317
2318                 dce_v6_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2319                                             amdgpu_crtc->cursor_y);
2320
2321                 dce_v6_0_show_cursor(crtc);
2322                 dce_v6_0_lock_cursor(crtc, false);
2323         }
2324 }
2325
2326 static int dce_v6_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2327                                    u16 *blue, uint32_t size,
2328                                    struct drm_modeset_acquire_ctx *ctx)
2329 {
2330         dce_v6_0_crtc_load_lut(crtc);
2331
2332         return 0;
2333 }
2334
2335 static void dce_v6_0_crtc_destroy(struct drm_crtc *crtc)
2336 {
2337         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2338
2339         drm_crtc_cleanup(crtc);
2340         kfree(amdgpu_crtc);
2341 }
2342
2343 static const struct drm_crtc_funcs dce_v6_0_crtc_funcs = {
2344         .cursor_set2 = dce_v6_0_crtc_cursor_set2,
2345         .cursor_move = dce_v6_0_crtc_cursor_move,
2346         .gamma_set = dce_v6_0_crtc_gamma_set,
2347         .set_config = amdgpu_display_crtc_set_config,
2348         .destroy = dce_v6_0_crtc_destroy,
2349         .page_flip_target = amdgpu_display_crtc_page_flip_target,
2350 };
2351
2352 static void dce_v6_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2353 {
2354         struct drm_device *dev = crtc->dev;
2355         struct amdgpu_device *adev = dev->dev_private;
2356         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2357         unsigned type;
2358
2359         switch (mode) {
2360         case DRM_MODE_DPMS_ON:
2361                 amdgpu_crtc->enabled = true;
2362                 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2363                 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2364                 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2365                 type = amdgpu_display_crtc_idx_to_irq_type(adev,
2366                                                 amdgpu_crtc->crtc_id);
2367                 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2368                 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2369                 drm_crtc_vblank_on(crtc);
2370                 dce_v6_0_crtc_load_lut(crtc);
2371                 break;
2372         case DRM_MODE_DPMS_STANDBY:
2373         case DRM_MODE_DPMS_SUSPEND:
2374         case DRM_MODE_DPMS_OFF:
2375                 drm_crtc_vblank_off(crtc);
2376                 if (amdgpu_crtc->enabled)
2377                         amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2378                 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2379                 amdgpu_crtc->enabled = false;
2380                 break;
2381         }
2382         /* adjust pm to dpms */
2383         amdgpu_pm_compute_clocks(adev);
2384 }
2385
2386 static void dce_v6_0_crtc_prepare(struct drm_crtc *crtc)
2387 {
2388         /* disable crtc pair power gating before programming */
2389         amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2390         amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2391         dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2392 }
2393
2394 static void dce_v6_0_crtc_commit(struct drm_crtc *crtc)
2395 {
2396         dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2397         amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2398 }
2399
2400 static void dce_v6_0_crtc_disable(struct drm_crtc *crtc)
2401 {
2402
2403         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2404         struct drm_device *dev = crtc->dev;
2405         struct amdgpu_device *adev = dev->dev_private;
2406         struct amdgpu_atom_ss ss;
2407         int i;
2408
2409         dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2410         if (crtc->primary->fb) {
2411                 int r;
2412                 struct amdgpu_bo *abo;
2413
2414                 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
2415                 r = amdgpu_bo_reserve(abo, true);
2416                 if (unlikely(r))
2417                         DRM_ERROR("failed to reserve abo before unpin\n");
2418                 else {
2419                         amdgpu_bo_unpin(abo);
2420                         amdgpu_bo_unreserve(abo);
2421                 }
2422         }
2423         /* disable the GRPH */
2424         dce_v6_0_grph_enable(crtc, false);
2425
2426         amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2427
2428         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2429                 if (adev->mode_info.crtcs[i] &&
2430                     adev->mode_info.crtcs[i]->enabled &&
2431                     i != amdgpu_crtc->crtc_id &&
2432                     amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2433                         /* one other crtc is using this pll don't turn
2434                          * off the pll
2435                          */
2436                         goto done;
2437                 }
2438         }
2439
2440         switch (amdgpu_crtc->pll_id) {
2441         case ATOM_PPLL1:
2442         case ATOM_PPLL2:
2443                 /* disable the ppll */
2444                 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2445                                                  0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2446                 break;
2447         default:
2448                 break;
2449         }
2450 done:
2451         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2452         amdgpu_crtc->adjusted_clock = 0;
2453         amdgpu_crtc->encoder = NULL;
2454         amdgpu_crtc->connector = NULL;
2455 }
2456
2457 static int dce_v6_0_crtc_mode_set(struct drm_crtc *crtc,
2458                                   struct drm_display_mode *mode,
2459                                   struct drm_display_mode *adjusted_mode,
2460                                   int x, int y, struct drm_framebuffer *old_fb)
2461 {
2462         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2463
2464         if (!amdgpu_crtc->adjusted_clock)
2465                 return -EINVAL;
2466
2467         amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2468         amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2469         dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2470         amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2471         amdgpu_atombios_crtc_scaler_setup(crtc);
2472         dce_v6_0_cursor_reset(crtc);
2473         /* update the hw version fpr dpm */
2474         amdgpu_crtc->hw_mode = *adjusted_mode;
2475
2476         return 0;
2477 }
2478
2479 static bool dce_v6_0_crtc_mode_fixup(struct drm_crtc *crtc,
2480                                      const struct drm_display_mode *mode,
2481                                      struct drm_display_mode *adjusted_mode)
2482 {
2483
2484         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2485         struct drm_device *dev = crtc->dev;
2486         struct drm_encoder *encoder;
2487
2488         /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2489         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2490                 if (encoder->crtc == crtc) {
2491                         amdgpu_crtc->encoder = encoder;
2492                         amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2493                         break;
2494                 }
2495         }
2496         if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2497                 amdgpu_crtc->encoder = NULL;
2498                 amdgpu_crtc->connector = NULL;
2499                 return false;
2500         }
2501         if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2502                 return false;
2503         if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2504                 return false;
2505         /* pick pll */
2506         amdgpu_crtc->pll_id = dce_v6_0_pick_pll(crtc);
2507         /* if we can't get a PPLL for a non-DP encoder, fail */
2508         if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2509             !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2510                 return false;
2511
2512         return true;
2513 }
2514
2515 static int dce_v6_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2516                                   struct drm_framebuffer *old_fb)
2517 {
2518         return dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2519 }
2520
2521 static int dce_v6_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2522                                          struct drm_framebuffer *fb,
2523                                          int x, int y, enum mode_set_atomic state)
2524 {
2525        return dce_v6_0_crtc_do_set_base(crtc, fb, x, y, 1);
2526 }
2527
2528 static const struct drm_crtc_helper_funcs dce_v6_0_crtc_helper_funcs = {
2529         .dpms = dce_v6_0_crtc_dpms,
2530         .mode_fixup = dce_v6_0_crtc_mode_fixup,
2531         .mode_set = dce_v6_0_crtc_mode_set,
2532         .mode_set_base = dce_v6_0_crtc_set_base,
2533         .mode_set_base_atomic = dce_v6_0_crtc_set_base_atomic,
2534         .prepare = dce_v6_0_crtc_prepare,
2535         .commit = dce_v6_0_crtc_commit,
2536         .disable = dce_v6_0_crtc_disable,
2537 };
2538
2539 static int dce_v6_0_crtc_init(struct amdgpu_device *adev, int index)
2540 {
2541         struct amdgpu_crtc *amdgpu_crtc;
2542
2543         amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2544                               (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2545         if (amdgpu_crtc == NULL)
2546                 return -ENOMEM;
2547
2548         drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v6_0_crtc_funcs);
2549
2550         drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2551         amdgpu_crtc->crtc_id = index;
2552         adev->mode_info.crtcs[index] = amdgpu_crtc;
2553
2554         amdgpu_crtc->max_cursor_width = CURSOR_WIDTH;
2555         amdgpu_crtc->max_cursor_height = CURSOR_HEIGHT;
2556         adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2557         adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2558
2559         amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];
2560
2561         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2562         amdgpu_crtc->adjusted_clock = 0;
2563         amdgpu_crtc->encoder = NULL;
2564         amdgpu_crtc->connector = NULL;
2565         drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v6_0_crtc_helper_funcs);
2566
2567         return 0;
2568 }
2569
2570 static int dce_v6_0_early_init(void *handle)
2571 {
2572         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2573
2574         adev->audio_endpt_rreg = &dce_v6_0_audio_endpt_rreg;
2575         adev->audio_endpt_wreg = &dce_v6_0_audio_endpt_wreg;
2576
2577         dce_v6_0_set_display_funcs(adev);
2578
2579         adev->mode_info.num_crtc = dce_v6_0_get_num_crtc(adev);
2580
2581         switch (adev->asic_type) {
2582         case CHIP_TAHITI:
2583         case CHIP_PITCAIRN:
2584         case CHIP_VERDE:
2585                 adev->mode_info.num_hpd = 6;
2586                 adev->mode_info.num_dig = 6;
2587                 break;
2588         case CHIP_OLAND:
2589                 adev->mode_info.num_hpd = 2;
2590                 adev->mode_info.num_dig = 2;
2591                 break;
2592         default:
2593                 return -EINVAL;
2594         }
2595
2596         dce_v6_0_set_irq_funcs(adev);
2597
2598         return 0;
2599 }
2600
2601 static int dce_v6_0_sw_init(void *handle)
2602 {
2603         int r, i;
2604         bool ret;
2605         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2606
2607         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2608                 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2609                 if (r)
2610                         return r;
2611         }
2612
2613         for (i = 8; i < 20; i += 2) {
2614                 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2615                 if (r)
2616                         return r;
2617         }
2618
2619         /* HPD hotplug */
2620         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq);
2621         if (r)
2622                 return r;
2623
2624         adev->mode_info.mode_config_initialized = true;
2625
2626         adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2627         adev->ddev->mode_config.async_page_flip = true;
2628         adev->ddev->mode_config.max_width = 16384;
2629         adev->ddev->mode_config.max_height = 16384;
2630         adev->ddev->mode_config.preferred_depth = 24;
2631         adev->ddev->mode_config.prefer_shadow = 1;
2632         adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
2633
2634         r = amdgpu_display_modeset_create_props(adev);
2635         if (r)
2636                 return r;
2637
2638         adev->ddev->mode_config.max_width = 16384;
2639         adev->ddev->mode_config.max_height = 16384;
2640
2641         /* allocate crtcs */
2642         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2643                 r = dce_v6_0_crtc_init(adev, i);
2644                 if (r)
2645                         return r;
2646         }
2647
2648         ret = amdgpu_atombios_get_connector_info_from_object_table(adev);
2649         if (ret)
2650                 amdgpu_display_print_display_setup(adev->ddev);
2651         else
2652                 return -EINVAL;
2653
2654         /* setup afmt */
2655         r = dce_v6_0_afmt_init(adev);
2656         if (r)
2657                 return r;
2658
2659         r = dce_v6_0_audio_init(adev);
2660         if (r)
2661                 return r;
2662
2663         drm_kms_helper_poll_init(adev->ddev);
2664
2665         return r;
2666 }
2667
2668 static int dce_v6_0_sw_fini(void *handle)
2669 {
2670         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2671
2672         kfree(adev->mode_info.bios_hardcoded_edid);
2673
2674         drm_kms_helper_poll_fini(adev->ddev);
2675
2676         dce_v6_0_audio_fini(adev);
2677         dce_v6_0_afmt_fini(adev);
2678
2679         drm_mode_config_cleanup(adev->ddev);
2680         adev->mode_info.mode_config_initialized = false;
2681
2682         return 0;
2683 }
2684
2685 static int dce_v6_0_hw_init(void *handle)
2686 {
2687         int i;
2688         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2689
2690         /* disable vga render */
2691         dce_v6_0_set_vga_render_state(adev, false);
2692         /* init dig PHYs, disp eng pll */
2693         amdgpu_atombios_encoder_init_dig(adev);
2694         amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2695
2696         /* initialize hpd */
2697         dce_v6_0_hpd_init(adev);
2698
2699         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2700                 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2701         }
2702
2703         dce_v6_0_pageflip_interrupt_init(adev);
2704
2705         return 0;
2706 }
2707
2708 static int dce_v6_0_hw_fini(void *handle)
2709 {
2710         int i;
2711         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2712
2713         dce_v6_0_hpd_fini(adev);
2714
2715         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2716                 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2717         }
2718
2719         dce_v6_0_pageflip_interrupt_fini(adev);
2720
2721         return 0;
2722 }
2723
2724 static int dce_v6_0_suspend(void *handle)
2725 {
2726         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2727
2728         adev->mode_info.bl_level =
2729                 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
2730
2731         return dce_v6_0_hw_fini(handle);
2732 }
2733
2734 static int dce_v6_0_resume(void *handle)
2735 {
2736         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2737         int ret;
2738
2739         amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
2740                                                            adev->mode_info.bl_level);
2741
2742         ret = dce_v6_0_hw_init(handle);
2743
2744         /* turn on the BL */
2745         if (adev->mode_info.bl_encoder) {
2746                 u8 bl_level = amdgpu_display_backlight_get_level(adev,
2747                                                                   adev->mode_info.bl_encoder);
2748                 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
2749                                                     bl_level);
2750         }
2751
2752         return ret;
2753 }
2754
2755 static bool dce_v6_0_is_idle(void *handle)
2756 {
2757         return true;
2758 }
2759
2760 static int dce_v6_0_wait_for_idle(void *handle)
2761 {
2762         return 0;
2763 }
2764
2765 static int dce_v6_0_soft_reset(void *handle)
2766 {
2767         DRM_INFO("xxxx: dce_v6_0_soft_reset --- no impl!!\n");
2768         return 0;
2769 }
2770
2771 static void dce_v6_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
2772                                                      int crtc,
2773                                                      enum amdgpu_interrupt_state state)
2774 {
2775         u32 reg_block, interrupt_mask;
2776
2777         if (crtc >= adev->mode_info.num_crtc) {
2778                 DRM_DEBUG("invalid crtc %d\n", crtc);
2779                 return;
2780         }
2781
2782         switch (crtc) {
2783         case 0:
2784                 reg_block = SI_CRTC0_REGISTER_OFFSET;
2785                 break;
2786         case 1:
2787                 reg_block = SI_CRTC1_REGISTER_OFFSET;
2788                 break;
2789         case 2:
2790                 reg_block = SI_CRTC2_REGISTER_OFFSET;
2791                 break;
2792         case 3:
2793                 reg_block = SI_CRTC3_REGISTER_OFFSET;
2794                 break;
2795         case 4:
2796                 reg_block = SI_CRTC4_REGISTER_OFFSET;
2797                 break;
2798         case 5:
2799                 reg_block = SI_CRTC5_REGISTER_OFFSET;
2800                 break;
2801         default:
2802                 DRM_DEBUG("invalid crtc %d\n", crtc);
2803                 return;
2804         }
2805
2806         switch (state) {
2807         case AMDGPU_IRQ_STATE_DISABLE:
2808                 interrupt_mask = RREG32(mmINT_MASK + reg_block);
2809                 interrupt_mask &= ~VBLANK_INT_MASK;
2810                 WREG32(mmINT_MASK + reg_block, interrupt_mask);
2811                 break;
2812         case AMDGPU_IRQ_STATE_ENABLE:
2813                 interrupt_mask = RREG32(mmINT_MASK + reg_block);
2814                 interrupt_mask |= VBLANK_INT_MASK;
2815                 WREG32(mmINT_MASK + reg_block, interrupt_mask);
2816                 break;
2817         default:
2818                 break;
2819         }
2820 }
2821
2822 static void dce_v6_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
2823                                                     int crtc,
2824                                                     enum amdgpu_interrupt_state state)
2825 {
2826
2827 }
2828
2829 static int dce_v6_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
2830                                             struct amdgpu_irq_src *src,
2831                                             unsigned type,
2832                                             enum amdgpu_interrupt_state state)
2833 {
2834         u32 dc_hpd_int_cntl;
2835
2836         if (type >= adev->mode_info.num_hpd) {
2837                 DRM_DEBUG("invalid hdp %d\n", type);
2838                 return 0;
2839         }
2840
2841         switch (state) {
2842         case AMDGPU_IRQ_STATE_DISABLE:
2843                 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
2844                 dc_hpd_int_cntl &= ~DC_HPDx_INT_EN;
2845                 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
2846                 break;
2847         case AMDGPU_IRQ_STATE_ENABLE:
2848                 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
2849                 dc_hpd_int_cntl |= DC_HPDx_INT_EN;
2850                 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
2851                 break;
2852         default:
2853                 break;
2854         }
2855
2856         return 0;
2857 }
2858
2859 static int dce_v6_0_set_crtc_interrupt_state(struct amdgpu_device *adev,
2860                                              struct amdgpu_irq_src *src,
2861                                              unsigned type,
2862                                              enum amdgpu_interrupt_state state)
2863 {
2864         switch (type) {
2865         case AMDGPU_CRTC_IRQ_VBLANK1:
2866                 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 0, state);
2867                 break;
2868         case AMDGPU_CRTC_IRQ_VBLANK2:
2869                 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 1, state);
2870                 break;
2871         case AMDGPU_CRTC_IRQ_VBLANK3:
2872                 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 2, state);
2873                 break;
2874         case AMDGPU_CRTC_IRQ_VBLANK4:
2875                 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 3, state);
2876                 break;
2877         case AMDGPU_CRTC_IRQ_VBLANK5:
2878                 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 4, state);
2879                 break;
2880         case AMDGPU_CRTC_IRQ_VBLANK6:
2881                 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 5, state);
2882                 break;
2883         case AMDGPU_CRTC_IRQ_VLINE1:
2884                 dce_v6_0_set_crtc_vline_interrupt_state(adev, 0, state);
2885                 break;
2886         case AMDGPU_CRTC_IRQ_VLINE2:
2887                 dce_v6_0_set_crtc_vline_interrupt_state(adev, 1, state);
2888                 break;
2889         case AMDGPU_CRTC_IRQ_VLINE3:
2890                 dce_v6_0_set_crtc_vline_interrupt_state(adev, 2, state);
2891                 break;
2892         case AMDGPU_CRTC_IRQ_VLINE4:
2893                 dce_v6_0_set_crtc_vline_interrupt_state(adev, 3, state);
2894                 break;
2895         case AMDGPU_CRTC_IRQ_VLINE5:
2896                 dce_v6_0_set_crtc_vline_interrupt_state(adev, 4, state);
2897                 break;
2898         case AMDGPU_CRTC_IRQ_VLINE6:
2899                 dce_v6_0_set_crtc_vline_interrupt_state(adev, 5, state);
2900                 break;
2901         default:
2902                 break;
2903         }
2904         return 0;
2905 }
2906
2907 static int dce_v6_0_crtc_irq(struct amdgpu_device *adev,
2908                              struct amdgpu_irq_src *source,
2909                              struct amdgpu_iv_entry *entry)
2910 {
2911         unsigned crtc = entry->src_id - 1;
2912         uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
2913         unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev,
2914                                                                     crtc);
2915
2916         switch (entry->src_data[0]) {
2917         case 0: /* vblank */
2918                 if (disp_int & interrupt_status_offsets[crtc].vblank)
2919                         WREG32(mmVBLANK_STATUS + crtc_offsets[crtc], VBLANK_ACK);
2920                 else
2921                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
2922
2923                 if (amdgpu_irq_enabled(adev, source, irq_type)) {
2924                         drm_handle_vblank(adev->ddev, crtc);
2925                 }
2926                 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
2927                 break;
2928         case 1: /* vline */
2929                 if (disp_int & interrupt_status_offsets[crtc].vline)
2930                         WREG32(mmVLINE_STATUS + crtc_offsets[crtc], VLINE_ACK);
2931                 else
2932                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
2933
2934                 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
2935                 break;
2936         default:
2937                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
2938                 break;
2939         }
2940
2941         return 0;
2942 }
2943
2944 static int dce_v6_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
2945                                                  struct amdgpu_irq_src *src,
2946                                                  unsigned type,
2947                                                  enum amdgpu_interrupt_state state)
2948 {
2949         u32 reg;
2950
2951         if (type >= adev->mode_info.num_crtc) {
2952                 DRM_ERROR("invalid pageflip crtc %d\n", type);
2953                 return -EINVAL;
2954         }
2955
2956         reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
2957         if (state == AMDGPU_IRQ_STATE_DISABLE)
2958                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
2959                        reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
2960         else
2961                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
2962                        reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
2963
2964         return 0;
2965 }
2966
2967 static int dce_v6_0_pageflip_irq(struct amdgpu_device *adev,
2968                                  struct amdgpu_irq_src *source,
2969                                  struct amdgpu_iv_entry *entry)
2970 {
2971                 unsigned long flags;
2972         unsigned crtc_id;
2973         struct amdgpu_crtc *amdgpu_crtc;
2974         struct amdgpu_flip_work *works;
2975
2976         crtc_id = (entry->src_id - 8) >> 1;
2977         amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
2978
2979         if (crtc_id >= adev->mode_info.num_crtc) {
2980                 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
2981                 return -EINVAL;
2982         }
2983
2984         if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
2985             GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
2986                 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
2987                        GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
2988
2989         /* IRQ could occur when in initial stage */
2990         if (amdgpu_crtc == NULL)
2991                 return 0;
2992
2993         spin_lock_irqsave(&adev->ddev->event_lock, flags);
2994         works = amdgpu_crtc->pflip_works;
2995         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
2996                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
2997                                                 "AMDGPU_FLIP_SUBMITTED(%d)\n",
2998                                                 amdgpu_crtc->pflip_status,
2999                                                 AMDGPU_FLIP_SUBMITTED);
3000                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3001                 return 0;
3002         }
3003
3004         /* page flip completed. clean up */
3005         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3006         amdgpu_crtc->pflip_works = NULL;
3007
3008         /* wakeup usersapce */
3009         if (works->event)
3010                 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3011
3012         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3013
3014         drm_crtc_vblank_put(&amdgpu_crtc->base);
3015         schedule_work(&works->unpin_work);
3016
3017         return 0;
3018 }
3019
3020 static int dce_v6_0_hpd_irq(struct amdgpu_device *adev,
3021                             struct amdgpu_irq_src *source,
3022                             struct amdgpu_iv_entry *entry)
3023 {
3024         uint32_t disp_int, mask, tmp;
3025         unsigned hpd;
3026
3027         if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3028                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3029                 return 0;
3030         }
3031
3032         hpd = entry->src_data[0];
3033         disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3034         mask = interrupt_status_offsets[hpd].hpd;
3035
3036         if (disp_int & mask) {
3037                 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
3038                 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
3039                 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
3040                 schedule_work(&adev->hotplug_work);
3041                 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3042         }
3043
3044         return 0;
3045
3046 }
3047
3048 static int dce_v6_0_set_clockgating_state(void *handle,
3049                                           enum amd_clockgating_state state)
3050 {
3051         return 0;
3052 }
3053
3054 static int dce_v6_0_set_powergating_state(void *handle,
3055                                           enum amd_powergating_state state)
3056 {
3057         return 0;
3058 }
3059
3060 static const struct amd_ip_funcs dce_v6_0_ip_funcs = {
3061         .name = "dce_v6_0",
3062         .early_init = dce_v6_0_early_init,
3063         .late_init = NULL,
3064         .sw_init = dce_v6_0_sw_init,
3065         .sw_fini = dce_v6_0_sw_fini,
3066         .hw_init = dce_v6_0_hw_init,
3067         .hw_fini = dce_v6_0_hw_fini,
3068         .suspend = dce_v6_0_suspend,
3069         .resume = dce_v6_0_resume,
3070         .is_idle = dce_v6_0_is_idle,
3071         .wait_for_idle = dce_v6_0_wait_for_idle,
3072         .soft_reset = dce_v6_0_soft_reset,
3073         .set_clockgating_state = dce_v6_0_set_clockgating_state,
3074         .set_powergating_state = dce_v6_0_set_powergating_state,
3075 };
3076
3077 static void
3078 dce_v6_0_encoder_mode_set(struct drm_encoder *encoder,
3079                           struct drm_display_mode *mode,
3080                           struct drm_display_mode *adjusted_mode)
3081 {
3082
3083         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3084         int em = amdgpu_atombios_encoder_get_encoder_mode(encoder);
3085
3086         amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3087
3088         /* need to call this here rather than in prepare() since we need some crtc info */
3089         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3090
3091         /* set scaler clears this on some chips */
3092         dce_v6_0_set_interleave(encoder->crtc, mode);
3093
3094         if (em == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(em)) {
3095                 dce_v6_0_afmt_enable(encoder, true);
3096                 dce_v6_0_afmt_setmode(encoder, adjusted_mode);
3097         }
3098 }
3099
3100 static void dce_v6_0_encoder_prepare(struct drm_encoder *encoder)
3101 {
3102
3103         struct amdgpu_device *adev = encoder->dev->dev_private;
3104         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3105         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3106
3107         if ((amdgpu_encoder->active_device &
3108              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3109             (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3110              ENCODER_OBJECT_ID_NONE)) {
3111                 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3112                 if (dig) {
3113                         dig->dig_encoder = dce_v6_0_pick_dig_encoder(encoder);
3114                         if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3115                                 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3116                 }
3117         }
3118
3119         amdgpu_atombios_scratch_regs_lock(adev, true);
3120
3121         if (connector) {
3122                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3123
3124                 /* select the clock/data port if it uses a router */
3125                 if (amdgpu_connector->router.cd_valid)
3126                         amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3127
3128                 /* turn eDP panel on for mode set */
3129                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3130                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
3131                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
3132         }
3133
3134         /* this is needed for the pll/ss setup to work correctly in some cases */
3135         amdgpu_atombios_encoder_set_crtc_source(encoder);
3136         /* set up the FMT blocks */
3137         dce_v6_0_program_fmt(encoder);
3138 }
3139
3140 static void dce_v6_0_encoder_commit(struct drm_encoder *encoder)
3141 {
3142
3143         struct drm_device *dev = encoder->dev;
3144         struct amdgpu_device *adev = dev->dev_private;
3145
3146         /* need to call this here as we need the crtc set up */
3147         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3148         amdgpu_atombios_scratch_regs_lock(adev, false);
3149 }
3150
3151 static void dce_v6_0_encoder_disable(struct drm_encoder *encoder)
3152 {
3153
3154         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3155         struct amdgpu_encoder_atom_dig *dig;
3156         int em = amdgpu_atombios_encoder_get_encoder_mode(encoder);
3157
3158         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3159
3160         if (amdgpu_atombios_encoder_is_digital(encoder)) {
3161                 if (em == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(em))
3162                         dce_v6_0_afmt_enable(encoder, false);
3163                 dig = amdgpu_encoder->enc_priv;
3164                 dig->dig_encoder = -1;
3165         }
3166         amdgpu_encoder->active_device = 0;
3167 }
3168
3169 /* these are handled by the primary encoders */
3170 static void dce_v6_0_ext_prepare(struct drm_encoder *encoder)
3171 {
3172
3173 }
3174
3175 static void dce_v6_0_ext_commit(struct drm_encoder *encoder)
3176 {
3177
3178 }
3179
3180 static void
3181 dce_v6_0_ext_mode_set(struct drm_encoder *encoder,
3182                       struct drm_display_mode *mode,
3183                       struct drm_display_mode *adjusted_mode)
3184 {
3185
3186 }
3187
3188 static void dce_v6_0_ext_disable(struct drm_encoder *encoder)
3189 {
3190
3191 }
3192
3193 static void
3194 dce_v6_0_ext_dpms(struct drm_encoder *encoder, int mode)
3195 {
3196
3197 }
3198
3199 static bool dce_v6_0_ext_mode_fixup(struct drm_encoder *encoder,
3200                                     const struct drm_display_mode *mode,
3201                                     struct drm_display_mode *adjusted_mode)
3202 {
3203         return true;
3204 }
3205
3206 static const struct drm_encoder_helper_funcs dce_v6_0_ext_helper_funcs = {
3207         .dpms = dce_v6_0_ext_dpms,
3208         .mode_fixup = dce_v6_0_ext_mode_fixup,
3209         .prepare = dce_v6_0_ext_prepare,
3210         .mode_set = dce_v6_0_ext_mode_set,
3211         .commit = dce_v6_0_ext_commit,
3212         .disable = dce_v6_0_ext_disable,
3213         /* no detect for TMDS/LVDS yet */
3214 };
3215
3216 static const struct drm_encoder_helper_funcs dce_v6_0_dig_helper_funcs = {
3217         .dpms = amdgpu_atombios_encoder_dpms,
3218         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3219         .prepare = dce_v6_0_encoder_prepare,
3220         .mode_set = dce_v6_0_encoder_mode_set,
3221         .commit = dce_v6_0_encoder_commit,
3222         .disable = dce_v6_0_encoder_disable,
3223         .detect = amdgpu_atombios_encoder_dig_detect,
3224 };
3225
3226 static const struct drm_encoder_helper_funcs dce_v6_0_dac_helper_funcs = {
3227         .dpms = amdgpu_atombios_encoder_dpms,
3228         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3229         .prepare = dce_v6_0_encoder_prepare,
3230         .mode_set = dce_v6_0_encoder_mode_set,
3231         .commit = dce_v6_0_encoder_commit,
3232         .detect = amdgpu_atombios_encoder_dac_detect,
3233 };
3234
3235 static void dce_v6_0_encoder_destroy(struct drm_encoder *encoder)
3236 {
3237         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3238         if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3239                 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3240         kfree(amdgpu_encoder->enc_priv);
3241         drm_encoder_cleanup(encoder);
3242         kfree(amdgpu_encoder);
3243 }
3244
3245 static const struct drm_encoder_funcs dce_v6_0_encoder_funcs = {
3246         .destroy = dce_v6_0_encoder_destroy,
3247 };
3248
3249 static void dce_v6_0_encoder_add(struct amdgpu_device *adev,
3250                                  uint32_t encoder_enum,
3251                                  uint32_t supported_device,
3252                                  u16 caps)
3253 {
3254         struct drm_device *dev = adev->ddev;
3255         struct drm_encoder *encoder;
3256         struct amdgpu_encoder *amdgpu_encoder;
3257
3258         /* see if we already added it */
3259         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3260                 amdgpu_encoder = to_amdgpu_encoder(encoder);
3261                 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3262                         amdgpu_encoder->devices |= supported_device;
3263                         return;
3264                 }
3265
3266         }
3267
3268         /* add a new one */
3269         amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3270         if (!amdgpu_encoder)
3271                 return;
3272
3273         encoder = &amdgpu_encoder->base;
3274         switch (adev->mode_info.num_crtc) {
3275         case 1:
3276                 encoder->possible_crtcs = 0x1;
3277                 break;
3278         case 2:
3279         default:
3280                 encoder->possible_crtcs = 0x3;
3281                 break;
3282         case 4:
3283                 encoder->possible_crtcs = 0xf;
3284                 break;
3285         case 6:
3286                 encoder->possible_crtcs = 0x3f;
3287                 break;
3288         }
3289
3290         amdgpu_encoder->enc_priv = NULL;
3291         amdgpu_encoder->encoder_enum = encoder_enum;
3292         amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3293         amdgpu_encoder->devices = supported_device;
3294         amdgpu_encoder->rmx_type = RMX_OFF;
3295         amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3296         amdgpu_encoder->is_ext_encoder = false;
3297         amdgpu_encoder->caps = caps;
3298
3299         switch (amdgpu_encoder->encoder_id) {
3300         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3301         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3302                 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3303                                  DRM_MODE_ENCODER_DAC, NULL);
3304                 drm_encoder_helper_add(encoder, &dce_v6_0_dac_helper_funcs);
3305                 break;
3306         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3307         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3308         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3309         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3310         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3311                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3312                         amdgpu_encoder->rmx_type = RMX_FULL;
3313                         drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3314                                          DRM_MODE_ENCODER_LVDS, NULL);
3315                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3316                 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3317                         drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3318                                          DRM_MODE_ENCODER_DAC, NULL);
3319                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3320                 } else {
3321                         drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3322                                          DRM_MODE_ENCODER_TMDS, NULL);
3323                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3324                 }
3325                 drm_encoder_helper_add(encoder, &dce_v6_0_dig_helper_funcs);
3326                 break;
3327         case ENCODER_OBJECT_ID_SI170B:
3328         case ENCODER_OBJECT_ID_CH7303:
3329         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3330         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3331         case ENCODER_OBJECT_ID_TITFP513:
3332         case ENCODER_OBJECT_ID_VT1623:
3333         case ENCODER_OBJECT_ID_HDMI_SI1930:
3334         case ENCODER_OBJECT_ID_TRAVIS:
3335         case ENCODER_OBJECT_ID_NUTMEG:
3336                 /* these are handled by the primary encoders */
3337                 amdgpu_encoder->is_ext_encoder = true;
3338                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3339                         drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3340                                          DRM_MODE_ENCODER_LVDS, NULL);
3341                 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3342                         drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3343                                          DRM_MODE_ENCODER_DAC, NULL);
3344                 else
3345                         drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3346                                          DRM_MODE_ENCODER_TMDS, NULL);
3347                 drm_encoder_helper_add(encoder, &dce_v6_0_ext_helper_funcs);
3348                 break;
3349         }
3350 }
3351
3352 static const struct amdgpu_display_funcs dce_v6_0_display_funcs = {
3353         .bandwidth_update = &dce_v6_0_bandwidth_update,
3354         .vblank_get_counter = &dce_v6_0_vblank_get_counter,
3355         .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3356         .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3357         .hpd_sense = &dce_v6_0_hpd_sense,
3358         .hpd_set_polarity = &dce_v6_0_hpd_set_polarity,
3359         .hpd_get_gpio_reg = &dce_v6_0_hpd_get_gpio_reg,
3360         .page_flip = &dce_v6_0_page_flip,
3361         .page_flip_get_scanoutpos = &dce_v6_0_crtc_get_scanoutpos,
3362         .add_encoder = &dce_v6_0_encoder_add,
3363         .add_connector = &amdgpu_connector_add,
3364 };
3365
3366 static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev)
3367 {
3368         if (adev->mode_info.funcs == NULL)
3369                 adev->mode_info.funcs = &dce_v6_0_display_funcs;
3370 }
3371
3372 static const struct amdgpu_irq_src_funcs dce_v6_0_crtc_irq_funcs = {
3373         .set = dce_v6_0_set_crtc_interrupt_state,
3374         .process = dce_v6_0_crtc_irq,
3375 };
3376
3377 static const struct amdgpu_irq_src_funcs dce_v6_0_pageflip_irq_funcs = {
3378         .set = dce_v6_0_set_pageflip_interrupt_state,
3379         .process = dce_v6_0_pageflip_irq,
3380 };
3381
3382 static const struct amdgpu_irq_src_funcs dce_v6_0_hpd_irq_funcs = {
3383         .set = dce_v6_0_set_hpd_interrupt_state,
3384         .process = dce_v6_0_hpd_irq,
3385 };
3386
3387 static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev)
3388 {
3389         if (adev->mode_info.num_crtc > 0)
3390                 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
3391         else
3392                 adev->crtc_irq.num_types = 0;
3393         adev->crtc_irq.funcs = &dce_v6_0_crtc_irq_funcs;
3394
3395         adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
3396         adev->pageflip_irq.funcs = &dce_v6_0_pageflip_irq_funcs;
3397
3398         adev->hpd_irq.num_types = adev->mode_info.num_hpd;
3399         adev->hpd_irq.funcs = &dce_v6_0_hpd_irq_funcs;
3400 }
3401
3402 const struct amdgpu_ip_block_version dce_v6_0_ip_block =
3403 {
3404         .type = AMD_IP_BLOCK_TYPE_DCE,
3405         .major = 6,
3406         .minor = 0,
3407         .rev = 0,
3408         .funcs = &dce_v6_0_ip_funcs,
3409 };
3410
3411 const struct amdgpu_ip_block_version dce_v6_4_ip_block =
3412 {
3413         .type = AMD_IP_BLOCK_TYPE_DCE,
3414         .major = 6,
3415         .minor = 4,
3416         .rev = 0,
3417         .funcs = &dce_v6_0_ip_funcs,
3418 };