drivers/gpu/drm/amd/amdgpu/dce_v11_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <drm/drmP.h>
  24 #include "amdgpu.h"
  25 #include "amdgpu_pm.h"
  26 #include "amdgpu_i2c.h"
  27 #include "vid.h"
  28 #include "atom.h"
  29 #include "amdgpu_atombios.h"
  30 #include "atombios_crtc.h"
  31 #include "atombios_encoders.h"
  32 #include "amdgpu_pll.h"
  33 #include "amdgpu_connectors.h"
  34 #include "dce_v11_0.h"
  35
  36 #include "dce/dce_11_0_d.h"
  37 #include "dce/dce_11_0_sh_mask.h"
  38 #include "dce/dce_11_0_enum.h"
  39 #include "oss/oss_3_0_d.h"
  40 #include "oss/oss_3_0_sh_mask.h"
  41 #include "gmc/gmc_8_1_d.h"
  42 #include "gmc/gmc_8_1_sh_mask.h"
  43
  44 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
  45 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
  46
  47 static const u32 crtc_offsets[] =
  48 {
  49         CRTC0_REGISTER_OFFSET,
  50         CRTC1_REGISTER_OFFSET,
  51         CRTC2_REGISTER_OFFSET,
  52         CRTC3_REGISTER_OFFSET,
  53         CRTC4_REGISTER_OFFSET,
  54         CRTC5_REGISTER_OFFSET,
  55         CRTC6_REGISTER_OFFSET
  56 };
  57
  58 static const u32 hpd_offsets[] =
  59 {
  60         HPD0_REGISTER_OFFSET,
  61         HPD1_REGISTER_OFFSET,
  62         HPD2_REGISTER_OFFSET,
  63         HPD3_REGISTER_OFFSET,
  64         HPD4_REGISTER_OFFSET,
  65         HPD5_REGISTER_OFFSET
  66 };
  67
  68 static const uint32_t dig_offsets[] = {
  69         DIG0_REGISTER_OFFSET,
  70         DIG1_REGISTER_OFFSET,
  71         DIG2_REGISTER_OFFSET,
  72         DIG3_REGISTER_OFFSET,
  73         DIG4_REGISTER_OFFSET,
  74         DIG5_REGISTER_OFFSET,
  75         DIG6_REGISTER_OFFSET,
  76         DIG7_REGISTER_OFFSET,
  77         DIG8_REGISTER_OFFSET
  78 };
  79
  80 static const struct {
  81         uint32_t        reg;
  82         uint32_t        vblank;
  83         uint32_t        vline;
  84         uint32_t        hpd;
  85
  86 } interrupt_status_offsets[] = { {
  87         .reg = mmDISP_INTERRUPT_STATUS,
  88         .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
  89         .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
  90         .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
  91 }, {
  92         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
  93         .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
  94         .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
  95         .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
  96 }, {
  97         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
  98         .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
  99         .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
 100         .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
 101 }, {
 102         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
 103         .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
 104         .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
 105         .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
 106 }, {
 107         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
 108         .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
 109         .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
 110         .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
 111 }, {
 112         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
 113         .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
 114         .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
 115         .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
 116 } };
 117
 118 static const u32 cz_golden_settings_a11[] =
 119 {
 120         mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
 121         mmFBC_MISC, 0x1f311fff, 0x14300000,
 122 };
 123
 124 static const u32 cz_mgcg_cgcg_init[] =
 125 {
 126         mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
 127         mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
 128 };
 129
 130 static const u32 stoney_golden_settings_a11[] =
 131 {
 132         mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
 133         mmFBC_MISC, 0x1f311fff, 0x14302000,
 134 };
 135
 136 static const u32 polaris11_golden_settings_a11[] =
 137 {
 138         mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
 139         mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
 140         mmFBC_DEBUG1, 0xffffffff, 0x00000008,
 141         mmFBC_MISC, 0x9f313fff, 0x14302008,
 142         mmHDMI_CONTROL, 0x313f031f, 0x00000011,
 143 };
 144
 145 static const u32 polaris10_golden_settings_a11[] =
 146 {
 147         mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
 148         mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
 149         mmFBC_MISC, 0x9f313fff, 0x14302008,
 150         mmHDMI_CONTROL, 0x313f031f, 0x00000011,
 151 };
 152
 153 static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
 154 {
 155         switch (adev->asic_type) {
 156         case CHIP_CARRIZO:
 157                 amdgpu_device_program_register_sequence(adev,
 158                                                         cz_mgcg_cgcg_init,
 159                                                         ARRAY_SIZE(cz_mgcg_cgcg_init));
 160                 amdgpu_device_program_register_sequence(adev,
 161                                                         cz_golden_settings_a11,
 162                                                         ARRAY_SIZE(cz_golden_settings_a11));
 163                 break;
 164         case CHIP_STONEY:
 165                 amdgpu_device_program_register_sequence(adev,
 166                                                         stoney_golden_settings_a11,
 167                                                         ARRAY_SIZE(stoney_golden_settings_a11));
 168                 break;
 169         case CHIP_POLARIS11:
 170         case CHIP_POLARIS12:
 171                 amdgpu_device_program_register_sequence(adev,
 172                                                         polaris11_golden_settings_a11,
 173                                                         ARRAY_SIZE(polaris11_golden_settings_a11));
 174                 break;
 175         case CHIP_POLARIS10:
 176         case CHIP_VEGAM:
 177                 amdgpu_device_program_register_sequence(adev,
 178                                                         polaris10_golden_settings_a11,
 179                                                         ARRAY_SIZE(polaris10_golden_settings_a11));
 180                 break;
 181         default:
 182                 break;
 183         }
 184 }
 185
 186 static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,
 187                                      u32 block_offset, u32 reg)
 188 {
 189         unsigned long flags;
 190         u32 r;
 191
 192         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 193         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 194         r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
 195         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 196
 197         return r;
 198 }
 199
 200 static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev,
 201                                       u32 block_offset, u32 reg, u32 v)
 202 {
 203         unsigned long flags;
 204
 205         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 206         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 207         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
 208         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 209 }
 210
 211 static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 212 {
 213         if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
 214                 return 0;
 215         else
 216                 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
 217 }
 218
 219 static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev)
 220 {
 221         unsigned i;
 222
 223         /* Enable pflip interrupts */
 224         for (i = 0; i < adev->mode_info.num_crtc; i++)
 225                 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
 226 }
 227
 228 static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
 229 {
 230         unsigned i;
 231
 232         /* Disable pflip interrupts */
 233         for (i = 0; i < adev->mode_info.num_crtc; i++)
 234                 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
 235 }
 236
 237 /**
 238  * dce_v11_0_page_flip - pageflip callback.
 239  *
 240  * @adev: amdgpu_device pointer
 241  * @crtc_id: crtc to cleanup pageflip on
 242  * @crtc_base: new address of the crtc (GPU MC address)
 243  *
 244  * Triggers the actual pageflip by updating the primary
 245  * surface base address.
 246  */
 247 static void dce_v11_0_page_flip(struct amdgpu_device *adev,
 248                                 int crtc_id, u64 crtc_base, bool async)
 249 {
 250         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 251         u32 tmp;
 252
 253         /* flip immediate for async, default is vsync */
 254         tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
 255         tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
 256                             GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0);
 257         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 258         /* update the scanout addresses */
 259         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
 260                upper_32_bits(crtc_base));
 261         /* writing to the low address triggers the update */
 262         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
 263                lower_32_bits(crtc_base));
 264         /* post the write */
 265         RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
 266 }
 267
 268 static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 269                                         u32 *vbl, u32 *position)
 270 {
 271         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 272                 return -EINVAL;
 273
 274         *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
 275         *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 276
 277         return 0;
 278 }
 279
 280 /**
 281  * dce_v11_0_hpd_sense - hpd sense callback.
 282  *
 283  * @adev: amdgpu_device pointer
 284  * @hpd: hpd (hotplug detect) pin
 285  *
 286  * Checks if a digital monitor is connected (evergreen+).
 287  * Returns true if connected, false if not connected.
 288  */
 289 static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,
 290                                enum amdgpu_hpd_id hpd)
 291 {
 292         bool connected = false;
 293
 294         if (hpd >= adev->mode_info.num_hpd)
 295                 return connected;
 296
 297         if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
 298             DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
 299                 connected = true;
 300
 301         return connected;
 302 }
 303
 304 /**
 305  * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
 306  *
 307  * @adev: amdgpu_device pointer
 308  * @hpd: hpd (hotplug detect) pin
 309  *
 310  * Set the polarity of the hpd pin (evergreen+).
 311  */
 312 static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,
 313                                       enum amdgpu_hpd_id hpd)
 314 {
 315         u32 tmp;
 316         bool connected = dce_v11_0_hpd_sense(adev, hpd);
 317
 318         if (hpd >= adev->mode_info.num_hpd)
 319                 return;
 320
 321         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
 322         if (connected)
 323                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
 324         else
 325                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
 326         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
 327 }
 328
 329 /**
 330  * dce_v11_0_hpd_init - hpd setup callback.
 331  *
 332  * @adev: amdgpu_device pointer
 333  *
 334  * Setup the hpd pins used by the card (evergreen+).
 335  * Enable the pin, set the polarity, and enable the hpd interrupts.
 336  */
 337 static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
 338 {
 339         struct drm_device *dev = adev->ddev;
 340         struct drm_connector *connector;
 341         u32 tmp;
 342
 343         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 344                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 345
 346                 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
 347                         continue;
 348
 349                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 350                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 351                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 352                          * aux dp channel on imac and help (but not completely fix)
 353                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 354                          * also avoid interrupt storms during dpms.
 355                          */
 356                         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 357                         tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
 358                         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 359                         continue;
 360                 }
 361
 362                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 363                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
 364                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 365
 366                 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 367                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
 368                                     DC_HPD_CONNECT_INT_DELAY,
 369                                     AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
 370                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
 371                                     DC_HPD_DISCONNECT_INT_DELAY,
 372                                     AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
 373                 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 374
 375                 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
 376                 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 377         }
 378 }
 379
 380 /**
 381  * dce_v11_0_hpd_fini - hpd tear down callback.
 382  *
 383  * @adev: amdgpu_device pointer
 384  *
 385  * Tear down the hpd pins used by the card (evergreen+).
 386  * Disable the hpd interrupts.
 387  */
 388 static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
 389 {
 390         struct drm_device *dev = adev->ddev;
 391         struct drm_connector *connector;
 392         u32 tmp;
 393
 394         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 395                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 396
 397                 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
 398                         continue;
 399
 400                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 401                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
 402                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 403
 404                 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 405         }
 406 }
 407
 408 static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
 409 {
 410         return mmDC_GPIO_HPD_A;
 411 }
 412
 413 static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)
 414 {
 415         u32 crtc_hung = 0;
 416         u32 crtc_status[6];
 417         u32 i, j, tmp;
 418
 419         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 420                 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 421                 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
 422                         crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 423                         crtc_hung |= (1 << i);
 424                 }
 425         }
 426
 427         for (j = 0; j < 10; j++) {
 428                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
 429                         if (crtc_hung & (1 << i)) {
 430                                 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 431                                 if (tmp != crtc_status[i])
 432                                         crtc_hung &= ~(1 << i);
 433                         }
 434                 }
 435                 if (crtc_hung == 0)
 436                         return false;
 437                 udelay(100);
 438         }
 439
 440         return true;
 441 }
 442
 443 static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
 444                                            bool render)
 445 {
 446         u32 tmp;
 447
 448         /* Lockout access through VGA aperture*/
 449         tmp = RREG32(mmVGA_HDP_CONTROL);
 450         if (render)
 451                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
 452         else
 453                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 454         WREG32(mmVGA_HDP_CONTROL, tmp);
 455
 456         /* disable VGA render */
 457         tmp = RREG32(mmVGA_RENDER_CONTROL);
 458         if (render)
 459                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
 460         else
 461                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 462         WREG32(mmVGA_RENDER_CONTROL, tmp);
 463 }
 464
 465 static int dce_v11_0_get_num_crtc (struct amdgpu_device *adev)
 466 {
 467         int num_crtc = 0;
 468
 469         switch (adev->asic_type) {
 470         case CHIP_CARRIZO:
 471                 num_crtc = 3;
 472                 break;
 473         case CHIP_STONEY:
 474                 num_crtc = 2;
 475                 break;
 476         case CHIP_POLARIS10:
 477         case CHIP_VEGAM:
 478                 num_crtc = 6;
 479                 break;
 480         case CHIP_POLARIS11:
 481         case CHIP_POLARIS12:
 482                 num_crtc = 5;
 483                 break;
 484         default:
 485                 num_crtc = 0;
 486         }
 487         return num_crtc;
 488 }
 489
 490 void dce_v11_0_disable_dce(struct amdgpu_device *adev)
 491 {
 492         /*Disable VGA render and enabled crtc, if has DCE engine*/
 493         if (amdgpu_atombios_has_dce_engine_info(adev)) {
 494                 u32 tmp;
 495                 int crtc_enabled, i;
 496
 497                 dce_v11_0_set_vga_render_state(adev, false);
 498
 499                 /*Disable crtc*/
 500                 for (i = 0; i < dce_v11_0_get_num_crtc(adev); i++) {
 501                         crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
 502                                                                          CRTC_CONTROL, CRTC_MASTER_EN);
 503                         if (crtc_enabled) {
 504                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 505                                 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 506                                 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
 507                                 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
 508                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 509                         }
 510                 }
 511         }
 512 }
 513
 514 static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
 515 {
 516         struct drm_device *dev = encoder->dev;
 517         struct amdgpu_device *adev = dev->dev_private;
 518         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 519         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
 520         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
 521         int bpc = 0;
 522         u32 tmp = 0;
 523         enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
 524
 525         if (connector) {
 526                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 527                 bpc = amdgpu_connector_get_monitor_bpc(connector);
 528                 dither = amdgpu_connector->dither;
 529         }
 530
 531         /* LVDS/eDP FMT is set up by atom */
 532         if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 533                 return;
 534
 535         /* not needed for analog */
 536         if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
 537             (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
 538                 return;
 539
 540         if (bpc == 0)
 541                 return;
 542
 543         switch (bpc) {
 544         case 6:
 545                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 546                         /* XXX sort out optimal dither settings */
 547                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 548                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 549                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 550                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
 551                 } else {
 552                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 553                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
 554                 }
 555                 break;
 556         case 8:
 557                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 558                         /* XXX sort out optimal dither settings */
 559                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 560                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 561                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
 562                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 563                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
 564                 } else {
 565                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 566                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
 567                 }
 568                 break;
 569         case 10:
 570                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 571                         /* XXX sort out optimal dither settings */
 572                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 573                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 574                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
 575                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 576                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
 577                 } else {
 578                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 579                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
 580                 }
 581                 break;
 582         default:
 583                 /* not needed */
 584                 break;
 585         }
 586
 587         WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 588 }
 589
 590
 591 /* display watermark setup */
 592 /**
 593  * dce_v11_0_line_buffer_adjust - Set up the line buffer
 594  *
 595  * @adev: amdgpu_device pointer
 596  * @amdgpu_crtc: the selected display controller
 597  * @mode: the current display mode on the selected display
 598  * controller
 599  *
 600  * Setup up the line buffer allocation for
 601  * the selected display controller (CIK).
 602  * Returns the line buffer size in pixels.
 603  */
 604 static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
 605                                        struct amdgpu_crtc *amdgpu_crtc,
 606                                        struct drm_display_mode *mode)
 607 {
 608         u32 tmp, buffer_alloc, i, mem_cfg;
 609         u32 pipe_offset = amdgpu_crtc->crtc_id;
 610         /*
 611          * Line Buffer Setup
 612          * There are 6 line buffers, one for each display controllers.
 613          * There are 3 partitions per LB. Select the number of partitions
 614          * to enable based on the display width.  For display widths larger
 615          * than 4096, you need use to use 2 display controllers and combine
 616          * them using the stereo blender.
 617          */
 618         if (amdgpu_crtc->base.enabled && mode) {
 619                 if (mode->crtc_hdisplay < 1920) {
 620                         mem_cfg = 1;
 621                         buffer_alloc = 2;
 622                 } else if (mode->crtc_hdisplay < 2560) {
 623                         mem_cfg = 2;
 624                         buffer_alloc = 2;
 625                 } else if (mode->crtc_hdisplay < 4096) {
 626                         mem_cfg = 0;
 627                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 628                 } else {
 629                         DRM_DEBUG_KMS("Mode too big for LB!\n");
 630                         mem_cfg = 0;
 631                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 632                 }
 633         } else {
 634                 mem_cfg = 1;
 635                 buffer_alloc = 0;
 636         }
 637
 638         tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
 639         tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
 640         WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
 641
 642         tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
 643         tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
 644         WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
 645
 646         for (i = 0; i < adev->usec_timeout; i++) {
 647                 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
 648                 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
 649                         break;
 650                 udelay(1);
 651         }
 652
 653         if (amdgpu_crtc->base.enabled && mode) {
 654                 switch (mem_cfg) {
 655                 case 0:
 656                 default:
 657                         return 4096 * 2;
 658                 case 1:
 659                         return 1920 * 2;
 660                 case 2:
 661                         return 2560 * 2;
 662                 }
 663         }
 664
 665         /* controller not enabled, so no lb used */
 666         return 0;
 667 }
 668
 669 /**
 670  * cik_get_number_of_dram_channels - get the number of dram channels
 671  *
 672  * @adev: amdgpu_device pointer
 673  *
 674  * Look up the number of video ram channels (CIK).
 675  * Used for display watermark bandwidth calculations
 676  * Returns the number of dram channels
 677  */
 678 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
 679 {
 680         u32 tmp = RREG32(mmMC_SHARED_CHMAP);
 681
 682         switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 683         case 0:
 684         default:
 685                 return 1;
 686         case 1:
 687                 return 2;
 688         case 2:
 689                 return 4;
 690         case 3:
 691                 return 8;
 692         case 4:
 693                 return 3;
 694         case 5:
 695                 return 6;
 696         case 6:
 697                 return 10;
 698         case 7:
 699                 return 12;
 700         case 8:
 701                 return 16;
 702         }
 703 }
 704
 705 struct dce10_wm_params {
 706         u32 dram_channels; /* number of dram channels */
 707         u32 yclk;          /* bandwidth per dram data pin in kHz */
 708         u32 sclk;          /* engine clock in kHz */
 709         u32 disp_clk;      /* display clock in kHz */
 710         u32 src_width;     /* viewport width */
 711         u32 active_time;   /* active display time in ns */
 712         u32 blank_time;    /* blank time in ns */
 713         bool interlaced;    /* mode is interlaced */
 714         fixed20_12 vsc;    /* vertical scale ratio */
 715         u32 num_heads;     /* number of active crtcs */
 716         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 717         u32 lb_size;       /* line buffer allocated to pipe */
 718         u32 vtaps;         /* vertical scaler taps */
 719 };
 720
 721 /**
 722  * dce_v11_0_dram_bandwidth - get the dram bandwidth
 723  *
 724  * @wm: watermark calculation data
 725  *
 726  * Calculate the raw dram bandwidth (CIK).
 727  * Used for display watermark bandwidth calculations
 728  * Returns the dram bandwidth in MBytes/s
 729  */
 730 static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)
 731 {
 732         /* Calculate raw DRAM Bandwidth */
 733         fixed20_12 dram_efficiency; /* 0.7 */
 734         fixed20_12 yclk, dram_channels, bandwidth;
 735         fixed20_12 a;
 736
 737         a.full = dfixed_const(1000);
 738         yclk.full = dfixed_const(wm->yclk);
 739         yclk.full = dfixed_div(yclk, a);
 740         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 741         a.full = dfixed_const(10);
 742         dram_efficiency.full = dfixed_const(7);
 743         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 744         bandwidth.full = dfixed_mul(dram_channels, yclk);
 745         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 746
 747         return dfixed_trunc(bandwidth);
 748 }
 749
 750 /**
 751  * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
 752  *
 753  * @wm: watermark calculation data
 754  *
 755  * Calculate the dram bandwidth used for display (CIK).
 756  * Used for display watermark bandwidth calculations
 757  * Returns the dram bandwidth for display in MBytes/s
 758  */
 759 static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
 760 {
 761         /* Calculate DRAM Bandwidth and the part allocated to display. */
 762         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 763         fixed20_12 yclk, dram_channels, bandwidth;
 764         fixed20_12 a;
 765
 766         a.full = dfixed_const(1000);
 767         yclk.full = dfixed_const(wm->yclk);
 768         yclk.full = dfixed_div(yclk, a);
 769         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 770         a.full = dfixed_const(10);
 771         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 772         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 773         bandwidth.full = dfixed_mul(dram_channels, yclk);
 774         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 775
 776         return dfixed_trunc(bandwidth);
 777 }
 778
 779 /**
 780  * dce_v11_0_data_return_bandwidth - get the data return bandwidth
 781  *
 782  * @wm: watermark calculation data
 783  *
 784  * Calculate the data return bandwidth used for display (CIK).
 785  * Used for display watermark bandwidth calculations
 786  * Returns the data return bandwidth in MBytes/s
 787  */
 788 static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)
 789 {
 790         /* Calculate the display Data return Bandwidth */
 791         fixed20_12 return_efficiency; /* 0.8 */
 792         fixed20_12 sclk, bandwidth;
 793         fixed20_12 a;
 794
 795         a.full = dfixed_const(1000);
 796         sclk.full = dfixed_const(wm->sclk);
 797         sclk.full = dfixed_div(sclk, a);
 798         a.full = dfixed_const(10);
 799         return_efficiency.full = dfixed_const(8);
 800         return_efficiency.full = dfixed_div(return_efficiency, a);
 801         a.full = dfixed_const(32);
 802         bandwidth.full = dfixed_mul(a, sclk);
 803         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 804
 805         return dfixed_trunc(bandwidth);
 806 }
 807
 808 /**
 809  * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
 810  *
 811  * @wm: watermark calculation data
 812  *
 813  * Calculate the dmif bandwidth used for display (CIK).
 814  * Used for display watermark bandwidth calculations
 815  * Returns the dmif bandwidth in MBytes/s
 816  */
 817 static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
 818 {
 819         /* Calculate the DMIF Request Bandwidth */
 820         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 821         fixed20_12 disp_clk, bandwidth;
 822         fixed20_12 a, b;
 823
 824         a.full = dfixed_const(1000);
 825         disp_clk.full = dfixed_const(wm->disp_clk);
 826         disp_clk.full = dfixed_div(disp_clk, a);
 827         a.full = dfixed_const(32);
 828         b.full = dfixed_mul(a, disp_clk);
 829
 830         a.full = dfixed_const(10);
 831         disp_clk_request_efficiency.full = dfixed_const(8);
 832         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
 833
 834         bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
 835
 836         return dfixed_trunc(bandwidth);
 837 }
 838
 839 /**
 840  * dce_v11_0_available_bandwidth - get the min available bandwidth
 841  *
 842  * @wm: watermark calculation data
 843  *
 844  * Calculate the min available bandwidth used for display (CIK).
 845  * Used for display watermark bandwidth calculations
 846  * Returns the min available bandwidth in MBytes/s
 847  */
 848 static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)
 849 {
 850         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
 851         u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);
 852         u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);
 853         u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);
 854
 855         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
 856 }
 857
 858 /**
 859  * dce_v11_0_average_bandwidth - get the average available bandwidth
 860  *
 861  * @wm: watermark calculation data
 862  *
 863  * Calculate the average available bandwidth used for display (CIK).
 864  * Used for display watermark bandwidth calculations
 865  * Returns the average available bandwidth in MBytes/s
 866  */
 867 static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)
 868 {
 869         /* Calculate the display mode Average Bandwidth
 870          * DisplayMode should contain the source and destination dimensions,
 871          * timing, etc.
 872          */
 873         fixed20_12 bpp;
 874         fixed20_12 line_time;
 875         fixed20_12 src_width;
 876         fixed20_12 bandwidth;
 877         fixed20_12 a;
 878
 879         a.full = dfixed_const(1000);
 880         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
 881         line_time.full = dfixed_div(line_time, a);
 882         bpp.full = dfixed_const(wm->bytes_per_pixel);
 883         src_width.full = dfixed_const(wm->src_width);
 884         bandwidth.full = dfixed_mul(src_width, bpp);
 885         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
 886         bandwidth.full = dfixed_div(bandwidth, line_time);
 887
 888         return dfixed_trunc(bandwidth);
 889 }
 890
 891 /**
 892  * dce_v11_0_latency_watermark - get the latency watermark
 893  *
 894  * @wm: watermark calculation data
 895  *
 896  * Calculate the latency watermark (CIK).
 897  * Used for display watermark bandwidth calculations
 898  * Returns the latency watermark in ns
 899  */
 900 static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
 901 {
 902         /* First calculate the latency in ns */
 903         u32 mc_latency = 2000; /* 2000 ns. */
 904         u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);
 905         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
 906         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
 907         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
 908         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
 909                 (wm->num_heads * cursor_line_pair_return_time);
 910         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
 911         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
 912         u32 tmp, dmif_size = 12288;
 913         fixed20_12 a, b, c;
 914
 915         if (wm->num_heads == 0)
 916                 return 0;
 917
 918         a.full = dfixed_const(2);
 919         b.full = dfixed_const(1);
 920         if ((wm->vsc.full > a.full) ||
 921             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
 922             (wm->vtaps >= 5) ||
 923             ((wm->vsc.full >= a.full) && wm->interlaced))
 924                 max_src_lines_per_dst_line = 4;
 925         else
 926                 max_src_lines_per_dst_line = 2;
 927
 928         a.full = dfixed_const(available_bandwidth);
 929         b.full = dfixed_const(wm->num_heads);
 930         a.full = dfixed_div(a, b);
 931         tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
 932         tmp = min(dfixed_trunc(a), tmp);
 933
 934         lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
 935
 936         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
 937         b.full = dfixed_const(1000);
 938         c.full = dfixed_const(lb_fill_bw);
 939         b.full = dfixed_div(c, b);
 940         a.full = dfixed_div(a, b);
 941         line_fill_time = dfixed_trunc(a);
 942
 943         if (line_fill_time < wm->active_time)
 944                 return latency;
 945         else
 946                 return latency + (line_fill_time - wm->active_time);
 947
 948 }
 949
 950 /**
 951  * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
 952  * average and available dram bandwidth
 953  *
 954  * @wm: watermark calculation data
 955  *
 956  * Check if the display average bandwidth fits in the display
 957  * dram bandwidth (CIK).
 958  * Used for display watermark bandwidth calculations
 959  * Returns true if the display fits, false if not.
 960  */
 961 static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
 962 {
 963         if (dce_v11_0_average_bandwidth(wm) <=
 964             (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
 965                 return true;
 966         else
 967                 return false;
 968 }
 969
 970 /**
 971  * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
 972  * average and available bandwidth
 973  *
 974  * @wm: watermark calculation data
 975  *
 976  * Check if the display average bandwidth fits in the display
 977  * available bandwidth (CIK).
 978  * Used for display watermark bandwidth calculations
 979  * Returns true if the display fits, false if not.
 980  */
 981 static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
 982 {
 983         if (dce_v11_0_average_bandwidth(wm) <=
 984             (dce_v11_0_available_bandwidth(wm) / wm->num_heads))
 985                 return true;
 986         else
 987                 return false;
 988 }
 989
 990 /**
 991  * dce_v11_0_check_latency_hiding - check latency hiding
 992  *
 993  * @wm: watermark calculation data
 994  *
 995  * Check latency hiding (CIK).
 996  * Used for display watermark bandwidth calculations
 997  * Returns true if the display fits, false if not.
 998  */
 999 static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm)
1000 {
1001         u32 lb_partitions = wm->lb_size / wm->src_width;
1002         u32 line_time = wm->active_time + wm->blank_time;
1003         u32 latency_tolerant_lines;
1004         u32 latency_hiding;
1005         fixed20_12 a;
1006
1007         a.full = dfixed_const(1);
1008         if (wm->vsc.full > a.full)
1009                 latency_tolerant_lines = 1;
1010         else {
1011                 if (lb_partitions <= (wm->vtaps + 1))
1012                         latency_tolerant_lines = 1;
1013                 else
1014                         latency_tolerant_lines = 2;
1015         }
1016
1017         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1018
1019         if (dce_v11_0_latency_watermark(wm) <= latency_hiding)
1020                 return true;
1021         else
1022                 return false;
1023 }
1024
1025 /**
1026  * dce_v11_0_program_watermarks - program display watermarks
1027  *
1028  * @adev: amdgpu_device pointer
1029  * @amdgpu_crtc: the selected display controller
1030  * @lb_size: line buffer size
1031  * @num_heads: number of display controllers in use
1032  *
1033  * Calculate and program the display watermarks for the
1034  * selected display controller (CIK).
1035  */
1036 static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
1037                                         struct amdgpu_crtc *amdgpu_crtc,
1038                                         u32 lb_size, u32 num_heads)
1039 {
1040         struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1041         struct dce10_wm_params wm_low, wm_high;
1042         u32 active_time;
1043         u32 line_time = 0;
1044         u32 latency_watermark_a = 0, latency_watermark_b = 0;
1045         u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1046
1047         if (amdgpu_crtc->base.enabled && num_heads && mode) {
1048                 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
1049                                             (u32)mode->clock);
1050                 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
1051                                           (u32)mode->clock);
1052                 line_time = min(line_time, (u32)65535);
1053
1054                 /* watermark for high clocks */
1055                 if (adev->pm.dpm_enabled) {
1056                         wm_high.yclk =
1057                                 amdgpu_dpm_get_mclk(adev, false) * 10;
1058                         wm_high.sclk =
1059                                 amdgpu_dpm_get_sclk(adev, false) * 10;
1060                 } else {
1061                         wm_high.yclk = adev->pm.current_mclk * 10;
1062                         wm_high.sclk = adev->pm.current_sclk * 10;
1063                 }
1064
1065                 wm_high.disp_clk = mode->clock;
1066                 wm_high.src_width = mode->crtc_hdisplay;
1067                 wm_high.active_time = active_time;
1068                 wm_high.blank_time = line_time - wm_high.active_time;
1069                 wm_high.interlaced = false;
1070                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1071                         wm_high.interlaced = true;
1072                 wm_high.vsc = amdgpu_crtc->vsc;
1073                 wm_high.vtaps = 1;
1074                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1075                         wm_high.vtaps = 2;
1076                 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1077                 wm_high.lb_size = lb_size;
1078                 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1079                 wm_high.num_heads = num_heads;
1080
1081                 /* set for high clocks */
1082                 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535);
1083
1084                 /* possibly force display priority to high */
1085                 /* should really do this at mode validation time... */
1086                 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1087                     !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1088                     !dce_v11_0_check_latency_hiding(&wm_high) ||
1089                     (adev->mode_info.disp_priority == 2)) {
1090                         DRM_DEBUG_KMS("force priority to high\n");
1091                 }
1092
1093                 /* watermark for low clocks */
1094                 if (adev->pm.dpm_enabled) {
1095                         wm_low.yclk =
1096                                 amdgpu_dpm_get_mclk(adev, true) * 10;
1097                         wm_low.sclk =
1098                                 amdgpu_dpm_get_sclk(adev, true) * 10;
1099                 } else {
1100                         wm_low.yclk = adev->pm.current_mclk * 10;
1101                         wm_low.sclk = adev->pm.current_sclk * 10;
1102                 }
1103
1104                 wm_low.disp_clk = mode->clock;
1105                 wm_low.src_width = mode->crtc_hdisplay;
1106                 wm_low.active_time = active_time;
1107                 wm_low.blank_time = line_time - wm_low.active_time;
1108                 wm_low.interlaced = false;
1109                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1110                         wm_low.interlaced = true;
1111                 wm_low.vsc = amdgpu_crtc->vsc;
1112                 wm_low.vtaps = 1;
1113                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1114                         wm_low.vtaps = 2;
1115                 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1116                 wm_low.lb_size = lb_size;
1117                 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1118                 wm_low.num_heads = num_heads;
1119
1120                 /* set for low clocks */
1121                 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535);
1122
1123                 /* possibly force display priority to high */
1124                 /* should really do this at mode validation time... */
1125                 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1126                     !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1127                     !dce_v11_0_check_latency_hiding(&wm_low) ||
1128                     (adev->mode_info.disp_priority == 2)) {
1129                         DRM_DEBUG_KMS("force priority to high\n");
1130                 }
1131                 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1132         }
1133
1134         /* select wm A */
1135         wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1136         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1137         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1138         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1139         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1140         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1141         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1142         /* select wm B */
1143         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1144         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1145         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1146         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1147         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1148         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1149         /* restore original selection */
1150         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1151
1152         /* save values for DPM */
1153         amdgpu_crtc->line_time = line_time;
1154         amdgpu_crtc->wm_high = latency_watermark_a;
1155         amdgpu_crtc->wm_low = latency_watermark_b;
1156         /* Save number of lines the linebuffer leads before the scanout */
1157         amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1158 }
1159
1160 /**
1161  * dce_v11_0_bandwidth_update - program display watermarks
1162  *
1163  * @adev: amdgpu_device pointer
1164  *
1165  * Calculate and program the display watermarks and line
1166  * buffer allocation (CIK).
1167  */
1168 static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)
1169 {
1170         struct drm_display_mode *mode = NULL;
1171         u32 num_heads = 0, lb_size;
1172         int i;
1173
1174         amdgpu_display_update_priority(adev);
1175
1176         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1177                 if (adev->mode_info.crtcs[i]->base.enabled)
1178                         num_heads++;
1179         }
1180         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1181                 mode = &adev->mode_info.crtcs[i]->base.mode;
1182                 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1183                 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1184                                             lb_size, num_heads);
1185         }
1186 }
1187
1188 static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev)
1189 {
1190         int i;
1191         u32 offset, tmp;
1192
1193         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1194                 offset = adev->mode_info.audio.pin[i].offset;
1195                 tmp = RREG32_AUDIO_ENDPT(offset,
1196                                          ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1197                 if (((tmp &
1198                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1199                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1200                         adev->mode_info.audio.pin[i].connected = false;
1201                 else
1202                         adev->mode_info.audio.pin[i].connected = true;
1203         }
1204 }
1205
1206 static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev)
1207 {
1208         int i;
1209
1210         dce_v11_0_audio_get_connected_pins(adev);
1211
1212         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1213                 if (adev->mode_info.audio.pin[i].connected)
1214                         return &adev->mode_info.audio.pin[i];
1215         }
1216         DRM_ERROR("No connected audio pins found!\n");
1217         return NULL;
1218 }
1219
1220 static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1221 {
1222         struct amdgpu_device *adev = encoder->dev->dev_private;
1223         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1224         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1225         u32 tmp;
1226
1227         if (!dig || !dig->afmt || !dig->afmt->pin)
1228                 return;
1229
1230         tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1231         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1232         WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1233 }
1234
1235 static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
1236                                                 struct drm_display_mode *mode)
1237 {
1238         struct amdgpu_device *adev = encoder->dev->dev_private;
1239         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1240         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1241         struct drm_connector *connector;
1242         struct amdgpu_connector *amdgpu_connector = NULL;
1243         u32 tmp;
1244         int interlace = 0;
1245
1246         if (!dig || !dig->afmt || !dig->afmt->pin)
1247                 return;
1248
1249         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1250                 if (connector->encoder == encoder) {
1251                         amdgpu_connector = to_amdgpu_connector(connector);
1252                         break;
1253                 }
1254         }
1255
1256         if (!amdgpu_connector) {
1257                 DRM_ERROR("Couldn't find encoder's connector\n");
1258                 return;
1259         }
1260
1261         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1262                 interlace = 1;
1263         if (connector->latency_present[interlace]) {
1264                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1265                                     VIDEO_LIPSYNC, connector->video_latency[interlace]);
1266                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1267                                     AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1268         } else {
1269                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1270                                     VIDEO_LIPSYNC, 0);
1271                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1272                                     AUDIO_LIPSYNC, 0);
1273         }
1274         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1275                            ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1276 }
1277
1278 static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1279 {
1280         struct amdgpu_device *adev = encoder->dev->dev_private;
1281         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1282         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1283         struct drm_connector *connector;
1284         struct amdgpu_connector *amdgpu_connector = NULL;
1285         u32 tmp;
1286         u8 *sadb = NULL;
1287         int sad_count;
1288
1289         if (!dig || !dig->afmt || !dig->afmt->pin)
1290                 return;
1291
1292         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1293                 if (connector->encoder == encoder) {
1294                         amdgpu_connector = to_amdgpu_connector(connector);
1295                         break;
1296                 }
1297         }
1298
1299         if (!amdgpu_connector) {
1300                 DRM_ERROR("Couldn't find encoder's connector\n");
1301                 return;
1302         }
1303
1304         sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1305         if (sad_count < 0) {
1306                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1307                 sad_count = 0;
1308         }
1309
1310         /* program the speaker allocation */
1311         tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1312                                  ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1313         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1314                             DP_CONNECTION, 0);
1315         /* set HDMI mode */
1316         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1317                             HDMI_CONNECTION, 1);
1318         if (sad_count)
1319                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1320                                     SPEAKER_ALLOCATION, sadb[0]);
1321         else
1322                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1323                                     SPEAKER_ALLOCATION, 5); /* stereo */
1324         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1325                            ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1326
1327         kfree(sadb);
1328 }
1329
1330 static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
1331 {
1332         struct amdgpu_device *adev = encoder->dev->dev_private;
1333         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1334         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1335         struct drm_connector *connector;
1336         struct amdgpu_connector *amdgpu_connector = NULL;
1337         struct cea_sad *sads;
1338         int i, sad_count;
1339
1340         static const u16 eld_reg_to_type[][2] = {
1341                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1342                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1343                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1344                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1345                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1346                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1347                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1348                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1349                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1350                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1351                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1352                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1353         };
1354
1355         if (!dig || !dig->afmt || !dig->afmt->pin)
1356                 return;
1357
1358         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1359                 if (connector->encoder == encoder) {
1360                         amdgpu_connector = to_amdgpu_connector(connector);
1361                         break;
1362                 }
1363         }
1364
1365         if (!amdgpu_connector) {
1366                 DRM_ERROR("Couldn't find encoder's connector\n");
1367                 return;
1368         }
1369
1370         sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1371         if (sad_count <= 0) {
1372                 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1373                 return;
1374         }
1375         BUG_ON(!sads);
1376
1377         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1378                 u32 tmp = 0;
1379                 u8 stereo_freqs = 0;
1380                 int max_channels = -1;
1381                 int j;
1382
1383                 for (j = 0; j < sad_count; j++) {
1384                         struct cea_sad *sad = &sads[j];
1385
1386                         if (sad->format == eld_reg_to_type[i][1]) {
1387                                 if (sad->channels > max_channels) {
1388                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1389                                                             MAX_CHANNELS, sad->channels);
1390                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1391                                                             DESCRIPTOR_BYTE_2, sad->byte2);
1392                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1393                                                             SUPPORTED_FREQUENCIES, sad->freq);
1394                                         max_channels = sad->channels;
1395                                 }
1396
1397                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1398                                         stereo_freqs |= sad->freq;
1399                                 else
1400                                         break;
1401                         }
1402                 }
1403
1404                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1405                                     SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1406                 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1407         }
1408
1409         kfree(sads);
1410 }
1411
1412 static void dce_v11_0_audio_enable(struct amdgpu_device *adev,
1413                                   struct amdgpu_audio_pin *pin,
1414                                   bool enable)
1415 {
1416         if (!pin)
1417                 return;
1418
1419         WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1420                            enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1421 }
1422
1423 static const u32 pin_offsets[] =
1424 {
1425         AUD0_REGISTER_OFFSET,
1426         AUD1_REGISTER_OFFSET,
1427         AUD2_REGISTER_OFFSET,
1428         AUD3_REGISTER_OFFSET,
1429         AUD4_REGISTER_OFFSET,
1430         AUD5_REGISTER_OFFSET,
1431         AUD6_REGISTER_OFFSET,
1432         AUD7_REGISTER_OFFSET,
1433 };
1434
1435 static int dce_v11_0_audio_init(struct amdgpu_device *adev)
1436 {
1437         int i;
1438
1439         if (!amdgpu_audio)
1440                 return 0;
1441
1442         adev->mode_info.audio.enabled = true;
1443
1444         switch (adev->asic_type) {
1445         case CHIP_CARRIZO:
1446         case CHIP_STONEY:
1447                 adev->mode_info.audio.num_pins = 7;
1448                 break;
1449         case CHIP_POLARIS10:
1450         case CHIP_VEGAM:
1451                 adev->mode_info.audio.num_pins = 8;
1452                 break;
1453         case CHIP_POLARIS11:
1454         case CHIP_POLARIS12:
1455                 adev->mode_info.audio.num_pins = 6;
1456                 break;
1457         default:
1458                 return -EINVAL;
1459         }
1460
1461         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1462                 adev->mode_info.audio.pin[i].channels = -1;
1463                 adev->mode_info.audio.pin[i].rate = -1;
1464                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1465                 adev->mode_info.audio.pin[i].status_bits = 0;
1466                 adev->mode_info.audio.pin[i].category_code = 0;
1467                 adev->mode_info.audio.pin[i].connected = false;
1468                 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1469                 adev->mode_info.audio.pin[i].id = i;
1470                 /* disable audio.  it will be set up later */
1471                 /* XXX remove once we switch to ip funcs */
1472                 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1473         }
1474
1475         return 0;
1476 }
1477
1478 static void dce_v11_0_audio_fini(struct amdgpu_device *adev)
1479 {
1480         int i;
1481
1482         if (!amdgpu_audio)
1483                 return;
1484
1485         if (!adev->mode_info.audio.enabled)
1486                 return;
1487
1488         for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1489                 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1490
1491         adev->mode_info.audio.enabled = false;
1492 }
1493
1494 /*
1495  * update the N and CTS parameters for a given pixel clock rate
1496  */
1497 static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1498 {
1499         struct drm_device *dev = encoder->dev;
1500         struct amdgpu_device *adev = dev->dev_private;
1501         struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1502         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1503         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1504         u32 tmp;
1505
1506         tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1507         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1508         WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1509         tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1510         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1511         WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1512
1513         tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1514         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1515         WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1516         tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1517         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1518         WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1519
1520         tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1521         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1522         WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1523         tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1524         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1525         WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1526
1527 }
1528
1529 /*
1530  * build a HDMI Video Info Frame
1531  */
1532 static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1533                                                void *buffer, size_t size)
1534 {
1535         struct drm_device *dev = encoder->dev;
1536         struct amdgpu_device *adev = dev->dev_private;
1537         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1538         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1539         uint8_t *frame = buffer + 3;
1540         uint8_t *header = buffer;
1541
1542         WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1543                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1544         WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1545                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1546         WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1547                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1548         WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1549                 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1550 }
1551
1552 static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1553 {
1554         struct drm_device *dev = encoder->dev;
1555         struct amdgpu_device *adev = dev->dev_private;
1556         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1557         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1558         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1559         u32 dto_phase = 24 * 1000;
1560         u32 dto_modulo = clock;
1561         u32 tmp;
1562
1563         if (!dig || !dig->afmt)
1564                 return;
1565
1566         /* XXX two dtos; generally use dto0 for hdmi */
1567         /* Express [24MHz / target pixel clock] as an exact rational
1568          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
1569          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1570          */
1571         tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1572         tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1573                             amdgpu_crtc->crtc_id);
1574         WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1575         WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1576         WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1577 }
1578
1579 /*
1580  * update the info frames with the data from the current display mode
1581  */
1582 static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder,
1583                                   struct drm_display_mode *mode)
1584 {
1585         struct drm_device *dev = encoder->dev;
1586         struct amdgpu_device *adev = dev->dev_private;
1587         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1588         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1589         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1590         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1591         struct hdmi_avi_infoframe frame;
1592         ssize_t err;
1593         u32 tmp;
1594         int bpc = 8;
1595
1596         if (!dig || !dig->afmt)
1597                 return;
1598
1599         /* Silent, r600_hdmi_enable will raise WARN for us */
1600         if (!dig->afmt->enabled)
1601                 return;
1602
1603         /* hdmi deep color mode general control packets setup, if bpc > 8 */
1604         if (encoder->crtc) {
1605                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1606                 bpc = amdgpu_crtc->bpc;
1607         }
1608
1609         /* disable audio prior to setting up hw */
1610         dig->afmt->pin = dce_v11_0_audio_get_pin(adev);
1611         dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1612
1613         dce_v11_0_audio_set_dto(encoder, mode->clock);
1614
1615         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1616         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1617         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1618
1619         WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1620
1621         tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1622         switch (bpc) {
1623         case 0:
1624         case 6:
1625         case 8:
1626         case 16:
1627         default:
1628                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1629                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1630                 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1631                           connector->name, bpc);
1632                 break;
1633         case 10:
1634                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1635                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1636                 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1637                           connector->name);
1638                 break;
1639         case 12:
1640                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1641                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1642                 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1643                           connector->name);
1644                 break;
1645         }
1646         WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1647
1648         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1649         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1650         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1651         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1652         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1653
1654         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1655         /* enable audio info frames (frames won't be set until audio is enabled) */
1656         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1657         /* required for audio info values to be updated */
1658         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1659         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1660
1661         tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1662         /* required for audio info values to be updated */
1663         tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1664         WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1665
1666         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1667         /* anything other than 0 */
1668         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1669         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1670
1671         WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1672
1673         tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1674         /* set the default audio delay */
1675         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1676         /* should be suffient for all audio modes and small enough for all hblanks */
1677         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1678         WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1679
1680         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1681         /* allow 60958 channel status fields to be updated */
1682         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1683         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1684
1685         tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1686         if (bpc > 8)
1687                 /* clear SW CTS value */
1688                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1689         else
1690                 /* select SW CTS value */
1691                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1692         /* allow hw to sent ACR packets when required */
1693         tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1694         WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1695
1696         dce_v11_0_afmt_update_ACR(encoder, mode->clock);
1697
1698         tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1699         tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1700         WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1701
1702         tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1703         tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1704         WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1705
1706         tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1707         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1708         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1709         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1710         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1711         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1712         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1713         WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1714
1715         dce_v11_0_audio_write_speaker_allocation(encoder);
1716
1717         WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1718                (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1719
1720         dce_v11_0_afmt_audio_select_pin(encoder);
1721         dce_v11_0_audio_write_sad_regs(encoder);
1722         dce_v11_0_audio_write_latency_fields(encoder, mode);
1723
1724         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false);
1725         if (err < 0) {
1726                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1727                 return;
1728         }
1729
1730         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1731         if (err < 0) {
1732                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1733                 return;
1734         }
1735
1736         dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1737
1738         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1739         /* enable AVI info frames */
1740         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1741         /* required for audio info values to be updated */
1742         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1743         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1744
1745         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1746         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1747         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1748
1749         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1750         /* send audio packets */
1751         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1752         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1753
1754         WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1755         WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1756         WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1757         WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1758
1759         /* enable audio after to setting up hw */
1760         dce_v11_0_audio_enable(adev, dig->afmt->pin, true);
1761 }
1762
1763 static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1764 {
1765         struct drm_device *dev = encoder->dev;
1766         struct amdgpu_device *adev = dev->dev_private;
1767         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1768         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1769
1770         if (!dig || !dig->afmt)
1771                 return;
1772
1773         /* Silent, r600_hdmi_enable will raise WARN for us */
1774         if (enable && dig->afmt->enabled)
1775                 return;
1776         if (!enable && !dig->afmt->enabled)
1777                 return;
1778
1779         if (!enable && dig->afmt->pin) {
1780                 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1781                 dig->afmt->pin = NULL;
1782         }
1783
1784         dig->afmt->enabled = enable;
1785
1786         DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1787                   enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1788 }
1789
1790 static int dce_v11_0_afmt_init(struct amdgpu_device *adev)
1791 {
1792         int i;
1793
1794         for (i = 0; i < adev->mode_info.num_dig; i++)
1795                 adev->mode_info.afmt[i] = NULL;
1796
1797         /* DCE11 has audio blocks tied to DIG encoders */
1798         for (i = 0; i < adev->mode_info.num_dig; i++) {
1799                 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1800                 if (adev->mode_info.afmt[i]) {
1801                         adev->mode_info.afmt[i]->offset = dig_offsets[i];
1802                         adev->mode_info.afmt[i]->id = i;
1803                 } else {
1804                         int j;
1805                         for (j = 0; j < i; j++) {
1806                                 kfree(adev->mode_info.afmt[j]);
1807                                 adev->mode_info.afmt[j] = NULL;
1808                         }
1809                         return -ENOMEM;
1810                 }
1811         }
1812         return 0;
1813 }
1814
1815 static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)
1816 {
1817         int i;
1818
1819         for (i = 0; i < adev->mode_info.num_dig; i++) {
1820                 kfree(adev->mode_info.afmt[i]);
1821                 adev->mode_info.afmt[i] = NULL;
1822         }
1823 }
1824
1825 static const u32 vga_control_regs[6] =
1826 {
1827         mmD1VGA_CONTROL,
1828         mmD2VGA_CONTROL,
1829         mmD3VGA_CONTROL,
1830         mmD4VGA_CONTROL,
1831         mmD5VGA_CONTROL,
1832         mmD6VGA_CONTROL,
1833 };
1834
1835 static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable)
1836 {
1837         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1838         struct drm_device *dev = crtc->dev;
1839         struct amdgpu_device *adev = dev->dev_private;
1840         u32 vga_control;
1841
1842         vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1843         if (enable)
1844                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1845         else
1846                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1847 }
1848
1849 static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable)
1850 {
1851         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1852         struct drm_device *dev = crtc->dev;
1853         struct amdgpu_device *adev = dev->dev_private;
1854
1855         if (enable)
1856                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1857         else
1858                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1859 }
1860
1861 static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
1862                                      struct drm_framebuffer *fb,
1863                                      int x, int y, int atomic)
1864 {
1865         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1866         struct drm_device *dev = crtc->dev;
1867         struct amdgpu_device *adev = dev->dev_private;
1868         struct drm_framebuffer *target_fb;
1869         struct drm_gem_object *obj;
1870         struct amdgpu_bo *abo;
1871         uint64_t fb_location, tiling_flags;
1872         uint32_t fb_format, fb_pitch_pixels;
1873         u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
1874         u32 pipe_config;
1875         u32 tmp, viewport_w, viewport_h;
1876         int r;
1877         bool bypass_lut = false;
1878         struct drm_format_name_buf format_name;
1879
1880         /* no fb bound */
1881         if (!atomic && !crtc->primary->fb) {
1882                 DRM_DEBUG_KMS("No FB bound\n");
1883                 return 0;
1884         }
1885
1886         if (atomic)
1887                 target_fb = fb;
1888         else
1889                 target_fb = crtc->primary->fb;
1890
1891         /* If atomic, assume fb object is pinned & idle & fenced and
1892          * just update base pointers
1893          */
1894         obj = target_fb->obj[0];
1895         abo = gem_to_amdgpu_bo(obj);
1896         r = amdgpu_bo_reserve(abo, false);
1897         if (unlikely(r != 0))
1898                 return r;
1899
1900         if (atomic) {
1901                 fb_location = amdgpu_bo_gpu_offset(abo);
1902         } else {
1903                 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
1904                 if (unlikely(r != 0)) {
1905                         amdgpu_bo_unreserve(abo);
1906                         return -EINVAL;
1907                 }
1908         }
1909
1910         amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1911         amdgpu_bo_unreserve(abo);
1912
1913         pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1914
1915         switch (target_fb->format->format) {
1916         case DRM_FORMAT_C8:
1917                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
1918                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1919                 break;
1920         case DRM_FORMAT_XRGB4444:
1921         case DRM_FORMAT_ARGB4444:
1922                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1923                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
1924 #ifdef __BIG_ENDIAN
1925                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1926                                         ENDIAN_8IN16);
1927 #endif
1928                 break;
1929         case DRM_FORMAT_XRGB1555:
1930         case DRM_FORMAT_ARGB1555:
1931                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1932                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1933 #ifdef __BIG_ENDIAN
1934                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1935                                         ENDIAN_8IN16);
1936 #endif
1937                 break;
1938         case DRM_FORMAT_BGRX5551:
1939         case DRM_FORMAT_BGRA5551:
1940                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1941                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
1942 #ifdef __BIG_ENDIAN
1943                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1944                                         ENDIAN_8IN16);
1945 #endif
1946                 break;
1947         case DRM_FORMAT_RGB565:
1948                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1949                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1950 #ifdef __BIG_ENDIAN
1951                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1952                                         ENDIAN_8IN16);
1953 #endif
1954                 break;
1955         case DRM_FORMAT_XRGB8888:
1956         case DRM_FORMAT_ARGB8888:
1957                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1958                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1959 #ifdef __BIG_ENDIAN
1960                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1961                                         ENDIAN_8IN32);
1962 #endif
1963                 break;
1964         case DRM_FORMAT_XRGB2101010:
1965         case DRM_FORMAT_ARGB2101010:
1966                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1967                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1968 #ifdef __BIG_ENDIAN
1969                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1970                                         ENDIAN_8IN32);
1971 #endif
1972                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1973                 bypass_lut = true;
1974                 break;
1975         case DRM_FORMAT_BGRX1010102:
1976         case DRM_FORMAT_BGRA1010102:
1977                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1978                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
1979 #ifdef __BIG_ENDIAN
1980                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1981                                         ENDIAN_8IN32);
1982 #endif
1983                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1984                 bypass_lut = true;
1985                 break;
1986         default:
1987                 DRM_ERROR("Unsupported screen format %s\n",
1988                           drm_get_format_name(target_fb->format->format, &format_name));
1989                 return -EINVAL;
1990         }
1991
1992         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1993                 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
1994
1995                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1996                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1997                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1998                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1999                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2000
2001                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2002                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2003                                           ARRAY_2D_TILED_THIN1);
2004                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2005                                           tile_split);
2006                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2007                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2008                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2009                                           mtaspect);
2010                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2011                                           ADDR_SURF_MICRO_TILING_DISPLAY);
2012         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2013                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2014                                           ARRAY_1D_TILED_THIN1);
2015         }
2016
2017         fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2018                                   pipe_config);
2019
2020         dce_v11_0_vga_enable(crtc, false);
2021
2022         /* Make sure surface address is updated at vertical blank rather than
2023          * horizontal blank
2024          */
2025         tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2026         tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2027                             GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2028         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2029
2030         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2031                upper_32_bits(fb_location));
2032         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2033                upper_32_bits(fb_location));
2034         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2035                (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2036         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2037                (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2038         WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2039         WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2040
2041         /*
2042          * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2043          * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2044          * retain the full precision throughout the pipeline.
2045          */
2046         tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2047         if (bypass_lut)
2048                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2049         else
2050                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2051         WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2052
2053         if (bypass_lut)
2054                 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2055
2056         WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2057         WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2058         WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2059         WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2060         WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2061         WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2062
2063         fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
2064         WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2065
2066         dce_v11_0_grph_enable(crtc, true);
2067
2068         WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2069                target_fb->height);
2070
2071         x &= ~3;
2072         y &= ~1;
2073         WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2074                (x << 16) | y);
2075         viewport_w = crtc->mode.hdisplay;
2076         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2077         WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2078                (viewport_w << 16) | viewport_h);
2079
2080         /* set pageflip to happen anywhere in vblank interval */
2081         WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2082
2083         if (!atomic && fb && fb != crtc->primary->fb) {
2084                 abo = gem_to_amdgpu_bo(fb->obj[0]);
2085                 r = amdgpu_bo_reserve(abo, true);
2086                 if (unlikely(r != 0))
2087                         return r;
2088                 amdgpu_bo_unpin(abo);
2089                 amdgpu_bo_unreserve(abo);
2090         }
2091
2092         /* Bytes per pixel may have changed */
2093         dce_v11_0_bandwidth_update(adev);
2094
2095         return 0;
2096 }
2097
2098 static void dce_v11_0_set_interleave(struct drm_crtc *crtc,
2099                                      struct drm_display_mode *mode)
2100 {
2101         struct drm_device *dev = crtc->dev;
2102         struct amdgpu_device *adev = dev->dev_private;
2103         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2104         u32 tmp;
2105
2106         tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2107         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2108                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2109         else
2110                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2111         WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2112 }
2113
2114 static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)
2115 {
2116         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2117         struct drm_device *dev = crtc->dev;
2118         struct amdgpu_device *adev = dev->dev_private;
2119         u16 *r, *g, *b;
2120         int i;
2121         u32 tmp;
2122
2123         DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2124
2125         tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2126         tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2127         WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2128
2129         tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2130         tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2131         WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2132
2133         tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2134         tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2135         WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2136
2137         WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2138
2139         WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2140         WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2141         WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2142
2143         WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2144         WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2145         WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2146
2147         WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2148         WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2149
2150         WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2151         r = crtc->gamma_store;
2152         g = r + crtc->gamma_size;
2153         b = g + crtc->gamma_size;
2154         for (i = 0; i < 256; i++) {
2155                 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2156                        ((*r++ & 0xffc0) << 14) |
2157                        ((*g++ & 0xffc0) << 4) |
2158                        (*b++ >> 6));
2159         }
2160
2161         tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2162         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2163         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2164         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0);
2165         WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2166
2167         tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2168         tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2169         WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2170
2171         tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2172         tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2173         WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2174
2175         tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2176         tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2177         WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2178
2179         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2180         WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2181         /* XXX this only needs to be programmed once per crtc at startup,
2182          * not sure where the best place for it is
2183          */
2184         tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2185         tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2186         WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2187 }
2188
2189 static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
2190 {
2191         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2192         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2193
2194         switch (amdgpu_encoder->encoder_id) {
2195         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2196                 if (dig->linkb)
2197                         return 1;
2198                 else
2199                         return 0;
2200                 break;
2201         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2202                 if (dig->linkb)
2203                         return 3;
2204                 else
2205                         return 2;
2206                 break;
2207         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2208                 if (dig->linkb)
2209                         return 5;
2210                 else
2211                         return 4;
2212                 break;
2213         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2214                 return 6;
2215                 break;
2216         default:
2217                 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2218                 return 0;
2219         }
2220 }
2221
2222 /**
2223  * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2224  *
2225  * @crtc: drm crtc
2226  *
2227  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
2228  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
2229  * monitors a dedicated PPLL must be used.  If a particular board has
2230  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2231  * as there is no need to program the PLL itself.  If we are not able to
2232  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2233  * avoid messing up an existing monitor.
2234  *
2235  * Asic specific PLL information
2236  *
2237  * DCE 10.x
2238  * Tonga
2239  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2240  * CI
2241  * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2242  *
2243  */
2244 static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
2245 {
2246         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2247         struct drm_device *dev = crtc->dev;
2248         struct amdgpu_device *adev = dev->dev_private;
2249         u32 pll_in_use;
2250         int pll;
2251
2252         if ((adev->asic_type == CHIP_POLARIS10) ||
2253             (adev->asic_type == CHIP_POLARIS11) ||
2254             (adev->asic_type == CHIP_POLARIS12) ||
2255             (adev->asic_type == CHIP_VEGAM)) {
2256                 struct amdgpu_encoder *amdgpu_encoder =
2257                         to_amdgpu_encoder(amdgpu_crtc->encoder);
2258                 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2259
2260                 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2261                         return ATOM_DP_DTO;
2262
2263                 switch (amdgpu_encoder->encoder_id) {
2264                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2265                         if (dig->linkb)
2266                                 return ATOM_COMBOPHY_PLL1;
2267                         else
2268                                 return ATOM_COMBOPHY_PLL0;
2269                         break;
2270                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2271                         if (dig->linkb)
2272                                 return ATOM_COMBOPHY_PLL3;
2273                         else
2274                                 return ATOM_COMBOPHY_PLL2;
2275                         break;
2276                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2277                         if (dig->linkb)
2278                                 return ATOM_COMBOPHY_PLL5;
2279                         else
2280                                 return ATOM_COMBOPHY_PLL4;
2281                         break;
2282                 default:
2283                         DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2284                         return ATOM_PPLL_INVALID;
2285                 }
2286         }
2287
2288         if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2289                 if (adev->clock.dp_extclk)
2290                         /* skip PPLL programming if using ext clock */
2291                         return ATOM_PPLL_INVALID;
2292                 else {
2293                         /* use the same PPLL for all DP monitors */
2294                         pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2295                         if (pll != ATOM_PPLL_INVALID)
2296                                 return pll;
2297                 }
2298         } else {
2299                 /* use the same PPLL for all monitors with the same clock */
2300                 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2301                 if (pll != ATOM_PPLL_INVALID)
2302                         return pll;
2303         }
2304
2305         /* XXX need to determine what plls are available on each DCE11 part */
2306         pll_in_use = amdgpu_pll_get_use_mask(crtc);
2307         if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) {
2308                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2309                         return ATOM_PPLL1;
2310                 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2311                         return ATOM_PPLL0;
2312                 DRM_ERROR("unable to allocate a PPLL\n");
2313                 return ATOM_PPLL_INVALID;
2314         } else {
2315                 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2316                         return ATOM_PPLL2;
2317                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2318                         return ATOM_PPLL1;
2319                 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2320                         return ATOM_PPLL0;
2321                 DRM_ERROR("unable to allocate a PPLL\n");
2322                 return ATOM_PPLL_INVALID;
2323         }
2324         return ATOM_PPLL_INVALID;
2325 }
2326
2327 static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2328 {
2329         struct amdgpu_device *adev = crtc->dev->dev_private;
2330         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2331         uint32_t cur_lock;
2332
2333         cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2334         if (lock)
2335                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2336         else
2337                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2338         WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2339 }
2340
2341 static void dce_v11_0_hide_cursor(struct drm_crtc *crtc)
2342 {
2343         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2344         struct amdgpu_device *adev = crtc->dev->dev_private;
2345         u32 tmp;
2346
2347         tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2348         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2349         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2350 }
2351
2352 static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
2353 {
2354         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2355         struct amdgpu_device *adev = crtc->dev->dev_private;
2356         u32 tmp;
2357
2358         WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2359                upper_32_bits(amdgpu_crtc->cursor_addr));
2360         WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2361                lower_32_bits(amdgpu_crtc->cursor_addr));
2362
2363         tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2364         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2365         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2366         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2367 }
2368
2369 static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
2370                                         int x, int y)
2371 {
2372         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2373         struct amdgpu_device *adev = crtc->dev->dev_private;
2374         int xorigin = 0, yorigin = 0;
2375
2376         amdgpu_crtc->cursor_x = x;
2377         amdgpu_crtc->cursor_y = y;
2378
2379         /* avivo cursor are offset into the total surface */
2380         x += crtc->x;
2381         y += crtc->y;
2382         DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2383
2384         if (x < 0) {
2385                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2386                 x = 0;
2387         }
2388         if (y < 0) {
2389                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2390                 y = 0;
2391         }
2392
2393         WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2394         WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2395         WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2396                ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2397
2398         return 0;
2399 }
2400
2401 static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
2402                                       int x, int y)
2403 {
2404         int ret;
2405
2406         dce_v11_0_lock_cursor(crtc, true);
2407         ret = dce_v11_0_cursor_move_locked(crtc, x, y);
2408         dce_v11_0_lock_cursor(crtc, false);
2409
2410         return ret;
2411 }
2412
2413 static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
2414                                       struct drm_file *file_priv,
2415                                       uint32_t handle,
2416                                       uint32_t width,
2417                                       uint32_t height,
2418                                       int32_t hot_x,
2419                                       int32_t hot_y)
2420 {
2421         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2422         struct drm_gem_object *obj;
2423         struct amdgpu_bo *aobj;
2424         int ret;
2425
2426         if (!handle) {
2427                 /* turn off cursor */
2428                 dce_v11_0_hide_cursor(crtc);
2429                 obj = NULL;
2430                 goto unpin;
2431         }
2432
2433         if ((width > amdgpu_crtc->max_cursor_width) ||
2434             (height > amdgpu_crtc->max_cursor_height)) {
2435                 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2436                 return -EINVAL;
2437         }
2438
2439         obj = drm_gem_object_lookup(file_priv, handle);
2440         if (!obj) {
2441                 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2442                 return -ENOENT;
2443         }
2444
2445         aobj = gem_to_amdgpu_bo(obj);
2446         ret = amdgpu_bo_reserve(aobj, false);
2447         if (ret != 0) {
2448                 drm_gem_object_put_unlocked(obj);
2449                 return ret;
2450         }
2451
2452         ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2453         amdgpu_bo_unreserve(aobj);
2454         if (ret) {
2455                 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2456                 drm_gem_object_put_unlocked(obj);
2457                 return ret;
2458         }
2459
2460         dce_v11_0_lock_cursor(crtc, true);
2461
2462         if (width != amdgpu_crtc->cursor_width ||
2463             height != amdgpu_crtc->cursor_height ||
2464             hot_x != amdgpu_crtc->cursor_hot_x ||
2465             hot_y != amdgpu_crtc->cursor_hot_y) {
2466                 int x, y;
2467
2468                 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2469                 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2470
2471                 dce_v11_0_cursor_move_locked(crtc, x, y);
2472
2473                 amdgpu_crtc->cursor_width = width;
2474                 amdgpu_crtc->cursor_height = height;
2475                 amdgpu_crtc->cursor_hot_x = hot_x;
2476                 amdgpu_crtc->cursor_hot_y = hot_y;
2477         }
2478
2479         dce_v11_0_show_cursor(crtc);
2480         dce_v11_0_lock_cursor(crtc, false);
2481
2482 unpin:
2483         if (amdgpu_crtc->cursor_bo) {
2484                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2485                 ret = amdgpu_bo_reserve(aobj, true);
2486                 if (likely(ret == 0)) {
2487                         amdgpu_bo_unpin(aobj);
2488                         amdgpu_bo_unreserve(aobj);
2489                 }
2490                 drm_gem_object_put_unlocked(amdgpu_crtc->cursor_bo);
2491         }
2492
2493         amdgpu_crtc->cursor_bo = obj;
2494         return 0;
2495 }
2496
2497 static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
2498 {
2499         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2500
2501         if (amdgpu_crtc->cursor_bo) {
2502                 dce_v11_0_lock_cursor(crtc, true);
2503
2504                 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2505                                              amdgpu_crtc->cursor_y);
2506
2507                 dce_v11_0_show_cursor(crtc);
2508
2509                 dce_v11_0_lock_cursor(crtc, false);
2510         }
2511 }
2512
2513 static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2514                                     u16 *blue, uint32_t size,
2515                                     struct drm_modeset_acquire_ctx *ctx)
2516 {
2517         dce_v11_0_crtc_load_lut(crtc);
2518
2519         return 0;
2520 }
2521
2522 static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
2523 {
2524         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2525
2526         drm_crtc_cleanup(crtc);
2527         kfree(amdgpu_crtc);
2528 }
2529
2530 static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = {
2531         .cursor_set2 = dce_v11_0_crtc_cursor_set2,
2532         .cursor_move = dce_v11_0_crtc_cursor_move,
2533         .gamma_set = dce_v11_0_crtc_gamma_set,
2534         .set_config = amdgpu_display_crtc_set_config,
2535         .destroy = dce_v11_0_crtc_destroy,
2536         .page_flip_target = amdgpu_display_crtc_page_flip_target,
2537 };
2538
2539 static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2540 {
2541         struct drm_device *dev = crtc->dev;
2542         struct amdgpu_device *adev = dev->dev_private;
2543         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2544         unsigned type;
2545
2546         switch (mode) {
2547         case DRM_MODE_DPMS_ON:
2548                 amdgpu_crtc->enabled = true;
2549                 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2550                 dce_v11_0_vga_enable(crtc, true);
2551                 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2552                 dce_v11_0_vga_enable(crtc, false);
2553                 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2554                 type = amdgpu_display_crtc_idx_to_irq_type(adev,
2555                                                 amdgpu_crtc->crtc_id);
2556                 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2557                 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2558                 drm_crtc_vblank_on(crtc);
2559                 dce_v11_0_crtc_load_lut(crtc);
2560                 break;
2561         case DRM_MODE_DPMS_STANDBY:
2562         case DRM_MODE_DPMS_SUSPEND:
2563         case DRM_MODE_DPMS_OFF:
2564                 drm_crtc_vblank_off(crtc);
2565                 if (amdgpu_crtc->enabled) {
2566                         dce_v11_0_vga_enable(crtc, true);
2567                         amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2568                         dce_v11_0_vga_enable(crtc, false);
2569                 }
2570                 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2571                 amdgpu_crtc->enabled = false;
2572                 break;
2573         }
2574         /* adjust pm to dpms */
2575         amdgpu_pm_compute_clocks(adev);
2576 }
2577
2578 static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc)
2579 {
2580         /* disable crtc pair power gating before programming */
2581         amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2582         amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2583         dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2584 }
2585
2586 static void dce_v11_0_crtc_commit(struct drm_crtc *crtc)
2587 {
2588         dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2589         amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2590 }
2591
2592 static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
2593 {
2594         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2595         struct drm_device *dev = crtc->dev;
2596         struct amdgpu_device *adev = dev->dev_private;
2597         struct amdgpu_atom_ss ss;
2598         int i;
2599
2600         dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2601         if (crtc->primary->fb) {
2602                 int r;
2603                 struct amdgpu_bo *abo;
2604
2605                 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
2606                 r = amdgpu_bo_reserve(abo, true);
2607                 if (unlikely(r))
2608                         DRM_ERROR("failed to reserve abo before unpin\n");
2609                 else {
2610                         amdgpu_bo_unpin(abo);
2611                         amdgpu_bo_unreserve(abo);
2612                 }
2613         }
2614         /* disable the GRPH */
2615         dce_v11_0_grph_enable(crtc, false);
2616
2617         amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2618
2619         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2620                 if (adev->mode_info.crtcs[i] &&
2621                     adev->mode_info.crtcs[i]->enabled &&
2622                     i != amdgpu_crtc->crtc_id &&
2623                     amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2624                         /* one other crtc is using this pll don't turn
2625                          * off the pll
2626                          */
2627                         goto done;
2628                 }
2629         }
2630
2631         switch (amdgpu_crtc->pll_id) {
2632         case ATOM_PPLL0:
2633         case ATOM_PPLL1:
2634         case ATOM_PPLL2:
2635                 /* disable the ppll */
2636                 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2637                                                  0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2638                 break;
2639         case ATOM_COMBOPHY_PLL0:
2640         case ATOM_COMBOPHY_PLL1:
2641         case ATOM_COMBOPHY_PLL2:
2642         case ATOM_COMBOPHY_PLL3:
2643         case ATOM_COMBOPHY_PLL4:
2644         case ATOM_COMBOPHY_PLL5:
2645                 /* disable the ppll */
2646                 amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id,
2647                                                  0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2648                 break;
2649         default:
2650                 break;
2651         }
2652 done:
2653         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2654         amdgpu_crtc->adjusted_clock = 0;
2655         amdgpu_crtc->encoder = NULL;
2656         amdgpu_crtc->connector = NULL;
2657 }
2658
2659 static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
2660                                   struct drm_display_mode *mode,
2661                                   struct drm_display_mode *adjusted_mode,
2662                                   int x, int y, struct drm_framebuffer *old_fb)
2663 {
2664         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2665         struct drm_device *dev = crtc->dev;
2666         struct amdgpu_device *adev = dev->dev_private;
2667
2668         if (!amdgpu_crtc->adjusted_clock)
2669                 return -EINVAL;
2670
2671         if ((adev->asic_type == CHIP_POLARIS10) ||
2672             (adev->asic_type == CHIP_POLARIS11) ||
2673             (adev->asic_type == CHIP_POLARIS12) ||
2674             (adev->asic_type == CHIP_VEGAM)) {
2675                 struct amdgpu_encoder *amdgpu_encoder =
2676                         to_amdgpu_encoder(amdgpu_crtc->encoder);
2677                 int encoder_mode =
2678                         amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
2679
2680                 /* SetPixelClock calculates the plls and ss values now */
2681                 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id,
2682                                                  amdgpu_crtc->pll_id,
2683                                                  encoder_mode, amdgpu_encoder->encoder_id,
2684                                                  adjusted_mode->clock, 0, 0, 0, 0,
2685                                                  amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss);
2686         } else {
2687                 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2688         }
2689         amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2690         dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2691         amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2692         amdgpu_atombios_crtc_scaler_setup(crtc);
2693         dce_v11_0_cursor_reset(crtc);
2694         /* update the hw version fpr dpm */
2695         amdgpu_crtc->hw_mode = *adjusted_mode;
2696
2697         return 0;
2698 }
2699
2700 static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc,
2701                                      const struct drm_display_mode *mode,
2702                                      struct drm_display_mode *adjusted_mode)
2703 {
2704         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2705         struct drm_device *dev = crtc->dev;
2706         struct drm_encoder *encoder;
2707
2708         /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2709         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2710                 if (encoder->crtc == crtc) {
2711                         amdgpu_crtc->encoder = encoder;
2712                         amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2713                         break;
2714                 }
2715         }
2716         if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2717                 amdgpu_crtc->encoder = NULL;
2718                 amdgpu_crtc->connector = NULL;
2719                 return false;
2720         }
2721         if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2722                 return false;
2723         if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2724                 return false;
2725         /* pick pll */
2726         amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
2727         /* if we can't get a PPLL for a non-DP encoder, fail */
2728         if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2729             !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2730                 return false;
2731
2732         return true;
2733 }
2734
2735 static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2736                                   struct drm_framebuffer *old_fb)
2737 {
2738         return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2739 }
2740
2741 static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2742                                          struct drm_framebuffer *fb,
2743                                          int x, int y, enum mode_set_atomic state)
2744 {
2745        return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1);
2746 }
2747
2748 static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = {
2749         .dpms = dce_v11_0_crtc_dpms,
2750         .mode_fixup = dce_v11_0_crtc_mode_fixup,
2751         .mode_set = dce_v11_0_crtc_mode_set,
2752         .mode_set_base = dce_v11_0_crtc_set_base,
2753         .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic,
2754         .prepare = dce_v11_0_crtc_prepare,
2755         .commit = dce_v11_0_crtc_commit,
2756         .disable = dce_v11_0_crtc_disable,
2757 };
2758
2759 static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
2760 {
2761         struct amdgpu_crtc *amdgpu_crtc;
2762
2763         amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2764                               (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2765         if (amdgpu_crtc == NULL)
2766                 return -ENOMEM;
2767
2768         drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
2769
2770         drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2771         amdgpu_crtc->crtc_id = index;
2772         adev->mode_info.crtcs[index] = amdgpu_crtc;
2773
2774         amdgpu_crtc->max_cursor_width = 128;
2775         amdgpu_crtc->max_cursor_height = 128;
2776         adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2777         adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2778
2779         switch (amdgpu_crtc->crtc_id) {
2780         case 0:
2781         default:
2782                 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2783                 break;
2784         case 1:
2785                 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2786                 break;
2787         case 2:
2788                 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2789                 break;
2790         case 3:
2791                 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2792                 break;
2793         case 4:
2794                 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2795                 break;
2796         case 5:
2797                 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2798                 break;
2799         }
2800
2801         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2802         amdgpu_crtc->adjusted_clock = 0;
2803         amdgpu_crtc->encoder = NULL;
2804         amdgpu_crtc->connector = NULL;
2805         drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs);
2806
2807         return 0;
2808 }
2809
2810 static int dce_v11_0_early_init(void *handle)
2811 {
2812         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2813
2814         adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;
2815         adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
2816
2817         dce_v11_0_set_display_funcs(adev);
2818
2819         adev->mode_info.num_crtc = dce_v11_0_get_num_crtc(adev);
2820
2821         switch (adev->asic_type) {
2822         case CHIP_CARRIZO:
2823                 adev->mode_info.num_hpd = 6;
2824                 adev->mode_info.num_dig = 9;
2825                 break;
2826         case CHIP_STONEY:
2827                 adev->mode_info.num_hpd = 6;
2828                 adev->mode_info.num_dig = 9;
2829                 break;
2830         case CHIP_POLARIS10:
2831         case CHIP_VEGAM:
2832                 adev->mode_info.num_hpd = 6;
2833                 adev->mode_info.num_dig = 6;
2834                 break;
2835         case CHIP_POLARIS11:
2836         case CHIP_POLARIS12:
2837                 adev->mode_info.num_hpd = 5;
2838                 adev->mode_info.num_dig = 5;
2839                 break;
2840         default:
2841                 /* FIXME: not supported yet */
2842                 return -EINVAL;
2843         }
2844
2845         dce_v11_0_set_irq_funcs(adev);
2846
2847         return 0;
2848 }
2849
2850 static int dce_v11_0_sw_init(void *handle)
2851 {
2852         int r, i;
2853         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2854
2855         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2856                 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2857                 if (r)
2858                         return r;
2859         }
2860
2861         for (i = 8; i < 20; i += 2) {
2862                 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2863                 if (r)
2864                         return r;
2865         }
2866
2867         /* HPD hotplug */
2868         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq);
2869         if (r)
2870                 return r;
2871
2872         adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2873
2874         adev->ddev->mode_config.async_page_flip = true;
2875
2876         adev->ddev->mode_config.max_width = 16384;
2877         adev->ddev->mode_config.max_height = 16384;
2878
2879         adev->ddev->mode_config.preferred_depth = 24;
2880         adev->ddev->mode_config.prefer_shadow = 1;
2881
2882         adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
2883
2884         r = amdgpu_display_modeset_create_props(adev);
2885         if (r)
2886                 return r;
2887
2888         adev->ddev->mode_config.max_width = 16384;
2889         adev->ddev->mode_config.max_height = 16384;
2890
2891
2892         /* allocate crtcs */
2893         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2894                 r = dce_v11_0_crtc_init(adev, i);
2895                 if (r)
2896                         return r;
2897         }
2898
2899         if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2900                 amdgpu_display_print_display_setup(adev->ddev);
2901         else
2902                 return -EINVAL;
2903
2904         /* setup afmt */
2905         r = dce_v11_0_afmt_init(adev);
2906         if (r)
2907                 return r;
2908
2909         r = dce_v11_0_audio_init(adev);
2910         if (r)
2911                 return r;
2912
2913         drm_kms_helper_poll_init(adev->ddev);
2914
2915         adev->mode_info.mode_config_initialized = true;
2916         return 0;
2917 }
2918
2919 static int dce_v11_0_sw_fini(void *handle)
2920 {
2921         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2922
2923         kfree(adev->mode_info.bios_hardcoded_edid);
2924
2925         drm_kms_helper_poll_fini(adev->ddev);
2926
2927         dce_v11_0_audio_fini(adev);
2928
2929         dce_v11_0_afmt_fini(adev);
2930
2931         drm_mode_config_cleanup(adev->ddev);
2932         adev->mode_info.mode_config_initialized = false;
2933
2934         return 0;
2935 }
2936
2937 static int dce_v11_0_hw_init(void *handle)
2938 {
2939         int i;
2940         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2941
2942         dce_v11_0_init_golden_registers(adev);
2943
2944         /* disable vga render */
2945         dce_v11_0_set_vga_render_state(adev, false);
2946         /* init dig PHYs, disp eng pll */
2947         amdgpu_atombios_crtc_powergate_init(adev);
2948         amdgpu_atombios_encoder_init_dig(adev);
2949         if ((adev->asic_type == CHIP_POLARIS10) ||
2950             (adev->asic_type == CHIP_POLARIS11) ||
2951             (adev->asic_type == CHIP_POLARIS12) ||
2952             (adev->asic_type == CHIP_VEGAM)) {
2953                 amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk,
2954                                                    DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS);
2955                 amdgpu_atombios_crtc_set_dce_clock(adev, 0,
2956                                                    DCE_CLOCK_TYPE_DPREFCLK, ATOM_GCK_DFS);
2957         } else {
2958                 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2959         }
2960
2961         /* initialize hpd */
2962         dce_v11_0_hpd_init(adev);
2963
2964         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2965                 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2966         }
2967
2968         dce_v11_0_pageflip_interrupt_init(adev);
2969
2970         return 0;
2971 }
2972
2973 static int dce_v11_0_hw_fini(void *handle)
2974 {
2975         int i;
2976         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2977
2978         dce_v11_0_hpd_fini(adev);
2979
2980         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2981                 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2982         }
2983
2984         dce_v11_0_pageflip_interrupt_fini(adev);
2985
2986         return 0;
2987 }
2988
2989 static int dce_v11_0_suspend(void *handle)
2990 {
2991         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2992
2993         adev->mode_info.bl_level =
2994                 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
2995
2996         return dce_v11_0_hw_fini(handle);
2997 }
2998
2999 static int dce_v11_0_resume(void *handle)
3000 {
3001         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3002         int ret;
3003
3004         amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
3005                                                            adev->mode_info.bl_level);
3006
3007         ret = dce_v11_0_hw_init(handle);
3008
3009         /* turn on the BL */
3010         if (adev->mode_info.bl_encoder) {
3011                 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3012                                                                   adev->mode_info.bl_encoder);
3013                 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3014                                                     bl_level);
3015         }
3016
3017         return ret;
3018 }
3019
3020 static bool dce_v11_0_is_idle(void *handle)
3021 {
3022         return true;
3023 }
3024
3025 static int dce_v11_0_wait_for_idle(void *handle)
3026 {
3027         return 0;
3028 }
3029
3030 static int dce_v11_0_soft_reset(void *handle)
3031 {
3032         u32 srbm_soft_reset = 0, tmp;
3033         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3034
3035         if (dce_v11_0_is_display_hung(adev))
3036                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3037
3038         if (srbm_soft_reset) {
3039                 tmp = RREG32(mmSRBM_SOFT_RESET);
3040                 tmp |= srbm_soft_reset;
3041                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3042                 WREG32(mmSRBM_SOFT_RESET, tmp);
3043                 tmp = RREG32(mmSRBM_SOFT_RESET);
3044
3045                 udelay(50);
3046
3047                 tmp &= ~srbm_soft_reset;
3048                 WREG32(mmSRBM_SOFT_RESET, tmp);
3049                 tmp = RREG32(mmSRBM_SOFT_RESET);
3050
3051                 /* Wait a little for things to settle down */
3052                 udelay(50);
3053         }
3054         return 0;
3055 }
3056
3057 static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3058                                                      int crtc,
3059                                                      enum amdgpu_interrupt_state state)
3060 {
3061         u32 lb_interrupt_mask;
3062
3063         if (crtc >= adev->mode_info.num_crtc) {
3064                 DRM_DEBUG("invalid crtc %d\n", crtc);
3065                 return;
3066         }
3067
3068         switch (state) {
3069         case AMDGPU_IRQ_STATE_DISABLE:
3070                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3071                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3072                                                   VBLANK_INTERRUPT_MASK, 0);
3073                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3074                 break;
3075         case AMDGPU_IRQ_STATE_ENABLE:
3076                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3077                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3078                                                   VBLANK_INTERRUPT_MASK, 1);
3079                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3080                 break;
3081         default:
3082                 break;
3083         }
3084 }
3085
3086 static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3087                                                     int crtc,
3088                                                     enum amdgpu_interrupt_state state)
3089 {
3090         u32 lb_interrupt_mask;
3091
3092         if (crtc >= adev->mode_info.num_crtc) {
3093                 DRM_DEBUG("invalid crtc %d\n", crtc);
3094                 return;
3095         }
3096
3097         switch (state) {
3098         case AMDGPU_IRQ_STATE_DISABLE:
3099                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3100                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3101                                                   VLINE_INTERRUPT_MASK, 0);
3102                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3103                 break;
3104         case AMDGPU_IRQ_STATE_ENABLE:
3105                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3106                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3107                                                   VLINE_INTERRUPT_MASK, 1);
3108                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3109                 break;
3110         default:
3111                 break;
3112         }
3113 }
3114
3115 static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev,
3116                                         struct amdgpu_irq_src *source,
3117                                         unsigned hpd,
3118                                         enum amdgpu_interrupt_state state)
3119 {
3120         u32 tmp;
3121
3122         if (hpd >= adev->mode_info.num_hpd) {
3123                 DRM_DEBUG("invalid hdp %d\n", hpd);
3124                 return 0;
3125         }
3126
3127         switch (state) {
3128         case AMDGPU_IRQ_STATE_DISABLE:
3129                 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3130                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3131                 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3132                 break;
3133         case AMDGPU_IRQ_STATE_ENABLE:
3134                 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3135                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3136                 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3137                 break;
3138         default:
3139                 break;
3140         }
3141
3142         return 0;
3143 }
3144
3145 static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev,
3146                                         struct amdgpu_irq_src *source,
3147                                         unsigned type,
3148                                         enum amdgpu_interrupt_state state)
3149 {
3150         switch (type) {
3151         case AMDGPU_CRTC_IRQ_VBLANK1:
3152                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3153                 break;
3154         case AMDGPU_CRTC_IRQ_VBLANK2:
3155                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3156                 break;
3157         case AMDGPU_CRTC_IRQ_VBLANK3:
3158                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3159                 break;
3160         case AMDGPU_CRTC_IRQ_VBLANK4:
3161                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3162                 break;
3163         case AMDGPU_CRTC_IRQ_VBLANK5:
3164                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3165                 break;
3166         case AMDGPU_CRTC_IRQ_VBLANK6:
3167                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3168                 break;
3169         case AMDGPU_CRTC_IRQ_VLINE1:
3170                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state);
3171                 break;
3172         case AMDGPU_CRTC_IRQ_VLINE2:
3173                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state);
3174                 break;
3175         case AMDGPU_CRTC_IRQ_VLINE3:
3176                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state);
3177                 break;
3178         case AMDGPU_CRTC_IRQ_VLINE4:
3179                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state);
3180                 break;
3181         case AMDGPU_CRTC_IRQ_VLINE5:
3182                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state);
3183                 break;
3184          case AMDGPU_CRTC_IRQ_VLINE6:
3185                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state);
3186                 break;
3187         default:
3188                 break;
3189         }
3190         return 0;
3191 }
3192
3193 static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3194                                             struct amdgpu_irq_src *src,
3195                                             unsigned type,
3196                                             enum amdgpu_interrupt_state state)
3197 {
3198         u32 reg;
3199
3200         if (type >= adev->mode_info.num_crtc) {
3201                 DRM_ERROR("invalid pageflip crtc %d\n", type);
3202                 return -EINVAL;
3203         }
3204
3205         reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3206         if (state == AMDGPU_IRQ_STATE_DISABLE)
3207                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3208                        reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3209         else
3210                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3211                        reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3212
3213         return 0;
3214 }
3215
3216 static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
3217                                   struct amdgpu_irq_src *source,
3218                                   struct amdgpu_iv_entry *entry)
3219 {
3220         unsigned long flags;
3221         unsigned crtc_id;
3222         struct amdgpu_crtc *amdgpu_crtc;
3223         struct amdgpu_flip_work *works;
3224
3225         crtc_id = (entry->src_id - 8) >> 1;
3226         amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3227
3228         if (crtc_id >= adev->mode_info.num_crtc) {
3229                 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3230                 return -EINVAL;
3231         }
3232
3233         if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3234             GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3235                 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3236                        GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3237
3238         /* IRQ could occur when in initial stage */
3239         if(amdgpu_crtc == NULL)
3240                 return 0;
3241
3242         spin_lock_irqsave(&adev->ddev->event_lock, flags);
3243         works = amdgpu_crtc->pflip_works;
3244         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3245                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3246                                                  "AMDGPU_FLIP_SUBMITTED(%d)\n",
3247                                                  amdgpu_crtc->pflip_status,
3248                                                  AMDGPU_FLIP_SUBMITTED);
3249                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3250                 return 0;
3251         }
3252
3253         /* page flip completed. clean up */
3254         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3255         amdgpu_crtc->pflip_works = NULL;
3256
3257         /* wakeup usersapce */
3258         if(works->event)
3259                 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3260
3261         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3262
3263         drm_crtc_vblank_put(&amdgpu_crtc->base);
3264         schedule_work(&works->unpin_work);
3265
3266         return 0;
3267 }
3268
3269 static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev,
3270                                   int hpd)
3271 {
3272         u32 tmp;
3273
3274         if (hpd >= adev->mode_info.num_hpd) {
3275                 DRM_DEBUG("invalid hdp %d\n", hpd);
3276                 return;
3277         }
3278
3279         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3280         tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3281         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3282 }
3283
3284 static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3285                                           int crtc)
3286 {
3287         u32 tmp;
3288
3289         if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3290                 DRM_DEBUG("invalid crtc %d\n", crtc);
3291                 return;
3292         }
3293
3294         tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3295         tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3296         WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3297 }
3298
3299 static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3300                                          int crtc)
3301 {
3302         u32 tmp;
3303
3304         if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3305                 DRM_DEBUG("invalid crtc %d\n", crtc);
3306                 return;
3307         }
3308
3309         tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3310         tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3311         WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3312 }
3313
3314 static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
3315                                 struct amdgpu_irq_src *source,
3316                                 struct amdgpu_iv_entry *entry)
3317 {
3318         unsigned crtc = entry->src_id - 1;
3319         uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3320         unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev,
3321                                                                     crtc);
3322
3323         switch (entry->src_data[0]) {
3324         case 0: /* vblank */
3325                 if (disp_int & interrupt_status_offsets[crtc].vblank)
3326                         dce_v11_0_crtc_vblank_int_ack(adev, crtc);
3327                 else
3328                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3329
3330                 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3331                         drm_handle_vblank(adev->ddev, crtc);
3332                 }
3333                 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3334
3335                 break;
3336         case 1: /* vline */
3337                 if (disp_int & interrupt_status_offsets[crtc].vline)
3338                         dce_v11_0_crtc_vline_int_ack(adev, crtc);
3339                 else
3340                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3341
3342                 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3343
3344                 break;
3345         default:
3346                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3347                 break;
3348         }
3349
3350         return 0;
3351 }
3352
3353 static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
3354                              struct amdgpu_irq_src *source,
3355                              struct amdgpu_iv_entry *entry)
3356 {
3357         uint32_t disp_int, mask;
3358         unsigned hpd;
3359
3360         if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3361                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3362                 return 0;
3363         }
3364
3365         hpd = entry->src_data[0];
3366         disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3367         mask = interrupt_status_offsets[hpd].hpd;
3368
3369         if (disp_int & mask) {
3370                 dce_v11_0_hpd_int_ack(adev, hpd);
3371                 schedule_work(&adev->hotplug_work);
3372                 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3373         }
3374
3375         return 0;
3376 }
3377
3378 static int dce_v11_0_set_clockgating_state(void *handle,
3379                                           enum amd_clockgating_state state)
3380 {
3381         return 0;
3382 }
3383
3384 static int dce_v11_0_set_powergating_state(void *handle,
3385                                           enum amd_powergating_state state)
3386 {
3387         return 0;
3388 }
3389
3390 static const struct amd_ip_funcs dce_v11_0_ip_funcs = {
3391         .name = "dce_v11_0",
3392         .early_init = dce_v11_0_early_init,
3393         .late_init = NULL,
3394         .sw_init = dce_v11_0_sw_init,
3395         .sw_fini = dce_v11_0_sw_fini,
3396         .hw_init = dce_v11_0_hw_init,
3397         .hw_fini = dce_v11_0_hw_fini,
3398         .suspend = dce_v11_0_suspend,
3399         .resume = dce_v11_0_resume,
3400         .is_idle = dce_v11_0_is_idle,
3401         .wait_for_idle = dce_v11_0_wait_for_idle,
3402         .soft_reset = dce_v11_0_soft_reset,
3403         .set_clockgating_state = dce_v11_0_set_clockgating_state,
3404         .set_powergating_state = dce_v11_0_set_powergating_state,
3405 };
3406
3407 static void
3408 dce_v11_0_encoder_mode_set(struct drm_encoder *encoder,
3409                           struct drm_display_mode *mode,
3410                           struct drm_display_mode *adjusted_mode)
3411 {
3412         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3413
3414         amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3415
3416         /* need to call this here rather than in prepare() since we need some crtc info */
3417         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3418
3419         /* set scaler clears this on some chips */
3420         dce_v11_0_set_interleave(encoder->crtc, mode);
3421
3422         if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3423                 dce_v11_0_afmt_enable(encoder, true);
3424                 dce_v11_0_afmt_setmode(encoder, adjusted_mode);
3425         }
3426 }
3427
3428 static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
3429 {
3430         struct amdgpu_device *adev = encoder->dev->dev_private;
3431         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3432         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3433
3434         if ((amdgpu_encoder->active_device &
3435              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3436             (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3437              ENCODER_OBJECT_ID_NONE)) {
3438                 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3439                 if (dig) {
3440                         dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder);
3441                         if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3442                                 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3443                 }
3444         }
3445
3446         amdgpu_atombios_scratch_regs_lock(adev, true);
3447
3448         if (connector) {
3449                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3450
3451                 /* select the clock/data port if it uses a router */
3452                 if (amdgpu_connector->router.cd_valid)
3453                         amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3454
3455                 /* turn eDP panel on for mode set */
3456                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3457                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
3458                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
3459         }
3460
3461         /* this is needed for the pll/ss setup to work correctly in some cases */
3462         amdgpu_atombios_encoder_set_crtc_source(encoder);
3463         /* set up the FMT blocks */
3464         dce_v11_0_program_fmt(encoder);
3465 }
3466
3467 static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)
3468 {
3469         struct drm_device *dev = encoder->dev;
3470         struct amdgpu_device *adev = dev->dev_private;
3471
3472         /* need to call this here as we need the crtc set up */
3473         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3474         amdgpu_atombios_scratch_regs_lock(adev, false);
3475 }
3476
3477 static void dce_v11_0_encoder_disable(struct drm_encoder *encoder)
3478 {
3479         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3480         struct amdgpu_encoder_atom_dig *dig;
3481
3482         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3483
3484         if (amdgpu_atombios_encoder_is_digital(encoder)) {
3485                 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3486                         dce_v11_0_afmt_enable(encoder, false);
3487                 dig = amdgpu_encoder->enc_priv;
3488                 dig->dig_encoder = -1;
3489         }
3490         amdgpu_encoder->active_device = 0;
3491 }
3492
3493 /* these are handled by the primary encoders */
3494 static void dce_v11_0_ext_prepare(struct drm_encoder *encoder)
3495 {
3496
3497 }
3498
3499 static void dce_v11_0_ext_commit(struct drm_encoder *encoder)
3500 {
3501
3502 }
3503
3504 static void
3505 dce_v11_0_ext_mode_set(struct drm_encoder *encoder,
3506                       struct drm_display_mode *mode,
3507                       struct drm_display_mode *adjusted_mode)
3508 {
3509
3510 }
3511
3512 static void dce_v11_0_ext_disable(struct drm_encoder *encoder)
3513 {
3514
3515 }
3516
3517 static void
3518 dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode)
3519 {
3520
3521 }
3522
3523 static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = {
3524         .dpms = dce_v11_0_ext_dpms,
3525         .prepare = dce_v11_0_ext_prepare,
3526         .mode_set = dce_v11_0_ext_mode_set,
3527         .commit = dce_v11_0_ext_commit,
3528         .disable = dce_v11_0_ext_disable,
3529         /* no detect for TMDS/LVDS yet */
3530 };
3531
3532 static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = {
3533         .dpms = amdgpu_atombios_encoder_dpms,
3534         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3535         .prepare = dce_v11_0_encoder_prepare,
3536         .mode_set = dce_v11_0_encoder_mode_set,
3537         .commit = dce_v11_0_encoder_commit,
3538         .disable = dce_v11_0_encoder_disable,
3539         .detect = amdgpu_atombios_encoder_dig_detect,
3540 };
3541
3542 static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = {
3543         .dpms = amdgpu_atombios_encoder_dpms,
3544         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3545         .prepare = dce_v11_0_encoder_prepare,
3546         .mode_set = dce_v11_0_encoder_mode_set,
3547         .commit = dce_v11_0_encoder_commit,
3548         .detect = amdgpu_atombios_encoder_dac_detect,
3549 };
3550
3551 static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder)
3552 {
3553         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3554         if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3555                 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3556         kfree(amdgpu_encoder->enc_priv);
3557         drm_encoder_cleanup(encoder);
3558         kfree(amdgpu_encoder);
3559 }
3560
3561 static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = {
3562         .destroy = dce_v11_0_encoder_destroy,
3563 };
3564
3565 static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
3566                                  uint32_t encoder_enum,
3567                                  uint32_t supported_device,
3568                                  u16 caps)
3569 {
3570         struct drm_device *dev = adev->ddev;
3571         struct drm_encoder *encoder;
3572         struct amdgpu_encoder *amdgpu_encoder;
3573
3574         /* see if we already added it */
3575         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3576                 amdgpu_encoder = to_amdgpu_encoder(encoder);
3577                 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3578                         amdgpu_encoder->devices |= supported_device;
3579                         return;
3580                 }
3581
3582         }
3583
3584         /* add a new one */
3585         amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3586         if (!amdgpu_encoder)
3587                 return;
3588
3589         encoder = &amdgpu_encoder->base;
3590         switch (adev->mode_info.num_crtc) {
3591         case 1:
3592                 encoder->possible_crtcs = 0x1;
3593                 break;
3594         case 2:
3595         default:
3596                 encoder->possible_crtcs = 0x3;
3597                 break;
3598         case 3:
3599                 encoder->possible_crtcs = 0x7;
3600                 break;
3601         case 4:
3602                 encoder->possible_crtcs = 0xf;
3603                 break;
3604         case 5:
3605                 encoder->possible_crtcs = 0x1f;
3606                 break;
3607         case 6:
3608                 encoder->possible_crtcs = 0x3f;
3609                 break;
3610         }
3611
3612         amdgpu_encoder->enc_priv = NULL;
3613
3614         amdgpu_encoder->encoder_enum = encoder_enum;
3615         amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3616         amdgpu_encoder->devices = supported_device;
3617         amdgpu_encoder->rmx_type = RMX_OFF;
3618         amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3619         amdgpu_encoder->is_ext_encoder = false;
3620         amdgpu_encoder->caps = caps;
3621
3622         switch (amdgpu_encoder->encoder_id) {
3623         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3624         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3625                 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3626                                  DRM_MODE_ENCODER_DAC, NULL);
3627                 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
3628                 break;
3629         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3630         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3631         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3632         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3633         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3634                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3635                         amdgpu_encoder->rmx_type = RMX_FULL;
3636                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3637                                          DRM_MODE_ENCODER_LVDS, NULL);
3638                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3639                 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3640                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3641                                          DRM_MODE_ENCODER_DAC, NULL);
3642                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3643                 } else {
3644                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3645                                          DRM_MODE_ENCODER_TMDS, NULL);
3646                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3647                 }
3648                 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
3649                 break;
3650         case ENCODER_OBJECT_ID_SI170B:
3651         case ENCODER_OBJECT_ID_CH7303:
3652         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3653         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3654         case ENCODER_OBJECT_ID_TITFP513:
3655         case ENCODER_OBJECT_ID_VT1623:
3656         case ENCODER_OBJECT_ID_HDMI_SI1930:
3657         case ENCODER_OBJECT_ID_TRAVIS:
3658         case ENCODER_OBJECT_ID_NUTMEG:
3659                 /* these are handled by the primary encoders */
3660                 amdgpu_encoder->is_ext_encoder = true;
3661                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3662                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3663                                          DRM_MODE_ENCODER_LVDS, NULL);
3664                 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3665                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3666                                          DRM_MODE_ENCODER_DAC, NULL);
3667                 else
3668                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3669                                          DRM_MODE_ENCODER_TMDS, NULL);
3670                 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs);
3671                 break;
3672         }
3673 }
3674
3675 static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
3676         .bandwidth_update = &dce_v11_0_bandwidth_update,
3677         .vblank_get_counter = &dce_v11_0_vblank_get_counter,
3678         .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3679         .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3680         .hpd_sense = &dce_v11_0_hpd_sense,
3681         .hpd_set_polarity = &dce_v11_0_hpd_set_polarity,
3682         .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg,
3683         .page_flip = &dce_v11_0_page_flip,
3684         .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos,
3685         .add_encoder = &dce_v11_0_encoder_add,
3686         .add_connector = &amdgpu_connector_add,
3687 };
3688
3689 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
3690 {
3691         if (adev->mode_info.funcs == NULL)
3692                 adev->mode_info.funcs = &dce_v11_0_display_funcs;
3693 }
3694
3695 static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {
3696         .set = dce_v11_0_set_crtc_irq_state,
3697         .process = dce_v11_0_crtc_irq,
3698 };
3699
3700 static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = {
3701         .set = dce_v11_0_set_pageflip_irq_state,
3702         .process = dce_v11_0_pageflip_irq,
3703 };
3704
3705 static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = {
3706         .set = dce_v11_0_set_hpd_irq_state,
3707         .process = dce_v11_0_hpd_irq,
3708 };
3709
3710 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
3711 {
3712         if (adev->mode_info.num_crtc > 0)
3713                 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
3714         else
3715                 adev->crtc_irq.num_types = 0;
3716         adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
3717
3718         adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
3719         adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
3720
3721         adev->hpd_irq.num_types = adev->mode_info.num_hpd;
3722         adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;
3723 }
3724
3725 const struct amdgpu_ip_block_version dce_v11_0_ip_block =
3726 {
3727         .type = AMD_IP_BLOCK_TYPE_DCE,
3728         .major = 11,
3729         .minor = 0,
3730         .rev = 0,
3731         .funcs = &dce_v11_0_ip_funcs,
3732 };
3733
3734 const struct amdgpu_ip_block_version dce_v11_2_ip_block =
3735 {
3736         .type = AMD_IP_BLOCK_TYPE_DCE,
3737         .major = 11,
3738         .minor = 2,
3739         .rev = 0,
3740         .funcs = &dce_v11_0_ip_funcs,
3741 };