drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <linux/list.h>
  33 #include <linux/slab.h>
  34 #include <drm/drmP.h>
  35 #include <drm/amdgpu_drm.h>
  36 #include <drm/drm_cache.h>
  37 #include "amdgpu.h"
  38 #include "amdgpu_trace.h"
  39 #include "amdgpu_amdkfd.h"
  40
  41 static bool amdgpu_need_backup(struct amdgpu_device *adev)
  42 {
  43         if (adev->flags & AMD_IS_APU)
  44                 return false;
  45
  46         if (amdgpu_gpu_recovery == 0 ||
  47             (amdgpu_gpu_recovery == -1  && !amdgpu_sriov_vf(adev)))
  48                 return false;
  49
  50         return true;
  51 }
  52
  53 static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  54 {
  55         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
  56         struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
  57
  58         if (bo->kfd_bo)
  59                 amdgpu_amdkfd_unreserve_system_memory_limit(bo);
  60
  61         amdgpu_bo_kunmap(bo);
  62
  63         if (bo->gem_base.import_attach)
  64                 drm_prime_gem_destroy(&bo->gem_base, bo->tbo.sg);
  65         drm_gem_object_release(&bo->gem_base);
  66         amdgpu_bo_unref(&bo->parent);
  67         if (!list_empty(&bo->shadow_list)) {
  68                 mutex_lock(&adev->shadow_list_lock);
  69                 list_del_init(&bo->shadow_list);
  70                 mutex_unlock(&adev->shadow_list_lock);
  71         }
  72         kfree(bo->metadata);
  73         kfree(bo);
  74 }
  75
  76 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
  77 {
  78         if (bo->destroy == &amdgpu_ttm_bo_destroy)
  79                 return true;
  80         return false;
  81 }
  82
  83 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
  84 {
  85         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
  86         struct ttm_placement *placement = &abo->placement;
  87         struct ttm_place *places = abo->placements;
  88         u64 flags = abo->flags;
  89         u32 c = 0;
  90
  91         if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
  92                 unsigned visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
  93
  94                 places[c].fpfn = 0;
  95                 places[c].lpfn = 0;
  96                 places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
  97                         TTM_PL_FLAG_VRAM;
  98
  99                 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
 100                         places[c].lpfn = visible_pfn;
 101                 else
 102                         places[c].flags |= TTM_PL_FLAG_TOPDOWN;
 103
 104                 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
 105                         places[c].flags |= TTM_PL_FLAG_CONTIGUOUS;
 106                 c++;
 107         }
 108
 109         if (domain & AMDGPU_GEM_DOMAIN_GTT) {
 110                 places[c].fpfn = 0;
 111                 if (flags & AMDGPU_GEM_CREATE_SHADOW)
 112                         places[c].lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
 113                 else
 114                         places[c].lpfn = 0;
 115                 places[c].flags = TTM_PL_FLAG_TT;
 116                 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 117                         places[c].flags |= TTM_PL_FLAG_WC |
 118                                 TTM_PL_FLAG_UNCACHED;
 119                 else
 120                         places[c].flags |= TTM_PL_FLAG_CACHED;
 121                 c++;
 122         }
 123
 124         if (domain & AMDGPU_GEM_DOMAIN_CPU) {
 125                 places[c].fpfn = 0;
 126                 places[c].lpfn = 0;
 127                 places[c].flags = TTM_PL_FLAG_SYSTEM;
 128                 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 129                         places[c].flags |= TTM_PL_FLAG_WC |
 130                                 TTM_PL_FLAG_UNCACHED;
 131                 else
 132                         places[c].flags |= TTM_PL_FLAG_CACHED;
 133                 c++;
 134         }
 135
 136         if (domain & AMDGPU_GEM_DOMAIN_GDS) {
 137                 places[c].fpfn = 0;
 138                 places[c].lpfn = 0;
 139                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GDS;
 140                 c++;
 141         }
 142
 143         if (domain & AMDGPU_GEM_DOMAIN_GWS) {
 144                 places[c].fpfn = 0;
 145                 places[c].lpfn = 0;
 146                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GWS;
 147                 c++;
 148         }
 149
 150         if (domain & AMDGPU_GEM_DOMAIN_OA) {
 151                 places[c].fpfn = 0;
 152                 places[c].lpfn = 0;
 153                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_OA;
 154                 c++;
 155         }
 156
 157         if (!c) {
 158                 places[c].fpfn = 0;
 159                 places[c].lpfn = 0;
 160                 places[c].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
 161                 c++;
 162         }
 163
 164         placement->num_placement = c;
 165         placement->placement = places;
 166
 167         placement->num_busy_placement = c;
 168         placement->busy_placement = places;
 169 }
 170
 171 /**
 172  * amdgpu_bo_create_reserved - create reserved BO for kernel use
 173  *
 174  * @adev: amdgpu device object
 175  * @size: size for the new BO
 176  * @align: alignment for the new BO
 177  * @domain: where to place it
 178  * @bo_ptr: used to initialize BOs in structures
 179  * @gpu_addr: GPU addr of the pinned BO
 180  * @cpu_addr: optional CPU address mapping
 181  *
 182  * Allocates and pins a BO for kernel internal use, and returns it still
 183  * reserved.
 184  *
 185  * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
 186  *
 187  * Returns 0 on success, negative error code otherwise.
 188  */
 189 int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
 190                               unsigned long size, int align,
 191                               u32 domain, struct amdgpu_bo **bo_ptr,
 192                               u64 *gpu_addr, void **cpu_addr)
 193 {
 194         struct amdgpu_bo_param bp;
 195         bool free = false;
 196         int r;
 197
 198         memset(&bp, 0, sizeof(bp));
 199         bp.size = size;
 200         bp.byte_align = align;
 201         bp.domain = domain;
 202         bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
 203                 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
 204         bp.type = ttm_bo_type_kernel;
 205         bp.resv = NULL;
 206
 207         if (!*bo_ptr) {
 208                 r = amdgpu_bo_create(adev, &bp, bo_ptr);
 209                 if (r) {
 210                         dev_err(adev->dev, "(%d) failed to allocate kernel bo\n",
 211                                 r);
 212                         return r;
 213                 }
 214                 free = true;
 215         }
 216
 217         r = amdgpu_bo_reserve(*bo_ptr, false);
 218         if (r) {
 219                 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r);
 220                 goto error_free;
 221         }
 222
 223         r = amdgpu_bo_pin(*bo_ptr, domain, gpu_addr);
 224         if (r) {
 225                 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r);
 226                 goto error_unreserve;
 227         }
 228
 229         if (cpu_addr) {
 230                 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
 231                 if (r) {
 232                         dev_err(adev->dev, "(%d) kernel bo map failed\n", r);
 233                         goto error_unreserve;
 234                 }
 235         }
 236
 237         return 0;
 238
 239 error_unreserve:
 240         amdgpu_bo_unreserve(*bo_ptr);
 241
 242 error_free:
 243         if (free)
 244                 amdgpu_bo_unref(bo_ptr);
 245
 246         return r;
 247 }
 248
 249 /**
 250  * amdgpu_bo_create_kernel - create BO for kernel use
 251  *
 252  * @adev: amdgpu device object
 253  * @size: size for the new BO
 254  * @align: alignment for the new BO
 255  * @domain: where to place it
 256  * @bo_ptr:  used to initialize BOs in structures
 257  * @gpu_addr: GPU addr of the pinned BO
 258  * @cpu_addr: optional CPU address mapping
 259  *
 260  * Allocates and pins a BO for kernel internal use.
 261  *
 262  * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
 263  *
 264  * Returns 0 on success, negative error code otherwise.
 265  */
 266 int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
 267                             unsigned long size, int align,
 268                             u32 domain, struct amdgpu_bo **bo_ptr,
 269                             u64 *gpu_addr, void **cpu_addr)
 270 {
 271         int r;
 272
 273         r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr,
 274                                       gpu_addr, cpu_addr);
 275
 276         if (r)
 277                 return r;
 278
 279         amdgpu_bo_unreserve(*bo_ptr);
 280
 281         return 0;
 282 }
 283
 284 /**
 285  * amdgpu_bo_free_kernel - free BO for kernel use
 286  *
 287  * @bo: amdgpu BO to free
 288  *
 289  * unmaps and unpin a BO for kernel internal use.
 290  */
 291 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
 292                            void **cpu_addr)
 293 {
 294         if (*bo == NULL)
 295                 return;
 296
 297         if (likely(amdgpu_bo_reserve(*bo, true) == 0)) {
 298                 if (cpu_addr)
 299                         amdgpu_bo_kunmap(*bo);
 300
 301                 amdgpu_bo_unpin(*bo);
 302                 amdgpu_bo_unreserve(*bo);
 303         }
 304         amdgpu_bo_unref(bo);
 305
 306         if (gpu_addr)
 307                 *gpu_addr = 0;
 308
 309         if (cpu_addr)
 310                 *cpu_addr = NULL;
 311 }
 312
 313 /* Validate bo size is bit bigger then the request domain */
 314 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev,
 315                                           unsigned long size, u32 domain)
 316 {
 317         struct ttm_mem_type_manager *man = NULL;
 318
 319         /*
 320          * If GTT is part of requested domains the check must succeed to
 321          * allow fall back to GTT
 322          */
 323         if (domain & AMDGPU_GEM_DOMAIN_GTT) {
 324                 man = &adev->mman.bdev.man[TTM_PL_TT];
 325
 326                 if (size < (man->size << PAGE_SHIFT))
 327                         return true;
 328                 else
 329                         goto fail;
 330         }
 331
 332         if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
 333                 man = &adev->mman.bdev.man[TTM_PL_VRAM];
 334
 335                 if (size < (man->size << PAGE_SHIFT))
 336                         return true;
 337                 else
 338                         goto fail;
 339         }
 340
 341
 342         /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */
 343         return true;
 344
 345 fail:
 346         DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size,
 347                   man->size << PAGE_SHIFT);
 348         return false;
 349 }
 350
 351 static int amdgpu_bo_do_create(struct amdgpu_device *adev,
 352                                struct amdgpu_bo_param *bp,
 353                                struct amdgpu_bo **bo_ptr)
 354 {
 355         struct ttm_operation_ctx ctx = {
 356                 .interruptible = (bp->type != ttm_bo_type_kernel),
 357                 .no_wait_gpu = false,
 358                 .resv = bp->resv,
 359                 .flags = TTM_OPT_FLAG_ALLOW_RES_EVICT
 360         };
 361         struct amdgpu_bo *bo;
 362         unsigned long page_align, size = bp->size;
 363         size_t acc_size;
 364         int r;
 365
 366         page_align = roundup(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT;
 367         size = ALIGN(size, PAGE_SIZE);
 368
 369         if (!amdgpu_bo_validate_size(adev, size, bp->domain))
 370                 return -ENOMEM;
 371
 372         *bo_ptr = NULL;
 373
 374         acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
 375                                        sizeof(struct amdgpu_bo));
 376
 377         bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL);
 378         if (bo == NULL)
 379                 return -ENOMEM;
 380         drm_gem_private_object_init(adev->ddev, &bo->gem_base, size);
 381         INIT_LIST_HEAD(&bo->shadow_list);
 382         INIT_LIST_HEAD(&bo->va);
 383         bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain :
 384                 bp->domain;
 385         bo->allowed_domains = bo->preferred_domains;
 386         if (bp->type != ttm_bo_type_kernel &&
 387             bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
 388                 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
 389
 390         bo->flags = bp->flags;
 391
 392 #ifdef CONFIG_X86_32
 393         /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
 394          * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
 395          */
 396         bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 397 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
 398         /* Don't try to enable write-combining when it can't work, or things
 399          * may be slow
 400          * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
 401          */
 402
 403 #ifndef CONFIG_COMPILE_TEST
 404 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
 405          thanks to write-combining
 406 #endif
 407
 408         if (bo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 409                 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
 410                               "better performance thanks to write-combining\n");
 411         bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 412 #else
 413         /* For architectures that don't support WC memory,
 414          * mask out the WC flag from the BO
 415          */
 416         if (!drm_arch_can_wc_memory())
 417                 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 418 #endif
 419
 420         bo->tbo.bdev = &adev->mman.bdev;
 421         amdgpu_ttm_placement_from_domain(bo, bp->domain);
 422         if (bp->type == ttm_bo_type_kernel)
 423                 bo->tbo.priority = 1;
 424
 425         r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, bp->type,
 426                                  &bo->placement, page_align, &ctx, acc_size,
 427                                  NULL, bp->resv, &amdgpu_ttm_bo_destroy);
 428         if (unlikely(r != 0))
 429                 return r;
 430
 431         if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
 432             bo->tbo.mem.mem_type == TTM_PL_VRAM &&
 433             bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT)
 434                 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved,
 435                                              ctx.bytes_moved);
 436         else
 437                 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0);
 438
 439         if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
 440             bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) {
 441                 struct dma_fence *fence;
 442
 443                 r = amdgpu_fill_buffer(bo, 0, bo->tbo.resv, &fence);
 444                 if (unlikely(r))
 445                         goto fail_unreserve;
 446
 447                 amdgpu_bo_fence(bo, fence, false);
 448                 dma_fence_put(bo->tbo.moving);
 449                 bo->tbo.moving = dma_fence_get(fence);
 450                 dma_fence_put(fence);
 451         }
 452         if (!bp->resv)
 453                 amdgpu_bo_unreserve(bo);
 454         *bo_ptr = bo;
 455
 456         trace_amdgpu_bo_create(bo);
 457
 458         /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */
 459         if (bp->type == ttm_bo_type_device)
 460                 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 461
 462         return 0;
 463
 464 fail_unreserve:
 465         if (!bp->resv)
 466                 ww_mutex_unlock(&bo->tbo.resv->lock);
 467         amdgpu_bo_unref(&bo);
 468         return r;
 469 }
 470
 471 static int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
 472                                    unsigned long size, int byte_align,
 473                                    struct amdgpu_bo *bo)
 474 {
 475         struct amdgpu_bo_param bp;
 476         int r;
 477
 478         if (bo->shadow)
 479                 return 0;
 480
 481         memset(&bp, 0, sizeof(bp));
 482         bp.size = size;
 483         bp.byte_align = byte_align;
 484         bp.domain = AMDGPU_GEM_DOMAIN_GTT;
 485         bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC |
 486                 AMDGPU_GEM_CREATE_SHADOW;
 487         bp.type = ttm_bo_type_kernel;
 488         bp.resv = bo->tbo.resv;
 489
 490         r = amdgpu_bo_do_create(adev, &bp, &bo->shadow);
 491         if (!r) {
 492                 bo->shadow->parent = amdgpu_bo_ref(bo);
 493                 mutex_lock(&adev->shadow_list_lock);
 494                 list_add_tail(&bo->shadow_list, &adev->shadow_list);
 495                 mutex_unlock(&adev->shadow_list_lock);
 496         }
 497
 498         return r;
 499 }
 500
 501 int amdgpu_bo_create(struct amdgpu_device *adev,
 502                      struct amdgpu_bo_param *bp,
 503                      struct amdgpu_bo **bo_ptr)
 504 {
 505         u64 flags = bp->flags;
 506         int r;
 507
 508         bp->flags = bp->flags & ~AMDGPU_GEM_CREATE_SHADOW;
 509         r = amdgpu_bo_do_create(adev, bp, bo_ptr);
 510         if (r)
 511                 return r;
 512
 513         if ((flags & AMDGPU_GEM_CREATE_SHADOW) && amdgpu_need_backup(adev)) {
 514                 if (!bp->resv)
 515                         WARN_ON(reservation_object_lock((*bo_ptr)->tbo.resv,
 516                                                         NULL));
 517
 518                 r = amdgpu_bo_create_shadow(adev, bp->size, bp->byte_align, (*bo_ptr));
 519
 520                 if (!bp->resv)
 521                         reservation_object_unlock((*bo_ptr)->tbo.resv);
 522
 523                 if (r)
 524                         amdgpu_bo_unref(bo_ptr);
 525         }
 526
 527         return r;
 528 }
 529
 530 int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev,
 531                                struct amdgpu_ring *ring,
 532                                struct amdgpu_bo *bo,
 533                                struct reservation_object *resv,
 534                                struct dma_fence **fence,
 535                                bool direct)
 536
 537 {
 538         struct amdgpu_bo *shadow = bo->shadow;
 539         uint64_t bo_addr, shadow_addr;
 540         int r;
 541
 542         if (!shadow)
 543                 return -EINVAL;
 544
 545         bo_addr = amdgpu_bo_gpu_offset(bo);
 546         shadow_addr = amdgpu_bo_gpu_offset(bo->shadow);
 547
 548         r = reservation_object_reserve_shared(bo->tbo.resv);
 549         if (r)
 550                 goto err;
 551
 552         r = amdgpu_copy_buffer(ring, bo_addr, shadow_addr,
 553                                amdgpu_bo_size(bo), resv, fence,
 554                                direct, false);
 555         if (!r)
 556                 amdgpu_bo_fence(bo, *fence, true);
 557
 558 err:
 559         return r;
 560 }
 561
 562 int amdgpu_bo_validate(struct amdgpu_bo *bo)
 563 {
 564         struct ttm_operation_ctx ctx = { false, false };
 565         uint32_t domain;
 566         int r;
 567
 568         if (bo->pin_count)
 569                 return 0;
 570
 571         domain = bo->preferred_domains;
 572
 573 retry:
 574         amdgpu_ttm_placement_from_domain(bo, domain);
 575         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 576         if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
 577                 domain = bo->allowed_domains;
 578                 goto retry;
 579         }
 580
 581         return r;
 582 }
 583
 584 int amdgpu_bo_restore_from_shadow(struct amdgpu_device *adev,
 585                                   struct amdgpu_ring *ring,
 586                                   struct amdgpu_bo *bo,
 587                                   struct reservation_object *resv,
 588                                   struct dma_fence **fence,
 589                                   bool direct)
 590
 591 {
 592         struct amdgpu_bo *shadow = bo->shadow;
 593         uint64_t bo_addr, shadow_addr;
 594         int r;
 595
 596         if (!shadow)
 597                 return -EINVAL;
 598
 599         bo_addr = amdgpu_bo_gpu_offset(bo);
 600         shadow_addr = amdgpu_bo_gpu_offset(bo->shadow);
 601
 602         r = reservation_object_reserve_shared(bo->tbo.resv);
 603         if (r)
 604                 goto err;
 605
 606         r = amdgpu_copy_buffer(ring, shadow_addr, bo_addr,
 607                                amdgpu_bo_size(bo), resv, fence,
 608                                direct, false);
 609         if (!r)
 610                 amdgpu_bo_fence(bo, *fence, true);
 611
 612 err:
 613         return r;
 614 }
 615
 616 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
 617 {
 618         void *kptr;
 619         long r;
 620
 621         if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 622                 return -EPERM;
 623
 624         kptr = amdgpu_bo_kptr(bo);
 625         if (kptr) {
 626                 if (ptr)
 627                         *ptr = kptr;
 628                 return 0;
 629         }
 630
 631         r = reservation_object_wait_timeout_rcu(bo->tbo.resv, false, false,
 632                                                 MAX_SCHEDULE_TIMEOUT);
 633         if (r < 0)
 634                 return r;
 635
 636         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
 637         if (r)
 638                 return r;
 639
 640         if (ptr)
 641                 *ptr = amdgpu_bo_kptr(bo);
 642
 643         return 0;
 644 }
 645
 646 void *amdgpu_bo_kptr(struct amdgpu_bo *bo)
 647 {
 648         bool is_iomem;
 649
 650         return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
 651 }
 652
 653 void amdgpu_bo_kunmap(struct amdgpu_bo *bo)
 654 {
 655         if (bo->kmap.bo)
 656                 ttm_bo_kunmap(&bo->kmap);
 657 }
 658
 659 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)
 660 {
 661         if (bo == NULL)
 662                 return NULL;
 663
 664         ttm_bo_reference(&bo->tbo);
 665         return bo;
 666 }
 667
 668 void amdgpu_bo_unref(struct amdgpu_bo **bo)
 669 {
 670         struct ttm_buffer_object *tbo;
 671
 672         if ((*bo) == NULL)
 673                 return;
 674
 675         tbo = &((*bo)->tbo);
 676         ttm_bo_unref(&tbo);
 677         if (tbo == NULL)
 678                 *bo = NULL;
 679 }
 680
 681 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
 682                              u64 min_offset, u64 max_offset,
 683                              u64 *gpu_addr)
 684 {
 685         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 686         struct ttm_operation_ctx ctx = { false, false };
 687         int r, i;
 688
 689         if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
 690                 return -EPERM;
 691
 692         if (WARN_ON_ONCE(min_offset > max_offset))
 693                 return -EINVAL;
 694
 695         /* A shared bo cannot be migrated to VRAM */
 696         if (bo->prime_shared_count) {
 697                 if (domain & AMDGPU_GEM_DOMAIN_GTT)
 698                         domain = AMDGPU_GEM_DOMAIN_GTT;
 699                 else
 700                         return -EINVAL;
 701         }
 702
 703         /* This assumes only APU display buffers are pinned with (VRAM|GTT).
 704          * See function amdgpu_display_supported_domains()
 705          */
 706         domain = amdgpu_bo_get_preferred_pin_domain(adev, domain);
 707
 708         if (bo->pin_count) {
 709                 uint32_t mem_type = bo->tbo.mem.mem_type;
 710
 711                 if (!(domain & amdgpu_mem_type_to_domain(mem_type)))
 712                         return -EINVAL;
 713
 714                 bo->pin_count++;
 715                 if (gpu_addr)
 716                         *gpu_addr = amdgpu_bo_gpu_offset(bo);
 717
 718                 if (max_offset != 0) {
 719                         u64 domain_start = bo->tbo.bdev->man[mem_type].gpu_offset;
 720                         WARN_ON_ONCE(max_offset <
 721                                      (amdgpu_bo_gpu_offset(bo) - domain_start));
 722                 }
 723
 724                 return 0;
 725         }
 726
 727         bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
 728         /* force to pin into visible video ram */
 729         if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS))
 730                 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 731         amdgpu_ttm_placement_from_domain(bo, domain);
 732         for (i = 0; i < bo->placement.num_placement; i++) {
 733                 unsigned fpfn, lpfn;
 734
 735                 fpfn = min_offset >> PAGE_SHIFT;
 736                 lpfn = max_offset >> PAGE_SHIFT;
 737
 738                 if (fpfn > bo->placements[i].fpfn)
 739                         bo->placements[i].fpfn = fpfn;
 740                 if (!bo->placements[i].lpfn ||
 741                     (lpfn && lpfn < bo->placements[i].lpfn))
 742                         bo->placements[i].lpfn = lpfn;
 743                 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
 744         }
 745
 746         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 747         if (unlikely(r)) {
 748                 dev_err(adev->dev, "%p pin failed\n", bo);
 749                 goto error;
 750         }
 751
 752         r = amdgpu_ttm_alloc_gart(&bo->tbo);
 753         if (unlikely(r)) {
 754                 dev_err(adev->dev, "%p bind failed\n", bo);
 755                 goto error;
 756         }
 757
 758         bo->pin_count = 1;
 759         if (gpu_addr != NULL)
 760                 *gpu_addr = amdgpu_bo_gpu_offset(bo);
 761
 762         domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 763         if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
 764                 adev->vram_pin_size += amdgpu_bo_size(bo);
 765                 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 766                         adev->invisible_pin_size += amdgpu_bo_size(bo);
 767         } else if (domain == AMDGPU_GEM_DOMAIN_GTT) {
 768                 adev->gart_pin_size += amdgpu_bo_size(bo);
 769         }
 770
 771 error:
 772         return r;
 773 }
 774
 775 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr)
 776 {
 777         return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr);
 778 }
 779
 780 int amdgpu_bo_unpin(struct amdgpu_bo *bo)
 781 {
 782         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 783         struct ttm_operation_ctx ctx = { false, false };
 784         int r, i;
 785
 786         if (!bo->pin_count) {
 787                 dev_warn(adev->dev, "%p unpin not necessary\n", bo);
 788                 return 0;
 789         }
 790         bo->pin_count--;
 791         if (bo->pin_count)
 792                 return 0;
 793         for (i = 0; i < bo->placement.num_placement; i++) {
 794                 bo->placements[i].lpfn = 0;
 795                 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
 796         }
 797         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 798         if (unlikely(r)) {
 799                 dev_err(adev->dev, "%p validate failed for unpin\n", bo);
 800                 goto error;
 801         }
 802
 803         if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
 804                 adev->vram_pin_size -= amdgpu_bo_size(bo);
 805                 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 806                         adev->invisible_pin_size -= amdgpu_bo_size(bo);
 807         } else if (bo->tbo.mem.mem_type == TTM_PL_TT) {
 808                 adev->gart_pin_size -= amdgpu_bo_size(bo);
 809         }
 810
 811 error:
 812         return r;
 813 }
 814
 815 int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
 816 {
 817         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
 818         if (0 && (adev->flags & AMD_IS_APU)) {
 819                 /* Useless to evict on IGP chips */
 820                 return 0;
 821         }
 822         return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM);
 823 }
 824
 825 static const char *amdgpu_vram_names[] = {
 826         "UNKNOWN",
 827         "GDDR1",
 828         "DDR2",
 829         "GDDR3",
 830         "GDDR4",
 831         "GDDR5",
 832         "HBM",
 833         "DDR3",
 834         "DDR4",
 835 };
 836
 837 int amdgpu_bo_init(struct amdgpu_device *adev)
 838 {
 839         /* reserve PAT memory space to WC for VRAM */
 840         arch_io_reserve_memtype_wc(adev->gmc.aper_base,
 841                                    adev->gmc.aper_size);
 842
 843         /* Add an MTRR for the VRAM */
 844         adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base,
 845                                               adev->gmc.aper_size);
 846         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
 847                  adev->gmc.mc_vram_size >> 20,
 848                  (unsigned long long)adev->gmc.aper_size >> 20);
 849         DRM_INFO("RAM width %dbits %s\n",
 850                  adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]);
 851         return amdgpu_ttm_init(adev);
 852 }
 853
 854 int amdgpu_bo_late_init(struct amdgpu_device *adev)
 855 {
 856         amdgpu_ttm_late_init(adev);
 857
 858         return 0;
 859 }
 860
 861 void amdgpu_bo_fini(struct amdgpu_device *adev)
 862 {
 863         amdgpu_ttm_fini(adev);
 864         arch_phys_wc_del(adev->gmc.vram_mtrr);
 865         arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
 866 }
 867
 868 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
 869                              struct vm_area_struct *vma)
 870 {
 871         return ttm_fbdev_mmap(vma, &bo->tbo);
 872 }
 873
 874 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
 875 {
 876         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 877
 878         if (adev->family <= AMDGPU_FAMILY_CZ &&
 879             AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
 880                 return -EINVAL;
 881
 882         bo->tiling_flags = tiling_flags;
 883         return 0;
 884 }
 885
 886 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
 887 {
 888         lockdep_assert_held(&bo->tbo.resv->lock.base);
 889
 890         if (tiling_flags)
 891                 *tiling_flags = bo->tiling_flags;
 892 }
 893
 894 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
 895                             uint32_t metadata_size, uint64_t flags)
 896 {
 897         void *buffer;
 898
 899         if (!metadata_size) {
 900                 if (bo->metadata_size) {
 901                         kfree(bo->metadata);
 902                         bo->metadata = NULL;
 903                         bo->metadata_size = 0;
 904                 }
 905                 return 0;
 906         }
 907
 908         if (metadata == NULL)
 909                 return -EINVAL;
 910
 911         buffer = kmemdup(metadata, metadata_size, GFP_KERNEL);
 912         if (buffer == NULL)
 913                 return -ENOMEM;
 914
 915         kfree(bo->metadata);
 916         bo->metadata_flags = flags;
 917         bo->metadata = buffer;
 918         bo->metadata_size = metadata_size;
 919
 920         return 0;
 921 }
 922
 923 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
 924                            size_t buffer_size, uint32_t *metadata_size,
 925                            uint64_t *flags)
 926 {
 927         if (!buffer && !metadata_size)
 928                 return -EINVAL;
 929
 930         if (buffer) {
 931                 if (buffer_size < bo->metadata_size)
 932                         return -EINVAL;
 933
 934                 if (bo->metadata_size)
 935                         memcpy(buffer, bo->metadata, bo->metadata_size);
 936         }
 937
 938         if (metadata_size)
 939                 *metadata_size = bo->metadata_size;
 940         if (flags)
 941                 *flags = bo->metadata_flags;
 942
 943         return 0;
 944 }
 945
 946 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
 947                            bool evict,
 948                            struct ttm_mem_reg *new_mem)
 949 {
 950         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 951         struct amdgpu_bo *abo;
 952         struct ttm_mem_reg *old_mem = &bo->mem;
 953
 954         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
 955                 return;
 956
 957         abo = ttm_to_amdgpu_bo(bo);
 958         amdgpu_vm_bo_invalidate(adev, abo, evict);
 959
 960         amdgpu_bo_kunmap(abo);
 961
 962         /* remember the eviction */
 963         if (evict)
 964                 atomic64_inc(&adev->num_evictions);
 965
 966         /* update statistics */
 967         if (!new_mem)
 968                 return;
 969
 970         /* move_notify is called before move happens */
 971         trace_amdgpu_ttm_bo_move(abo, new_mem->mem_type, old_mem->mem_type);
 972 }
 973
 974 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 975 {
 976         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 977         struct ttm_operation_ctx ctx = { false, false };
 978         struct amdgpu_bo *abo;
 979         unsigned long offset, size;
 980         int r;
 981
 982         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
 983                 return 0;
 984
 985         abo = ttm_to_amdgpu_bo(bo);
 986
 987         /* Remember that this BO was accessed by the CPU */
 988         abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 989
 990         if (bo->mem.mem_type != TTM_PL_VRAM)
 991                 return 0;
 992
 993         size = bo->mem.num_pages << PAGE_SHIFT;
 994         offset = bo->mem.start << PAGE_SHIFT;
 995         if ((offset + size) <= adev->gmc.visible_vram_size)
 996                 return 0;
 997
 998         /* Can't move a pinned BO to visible VRAM */
 999         if (abo->pin_count > 0)
1000                 return -EINVAL;
1001
1002         /* hurrah the memory is not visible ! */
1003         atomic64_inc(&adev->num_vram_cpu_page_faults);
1004         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
1005                                          AMDGPU_GEM_DOMAIN_GTT);
1006
1007         /* Avoid costly evictions; only set GTT as a busy placement */
1008         abo->placement.num_busy_placement = 1;
1009         abo->placement.busy_placement = &abo->placements[1];
1010
1011         r = ttm_bo_validate(bo, &abo->placement, &ctx);
1012         if (unlikely(r != 0))
1013                 return r;
1014
1015         offset = bo->mem.start << PAGE_SHIFT;
1016         /* this should never happen */
1017         if (bo->mem.mem_type == TTM_PL_VRAM &&
1018             (offset + size) > adev->gmc.visible_vram_size)
1019                 return -EINVAL;
1020
1021         return 0;
1022 }
1023
1024 /**
1025  * amdgpu_bo_fence - add fence to buffer object
1026  *
1027  * @bo: buffer object in question
1028  * @fence: fence to add
1029  * @shared: true if fence should be added shared
1030  *
1031  */
1032 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
1033                      bool shared)
1034 {
1035         struct reservation_object *resv = bo->tbo.resv;
1036
1037         if (shared)
1038                 reservation_object_add_shared_fence(resv, fence);
1039         else
1040                 reservation_object_add_excl_fence(resv, fence);
1041 }
1042
1043 /**
1044  * amdgpu_bo_gpu_offset - return GPU offset of bo
1045  * @bo: amdgpu object for which we query the offset
1046  *
1047  * Returns current GPU offset of the object.
1048  *
1049  * Note: object should either be pinned or reserved when calling this
1050  * function, it might be useful to add check for this for debugging.
1051  */
1052 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
1053 {
1054         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM);
1055         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_TT &&
1056                      !amdgpu_gtt_mgr_has_gart_addr(&bo->tbo.mem));
1057         WARN_ON_ONCE(!ww_mutex_is_locked(&bo->tbo.resv->lock) &&
1058                      !bo->pin_count);
1059         WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET);
1060         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM &&
1061                      !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS));
1062
1063         return bo->tbo.offset;
1064 }
1065
1066 uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev,
1067                                             uint32_t domain)
1068 {
1069         if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) {
1070                 domain = AMDGPU_GEM_DOMAIN_VRAM;
1071                 if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD)
1072                         domain = AMDGPU_GEM_DOMAIN_GTT;
1073         }
1074         return domain;
1075 }