drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "kfd_device_queue_manager.h"
  25 #include "gca/gfx_8_0_enum.h"
  26 #include "gca/gfx_8_0_sh_mask.h"
  27 #include "gca/gfx_8_0_enum.h"
  28 #include "oss/oss_3_0_sh_mask.h"
  29
  30 static bool set_cache_memory_policy_vi(struct device_queue_manager *dqm,
  31                                    struct qcm_process_device *qpd,
  32                                    enum cache_policy default_policy,
  33                                    enum cache_policy alternate_policy,
  34                                    void __user *alternate_aperture_base,
  35                                    uint64_t alternate_aperture_size);
  36 static int update_qpd_vi(struct device_queue_manager *dqm,
  37                                         struct qcm_process_device *qpd);
  38 static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q,
  39                                 struct qcm_process_device *qpd);
  40
  41 void device_queue_manager_init_vi(
  42                 struct device_queue_manager_asic_ops *asic_ops)
  43 {
  44         asic_ops->set_cache_memory_policy = set_cache_memory_policy_vi;
  45         asic_ops->update_qpd = update_qpd_vi;
  46         asic_ops->init_sdma_vm = init_sdma_vm;
  47 }
  48
  49 static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble)
  50 {
  51         /* In 64-bit mode, we can only control the top 3 bits of the LDS,
  52          * scratch and GPUVM apertures.
  53          * The hardware fills in the remaining 59 bits according to the
  54          * following pattern:
  55          * LDS:         X0000000'00000000 - X0000001'00000000 (4GB)
  56          * Scratch:     X0000001'00000000 - X0000002'00000000 (4GB)
  57          * GPUVM:       Y0010000'00000000 - Y0020000'00000000 (1TB)
  58          *
  59          * (where X/Y is the configurable nybble with the low-bit 0)
  60          *
  61          * LDS and scratch will have the same top nybble programmed in the
  62          * top 3 bits of SH_MEM_BASES.PRIVATE_BASE.
  63          * GPUVM can have a different top nybble programmed in the
  64          * top 3 bits of SH_MEM_BASES.SHARED_BASE.
  65          * We don't bother to support different top nybbles
  66          * for LDS/Scratch and GPUVM.
  67          */
  68
  69         WARN_ON((top_address_nybble & 1) || top_address_nybble > 0xE ||
  70                 top_address_nybble == 0);
  71
  72         return top_address_nybble << 12 |
  73                         (top_address_nybble << 12) <<
  74                         SH_MEM_BASES__SHARED_BASE__SHIFT;
  75 }
  76
  77 static bool set_cache_memory_policy_vi(struct device_queue_manager *dqm,
  78                                    struct qcm_process_device *qpd,
  79                                    enum cache_policy default_policy,
  80                                    enum cache_policy alternate_policy,
  81                                    void __user *alternate_aperture_base,
  82                                    uint64_t alternate_aperture_size)
  83 {
  84         uint32_t default_mtype;
  85         uint32_t ape1_mtype;
  86
  87         default_mtype = (default_policy == cache_policy_coherent) ?
  88                         MTYPE_CC :
  89                         MTYPE_NC;
  90
  91         ape1_mtype = (alternate_policy == cache_policy_coherent) ?
  92                         MTYPE_CC :
  93                         MTYPE_NC;
  94
  95         qpd->sh_mem_config = (qpd->sh_mem_config &
  96                         SH_MEM_CONFIG__ADDRESS_MODE_MASK) |
  97                 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
  98                                 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
  99                 default_mtype << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
 100                 ape1_mtype << SH_MEM_CONFIG__APE1_MTYPE__SHIFT |
 101                 SH_MEM_CONFIG__PRIVATE_ATC_MASK;
 102
 103         return true;
 104 }
 105
 106 static int update_qpd_vi(struct device_queue_manager *dqm,
 107                                         struct qcm_process_device *qpd)
 108 {
 109         struct kfd_process_device *pdd;
 110         unsigned int temp;
 111
 112         pdd = qpd_to_pdd(qpd);
 113
 114         /* check if sh_mem_config register already configured */
 115         if (qpd->sh_mem_config == 0) {
 116                 qpd->sh_mem_config =
 117                         SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
 118                                 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
 119                         MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
 120                         MTYPE_CC << SH_MEM_CONFIG__APE1_MTYPE__SHIFT |
 121                         SH_MEM_CONFIG__PRIVATE_ATC_MASK;
 122
 123                 qpd->sh_mem_ape1_limit = 0;
 124                 qpd->sh_mem_ape1_base = 0;
 125         }
 126
 127         if (qpd->pqm->process->is_32bit_user_mode) {
 128                 temp = get_sh_mem_bases_32(pdd);
 129                 qpd->sh_mem_bases = temp << SH_MEM_BASES__SHARED_BASE__SHIFT;
 130                 qpd->sh_mem_config |= SH_MEM_ADDRESS_MODE_HSA32 <<
 131                                         SH_MEM_CONFIG__ADDRESS_MODE__SHIFT;
 132         } else {
 133                 temp = get_sh_mem_bases_nybble_64(pdd);
 134                 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp);
 135                 qpd->sh_mem_config |= SH_MEM_ADDRESS_MODE_HSA64 <<
 136                         SH_MEM_CONFIG__ADDRESS_MODE__SHIFT;
 137                 qpd->sh_mem_config |= 1  <<
 138                         SH_MEM_CONFIG__PRIVATE_ATC__SHIFT;
 139         }
 140
 141         pr_debug("is32bit process: %d sh_mem_bases nybble: 0x%X and register 0x%X\n",
 142                 qpd->pqm->process->is_32bit_user_mode, temp, qpd->sh_mem_bases);
 143
 144         return 0;
 145 }
 146
 147 static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q,
 148                                 struct qcm_process_device *qpd)
 149 {
 150         uint32_t value = (1 << SDMA0_RLC0_VIRTUAL_ADDR__ATC__SHIFT);
 151
 152         if (q->process->is_32bit_user_mode)
 153                 value |= (1 << SDMA0_RLC0_VIRTUAL_ADDR__PTR32__SHIFT) |
 154                                 get_sh_mem_bases_32(qpd_to_pdd(qpd));
 155         else
 156                 value |= ((get_sh_mem_bases_nybble_64(qpd_to_pdd(qpd))) <<
 157                                 SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT) &
 158                                 SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK;
 159
 160         q->properties.sdma_vm_addr = value;
 161 }