drivers/gpu/drm/amd/amdgpu/psp_v10_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_psp.h"
  29 #include "amdgpu_ucode.h"
  30 #include "soc15_common.h"
  31 #include "psp_v10_0.h"
  32
  33 #include "vega10/soc15ip.h"
  34 #include "raven1/MP/mp_10_0_offset.h"
  35 #include "raven1/GC/gc_9_1_offset.h"
  36 #include "raven1/SDMA0/sdma0_4_1_offset.h"
  37
  38 MODULE_FIRMWARE("amdgpu/raven_asd.bin");
  39
  40 static int
  41 psp_v10_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type)
  42 {
  43         switch(ucode->ucode_id) {
  44         case AMDGPU_UCODE_ID_SDMA0:
  45                 *type = GFX_FW_TYPE_SDMA0;
  46                 break;
  47         case AMDGPU_UCODE_ID_SDMA1:
  48                 *type = GFX_FW_TYPE_SDMA1;
  49                 break;
  50         case AMDGPU_UCODE_ID_CP_CE:
  51                 *type = GFX_FW_TYPE_CP_CE;
  52                 break;
  53         case AMDGPU_UCODE_ID_CP_PFP:
  54                 *type = GFX_FW_TYPE_CP_PFP;
  55                 break;
  56         case AMDGPU_UCODE_ID_CP_ME:
  57                 *type = GFX_FW_TYPE_CP_ME;
  58                 break;
  59         case AMDGPU_UCODE_ID_CP_MEC1:
  60                 *type = GFX_FW_TYPE_CP_MEC;
  61                 break;
  62         case AMDGPU_UCODE_ID_CP_MEC1_JT:
  63                 *type = GFX_FW_TYPE_CP_MEC_ME1;
  64                 break;
  65         case AMDGPU_UCODE_ID_CP_MEC2:
  66                 *type = GFX_FW_TYPE_CP_MEC;
  67                 break;
  68         case AMDGPU_UCODE_ID_CP_MEC2_JT:
  69                 *type = GFX_FW_TYPE_CP_MEC_ME2;
  70                 break;
  71         case AMDGPU_UCODE_ID_RLC_G:
  72                 *type = GFX_FW_TYPE_RLC_G;
  73                 break;
  74         case AMDGPU_UCODE_ID_SMC:
  75                 *type = GFX_FW_TYPE_SMU;
  76                 break;
  77         case AMDGPU_UCODE_ID_UVD:
  78                 *type = GFX_FW_TYPE_UVD;
  79                 break;
  80         case AMDGPU_UCODE_ID_VCE:
  81                 *type = GFX_FW_TYPE_VCE;
  82                 break;
  83         case AMDGPU_UCODE_ID_MAXIMUM:
  84         default:
  85                 return -EINVAL;
  86         }
  87
  88         return 0;
  89 }
  90
  91 int psp_v10_0_init_microcode(struct psp_context *psp)
  92 {
  93         struct amdgpu_device *adev = psp->adev;
  94         const char *chip_name;
  95         char fw_name[30];
  96         int err = 0;
  97         const struct psp_firmware_header_v1_0 *hdr;
  98
  99         DRM_DEBUG("\n");
 100
 101         switch (adev->asic_type) {
 102         case CHIP_RAVEN:
 103                 chip_name = "raven";
 104                 break;
 105         default: BUG();
 106         }
 107
 108         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
 109         err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
 110         if (err)
 111                 goto out;
 112
 113         err = amdgpu_ucode_validate(adev->psp.asd_fw);
 114         if (err)
 115                 goto out;
 116
 117         hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
 118         adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version);
 119         adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version);
 120         adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
 121         adev->psp.asd_start_addr = (uint8_t *)hdr +
 122                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes);
 123
 124         return 0;
 125 out:
 126         if (err) {
 127                 dev_err(adev->dev,
 128                         "psp v10.0: Failed to load firmware \"%s\"\n",
 129                         fw_name);
 130                 release_firmware(adev->psp.asd_fw);
 131                 adev->psp.asd_fw = NULL;
 132         }
 133
 134         return err;
 135 }
 136
 137 int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct psp_gfx_cmd_resp *cmd)
 138 {
 139         int ret;
 140         uint64_t fw_mem_mc_addr = ucode->mc_addr;
 141
 142         memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
 143
 144         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
 145         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
 146         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
 147         cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
 148
 149         ret = psp_v10_0_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
 150         if (ret)
 151                 DRM_ERROR("Unknown firmware type\n");
 152
 153         return ret;
 154 }
 155
 156 int psp_v10_0_ring_init(struct psp_context *psp, enum psp_ring_type ring_type)
 157 {
 158         int ret = 0;
 159         struct psp_ring *ring;
 160         struct amdgpu_device *adev = psp->adev;
 161
 162         ring = &psp->km_ring;
 163
 164         ring->ring_type = ring_type;
 165
 166         /* allocate 4k Page of Local Frame Buffer memory for ring */
 167         ring->ring_size = 0x1000;
 168         ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
 169                                       AMDGPU_GEM_DOMAIN_VRAM,
 170                                       &adev->firmware.rbuf,
 171                                       &ring->ring_mem_mc_addr,
 172                                       (void **)&ring->ring_mem);
 173         if (ret) {
 174                 ring->ring_size = 0;
 175                 return ret;
 176         }
 177
 178         return 0;
 179 }
 180
 181 int psp_v10_0_ring_create(struct psp_context *psp, enum psp_ring_type ring_type)
 182 {
 183         int ret = 0;
 184         unsigned int psp_ring_reg = 0;
 185         struct psp_ring *ring = &psp->km_ring;
 186         struct amdgpu_device *adev = psp->adev;
 187
 188         /* Write low address of the ring to C2PMSG_69 */
 189         psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 190         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
 191         /* Write high address of the ring to C2PMSG_70 */
 192         psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 193         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
 194         /* Write size of ring to C2PMSG_71 */
 195         psp_ring_reg = ring->ring_size;
 196         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
 197         /* Write the ring initialization command to C2PMSG_64 */
 198         psp_ring_reg = ring_type;
 199         psp_ring_reg = psp_ring_reg << 16;
 200         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
 201
 202         /* There might be handshake issue with hardware which needs delay */
 203         mdelay(20);
 204
 205         /* Wait for response flag (bit 31) in C2PMSG_64 */
 206         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 207                            0x80000000, 0x8000FFFF, false);
 208
 209         return ret;
 210 }
 211
 212 int psp_v10_0_ring_stop(struct psp_context *psp, enum psp_ring_type ring_type)
 213 {
 214         int ret = 0;
 215         struct psp_ring *ring;
 216         unsigned int psp_ring_reg = 0;
 217         struct amdgpu_device *adev = psp->adev;
 218
 219         ring = &psp->km_ring;
 220
 221         /* Write the ring destroy command to C2PMSG_64 */
 222         psp_ring_reg = 3 << 16;
 223         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
 224
 225         /* There might be handshake issue with hardware which needs delay */
 226         mdelay(20);
 227
 228         /* Wait for response flag (bit 31) in C2PMSG_64 */
 229         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 230                            0x80000000, 0x80000000, false);
 231
 232         return ret;
 233 }
 234
 235 int psp_v10_0_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type)
 236 {
 237         int ret = 0;
 238         struct psp_ring *ring = &psp->km_ring;
 239         struct amdgpu_device *adev = psp->adev;
 240
 241         ret = psp_v10_0_ring_stop(psp, ring_type);
 242         if (ret)
 243                 DRM_ERROR("Fail to stop psp ring\n");
 244
 245         amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 246                               &ring->ring_mem_mc_addr,
 247                               (void **)&ring->ring_mem);
 248
 249         return ret;
 250 }
 251
 252 int psp_v10_0_cmd_submit(struct psp_context *psp,
 253                         struct amdgpu_firmware_info *ucode,
 254                         uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
 255                         int index)
 256 {
 257         unsigned int psp_write_ptr_reg = 0;
 258         struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
 259         struct psp_ring *ring = &psp->km_ring;
 260         struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
 261         struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
 262                 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
 263         struct amdgpu_device *adev = psp->adev;
 264         uint32_t ring_size_dw = ring->ring_size / 4;
 265         uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
 266
 267         /* KM (GPCOM) prepare write pointer */
 268         psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
 269
 270         /* Update KM RB frame pointer to new frame */
 271         if ((psp_write_ptr_reg % ring_size_dw) == 0)
 272                 write_frame = ring_buffer_start;
 273         else
 274                 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
 275         /* Check invalid write_frame ptr address */
 276         if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
 277                 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
 278                           ring_buffer_start, ring_buffer_end, write_frame);
 279                 DRM_ERROR("write_frame is pointing to address out of bounds\n");
 280                 return -EINVAL;
 281         }
 282
 283         /* Initialize KM RB frame */
 284         memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
 285
 286         /* Update KM RB frame */
 287         write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
 288         write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
 289         write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
 290         write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
 291         write_frame->fence_value = index;
 292
 293         /* Update the write Pointer in DWORDs */
 294         psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
 295         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
 296
 297         return 0;
 298 }
 299
 300 static int
 301 psp_v10_0_sram_map(unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
 302                   unsigned int *sram_data_reg_offset,
 303                   enum AMDGPU_UCODE_ID ucode_id)
 304 {
 305         int ret = 0;
 306
 307         switch(ucode_id) {
 308 /* TODO: needs to confirm */
 309 #if 0
 310         case AMDGPU_UCODE_ID_SMC:
 311                 *sram_offset = 0;
 312                 *sram_addr_reg_offset = 0;
 313                 *sram_data_reg_offset = 0;
 314                 break;
 315 #endif
 316
 317         case AMDGPU_UCODE_ID_CP_CE:
 318                 *sram_offset = 0x0;
 319                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
 320                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
 321                 break;
 322
 323         case AMDGPU_UCODE_ID_CP_PFP:
 324                 *sram_offset = 0x0;
 325                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
 326                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
 327                 break;
 328
 329         case AMDGPU_UCODE_ID_CP_ME:
 330                 *sram_offset = 0x0;
 331                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
 332                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
 333                 break;
 334
 335         case AMDGPU_UCODE_ID_CP_MEC1:
 336                 *sram_offset = 0x10000;
 337                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
 338                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
 339                 break;
 340
 341         case AMDGPU_UCODE_ID_CP_MEC2:
 342                 *sram_offset = 0x10000;
 343                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
 344                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
 345                 break;
 346
 347         case AMDGPU_UCODE_ID_RLC_G:
 348                 *sram_offset = 0x2000;
 349                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
 350                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
 351                 break;
 352
 353         case AMDGPU_UCODE_ID_SDMA0:
 354                 *sram_offset = 0x0;
 355                 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
 356                 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
 357                 break;
 358
 359 /* TODO: needs to confirm */
 360 #if 0
 361         case AMDGPU_UCODE_ID_SDMA1:
 362                 *sram_offset = ;
 363                 *sram_addr_reg_offset = ;
 364                 break;
 365
 366         case AMDGPU_UCODE_ID_UVD:
 367                 *sram_offset = ;
 368                 *sram_addr_reg_offset = ;
 369                 break;
 370
 371         case AMDGPU_UCODE_ID_VCE:
 372                 *sram_offset = ;
 373                 *sram_addr_reg_offset = ;
 374                 break;
 375 #endif
 376
 377         case AMDGPU_UCODE_ID_MAXIMUM:
 378         default:
 379                 ret = -EINVAL;
 380                 break;
 381         }
 382
 383         return ret;
 384 }
 385
 386 bool psp_v10_0_compare_sram_data(struct psp_context *psp,
 387                                 struct amdgpu_firmware_info *ucode,
 388                                 enum AMDGPU_UCODE_ID ucode_type)
 389 {
 390         int err = 0;
 391         unsigned int fw_sram_reg_val = 0;
 392         unsigned int fw_sram_addr_reg_offset = 0;
 393         unsigned int fw_sram_data_reg_offset = 0;
 394         unsigned int ucode_size;
 395         uint32_t *ucode_mem = NULL;
 396         struct amdgpu_device *adev = psp->adev;
 397
 398         err = psp_v10_0_sram_map(&fw_sram_reg_val, &fw_sram_addr_reg_offset,
 399                                 &fw_sram_data_reg_offset, ucode_type);
 400         if (err)
 401                 return false;
 402
 403         WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
 404
 405         ucode_size = ucode->ucode_size;
 406         ucode_mem = (uint32_t *)ucode->kaddr;
 407         while (!ucode_size) {
 408                 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
 409
 410                 if (*ucode_mem != fw_sram_reg_val)
 411                         return false;
 412
 413                 ucode_mem++;
 414                 /* 4 bytes */
 415                 ucode_size -= 4;
 416         }
 417
 418         return true;
 419 }
 420
 421
 422 int psp_v10_0_mode1_reset(struct psp_context *psp)
 423 {
 424         DRM_INFO("psp mode 1 reset not supported now! \n");
 425         return -EINVAL;
 426 }