2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
25 #include "amdgpu_ih.h"
26 #include "amdgpu_gfx.h"
27 #include "amdgpu_ucode.h"
28 #include "clearstate_si.h"
29 #include "bif/bif_3_0_d.h"
30 #include "bif/bif_3_0_sh_mask.h"
31 #include "oss/oss_1_0_d.h"
32 #include "oss/oss_1_0_sh_mask.h"
33 #include "gca/gfx_6_0_d.h"
34 #include "gca/gfx_6_0_sh_mask.h"
35 #include "gmc/gmc_6_0_d.h"
36 #include "gmc/gmc_6_0_sh_mask.h"
37 #include "dce/dce_6_0_d.h"
38 #include "dce/dce_6_0_sh_mask.h"
39 #include "gca/gfx_7_2_enum.h"
42 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev);
43 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev);
44 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev);
46 MODULE_FIRMWARE("radeon/tahiti_pfp.bin");
47 MODULE_FIRMWARE("radeon/tahiti_me.bin");
48 MODULE_FIRMWARE("radeon/tahiti_ce.bin");
49 MODULE_FIRMWARE("radeon/tahiti_rlc.bin");
51 MODULE_FIRMWARE("radeon/pitcairn_pfp.bin");
52 MODULE_FIRMWARE("radeon/pitcairn_me.bin");
53 MODULE_FIRMWARE("radeon/pitcairn_ce.bin");
54 MODULE_FIRMWARE("radeon/pitcairn_rlc.bin");
56 MODULE_FIRMWARE("radeon/verde_pfp.bin");
57 MODULE_FIRMWARE("radeon/verde_me.bin");
58 MODULE_FIRMWARE("radeon/verde_ce.bin");
59 MODULE_FIRMWARE("radeon/verde_rlc.bin");
61 MODULE_FIRMWARE("radeon/oland_pfp.bin");
62 MODULE_FIRMWARE("radeon/oland_me.bin");
63 MODULE_FIRMWARE("radeon/oland_ce.bin");
64 MODULE_FIRMWARE("radeon/oland_rlc.bin");
66 MODULE_FIRMWARE("radeon/hainan_pfp.bin");
67 MODULE_FIRMWARE("radeon/hainan_me.bin");
68 MODULE_FIRMWARE("radeon/hainan_ce.bin");
69 MODULE_FIRMWARE("radeon/hainan_rlc.bin");
71 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev);
72 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
73 //static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev);
74 static void gfx_v6_0_init_pg(struct amdgpu_device *adev);
76 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
77 #define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
78 #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
79 #define MICRO_TILE_MODE(x) ((x) << 0)
80 #define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
81 #define BANK_WIDTH(x) ((x) << 14)
82 #define BANK_HEIGHT(x) ((x) << 16)
83 #define MACRO_TILE_ASPECT(x) ((x) << 18)
84 #define NUM_BANKS(x) ((x) << 20)
86 static const u32 verde_rlc_save_restore_register_list[] =
88 (0x8000 << 16) | (0x98f4 >> 2),
90 (0x8040 << 16) | (0x98f4 >> 2),
92 (0x8000 << 16) | (0xe80 >> 2),
94 (0x8040 << 16) | (0xe80 >> 2),
96 (0x8000 << 16) | (0x89bc >> 2),
98 (0x8040 << 16) | (0x89bc >> 2),
100 (0x8000 << 16) | (0x8c1c >> 2),
102 (0x8040 << 16) | (0x8c1c >> 2),
104 (0x9c00 << 16) | (0x98f0 >> 2),
106 (0x9c00 << 16) | (0xe7c >> 2),
108 (0x8000 << 16) | (0x9148 >> 2),
110 (0x8040 << 16) | (0x9148 >> 2),
112 (0x9c00 << 16) | (0x9150 >> 2),
114 (0x9c00 << 16) | (0x897c >> 2),
116 (0x9c00 << 16) | (0x8d8c >> 2),
118 (0x9c00 << 16) | (0xac54 >> 2),
121 (0x9c00 << 16) | (0x98f8 >> 2),
123 (0x9c00 << 16) | (0x9910 >> 2),
125 (0x9c00 << 16) | (0x9914 >> 2),
127 (0x9c00 << 16) | (0x9918 >> 2),
129 (0x9c00 << 16) | (0x991c >> 2),
131 (0x9c00 << 16) | (0x9920 >> 2),
133 (0x9c00 << 16) | (0x9924 >> 2),
135 (0x9c00 << 16) | (0x9928 >> 2),
137 (0x9c00 << 16) | (0x992c >> 2),
139 (0x9c00 << 16) | (0x9930 >> 2),
141 (0x9c00 << 16) | (0x9934 >> 2),
143 (0x9c00 << 16) | (0x9938 >> 2),
145 (0x9c00 << 16) | (0x993c >> 2),
147 (0x9c00 << 16) | (0x9940 >> 2),
149 (0x9c00 << 16) | (0x9944 >> 2),
151 (0x9c00 << 16) | (0x9948 >> 2),
153 (0x9c00 << 16) | (0x994c >> 2),
155 (0x9c00 << 16) | (0x9950 >> 2),
157 (0x9c00 << 16) | (0x9954 >> 2),
159 (0x9c00 << 16) | (0x9958 >> 2),
161 (0x9c00 << 16) | (0x995c >> 2),
163 (0x9c00 << 16) | (0x9960 >> 2),
165 (0x9c00 << 16) | (0x9964 >> 2),
167 (0x9c00 << 16) | (0x9968 >> 2),
169 (0x9c00 << 16) | (0x996c >> 2),
171 (0x9c00 << 16) | (0x9970 >> 2),
173 (0x9c00 << 16) | (0x9974 >> 2),
175 (0x9c00 << 16) | (0x9978 >> 2),
177 (0x9c00 << 16) | (0x997c >> 2),
179 (0x9c00 << 16) | (0x9980 >> 2),
181 (0x9c00 << 16) | (0x9984 >> 2),
183 (0x9c00 << 16) | (0x9988 >> 2),
185 (0x9c00 << 16) | (0x998c >> 2),
187 (0x9c00 << 16) | (0x8c00 >> 2),
189 (0x9c00 << 16) | (0x8c14 >> 2),
191 (0x9c00 << 16) | (0x8c04 >> 2),
193 (0x9c00 << 16) | (0x8c08 >> 2),
195 (0x8000 << 16) | (0x9b7c >> 2),
197 (0x8040 << 16) | (0x9b7c >> 2),
199 (0x8000 << 16) | (0xe84 >> 2),
201 (0x8040 << 16) | (0xe84 >> 2),
203 (0x8000 << 16) | (0x89c0 >> 2),
205 (0x8040 << 16) | (0x89c0 >> 2),
207 (0x8000 << 16) | (0x914c >> 2),
209 (0x8040 << 16) | (0x914c >> 2),
211 (0x8000 << 16) | (0x8c20 >> 2),
213 (0x8040 << 16) | (0x8c20 >> 2),
215 (0x8000 << 16) | (0x9354 >> 2),
217 (0x8040 << 16) | (0x9354 >> 2),
219 (0x9c00 << 16) | (0x9060 >> 2),
221 (0x9c00 << 16) | (0x9364 >> 2),
223 (0x9c00 << 16) | (0x9100 >> 2),
225 (0x9c00 << 16) | (0x913c >> 2),
227 (0x8000 << 16) | (0x90e0 >> 2),
229 (0x8000 << 16) | (0x90e4 >> 2),
231 (0x8000 << 16) | (0x90e8 >> 2),
233 (0x8040 << 16) | (0x90e0 >> 2),
235 (0x8040 << 16) | (0x90e4 >> 2),
237 (0x8040 << 16) | (0x90e8 >> 2),
239 (0x9c00 << 16) | (0x8bcc >> 2),
241 (0x9c00 << 16) | (0x8b24 >> 2),
243 (0x9c00 << 16) | (0x88c4 >> 2),
245 (0x9c00 << 16) | (0x8e50 >> 2),
247 (0x9c00 << 16) | (0x8c0c >> 2),
249 (0x9c00 << 16) | (0x8e58 >> 2),
251 (0x9c00 << 16) | (0x8e5c >> 2),
253 (0x9c00 << 16) | (0x9508 >> 2),
255 (0x9c00 << 16) | (0x950c >> 2),
257 (0x9c00 << 16) | (0x9494 >> 2),
259 (0x9c00 << 16) | (0xac0c >> 2),
261 (0x9c00 << 16) | (0xac10 >> 2),
263 (0x9c00 << 16) | (0xac14 >> 2),
265 (0x9c00 << 16) | (0xae00 >> 2),
267 (0x9c00 << 16) | (0xac08 >> 2),
269 (0x9c00 << 16) | (0x88d4 >> 2),
271 (0x9c00 << 16) | (0x88c8 >> 2),
273 (0x9c00 << 16) | (0x88cc >> 2),
275 (0x9c00 << 16) | (0x89b0 >> 2),
277 (0x9c00 << 16) | (0x8b10 >> 2),
279 (0x9c00 << 16) | (0x8a14 >> 2),
281 (0x9c00 << 16) | (0x9830 >> 2),
283 (0x9c00 << 16) | (0x9834 >> 2),
285 (0x9c00 << 16) | (0x9838 >> 2),
287 (0x9c00 << 16) | (0x9a10 >> 2),
289 (0x8000 << 16) | (0x9870 >> 2),
291 (0x8000 << 16) | (0x9874 >> 2),
293 (0x8001 << 16) | (0x9870 >> 2),
295 (0x8001 << 16) | (0x9874 >> 2),
297 (0x8040 << 16) | (0x9870 >> 2),
299 (0x8040 << 16) | (0x9874 >> 2),
301 (0x8041 << 16) | (0x9870 >> 2),
303 (0x8041 << 16) | (0x9874 >> 2),
308 static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
310 const char *chip_name;
313 const struct gfx_firmware_header_v1_0 *cp_hdr;
314 const struct rlc_firmware_header_v1_0 *rlc_hdr;
318 switch (adev->asic_type) {
320 chip_name = "tahiti";
323 chip_name = "pitcairn";
332 chip_name = "hainan";
337 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
338 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
341 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
344 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
345 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
346 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
348 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
349 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
352 err = amdgpu_ucode_validate(adev->gfx.me_fw);
355 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
356 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
357 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
359 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
360 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
363 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
366 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
367 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
368 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
370 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
371 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
374 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
375 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
376 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
377 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
381 pr_err("gfx6: Failed to load firmware \"%s\"\n", fw_name);
382 release_firmware(adev->gfx.pfp_fw);
383 adev->gfx.pfp_fw = NULL;
384 release_firmware(adev->gfx.me_fw);
385 adev->gfx.me_fw = NULL;
386 release_firmware(adev->gfx.ce_fw);
387 adev->gfx.ce_fw = NULL;
388 release_firmware(adev->gfx.rlc_fw);
389 adev->gfx.rlc_fw = NULL;
394 static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
396 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);
397 u32 reg_offset, split_equal_to_row_size, *tilemode;
399 memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array));
400 tilemode = adev->gfx.config.tile_mode_array;
402 switch (adev->gfx.config.mem_row_size_in_kb) {
404 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
408 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
411 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
415 if (adev->asic_type == CHIP_VERDE) {
416 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
417 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
418 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
419 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
420 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
421 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
422 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
423 NUM_BANKS(ADDR_SURF_16_BANK);
424 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
425 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
426 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
427 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
428 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
429 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
430 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
431 NUM_BANKS(ADDR_SURF_16_BANK);
432 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
433 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
434 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
435 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
436 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
437 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
438 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
439 NUM_BANKS(ADDR_SURF_16_BANK);
440 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
441 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
442 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
443 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
444 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
445 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
446 NUM_BANKS(ADDR_SURF_8_BANK) |
447 TILE_SPLIT(split_equal_to_row_size);
448 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
449 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
450 PIPE_CONFIG(ADDR_SURF_P4_8x16);
451 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
452 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
453 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
454 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
455 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
456 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
457 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
458 NUM_BANKS(ADDR_SURF_4_BANK);
459 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
460 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
461 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
462 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
463 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
464 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
465 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
466 NUM_BANKS(ADDR_SURF_4_BANK);
467 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
468 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
469 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
470 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
471 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
472 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
473 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
474 NUM_BANKS(ADDR_SURF_2_BANK);
475 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
476 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
477 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
478 PIPE_CONFIG(ADDR_SURF_P4_8x16);
479 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
480 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
481 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
482 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
483 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
484 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
485 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
486 NUM_BANKS(ADDR_SURF_16_BANK);
487 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
488 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
489 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
490 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
491 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
492 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
493 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
494 NUM_BANKS(ADDR_SURF_16_BANK);
495 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
496 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
497 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
498 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
499 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
500 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
501 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
502 NUM_BANKS(ADDR_SURF_16_BANK);
503 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
504 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
505 PIPE_CONFIG(ADDR_SURF_P4_8x16);
506 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
507 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
508 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
509 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
510 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
511 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
512 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
513 NUM_BANKS(ADDR_SURF_16_BANK);
514 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
515 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
516 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
517 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
518 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
519 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
520 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
521 NUM_BANKS(ADDR_SURF_16_BANK);
522 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
523 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
524 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
525 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
526 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
527 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
528 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
529 NUM_BANKS(ADDR_SURF_16_BANK);
530 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
531 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
532 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
533 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
534 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
535 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
536 NUM_BANKS(ADDR_SURF_16_BANK) |
537 TILE_SPLIT(split_equal_to_row_size);
538 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
539 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
540 PIPE_CONFIG(ADDR_SURF_P4_8x16);
541 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
542 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
543 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
544 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
545 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
546 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
547 NUM_BANKS(ADDR_SURF_16_BANK) |
548 TILE_SPLIT(split_equal_to_row_size);
549 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
550 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
551 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
552 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
553 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
554 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
555 NUM_BANKS(ADDR_SURF_16_BANK) |
556 TILE_SPLIT(split_equal_to_row_size);
557 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
558 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
559 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
560 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
561 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
562 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
563 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
564 NUM_BANKS(ADDR_SURF_8_BANK);
565 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
566 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
567 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
568 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
569 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
570 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
571 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
572 NUM_BANKS(ADDR_SURF_8_BANK);
573 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
574 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
575 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
576 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
577 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
578 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
579 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
580 NUM_BANKS(ADDR_SURF_4_BANK);
581 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
582 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
583 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
584 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
585 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
586 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
587 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
588 NUM_BANKS(ADDR_SURF_4_BANK);
589 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
590 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
591 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
592 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
593 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
594 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
595 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
596 NUM_BANKS(ADDR_SURF_2_BANK);
597 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
598 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
599 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
600 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
601 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
602 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
603 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
604 NUM_BANKS(ADDR_SURF_2_BANK);
605 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
606 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
607 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
608 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
609 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
610 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
611 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
612 NUM_BANKS(ADDR_SURF_2_BANK);
613 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
614 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
615 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
616 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
617 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
618 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
619 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
620 NUM_BANKS(ADDR_SURF_2_BANK);
621 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
622 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
623 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
624 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
625 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
626 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
627 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
628 NUM_BANKS(ADDR_SURF_2_BANK);
629 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
630 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
631 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
632 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
633 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
634 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
635 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
636 NUM_BANKS(ADDR_SURF_2_BANK);
637 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
638 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
639 } else if (adev->asic_type == CHIP_OLAND) {
640 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
641 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
642 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
643 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
644 NUM_BANKS(ADDR_SURF_16_BANK) |
645 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
646 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
647 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
648 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
649 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
650 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
651 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
652 NUM_BANKS(ADDR_SURF_16_BANK) |
653 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
654 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
655 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
656 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
657 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
658 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
659 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
660 NUM_BANKS(ADDR_SURF_16_BANK) |
661 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
662 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
663 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
664 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
665 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
666 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
667 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
668 NUM_BANKS(ADDR_SURF_16_BANK) |
669 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
670 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
671 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
672 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
673 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
674 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
675 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
676 NUM_BANKS(ADDR_SURF_16_BANK) |
677 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
678 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
679 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
680 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
681 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
682 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
683 TILE_SPLIT(split_equal_to_row_size) |
684 NUM_BANKS(ADDR_SURF_16_BANK) |
685 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
686 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
687 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
688 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
689 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
690 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
691 TILE_SPLIT(split_equal_to_row_size) |
692 NUM_BANKS(ADDR_SURF_16_BANK) |
693 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
694 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
695 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
696 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
697 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
698 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
699 TILE_SPLIT(split_equal_to_row_size) |
700 NUM_BANKS(ADDR_SURF_16_BANK) |
701 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
702 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
703 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
704 tilemode[8] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
705 ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
706 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
707 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
708 NUM_BANKS(ADDR_SURF_16_BANK) |
709 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
710 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
711 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
712 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
713 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
714 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
715 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
716 NUM_BANKS(ADDR_SURF_16_BANK) |
717 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
718 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
719 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
720 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
721 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
722 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
723 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
724 NUM_BANKS(ADDR_SURF_16_BANK) |
725 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
726 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
727 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
728 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
729 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
730 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
731 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
732 NUM_BANKS(ADDR_SURF_16_BANK) |
733 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
734 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
735 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
736 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
737 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
738 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
739 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
740 NUM_BANKS(ADDR_SURF_16_BANK) |
741 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
742 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
743 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
744 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
745 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
746 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
747 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
748 NUM_BANKS(ADDR_SURF_16_BANK) |
749 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
750 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
751 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
752 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
753 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
754 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
755 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
756 NUM_BANKS(ADDR_SURF_16_BANK) |
757 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
758 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
759 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
760 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
761 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
762 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
763 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
764 NUM_BANKS(ADDR_SURF_16_BANK) |
765 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
766 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
767 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
768 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
769 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
770 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
771 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
772 NUM_BANKS(ADDR_SURF_16_BANK) |
773 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
774 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
775 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
776 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
777 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
778 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
779 TILE_SPLIT(split_equal_to_row_size) |
780 NUM_BANKS(ADDR_SURF_16_BANK) |
781 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
782 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
783 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
784 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
785 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
786 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
787 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
788 NUM_BANKS(ADDR_SURF_16_BANK) |
789 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
790 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
791 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
792 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
793 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
794 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
795 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
796 NUM_BANKS(ADDR_SURF_16_BANK) |
797 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
798 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
799 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
800 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
801 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
802 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
803 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
804 NUM_BANKS(ADDR_SURF_16_BANK) |
805 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
806 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
807 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
808 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
809 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
810 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
811 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
812 NUM_BANKS(ADDR_SURF_16_BANK) |
813 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
814 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
815 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
816 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
817 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
818 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
819 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
820 NUM_BANKS(ADDR_SURF_8_BANK) |
821 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
822 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
823 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1);
824 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
825 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
826 } else if (adev->asic_type == CHIP_HAINAN) {
827 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
828 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
829 PIPE_CONFIG(ADDR_SURF_P2) |
830 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
831 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
832 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
833 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
834 NUM_BANKS(ADDR_SURF_16_BANK);
835 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
836 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
837 PIPE_CONFIG(ADDR_SURF_P2) |
838 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
839 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
840 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
841 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
842 NUM_BANKS(ADDR_SURF_16_BANK);
843 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
844 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
845 PIPE_CONFIG(ADDR_SURF_P2) |
846 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
847 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
848 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
849 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
850 NUM_BANKS(ADDR_SURF_16_BANK);
851 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
852 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
853 PIPE_CONFIG(ADDR_SURF_P2) |
854 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
855 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
856 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
857 NUM_BANKS(ADDR_SURF_8_BANK) |
858 TILE_SPLIT(split_equal_to_row_size);
859 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
860 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
861 PIPE_CONFIG(ADDR_SURF_P2);
862 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
863 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
864 PIPE_CONFIG(ADDR_SURF_P2) |
865 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
866 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
867 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
868 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
869 NUM_BANKS(ADDR_SURF_8_BANK);
870 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
871 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
872 PIPE_CONFIG(ADDR_SURF_P2) |
873 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
874 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
875 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
876 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
877 NUM_BANKS(ADDR_SURF_8_BANK);
878 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
879 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
880 PIPE_CONFIG(ADDR_SURF_P2) |
881 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
882 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
883 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
884 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
885 NUM_BANKS(ADDR_SURF_4_BANK);
886 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
887 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
888 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
889 PIPE_CONFIG(ADDR_SURF_P2);
890 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
891 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
892 PIPE_CONFIG(ADDR_SURF_P2) |
893 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
894 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
895 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
896 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
897 NUM_BANKS(ADDR_SURF_16_BANK);
898 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
899 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
900 PIPE_CONFIG(ADDR_SURF_P2) |
901 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
902 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
903 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
904 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
905 NUM_BANKS(ADDR_SURF_16_BANK);
906 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
907 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
908 PIPE_CONFIG(ADDR_SURF_P2) |
909 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
910 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
911 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
912 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
913 NUM_BANKS(ADDR_SURF_16_BANK);
914 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
915 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
916 PIPE_CONFIG(ADDR_SURF_P2);
917 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
918 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
919 PIPE_CONFIG(ADDR_SURF_P2) |
920 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
921 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
922 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
923 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
924 NUM_BANKS(ADDR_SURF_16_BANK);
925 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
926 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
927 PIPE_CONFIG(ADDR_SURF_P2) |
928 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
929 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
930 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
931 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
932 NUM_BANKS(ADDR_SURF_16_BANK);
933 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
934 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
935 PIPE_CONFIG(ADDR_SURF_P2) |
936 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
937 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
938 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
939 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
940 NUM_BANKS(ADDR_SURF_16_BANK);
941 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
942 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
943 PIPE_CONFIG(ADDR_SURF_P2) |
944 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
945 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
946 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
947 NUM_BANKS(ADDR_SURF_16_BANK) |
948 TILE_SPLIT(split_equal_to_row_size);
949 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
950 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
951 PIPE_CONFIG(ADDR_SURF_P2);
952 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
953 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
954 PIPE_CONFIG(ADDR_SURF_P2) |
955 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
956 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
957 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
958 NUM_BANKS(ADDR_SURF_16_BANK) |
959 TILE_SPLIT(split_equal_to_row_size);
960 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
961 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
962 PIPE_CONFIG(ADDR_SURF_P2) |
963 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
964 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
965 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
966 NUM_BANKS(ADDR_SURF_16_BANK) |
967 TILE_SPLIT(split_equal_to_row_size);
968 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
969 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
970 PIPE_CONFIG(ADDR_SURF_P2) |
971 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
972 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
973 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
974 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
975 NUM_BANKS(ADDR_SURF_8_BANK);
976 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
977 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
978 PIPE_CONFIG(ADDR_SURF_P2) |
979 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
980 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
981 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
982 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
983 NUM_BANKS(ADDR_SURF_8_BANK);
984 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
985 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
986 PIPE_CONFIG(ADDR_SURF_P2) |
987 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
988 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
989 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
990 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
991 NUM_BANKS(ADDR_SURF_8_BANK);
992 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
993 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
994 PIPE_CONFIG(ADDR_SURF_P2) |
995 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
996 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
997 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
998 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
999 NUM_BANKS(ADDR_SURF_8_BANK);
1000 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1001 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1002 PIPE_CONFIG(ADDR_SURF_P2) |
1003 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1004 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1005 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1006 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1007 NUM_BANKS(ADDR_SURF_4_BANK);
1008 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1009 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1010 PIPE_CONFIG(ADDR_SURF_P2) |
1011 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1012 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1013 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1014 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1015 NUM_BANKS(ADDR_SURF_4_BANK);
1016 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1017 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1018 PIPE_CONFIG(ADDR_SURF_P2) |
1019 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1020 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1021 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1022 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1023 NUM_BANKS(ADDR_SURF_4_BANK);
1024 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1025 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1026 PIPE_CONFIG(ADDR_SURF_P2) |
1027 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1028 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1029 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1030 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1031 NUM_BANKS(ADDR_SURF_4_BANK);
1032 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1033 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1034 PIPE_CONFIG(ADDR_SURF_P2) |
1035 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1036 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1037 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1038 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1039 NUM_BANKS(ADDR_SURF_4_BANK);
1040 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1041 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1042 PIPE_CONFIG(ADDR_SURF_P2) |
1043 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1044 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1045 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1046 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1047 NUM_BANKS(ADDR_SURF_4_BANK);
1048 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1049 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
1050 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) {
1051 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1052 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1053 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1054 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1055 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1056 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1057 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1058 NUM_BANKS(ADDR_SURF_16_BANK);
1059 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1060 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1061 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1062 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1063 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1064 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1065 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1066 NUM_BANKS(ADDR_SURF_16_BANK);
1067 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1068 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1069 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1070 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1071 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1072 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1073 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1074 NUM_BANKS(ADDR_SURF_16_BANK);
1075 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1076 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1077 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1078 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1079 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1080 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1081 NUM_BANKS(ADDR_SURF_4_BANK) |
1082 TILE_SPLIT(split_equal_to_row_size);
1083 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1084 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1085 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1086 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1087 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1088 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1089 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1090 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1091 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1092 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1093 NUM_BANKS(ADDR_SURF_2_BANK);
1094 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1095 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1096 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1097 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1098 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1099 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1100 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1101 NUM_BANKS(ADDR_SURF_2_BANK);
1102 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1103 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1104 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1105 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1106 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1107 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1108 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1109 NUM_BANKS(ADDR_SURF_2_BANK);
1110 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
1111 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1112 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1113 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1114 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1115 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1116 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1117 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1118 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1119 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1120 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1121 NUM_BANKS(ADDR_SURF_16_BANK);
1122 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1123 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1124 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1125 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1126 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1127 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1128 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1129 NUM_BANKS(ADDR_SURF_16_BANK);
1130 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1131 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1132 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1133 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1134 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1135 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1136 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1137 NUM_BANKS(ADDR_SURF_16_BANK);
1138 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1139 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1140 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1141 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1142 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1143 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1144 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1145 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1146 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1147 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1148 NUM_BANKS(ADDR_SURF_16_BANK);
1149 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1150 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1151 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1152 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1153 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1154 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1155 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1156 NUM_BANKS(ADDR_SURF_16_BANK);
1157 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1158 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1159 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1160 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1161 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1162 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1163 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1164 NUM_BANKS(ADDR_SURF_16_BANK);
1165 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1166 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1167 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1168 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1169 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1170 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1171 NUM_BANKS(ADDR_SURF_16_BANK) |
1172 TILE_SPLIT(split_equal_to_row_size);
1173 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1174 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1175 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1176 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1177 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1178 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1179 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1180 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1181 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1182 NUM_BANKS(ADDR_SURF_16_BANK) |
1183 TILE_SPLIT(split_equal_to_row_size);
1184 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1185 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1186 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1187 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1188 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1189 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1190 NUM_BANKS(ADDR_SURF_16_BANK) |
1191 TILE_SPLIT(split_equal_to_row_size);
1192 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1193 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1194 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1195 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1196 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1197 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1198 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1199 NUM_BANKS(ADDR_SURF_4_BANK);
1200 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1201 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1202 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1203 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1204 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1205 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1206 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1207 NUM_BANKS(ADDR_SURF_4_BANK);
1208 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1209 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1210 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1211 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1212 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1213 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1214 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1215 NUM_BANKS(ADDR_SURF_2_BANK);
1216 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1217 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1218 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1219 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1220 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1221 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1222 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1223 NUM_BANKS(ADDR_SURF_2_BANK);
1224 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1225 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1226 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1227 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1228 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1229 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1230 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1231 NUM_BANKS(ADDR_SURF_2_BANK);
1232 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1233 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1234 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1235 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1236 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1237 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1238 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1239 NUM_BANKS(ADDR_SURF_2_BANK);
1240 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1241 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1242 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1243 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1244 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1245 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1246 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1247 NUM_BANKS(ADDR_SURF_2_BANK);
1248 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1249 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1250 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1251 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1252 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1253 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1254 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1255 NUM_BANKS(ADDR_SURF_2_BANK);
1256 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1257 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1258 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1259 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1260 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1261 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1262 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1263 NUM_BANKS(ADDR_SURF_2_BANK);
1264 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1265 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1266 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1267 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1268 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1269 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1270 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1271 NUM_BANKS(ADDR_SURF_2_BANK);
1272 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1273 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
1275 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1279 static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1280 u32 sh_num, u32 instance)
1284 if (instance == 0xffffffff)
1285 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1287 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1289 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1290 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1291 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1292 else if (se_num == 0xffffffff)
1293 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1294 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1295 else if (sh_num == 0xffffffff)
1296 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1297 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1299 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1300 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1301 WREG32(mmGRBM_GFX_INDEX, data);
1304 static u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1308 data = RREG32(mmCC_RB_BACKEND_DISABLE) |
1309 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1311 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE);
1313 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/
1314 adev->gfx.config.max_sh_per_se);
1316 return ~data & mask;
1319 static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf)
1321 switch (adev->asic_type) {
1325 (2 << PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT) |
1326 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
1327 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
1328 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT) |
1329 (2 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT) |
1330 (2 << PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT) |
1331 (2 << PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT);
1335 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
1336 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
1337 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT);
1340 *rconf |= (1 << PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT);
1346 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1351 static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1352 u32 raster_config, unsigned rb_mask,
1355 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
1356 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
1357 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
1358 unsigned rb_per_se = num_rb / num_se;
1359 unsigned se_mask[4];
1362 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1363 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1364 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1365 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1367 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
1368 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
1369 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
1371 for (se = 0; se < num_se; se++) {
1372 unsigned raster_config_se = raster_config;
1373 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1374 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1375 int idx = (se / 2) * 2;
1377 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
1378 raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK;
1381 raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
1383 raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
1386 pkr0_mask &= rb_mask;
1387 pkr1_mask &= rb_mask;
1388 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
1389 raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK;
1392 raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
1394 raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
1397 if (rb_per_se >= 2) {
1398 unsigned rb0_mask = 1 << (se * rb_per_se);
1399 unsigned rb1_mask = rb0_mask << 1;
1401 rb0_mask &= rb_mask;
1402 rb1_mask &= rb_mask;
1403 if (!rb0_mask || !rb1_mask) {
1404 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK;
1408 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
1411 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
1414 if (rb_per_se > 2) {
1415 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1416 rb1_mask = rb0_mask << 1;
1417 rb0_mask &= rb_mask;
1418 rb1_mask &= rb_mask;
1419 if (!rb0_mask || !rb1_mask) {
1420 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK;
1424 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
1427 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
1432 /* GRBM_GFX_INDEX has a different offset on SI */
1433 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
1434 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
1437 /* GRBM_GFX_INDEX has a different offset on SI */
1438 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1441 static void gfx_v6_0_setup_rb(struct amdgpu_device *adev)
1445 u32 raster_config = 0;
1447 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1448 adev->gfx.config.max_sh_per_se;
1449 unsigned num_rb_pipes;
1451 mutex_lock(&adev->grbm_idx_mutex);
1452 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1453 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1454 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1455 data = gfx_v6_0_get_rb_active_bitmap(adev);
1456 active_rbs |= data <<
1457 ((i * adev->gfx.config.max_sh_per_se + j) *
1458 rb_bitmap_width_per_sh);
1461 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1463 adev->gfx.config.backend_enable_mask = active_rbs;
1464 adev->gfx.config.num_rbs = hweight32(active_rbs);
1466 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1467 adev->gfx.config.max_shader_engines, 16);
1469 gfx_v6_0_raster_config(adev, &raster_config);
1471 if (!adev->gfx.config.backend_enable_mask ||
1472 adev->gfx.config.num_rbs >= num_rb_pipes)
1473 WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
1475 gfx_v6_0_write_harvested_raster_configs(adev, raster_config,
1476 adev->gfx.config.backend_enable_mask,
1479 /* cache the values for userspace */
1480 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1481 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1482 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1483 adev->gfx.config.rb_config[i][j].rb_backend_disable =
1484 RREG32(mmCC_RB_BACKEND_DISABLE);
1485 adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
1486 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1487 adev->gfx.config.rb_config[i][j].raster_config =
1488 RREG32(mmPA_SC_RASTER_CONFIG);
1491 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1492 mutex_unlock(&adev->grbm_idx_mutex);
1495 static void gfx_v6_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
1503 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
1504 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
1506 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
1509 static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev)
1513 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |
1514 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
1516 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
1517 return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask;
1521 static void gfx_v6_0_setup_spi(struct amdgpu_device *adev)
1527 mutex_lock(&adev->grbm_idx_mutex);
1528 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1529 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1530 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1531 data = RREG32(mmSPI_STATIC_THREAD_MGMT_3);
1532 active_cu = gfx_v6_0_get_cu_enabled(adev);
1535 for (k = 0; k < 16; k++) {
1537 if (active_cu & mask) {
1539 WREG32(mmSPI_STATIC_THREAD_MGMT_3, data);
1545 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1546 mutex_unlock(&adev->grbm_idx_mutex);
1549 static void gfx_v6_0_config_init(struct amdgpu_device *adev)
1551 adev->gfx.config.double_offchip_lds_buf = 0;
1554 static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
1556 u32 gb_addr_config = 0;
1557 u32 mc_shared_chmap, mc_arb_ramcfg;
1559 u32 hdp_host_path_cntl;
1562 switch (adev->asic_type) {
1564 adev->gfx.config.max_shader_engines = 2;
1565 adev->gfx.config.max_tile_pipes = 12;
1566 adev->gfx.config.max_cu_per_sh = 8;
1567 adev->gfx.config.max_sh_per_se = 2;
1568 adev->gfx.config.max_backends_per_se = 4;
1569 adev->gfx.config.max_texture_channel_caches = 12;
1570 adev->gfx.config.max_gprs = 256;
1571 adev->gfx.config.max_gs_threads = 32;
1572 adev->gfx.config.max_hw_contexts = 8;
1574 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1575 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1576 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1577 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1578 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1581 adev->gfx.config.max_shader_engines = 2;
1582 adev->gfx.config.max_tile_pipes = 8;
1583 adev->gfx.config.max_cu_per_sh = 5;
1584 adev->gfx.config.max_sh_per_se = 2;
1585 adev->gfx.config.max_backends_per_se = 4;
1586 adev->gfx.config.max_texture_channel_caches = 8;
1587 adev->gfx.config.max_gprs = 256;
1588 adev->gfx.config.max_gs_threads = 32;
1589 adev->gfx.config.max_hw_contexts = 8;
1591 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1592 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1593 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1594 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1595 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1598 adev->gfx.config.max_shader_engines = 1;
1599 adev->gfx.config.max_tile_pipes = 4;
1600 adev->gfx.config.max_cu_per_sh = 5;
1601 adev->gfx.config.max_sh_per_se = 2;
1602 adev->gfx.config.max_backends_per_se = 4;
1603 adev->gfx.config.max_texture_channel_caches = 4;
1604 adev->gfx.config.max_gprs = 256;
1605 adev->gfx.config.max_gs_threads = 32;
1606 adev->gfx.config.max_hw_contexts = 8;
1608 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1609 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1610 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1611 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1612 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1615 adev->gfx.config.max_shader_engines = 1;
1616 adev->gfx.config.max_tile_pipes = 4;
1617 adev->gfx.config.max_cu_per_sh = 6;
1618 adev->gfx.config.max_sh_per_se = 1;
1619 adev->gfx.config.max_backends_per_se = 2;
1620 adev->gfx.config.max_texture_channel_caches = 4;
1621 adev->gfx.config.max_gprs = 256;
1622 adev->gfx.config.max_gs_threads = 16;
1623 adev->gfx.config.max_hw_contexts = 8;
1625 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1626 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1627 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1628 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1629 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1632 adev->gfx.config.max_shader_engines = 1;
1633 adev->gfx.config.max_tile_pipes = 4;
1634 adev->gfx.config.max_cu_per_sh = 5;
1635 adev->gfx.config.max_sh_per_se = 1;
1636 adev->gfx.config.max_backends_per_se = 1;
1637 adev->gfx.config.max_texture_channel_caches = 2;
1638 adev->gfx.config.max_gprs = 256;
1639 adev->gfx.config.max_gs_threads = 16;
1640 adev->gfx.config.max_hw_contexts = 8;
1642 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1643 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1644 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1645 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1646 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;
1653 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1654 WREG32(mmSRBM_INT_CNTL, 1);
1655 WREG32(mmSRBM_INT_ACK, 1);
1657 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
1659 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
1660 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1661 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
1663 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1664 adev->gfx.config.mem_max_burst_length_bytes = 256;
1665 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
1666 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1667 if (adev->gfx.config.mem_row_size_in_kb > 4)
1668 adev->gfx.config.mem_row_size_in_kb = 4;
1669 adev->gfx.config.shader_engine_tile_size = 32;
1670 adev->gfx.config.num_gpus = 1;
1671 adev->gfx.config.multi_gpu_tile_size = 64;
1673 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
1674 switch (adev->gfx.config.mem_row_size_in_kb) {
1677 gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1680 gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1683 gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1686 gb_addr_config &= ~GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK;
1687 if (adev->gfx.config.max_shader_engines == 2)
1688 gb_addr_config |= 1 << GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT;
1689 adev->gfx.config.gb_addr_config = gb_addr_config;
1691 WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
1692 WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config);
1693 WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
1694 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
1695 WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1696 WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1699 if (adev->has_uvd) {
1700 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
1701 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1702 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
1705 gfx_v6_0_tiling_mode_table_init(adev);
1707 gfx_v6_0_setup_rb(adev);
1709 gfx_v6_0_setup_spi(adev);
1711 gfx_v6_0_get_cu_info(adev);
1712 gfx_v6_0_config_init(adev);
1714 WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) |
1715 (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT)));
1716 WREG32(mmCP_MEQ_THRESHOLDS, (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1717 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
1719 sx_debug_1 = RREG32(mmSX_DEBUG_1);
1720 WREG32(mmSX_DEBUG_1, sx_debug_1);
1722 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1724 WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1725 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1726 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1727 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1729 WREG32(mmVGT_NUM_INSTANCES, 1);
1730 WREG32(mmCP_PERFMON_CNTL, 0);
1731 WREG32(mmSQ_CONFIG, 0);
1732 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1733 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
1735 WREG32(mmVGT_CACHE_INVALIDATION,
1736 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
1737 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
1739 WREG32(mmVGT_GS_VERTEX_REUSE, 16);
1740 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
1742 WREG32(mmCB_PERFCOUNTER0_SELECT0, 0);
1743 WREG32(mmCB_PERFCOUNTER0_SELECT1, 0);
1744 WREG32(mmCB_PERFCOUNTER1_SELECT0, 0);
1745 WREG32(mmCB_PERFCOUNTER1_SELECT1, 0);
1746 WREG32(mmCB_PERFCOUNTER2_SELECT0, 0);
1747 WREG32(mmCB_PERFCOUNTER2_SELECT1, 0);
1748 WREG32(mmCB_PERFCOUNTER3_SELECT0, 0);
1749 WREG32(mmCB_PERFCOUNTER3_SELECT1, 0);
1751 hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL);
1752 WREG32(mmHDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1754 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
1755 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
1761 static void gfx_v6_0_scratch_init(struct amdgpu_device *adev)
1763 adev->gfx.scratch.num_reg = 8;
1764 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
1765 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
1768 static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring)
1770 struct amdgpu_device *adev = ring->adev;
1776 r = amdgpu_gfx_scratch_get(adev, &scratch);
1778 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
1781 WREG32(scratch, 0xCAFEDEAD);
1783 r = amdgpu_ring_alloc(ring, 3);
1785 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
1786 amdgpu_gfx_scratch_free(adev, scratch);
1789 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1790 amdgpu_ring_write(ring, (scratch - PACKET3_SET_CONFIG_REG_START));
1791 amdgpu_ring_write(ring, 0xDEADBEEF);
1792 amdgpu_ring_commit(ring);
1794 for (i = 0; i < adev->usec_timeout; i++) {
1795 tmp = RREG32(scratch);
1796 if (tmp == 0xDEADBEEF)
1800 if (i < adev->usec_timeout) {
1801 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
1803 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
1804 ring->idx, scratch, tmp);
1807 amdgpu_gfx_scratch_free(adev, scratch);
1811 static void gfx_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
1813 /* flush hdp cache */
1814 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1815 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1816 WRITE_DATA_DST_SEL(0)));
1817 amdgpu_ring_write(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL);
1818 amdgpu_ring_write(ring, 0);
1819 amdgpu_ring_write(ring, 0x1);
1822 static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
1824 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
1825 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
1830 * gfx_v6_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
1832 * @adev: amdgpu_device pointer
1833 * @ridx: amdgpu ring index
1835 * Emits an hdp invalidate on the cp.
1837 static void gfx_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
1839 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1840 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1841 WRITE_DATA_DST_SEL(0)));
1842 amdgpu_ring_write(ring, mmHDP_DEBUG0);
1843 amdgpu_ring_write(ring, 0);
1844 amdgpu_ring_write(ring, 0x1);
1847 static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1848 u64 seq, unsigned flags)
1850 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
1851 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
1852 /* flush read cache over gart */
1853 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1854 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START));
1855 amdgpu_ring_write(ring, 0);
1856 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1857 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1858 PACKET3_TC_ACTION_ENA |
1859 PACKET3_SH_KCACHE_ACTION_ENA |
1860 PACKET3_SH_ICACHE_ACTION_ENA);
1861 amdgpu_ring_write(ring, 0xFFFFFFFF);
1862 amdgpu_ring_write(ring, 0);
1863 amdgpu_ring_write(ring, 10); /* poll interval */
1864 /* EVENT_WRITE_EOP - flush caches, send int */
1865 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1866 amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1867 amdgpu_ring_write(ring, addr & 0xfffffffc);
1868 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
1869 ((write64bit ? 2 : 1) << CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT) |
1870 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT));
1871 amdgpu_ring_write(ring, lower_32_bits(seq));
1872 amdgpu_ring_write(ring, upper_32_bits(seq));
1875 static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
1876 struct amdgpu_ib *ib,
1877 unsigned vm_id, bool ctx_switch)
1879 u32 header, control = 0;
1881 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
1883 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1884 amdgpu_ring_write(ring, 0);
1887 if (ib->flags & AMDGPU_IB_FLAG_CE)
1888 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
1890 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
1892 control |= ib->length_dw | (vm_id << 24);
1894 amdgpu_ring_write(ring, header);
1895 amdgpu_ring_write(ring,
1899 (ib->gpu_addr & 0xFFFFFFFC));
1900 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
1901 amdgpu_ring_write(ring, control);
1905 * gfx_v6_0_ring_test_ib - basic ring IB test
1907 * @ring: amdgpu_ring structure holding ring information
1909 * Allocate an IB and execute it on the gfx ring (SI).
1910 * Provides a basic gfx ring test to verify that IBs are working.
1911 * Returns 0 on success, error on failure.
1913 static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1915 struct amdgpu_device *adev = ring->adev;
1916 struct amdgpu_ib ib;
1917 struct dma_fence *f = NULL;
1922 r = amdgpu_gfx_scratch_get(adev, &scratch);
1924 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
1927 WREG32(scratch, 0xCAFEDEAD);
1928 memset(&ib, 0, sizeof(ib));
1929 r = amdgpu_ib_get(adev, NULL, 256, &ib);
1931 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1934 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
1935 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_START));
1936 ib.ptr[2] = 0xDEADBEEF;
1939 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1943 r = dma_fence_wait_timeout(f, false, timeout);
1945 DRM_ERROR("amdgpu: IB test timed out\n");
1949 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1952 tmp = RREG32(scratch);
1953 if (tmp == 0xDEADBEEF) {
1954 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
1957 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
1963 amdgpu_ib_free(adev, &ib, NULL);
1966 amdgpu_gfx_scratch_free(adev, scratch);
1970 static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
1974 WREG32(mmCP_ME_CNTL, 0);
1976 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK |
1977 CP_ME_CNTL__PFP_HALT_MASK |
1978 CP_ME_CNTL__CE_HALT_MASK));
1979 WREG32(mmSCRATCH_UMSK, 0);
1980 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1981 adev->gfx.gfx_ring[i].ready = false;
1982 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1983 adev->gfx.compute_ring[i].ready = false;
1988 static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
1991 const struct gfx_firmware_header_v1_0 *pfp_hdr;
1992 const struct gfx_firmware_header_v1_0 *ce_hdr;
1993 const struct gfx_firmware_header_v1_0 *me_hdr;
1994 const __le32 *fw_data;
1997 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2000 gfx_v6_0_cp_gfx_enable(adev, false);
2001 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2002 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2003 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2005 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2006 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2007 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2010 fw_data = (const __le32 *)
2011 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2012 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2013 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2014 for (i = 0; i < fw_size; i++)
2015 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2016 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2019 fw_data = (const __le32 *)
2020 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2021 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2022 WREG32(mmCP_CE_UCODE_ADDR, 0);
2023 for (i = 0; i < fw_size; i++)
2024 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2025 WREG32(mmCP_CE_UCODE_ADDR, 0);
2028 fw_data = (const __be32 *)
2029 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2030 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2031 WREG32(mmCP_ME_RAM_WADDR, 0);
2032 for (i = 0; i < fw_size; i++)
2033 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2034 WREG32(mmCP_ME_RAM_WADDR, 0);
2036 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2037 WREG32(mmCP_CE_UCODE_ADDR, 0);
2038 WREG32(mmCP_ME_RAM_WADDR, 0);
2039 WREG32(mmCP_ME_RAM_RADDR, 0);
2043 static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev)
2045 const struct cs_section_def *sect = NULL;
2046 const struct cs_extent_def *ext = NULL;
2047 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2050 r = amdgpu_ring_alloc(ring, 7 + 4);
2052 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2055 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2056 amdgpu_ring_write(ring, 0x1);
2057 amdgpu_ring_write(ring, 0x0);
2058 amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1);
2059 amdgpu_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2060 amdgpu_ring_write(ring, 0);
2061 amdgpu_ring_write(ring, 0);
2063 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2064 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2065 amdgpu_ring_write(ring, 0xc000);
2066 amdgpu_ring_write(ring, 0xe000);
2067 amdgpu_ring_commit(ring);
2069 gfx_v6_0_cp_gfx_enable(adev, true);
2071 r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10);
2073 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2077 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2078 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2080 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2081 for (ext = sect->section; ext->extent != NULL; ++ext) {
2082 if (sect->id == SECT_CONTEXT) {
2083 amdgpu_ring_write(ring,
2084 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2085 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2086 for (i = 0; i < ext->reg_count; i++)
2087 amdgpu_ring_write(ring, ext->extent[i]);
2092 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2093 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2095 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2096 amdgpu_ring_write(ring, 0);
2098 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2099 amdgpu_ring_write(ring, 0x00000316);
2100 amdgpu_ring_write(ring, 0x0000000e);
2101 amdgpu_ring_write(ring, 0x00000010);
2103 amdgpu_ring_commit(ring);
2108 static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
2110 struct amdgpu_ring *ring;
2116 WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2117 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2119 /* Set the write pointer delay */
2120 WREG32(mmCP_RB_WPTR_DELAY, 0);
2122 WREG32(mmCP_DEBUG, 0);
2123 WREG32(mmSCRATCH_ADDR, 0);
2125 /* ring 0 - compute and gfx */
2126 /* Set ring buffer size */
2127 ring = &adev->gfx.gfx_ring[0];
2128 rb_bufsz = order_base_2(ring->ring_size / 8);
2129 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2132 tmp |= BUF_SWAP_32BIT;
2134 WREG32(mmCP_RB0_CNTL, tmp);
2136 /* Initialize the ring buffer's read and write pointers */
2137 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2139 WREG32(mmCP_RB0_WPTR, ring->wptr);
2141 /* set the wb address whether it's enabled or not */
2142 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2143 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2144 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2146 WREG32(mmSCRATCH_UMSK, 0);
2149 WREG32(mmCP_RB0_CNTL, tmp);
2151 WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8);
2153 /* start the rings */
2154 gfx_v6_0_cp_gfx_start(adev);
2156 r = amdgpu_ring_test_ring(ring);
2158 ring->ready = false;
2165 static u64 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
2167 return ring->adev->wb.wb[ring->rptr_offs];
2170 static u64 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
2172 struct amdgpu_device *adev = ring->adev;
2174 if (ring == &adev->gfx.gfx_ring[0])
2175 return RREG32(mmCP_RB0_WPTR);
2176 else if (ring == &adev->gfx.compute_ring[0])
2177 return RREG32(mmCP_RB1_WPTR);
2178 else if (ring == &adev->gfx.compute_ring[1])
2179 return RREG32(mmCP_RB2_WPTR);
2184 static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2186 struct amdgpu_device *adev = ring->adev;
2188 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2189 (void)RREG32(mmCP_RB0_WPTR);
2192 static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2194 struct amdgpu_device *adev = ring->adev;
2196 if (ring == &adev->gfx.compute_ring[0]) {
2197 WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
2198 (void)RREG32(mmCP_RB1_WPTR);
2199 } else if (ring == &adev->gfx.compute_ring[1]) {
2200 WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr));
2201 (void)RREG32(mmCP_RB2_WPTR);
2208 static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
2210 struct amdgpu_ring *ring;
2216 /* ring1 - compute only */
2217 /* Set ring buffer size */
2219 ring = &adev->gfx.compute_ring[0];
2220 rb_bufsz = order_base_2(ring->ring_size / 8);
2221 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2223 tmp |= BUF_SWAP_32BIT;
2225 WREG32(mmCP_RB1_CNTL, tmp);
2227 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK);
2229 WREG32(mmCP_RB1_WPTR, ring->wptr);
2231 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2232 WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
2233 WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2236 WREG32(mmCP_RB1_CNTL, tmp);
2237 WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8);
2239 ring = &adev->gfx.compute_ring[1];
2240 rb_bufsz = order_base_2(ring->ring_size / 8);
2241 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2243 tmp |= BUF_SWAP_32BIT;
2245 WREG32(mmCP_RB2_CNTL, tmp);
2247 WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK);
2249 WREG32(mmCP_RB2_WPTR, ring->wptr);
2250 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2251 WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr));
2252 WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2255 WREG32(mmCP_RB2_CNTL, tmp);
2256 WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8);
2258 adev->gfx.compute_ring[0].ready = false;
2259 adev->gfx.compute_ring[1].ready = false;
2261 for (i = 0; i < 2; i++) {
2262 r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[i]);
2265 adev->gfx.compute_ring[i].ready = true;
2271 static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable)
2273 gfx_v6_0_cp_gfx_enable(adev, enable);
2276 static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev)
2278 return gfx_v6_0_cp_gfx_load_microcode(adev);
2281 static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2284 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
2289 tmp |= (CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
2290 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
2292 tmp &= ~(CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
2293 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
2294 WREG32(mmCP_INT_CNTL_RING0, tmp);
2297 /* read a gfx register */
2298 tmp = RREG32(mmDB_DEPTH_INFO);
2300 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS;
2301 for (i = 0; i < adev->usec_timeout; i++) {
2302 if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))
2309 static int gfx_v6_0_cp_resume(struct amdgpu_device *adev)
2313 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2315 r = gfx_v6_0_cp_load_microcode(adev);
2319 r = gfx_v6_0_cp_gfx_resume(adev);
2322 r = gfx_v6_0_cp_compute_resume(adev);
2326 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2331 static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
2333 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2334 uint32_t seq = ring->fence_drv.sync_seq;
2335 uint64_t addr = ring->fence_drv.gpu_addr;
2337 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2338 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
2339 WAIT_REG_MEM_FUNCTION(3) | /* equal */
2340 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
2341 amdgpu_ring_write(ring, addr & 0xfffffffc);
2342 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
2343 amdgpu_ring_write(ring, seq);
2344 amdgpu_ring_write(ring, 0xffffffff);
2345 amdgpu_ring_write(ring, 4); /* poll interval */
2348 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
2349 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2350 amdgpu_ring_write(ring, 0);
2351 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2352 amdgpu_ring_write(ring, 0);
2356 static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
2357 unsigned vm_id, uint64_t pd_addr)
2359 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2361 /* write new base address */
2362 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2363 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
2364 WRITE_DATA_DST_SEL(0)));
2366 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id ));
2368 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vm_id - 8)));
2370 amdgpu_ring_write(ring, 0);
2371 amdgpu_ring_write(ring, pd_addr >> 12);
2373 /* bits 0-15 are the VM contexts0-15 */
2374 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2375 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
2376 WRITE_DATA_DST_SEL(0)));
2377 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
2378 amdgpu_ring_write(ring, 0);
2379 amdgpu_ring_write(ring, 1 << vm_id);
2381 /* wait for the invalidate to complete */
2382 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2383 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */
2384 WAIT_REG_MEM_ENGINE(0))); /* me */
2385 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
2386 amdgpu_ring_write(ring, 0);
2387 amdgpu_ring_write(ring, 0); /* ref */
2388 amdgpu_ring_write(ring, 0); /* mask */
2389 amdgpu_ring_write(ring, 0x20); /* poll interval */
2392 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2393 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2394 amdgpu_ring_write(ring, 0x0);
2396 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
2397 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2398 amdgpu_ring_write(ring, 0);
2399 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2400 amdgpu_ring_write(ring, 0);
2405 static void gfx_v6_0_rlc_fini(struct amdgpu_device *adev)
2407 amdgpu_bo_free_kernel(&adev->gfx.rlc.save_restore_obj, NULL, NULL);
2408 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, NULL, NULL);
2409 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, NULL, NULL);
2412 static int gfx_v6_0_rlc_init(struct amdgpu_device *adev)
2415 volatile u32 *dst_ptr;
2417 u64 reg_list_mc_addr;
2418 const struct cs_section_def *cs_data;
2421 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list;
2422 adev->gfx.rlc.reg_list_size =
2423 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list);
2425 adev->gfx.rlc.cs_data = si_cs_data;
2426 src_ptr = adev->gfx.rlc.reg_list;
2427 dws = adev->gfx.rlc.reg_list_size;
2428 cs_data = adev->gfx.rlc.cs_data;
2431 /* save restore block */
2432 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
2433 AMDGPU_GEM_DOMAIN_VRAM,
2434 &adev->gfx.rlc.save_restore_obj,
2435 &adev->gfx.rlc.save_restore_gpu_addr,
2436 (void **)&adev->gfx.rlc.sr_ptr);
2438 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n",
2440 gfx_v6_0_rlc_fini(adev);
2444 /* write the sr buffer */
2445 dst_ptr = adev->gfx.rlc.sr_ptr;
2446 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
2447 dst_ptr[i] = cpu_to_le32(src_ptr[i]);
2449 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
2450 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
2454 /* clear state block */
2455 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev);
2456 dws = adev->gfx.rlc.clear_state_size + (256 / 4);
2458 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
2459 AMDGPU_GEM_DOMAIN_VRAM,
2460 &adev->gfx.rlc.clear_state_obj,
2461 &adev->gfx.rlc.clear_state_gpu_addr,
2462 (void **)&adev->gfx.rlc.cs_ptr);
2464 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
2465 gfx_v6_0_rlc_fini(adev);
2469 /* set up the cs buffer */
2470 dst_ptr = adev->gfx.rlc.cs_ptr;
2471 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256;
2472 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr));
2473 dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr));
2474 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size);
2475 gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]);
2476 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
2477 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2483 static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
2485 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
2488 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2489 WREG32(mmSPI_LB_CU_MASK, 0x00ff);
2493 static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2497 for (i = 0; i < adev->usec_timeout; i++) {
2498 if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0)
2503 for (i = 0; i < adev->usec_timeout; i++) {
2504 if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0)
2510 static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
2514 tmp = RREG32(mmRLC_CNTL);
2516 WREG32(mmRLC_CNTL, rlc);
2519 static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev)
2523 orig = data = RREG32(mmRLC_CNTL);
2525 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
2526 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
2527 WREG32(mmRLC_CNTL, data);
2529 gfx_v6_0_wait_for_rlc_serdes(adev);
2535 static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev)
2537 WREG32(mmRLC_CNTL, 0);
2539 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2540 gfx_v6_0_wait_for_rlc_serdes(adev);
2543 static void gfx_v6_0_rlc_start(struct amdgpu_device *adev)
2545 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
2547 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2552 static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev)
2554 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2556 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2560 static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev)
2564 /* Enable LBPW only for DDR3 */
2565 tmp = RREG32(mmMC_SEQ_MISC0);
2566 if ((tmp & 0xF0000000) == 0xB0000000)
2571 static void gfx_v6_0_init_cg(struct amdgpu_device *adev)
2575 static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
2578 const struct rlc_firmware_header_v1_0 *hdr;
2579 const __le32 *fw_data;
2583 if (!adev->gfx.rlc_fw)
2586 gfx_v6_0_rlc_stop(adev);
2587 gfx_v6_0_rlc_reset(adev);
2588 gfx_v6_0_init_pg(adev);
2589 gfx_v6_0_init_cg(adev);
2591 WREG32(mmRLC_RL_BASE, 0);
2592 WREG32(mmRLC_RL_SIZE, 0);
2593 WREG32(mmRLC_LB_CNTL, 0);
2594 WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff);
2595 WREG32(mmRLC_LB_CNTR_INIT, 0);
2596 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
2598 WREG32(mmRLC_MC_CNTL, 0);
2599 WREG32(mmRLC_UCODE_CNTL, 0);
2601 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
2602 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2603 fw_data = (const __le32 *)
2604 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2606 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2608 for (i = 0; i < fw_size; i++) {
2609 WREG32(mmRLC_UCODE_ADDR, i);
2610 WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++));
2612 WREG32(mmRLC_UCODE_ADDR, 0);
2614 gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev));
2615 gfx_v6_0_rlc_start(adev);
2620 static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
2622 u32 data, orig, tmp;
2624 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
2626 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
2627 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2629 WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080);
2631 tmp = gfx_v6_0_halt_rlc(adev);
2633 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2634 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2635 WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff);
2637 gfx_v6_0_wait_for_rlc_serdes(adev);
2638 gfx_v6_0_update_rlc(adev, tmp);
2640 WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff);
2642 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
2644 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2646 RREG32(mmCB_CGTT_SCLK_CTRL);
2647 RREG32(mmCB_CGTT_SCLK_CTRL);
2648 RREG32(mmCB_CGTT_SCLK_CTRL);
2649 RREG32(mmCB_CGTT_SCLK_CTRL);
2651 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
2655 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
2659 static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
2662 u32 data, orig, tmp = 0;
2664 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
2665 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2668 WREG32(mmCGTS_SM_CTRL_REG, data);
2670 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
2671 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
2672 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2674 WREG32(mmCP_MEM_SLP_CNTL, data);
2677 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2680 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2682 tmp = gfx_v6_0_halt_rlc(adev);
2684 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2685 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2686 WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff);
2688 gfx_v6_0_update_rlc(adev, tmp);
2690 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2693 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2695 data = RREG32(mmCP_MEM_SLP_CNTL);
2696 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
2697 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2698 WREG32(mmCP_MEM_SLP_CNTL, data);
2700 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2701 data |= CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK | CGTS_SM_CTRL_REG__OVERRIDE_MASK;
2703 WREG32(mmCGTS_SM_CTRL_REG, data);
2705 tmp = gfx_v6_0_halt_rlc(adev);
2707 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2708 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2709 WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff);
2711 gfx_v6_0_update_rlc(adev, tmp);
2715 static void gfx_v6_0_update_cg(struct amdgpu_device *adev,
2718 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2720 gfx_v6_0_enable_mgcg(adev, true);
2721 gfx_v6_0_enable_cgcg(adev, true);
2723 gfx_v6_0_enable_cgcg(adev, false);
2724 gfx_v6_0_enable_mgcg(adev, false);
2726 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2730 static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
2735 static void gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
2740 static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
2744 orig = data = RREG32(mmRLC_PG_CNTL);
2745 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
2750 WREG32(mmRLC_PG_CNTL, data);
2753 static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
2757 static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev)
2759 const __le32 *fw_data;
2760 volatile u32 *dst_ptr;
2761 int me, i, max_me = 4;
2763 u32 table_offset, table_size;
2765 if (adev->asic_type == CHIP_KAVERI)
2768 if (adev->gfx.rlc.cp_table_ptr == NULL)
2771 dst_ptr = adev->gfx.rlc.cp_table_ptr;
2772 for (me = 0; me < max_me; me++) {
2774 const struct gfx_firmware_header_v1_0 *hdr =
2775 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2776 fw_data = (const __le32 *)
2777 (adev->gfx.ce_fw->data +
2778 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2779 table_offset = le32_to_cpu(hdr->jt_offset);
2780 table_size = le32_to_cpu(hdr->jt_size);
2781 } else if (me == 1) {
2782 const struct gfx_firmware_header_v1_0 *hdr =
2783 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2784 fw_data = (const __le32 *)
2785 (adev->gfx.pfp_fw->data +
2786 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2787 table_offset = le32_to_cpu(hdr->jt_offset);
2788 table_size = le32_to_cpu(hdr->jt_size);
2789 } else if (me == 2) {
2790 const struct gfx_firmware_header_v1_0 *hdr =
2791 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2792 fw_data = (const __le32 *)
2793 (adev->gfx.me_fw->data +
2794 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2795 table_offset = le32_to_cpu(hdr->jt_offset);
2796 table_size = le32_to_cpu(hdr->jt_size);
2797 } else if (me == 3) {
2798 const struct gfx_firmware_header_v1_0 *hdr =
2799 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2800 fw_data = (const __le32 *)
2801 (adev->gfx.mec_fw->data +
2802 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2803 table_offset = le32_to_cpu(hdr->jt_offset);
2804 table_size = le32_to_cpu(hdr->jt_size);
2806 const struct gfx_firmware_header_v1_0 *hdr =
2807 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2808 fw_data = (const __le32 *)
2809 (adev->gfx.mec2_fw->data +
2810 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2811 table_offset = le32_to_cpu(hdr->jt_offset);
2812 table_size = le32_to_cpu(hdr->jt_size);
2815 for (i = 0; i < table_size; i ++) {
2816 dst_ptr[bo_offset + i] =
2817 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
2820 bo_offset += table_size;
2824 static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev,
2827 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
2828 WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10));
2829 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1);
2830 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1);
2832 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0);
2833 (void)RREG32(mmDB_RENDER_CONTROL);
2837 static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev)
2841 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
2843 tmp = RREG32(mmRLC_MAX_PG_CU);
2844 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
2845 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
2846 WREG32(mmRLC_MAX_PG_CU, tmp);
2849 static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
2854 orig = data = RREG32(mmRLC_PG_CNTL);
2855 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
2856 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2858 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2860 WREG32(mmRLC_PG_CNTL, data);
2863 static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
2868 orig = data = RREG32(mmRLC_PG_CNTL);
2869 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
2870 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2872 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2874 WREG32(mmRLC_PG_CNTL, data);
2877 static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev)
2881 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2882 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1);
2883 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2885 tmp = RREG32(mmRLC_AUTO_PG_CTRL);
2886 tmp &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
2887 tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
2888 tmp &= ~RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK;
2889 WREG32(mmRLC_AUTO_PG_CTRL, tmp);
2892 static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
2894 gfx_v6_0_enable_gfx_cgpg(adev, enable);
2895 gfx_v6_0_enable_gfx_static_mgpg(adev, enable);
2896 gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable);
2899 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev)
2902 const struct cs_section_def *sect = NULL;
2903 const struct cs_extent_def *ext = NULL;
2905 if (adev->gfx.rlc.cs_data == NULL)
2908 /* begin clear state */
2910 /* context control state */
2913 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2914 for (ext = sect->section; ext->extent != NULL; ++ext) {
2915 if (sect->id == SECT_CONTEXT)
2916 count += 2 + ext->reg_count;
2921 /* pa_sc_raster_config */
2923 /* end clear state */
2931 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev,
2932 volatile u32 *buffer)
2935 const struct cs_section_def *sect = NULL;
2936 const struct cs_extent_def *ext = NULL;
2938 if (adev->gfx.rlc.cs_data == NULL)
2943 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2944 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2945 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2946 buffer[count++] = cpu_to_le32(0x80000000);
2947 buffer[count++] = cpu_to_le32(0x80000000);
2949 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2950 for (ext = sect->section; ext->extent != NULL; ++ext) {
2951 if (sect->id == SECT_CONTEXT) {
2953 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2954 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
2955 for (i = 0; i < ext->reg_count; i++)
2956 buffer[count++] = cpu_to_le32(ext->extent[i]);
2963 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
2964 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2966 switch (adev->asic_type) {
2969 buffer[count++] = cpu_to_le32(0x2a00126a);
2972 buffer[count++] = cpu_to_le32(0x0000124a);
2975 buffer[count++] = cpu_to_le32(0x00000082);
2978 buffer[count++] = cpu_to_le32(0x00000000);
2981 buffer[count++] = cpu_to_le32(0x00000000);
2985 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2986 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
2988 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
2989 buffer[count++] = cpu_to_le32(0);
2992 static void gfx_v6_0_init_pg(struct amdgpu_device *adev)
2994 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2995 AMD_PG_SUPPORT_GFX_SMG |
2996 AMD_PG_SUPPORT_GFX_DMG |
2998 AMD_PG_SUPPORT_GDS |
2999 AMD_PG_SUPPORT_RLC_SMU_HS)) {
3000 gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true);
3001 gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true);
3002 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3003 gfx_v6_0_init_gfx_cgpg(adev);
3004 gfx_v6_0_enable_cp_pg(adev, true);
3005 gfx_v6_0_enable_gds_pg(adev, true);
3007 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
3008 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
3011 gfx_v6_0_init_ao_cu_mask(adev);
3012 gfx_v6_0_update_gfx_pg(adev, true);
3015 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
3016 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
3020 static void gfx_v6_0_fini_pg(struct amdgpu_device *adev)
3022 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3023 AMD_PG_SUPPORT_GFX_SMG |
3024 AMD_PG_SUPPORT_GFX_DMG |
3026 AMD_PG_SUPPORT_GDS |
3027 AMD_PG_SUPPORT_RLC_SMU_HS)) {
3028 gfx_v6_0_update_gfx_pg(adev, false);
3029 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3030 gfx_v6_0_enable_cp_pg(adev, false);
3031 gfx_v6_0_enable_gds_pg(adev, false);
3036 static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3040 mutex_lock(&adev->gfx.gpu_clock_mutex);
3041 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3042 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
3043 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3044 mutex_unlock(&adev->gfx.gpu_clock_mutex);
3048 static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
3050 if (flags & AMDGPU_HAVE_CTX_SWITCH)
3051 gfx_v6_0_ring_emit_vgt_flush(ring);
3052 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3053 amdgpu_ring_write(ring, 0x80000000);
3054 amdgpu_ring_write(ring, 0);
3058 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
3060 WREG32(mmSQ_IND_INDEX,
3061 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
3062 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
3063 (address << SQ_IND_INDEX__INDEX__SHIFT) |
3064 (SQ_IND_INDEX__FORCE_READ_MASK));
3065 return RREG32(mmSQ_IND_DATA);
3068 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
3069 uint32_t wave, uint32_t thread,
3070 uint32_t regno, uint32_t num, uint32_t *out)
3072 WREG32(mmSQ_IND_INDEX,
3073 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
3074 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
3075 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
3076 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
3077 (SQ_IND_INDEX__FORCE_READ_MASK) |
3078 (SQ_IND_INDEX__AUTO_INCR_MASK));
3080 *(out++) = RREG32(mmSQ_IND_DATA);
3083 static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
3085 /* type 0 wave data */
3086 dst[(*no_fields)++] = 0;
3087 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
3088 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
3089 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
3090 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
3091 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
3092 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
3093 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
3094 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
3095 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
3096 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
3097 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
3098 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
3099 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
3100 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
3101 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
3102 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
3103 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
3104 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
3107 static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
3108 uint32_t wave, uint32_t start,
3109 uint32_t size, uint32_t *dst)
3112 adev, simd, wave, 0,
3113 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
3116 static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = {
3117 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter,
3118 .select_se_sh = &gfx_v6_0_select_se_sh,
3119 .read_wave_data = &gfx_v6_0_read_wave_data,
3120 .read_wave_sgprs = &gfx_v6_0_read_wave_sgprs,
3123 static int gfx_v6_0_early_init(void *handle)
3125 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3127 adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS;
3128 adev->gfx.num_compute_rings = GFX6_NUM_COMPUTE_RINGS;
3129 adev->gfx.funcs = &gfx_v6_0_gfx_funcs;
3130 gfx_v6_0_set_ring_funcs(adev);
3131 gfx_v6_0_set_irq_funcs(adev);
3136 static int gfx_v6_0_sw_init(void *handle)
3138 struct amdgpu_ring *ring;
3139 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3142 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
3146 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq);
3150 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq);
3154 gfx_v6_0_scratch_init(adev);
3156 r = gfx_v6_0_init_microcode(adev);
3158 DRM_ERROR("Failed to load gfx firmware!\n");
3162 r = gfx_v6_0_rlc_init(adev);
3164 DRM_ERROR("Failed to init rlc BOs!\n");
3168 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3169 ring = &adev->gfx.gfx_ring[i];
3170 ring->ring_obj = NULL;
3171 sprintf(ring->name, "gfx");
3172 r = amdgpu_ring_init(adev, ring, 1024,
3173 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
3178 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3181 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
3182 DRM_ERROR("Too many (%d) compute rings!\n", i);
3185 ring = &adev->gfx.compute_ring[i];
3186 ring->ring_obj = NULL;
3187 ring->use_doorbell = false;
3188 ring->doorbell_index = 0;
3192 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
3193 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
3194 r = amdgpu_ring_init(adev, ring, 1024,
3195 &adev->gfx.eop_irq, irq_type);
3203 static int gfx_v6_0_sw_fini(void *handle)
3206 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3208 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3209 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
3210 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3211 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
3213 gfx_v6_0_rlc_fini(adev);
3218 static int gfx_v6_0_hw_init(void *handle)
3221 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3223 gfx_v6_0_gpu_init(adev);
3225 r = gfx_v6_0_rlc_resume(adev);
3229 r = gfx_v6_0_cp_resume(adev);
3233 adev->gfx.ce_ram_size = 0x8000;
3238 static int gfx_v6_0_hw_fini(void *handle)
3240 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3242 gfx_v6_0_cp_enable(adev, false);
3243 gfx_v6_0_rlc_stop(adev);
3244 gfx_v6_0_fini_pg(adev);
3249 static int gfx_v6_0_suspend(void *handle)
3251 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3253 return gfx_v6_0_hw_fini(adev);
3256 static int gfx_v6_0_resume(void *handle)
3258 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3260 return gfx_v6_0_hw_init(adev);
3263 static bool gfx_v6_0_is_idle(void *handle)
3265 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3267 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
3273 static int gfx_v6_0_wait_for_idle(void *handle)
3276 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3278 for (i = 0; i < adev->usec_timeout; i++) {
3279 if (gfx_v6_0_is_idle(handle))
3286 static int gfx_v6_0_soft_reset(void *handle)
3291 static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3292 enum amdgpu_interrupt_state state)
3297 case AMDGPU_IRQ_STATE_DISABLE:
3298 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3299 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3300 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3302 case AMDGPU_IRQ_STATE_ENABLE:
3303 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3304 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3305 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3312 static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3314 enum amdgpu_interrupt_state state)
3318 case AMDGPU_IRQ_STATE_DISABLE:
3320 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3321 cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3322 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
3325 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3326 cp_int_cntl &= ~CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3327 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
3331 case AMDGPU_IRQ_STATE_ENABLE:
3333 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3334 cp_int_cntl |= CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3335 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
3338 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3339 cp_int_cntl |= CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3340 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
3352 static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
3353 struct amdgpu_irq_src *src,
3355 enum amdgpu_interrupt_state state)
3360 case AMDGPU_IRQ_STATE_DISABLE:
3361 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3362 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3363 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3365 case AMDGPU_IRQ_STATE_ENABLE:
3366 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3367 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3368 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3377 static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
3378 struct amdgpu_irq_src *src,
3380 enum amdgpu_interrupt_state state)
3385 case AMDGPU_IRQ_STATE_DISABLE:
3386 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3387 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3388 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3390 case AMDGPU_IRQ_STATE_ENABLE:
3391 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3392 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3393 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3402 static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev,
3403 struct amdgpu_irq_src *src,
3405 enum amdgpu_interrupt_state state)
3408 case AMDGPU_CP_IRQ_GFX_EOP:
3409 gfx_v6_0_set_gfx_eop_interrupt_state(adev, state);
3411 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
3412 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state);
3414 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
3415 gfx_v6_0_set_compute_eop_interrupt_state(adev, 1, state);
3423 static int gfx_v6_0_eop_irq(struct amdgpu_device *adev,
3424 struct amdgpu_irq_src *source,
3425 struct amdgpu_iv_entry *entry)
3427 switch (entry->ring_id) {
3429 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
3433 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id - 1]);
3441 static int gfx_v6_0_priv_reg_irq(struct amdgpu_device *adev,
3442 struct amdgpu_irq_src *source,
3443 struct amdgpu_iv_entry *entry)
3445 DRM_ERROR("Illegal register access in command stream\n");
3446 schedule_work(&adev->reset_work);
3450 static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev,
3451 struct amdgpu_irq_src *source,
3452 struct amdgpu_iv_entry *entry)
3454 DRM_ERROR("Illegal instruction in command stream\n");
3455 schedule_work(&adev->reset_work);
3459 static int gfx_v6_0_set_clockgating_state(void *handle,
3460 enum amd_clockgating_state state)
3463 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3465 if (state == AMD_CG_STATE_GATE)
3468 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
3470 gfx_v6_0_enable_mgcg(adev, true);
3471 gfx_v6_0_enable_cgcg(adev, true);
3473 gfx_v6_0_enable_cgcg(adev, false);
3474 gfx_v6_0_enable_mgcg(adev, false);
3476 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
3481 static int gfx_v6_0_set_powergating_state(void *handle,
3482 enum amd_powergating_state state)
3485 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3487 if (state == AMD_PG_STATE_GATE)
3490 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3491 AMD_PG_SUPPORT_GFX_SMG |
3492 AMD_PG_SUPPORT_GFX_DMG |
3494 AMD_PG_SUPPORT_GDS |
3495 AMD_PG_SUPPORT_RLC_SMU_HS)) {
3496 gfx_v6_0_update_gfx_pg(adev, gate);
3497 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3498 gfx_v6_0_enable_cp_pg(adev, gate);
3499 gfx_v6_0_enable_gds_pg(adev, gate);
3506 static const struct amd_ip_funcs gfx_v6_0_ip_funcs = {
3508 .early_init = gfx_v6_0_early_init,
3510 .sw_init = gfx_v6_0_sw_init,
3511 .sw_fini = gfx_v6_0_sw_fini,
3512 .hw_init = gfx_v6_0_hw_init,
3513 .hw_fini = gfx_v6_0_hw_fini,
3514 .suspend = gfx_v6_0_suspend,
3515 .resume = gfx_v6_0_resume,
3516 .is_idle = gfx_v6_0_is_idle,
3517 .wait_for_idle = gfx_v6_0_wait_for_idle,
3518 .soft_reset = gfx_v6_0_soft_reset,
3519 .set_clockgating_state = gfx_v6_0_set_clockgating_state,
3520 .set_powergating_state = gfx_v6_0_set_powergating_state,
3523 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
3524 .type = AMDGPU_RING_TYPE_GFX,
3527 .support_64bit_ptrs = false,
3528 .get_rptr = gfx_v6_0_ring_get_rptr,
3529 .get_wptr = gfx_v6_0_ring_get_wptr,
3530 .set_wptr = gfx_v6_0_ring_set_wptr_gfx,
3532 5 + /* gfx_v6_0_ring_emit_hdp_flush */
3533 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */
3534 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
3535 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */
3536 17 + 6 + /* gfx_v6_0_ring_emit_vm_flush */
3537 3 + 2, /* gfx_v6_ring_emit_cntxcntl including vgt flush */
3538 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
3539 .emit_ib = gfx_v6_0_ring_emit_ib,
3540 .emit_fence = gfx_v6_0_ring_emit_fence,
3541 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3542 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3543 .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush,
3544 .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate,
3545 .test_ring = gfx_v6_0_ring_test_ring,
3546 .test_ib = gfx_v6_0_ring_test_ib,
3547 .insert_nop = amdgpu_ring_insert_nop,
3548 .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl,
3551 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
3552 .type = AMDGPU_RING_TYPE_COMPUTE,
3555 .get_rptr = gfx_v6_0_ring_get_rptr,
3556 .get_wptr = gfx_v6_0_ring_get_wptr,
3557 .set_wptr = gfx_v6_0_ring_set_wptr_compute,
3559 5 + /* gfx_v6_0_ring_emit_hdp_flush */
3560 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */
3561 7 + /* gfx_v6_0_ring_emit_pipeline_sync */
3562 17 + /* gfx_v6_0_ring_emit_vm_flush */
3563 14 + 14 + 14, /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
3564 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
3565 .emit_ib = gfx_v6_0_ring_emit_ib,
3566 .emit_fence = gfx_v6_0_ring_emit_fence,
3567 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3568 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3569 .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush,
3570 .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate,
3571 .test_ring = gfx_v6_0_ring_test_ring,
3572 .test_ib = gfx_v6_0_ring_test_ib,
3573 .insert_nop = amdgpu_ring_insert_nop,
3576 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev)
3580 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3581 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx;
3582 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3583 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute;
3586 static const struct amdgpu_irq_src_funcs gfx_v6_0_eop_irq_funcs = {
3587 .set = gfx_v6_0_set_eop_interrupt_state,
3588 .process = gfx_v6_0_eop_irq,
3591 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_reg_irq_funcs = {
3592 .set = gfx_v6_0_set_priv_reg_fault_state,
3593 .process = gfx_v6_0_priv_reg_irq,
3596 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_inst_irq_funcs = {
3597 .set = gfx_v6_0_set_priv_inst_fault_state,
3598 .process = gfx_v6_0_priv_inst_irq,
3601 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev)
3603 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
3604 adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs;
3606 adev->gfx.priv_reg_irq.num_types = 1;
3607 adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs;
3609 adev->gfx.priv_inst_irq.num_types = 1;
3610 adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs;
3613 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev)
3615 int i, j, k, counter, active_cu_number = 0;
3616 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
3617 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
3618 unsigned disable_masks[4 * 2];
3621 if (adev->flags & AMD_IS_APU)
3624 ao_cu_num = adev->gfx.config.max_cu_per_sh;
3626 memset(cu_info, 0, sizeof(*cu_info));
3628 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
3630 mutex_lock(&adev->grbm_idx_mutex);
3631 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3632 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3636 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
3638 gfx_v6_0_set_user_cu_inactive_bitmap(
3639 adev, disable_masks[i * 2 + j]);
3640 bitmap = gfx_v6_0_get_cu_enabled(adev);
3641 cu_info->bitmap[i][j] = bitmap;
3643 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
3644 if (bitmap & mask) {
3645 if (counter < ao_cu_num)
3651 active_cu_number += counter;
3653 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
3654 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
3658 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3659 mutex_unlock(&adev->grbm_idx_mutex);
3661 cu_info->number = active_cu_number;
3662 cu_info->ao_cu_mask = ao_cu_mask;
3665 const struct amdgpu_ip_block_version gfx_v6_0_ip_block =
3667 .type = AMD_IP_BLOCK_TYPE_GFX,
3671 .funcs = &gfx_v6_0_ip_funcs,
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