drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a
   3  * copy of this software and associated documentation files (the "Software"),
   4  * to deal in the Software without restriction, including without limitation
   5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   6  * and/or sell copies of the Software, and to permit persons to whom the
   7  * Software is furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18  * OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * Authors: Rafał Miłecki <[email protected]>
  21  *          Alex Deucher <[email protected]>
  22  */
  23 #include <drm/drmP.h>
  24 #include "amdgpu.h"
  25 #include "amdgpu_drv.h"
  26 #include "amdgpu_pm.h"
  27 #include "amdgpu_dpm.h"
  28 #include "atom.h"
  29 #include <linux/power_supply.h>
  30 #include <linux/hwmon.h>
  31 #include <linux/hwmon-sysfs.h>
  32
  33 #include "amd_powerplay.h"
  34
  35 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
  36
  37 static const struct cg_flag_name clocks[] = {
  38         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  39         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  40         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  41         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  42         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  43         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  44         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  45         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  46         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
  47         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
  48         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  49         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  50         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  51         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  52         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
  53         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  54         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  55         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  56         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  57         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  58         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
  59         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
  60         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  61         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
  62         {0, NULL},
  63 };
  64
  65 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  66 {
  67         if (adev->pm.dpm_enabled) {
  68                 mutex_lock(&adev->pm.mutex);
  69                 if (power_supply_is_system_supplied() > 0)
  70                         adev->pm.dpm.ac_power = true;
  71                 else
  72                         adev->pm.dpm.ac_power = false;
  73                 if (adev->powerplay.pp_funcs->enable_bapm)
  74                         amdgpu_dpm_enable_bapm(adev, adev->pm.dpm.ac_power);
  75                 mutex_unlock(&adev->pm.mutex);
  76         }
  77 }
  78
  79 static ssize_t amdgpu_get_dpm_state(struct device *dev,
  80                                     struct device_attribute *attr,
  81                                     char *buf)
  82 {
  83         struct drm_device *ddev = dev_get_drvdata(dev);
  84         struct amdgpu_device *adev = ddev->dev_private;
  85         enum amd_pm_state_type pm;
  86
  87         if (adev->powerplay.pp_funcs->get_current_power_state)
  88                 pm = amdgpu_dpm_get_current_power_state(adev);
  89         else
  90                 pm = adev->pm.dpm.user_state;
  91
  92         return snprintf(buf, PAGE_SIZE, "%s\n",
  93                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
  94                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
  95 }
  96
  97 static ssize_t amdgpu_set_dpm_state(struct device *dev,
  98                                     struct device_attribute *attr,
  99                                     const char *buf,
 100                                     size_t count)
 101 {
 102         struct drm_device *ddev = dev_get_drvdata(dev);
 103         struct amdgpu_device *adev = ddev->dev_private;
 104         enum amd_pm_state_type  state;
 105
 106         if (strncmp("battery", buf, strlen("battery")) == 0)
 107                 state = POWER_STATE_TYPE_BATTERY;
 108         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 109                 state = POWER_STATE_TYPE_BALANCED;
 110         else if (strncmp("performance", buf, strlen("performance")) == 0)
 111                 state = POWER_STATE_TYPE_PERFORMANCE;
 112         else {
 113                 count = -EINVAL;
 114                 goto fail;
 115         }
 116
 117         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 118                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state, NULL);
 119         } else {
 120                 mutex_lock(&adev->pm.mutex);
 121                 adev->pm.dpm.user_state = state;
 122                 mutex_unlock(&adev->pm.mutex);
 123
 124                 /* Can't set dpm state when the card is off */
 125                 if (!(adev->flags & AMD_IS_PX) ||
 126                     (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
 127                         amdgpu_pm_compute_clocks(adev);
 128         }
 129 fail:
 130         return count;
 131 }
 132
 133 static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
 134                                                 struct device_attribute *attr,
 135                                                                 char *buf)
 136 {
 137         struct drm_device *ddev = dev_get_drvdata(dev);
 138         struct amdgpu_device *adev = ddev->dev_private;
 139         enum amd_dpm_forced_level level = 0xff;
 140
 141         if  ((adev->flags & AMD_IS_PX) &&
 142              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 143                 return snprintf(buf, PAGE_SIZE, "off\n");
 144
 145         if (adev->powerplay.pp_funcs->get_performance_level)
 146                 level = amdgpu_dpm_get_performance_level(adev);
 147         else
 148                 level = adev->pm.dpm.forced_level;
 149
 150         return snprintf(buf, PAGE_SIZE, "%s\n",
 151                         (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 152                         (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 153                         (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 154                         (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 155                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 156                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 157                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 158                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 159                         "unknown");
 160 }
 161
 162 static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
 163                                                        struct device_attribute *attr,
 164                                                        const char *buf,
 165                                                        size_t count)
 166 {
 167         struct drm_device *ddev = dev_get_drvdata(dev);
 168         struct amdgpu_device *adev = ddev->dev_private;
 169         enum amd_dpm_forced_level level;
 170         enum amd_dpm_forced_level current_level = 0xff;
 171         int ret = 0;
 172
 173         /* Can't force performance level when the card is off */
 174         if  ((adev->flags & AMD_IS_PX) &&
 175              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 176                 return -EINVAL;
 177
 178         if (adev->powerplay.pp_funcs->get_performance_level)
 179                 current_level = amdgpu_dpm_get_performance_level(adev);
 180
 181         if (strncmp("low", buf, strlen("low")) == 0) {
 182                 level = AMD_DPM_FORCED_LEVEL_LOW;
 183         } else if (strncmp("high", buf, strlen("high")) == 0) {
 184                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 185         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 186                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 187         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 188                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 189         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 190                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 191         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 192                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 193         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 194                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 195         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 196                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 197         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 198                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 199         }  else {
 200                 count = -EINVAL;
 201                 goto fail;
 202         }
 203
 204         if (current_level == level)
 205                 return count;
 206
 207         if (adev->powerplay.pp_funcs->force_performance_level) {
 208                 mutex_lock(&adev->pm.mutex);
 209                 if (adev->pm.dpm.thermal_active) {
 210                         count = -EINVAL;
 211                         mutex_unlock(&adev->pm.mutex);
 212                         goto fail;
 213                 }
 214                 ret = amdgpu_dpm_force_performance_level(adev, level);
 215                 if (ret)
 216                         count = -EINVAL;
 217                 else
 218                         adev->pm.dpm.forced_level = level;
 219                 mutex_unlock(&adev->pm.mutex);
 220         }
 221
 222 fail:
 223         return count;
 224 }
 225
 226 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 227                 struct device_attribute *attr,
 228                 char *buf)
 229 {
 230         struct drm_device *ddev = dev_get_drvdata(dev);
 231         struct amdgpu_device *adev = ddev->dev_private;
 232         struct pp_states_info data;
 233         int i, buf_len;
 234
 235         if (adev->powerplay.pp_funcs->get_pp_num_states)
 236                 amdgpu_dpm_get_pp_num_states(adev, &data);
 237
 238         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 239         for (i = 0; i < data.nums; i++)
 240                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 241                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 242                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 243                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 244                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 245
 246         return buf_len;
 247 }
 248
 249 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 250                 struct device_attribute *attr,
 251                 char *buf)
 252 {
 253         struct drm_device *ddev = dev_get_drvdata(dev);
 254         struct amdgpu_device *adev = ddev->dev_private;
 255         struct pp_states_info data;
 256         enum amd_pm_state_type pm = 0;
 257         int i = 0;
 258
 259         if (adev->powerplay.pp_funcs->get_current_power_state
 260                  && adev->powerplay.pp_funcs->get_pp_num_states) {
 261                 pm = amdgpu_dpm_get_current_power_state(adev);
 262                 amdgpu_dpm_get_pp_num_states(adev, &data);
 263
 264                 for (i = 0; i < data.nums; i++) {
 265                         if (pm == data.states[i])
 266                                 break;
 267                 }
 268
 269                 if (i == data.nums)
 270                         i = -EINVAL;
 271         }
 272
 273         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 274 }
 275
 276 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 277                 struct device_attribute *attr,
 278                 char *buf)
 279 {
 280         struct drm_device *ddev = dev_get_drvdata(dev);
 281         struct amdgpu_device *adev = ddev->dev_private;
 282
 283         if (adev->pp_force_state_enabled)
 284                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 285         else
 286                 return snprintf(buf, PAGE_SIZE, "\n");
 287 }
 288
 289 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 290                 struct device_attribute *attr,
 291                 const char *buf,
 292                 size_t count)
 293 {
 294         struct drm_device *ddev = dev_get_drvdata(dev);
 295         struct amdgpu_device *adev = ddev->dev_private;
 296         enum amd_pm_state_type state = 0;
 297         unsigned long idx;
 298         int ret;
 299
 300         if (strlen(buf) == 1)
 301                 adev->pp_force_state_enabled = false;
 302         else if (adev->powerplay.pp_funcs->dispatch_tasks &&
 303                         adev->powerplay.pp_funcs->get_pp_num_states) {
 304                 struct pp_states_info data;
 305
 306                 ret = kstrtoul(buf, 0, &idx);
 307                 if (ret || idx >= ARRAY_SIZE(data.states)) {
 308                         count = -EINVAL;
 309                         goto fail;
 310                 }
 311
 312                 amdgpu_dpm_get_pp_num_states(adev, &data);
 313                 state = data.states[idx];
 314                 /* only set user selected power states */
 315                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 316                     state != POWER_STATE_TYPE_DEFAULT) {
 317                         amdgpu_dpm_dispatch_task(adev,
 318                                         AMD_PP_TASK_ENABLE_USER_STATE, &state, NULL);
 319                         adev->pp_force_state_enabled = true;
 320                 }
 321         }
 322 fail:
 323         return count;
 324 }
 325
 326 static ssize_t amdgpu_get_pp_table(struct device *dev,
 327                 struct device_attribute *attr,
 328                 char *buf)
 329 {
 330         struct drm_device *ddev = dev_get_drvdata(dev);
 331         struct amdgpu_device *adev = ddev->dev_private;
 332         char *table = NULL;
 333         int size;
 334
 335         if (adev->powerplay.pp_funcs->get_pp_table)
 336                 size = amdgpu_dpm_get_pp_table(adev, &table);
 337         else
 338                 return 0;
 339
 340         if (size >= PAGE_SIZE)
 341                 size = PAGE_SIZE - 1;
 342
 343         memcpy(buf, table, size);
 344
 345         return size;
 346 }
 347
 348 static ssize_t amdgpu_set_pp_table(struct device *dev,
 349                 struct device_attribute *attr,
 350                 const char *buf,
 351                 size_t count)
 352 {
 353         struct drm_device *ddev = dev_get_drvdata(dev);
 354         struct amdgpu_device *adev = ddev->dev_private;
 355
 356         if (adev->powerplay.pp_funcs->set_pp_table)
 357                 amdgpu_dpm_set_pp_table(adev, buf, count);
 358
 359         return count;
 360 }
 361
 362 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
 363                 struct device_attribute *attr,
 364                 char *buf)
 365 {
 366         struct drm_device *ddev = dev_get_drvdata(dev);
 367         struct amdgpu_device *adev = ddev->dev_private;
 368
 369         if (adev->powerplay.pp_funcs->print_clock_levels)
 370                 return amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
 371         else
 372                 return snprintf(buf, PAGE_SIZE, "\n");
 373 }
 374
 375 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
 376                 struct device_attribute *attr,
 377                 const char *buf,
 378                 size_t count)
 379 {
 380         struct drm_device *ddev = dev_get_drvdata(dev);
 381         struct amdgpu_device *adev = ddev->dev_private;
 382         int ret;
 383         long level;
 384         uint32_t i, mask = 0;
 385         char sub_str[2];
 386
 387         for (i = 0; i < strlen(buf); i++) {
 388                 if (*(buf + i) == '\n')
 389                         continue;
 390                 sub_str[0] = *(buf + i);
 391                 sub_str[1] = '\0';
 392                 ret = kstrtol(sub_str, 0, &level);
 393
 394                 if (ret) {
 395                         count = -EINVAL;
 396                         goto fail;
 397                 }
 398                 mask |= 1 << level;
 399         }
 400
 401         if (adev->powerplay.pp_funcs->force_clock_level)
 402                 amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
 403
 404 fail:
 405         return count;
 406 }
 407
 408 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
 409                 struct device_attribute *attr,
 410                 char *buf)
 411 {
 412         struct drm_device *ddev = dev_get_drvdata(dev);
 413         struct amdgpu_device *adev = ddev->dev_private;
 414
 415         if (adev->powerplay.pp_funcs->print_clock_levels)
 416                 return amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
 417         else
 418                 return snprintf(buf, PAGE_SIZE, "\n");
 419 }
 420
 421 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
 422                 struct device_attribute *attr,
 423                 const char *buf,
 424                 size_t count)
 425 {
 426         struct drm_device *ddev = dev_get_drvdata(dev);
 427         struct amdgpu_device *adev = ddev->dev_private;
 428         int ret;
 429         long level;
 430         uint32_t i, mask = 0;
 431         char sub_str[2];
 432
 433         for (i = 0; i < strlen(buf); i++) {
 434                 if (*(buf + i) == '\n')
 435                         continue;
 436                 sub_str[0] = *(buf + i);
 437                 sub_str[1] = '\0';
 438                 ret = kstrtol(sub_str, 0, &level);
 439
 440                 if (ret) {
 441                         count = -EINVAL;
 442                         goto fail;
 443                 }
 444                 mask |= 1 << level;
 445         }
 446         if (adev->powerplay.pp_funcs->force_clock_level)
 447                 amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
 448
 449 fail:
 450         return count;
 451 }
 452
 453 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
 454                 struct device_attribute *attr,
 455                 char *buf)
 456 {
 457         struct drm_device *ddev = dev_get_drvdata(dev);
 458         struct amdgpu_device *adev = ddev->dev_private;
 459
 460         if (adev->powerplay.pp_funcs->print_clock_levels)
 461                 return amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
 462         else
 463                 return snprintf(buf, PAGE_SIZE, "\n");
 464 }
 465
 466 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
 467                 struct device_attribute *attr,
 468                 const char *buf,
 469                 size_t count)
 470 {
 471         struct drm_device *ddev = dev_get_drvdata(dev);
 472         struct amdgpu_device *adev = ddev->dev_private;
 473         int ret;
 474         long level;
 475         uint32_t i, mask = 0;
 476         char sub_str[2];
 477
 478         for (i = 0; i < strlen(buf); i++) {
 479                 if (*(buf + i) == '\n')
 480                         continue;
 481                 sub_str[0] = *(buf + i);
 482                 sub_str[1] = '\0';
 483                 ret = kstrtol(sub_str, 0, &level);
 484
 485                 if (ret) {
 486                         count = -EINVAL;
 487                         goto fail;
 488                 }
 489                 mask |= 1 << level;
 490         }
 491         if (adev->powerplay.pp_funcs->force_clock_level)
 492                 amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
 493
 494 fail:
 495         return count;
 496 }
 497
 498 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
 499                 struct device_attribute *attr,
 500                 char *buf)
 501 {
 502         struct drm_device *ddev = dev_get_drvdata(dev);
 503         struct amdgpu_device *adev = ddev->dev_private;
 504         uint32_t value = 0;
 505
 506         if (adev->powerplay.pp_funcs->get_sclk_od)
 507                 value = amdgpu_dpm_get_sclk_od(adev);
 508
 509         return snprintf(buf, PAGE_SIZE, "%d\n", value);
 510 }
 511
 512 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
 513                 struct device_attribute *attr,
 514                 const char *buf,
 515                 size_t count)
 516 {
 517         struct drm_device *ddev = dev_get_drvdata(dev);
 518         struct amdgpu_device *adev = ddev->dev_private;
 519         int ret;
 520         long int value;
 521
 522         ret = kstrtol(buf, 0, &value);
 523
 524         if (ret) {
 525                 count = -EINVAL;
 526                 goto fail;
 527         }
 528         if (adev->powerplay.pp_funcs->set_sclk_od)
 529                 amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
 530
 531         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 532                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL, NULL);
 533         } else {
 534                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
 535                 amdgpu_pm_compute_clocks(adev);
 536         }
 537
 538 fail:
 539         return count;
 540 }
 541
 542 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
 543                 struct device_attribute *attr,
 544                 char *buf)
 545 {
 546         struct drm_device *ddev = dev_get_drvdata(dev);
 547         struct amdgpu_device *adev = ddev->dev_private;
 548         uint32_t value = 0;
 549
 550         if (adev->powerplay.pp_funcs->get_mclk_od)
 551                 value = amdgpu_dpm_get_mclk_od(adev);
 552
 553         return snprintf(buf, PAGE_SIZE, "%d\n", value);
 554 }
 555
 556 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
 557                 struct device_attribute *attr,
 558                 const char *buf,
 559                 size_t count)
 560 {
 561         struct drm_device *ddev = dev_get_drvdata(dev);
 562         struct amdgpu_device *adev = ddev->dev_private;
 563         int ret;
 564         long int value;
 565
 566         ret = kstrtol(buf, 0, &value);
 567
 568         if (ret) {
 569                 count = -EINVAL;
 570                 goto fail;
 571         }
 572         if (adev->powerplay.pp_funcs->set_mclk_od)
 573                 amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
 574
 575         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 576                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL, NULL);
 577         } else {
 578                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
 579                 amdgpu_pm_compute_clocks(adev);
 580         }
 581
 582 fail:
 583         return count;
 584 }
 585
 586 static ssize_t amdgpu_get_pp_power_profile(struct device *dev,
 587                 char *buf, struct amd_pp_profile *query)
 588 {
 589         struct drm_device *ddev = dev_get_drvdata(dev);
 590         struct amdgpu_device *adev = ddev->dev_private;
 591         int ret = 0xff;
 592
 593         if (adev->powerplay.pp_funcs->get_power_profile_state)
 594                 ret = amdgpu_dpm_get_power_profile_state(
 595                                 adev, query);
 596
 597         if (ret)
 598                 return ret;
 599
 600         return snprintf(buf, PAGE_SIZE,
 601                         "%d %d %d %d %d\n",
 602                         query->min_sclk / 100,
 603                         query->min_mclk / 100,
 604                         query->activity_threshold,
 605                         query->up_hyst,
 606                         query->down_hyst);
 607 }
 608
 609 static ssize_t amdgpu_get_pp_gfx_power_profile(struct device *dev,
 610                 struct device_attribute *attr,
 611                 char *buf)
 612 {
 613         struct amd_pp_profile query = {0};
 614
 615         query.type = AMD_PP_GFX_PROFILE;
 616
 617         return amdgpu_get_pp_power_profile(dev, buf, &query);
 618 }
 619
 620 static ssize_t amdgpu_get_pp_compute_power_profile(struct device *dev,
 621                 struct device_attribute *attr,
 622                 char *buf)
 623 {
 624         struct amd_pp_profile query = {0};
 625
 626         query.type = AMD_PP_COMPUTE_PROFILE;
 627
 628         return amdgpu_get_pp_power_profile(dev, buf, &query);
 629 }
 630
 631 static ssize_t amdgpu_set_pp_power_profile(struct device *dev,
 632                 const char *buf,
 633                 size_t count,
 634                 struct amd_pp_profile *request)
 635 {
 636         struct drm_device *ddev = dev_get_drvdata(dev);
 637         struct amdgpu_device *adev = ddev->dev_private;
 638         uint32_t loop = 0;
 639         char *sub_str, buf_cpy[128], *tmp_str;
 640         const char delimiter[3] = {' ', '\n', '\0'};
 641         long int value;
 642         int ret = 0xff;
 643
 644         if (strncmp("reset", buf, strlen("reset")) == 0) {
 645                 if (adev->powerplay.pp_funcs->reset_power_profile_state)
 646                         ret = amdgpu_dpm_reset_power_profile_state(
 647                                         adev, request);
 648                 if (ret) {
 649                         count = -EINVAL;
 650                         goto fail;
 651                 }
 652                 return count;
 653         }
 654
 655         if (strncmp("set", buf, strlen("set")) == 0) {
 656                 if (adev->powerplay.pp_funcs->set_power_profile_state)
 657                         ret = amdgpu_dpm_set_power_profile_state(
 658                                         adev, request);
 659
 660                 if (ret) {
 661                         count = -EINVAL;
 662                         goto fail;
 663                 }
 664                 return count;
 665         }
 666
 667         if (count + 1 >= 128) {
 668                 count = -EINVAL;
 669                 goto fail;
 670         }
 671
 672         memcpy(buf_cpy, buf, count + 1);
 673         tmp_str = buf_cpy;
 674
 675         while (tmp_str[0]) {
 676                 sub_str = strsep(&tmp_str, delimiter);
 677                 ret = kstrtol(sub_str, 0, &value);
 678                 if (ret) {
 679                         count = -EINVAL;
 680                         goto fail;
 681                 }
 682
 683                 switch (loop) {
 684                 case 0:
 685                         /* input unit MHz convert to dpm table unit 10KHz*/
 686                         request->min_sclk = (uint32_t)value * 100;
 687                         break;
 688                 case 1:
 689                         /* input unit MHz convert to dpm table unit 10KHz*/
 690                         request->min_mclk = (uint32_t)value * 100;
 691                         break;
 692                 case 2:
 693                         request->activity_threshold = (uint16_t)value;
 694                         break;
 695                 case 3:
 696                         request->up_hyst = (uint8_t)value;
 697                         break;
 698                 case 4:
 699                         request->down_hyst = (uint8_t)value;
 700                         break;
 701                 default:
 702                         break;
 703                 }
 704
 705                 loop++;
 706         }
 707         if (adev->powerplay.pp_funcs->set_power_profile_state)
 708                 ret = amdgpu_dpm_set_power_profile_state(adev, request);
 709
 710         if (ret)
 711                 count = -EINVAL;
 712
 713 fail:
 714         return count;
 715 }
 716
 717 static ssize_t amdgpu_set_pp_gfx_power_profile(struct device *dev,
 718                 struct device_attribute *attr,
 719                 const char *buf,
 720                 size_t count)
 721 {
 722         struct amd_pp_profile request = {0};
 723
 724         request.type = AMD_PP_GFX_PROFILE;
 725
 726         return amdgpu_set_pp_power_profile(dev, buf, count, &request);
 727 }
 728
 729 static ssize_t amdgpu_set_pp_compute_power_profile(struct device *dev,
 730                 struct device_attribute *attr,
 731                 const char *buf,
 732                 size_t count)
 733 {
 734         struct amd_pp_profile request = {0};
 735
 736         request.type = AMD_PP_COMPUTE_PROFILE;
 737
 738         return amdgpu_set_pp_power_profile(dev, buf, count, &request);
 739 }
 740
 741 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
 742 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
 743                    amdgpu_get_dpm_forced_performance_level,
 744                    amdgpu_set_dpm_forced_performance_level);
 745 static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
 746 static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
 747 static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
 748                 amdgpu_get_pp_force_state,
 749                 amdgpu_set_pp_force_state);
 750 static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
 751                 amdgpu_get_pp_table,
 752                 amdgpu_set_pp_table);
 753 static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
 754                 amdgpu_get_pp_dpm_sclk,
 755                 amdgpu_set_pp_dpm_sclk);
 756 static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
 757                 amdgpu_get_pp_dpm_mclk,
 758                 amdgpu_set_pp_dpm_mclk);
 759 static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
 760                 amdgpu_get_pp_dpm_pcie,
 761                 amdgpu_set_pp_dpm_pcie);
 762 static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR,
 763                 amdgpu_get_pp_sclk_od,
 764                 amdgpu_set_pp_sclk_od);
 765 static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR,
 766                 amdgpu_get_pp_mclk_od,
 767                 amdgpu_set_pp_mclk_od);
 768 static DEVICE_ATTR(pp_gfx_power_profile, S_IRUGO | S_IWUSR,
 769                 amdgpu_get_pp_gfx_power_profile,
 770                 amdgpu_set_pp_gfx_power_profile);
 771 static DEVICE_ATTR(pp_compute_power_profile, S_IRUGO | S_IWUSR,
 772                 amdgpu_get_pp_compute_power_profile,
 773                 amdgpu_set_pp_compute_power_profile);
 774
 775 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
 776                                       struct device_attribute *attr,
 777                                       char *buf)
 778 {
 779         struct amdgpu_device *adev = dev_get_drvdata(dev);
 780         struct drm_device *ddev = adev->ddev;
 781         int temp;
 782
 783         /* Can't get temperature when the card is off */
 784         if  ((adev->flags & AMD_IS_PX) &&
 785              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 786                 return -EINVAL;
 787
 788         if (!adev->powerplay.pp_funcs->get_temperature)
 789                 temp = 0;
 790         else
 791                 temp = amdgpu_dpm_get_temperature(adev);
 792
 793         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 794 }
 795
 796 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
 797                                              struct device_attribute *attr,
 798                                              char *buf)
 799 {
 800         struct amdgpu_device *adev = dev_get_drvdata(dev);
 801         int hyst = to_sensor_dev_attr(attr)->index;
 802         int temp;
 803
 804         if (hyst)
 805                 temp = adev->pm.dpm.thermal.min_temp;
 806         else
 807                 temp = adev->pm.dpm.thermal.max_temp;
 808
 809         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 810 }
 811
 812 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
 813                                             struct device_attribute *attr,
 814                                             char *buf)
 815 {
 816         struct amdgpu_device *adev = dev_get_drvdata(dev);
 817         u32 pwm_mode = 0;
 818
 819         if (!adev->powerplay.pp_funcs->get_fan_control_mode)
 820                 return -EINVAL;
 821
 822         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
 823
 824         return sprintf(buf, "%i\n", pwm_mode);
 825 }
 826
 827 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
 828                                             struct device_attribute *attr,
 829                                             const char *buf,
 830                                             size_t count)
 831 {
 832         struct amdgpu_device *adev = dev_get_drvdata(dev);
 833         int err;
 834         int value;
 835
 836         if (!adev->powerplay.pp_funcs->set_fan_control_mode)
 837                 return -EINVAL;
 838
 839         err = kstrtoint(buf, 10, &value);
 840         if (err)
 841                 return err;
 842
 843         amdgpu_dpm_set_fan_control_mode(adev, value);
 844
 845         return count;
 846 }
 847
 848 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
 849                                          struct device_attribute *attr,
 850                                          char *buf)
 851 {
 852         return sprintf(buf, "%i\n", 0);
 853 }
 854
 855 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
 856                                          struct device_attribute *attr,
 857                                          char *buf)
 858 {
 859         return sprintf(buf, "%i\n", 255);
 860 }
 861
 862 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
 863                                      struct device_attribute *attr,
 864                                      const char *buf, size_t count)
 865 {
 866         struct amdgpu_device *adev = dev_get_drvdata(dev);
 867         int err;
 868         u32 value;
 869
 870         err = kstrtou32(buf, 10, &value);
 871         if (err)
 872                 return err;
 873
 874         value = (value * 100) / 255;
 875
 876         if (adev->powerplay.pp_funcs->set_fan_speed_percent) {
 877                 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
 878                 if (err)
 879                         return err;
 880         }
 881
 882         return count;
 883 }
 884
 885 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
 886                                      struct device_attribute *attr,
 887                                      char *buf)
 888 {
 889         struct amdgpu_device *adev = dev_get_drvdata(dev);
 890         int err;
 891         u32 speed = 0;
 892
 893         if (adev->powerplay.pp_funcs->get_fan_speed_percent) {
 894                 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
 895                 if (err)
 896                         return err;
 897         }
 898
 899         speed = (speed * 255) / 100;
 900
 901         return sprintf(buf, "%i\n", speed);
 902 }
 903
 904 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
 905                                            struct device_attribute *attr,
 906                                            char *buf)
 907 {
 908         struct amdgpu_device *adev = dev_get_drvdata(dev);
 909         int err;
 910         u32 speed = 0;
 911
 912         if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
 913                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
 914                 if (err)
 915                         return err;
 916         }
 917
 918         return sprintf(buf, "%i\n", speed);
 919 }
 920
 921 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0);
 922 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
 923 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
 924 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
 925 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
 926 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
 927 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
 928 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
 929
 930 static struct attribute *hwmon_attributes[] = {
 931         &sensor_dev_attr_temp1_input.dev_attr.attr,
 932         &sensor_dev_attr_temp1_crit.dev_attr.attr,
 933         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
 934         &sensor_dev_attr_pwm1.dev_attr.attr,
 935         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
 936         &sensor_dev_attr_pwm1_min.dev_attr.attr,
 937         &sensor_dev_attr_pwm1_max.dev_attr.attr,
 938         &sensor_dev_attr_fan1_input.dev_attr.attr,
 939         NULL
 940 };
 941
 942 static umode_t hwmon_attributes_visible(struct kobject *kobj,
 943                                         struct attribute *attr, int index)
 944 {
 945         struct device *dev = kobj_to_dev(kobj);
 946         struct amdgpu_device *adev = dev_get_drvdata(dev);
 947         umode_t effective_mode = attr->mode;
 948
 949         /* no skipping for powerplay */
 950         if (adev->powerplay.cgs_device)
 951                 return effective_mode;
 952
 953         /* Skip limit attributes if DPM is not enabled */
 954         if (!adev->pm.dpm_enabled &&
 955             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
 956              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
 957              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
 958              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
 959              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
 960              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
 961                 return 0;
 962
 963         /* Skip fan attributes if fan is not present */
 964         if (adev->pm.no_fan &&
 965             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
 966              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
 967              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
 968              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
 969                 return 0;
 970
 971         /* mask fan attributes if we have no bindings for this asic to expose */
 972         if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
 973              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
 974             (!adev->powerplay.pp_funcs->get_fan_control_mode &&
 975              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
 976                 effective_mode &= ~S_IRUGO;
 977
 978         if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
 979              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
 980             (!adev->powerplay.pp_funcs->set_fan_control_mode &&
 981              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
 982                 effective_mode &= ~S_IWUSR;
 983
 984         /* hide max/min values if we can't both query and manage the fan */
 985         if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
 986              !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
 987             (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
 988              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
 989                 return 0;
 990
 991         /* requires powerplay */
 992         if (attr == &sensor_dev_attr_fan1_input.dev_attr.attr)
 993                 return 0;
 994
 995         return effective_mode;
 996 }
 997
 998 static const struct attribute_group hwmon_attrgroup = {
 999         .attrs = hwmon_attributes,
1000         .is_visible = hwmon_attributes_visible,
1001 };
1002
1003 static const struct attribute_group *hwmon_groups[] = {
1004         &hwmon_attrgroup,
1005         NULL
1006 };
1007
1008 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
1009 {
1010         struct amdgpu_device *adev =
1011                 container_of(work, struct amdgpu_device,
1012                              pm.dpm.thermal.work);
1013         /* switch to the thermal state */
1014         enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
1015
1016         if (!adev->pm.dpm_enabled)
1017                 return;
1018
1019         if (adev->powerplay.pp_funcs->get_temperature) {
1020                 int temp = amdgpu_dpm_get_temperature(adev);
1021
1022                 if (temp < adev->pm.dpm.thermal.min_temp)
1023                         /* switch back the user state */
1024                         dpm_state = adev->pm.dpm.user_state;
1025         } else {
1026                 if (adev->pm.dpm.thermal.high_to_low)
1027                         /* switch back the user state */
1028                         dpm_state = adev->pm.dpm.user_state;
1029         }
1030         mutex_lock(&adev->pm.mutex);
1031         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
1032                 adev->pm.dpm.thermal_active = true;
1033         else
1034                 adev->pm.dpm.thermal_active = false;
1035         adev->pm.dpm.state = dpm_state;
1036         mutex_unlock(&adev->pm.mutex);
1037
1038         amdgpu_pm_compute_clocks(adev);
1039 }
1040
1041 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
1042                                                      enum amd_pm_state_type dpm_state)
1043 {
1044         int i;
1045         struct amdgpu_ps *ps;
1046         u32 ui_class;
1047         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
1048                 true : false;
1049
1050         /* check if the vblank period is too short to adjust the mclk */
1051         if (single_display && adev->powerplay.pp_funcs->vblank_too_short) {
1052                 if (amdgpu_dpm_vblank_too_short(adev))
1053                         single_display = false;
1054         }
1055
1056         /* certain older asics have a separare 3D performance state,
1057          * so try that first if the user selected performance
1058          */
1059         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
1060                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
1061         /* balanced states don't exist at the moment */
1062         if (dpm_state == POWER_STATE_TYPE_BALANCED)
1063                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1064
1065 restart_search:
1066         /* Pick the best power state based on current conditions */
1067         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
1068                 ps = &adev->pm.dpm.ps[i];
1069                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
1070                 switch (dpm_state) {
1071                 /* user states */
1072                 case POWER_STATE_TYPE_BATTERY:
1073                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
1074                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1075                                         if (single_display)
1076                                                 return ps;
1077                                 } else
1078                                         return ps;
1079                         }
1080                         break;
1081                 case POWER_STATE_TYPE_BALANCED:
1082                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
1083                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1084                                         if (single_display)
1085                                                 return ps;
1086                                 } else
1087                                         return ps;
1088                         }
1089                         break;
1090                 case POWER_STATE_TYPE_PERFORMANCE:
1091                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
1092                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1093                                         if (single_display)
1094                                                 return ps;
1095                                 } else
1096                                         return ps;
1097                         }
1098                         break;
1099                 /* internal states */
1100                 case POWER_STATE_TYPE_INTERNAL_UVD:
1101                         if (adev->pm.dpm.uvd_ps)
1102                                 return adev->pm.dpm.uvd_ps;
1103                         else
1104                                 break;
1105                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1106                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
1107                                 return ps;
1108                         break;
1109                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1110                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
1111                                 return ps;
1112                         break;
1113                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1114                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
1115                                 return ps;
1116                         break;
1117                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1118                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
1119                                 return ps;
1120                         break;
1121                 case POWER_STATE_TYPE_INTERNAL_BOOT:
1122                         return adev->pm.dpm.boot_ps;
1123                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
1124                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
1125                                 return ps;
1126                         break;
1127                 case POWER_STATE_TYPE_INTERNAL_ACPI:
1128                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
1129                                 return ps;
1130                         break;
1131                 case POWER_STATE_TYPE_INTERNAL_ULV:
1132                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
1133                                 return ps;
1134                         break;
1135                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
1136                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
1137                                 return ps;
1138                         break;
1139                 default:
1140                         break;
1141                 }
1142         }
1143         /* use a fallback state if we didn't match */
1144         switch (dpm_state) {
1145         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1146                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1147                 goto restart_search;
1148         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1149         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1150         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1151                 if (adev->pm.dpm.uvd_ps) {
1152                         return adev->pm.dpm.uvd_ps;
1153                 } else {
1154                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1155                         goto restart_search;
1156                 }
1157         case POWER_STATE_TYPE_INTERNAL_THERMAL:
1158                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
1159                 goto restart_search;
1160         case POWER_STATE_TYPE_INTERNAL_ACPI:
1161                 dpm_state = POWER_STATE_TYPE_BATTERY;
1162                 goto restart_search;
1163         case POWER_STATE_TYPE_BATTERY:
1164         case POWER_STATE_TYPE_BALANCED:
1165         case POWER_STATE_TYPE_INTERNAL_3DPERF:
1166                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1167                 goto restart_search;
1168         default:
1169                 break;
1170         }
1171
1172         return NULL;
1173 }
1174
1175 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
1176 {
1177         struct amdgpu_ps *ps;
1178         enum amd_pm_state_type dpm_state;
1179         int ret;
1180         bool equal = false;
1181
1182         /* if dpm init failed */
1183         if (!adev->pm.dpm_enabled)
1184                 return;
1185
1186         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
1187                 /* add other state override checks here */
1188                 if ((!adev->pm.dpm.thermal_active) &&
1189                     (!adev->pm.dpm.uvd_active))
1190                         adev->pm.dpm.state = adev->pm.dpm.user_state;
1191         }
1192         dpm_state = adev->pm.dpm.state;
1193
1194         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
1195         if (ps)
1196                 adev->pm.dpm.requested_ps = ps;
1197         else
1198                 return;
1199
1200         if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) {
1201                 printk("switching from power state:\n");
1202                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
1203                 printk("switching to power state:\n");
1204                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
1205         }
1206
1207         /* update whether vce is active */
1208         ps->vce_active = adev->pm.dpm.vce_active;
1209         if (adev->powerplay.pp_funcs->display_configuration_changed)
1210                 amdgpu_dpm_display_configuration_changed(adev);
1211
1212         ret = amdgpu_dpm_pre_set_power_state(adev);
1213         if (ret)
1214                 return;
1215
1216         if (adev->powerplay.pp_funcs->check_state_equal) {
1217                 if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
1218                         equal = false;
1219         }
1220
1221         if (equal)
1222                 return;
1223
1224         amdgpu_dpm_set_power_state(adev);
1225         amdgpu_dpm_post_set_power_state(adev);
1226
1227         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
1228         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
1229
1230         if (adev->powerplay.pp_funcs->force_performance_level) {
1231                 if (adev->pm.dpm.thermal_active) {
1232                         enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
1233                         /* force low perf level for thermal */
1234                         amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
1235                         /* save the user's level */
1236                         adev->pm.dpm.forced_level = level;
1237                 } else {
1238                         /* otherwise, user selected level */
1239                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
1240                 }
1241         }
1242 }
1243
1244 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
1245 {
1246         if (adev->powerplay.pp_funcs->powergate_uvd) {
1247                 /* enable/disable UVD */
1248                 mutex_lock(&adev->pm.mutex);
1249                 amdgpu_dpm_powergate_uvd(adev, !enable);
1250                 mutex_unlock(&adev->pm.mutex);
1251         } else {
1252                 if (enable) {
1253                         mutex_lock(&adev->pm.mutex);
1254                         adev->pm.dpm.uvd_active = true;
1255                         adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
1256                         mutex_unlock(&adev->pm.mutex);
1257                 } else {
1258                         mutex_lock(&adev->pm.mutex);
1259                         adev->pm.dpm.uvd_active = false;
1260                         mutex_unlock(&adev->pm.mutex);
1261                 }
1262                 amdgpu_pm_compute_clocks(adev);
1263         }
1264 }
1265
1266 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
1267 {
1268         if (adev->powerplay.pp_funcs->powergate_vce) {
1269                 /* enable/disable VCE */
1270                 mutex_lock(&adev->pm.mutex);
1271                 amdgpu_dpm_powergate_vce(adev, !enable);
1272                 mutex_unlock(&adev->pm.mutex);
1273         } else {
1274                 if (enable) {
1275                         mutex_lock(&adev->pm.mutex);
1276                         adev->pm.dpm.vce_active = true;
1277                         /* XXX select vce level based on ring/task */
1278                         adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;
1279                         mutex_unlock(&adev->pm.mutex);
1280                         amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1281                                                         AMD_CG_STATE_UNGATE);
1282                         amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1283                                                         AMD_PG_STATE_UNGATE);
1284                         amdgpu_pm_compute_clocks(adev);
1285                 } else {
1286                         amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1287                                                         AMD_PG_STATE_GATE);
1288                         amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1289                                                         AMD_CG_STATE_GATE);
1290                         mutex_lock(&adev->pm.mutex);
1291                         adev->pm.dpm.vce_active = false;
1292                         mutex_unlock(&adev->pm.mutex);
1293                         amdgpu_pm_compute_clocks(adev);
1294                 }
1295
1296         }
1297 }
1298
1299 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
1300 {
1301         int i;
1302
1303         if (adev->powerplay.pp_funcs->print_power_state == NULL)
1304                 return;
1305
1306         for (i = 0; i < adev->pm.dpm.num_ps; i++)
1307                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
1308
1309 }
1310
1311 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
1312 {
1313         int ret;
1314
1315         if (adev->pm.sysfs_initialized)
1316                 return 0;
1317
1318         if (adev->pm.dpm_enabled == 0)
1319                 return 0;
1320
1321         if (adev->powerplay.pp_funcs->get_temperature == NULL)
1322                 return 0;
1323
1324         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
1325                                                                    DRIVER_NAME, adev,
1326                                                                    hwmon_groups);
1327         if (IS_ERR(adev->pm.int_hwmon_dev)) {
1328                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
1329                 dev_err(adev->dev,
1330                         "Unable to register hwmon device: %d\n", ret);
1331                 return ret;
1332         }
1333
1334         ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
1335         if (ret) {
1336                 DRM_ERROR("failed to create device file for dpm state\n");
1337                 return ret;
1338         }
1339         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1340         if (ret) {
1341                 DRM_ERROR("failed to create device file for dpm state\n");
1342                 return ret;
1343         }
1344
1345
1346         ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
1347         if (ret) {
1348                 DRM_ERROR("failed to create device file pp_num_states\n");
1349                 return ret;
1350         }
1351         ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
1352         if (ret) {
1353                 DRM_ERROR("failed to create device file pp_cur_state\n");
1354                 return ret;
1355         }
1356         ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
1357         if (ret) {
1358                 DRM_ERROR("failed to create device file pp_force_state\n");
1359                 return ret;
1360         }
1361         ret = device_create_file(adev->dev, &dev_attr_pp_table);
1362         if (ret) {
1363                 DRM_ERROR("failed to create device file pp_table\n");
1364                 return ret;
1365         }
1366
1367         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
1368         if (ret) {
1369                 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
1370                 return ret;
1371         }
1372         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
1373         if (ret) {
1374                 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
1375                 return ret;
1376         }
1377         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
1378         if (ret) {
1379                 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
1380                 return ret;
1381         }
1382         ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
1383         if (ret) {
1384                 DRM_ERROR("failed to create device file pp_sclk_od\n");
1385                 return ret;
1386         }
1387         ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od);
1388         if (ret) {
1389                 DRM_ERROR("failed to create device file pp_mclk_od\n");
1390                 return ret;
1391         }
1392         ret = device_create_file(adev->dev,
1393                         &dev_attr_pp_gfx_power_profile);
1394         if (ret) {
1395                 DRM_ERROR("failed to create device file "
1396                                 "pp_gfx_power_profile\n");
1397                 return ret;
1398         }
1399         ret = device_create_file(adev->dev,
1400                         &dev_attr_pp_compute_power_profile);
1401         if (ret) {
1402                 DRM_ERROR("failed to create device file "
1403                                 "pp_compute_power_profile\n");
1404                 return ret;
1405         }
1406
1407         ret = amdgpu_debugfs_pm_init(adev);
1408         if (ret) {
1409                 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1410                 return ret;
1411         }
1412
1413         adev->pm.sysfs_initialized = true;
1414
1415         return 0;
1416 }
1417
1418 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
1419 {
1420         if (adev->pm.dpm_enabled == 0)
1421                 return;
1422
1423         if (adev->pm.int_hwmon_dev)
1424                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
1425         device_remove_file(adev->dev, &dev_attr_power_dpm_state);
1426         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1427
1428         device_remove_file(adev->dev, &dev_attr_pp_num_states);
1429         device_remove_file(adev->dev, &dev_attr_pp_cur_state);
1430         device_remove_file(adev->dev, &dev_attr_pp_force_state);
1431         device_remove_file(adev->dev, &dev_attr_pp_table);
1432
1433         device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
1434         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
1435         device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
1436         device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
1437         device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
1438         device_remove_file(adev->dev,
1439                         &dev_attr_pp_gfx_power_profile);
1440         device_remove_file(adev->dev,
1441                         &dev_attr_pp_compute_power_profile);
1442 }
1443
1444 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
1445 {
1446         struct drm_device *ddev = adev->ddev;
1447         struct drm_crtc *crtc;
1448         struct amdgpu_crtc *amdgpu_crtc;
1449         int i = 0;
1450
1451         if (!adev->pm.dpm_enabled)
1452                 return;
1453
1454         if (adev->mode_info.num_crtc)
1455                 amdgpu_display_bandwidth_update(adev);
1456
1457         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1458                 struct amdgpu_ring *ring = adev->rings[i];
1459                 if (ring && ring->ready)
1460                         amdgpu_fence_wait_empty(ring);
1461         }
1462
1463         if (adev->powerplay.pp_funcs->dispatch_tasks) {
1464                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL, NULL);
1465         } else {
1466                 mutex_lock(&adev->pm.mutex);
1467                 adev->pm.dpm.new_active_crtcs = 0;
1468                 adev->pm.dpm.new_active_crtc_count = 0;
1469                 if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
1470                         list_for_each_entry(crtc,
1471                                             &ddev->mode_config.crtc_list, head) {
1472                                 amdgpu_crtc = to_amdgpu_crtc(crtc);
1473                                 if (amdgpu_crtc->enabled) {
1474                                         adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id);
1475                                         adev->pm.dpm.new_active_crtc_count++;
1476                                 }
1477                         }
1478                 }
1479                 /* update battery/ac status */
1480                 if (power_supply_is_system_supplied() > 0)
1481                         adev->pm.dpm.ac_power = true;
1482                 else
1483                         adev->pm.dpm.ac_power = false;
1484
1485                 amdgpu_dpm_change_power_state_locked(adev);
1486
1487                 mutex_unlock(&adev->pm.mutex);
1488         }
1489 }
1490
1491 /*
1492  * Debugfs info
1493  */
1494 #if defined(CONFIG_DEBUG_FS)
1495
1496 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
1497 {
1498         uint32_t value;
1499         struct pp_gpu_power query = {0};
1500         int size;
1501
1502         /* sanity check PP is enabled */
1503         if (!(adev->powerplay.pp_funcs &&
1504               adev->powerplay.pp_funcs->read_sensor))
1505               return -EINVAL;
1506
1507         /* GPU Clocks */
1508         size = sizeof(value);
1509         seq_printf(m, "GFX Clocks and Power:\n");
1510         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
1511                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
1512         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
1513                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
1514         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
1515                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
1516         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
1517                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
1518         size = sizeof(query);
1519         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size)) {
1520                 seq_printf(m, "\t%u.%u W (VDDC)\n", query.vddc_power >> 8,
1521                                 query.vddc_power & 0xff);
1522                 seq_printf(m, "\t%u.%u W (VDDCI)\n", query.vddci_power >> 8,
1523                                 query.vddci_power & 0xff);
1524                 seq_printf(m, "\t%u.%u W (max GPU)\n", query.max_gpu_power >> 8,
1525                                 query.max_gpu_power & 0xff);
1526                 seq_printf(m, "\t%u.%u W (average GPU)\n", query.average_gpu_power >> 8,
1527                                 query.average_gpu_power & 0xff);
1528         }
1529         size = sizeof(value);
1530         seq_printf(m, "\n");
1531
1532         /* GPU Temp */
1533         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
1534                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
1535
1536         /* GPU Load */
1537         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
1538                 seq_printf(m, "GPU Load: %u %%\n", value);
1539         seq_printf(m, "\n");
1540
1541         /* UVD clocks */
1542         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
1543                 if (!value) {
1544                         seq_printf(m, "UVD: Disabled\n");
1545                 } else {
1546                         seq_printf(m, "UVD: Enabled\n");
1547                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
1548                                 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
1549                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
1550                                 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
1551                 }
1552         }
1553         seq_printf(m, "\n");
1554
1555         /* VCE clocks */
1556         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
1557                 if (!value) {
1558                         seq_printf(m, "VCE: Disabled\n");
1559                 } else {
1560                         seq_printf(m, "VCE: Enabled\n");
1561                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
1562                                 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
1563                 }
1564         }
1565
1566         return 0;
1567 }
1568
1569 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
1570 {
1571         int i;
1572
1573         for (i = 0; clocks[i].flag; i++)
1574                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
1575                            (flags & clocks[i].flag) ? "On" : "Off");
1576 }
1577
1578 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
1579 {
1580         struct drm_info_node *node = (struct drm_info_node *) m->private;
1581         struct drm_device *dev = node->minor->dev;
1582         struct amdgpu_device *adev = dev->dev_private;
1583         struct drm_device *ddev = adev->ddev;
1584         u32 flags = 0;
1585
1586         amdgpu_get_clockgating_state(adev, &flags);
1587         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
1588         amdgpu_parse_cg_state(m, flags);
1589         seq_printf(m, "\n");
1590
1591         if (!adev->pm.dpm_enabled) {
1592                 seq_printf(m, "dpm not enabled\n");
1593                 return 0;
1594         }
1595         if  ((adev->flags & AMD_IS_PX) &&
1596              (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
1597                 seq_printf(m, "PX asic powered off\n");
1598         } else if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
1599                 mutex_lock(&adev->pm.mutex);
1600                 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
1601                         adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
1602                 else
1603                         seq_printf(m, "Debugfs support not implemented for this asic\n");
1604                 mutex_unlock(&adev->pm.mutex);
1605         } else {
1606                 return amdgpu_debugfs_pm_info_pp(m, adev);
1607         }
1608
1609         return 0;
1610 }
1611
1612 static const struct drm_info_list amdgpu_pm_info_list[] = {
1613         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
1614 };
1615 #endif
1616
1617 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
1618 {
1619 #if defined(CONFIG_DEBUG_FS)
1620         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
1621 #else
1622         return 0;
1623 #endif
1624 }