drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef __AMDGPU_IH_H__
  25 #define __AMDGPU_IH_H__
  26
  27 #include <linux/chash.h>
  28
  29 struct amdgpu_device;
  30  /*
  31   * vega10+ IH clients
  32  */
  33 enum amdgpu_ih_clientid
  34 {
  35     AMDGPU_IH_CLIENTID_IH           = 0x00,
  36     AMDGPU_IH_CLIENTID_ACP          = 0x01,
  37     AMDGPU_IH_CLIENTID_ATHUB        = 0x02,
  38     AMDGPU_IH_CLIENTID_BIF          = 0x03,
  39     AMDGPU_IH_CLIENTID_DCE          = 0x04,
  40     AMDGPU_IH_CLIENTID_ISP          = 0x05,
  41     AMDGPU_IH_CLIENTID_PCIE0        = 0x06,
  42     AMDGPU_IH_CLIENTID_RLC          = 0x07,
  43     AMDGPU_IH_CLIENTID_SDMA0        = 0x08,
  44     AMDGPU_IH_CLIENTID_SDMA1        = 0x09,
  45     AMDGPU_IH_CLIENTID_SE0SH        = 0x0a,
  46     AMDGPU_IH_CLIENTID_SE1SH        = 0x0b,
  47     AMDGPU_IH_CLIENTID_SE2SH        = 0x0c,
  48     AMDGPU_IH_CLIENTID_SE3SH        = 0x0d,
  49     AMDGPU_IH_CLIENTID_SYSHUB       = 0x0e,
  50     AMDGPU_IH_CLIENTID_THM          = 0x0f,
  51     AMDGPU_IH_CLIENTID_UVD          = 0x10,
  52     AMDGPU_IH_CLIENTID_VCE0         = 0x11,
  53     AMDGPU_IH_CLIENTID_VMC          = 0x12,
  54     AMDGPU_IH_CLIENTID_XDMA         = 0x13,
  55     AMDGPU_IH_CLIENTID_GRBM_CP      = 0x14,
  56     AMDGPU_IH_CLIENTID_ATS          = 0x15,
  57     AMDGPU_IH_CLIENTID_ROM_SMUIO    = 0x16,
  58     AMDGPU_IH_CLIENTID_DF           = 0x17,
  59     AMDGPU_IH_CLIENTID_VCE1         = 0x18,
  60     AMDGPU_IH_CLIENTID_PWR          = 0x19,
  61     AMDGPU_IH_CLIENTID_UTCL2        = 0x1b,
  62     AMDGPU_IH_CLIENTID_EA           = 0x1c,
  63     AMDGPU_IH_CLIENTID_UTCL2LOG     = 0x1d,
  64     AMDGPU_IH_CLIENTID_MP0          = 0x1e,
  65     AMDGPU_IH_CLIENTID_MP1          = 0x1f,
  66
  67     AMDGPU_IH_CLIENTID_MAX,
  68
  69     AMDGPU_IH_CLIENTID_VCN          = AMDGPU_IH_CLIENTID_UVD
  70 };
  71
  72 #define AMDGPU_IH_CLIENTID_LEGACY 0
  73
  74 #define AMDGPU_PAGEFAULT_HASH_BITS 8
  75 struct amdgpu_retryfault_hashtable {
  76         DECLARE_CHASH_TABLE(hash, AMDGPU_PAGEFAULT_HASH_BITS, 8, 0);
  77         spinlock_t      lock;
  78         int             count;
  79 };
  80
  81 /*
  82  * R6xx+ IH ring
  83  */
  84 struct amdgpu_ih_ring {
  85         struct amdgpu_bo        *ring_obj;
  86         volatile uint32_t       *ring;
  87         unsigned                rptr;
  88         unsigned                ring_size;
  89         uint64_t                gpu_addr;
  90         uint32_t                ptr_mask;
  91         atomic_t                lock;
  92         bool                    enabled;
  93         unsigned                wptr_offs;
  94         unsigned                rptr_offs;
  95         u32                     doorbell_index;
  96         bool                    use_doorbell;
  97         bool                    use_bus_addr;
  98         dma_addr_t              rb_dma_addr; /* only used when use_bus_addr = true */
  99         struct amdgpu_retryfault_hashtable *faults;
 100 };
 101
 102 #define AMDGPU_IH_SRC_DATA_MAX_SIZE_DW 4
 103
 104 struct amdgpu_iv_entry {
 105         unsigned client_id;
 106         unsigned src_id;
 107         unsigned ring_id;
 108         unsigned vm_id;
 109         unsigned vm_id_src;
 110         uint64_t timestamp;
 111         unsigned timestamp_src;
 112         unsigned pas_id;
 113         unsigned pasid_src;
 114         unsigned src_data[AMDGPU_IH_SRC_DATA_MAX_SIZE_DW];
 115         const uint32_t *iv_entry;
 116 };
 117
 118 int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size,
 119                         bool use_bus_addr);
 120 void amdgpu_ih_ring_fini(struct amdgpu_device *adev);
 121 int amdgpu_ih_process(struct amdgpu_device *adev);
 122 int amdgpu_ih_add_fault(struct amdgpu_device *adev, u64 key);
 123 void amdgpu_ih_clear_fault(struct amdgpu_device *adev, u64 key);
 124
 125 #endif