drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/amdgpu_drm.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_i2c.h"
  30 #include "atom.h"
  31 #include "amdgpu_connectors.h"
  32 #include <asm/div64.h>
  33
  34 #include <linux/pm_runtime.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_edid.h>
  37
  38 static void amdgpu_flip_callback(struct dma_fence *f, struct dma_fence_cb *cb)
  39 {
  40         struct amdgpu_flip_work *work =
  41                 container_of(cb, struct amdgpu_flip_work, cb);
  42
  43         dma_fence_put(f);
  44         schedule_work(&work->flip_work.work);
  45 }
  46
  47 static bool amdgpu_flip_handle_fence(struct amdgpu_flip_work *work,
  48                                      struct dma_fence **f)
  49 {
  50         struct dma_fence *fence= *f;
  51
  52         if (fence == NULL)
  53                 return false;
  54
  55         *f = NULL;
  56
  57         if (!dma_fence_add_callback(fence, &work->cb, amdgpu_flip_callback))
  58                 return true;
  59
  60         dma_fence_put(fence);
  61         return false;
  62 }
  63
  64 static void amdgpu_flip_work_func(struct work_struct *__work)
  65 {
  66         struct delayed_work *delayed_work =
  67                 container_of(__work, struct delayed_work, work);
  68         struct amdgpu_flip_work *work =
  69                 container_of(delayed_work, struct amdgpu_flip_work, flip_work);
  70         struct amdgpu_device *adev = work->adev;
  71         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id];
  72
  73         struct drm_crtc *crtc = &amdgpu_crtc->base;
  74         unsigned long flags;
  75         unsigned i;
  76         int vpos, hpos;
  77
  78         if (amdgpu_flip_handle_fence(work, &work->excl))
  79                 return;
  80
  81         for (i = 0; i < work->shared_count; ++i)
  82                 if (amdgpu_flip_handle_fence(work, &work->shared[i]))
  83                         return;
  84
  85         /* Wait until we're out of the vertical blank period before the one
  86          * targeted by the flip
  87          */
  88         if (amdgpu_crtc->enabled &&
  89             (amdgpu_get_crtc_scanoutpos(adev->ddev, work->crtc_id, 0,
  90                                         &vpos, &hpos, NULL, NULL,
  91                                         &crtc->hwmode)
  92              & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
  93             (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
  94             (int)(work->target_vblank -
  95                   amdgpu_get_vblank_counter_kms(adev->ddev, amdgpu_crtc->crtc_id)) > 0) {
  96                 schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000));
  97                 return;
  98         }
  99
 100         /* We borrow the event spin lock for protecting flip_status */
 101         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 102
 103         /* Do the flip (mmio) */
 104         adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async);
 105
 106         /* Set the flip status */
 107         amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
 108         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 109
 110
 111         DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n",
 112                                          amdgpu_crtc->crtc_id, amdgpu_crtc, work);
 113
 114 }
 115
 116 /*
 117  * Handle unpin events outside the interrupt handler proper.
 118  */
 119 static void amdgpu_unpin_work_func(struct work_struct *__work)
 120 {
 121         struct amdgpu_flip_work *work =
 122                 container_of(__work, struct amdgpu_flip_work, unpin_work);
 123         int r;
 124
 125         /* unpin of the old buffer */
 126         r = amdgpu_bo_reserve(work->old_abo, true);
 127         if (likely(r == 0)) {
 128                 r = amdgpu_bo_unpin(work->old_abo);
 129                 if (unlikely(r != 0)) {
 130                         DRM_ERROR("failed to unpin buffer after flip\n");
 131                 }
 132                 amdgpu_bo_unreserve(work->old_abo);
 133         } else
 134                 DRM_ERROR("failed to reserve buffer after flip\n");
 135
 136         amdgpu_bo_unref(&work->old_abo);
 137         kfree(work->shared);
 138         kfree(work);
 139 }
 140
 141 int amdgpu_crtc_page_flip_target(struct drm_crtc *crtc,
 142                                  struct drm_framebuffer *fb,
 143                                  struct drm_pending_vblank_event *event,
 144                                  uint32_t page_flip_flags, uint32_t target,
 145                                  struct drm_modeset_acquire_ctx *ctx)
 146 {
 147         struct drm_device *dev = crtc->dev;
 148         struct amdgpu_device *adev = dev->dev_private;
 149         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 150         struct amdgpu_framebuffer *old_amdgpu_fb;
 151         struct amdgpu_framebuffer *new_amdgpu_fb;
 152         struct drm_gem_object *obj;
 153         struct amdgpu_flip_work *work;
 154         struct amdgpu_bo *new_abo;
 155         unsigned long flags;
 156         u64 tiling_flags;
 157         u64 base;
 158         int i, r;
 159
 160         work = kzalloc(sizeof *work, GFP_KERNEL);
 161         if (work == NULL)
 162                 return -ENOMEM;
 163
 164         INIT_DELAYED_WORK(&work->flip_work, amdgpu_flip_work_func);
 165         INIT_WORK(&work->unpin_work, amdgpu_unpin_work_func);
 166
 167         work->event = event;
 168         work->adev = adev;
 169         work->crtc_id = amdgpu_crtc->crtc_id;
 170         work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
 171
 172         /* schedule unpin of the old buffer */
 173         old_amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
 174         obj = old_amdgpu_fb->obj;
 175
 176         /* take a reference to the old object */
 177         work->old_abo = gem_to_amdgpu_bo(obj);
 178         amdgpu_bo_ref(work->old_abo);
 179
 180         new_amdgpu_fb = to_amdgpu_framebuffer(fb);
 181         obj = new_amdgpu_fb->obj;
 182         new_abo = gem_to_amdgpu_bo(obj);
 183
 184         /* pin the new buffer */
 185         r = amdgpu_bo_reserve(new_abo, false);
 186         if (unlikely(r != 0)) {
 187                 DRM_ERROR("failed to reserve new abo buffer before flip\n");
 188                 goto cleanup;
 189         }
 190
 191         r = amdgpu_bo_pin(new_abo, AMDGPU_GEM_DOMAIN_VRAM, &base);
 192         if (unlikely(r != 0)) {
 193                 DRM_ERROR("failed to pin new abo buffer before flip\n");
 194                 goto unreserve;
 195         }
 196
 197         r = reservation_object_get_fences_rcu(new_abo->tbo.resv, &work->excl,
 198                                               &work->shared_count,
 199                                               &work->shared);
 200         if (unlikely(r != 0)) {
 201                 DRM_ERROR("failed to get fences for buffer\n");
 202                 goto unpin;
 203         }
 204
 205         amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags);
 206         amdgpu_bo_unreserve(new_abo);
 207
 208         work->base = base;
 209         work->target_vblank = target - drm_crtc_vblank_count(crtc) +
 210                 amdgpu_get_vblank_counter_kms(dev, work->crtc_id);
 211
 212         /* we borrow the event spin lock for protecting flip_wrok */
 213         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 214         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) {
 215                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 216                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 217                 r = -EBUSY;
 218                 goto pflip_cleanup;
 219         }
 220
 221         amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING;
 222         amdgpu_crtc->pflip_works = work;
 223
 224
 225         DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n",
 226                                          amdgpu_crtc->crtc_id, amdgpu_crtc, work);
 227         /* update crtc fb */
 228         crtc->primary->fb = fb;
 229         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 230         amdgpu_flip_work_func(&work->flip_work.work);
 231         return 0;
 232
 233 pflip_cleanup:
 234         if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) {
 235                 DRM_ERROR("failed to reserve new abo in error path\n");
 236                 goto cleanup;
 237         }
 238 unpin:
 239         if (unlikely(amdgpu_bo_unpin(new_abo) != 0)) {
 240                 DRM_ERROR("failed to unpin new abo in error path\n");
 241         }
 242 unreserve:
 243         amdgpu_bo_unreserve(new_abo);
 244
 245 cleanup:
 246         amdgpu_bo_unref(&work->old_abo);
 247         dma_fence_put(work->excl);
 248         for (i = 0; i < work->shared_count; ++i)
 249                 dma_fence_put(work->shared[i]);
 250         kfree(work->shared);
 251         kfree(work);
 252
 253         return r;
 254 }
 255
 256 int amdgpu_crtc_set_config(struct drm_mode_set *set,
 257                            struct drm_modeset_acquire_ctx *ctx)
 258 {
 259         struct drm_device *dev;
 260         struct amdgpu_device *adev;
 261         struct drm_crtc *crtc;
 262         bool active = false;
 263         int ret;
 264
 265         if (!set || !set->crtc)
 266                 return -EINVAL;
 267
 268         dev = set->crtc->dev;
 269
 270         ret = pm_runtime_get_sync(dev->dev);
 271         if (ret < 0)
 272                 return ret;
 273
 274         ret = drm_crtc_helper_set_config(set, ctx);
 275
 276         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 277                 if (crtc->enabled)
 278                         active = true;
 279
 280         pm_runtime_mark_last_busy(dev->dev);
 281
 282         adev = dev->dev_private;
 283         /* if we have active crtcs and we don't have a power ref,
 284            take the current one */
 285         if (active && !adev->have_disp_power_ref) {
 286                 adev->have_disp_power_ref = true;
 287                 return ret;
 288         }
 289         /* if we have no active crtcs, then drop the power ref
 290            we got before */
 291         if (!active && adev->have_disp_power_ref) {
 292                 pm_runtime_put_autosuspend(dev->dev);
 293                 adev->have_disp_power_ref = false;
 294         }
 295
 296         /* drop the power reference we got coming in here */
 297         pm_runtime_put_autosuspend(dev->dev);
 298         return ret;
 299 }
 300
 301 static const char *encoder_names[41] = {
 302         "NONE",
 303         "INTERNAL_LVDS",
 304         "INTERNAL_TMDS1",
 305         "INTERNAL_TMDS2",
 306         "INTERNAL_DAC1",
 307         "INTERNAL_DAC2",
 308         "INTERNAL_SDVOA",
 309         "INTERNAL_SDVOB",
 310         "SI170B",
 311         "CH7303",
 312         "CH7301",
 313         "INTERNAL_DVO1",
 314         "EXTERNAL_SDVOA",
 315         "EXTERNAL_SDVOB",
 316         "TITFP513",
 317         "INTERNAL_LVTM1",
 318         "VT1623",
 319         "HDMI_SI1930",
 320         "HDMI_INTERNAL",
 321         "INTERNAL_KLDSCP_TMDS1",
 322         "INTERNAL_KLDSCP_DVO1",
 323         "INTERNAL_KLDSCP_DAC1",
 324         "INTERNAL_KLDSCP_DAC2",
 325         "SI178",
 326         "MVPU_FPGA",
 327         "INTERNAL_DDI",
 328         "VT1625",
 329         "HDMI_SI1932",
 330         "DP_AN9801",
 331         "DP_DP501",
 332         "INTERNAL_UNIPHY",
 333         "INTERNAL_KLDSCP_LVTMA",
 334         "INTERNAL_UNIPHY1",
 335         "INTERNAL_UNIPHY2",
 336         "NUTMEG",
 337         "TRAVIS",
 338         "INTERNAL_VCE",
 339         "INTERNAL_UNIPHY3",
 340         "HDMI_ANX9805",
 341         "INTERNAL_AMCLK",
 342         "VIRTUAL",
 343 };
 344
 345 static const char *hpd_names[6] = {
 346         "HPD1",
 347         "HPD2",
 348         "HPD3",
 349         "HPD4",
 350         "HPD5",
 351         "HPD6",
 352 };
 353
 354 void amdgpu_print_display_setup(struct drm_device *dev)
 355 {
 356         struct drm_connector *connector;
 357         struct amdgpu_connector *amdgpu_connector;
 358         struct drm_encoder *encoder;
 359         struct amdgpu_encoder *amdgpu_encoder;
 360         uint32_t devices;
 361         int i = 0;
 362
 363         DRM_INFO("AMDGPU Display Connectors\n");
 364         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 365                 amdgpu_connector = to_amdgpu_connector(connector);
 366                 DRM_INFO("Connector %d:\n", i);
 367                 DRM_INFO("  %s\n", connector->name);
 368                 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE)
 369                         DRM_INFO("  %s\n", hpd_names[amdgpu_connector->hpd.hpd]);
 370                 if (amdgpu_connector->ddc_bus) {
 371                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 372                                  amdgpu_connector->ddc_bus->rec.mask_clk_reg,
 373                                  amdgpu_connector->ddc_bus->rec.mask_data_reg,
 374                                  amdgpu_connector->ddc_bus->rec.a_clk_reg,
 375                                  amdgpu_connector->ddc_bus->rec.a_data_reg,
 376                                  amdgpu_connector->ddc_bus->rec.en_clk_reg,
 377                                  amdgpu_connector->ddc_bus->rec.en_data_reg,
 378                                  amdgpu_connector->ddc_bus->rec.y_clk_reg,
 379                                  amdgpu_connector->ddc_bus->rec.y_data_reg);
 380                         if (amdgpu_connector->router.ddc_valid)
 381                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 382                                          amdgpu_connector->router.ddc_mux_control_pin,
 383                                          amdgpu_connector->router.ddc_mux_state);
 384                         if (amdgpu_connector->router.cd_valid)
 385                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 386                                          amdgpu_connector->router.cd_mux_control_pin,
 387                                          amdgpu_connector->router.cd_mux_state);
 388                 } else {
 389                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 390                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 391                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 392                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 393                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 394                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 395                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to [email protected]\n");
 396                 }
 397                 DRM_INFO("  Encoders:\n");
 398                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 399                         amdgpu_encoder = to_amdgpu_encoder(encoder);
 400                         devices = amdgpu_encoder->devices & amdgpu_connector->devices;
 401                         if (devices) {
 402                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 403                                         DRM_INFO("    CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 404                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 405                                         DRM_INFO("    CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 406                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 407                                         DRM_INFO("    LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 408                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 409                                         DRM_INFO("    DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 410                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 411                                         DRM_INFO("    DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 412                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 413                                         DRM_INFO("    DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 414                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 415                                         DRM_INFO("    DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 416                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 417                                         DRM_INFO("    DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 418                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 419                                         DRM_INFO("    DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 420                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 421                                         DRM_INFO("    TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 422                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 423                                         DRM_INFO("    CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 424                         }
 425                 }
 426                 i++;
 427         }
 428 }
 429
 430 /**
 431  * amdgpu_ddc_probe
 432  *
 433  */
 434 bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector,
 435                        bool use_aux)
 436 {
 437         u8 out = 0x0;
 438         u8 buf[8];
 439         int ret;
 440         struct i2c_msg msgs[] = {
 441                 {
 442                         .addr = DDC_ADDR,
 443                         .flags = 0,
 444                         .len = 1,
 445                         .buf = &out,
 446                 },
 447                 {
 448                         .addr = DDC_ADDR,
 449                         .flags = I2C_M_RD,
 450                         .len = 8,
 451                         .buf = buf,
 452                 }
 453         };
 454
 455         /* on hw with routers, select right port */
 456         if (amdgpu_connector->router.ddc_valid)
 457                 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
 458
 459         if (use_aux) {
 460                 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2);
 461         } else {
 462                 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2);
 463         }
 464
 465         if (ret != 2)
 466                 /* Couldn't find an accessible DDC on this connector */
 467                 return false;
 468         /* Probe also for valid EDID header
 469          * EDID header starts with:
 470          * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
 471          * Only the first 6 bytes must be valid as
 472          * drm_edid_block_valid() can fix the last 2 bytes */
 473         if (drm_edid_header_is_valid(buf) < 6) {
 474                 /* Couldn't find an accessible EDID on this
 475                  * connector */
 476                 return false;
 477         }
 478         return true;
 479 }
 480
 481 static void amdgpu_user_framebuffer_destroy(struct drm_framebuffer *fb)
 482 {
 483         struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb);
 484
 485         drm_gem_object_put_unlocked(amdgpu_fb->obj);
 486         drm_framebuffer_cleanup(fb);
 487         kfree(amdgpu_fb);
 488 }
 489
 490 static int amdgpu_user_framebuffer_create_handle(struct drm_framebuffer *fb,
 491                                                   struct drm_file *file_priv,
 492                                                   unsigned int *handle)
 493 {
 494         struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb);
 495
 496         return drm_gem_handle_create(file_priv, amdgpu_fb->obj, handle);
 497 }
 498
 499 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
 500         .destroy = amdgpu_user_framebuffer_destroy,
 501         .create_handle = amdgpu_user_framebuffer_create_handle,
 502 };
 503
 504 int
 505 amdgpu_framebuffer_init(struct drm_device *dev,
 506                         struct amdgpu_framebuffer *rfb,
 507                         const struct drm_mode_fb_cmd2 *mode_cmd,
 508                         struct drm_gem_object *obj)
 509 {
 510         int ret;
 511         rfb->obj = obj;
 512         drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd);
 513         ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
 514         if (ret) {
 515                 rfb->obj = NULL;
 516                 return ret;
 517         }
 518         return 0;
 519 }
 520
 521 struct drm_framebuffer *
 522 amdgpu_user_framebuffer_create(struct drm_device *dev,
 523                                struct drm_file *file_priv,
 524                                const struct drm_mode_fb_cmd2 *mode_cmd)
 525 {
 526         struct drm_gem_object *obj;
 527         struct amdgpu_framebuffer *amdgpu_fb;
 528         int ret;
 529
 530         obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
 531         if (obj ==  NULL) {
 532                 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
 533                         "can't create framebuffer\n", mode_cmd->handles[0]);
 534                 return ERR_PTR(-ENOENT);
 535         }
 536
 537         /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
 538         if (obj->import_attach) {
 539                 DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n");
 540                 return ERR_PTR(-EINVAL);
 541         }
 542
 543         amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL);
 544         if (amdgpu_fb == NULL) {
 545                 drm_gem_object_put_unlocked(obj);
 546                 return ERR_PTR(-ENOMEM);
 547         }
 548
 549         ret = amdgpu_framebuffer_init(dev, amdgpu_fb, mode_cmd, obj);
 550         if (ret) {
 551                 kfree(amdgpu_fb);
 552                 drm_gem_object_put_unlocked(obj);
 553                 return ERR_PTR(ret);
 554         }
 555
 556         return &amdgpu_fb->base;
 557 }
 558
 559 void amdgpu_output_poll_changed(struct drm_device *dev)
 560 {
 561         struct amdgpu_device *adev = dev->dev_private;
 562         amdgpu_fb_output_poll_changed(adev);
 563 }
 564
 565 const struct drm_mode_config_funcs amdgpu_mode_funcs = {
 566         .fb_create = amdgpu_user_framebuffer_create,
 567         .output_poll_changed = amdgpu_output_poll_changed
 568 };
 569
 570 static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] =
 571 {       { UNDERSCAN_OFF, "off" },
 572         { UNDERSCAN_ON, "on" },
 573         { UNDERSCAN_AUTO, "auto" },
 574 };
 575
 576 static const struct drm_prop_enum_list amdgpu_audio_enum_list[] =
 577 {       { AMDGPU_AUDIO_DISABLE, "off" },
 578         { AMDGPU_AUDIO_ENABLE, "on" },
 579         { AMDGPU_AUDIO_AUTO, "auto" },
 580 };
 581
 582 /* XXX support different dither options? spatial, temporal, both, etc. */
 583 static const struct drm_prop_enum_list amdgpu_dither_enum_list[] =
 584 {       { AMDGPU_FMT_DITHER_DISABLE, "off" },
 585         { AMDGPU_FMT_DITHER_ENABLE, "on" },
 586 };
 587
 588 int amdgpu_modeset_create_props(struct amdgpu_device *adev)
 589 {
 590         int sz;
 591
 592         adev->mode_info.coherent_mode_property =
 593                 drm_property_create_range(adev->ddev, 0 , "coherent", 0, 1);
 594         if (!adev->mode_info.coherent_mode_property)
 595                 return -ENOMEM;
 596
 597         adev->mode_info.load_detect_property =
 598                 drm_property_create_range(adev->ddev, 0, "load detection", 0, 1);
 599         if (!adev->mode_info.load_detect_property)
 600                 return -ENOMEM;
 601
 602         drm_mode_create_scaling_mode_property(adev->ddev);
 603
 604         sz = ARRAY_SIZE(amdgpu_underscan_enum_list);
 605         adev->mode_info.underscan_property =
 606                 drm_property_create_enum(adev->ddev, 0,
 607                                     "underscan",
 608                                     amdgpu_underscan_enum_list, sz);
 609
 610         adev->mode_info.underscan_hborder_property =
 611                 drm_property_create_range(adev->ddev, 0,
 612                                         "underscan hborder", 0, 128);
 613         if (!adev->mode_info.underscan_hborder_property)
 614                 return -ENOMEM;
 615
 616         adev->mode_info.underscan_vborder_property =
 617                 drm_property_create_range(adev->ddev, 0,
 618                                         "underscan vborder", 0, 128);
 619         if (!adev->mode_info.underscan_vborder_property)
 620                 return -ENOMEM;
 621
 622         sz = ARRAY_SIZE(amdgpu_audio_enum_list);
 623         adev->mode_info.audio_property =
 624                 drm_property_create_enum(adev->ddev, 0,
 625                                          "audio",
 626                                          amdgpu_audio_enum_list, sz);
 627
 628         sz = ARRAY_SIZE(amdgpu_dither_enum_list);
 629         adev->mode_info.dither_property =
 630                 drm_property_create_enum(adev->ddev, 0,
 631                                          "dither",
 632                                          amdgpu_dither_enum_list, sz);
 633
 634         return 0;
 635 }
 636
 637 void amdgpu_update_display_priority(struct amdgpu_device *adev)
 638 {
 639         /* adjustment options for the display watermarks */
 640         if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2))
 641                 adev->mode_info.disp_priority = 0;
 642         else
 643                 adev->mode_info.disp_priority = amdgpu_disp_priority;
 644
 645 }
 646
 647 static bool is_hdtv_mode(const struct drm_display_mode *mode)
 648 {
 649         /* try and guess if this is a tv or a monitor */
 650         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
 651             (mode->vdisplay == 576) || /* 576p */
 652             (mode->vdisplay == 720) || /* 720p */
 653             (mode->vdisplay == 1080)) /* 1080p */
 654                 return true;
 655         else
 656                 return false;
 657 }
 658
 659 bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
 660                                     const struct drm_display_mode *mode,
 661                                     struct drm_display_mode *adjusted_mode)
 662 {
 663         struct drm_device *dev = crtc->dev;
 664         struct drm_encoder *encoder;
 665         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 666         struct amdgpu_encoder *amdgpu_encoder;
 667         struct drm_connector *connector;
 668         struct amdgpu_connector *amdgpu_connector;
 669         u32 src_v = 1, dst_v = 1;
 670         u32 src_h = 1, dst_h = 1;
 671
 672         amdgpu_crtc->h_border = 0;
 673         amdgpu_crtc->v_border = 0;
 674
 675         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 676                 if (encoder->crtc != crtc)
 677                         continue;
 678                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 679                 connector = amdgpu_get_connector_for_encoder(encoder);
 680                 amdgpu_connector = to_amdgpu_connector(connector);
 681
 682                 /* set scaling */
 683                 if (amdgpu_encoder->rmx_type == RMX_OFF)
 684                         amdgpu_crtc->rmx_type = RMX_OFF;
 685                 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay ||
 686                          mode->vdisplay < amdgpu_encoder->native_mode.vdisplay)
 687                         amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type;
 688                 else
 689                         amdgpu_crtc->rmx_type = RMX_OFF;
 690                 /* copy native mode */
 691                 memcpy(&amdgpu_crtc->native_mode,
 692                        &amdgpu_encoder->native_mode,
 693                        sizeof(struct drm_display_mode));
 694                 src_v = crtc->mode.vdisplay;
 695                 dst_v = amdgpu_crtc->native_mode.vdisplay;
 696                 src_h = crtc->mode.hdisplay;
 697                 dst_h = amdgpu_crtc->native_mode.hdisplay;
 698
 699                 /* fix up for overscan on hdmi */
 700                 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
 701                     ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) ||
 702                      ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) &&
 703                       drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) &&
 704                       is_hdtv_mode(mode)))) {
 705                         if (amdgpu_encoder->underscan_hborder != 0)
 706                                 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder;
 707                         else
 708                                 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16;
 709                         if (amdgpu_encoder->underscan_vborder != 0)
 710                                 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder;
 711                         else
 712                                 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16;
 713                         amdgpu_crtc->rmx_type = RMX_FULL;
 714                         src_v = crtc->mode.vdisplay;
 715                         dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2);
 716                         src_h = crtc->mode.hdisplay;
 717                         dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2);
 718                 }
 719         }
 720         if (amdgpu_crtc->rmx_type != RMX_OFF) {
 721                 fixed20_12 a, b;
 722                 a.full = dfixed_const(src_v);
 723                 b.full = dfixed_const(dst_v);
 724                 amdgpu_crtc->vsc.full = dfixed_div(a, b);
 725                 a.full = dfixed_const(src_h);
 726                 b.full = dfixed_const(dst_h);
 727                 amdgpu_crtc->hsc.full = dfixed_div(a, b);
 728         } else {
 729                 amdgpu_crtc->vsc.full = dfixed_const(1);
 730                 amdgpu_crtc->hsc.full = dfixed_const(1);
 731         }
 732         return true;
 733 }
 734
 735 /*
 736  * Retrieve current video scanout position of crtc on a given gpu, and
 737  * an optional accurate timestamp of when query happened.
 738  *
 739  * \param dev Device to query.
 740  * \param pipe Crtc to query.
 741  * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
 742  *              For driver internal use only also supports these flags:
 743  *
 744  *              USE_REAL_VBLANKSTART to use the real start of vblank instead
 745  *              of a fudged earlier start of vblank.
 746  *
 747  *              GET_DISTANCE_TO_VBLANKSTART to return distance to the
 748  *              fudged earlier start of vblank in *vpos and the distance
 749  *              to true start of vblank in *hpos.
 750  *
 751  * \param *vpos Location where vertical scanout position should be stored.
 752  * \param *hpos Location where horizontal scanout position should go.
 753  * \param *stime Target location for timestamp taken immediately before
 754  *               scanout position query. Can be NULL to skip timestamp.
 755  * \param *etime Target location for timestamp taken immediately after
 756  *               scanout position query. Can be NULL to skip timestamp.
 757  *
 758  * Returns vpos as a positive number while in active scanout area.
 759  * Returns vpos as a negative number inside vblank, counting the number
 760  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
 761  * until start of active scanout / end of vblank."
 762  *
 763  * \return Flags, or'ed together as follows:
 764  *
 765  * DRM_SCANOUTPOS_VALID = Query successful.
 766  * DRM_SCANOUTPOS_INVBL = Inside vblank.
 767  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
 768  * this flag means that returned position may be offset by a constant but
 769  * unknown small number of scanlines wrt. real scanout position.
 770  *
 771  */
 772 int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
 773                                unsigned int flags, int *vpos, int *hpos,
 774                                ktime_t *stime, ktime_t *etime,
 775                                const struct drm_display_mode *mode)
 776 {
 777         u32 vbl = 0, position = 0;
 778         int vbl_start, vbl_end, vtotal, ret = 0;
 779         bool in_vbl = true;
 780
 781         struct amdgpu_device *adev = dev->dev_private;
 782
 783         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 784
 785         /* Get optional system timestamp before query. */
 786         if (stime)
 787                 *stime = ktime_get();
 788
 789         if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0)
 790                 ret |= DRM_SCANOUTPOS_VALID;
 791
 792         /* Get optional system timestamp after query. */
 793         if (etime)
 794                 *etime = ktime_get();
 795
 796         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 797
 798         /* Decode into vertical and horizontal scanout position. */
 799         *vpos = position & 0x1fff;
 800         *hpos = (position >> 16) & 0x1fff;
 801
 802         /* Valid vblank area boundaries from gpu retrieved? */
 803         if (vbl > 0) {
 804                 /* Yes: Decode. */
 805                 ret |= DRM_SCANOUTPOS_ACCURATE;
 806                 vbl_start = vbl & 0x1fff;
 807                 vbl_end = (vbl >> 16) & 0x1fff;
 808         }
 809         else {
 810                 /* No: Fake something reasonable which gives at least ok results. */
 811                 vbl_start = mode->crtc_vdisplay;
 812                 vbl_end = 0;
 813         }
 814
 815         /* Called from driver internal vblank counter query code? */
 816         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
 817             /* Caller wants distance from real vbl_start in *hpos */
 818             *hpos = *vpos - vbl_start;
 819         }
 820
 821         /* Fudge vblank to start a few scanlines earlier to handle the
 822          * problem that vblank irqs fire a few scanlines before start
 823          * of vblank. Some driver internal callers need the true vblank
 824          * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
 825          *
 826          * The cause of the "early" vblank irq is that the irq is triggered
 827          * by the line buffer logic when the line buffer read position enters
 828          * the vblank, whereas our crtc scanout position naturally lags the
 829          * line buffer read position.
 830          */
 831         if (!(flags & USE_REAL_VBLANKSTART))
 832                 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
 833
 834         /* Test scanout position against vblank region. */
 835         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
 836                 in_vbl = false;
 837
 838         /* In vblank? */
 839         if (in_vbl)
 840             ret |= DRM_SCANOUTPOS_IN_VBLANK;
 841
 842         /* Called from driver internal vblank counter query code? */
 843         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
 844                 /* Caller wants distance from fudged earlier vbl_start */
 845                 *vpos -= vbl_start;
 846                 return ret;
 847         }
 848
 849         /* Check if inside vblank area and apply corrective offsets:
 850          * vpos will then be >=0 in video scanout area, but negative
 851          * within vblank area, counting down the number of lines until
 852          * start of scanout.
 853          */
 854
 855         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
 856         if (in_vbl && (*vpos >= vbl_start)) {
 857                 vtotal = mode->crtc_vtotal;
 858                 *vpos = *vpos - vtotal;
 859         }
 860
 861         /* Correct for shifted end of vbl at vbl_end. */
 862         *vpos = *vpos - vbl_end;
 863
 864         return ret;
 865 }
 866
 867 int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc)
 868 {
 869         if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
 870                 return AMDGPU_CRTC_IRQ_NONE;
 871
 872         switch (crtc) {
 873         case 0:
 874                 return AMDGPU_CRTC_IRQ_VBLANK1;
 875         case 1:
 876                 return AMDGPU_CRTC_IRQ_VBLANK2;
 877         case 2:
 878                 return AMDGPU_CRTC_IRQ_VBLANK3;
 879         case 3:
 880                 return AMDGPU_CRTC_IRQ_VBLANK4;
 881         case 4:
 882                 return AMDGPU_CRTC_IRQ_VBLANK5;
 883         case 5:
 884                 return AMDGPU_CRTC_IRQ_VBLANK6;
 885         default:
 886                 return AMDGPU_CRTC_IRQ_NONE;
 887         }
 888 }