1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 * Adapted for Power Macintosh by Paul Mackerras.
9 * Low-level exception handlers and MMU support
10 * rewritten by Paul Mackerras.
11 * Copyright (C) 1996 Paul Mackerras.
14 * This file contains the low-level support and setup for the
15 * PowerPC platform, including trap and interrupt dispatch.
16 * (The PPC 8xx embedded CPUs use head_8xx.S instead.)
19 #include <linux/init.h>
23 #include <asm/pgtable.h>
24 #include <asm/cputable.h>
25 #include <asm/cache.h>
26 #include <asm/thread_info.h>
27 #include <asm/ppc_asm.h>
28 #include <asm/asm-offsets.h>
29 #include <asm/ptrace.h>
31 #include <asm/kvm_book3s_asm.h>
32 #include <asm/export.h>
33 #include <asm/feature-fixups.h>
37 /* 601 only have IBAT; cr0.eq is set on 601 when using this macro */
38 #define LOAD_BAT(n, reg, RA, RB) \
39 /* see the comment for clear_bats() -- Cort */ \
41 mtspr SPRN_IBAT##n##U,RA; \
42 mtspr SPRN_DBAT##n##U,RA; \
43 lwz RA,(n*16)+0(reg); \
44 lwz RB,(n*16)+4(reg); \
45 mtspr SPRN_IBAT##n##U,RA; \
46 mtspr SPRN_IBAT##n##L,RB; \
48 lwz RA,(n*16)+8(reg); \
49 lwz RB,(n*16)+12(reg); \
50 mtspr SPRN_DBAT##n##U,RA; \
51 mtspr SPRN_DBAT##n##L,RB; \
55 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
56 .stabs "head_32.S",N_SO,0,0,0f
61 * _start is defined this way because the XCOFF loader in the OpenFirmware
62 * on the powermac expects the entry point to be a procedure descriptor.
66 * These are here for legacy reasons, the kernel used to
67 * need to look like a coff function entry for the pmac
68 * but we're always started by some kind of bootloader now.
71 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
72 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
76 * Enter here with the kernel text, data and bss loaded starting at
77 * 0, running with virtual == physical mapping.
78 * r5 points to the prom entry point (the client interface handler
79 * address). Address translation is turned on, with the prom
80 * managing the hash table. Interrupts are disabled. The stack
81 * pointer (r1) points to just below the end of the half-meg region
82 * from 0x380000 - 0x400000, which is mapped in already.
84 * If we are booted from MacOS via BootX, we enter with the kernel
85 * image loaded somewhere, and the following values in registers:
86 * r3: 'BooX' (0x426f6f58)
87 * r4: virtual address of boot_infos_t
91 * This is jumped to on prep systems right after the kernel is relocated
92 * to its proper place in memory by the boot loader. The expected layout
94 * r3: ptr to residual data
95 * r4: initrd_start or if no initrd then 0
96 * r5: initrd_end - unused if r4 is 0
97 * r6: Start of command line string
98 * r7: End of command line string
100 * This just gets a minimal mmu environment setup so we can call
101 * start_here() to do the real work.
108 * We have to do any OF calls before we map ourselves to KERNELBASE,
109 * because OF may have I/O devices mapped into that area
110 * (particularly on CHRP).
115 #ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
116 /* find out where we are now */
118 0: mflr r8 /* r8 = runtime addr here */
119 addis r8,r8,(_stext - 0b)@ha
120 addi r8,r8,(_stext - 0b)@l /* current runtime base addr */
122 #endif /* CONFIG_PPC_OF_BOOT_TRAMPOLINE */
124 /* We never return. We also hit that trap if trying to boot
125 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */
129 * Check for BootX signature when supporting PowerMac and branch to
130 * appropriate trampoline if it's present
132 #ifdef CONFIG_PPC_PMAC
139 #endif /* CONFIG_PPC_PMAC */
141 1: mr r31,r3 /* save device tree ptr */
145 * early_init() does the early machine identification and does
146 * the necessary low-level setup and clears the BSS
151 /* Switch MMU off, clear BATs and flush TLB. At this point, r3 contains
152 * the physical address we are running at, returned by early_init()
160 bl load_segment_registers
164 #if defined(CONFIG_BOOTX_TEXT)
167 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
170 #ifdef CONFIG_PPC_EARLY_DEBUG_USBGECKO
171 bl setup_usbgecko_bat
175 * Call setup_cpu for CPU 0 and initialize 6xx Idle
179 bl call_setup_cpu /* Call setup_cpu for this CPU */
180 #ifdef CONFIG_PPC_BOOK3S_32
183 #endif /* CONFIG_PPC_BOOK3S_32 */
187 * We need to run with _start at physical address 0.
188 * On CHRP, we are loaded at 0x10000 since OF on CHRP uses
189 * the exception vectors at 0 (and therefore this copy
190 * overwrites OF's exception vectors with our own).
191 * The MMU is off at this point.
195 addis r4,r3,KERNELBASE@h /* current address of _start */
196 lis r5,PHYSICAL_START@h
197 cmplw 0,r4,r5 /* already running at PHYSICAL_START? */
200 * we now have the 1st 16M of ram mapped with the bats.
201 * prep needs the mmu to be turned on here, but pmac already has it on.
202 * this shouldn't bother the pmac since it just gets turned on again
203 * as we jump to our code at KERNELBASE. -- Cort
204 * Actually no, pmac doesn't have it on any more. BootX enters with MMU
205 * off, and in other cases, we now turn it off before changing BATs above.
209 ori r0,r0,MSR_DR|MSR_IR|MSR_RI
212 ori r0,r0,start_here@l
215 RFI /* enables MMU */
218 * We need __secondary_hold as a place to hold the other cpus on
219 * an SMP machine, even when we are running a UP kernel.
221 . = 0xc0 /* for prep bootloader */
222 li r3,1 /* MTX only has 1 cpu */
223 .globl __secondary_hold
225 /* tell the master we're here */
226 stw r3,__secondary_hold_acknowledge@l(0)
229 /* wait until we're told to start */
232 /* our cpu # was at addr 0 - go */
233 mr r24,r3 /* cpu # */
237 #endif /* CONFIG_SMP */
239 .globl __secondary_hold_spinloop
240 __secondary_hold_spinloop:
242 .globl __secondary_hold_acknowledge
243 __secondary_hold_acknowledge:
247 /* core99 pmac starts the seconary here by changing the vector, and
248 putting it back to what it was (unknown_exception) when done. */
249 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
253 * On CHRP, this is complicated by the fact that we could get a
254 * machine check inside RTAS, and we have no guarantee that certain
255 * critical registers will have the values we expect. The set of
256 * registers that might have bad values includes all the GPRs
257 * and all the BATs. We indicate that we are in RTAS by putting
258 * a non-zero value, the address of the exception frame to use,
259 * in thread.rtas_sp. The machine check handler checks thread.rtas_sp
260 * and uses its value if it is non-zero.
261 * (Other exception handlers assume that r1 is a valid kernel stack
262 * pointer when we take an exception from supervisor mode.)
267 mtspr SPRN_SPRG_SCRATCH0,r10
268 mtspr SPRN_SPRG_SCRATCH1,r11
270 #ifdef CONFIG_PPC_CHRP
271 mfspr r11, SPRN_SPRG_THREAD
272 lwz r11, RTAS_SP(r11)
275 #endif /* CONFIG_PPC_CHRP */
277 7: EXCEPTION_PROLOG_2
278 addi r3,r1,STACK_FRAME_OVERHEAD
279 #ifdef CONFIG_PPC_CHRP
282 EXC_XFER_STD(0x200, machine_check_exception)
283 #ifdef CONFIG_PPC_CHRP
284 1: b machine_check_in_rtas
287 /* Data access exception. */
294 #ifdef CONFIG_PPC_KUAP
295 andis. r0,r10,(DSISR_BAD_FAULT_32S | DSISR_DABRMATCH | DSISR_PROTFAULT)@h
297 andis. r0,r10,(DSISR_BAD_FAULT_32S|DSISR_DABRMATCH)@h
299 bne 1f /* if not, try to put a PTE */
300 mfspr r4,SPRN_DAR /* into the hash table */
301 rlwinm r3,r10,32-15,21,21 /* DSISR_STORE -> _PAGE_RW */
302 BEGIN_MMU_FTR_SECTION
304 END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
305 1: lwz r5,_DSISR(r11) /* get DSISR value */
307 EXC_XFER_LITE(0x300, handle_page_fault)
310 /* Instruction access exception. */
315 andis. r0,r9,SRR1_ISI_NOPT@h /* no pte found? */
316 beq 1f /* if so, try to put a PTE */
317 li r3,0 /* into the hash table */
318 mr r4,r12 /* SRR0 is fault address */
319 BEGIN_MMU_FTR_SECTION
321 END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
323 andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */
324 EXC_XFER_LITE(0x400, handle_page_fault)
326 /* External interrupt */
327 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
329 /* Alignment exception */
338 addi r3,r1,STACK_FRAME_OVERHEAD
339 EXC_XFER_STD(0x600, alignment_exception)
341 /* Program check exception */
342 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
344 /* Floating-point unavailable */
350 * Certain Freescale cores don't have a FPU and treat fp instructions
351 * as a FP Unavailable exception. Redirect to illegal/emulation handling.
354 END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
357 bl load_up_fpu /* if from user, just load it up */
358 b fast_exception_return
359 1: addi r3,r1,STACK_FRAME_OVERHEAD
360 EXC_XFER_LITE(0x800, kernel_fp_unavailable_exception)
363 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
365 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_STD)
366 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_STD)
374 /* Single step - not used on 601 */
375 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
376 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_STD)
379 * The Altivec unavailable trap is at 0x0f20. Foo.
380 * We effectively remap it to 0x3000.
381 * We include an altivec unavailable exception vector even if
382 * not configured for Altivec, so that you can't panic a
383 * non-altivec kernel running on a machine with altivec just
384 * by executing an altivec instruction.
395 * Handle TLB miss for instruction on 603/603e.
396 * Note: we get an alternate set of r0 - r3 to use automatically.
402 * r1: linux style pte ( later becomes ppc hardware pte )
403 * r2: ptr to linux-style pte
406 /* Get PTE (linux-style) and check access */
408 #if defined(CONFIG_MODULES) || defined(CONFIG_DEBUG_PAGEALLOC)
409 lis r1,PAGE_OFFSET@h /* check if kernel address */
412 mfspr r2, SPRN_SPRG_PGDIR
414 li r1,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
416 li r1,_PAGE_PRESENT | _PAGE_EXEC
418 #if defined(CONFIG_MODULES) || defined(CONFIG_DEBUG_PAGEALLOC)
420 lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
421 addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
423 112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
424 lwz r2,0(r2) /* get pmd entry */
425 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
426 beq- InstructionAddressInvalid /* return if no mapping */
427 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
428 lwz r0,0(r2) /* get linux-style pte */
429 andc. r1,r1,r0 /* check access & ~permission */
430 bne- InstructionAddressInvalid /* return if access not permitted */
431 /* Convert linux-style PTE to low word of PPC-style PTE */
432 rlwimi r0,r0,32-2,31,31 /* _PAGE_USER -> PP lsb */
433 ori r1, r1, 0xe06 /* clear out reserved bits */
434 andc r1, r0, r1 /* PP = user? 1 : 0 */
436 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
437 END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
440 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
443 InstructionAddressInvalid:
445 rlwinm r1,r3,9,6,6 /* Get load/store bit */
448 mtspr SPRN_DSISR,r1 /* (shouldn't be needed) */
449 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
452 mfspr r1,SPRN_IMISS /* Get failing address */
453 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
454 rlwimi r2,r2,1,30,30 /* change 1 -> 3 */
456 mtspr SPRN_DAR,r1 /* Set fault address */
457 mfmsr r0 /* Restore "normal" registers */
458 xoris r0,r0,MSR_TGPR>>16
459 mtcrf 0x80,r3 /* Restore CR0 */
464 * Handle TLB miss for DATA Load operation on 603/603e
470 * r1: linux style pte ( later becomes ppc hardware pte )
471 * r2: ptr to linux-style pte
474 /* Get PTE (linux-style) and check access */
476 lis r1,PAGE_OFFSET@h /* check if kernel address */
478 mfspr r2, SPRN_SPRG_PGDIR
480 li r1, _PAGE_PRESENT | _PAGE_ACCESSED
485 lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
486 addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
487 112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
488 lwz r2,0(r2) /* get pmd entry */
489 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
490 beq- DataAddressInvalid /* return if no mapping */
491 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
492 lwz r0,0(r2) /* get linux-style pte */
493 andc. r1,r1,r0 /* check access & ~permission */
494 bne- DataAddressInvalid /* return if access not permitted */
496 * NOTE! We are assuming this is not an SMP system, otherwise
497 * we would need to update the pte atomically with lwarx/stwcx.
499 /* Convert linux-style PTE to low word of PPC-style PTE */
500 rlwinm r1,r0,32-9,30,30 /* _PAGE_RW -> PP msb */
501 rlwimi r0,r0,32-1,30,30 /* _PAGE_USER -> PP msb */
502 rlwimi r0,r0,32-1,31,31 /* _PAGE_USER -> PP lsb */
503 ori r1,r1,0xe04 /* clear out reserved bits */
504 andc r1,r0,r1 /* PP = user? rw? 1: 3: 0 */
506 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
507 END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
509 mfspr r2,SPRN_SRR1 /* Need to restore CR0 */
511 BEGIN_MMU_FTR_SECTION
513 mfspr r1,SPRN_SPRG_603_LRU
514 rlwinm r2,r3,20,27,31 /* Get Address bits 15:19 */
518 mtspr SPRN_SPRG_603_LRU,r1
520 rlwimi r2,r0,31-14,14,14
522 END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
527 rlwinm r1,r3,9,6,6 /* Get load/store bit */
530 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
532 mfspr r1,SPRN_DMISS /* Get failing address */
533 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
534 beq 20f /* Jump if big endian */
536 20: mtspr SPRN_DAR,r1 /* Set fault address */
537 mfmsr r0 /* Restore "normal" registers */
538 xoris r0,r0,MSR_TGPR>>16
539 mtcrf 0x80,r3 /* Restore CR0 */
544 * Handle TLB miss for DATA Store on 603/603e
550 * r1: linux style pte ( later becomes ppc hardware pte )
551 * r2: ptr to linux-style pte
554 /* Get PTE (linux-style) and check access */
556 lis r1,PAGE_OFFSET@h /* check if kernel address */
558 mfspr r2, SPRN_SPRG_PGDIR
560 li r1, _PAGE_RW | _PAGE_PRESENT | _PAGE_ACCESSED
562 li r1, _PAGE_RW | _PAGE_PRESENT
565 lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
566 addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
567 112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
568 lwz r2,0(r2) /* get pmd entry */
569 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
570 beq- DataAddressInvalid /* return if no mapping */
571 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
572 lwz r0,0(r2) /* get linux-style pte */
573 andc. r1,r1,r0 /* check access & ~permission */
574 bne- DataAddressInvalid /* return if access not permitted */
576 * NOTE! We are assuming this is not an SMP system, otherwise
577 * we would need to update the pte atomically with lwarx/stwcx.
579 /* Convert linux-style PTE to low word of PPC-style PTE */
580 rlwimi r0,r0,32-2,31,31 /* _PAGE_USER -> PP lsb */
581 li r1,0xe06 /* clear out reserved bits & PP msb */
582 andc r1,r0,r1 /* PP = user? 1: 0 */
584 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
585 END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
587 mfspr r2,SPRN_SRR1 /* Need to restore CR0 */
589 BEGIN_MMU_FTR_SECTION
591 mfspr r1,SPRN_SPRG_603_LRU
592 rlwinm r2,r3,20,27,31 /* Get Address bits 15:19 */
596 mtspr SPRN_SPRG_603_LRU,r1
598 rlwimi r2,r0,31-14,14,14
600 END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
604 #ifndef CONFIG_ALTIVEC
605 #define altivec_assist_exception unknown_exception
608 EXCEPTION(0x1300, Trap_13, instruction_breakpoint_exception, EXC_XFER_STD)
609 EXCEPTION(0x1400, SMI, SMIException, EXC_XFER_STD)
610 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_STD)
611 EXCEPTION(0x1600, Trap_16, altivec_assist_exception, EXC_XFER_STD)
612 EXCEPTION(0x1700, Trap_17, TAUException, EXC_XFER_STD)
613 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_STD)
614 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_STD)
615 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_STD)
616 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_STD)
617 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_STD)
618 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_STD)
619 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_STD)
620 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_STD)
621 EXCEPTION(0x2000, RunMode, RunModeException, EXC_XFER_STD)
622 EXCEPTION(0x2100, Trap_21, unknown_exception, EXC_XFER_STD)
623 EXCEPTION(0x2200, Trap_22, unknown_exception, EXC_XFER_STD)
624 EXCEPTION(0x2300, Trap_23, unknown_exception, EXC_XFER_STD)
625 EXCEPTION(0x2400, Trap_24, unknown_exception, EXC_XFER_STD)
626 EXCEPTION(0x2500, Trap_25, unknown_exception, EXC_XFER_STD)
627 EXCEPTION(0x2600, Trap_26, unknown_exception, EXC_XFER_STD)
628 EXCEPTION(0x2700, Trap_27, unknown_exception, EXC_XFER_STD)
629 EXCEPTION(0x2800, Trap_28, unknown_exception, EXC_XFER_STD)
630 EXCEPTION(0x2900, Trap_29, unknown_exception, EXC_XFER_STD)
631 EXCEPTION(0x2a00, Trap_2a, unknown_exception, EXC_XFER_STD)
632 EXCEPTION(0x2b00, Trap_2b, unknown_exception, EXC_XFER_STD)
633 EXCEPTION(0x2c00, Trap_2c, unknown_exception, EXC_XFER_STD)
634 EXCEPTION(0x2d00, Trap_2d, unknown_exception, EXC_XFER_STD)
635 EXCEPTION(0x2e00, Trap_2e, unknown_exception, EXC_XFER_STD)
636 EXCEPTION(0x2f00, Trap_2f, unknown_exception, EXC_XFER_STD)
642 #ifdef CONFIG_ALTIVEC
644 bl load_up_altivec /* if from user, just load it up */
645 b fast_exception_return
646 #endif /* CONFIG_ALTIVEC */
647 1: addi r3,r1,STACK_FRAME_OVERHEAD
648 EXC_XFER_LITE(0xf20, altivec_unavailable_exception)
652 addi r3,r1,STACK_FRAME_OVERHEAD
653 EXC_XFER_STD(0xf00, performance_monitor_exception)
657 * This code is jumped to from the startup code to copy
658 * the kernel image to physical address PHYSICAL_START.
661 addis r9,r26,klimit@ha /* fetch klimit */
663 addis r25,r25,-KERNELBASE@h
664 lis r3,PHYSICAL_START@h /* Destination base address */
665 li r6,0 /* Destination offset */
666 li r5,0x4000 /* # bytes of memory to copy */
667 bl copy_and_flush /* copy the first 0x4000 bytes */
668 addi r0,r3,4f@l /* jump to the address of 4f */
669 mtctr r0 /* in copy and do the rest. */
670 bctr /* jump to the copy */
672 bl copy_and_flush /* copy the rest */
676 * Copy routine used to copy the kernel to start at physical address 0
677 * and flush and invalidate the caches as needed.
678 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
679 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
681 _ENTRY(copy_and_flush)
684 4: li r0,L1_CACHE_BYTES/4
686 3: addi r6,r6,4 /* copy a cache line */
690 dcbst r6,r3 /* write it to memory */
692 icbi r6,r3 /* flush the icache line */
695 sync /* additional sync needed on g4 */
702 .globl __secondary_start_mpc86xx
703 __secondary_start_mpc86xx:
705 stw r3, __secondary_hold_acknowledge@l(0)
706 mr r24, r3 /* cpu # */
709 .globl __secondary_start_pmac_0
710 __secondary_start_pmac_0:
711 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
720 /* on powersurge, we come in here with IR=0 and DR=1, and DBAT 0
721 set to map the 0xf0000000 - 0xffffffff region */
723 rlwinm r0,r0,0,28,26 /* clear DR (0x10) */
728 .globl __secondary_start
730 /* Copy some CPU settings from CPU 0 */
731 bl __restore_cpu_setup
735 bl call_setup_cpu /* Call setup_cpu for this CPU */
736 #ifdef CONFIG_PPC_BOOK3S_32
739 #endif /* CONFIG_PPC_BOOK3S_32 */
741 /* get current's stack and current */
742 lis r2,secondary_current@ha
744 lwz r2,secondary_current@l(r2)
746 lwz r1,TASK_STACK(r1)
749 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
754 /* load up the MMU */
755 bl load_segment_registers
758 /* ptr to phys current thread */
760 addi r4,r4,THREAD /* phys address of our thread_struct */
761 mtspr SPRN_SPRG_THREAD,r4
762 lis r4, (swapper_pg_dir - PAGE_OFFSET)@h
763 ori r4, r4, (swapper_pg_dir - PAGE_OFFSET)@l
764 mtspr SPRN_SPRG_PGDIR, r4
766 /* enable MMU and jump to start_secondary */
768 lis r3,start_secondary@h
769 ori r3,r3,start_secondary@l
774 #endif /* CONFIG_SMP */
776 #ifdef CONFIG_KVM_BOOK3S_HANDLER
777 #include "../kvm/book3s_rmhandlers.S"
781 * Those generic dummy functions are kept for CPUs not
782 * included in CONFIG_PPC_BOOK3S_32
784 #if !defined(CONFIG_PPC_BOOK3S_32)
785 _ENTRY(__save_cpu_setup)
787 _ENTRY(__restore_cpu_setup)
789 #endif /* !defined(CONFIG_PPC_BOOK3S_32) */
792 * Load stuff into the MMU. Intended to be called with
797 sync /* Force all PTE updates to finish */
799 tlbia /* Clear all TLB entries */
800 sync /* wait for tlbia/tlbie to finish */
801 TLBSYNC /* ... on all CPUs */
802 /* Load the SDR1 register (hash table base & size) */
803 lis r6, early_hash - PAGE_OFFSET@h
804 ori r6, r6, 3 /* 256kB table */
810 sync /* Force all PTE updates to finish */
812 tlbia /* Clear all TLB entries */
813 sync /* wait for tlbia/tlbie to finish */
814 TLBSYNC /* ... on all CPUs */
815 /* Load the SDR1 register (hash table base & size) */
821 /* Load the BAT registers with the values set up by MMU_init.
822 MMU_init takes care of whether we're on a 601 or not. */
833 BEGIN_MMU_FTR_SECTION
838 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
841 load_segment_registers:
842 li r0, NUM_USER_SEGMENTS /* load up user segment register values */
843 mtctr r0 /* for context 0 */
844 li r3, 0 /* Kp = 0, Ks = 0, VSID = 0 */
845 #ifdef CONFIG_PPC_KUEP
846 oris r3, r3, SR_NX@h /* Set Nx */
848 #ifdef CONFIG_PPC_KUAP
849 oris r3, r3, SR_KS@h /* Set Ks */
853 addi r3, r3, 0x111 /* increment VSID */
854 addis r4, r4, 0x1000 /* address of next segment */
856 li r0, 16 - NUM_USER_SEGMENTS /* load up kernel segment registers */
857 mtctr r0 /* for context 0 */
858 rlwinm r3, r3, 0, ~SR_NX /* Nx = 0 */
859 rlwinm r3, r3, 0, ~SR_KS /* Ks = 0 */
860 oris r3, r3, SR_KP@h /* Kp = 1 */
862 addi r3, r3, 0x111 /* increment VSID */
863 addis r4, r4, 0x1000 /* address of next segment */
868 * This is where the main kernel code starts.
873 ori r2,r2,init_task@l
874 /* Set up for using our exception vectors */
875 /* ptr to phys current thread */
877 addi r4,r4,THREAD /* init task's THREAD */
878 mtspr SPRN_SPRG_THREAD,r4
879 lis r4, (swapper_pg_dir - PAGE_OFFSET)@h
880 ori r4, r4, (swapper_pg_dir - PAGE_OFFSET)@l
881 mtspr SPRN_SPRG_PGDIR, r4
884 lis r1,init_thread_union@ha
885 addi r1,r1,init_thread_union@l
887 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
889 * Do early platform-specific initialization,
890 * and set up the MMU.
900 BEGIN_MMU_FTR_SECTION
902 END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
905 * Go back to running unmapped so we can load up new values
906 * for SDR1 (hash table pointer) and the segment registers
907 * and change to using our exception vectors.
912 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
917 /* Load up the kernel context */
920 #ifdef CONFIG_BDI_SWITCH
921 /* Add helper information for the Abatron bdiGDB debugger.
922 * We do this here because we know the mmu is disabled, and
923 * will be enabled for real in just a few instructions.
925 lis r5, abatron_pteptrs@h
926 ori r5, r5, abatron_pteptrs@l
927 stw r5, 0xf0(r0) /* This much match your Abatron config */
928 lis r6, swapper_pg_dir@h
929 ori r6, r6, swapper_pg_dir@l
932 #endif /* CONFIG_BDI_SWITCH */
934 /* Now turn on the MMU for real! */
936 lis r3,start_kernel@h
937 ori r3,r3,start_kernel@l
944 * void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next);
946 * Set up the segment registers for a new context.
948 _ENTRY(switch_mmu_context)
949 lwz r3,MMCONTEXTID(r4)
952 mulli r3,r3,897 /* multiply context by skew factor */
953 rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */
954 #ifdef CONFIG_PPC_KUEP
955 oris r3, r3, SR_NX@h /* Set Nx */
957 #ifdef CONFIG_PPC_KUAP
958 oris r3, r3, SR_KS@h /* Set Ks */
960 li r0,NUM_USER_SEGMENTS
964 #ifdef CONFIG_BDI_SWITCH
965 /* Context switch the PTE pointer for the Abatron BDI2000.
966 * The PGDIR is passed as second argument.
968 lis r5, abatron_pteptrs@ha
969 stw r4, abatron_pteptrs@l + 0x4(r5)
972 mtspr SPRN_SPRG_PGDIR, r4
977 addi r3,r3,0x111 /* next VSID */
978 rlwinm r3,r3,0,8,3 /* clear out any overflow from VSID field */
979 addis r4,r4,0x1000 /* address of next segment */
985 EMIT_BUG_ENTRY 4b,__FILE__,__LINE__,0
987 EXPORT_SYMBOL(switch_mmu_context)
990 * An undocumented "feature" of 604e requires that the v bit
991 * be cleared before changing BAT values.
993 * Also, newer IBM firmware does not clear bat3 and 4 so
994 * this makes sure it's done.
1000 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1004 mtspr SPRN_DBAT0U,r10
1005 mtspr SPRN_DBAT0L,r10
1006 mtspr SPRN_DBAT1U,r10
1007 mtspr SPRN_DBAT1L,r10
1008 mtspr SPRN_DBAT2U,r10
1009 mtspr SPRN_DBAT2L,r10
1010 mtspr SPRN_DBAT3U,r10
1011 mtspr SPRN_DBAT3L,r10
1013 mtspr SPRN_IBAT0U,r10
1014 mtspr SPRN_IBAT0L,r10
1015 mtspr SPRN_IBAT1U,r10
1016 mtspr SPRN_IBAT1L,r10
1017 mtspr SPRN_IBAT2U,r10
1018 mtspr SPRN_IBAT2L,r10
1019 mtspr SPRN_IBAT3U,r10
1020 mtspr SPRN_IBAT3L,r10
1021 BEGIN_MMU_FTR_SECTION
1022 /* Here's a tweak: at this point, CPU setup have
1023 * not been called yet, so HIGH_BAT_EN may not be
1024 * set in HID0 for the 745x processors. However, it
1025 * seems that doesn't affect our ability to actually
1026 * write to these SPRs.
1028 mtspr SPRN_DBAT4U,r10
1029 mtspr SPRN_DBAT4L,r10
1030 mtspr SPRN_DBAT5U,r10
1031 mtspr SPRN_DBAT5L,r10
1032 mtspr SPRN_DBAT6U,r10
1033 mtspr SPRN_DBAT6L,r10
1034 mtspr SPRN_DBAT7U,r10
1035 mtspr SPRN_DBAT7L,r10
1036 mtspr SPRN_IBAT4U,r10
1037 mtspr SPRN_IBAT4L,r10
1038 mtspr SPRN_IBAT5U,r10
1039 mtspr SPRN_IBAT5L,r10
1040 mtspr SPRN_IBAT6U,r10
1041 mtspr SPRN_IBAT6L,r10
1042 mtspr SPRN_IBAT7U,r10
1043 mtspr SPRN_IBAT7L,r10
1044 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
1053 li r3, MSR_KERNEL & ~(MSR_IR | MSR_DR)
1054 rlwinm r0, r6, 0, ~MSR_RI
1055 rlwinm r0, r0, 0, ~MSR_EE
1065 LOAD_BAT(0, r3, r4, r5)
1066 LOAD_BAT(1, r3, r4, r5)
1067 LOAD_BAT(2, r3, r4, r5)
1068 LOAD_BAT(3, r3, r4, r5)
1069 BEGIN_MMU_FTR_SECTION
1070 LOAD_BAT(4, r3, r4, r5)
1071 LOAD_BAT(5, r3, r4, r5)
1072 LOAD_BAT(6, r3, r4, r5)
1073 LOAD_BAT(7, r3, r4, r5)
1074 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
1075 li r3, MSR_KERNEL & ~(MSR_IR | MSR_DR | MSR_RI)
1084 1: addic. r10, r10, -0x1000
1091 addi r4, r3, __after_mmu_off - _start
1093 andi. r0,r3,MSR_DR|MSR_IR /* MMU enabled? */
1102 * On 601, we use 3 BATs to map up to 24M of RAM at _PAGE_OFFSET
1103 * (we keep one for debugging) and on others, we use one 256M BAT.
1106 lis r11,PAGE_OFFSET@h
1108 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1111 ori r11,r11,4 /* set up BAT registers for 601 */
1112 li r8,0x7f /* valid, block length = 8MB */
1113 mtspr SPRN_IBAT0U,r11 /* N.B. 601 has valid bit in */
1114 mtspr SPRN_IBAT0L,r8 /* lower BAT register */
1115 addis r11,r11,0x800000@h
1116 addis r8,r8,0x800000@h
1117 mtspr SPRN_IBAT1U,r11
1118 mtspr SPRN_IBAT1L,r8
1119 addis r11,r11,0x800000@h
1120 addis r8,r8,0x800000@h
1121 mtspr SPRN_IBAT2U,r11
1122 mtspr SPRN_IBAT2L,r8
1128 ori r8,r8,0x12 /* R/W access, M=1 */
1130 ori r8,r8,2 /* R/W access */
1131 #endif /* CONFIG_SMP */
1132 ori r11,r11,BL_256M<<2|0x2 /* set up BAT registers for 604 */
1134 mtspr SPRN_DBAT0L,r8 /* N.B. 6xx (not 601) have valid */
1135 mtspr SPRN_DBAT0U,r11 /* bit in upper BAT register */
1136 mtspr SPRN_IBAT0L,r8
1137 mtspr SPRN_IBAT0U,r11
1142 #ifdef CONFIG_BOOTX_TEXT
1145 * setup the display bat prepared for us in prom.c
1150 addis r8,r3,disp_BAT@ha
1151 addi r8,r8,disp_BAT@l
1157 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1160 mtspr SPRN_DBAT3L,r8
1161 mtspr SPRN_DBAT3U,r11
1163 1: mtspr SPRN_IBAT3L,r8
1164 mtspr SPRN_IBAT3U,r11
1166 #endif /* CONFIG_BOOTX_TEXT */
1168 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
1172 mtspr SPRN_DBAT1L, r8
1175 ori r11, r11, (BL_1M << 2) | 2
1176 mtspr SPRN_DBAT1U, r11
1181 #ifdef CONFIG_PPC_EARLY_DEBUG_USBGECKO
1183 /* prepare a BAT for early io */
1184 #if defined(CONFIG_GAMECUBE)
1186 #elif defined(CONFIG_WII)
1189 #error Invalid platform for USB Gecko based early debugging.
1192 * The virtual address used must match the virtual address
1193 * associated to the fixmap entry FIX_EARLY_DEBUG_BASE.
1195 lis r11, 0xfffe /* top 128K */
1196 ori r8, r8, 0x002a /* uncached, guarded ,rw */
1197 ori r11, r11, 0x2 /* 128K, Vs=1, Vp=0 */
1198 mtspr SPRN_DBAT1L, r8
1199 mtspr SPRN_DBAT1U, r11
1204 /* Jump into the system reset for the rom.
1205 * We first disable the MMU, and then jump to the ROM reset address.
1207 * r3 is the board info structure, r4 is the location for starting.
1208 * I use this for building a small kernel that can load other kernels,
1209 * rather than trying to write or rely on a rom monitor that can tftp load.
1214 rlwinm r0,r0,0,17,15 /* clear MSR_EE in r0 */
1218 mfspr r11, SPRN_HID0
1220 ori r10,r10,HID0_ICE|HID0_DCE
1222 mtspr SPRN_HID0, r11
1224 li r5, MSR_ME|MSR_RI
1226 addis r6,r6,-KERNELBASE@h
1240 * We put a few things here that have to be page-aligned.
1241 * This stuff goes at the beginning of the data segment,
1242 * which is page-aligned.
1247 .globl empty_zero_page
1250 EXPORT_SYMBOL(empty_zero_page)
1252 .globl swapper_pg_dir
1254 .space PGD_TABLE_SIZE
1256 /* Room for two PTE pointers, usually the kernel and current user pointers
1257 * to their respective root page table.