drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef F32_MES_PM4_PACKETS_H
  25 #define F32_MES_PM4_PACKETS_H
  26
  27 #ifndef PM4_MES_HEADER_DEFINED
  28 #define PM4_MES_HEADER_DEFINED
  29 union PM4_MES_TYPE_3_HEADER {
  30         struct {
  31                 uint32_t reserved1 : 8; /* < reserved */
  32                 uint32_t opcode    : 8; /* < IT opcode */
  33                 uint32_t count     : 14;/* < number of DWORDs - 1 in the
  34                                          *   information body.
  35                                          */
  36                 uint32_t type      : 2; /* < packet identifier.
  37                                          *   It should be 3 for type 3 packets
  38                                          */
  39         };
  40         uint32_t u32All;
  41 };
  42 #endif /* PM4_MES_HEADER_DEFINED */
  43
  44 /*--------------------MES_SET_RESOURCES--------------------*/
  45
  46 #ifndef PM4_MES_SET_RESOURCES_DEFINED
  47 #define PM4_MES_SET_RESOURCES_DEFINED
  48 enum mes_set_resources_queue_type_enum {
  49         queue_type__mes_set_resources__kernel_interface_queue_kiq = 0,
  50         queue_type__mes_set_resources__hsa_interface_queue_hiq = 1,
  51         queue_type__mes_set_resources__hsa_debug_interface_queue = 4
  52 };
  53
  54
  55 struct pm4_mes_set_resources {
  56         union {
  57                 union PM4_MES_TYPE_3_HEADER     header;         /* header */
  58                 uint32_t                        ordinal1;
  59         };
  60
  61         union {
  62                 struct {
  63                         uint32_t vmid_mask:16;
  64                         uint32_t unmap_latency:8;
  65                         uint32_t reserved1:5;
  66                         enum mes_set_resources_queue_type_enum queue_type:3;
  67                 } bitfields2;
  68                 uint32_t ordinal2;
  69         };
  70
  71         uint32_t queue_mask_lo;
  72         uint32_t queue_mask_hi;
  73         uint32_t gws_mask_lo;
  74         uint32_t gws_mask_hi;
  75
  76         union {
  77                 struct {
  78                         uint32_t oac_mask:16;
  79                         uint32_t reserved2:16;
  80                 } bitfields7;
  81                 uint32_t ordinal7;
  82         };
  83
  84         union {
  85                 struct {
  86                 uint32_t gds_heap_base:10;
  87                 uint32_t reserved3:1;
  88                 uint32_t gds_heap_size:10;
  89                 uint32_t reserved4:11;
  90                 } bitfields8;
  91                 uint32_t ordinal8;
  92         };
  93
  94 };
  95 #endif
  96
  97 /*--------------------MES_RUN_LIST--------------------*/
  98
  99 #ifndef PM4_MES_RUN_LIST_DEFINED
 100 #define PM4_MES_RUN_LIST_DEFINED
 101
 102 struct pm4_mes_runlist {
 103         union {
 104                 union PM4_MES_TYPE_3_HEADER header; /* header */
 105                 uint32_t ordinal1;
 106         };
 107
 108         union {
 109                 struct {
 110                         uint32_t reserved1:2;
 111                         uint32_t ib_base_lo:30;
 112                 } bitfields2;
 113                 uint32_t ordinal2;
 114         };
 115
 116         uint32_t ib_base_hi;
 117
 118         union {
 119                 struct {
 120                         uint32_t ib_size:20;
 121                         uint32_t chain:1;
 122                         uint32_t offload_polling:1;
 123                         uint32_t chained_runlist_idle_disable:1;
 124                         uint32_t valid:1;
 125                         uint32_t process_cnt:4;
 126                         uint32_t reserved3:4;
 127                 } bitfields4;
 128                 uint32_t ordinal4;
 129         };
 130
 131 };
 132 #endif
 133
 134 /*--------------------MES_MAP_PROCESS--------------------*/
 135
 136 #ifndef PM4_MES_MAP_PROCESS_DEFINED
 137 #define PM4_MES_MAP_PROCESS_DEFINED
 138
 139 struct pm4_mes_map_process {
 140         union {
 141                 union PM4_MES_TYPE_3_HEADER header;     /* header */
 142                 uint32_t ordinal1;
 143         };
 144
 145         union {
 146                 struct {
 147                         uint32_t pasid:16;
 148                         uint32_t reserved1:8;
 149                         uint32_t diq_enable:1;
 150                         uint32_t process_quantum:7;
 151                 } bitfields2;
 152                 uint32_t ordinal2;
 153         };
 154
 155         uint32_t vm_context_page_table_base_addr_lo32;
 156
 157         uint32_t vm_context_page_table_base_addr_hi32;
 158
 159         uint32_t sh_mem_bases;
 160
 161         uint32_t sh_mem_config;
 162
 163         uint32_t sq_shader_tba_lo;
 164
 165         uint32_t sq_shader_tba_hi;
 166
 167         uint32_t sq_shader_tma_lo;
 168
 169         uint32_t sq_shader_tma_hi;
 170
 171         uint32_t reserved6;
 172
 173         uint32_t gds_addr_lo;
 174
 175         uint32_t gds_addr_hi;
 176
 177         union {
 178                 struct {
 179                         uint32_t num_gws:7;
 180                         uint32_t sdma_enable:1;
 181                         uint32_t num_oac:4;
 182                         uint32_t gds_size_hi:4;
 183                         uint32_t gds_size:6;
 184                         uint32_t num_queues:10;
 185                 } bitfields14;
 186                 uint32_t ordinal14;
 187         };
 188
 189         uint32_t completion_signal_lo;
 190
 191         uint32_t completion_signal_hi;
 192
 193 };
 194
 195 #endif
 196
 197 /*--------------------MES_MAP_PROCESS_VM--------------------*/
 198
 199 #ifndef PM4_MES_MAP_PROCESS_VM_DEFINED
 200 #define PM4_MES_MAP_PROCESS_VM_DEFINED
 201
 202 struct PM4_MES_MAP_PROCESS_VM {
 203         union {
 204                 union PM4_MES_TYPE_3_HEADER header;     /* header */
 205                 uint32_t ordinal1;
 206         };
 207
 208         uint32_t reserved1;
 209
 210         uint32_t vm_context_cntl;
 211
 212         uint32_t reserved2;
 213
 214         uint32_t vm_context_page_table_end_addr_lo32;
 215
 216         uint32_t vm_context_page_table_end_addr_hi32;
 217
 218         uint32_t vm_context_page_table_start_addr_lo32;
 219
 220         uint32_t vm_context_page_table_start_addr_hi32;
 221
 222         uint32_t reserved3;
 223
 224         uint32_t reserved4;
 225
 226         uint32_t reserved5;
 227
 228         uint32_t reserved6;
 229
 230         uint32_t reserved7;
 231
 232         uint32_t reserved8;
 233
 234         uint32_t completion_signal_lo32;
 235
 236         uint32_t completion_signal_hi32;
 237
 238 };
 239 #endif
 240
 241 /*--------------------MES_MAP_QUEUES--------------------*/
 242
 243 #ifndef PM4_MES_MAP_QUEUES_VI_DEFINED
 244 #define PM4_MES_MAP_QUEUES_VI_DEFINED
 245 enum mes_map_queues_queue_sel_enum {
 246         queue_sel__mes_map_queues__map_to_specified_queue_slots_vi = 0,
 247 queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi = 1
 248 };
 249
 250 enum mes_map_queues_queue_type_enum {
 251         queue_type__mes_map_queues__normal_compute_vi = 0,
 252         queue_type__mes_map_queues__debug_interface_queue_vi = 1,
 253         queue_type__mes_map_queues__normal_latency_static_queue_vi = 2,
 254 queue_type__mes_map_queues__low_latency_static_queue_vi = 3
 255 };
 256
 257 enum mes_map_queues_engine_sel_enum {
 258         engine_sel__mes_map_queues__compute_vi = 0,
 259         engine_sel__mes_map_queues__sdma0_vi = 2,
 260         engine_sel__mes_map_queues__sdma1_vi = 3
 261 };
 262
 263 enum mes_map_queues_extended_engine_sel_enum {
 264         extended_engine_sel__mes_map_queues__legacy_engine_sel = 0,
 265         extended_engine_sel__mes_map_queues__sdma0_to_7_sel = 1
 266 };
 267
 268 struct pm4_mes_map_queues {
 269         union {
 270                 union PM4_MES_TYPE_3_HEADER   header;            /* header */
 271                 uint32_t            ordinal1;
 272         };
 273
 274         union {
 275                 struct {
 276                         uint32_t reserved1:2;
 277                         enum mes_map_queues_extended_engine_sel_enum extended_engine_sel:2;
 278                         enum mes_map_queues_queue_sel_enum queue_sel:2;
 279                         uint32_t reserved5:6;
 280                         uint32_t gws_control_queue:1;
 281                         uint32_t reserved2:8;
 282                         enum mes_map_queues_queue_type_enum queue_type:3;
 283                         uint32_t reserved3:2;
 284                         enum mes_map_queues_engine_sel_enum engine_sel:3;
 285                         uint32_t num_queues:3;
 286                 } bitfields2;
 287                 uint32_t ordinal2;
 288         };
 289
 290         union {
 291                 struct {
 292                         uint32_t reserved3:1;
 293                         uint32_t check_disable:1;
 294                         uint32_t doorbell_offset:26;
 295                         uint32_t reserved4:4;
 296                 } bitfields3;
 297                 uint32_t ordinal3;
 298         };
 299
 300         uint32_t mqd_addr_lo;
 301         uint32_t mqd_addr_hi;
 302         uint32_t wptr_addr_lo;
 303         uint32_t wptr_addr_hi;
 304 };
 305 #endif
 306
 307 /*--------------------MES_QUERY_STATUS--------------------*/
 308
 309 #ifndef PM4_MES_QUERY_STATUS_DEFINED
 310 #define PM4_MES_QUERY_STATUS_DEFINED
 311 enum mes_query_status_interrupt_sel_enum {
 312         interrupt_sel__mes_query_status__completion_status = 0,
 313         interrupt_sel__mes_query_status__process_status = 1,
 314         interrupt_sel__mes_query_status__queue_status = 2
 315 };
 316
 317 enum mes_query_status_command_enum {
 318         command__mes_query_status__interrupt_only = 0,
 319         command__mes_query_status__fence_only_immediate = 1,
 320         command__mes_query_status__fence_only_after_write_ack = 2,
 321         command__mes_query_status__fence_wait_for_write_ack_send_interrupt = 3
 322 };
 323
 324 enum mes_query_status_engine_sel_enum {
 325         engine_sel__mes_query_status__compute = 0,
 326         engine_sel__mes_query_status__sdma0_queue = 2,
 327         engine_sel__mes_query_status__sdma1_queue = 3
 328 };
 329
 330 struct pm4_mes_query_status {
 331         union {
 332                 union PM4_MES_TYPE_3_HEADER   header;            /* header */
 333                 uint32_t            ordinal1;
 334         };
 335
 336         union {
 337                 struct {
 338                         uint32_t context_id:28;
 339                         enum mes_query_status_interrupt_sel_enum        interrupt_sel:2;
 340                         enum mes_query_status_command_enum command:2;
 341                 } bitfields2;
 342                 uint32_t ordinal2;
 343         };
 344
 345         union {
 346                 struct {
 347                         uint32_t pasid:16;
 348                         uint32_t reserved1:16;
 349                 } bitfields3a;
 350                 struct {
 351                         uint32_t reserved2:2;
 352                         uint32_t doorbell_offset:26;
 353                         enum mes_query_status_engine_sel_enum engine_sel:3;
 354                         uint32_t reserved3:1;
 355                 } bitfields3b;
 356                 uint32_t ordinal3;
 357         };
 358
 359         uint32_t addr_lo;
 360         uint32_t addr_hi;
 361         uint32_t data_lo;
 362         uint32_t data_hi;
 363 };
 364 #endif
 365
 366 /*--------------------MES_UNMAP_QUEUES--------------------*/
 367
 368 #ifndef PM4_MES_UNMAP_QUEUES_DEFINED
 369 #define PM4_MES_UNMAP_QUEUES_DEFINED
 370 enum mes_unmap_queues_action_enum {
 371         action__mes_unmap_queues__preempt_queues = 0,
 372         action__mes_unmap_queues__reset_queues = 1,
 373         action__mes_unmap_queues__disable_process_queues = 2,
 374         action__mes_unmap_queues__reserved = 3
 375 };
 376
 377 enum mes_unmap_queues_queue_sel_enum {
 378         queue_sel__mes_unmap_queues__perform_request_on_specified_queues = 0,
 379         queue_sel__mes_unmap_queues__perform_request_on_pasid_queues = 1,
 380         queue_sel__mes_unmap_queues__unmap_all_queues = 2,
 381         queue_sel__mes_unmap_queues__unmap_all_non_static_queues = 3
 382 };
 383
 384 enum mes_unmap_queues_engine_sel_enum {
 385         engine_sel__mes_unmap_queues__compute = 0,
 386         engine_sel__mes_unmap_queues__sdma0 = 2,
 387         engine_sel__mes_unmap_queues__sdmal = 3
 388 };
 389
 390 enum mes_unmap_queues_extended_engine_sel_enum {
 391         extended_engine_sel__mes_unmap_queues__legacy_engine_sel = 0,
 392         extended_engine_sel__mes_unmap_queues__sdma0_to_7_sel = 1
 393 };
 394
 395 struct pm4_mes_unmap_queues {
 396         union {
 397                 union PM4_MES_TYPE_3_HEADER   header;            /* header */
 398                 uint32_t            ordinal1;
 399         };
 400
 401         union {
 402                 struct {
 403                         enum mes_unmap_queues_action_enum action:2;
 404                         enum mes_unmap_queues_extended_engine_sel_enum extended_engine_sel:2;
 405                         enum mes_unmap_queues_queue_sel_enum queue_sel:2;
 406                         uint32_t reserved2:20;
 407                         enum mes_unmap_queues_engine_sel_enum engine_sel:3;
 408                         uint32_t num_queues:3;
 409                 } bitfields2;
 410                 uint32_t ordinal2;
 411         };
 412
 413         union {
 414                 struct {
 415                         uint32_t pasid:16;
 416                         uint32_t reserved3:16;
 417                 } bitfields3a;
 418                 struct {
 419                         uint32_t reserved4:2;
 420                         uint32_t doorbell_offset0:26;
 421                         int32_t reserved5:4;
 422                 } bitfields3b;
 423                 uint32_t ordinal3;
 424         };
 425
 426         union {
 427         struct {
 428                         uint32_t reserved6:2;
 429                         uint32_t doorbell_offset1:26;
 430                         uint32_t reserved7:4;
 431                 } bitfields4;
 432                 uint32_t ordinal4;
 433         };
 434
 435         union {
 436                 struct {
 437                         uint32_t reserved8:2;
 438                         uint32_t doorbell_offset2:26;
 439                         uint32_t reserved9:4;
 440                 } bitfields5;
 441                 uint32_t ordinal5;
 442         };
 443
 444         union {
 445                 struct {
 446                         uint32_t reserved10:2;
 447                         uint32_t doorbell_offset3:26;
 448                         uint32_t reserved11:4;
 449                 } bitfields6;
 450                 uint32_t ordinal6;
 451         };
 452 };
 453 #endif
 454
 455 #ifndef PM4_MEC_RELEASE_MEM_DEFINED
 456 #define PM4_MEC_RELEASE_MEM_DEFINED
 457
 458 enum mec_release_mem_event_index_enum {
 459         event_index__mec_release_mem__end_of_pipe = 5,
 460         event_index__mec_release_mem__shader_done = 6
 461 };
 462
 463 enum mec_release_mem_cache_policy_enum {
 464         cache_policy__mec_release_mem__lru = 0,
 465         cache_policy__mec_release_mem__stream = 1
 466 };
 467
 468 enum mec_release_mem_pq_exe_status_enum {
 469         pq_exe_status__mec_release_mem__default = 0,
 470         pq_exe_status__mec_release_mem__phase_update = 1
 471 };
 472
 473 enum mec_release_mem_dst_sel_enum {
 474         dst_sel__mec_release_mem__memory_controller = 0,
 475         dst_sel__mec_release_mem__tc_l2 = 1,
 476         dst_sel__mec_release_mem__queue_write_pointer_register = 2,
 477         dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit = 3
 478 };
 479
 480 enum mec_release_mem_int_sel_enum {
 481         int_sel__mec_release_mem__none = 0,
 482         int_sel__mec_release_mem__send_interrupt_only = 1,
 483         int_sel__mec_release_mem__send_interrupt_after_write_confirm = 2,
 484         int_sel__mec_release_mem__send_data_after_write_confirm = 3,
 485         int_sel__mec_release_mem__unconditionally_send_int_ctxid = 4,
 486         int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare = 5,
 487         int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare = 6
 488 };
 489
 490 enum mec_release_mem_data_sel_enum {
 491         data_sel__mec_release_mem__none = 0,
 492         data_sel__mec_release_mem__send_32_bit_low = 1,
 493         data_sel__mec_release_mem__send_64_bit_data = 2,
 494         data_sel__mec_release_mem__send_gpu_clock_counter = 3,
 495         data_sel__mec_release_mem__send_cp_perfcounter_hi_lo = 4,
 496         data_sel__mec_release_mem__store_gds_data_to_memory = 5
 497 };
 498
 499 struct pm4_mec_release_mem {
 500         union {
 501                 union PM4_MES_TYPE_3_HEADER header;     /*header */
 502                 unsigned int ordinal1;
 503         };
 504
 505         union {
 506                 struct {
 507                         unsigned int event_type:6;
 508                         unsigned int reserved1:2;
 509                         enum mec_release_mem_event_index_enum event_index:4;
 510                         unsigned int tcl1_vol_action_ena:1;
 511                         unsigned int tc_vol_action_ena:1;
 512                         unsigned int reserved2:1;
 513                         unsigned int tc_wb_action_ena:1;
 514                         unsigned int tcl1_action_ena:1;
 515                         unsigned int tc_action_ena:1;
 516                         uint32_t reserved3:1;
 517                         uint32_t tc_nc_action_ena:1;
 518                         uint32_t tc_wc_action_ena:1;
 519                         uint32_t tc_md_action_ena:1;
 520                         uint32_t reserved4:3;
 521                         enum mec_release_mem_cache_policy_enum cache_policy:2;
 522                         uint32_t reserved5:2;
 523                         enum mec_release_mem_pq_exe_status_enum pq_exe_status:1;
 524                         uint32_t reserved6:2;
 525                 } bitfields2;
 526                 unsigned int ordinal2;
 527         };
 528
 529         union {
 530                 struct {
 531                         uint32_t reserved7:16;
 532                         enum mec_release_mem_dst_sel_enum dst_sel:2;
 533                         uint32_t reserved8:6;
 534                         enum mec_release_mem_int_sel_enum int_sel:3;
 535                         uint32_t reserved9:2;
 536                         enum mec_release_mem_data_sel_enum data_sel:3;
 537                 } bitfields3;
 538                 unsigned int ordinal3;
 539         };
 540
 541         union {
 542                 struct {
 543                         uint32_t reserved10:2;
 544                         unsigned int address_lo_32b:30;
 545                 } bitfields4;
 546                 struct {
 547                         uint32_t reserved11:3;
 548                         uint32_t address_lo_64b:29;
 549                 } bitfields4b;
 550                 uint32_t reserved12;
 551                 unsigned int ordinal4;
 552         };
 553
 554         union {
 555                 uint32_t address_hi;
 556                 uint32_t reserved13;
 557                 uint32_t ordinal5;
 558         };
 559
 560         union {
 561                 uint32_t data_lo;
 562                 uint32_t cmp_data_lo;
 563                 struct {
 564                         uint32_t dw_offset:16;
 565                         uint32_t num_dwords:16;
 566                 } bitfields6c;
 567                 uint32_t reserved14;
 568                 uint32_t ordinal6;
 569         };
 570
 571         union {
 572                 uint32_t data_hi;
 573                 uint32_t cmp_data_hi;
 574                 uint32_t reserved15;
 575                 uint32_t reserved16;
 576                 uint32_t ordinal7;
 577         };
 578
 579         uint32_t int_ctxid;
 580
 581 };
 582
 583 #endif
 584
 585 enum {
 586         CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014
 587 };
 588 #endif
 589